1
2 #ifndef __ASM_ARCH_REGS_AC97_H
3 #define __ASM_ARCH_REGS_AC97_H
4
5 #include <mach/hardware.h>
6
7
8
9
10
11 #define POCR __REG(0x40500000)
12 #define POCR_FEIE (1 << 3)
13 #define POCR_FSRIE (1 << 1)
14
15 #define PICR __REG(0x40500004)
16 #define PICR_FEIE (1 << 3)
17 #define PICR_FSRIE (1 << 1)
18
19 #define MCCR __REG(0x40500008)
20 #define MCCR_FEIE (1 << 3)
21 #define MCCR_FSRIE (1 << 1)
22
23 #define GCR __REG(0x4050000C)
24 #ifdef CONFIG_PXA3xx
25 #define GCR_CLKBPB (1 << 31)
26 #endif
27 #define GCR_nDMAEN (1 << 24)
28 #define GCR_CDONE_IE (1 << 19)
29 #define GCR_SDONE_IE (1 << 18)
30 #define GCR_SECRDY_IEN (1 << 9)
31 #define GCR_PRIRDY_IEN (1 << 8)
32 #define GCR_SECRES_IEN (1 << 5)
33 #define GCR_PRIRES_IEN (1 << 4)
34 #define GCR_ACLINK_OFF (1 << 3)
35 #define GCR_WARM_RST (1 << 2)
36 #define GCR_COLD_RST (1 << 1)
37 #define GCR_GIE (1 << 0)
38
39 #define POSR __REG(0x40500010)
40 #define POSR_FIFOE (1 << 4)
41 #define POSR_FSR (1 << 2)
42
43 #define PISR __REG(0x40500014)
44 #define PISR_FIFOE (1 << 4)
45 #define PISR_EOC (1 << 3)
46 #define PISR_FSR (1 << 2)
47
48 #define MCSR __REG(0x40500018)
49 #define MCSR_FIFOE (1 << 4)
50 #define MCSR_EOC (1 << 3)
51 #define MCSR_FSR (1 << 2)
52
53 #define GSR __REG(0x4050001C)
54 #define GSR_CDONE (1 << 19)
55 #define GSR_SDONE (1 << 18)
56 #define GSR_RDCS (1 << 15)
57 #define GSR_BIT3SLT12 (1 << 14)
58 #define GSR_BIT2SLT12 (1 << 13)
59 #define GSR_BIT1SLT12 (1 << 12)
60 #define GSR_SECRES (1 << 11)
61 #define GSR_PRIRES (1 << 10)
62 #define GSR_SCR (1 << 9)
63 #define GSR_PCR (1 << 8)
64 #define GSR_MCINT (1 << 7)
65 #define GSR_POINT (1 << 6)
66 #define GSR_PIINT (1 << 5)
67 #define GSR_ACOFFD (1 << 3)
68 #define GSR_MOINT (1 << 2)
69 #define GSR_MIINT (1 << 1)
70 #define GSR_GSCI (1 << 0)
71
72 #define CAR __REG(0x40500020)
73 #define CAR_CAIP (1 << 0)
74
75 #define PCDR __REG(0x40500040)
76 #define MCDR __REG(0x40500060)
77
78 #define MOCR __REG(0x40500100)
79 #define MOCR_FEIE (1 << 3)
80 #define MOCR_FSRIE (1 << 1)
81
82 #define MICR __REG(0x40500108)
83 #define MICR_FEIE (1 << 3)
84 #define MICR_FSRIE (1 << 1)
85
86 #define MOSR __REG(0x40500110)
87 #define MOSR_FIFOE (1 << 4)
88 #define MOSR_FSR (1 << 2)
89
90 #define MISR __REG(0x40500118)
91 #define MISR_FIFOE (1 << 4)
92 #define MISR_EOC (1 << 3)
93 #define MISR_FSR (1 << 2)
94
95 #define MODR __REG(0x40500140)
96
97 #define PAC_REG_BASE __REG(0x40500200)
98 #define SAC_REG_BASE __REG(0x40500300)
99 #define PMC_REG_BASE __REG(0x40500400)
100 #define SMC_REG_BASE __REG(0x40500500)
101
102 #endif