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10 #ifndef ASM_ARCH_MAINSTONE_H
11 #define ASM_ARCH_MAINSTONE_H
12
13 #include <mach/irqs.h>
14
15 #define MST_ETH_PHYS PXA_CS4_PHYS
16
17 #define MST_FPGA_PHYS PXA_CS2_PHYS
18 #define MST_FPGA_VIRT (0xf0000000)
19 #define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
20 #define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
21
22 #ifndef __ASSEMBLY__
23 # define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x)))
24 #else
25 # define __MST_REG(x) MST_P2V(x)
26 #endif
27
28
29
30 #define MST_LEDDAT1 __MST_REG(0x08000010)
31 #define MST_LEDDAT2 __MST_REG(0x08000014)
32 #define MST_LEDCTRL __MST_REG(0x08000040)
33 #define MST_GPSWR __MST_REG(0x08000060)
34 #define MST_MSCWR1 __MST_REG(0x08000080)
35 #define MST_MSCWR2 __MST_REG(0x08000084)
36 #define MST_MSCWR3 __MST_REG(0x08000088)
37 #define MST_MSCRD __MST_REG(0x08000090)
38 #define MST_INTMSKENA __MST_REG(0x080000c0)
39 #define MST_INTSETCLR __MST_REG(0x080000d0)
40 #define MST_PCMCIA0 __MST_REG(0x080000e0)
41 #define MST_PCMCIA1 __MST_REG(0x080000e4)
42
43 #define MST_MSCWR1_CAMERA_ON (1 << 15)
44 #define MST_MSCWR1_CAMERA_SEL (1 << 14)
45 #define MST_MSCWR1_LCD_CTL (1 << 13)
46 #define MST_MSCWR1_MS_ON (1 << 12)
47 #define MST_MSCWR1_MMC_ON (1 << 11)
48 #define MST_MSCWR1_MS_SEL (1 << 10)
49 #define MST_MSCWR1_BB_SEL (1 << 9)
50 #define MST_MSCWR1_BT_ON (1 << 8)
51 #define MST_MSCWR1_BTDTR (1 << 7)
52
53 #define MST_MSCWR1_IRDA_MASK (3 << 5)
54 #define MST_MSCWR1_IRDA_FULL (0 << 5)
55 #define MST_MSCWR1_IRDA_OFF (1 << 5)
56 #define MST_MSCWR1_IRDA_MED (2 << 5)
57 #define MST_MSCWR1_IRDA_LOW (3 << 5)
58
59 #define MST_MSCWR1_IRDA_FIR (1 << 4)
60 #define MST_MSCWR1_GREENLED (1 << 3)
61 #define MST_MSCWR1_PDC_CTL (1 << 2)
62 #define MST_MSCWR1_MTR_ON (1 << 1)
63 #define MST_MSCWR1_SYSRESET (1 << 0)
64
65 #define MST_MSCWR2_USB_OTG_RST (1 << 6)
66 #define MST_MSCWR2_USB_OTG_SEL (1 << 5)
67 #define MST_MSCWR2_nUSBC_SC (1 << 4)
68 #define MST_MSCWR2_I2S_SPKROFF (1 << 3)
69 #define MST_MSCWR2_AC97_SPKROFF (1 << 2)
70 #define MST_MSCWR2_RADIO_PWR (1 << 1)
71 #define MST_MSCWR2_RADIO_WAKE (1 << 0)
72
73 #define MST_MSCWR3_GPIO_RESET_EN (1 << 2)
74 #define MST_MSCWR3_GPIO_RESET (1 << 1)
75 #define MST_MSCWR3_COMMS_SW_RESET (1 << 0)
76
77 #define MST_MSCRD_nPENIRQ (1 << 9)
78 #define MST_MSCRD_nMEMSTK_CD (1 << 8)
79 #define MST_MSCRD_nMMC_CD (1 << 7)
80 #define MST_MSCRD_nUSIM_CD (1 << 6)
81 #define MST_MSCRD_USB_CBL (1 << 5)
82 #define MST_MSCRD_TS_BUSY (1 << 4)
83 #define MST_MSCRD_BTDSR (1 << 3)
84 #define MST_MSCRD_BTRI (1 << 2)
85 #define MST_MSCRD_BTDCD (1 << 1)
86 #define MST_MSCRD_nMMC_WP (1 << 0)
87
88 #define MST_INT_S1_IRQ (1 << 15)
89 #define MST_INT_S1_STSCHG (1 << 14)
90 #define MST_INT_S1_CD (1 << 13)
91 #define MST_INT_S0_IRQ (1 << 11)
92 #define MST_INT_S0_STSCHG (1 << 10)
93 #define MST_INT_S0_CD (1 << 9)
94 #define MST_INT_nEXBRD_INT (1 << 7)
95 #define MST_INT_MSINS (1 << 6)
96 #define MST_INT_PENIRQ (1 << 5)
97 #define MST_INT_AC97 (1 << 4)
98 #define MST_INT_ETHERNET (1 << 3)
99 #define MST_INT_USBC (1 << 2)
100 #define MST_INT_USIM (1 << 1)
101 #define MST_INT_MMC (1 << 0)
102
103 #define MST_PCMCIA_nIRQ (1 << 10)
104 #define MST_PCMCIA_nSPKR_BVD2 (1 << 9)
105 #define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8)
106 #define MST_PCMCIA_nVS2 (1 << 7)
107 #define MST_PCMCIA_nVS1 (1 << 6)
108 #define MST_PCMCIA_nCD (1 << 5)
109 #define MST_PCMCIA_RESET (1 << 4)
110 #define MST_PCMCIA_PWR_MASK (0x000f)
111
112 #define MST_PCMCIA_PWR_VPP_0 0x0
113 #define MST_PCMCIA_PWR_VPP_120 0x2
114 #define MST_PCMCIA_PWR_VPP_VCC 0x1
115 #define MST_PCMCIA_PWR_VCC_0 0x0
116 #define MST_PCMCIA_PWR_VCC_33 0x8
117 #define MST_PCMCIA_PWR_VCC_50 0x4
118
119 #define MST_PCMCIA_INPUTS \
120 (MST_PCMCIA_nIRQ | MST_PCMCIA_nSPKR_BVD2 | MST_PCMCIA_nSTSCHG_BVD1 | \
121 MST_PCMCIA_nVS2 | MST_PCMCIA_nVS1 | MST_PCMCIA_nCD)
122
123
124 #define MAINSTONE_NR_IRQS IRQ_BOARD_START
125
126 #define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
127 #define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
128 #define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
129 #define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
130 #define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3)
131 #define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4)
132 #define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5)
133 #define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6)
134 #define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7)
135 #define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9)
136 #define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
137 #define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11)
138 #define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13)
139 #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
140 #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
141
142 #endif