root/arch/arm/mach-integrator/hardware.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  This file contains the hardware definitions of the Integrator.
   4  *
   5  *  Copyright (C) 1998-1999 ARM Limited.
   6  */
   7 #ifndef INTEGRATOR_HARDWARE_H
   8 #define INTEGRATOR_HARDWARE_H
   9 
  10 /*
  11  * Where in virtual memory the IO devices (timers, system controllers
  12  * and so on)
  13  */
  14 #define IO_BASE                 0xF0000000                 // VA of IO
  15 #define IO_SIZE                 0x0B000000                 // How much?
  16 #define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
  17 
  18 /* macro to get at IO space when running virtually */
  19 #ifdef CONFIG_MMU
  20 #define IO_ADDRESS(x)   (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
  21 #else
  22 #define IO_ADDRESS(x)   (x)
  23 #endif
  24 
  25 #define __io_address(n)         ((void __iomem *)IO_ADDRESS(n))
  26 
  27 /*
  28  *  Integrator memory map
  29  */
  30 #define INTEGRATOR_BOOT_ROM_LO          0x00000000
  31 #define INTEGRATOR_BOOT_ROM_HI          0x20000000
  32 #define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI   /*  Normal position */
  33 #define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
  34 
  35 /*
  36  * New Core Modules have different amounts of SSRAM, the amount of SSRAM
  37  * fitted can be found in HDR_STAT.
  38  *
  39  * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
  40  * the minimum amount of SSRAM fitted on any core module.
  41  *
  42  * New Core Modules also alias the SSRAM.
  43  *
  44  */
  45 #define INTEGRATOR_SSRAM_BASE           0x00000000
  46 #define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
  47 #define INTEGRATOR_SSRAM_SIZE           SZ_256K
  48 
  49 #define INTEGRATOR_FLASH_BASE           0x24000000
  50 #define INTEGRATOR_FLASH_SIZE           SZ_32M
  51 
  52 #define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
  53 #define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K
  54 
  55 /*
  56  *  SDRAM is a SIMM therefore the size is not known.
  57  */
  58 #define INTEGRATOR_SDRAM_BASE           0x00040000
  59 
  60 #define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
  61 #define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
  62 #define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
  63 #define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
  64 #define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000
  65 
  66 /*
  67  *  Logic expansion modules
  68  *
  69  */
  70 #define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
  71 #define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
  72 #define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
  73 #define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
  74 #define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
  75 
  76 /*
  77  * Integrator header card registers
  78  */
  79 #define INTEGRATOR_HDR_ID_OFFSET        0x00
  80 #define INTEGRATOR_HDR_PROC_OFFSET      0x04
  81 #define INTEGRATOR_HDR_OSC_OFFSET       0x08
  82 #define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
  83 #define INTEGRATOR_HDR_STAT_OFFSET      0x10
  84 #define INTEGRATOR_HDR_LOCK_OFFSET      0x14
  85 #define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
  86 #define INTEGRATOR_HDR_INIT_OFFSET      0x24     /*  CM9x6 */
  87 #define INTEGRATOR_HDR_IC_OFFSET        0x40
  88 #define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
  89 #define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200
  90 
  91 #define INTEGRATOR_HDR_BASE             0x10000000
  92 #define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
  93 #define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
  94 #define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
  95 #define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
  96 #define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
  97 #define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
  98 #define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
  99 #define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
 100 #define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
 101 #define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
 102 #define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
 103 
 104 #define INTEGRATOR_HDR_CTRL_LED         0x01
 105 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
 106 #define INTEGRATOR_HDR_CTRL_REMAP       0x04
 107 #define INTEGRATOR_HDR_CTRL_RESET       0x08
 108 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
 109 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
 110 #define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
 111 #define INTEGRATOR_HDR_CTRL_SYNC        0x80
 112 
 113 #define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
 114 #define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
 115 #define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
 116 #define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
 117 #define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
 118 #define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
 119 #define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
 120 #define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
 121 #define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
 122 #define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
 123 #define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
 124 #define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
 125 #define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
 126 #define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
 127 #define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
 128 #define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
 129 #define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
 130 #define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
 131 #define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
 132 #define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
 133 #define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
 134 #define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
 135 #define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
 136 #define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
 137 #define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
 138 #define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
 139 #define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
 140 #define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
 141 #define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
 142 #define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
 143 #define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
 144 #define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF
 145 
 146 #define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
 147 #define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
 148 #define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
 149 #define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
 150 #define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
 151 #define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
 152 #define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
 153 #define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
 154 #define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
 155 #define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
 156 #define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000
 157 
 158 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
 159 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
 160 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
 161 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
 162 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000
 163 
 164 #define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
 165 
 166 /*
 167  * Integrator system registers
 168  */
 169 
 170 /*
 171  *  System Controller
 172  */
 173 #define INTEGRATOR_SC_ID_OFFSET         0x00
 174 #define INTEGRATOR_SC_OSC_OFFSET        0x04
 175 #define INTEGRATOR_SC_CTRLS_OFFSET      0x08
 176 #define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
 177 #define INTEGRATOR_SC_DEC_OFFSET        0x10
 178 #define INTEGRATOR_SC_ARB_OFFSET        0x14
 179 #define INTEGRATOR_SC_LOCK_OFFSET       0x1C
 180 
 181 #define INTEGRATOR_SC_BASE              0x11000000
 182 #define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
 183 #define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
 184 #define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 185 #define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 186 #define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
 187 #define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
 188 #define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
 189 #define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
 190 
 191 #define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
 192 #define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
 193 #define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
 194 #define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
 195 #define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
 196 #define INTEGRATOR_SC_OSC_SYS_MASK      0xFF
 197 
 198 #define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
 199 #define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
 200 #define INTEGRATOR_SC_OSC_PCI_MASK      0x100
 201 
 202 #define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
 203 #define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
 204 #define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
 205 #define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
 206 #define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
 207 #define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
 208 #define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)
 209 
 210 /*
 211  *  External Bus Interface
 212  */
 213 #define INTEGRATOR_EBI_BASE             0x12000000
 214 
 215 #define INTEGRATOR_EBI_CSR0_OFFSET      0x00
 216 #define INTEGRATOR_EBI_CSR1_OFFSET      0x04
 217 #define INTEGRATOR_EBI_CSR2_OFFSET      0x08
 218 #define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
 219 #define INTEGRATOR_EBI_LOCK_OFFSET      0x20
 220 
 221 #define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
 222 #define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 223 #define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
 224 #define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
 225 #define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 226 
 227 #define INTEGRATOR_EBI_8_BIT            0x00
 228 #define INTEGRATOR_EBI_16_BIT           0x01
 229 #define INTEGRATOR_EBI_32_BIT           0x02
 230 #define INTEGRATOR_EBI_WRITE_ENABLE     0x04
 231 #define INTEGRATOR_EBI_SYNC             0x08
 232 #define INTEGRATOR_EBI_WS_2             0x00
 233 #define INTEGRATOR_EBI_WS_3             0x10
 234 #define INTEGRATOR_EBI_WS_4             0x20
 235 #define INTEGRATOR_EBI_WS_5             0x30
 236 #define INTEGRATOR_EBI_WS_6             0x40
 237 #define INTEGRATOR_EBI_WS_7             0x50
 238 #define INTEGRATOR_EBI_WS_8             0x60
 239 #define INTEGRATOR_EBI_WS_9             0x70
 240 #define INTEGRATOR_EBI_WS_10            0x80
 241 #define INTEGRATOR_EBI_WS_11            0x90
 242 #define INTEGRATOR_EBI_WS_12            0xA0
 243 #define INTEGRATOR_EBI_WS_13            0xB0
 244 #define INTEGRATOR_EBI_WS_14            0xC0
 245 #define INTEGRATOR_EBI_WS_15            0xD0
 246 #define INTEGRATOR_EBI_WS_16            0xE0
 247 #define INTEGRATOR_EBI_WS_17            0xF0
 248 
 249 
 250 #define INTEGRATOR_CT_BASE              0x13000000       /*  Counter/Timers */
 251 #define INTEGRATOR_IC_BASE              0x14000000       /*  Interrupt Controller */
 252 #define INTEGRATOR_RTC_BASE             0x15000000       /*  Real Time Clock */
 253 #define INTEGRATOR_UART0_BASE           0x16000000       /*  UART 0 */
 254 #define INTEGRATOR_UART1_BASE           0x17000000       /*  UART 1 */
 255 #define INTEGRATOR_KBD_BASE             0x18000000       /*  Keyboard */
 256 #define INTEGRATOR_MOUSE_BASE           0x19000000       /*  Mouse */
 257 
 258 /*
 259  *  LED's & Switches
 260  */
 261 #define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
 262 #define INTEGRATOR_DBG_LEDS_OFFSET      0x04
 263 #define INTEGRATOR_DBG_SWITCH_OFFSET    0x08
 264 
 265 #define INTEGRATOR_DBG_BASE             0x1A000000
 266 #define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
 267 #define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
 268 #define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
 269 
 270 #define INTEGRATOR_AP_GPIO_BASE         0x1B000000      /* GPIO */
 271 
 272 #define INTEGRATOR_CP_MMC_BASE          0x1C000000      /* MMC */
 273 #define INTEGRATOR_CP_AACI_BASE         0x1D000000      /* AACI */
 274 #define INTEGRATOR_CP_ETH_BASE          0xC8000000      /* Ethernet */
 275 #define INTEGRATOR_CP_GPIO_BASE         0xC9000000      /* GPIO */
 276 #define INTEGRATOR_CP_SIC_BASE          0xCA000000      /* SIC */
 277 #define INTEGRATOR_CP_CTL_BASE          0xCB000000      /* CP system control */
 278 
 279 /* PS2 Keyboard interface */
 280 #define KMI0_BASE                       INTEGRATOR_KBD_BASE
 281 
 282 /* PS2 Mouse interface */
 283 #define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
 284 
 285 /*
 286  * Integrator Interrupt Controllers
 287  *
 288  *
 289  * Offsets from interrupt controller base
 290  *
 291  * System Controller interrupt controller base is
 292  *
 293  *      INTEGRATOR_IC_BASE + (header_number << 6)
 294  *
 295  * Core Module interrupt controller base is
 296  *
 297  *      INTEGRATOR_HDR_IC
 298  */
 299 #define IRQ_STATUS                      0
 300 #define IRQ_RAW_STATUS                  0x04
 301 #define IRQ_ENABLE                      0x08
 302 #define IRQ_ENABLE_SET                  0x08
 303 #define IRQ_ENABLE_CLEAR                0x0C
 304 
 305 #define INT_SOFT_SET                    0x10
 306 #define INT_SOFT_CLEAR                  0x14
 307 
 308 #define FIQ_STATUS                      0x20
 309 #define FIQ_RAW_STATUS                  0x24
 310 #define FIQ_ENABLE                      0x28
 311 #define FIQ_ENABLE_SET                  0x28
 312 #define FIQ_ENABLE_CLEAR                0x2C
 313 
 314 
 315 /*
 316  * LED's
 317  */
 318 #define GREEN_LED                       0x01
 319 #define YELLOW_LED                      0x02
 320 #define RED_LED                         0x04
 321 #define GREEN_LED_2                     0x08
 322 #define ALL_LEDS                        0x0F
 323 
 324 #define LED_BANK                        INTEGRATOR_DBG_LEDS
 325 
 326 /*
 327  *  Timer definitions
 328  *
 329  *  Only use timer 1 & 2
 330  *  (both run at 24MHz and will need the clock divider set to 16).
 331  *
 332  *  Timer 0 runs at bus frequency
 333  */
 334 #define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
 335 #define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
 336 #define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
 337 
 338 #define INTEGRATOR_CSR_BASE             0x10000000
 339 #define INTEGRATOR_CSR_SIZE             0x10000000
 340 
 341 #endif /* INTEGRATOR_HARDWARE_H */