This source file includes following definitions.
- omap2420_hwmod_init
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13 #include <linux/platform_data/i2c-omap.h>
14 #include <linux/omap-dma.h>
15
16 #include "omap_hwmod.h"
17 #include "l3_2xxx.h"
18 #include "l4_2xxx.h"
19
20 #include "omap_hwmod_common_data.h"
21
22 #include "cm-regbits-24xx.h"
23 #include "prm-regbits-24xx.h"
24 #include "i2c.h"
25 #include "mmc.h"
26 #include "serial.h"
27 #include "wd_timer.h"
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42
43 static struct omap_hwmod_class iva1_hwmod_class = {
44 .name = "iva1",
45 };
46
47 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
48 { .name = "iva", .rst_shift = 8 },
49 };
50
51 static struct omap_hwmod omap2420_iva_hwmod = {
52 .name = "iva",
53 .class = &iva1_hwmod_class,
54 .clkdm_name = "iva1_clkdm",
55 .rst_lines = omap2420_iva_resets,
56 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
57 .main_clk = "iva1_ifck",
58 };
59
60
61 static struct omap_hwmod_class dsp_hwmod_class = {
62 .name = "dsp",
63 };
64
65 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
66 { .name = "logic", .rst_shift = 0 },
67 { .name = "mmu", .rst_shift = 1 },
68 };
69
70 static struct omap_hwmod omap2420_dsp_hwmod = {
71 .name = "dsp",
72 .class = &dsp_hwmod_class,
73 .clkdm_name = "dsp_clkdm",
74 .rst_lines = omap2420_dsp_resets,
75 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
76 .main_clk = "dsp_fck",
77 };
78
79
80 static struct omap_hwmod_class_sysconfig i2c_sysc = {
81 .rev_offs = 0x00,
82 .sysc_offs = 0x20,
83 .syss_offs = 0x10,
84 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
85 .sysc_fields = &omap_hwmod_sysc_type1,
86 };
87
88 static struct omap_hwmod_class i2c_class = {
89 .name = "i2c",
90 .sysc = &i2c_sysc,
91 .reset = &omap_i2c_reset,
92 };
93
94
95 static struct omap_hwmod omap2420_i2c1_hwmod = {
96 .name = "i2c1",
97 .main_clk = "i2c1_fck",
98 .prcm = {
99 .omap2 = {
100 .module_offs = CORE_MOD,
101 .idlest_reg_id = 1,
102 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
103 },
104 },
105 .class = &i2c_class,
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107
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110
111 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
112 };
113
114
115 static struct omap_hwmod omap2420_i2c2_hwmod = {
116 .name = "i2c2",
117 .main_clk = "i2c2_fck",
118 .prcm = {
119 .omap2 = {
120 .module_offs = CORE_MOD,
121 .idlest_reg_id = 1,
122 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
123 },
124 },
125 .class = &i2c_class,
126 .flags = HWMOD_16BIT_REG,
127 };
128
129
130 static struct omap_dma_dev_attr dma_dev_attr = {
131 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
132 IS_CSSA_32 | IS_CDSA_32,
133 .lch_count = 32,
134 };
135
136 static struct omap_hwmod omap2420_dma_system_hwmod = {
137 .name = "dma",
138 .class = &omap2xxx_dma_hwmod_class,
139 .main_clk = "core_l3_ck",
140 .dev_attr = &dma_dev_attr,
141 .flags = HWMOD_NO_IDLEST,
142 };
143
144
145 static struct omap_hwmod omap2420_mailbox_hwmod = {
146 .name = "mailbox",
147 .class = &omap2xxx_mailbox_hwmod_class,
148 .main_clk = "mailboxes_ick",
149 .prcm = {
150 .omap2 = {
151 .module_offs = CORE_MOD,
152 .idlest_reg_id = 1,
153 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
154 },
155 },
156 };
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162
163 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
164 .name = "mcbsp",
165 };
166
167 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
168 { .role = "pad_fck", .clk = "mcbsp_clks" },
169 { .role = "prcm_fck", .clk = "func_96m_ck" },
170 };
171
172
173 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
174 .name = "mcbsp1",
175 .class = &omap2420_mcbsp_hwmod_class,
176 .main_clk = "mcbsp1_fck",
177 .prcm = {
178 .omap2 = {
179 .module_offs = CORE_MOD,
180 .idlest_reg_id = 1,
181 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
182 },
183 },
184 .opt_clks = mcbsp_opt_clks,
185 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
186 };
187
188
189 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
190 .name = "mcbsp2",
191 .class = &omap2420_mcbsp_hwmod_class,
192 .main_clk = "mcbsp2_fck",
193 .prcm = {
194 .omap2 = {
195 .module_offs = CORE_MOD,
196 .idlest_reg_id = 1,
197 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
198 },
199 },
200 .opt_clks = mcbsp_opt_clks,
201 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
202 };
203
204 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
205 .rev_offs = 0x3c,
206 .sysc_offs = 0x64,
207 .syss_offs = 0x68,
208 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
209 .sysc_fields = &omap_hwmod_sysc_type1,
210 };
211
212 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
213 .name = "msdi",
214 .sysc = &omap2420_msdi_sysc,
215 .reset = &omap_msdi_reset,
216 };
217
218
219 static struct omap_hwmod omap2420_msdi1_hwmod = {
220 .name = "msdi1",
221 .class = &omap2420_msdi_hwmod_class,
222 .main_clk = "mmc_fck",
223 .prcm = {
224 .omap2 = {
225 .module_offs = CORE_MOD,
226 .idlest_reg_id = 1,
227 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
228 },
229 },
230 .flags = HWMOD_16BIT_REG,
231 };
232
233
234 static struct omap_hwmod omap2420_hdq1w_hwmod = {
235 .name = "hdq1w",
236 .main_clk = "hdq_fck",
237 .prcm = {
238 .omap2 = {
239 .module_offs = CORE_MOD,
240 .idlest_reg_id = 1,
241 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
242 },
243 },
244 .class = &omap2_hdq1w_class,
245 };
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251
252 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2420_i2c1_hwmod,
255 .clk = "i2c1_ick",
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
257 };
258
259
260 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
261 .master = &omap2xxx_l4_core_hwmod,
262 .slave = &omap2420_i2c2_hwmod,
263 .clk = "i2c2_ick",
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 };
266
267
268 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
269 .master = &omap2xxx_l3_main_hwmod,
270 .slave = &omap2420_iva_hwmod,
271 .clk = "core_l3_ck",
272 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 };
274
275
276 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
277 .master = &omap2xxx_l3_main_hwmod,
278 .slave = &omap2420_dsp_hwmod,
279 .clk = "dsp_ick",
280 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 };
282
283
284 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
285 .master = &omap2xxx_l4_wkup_hwmod,
286 .slave = &omap2xxx_timer1_hwmod,
287 .clk = "gpt1_ick",
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 };
290
291
292 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
293 .master = &omap2xxx_l4_wkup_hwmod,
294 .slave = &omap2xxx_wd_timer2_hwmod,
295 .clk = "mpu_wdt_ick",
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297 };
298
299
300 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
301 .master = &omap2xxx_l4_wkup_hwmod,
302 .slave = &omap2xxx_gpio1_hwmod,
303 .clk = "gpios_ick",
304 .user = OCP_USER_MPU | OCP_USER_SDMA,
305 };
306
307
308 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
309 .master = &omap2xxx_l4_wkup_hwmod,
310 .slave = &omap2xxx_gpio2_hwmod,
311 .clk = "gpios_ick",
312 .user = OCP_USER_MPU | OCP_USER_SDMA,
313 };
314
315
316 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
317 .master = &omap2xxx_l4_wkup_hwmod,
318 .slave = &omap2xxx_gpio3_hwmod,
319 .clk = "gpios_ick",
320 .user = OCP_USER_MPU | OCP_USER_SDMA,
321 };
322
323
324 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
325 .master = &omap2xxx_l4_wkup_hwmod,
326 .slave = &omap2xxx_gpio4_hwmod,
327 .clk = "gpios_ick",
328 .user = OCP_USER_MPU | OCP_USER_SDMA,
329 };
330
331
332 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
333 .master = &omap2420_dma_system_hwmod,
334 .slave = &omap2xxx_l3_main_hwmod,
335 .clk = "core_l3_ck",
336 .user = OCP_USER_MPU | OCP_USER_SDMA,
337 };
338
339
340 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
341 .master = &omap2xxx_l4_core_hwmod,
342 .slave = &omap2420_dma_system_hwmod,
343 .clk = "sdma_ick",
344 .user = OCP_USER_MPU | OCP_USER_SDMA,
345 };
346
347
348 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
349 .master = &omap2xxx_l4_core_hwmod,
350 .slave = &omap2420_mailbox_hwmod,
351 .user = OCP_USER_MPU | OCP_USER_SDMA,
352 };
353
354
355 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
356 .master = &omap2xxx_l4_core_hwmod,
357 .slave = &omap2420_mcbsp1_hwmod,
358 .clk = "mcbsp1_ick",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
360 };
361
362
363 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
364 .master = &omap2xxx_l4_core_hwmod,
365 .slave = &omap2420_mcbsp2_hwmod,
366 .clk = "mcbsp2_ick",
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
368 };
369
370
371 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
372 .master = &omap2xxx_l4_core_hwmod,
373 .slave = &omap2420_msdi1_hwmod,
374 .clk = "mmc_ick",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
376 };
377
378
379 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
380 .master = &omap2xxx_l4_core_hwmod,
381 .slave = &omap2420_hdq1w_hwmod,
382 .clk = "hdq_ick",
383 .user = OCP_USER_MPU | OCP_USER_SDMA,
384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
385 };
386
387
388
389 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
390 .master = &omap2xxx_l4_wkup_hwmod,
391 .slave = &omap2xxx_counter_32k_hwmod,
392 .clk = "sync_32k_ick",
393 .user = OCP_USER_MPU | OCP_USER_SDMA,
394 };
395
396 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
397 .master = &omap2xxx_l3_main_hwmod,
398 .slave = &omap2xxx_gpmc_hwmod,
399 .clk = "core_l3_ck",
400 .user = OCP_USER_MPU | OCP_USER_SDMA,
401 };
402
403 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
404 &omap2xxx_l3_main__l4_core,
405 &omap2xxx_mpu__l3_main,
406 &omap2xxx_dss__l3,
407 &omap2xxx_l4_core__mcspi1,
408 &omap2xxx_l4_core__mcspi2,
409 &omap2xxx_l4_core__l4_wkup,
410 &omap2_l4_core__uart1,
411 &omap2_l4_core__uart2,
412 &omap2_l4_core__uart3,
413 &omap2420_l4_core__i2c1,
414 &omap2420_l4_core__i2c2,
415 &omap2420_l3__iva,
416 &omap2420_l3__dsp,
417 &omap2420_l4_wkup__timer1,
418 &omap2xxx_l4_core__timer2,
419 &omap2xxx_l4_core__timer3,
420 &omap2xxx_l4_core__timer4,
421 &omap2xxx_l4_core__timer5,
422 &omap2xxx_l4_core__timer6,
423 &omap2xxx_l4_core__timer7,
424 &omap2xxx_l4_core__timer8,
425 &omap2xxx_l4_core__timer9,
426 &omap2xxx_l4_core__timer10,
427 &omap2xxx_l4_core__timer11,
428 &omap2xxx_l4_core__timer12,
429 &omap2420_l4_wkup__wd_timer2,
430 &omap2xxx_l4_core__dss,
431 &omap2xxx_l4_core__dss_dispc,
432 &omap2xxx_l4_core__dss_rfbi,
433 &omap2xxx_l4_core__dss_venc,
434 &omap2420_l4_wkup__gpio1,
435 &omap2420_l4_wkup__gpio2,
436 &omap2420_l4_wkup__gpio3,
437 &omap2420_l4_wkup__gpio4,
438 &omap2420_dma_system__l3,
439 &omap2420_l4_core__dma_system,
440 &omap2420_l4_core__mailbox,
441 &omap2420_l4_core__mcbsp1,
442 &omap2420_l4_core__mcbsp2,
443 &omap2420_l4_core__msdi1,
444 &omap2xxx_l4_core__rng,
445 &omap2xxx_l4_core__sham,
446 &omap2xxx_l4_core__aes,
447 &omap2420_l4_core__hdq1w,
448 &omap2420_l4_wkup__counter_32k,
449 &omap2420_l3__gpmc,
450 NULL,
451 };
452
453 int __init omap2420_hwmod_init(void)
454 {
455 omap_hwmod_init();
456 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
457 }