This source file includes following definitions.
- am43xx_hwmod_init
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17 #include "omap_hwmod.h"
18 #include "omap_hwmod_33xx_43xx_common_data.h"
19 #include "prcm43xx.h"
20 #include "omap_hwmod_common_data.h"
21 #include "hdq1w.h"
22
23
24
25 static struct omap_hwmod am43xx_emif_hwmod = {
26 .name = "emif",
27 .class = &am33xx_emif_hwmod_class,
28 .clkdm_name = "emif_clkdm",
29 .flags = HWMOD_INIT_NO_IDLE,
30 .main_clk = "dpll_ddr_m2_ck",
31 .prcm = {
32 .omap4 = {
33 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
34 .modulemode = MODULEMODE_SWCTRL,
35 },
36 },
37 };
38
39 static struct omap_hwmod am43xx_l4_hs_hwmod = {
40 .name = "l4_hs",
41 .class = &am33xx_l4_hwmod_class,
42 .clkdm_name = "l3_clkdm",
43 .flags = HWMOD_INIT_NO_IDLE,
44 .main_clk = "l4hs_gclk",
45 .prcm = {
46 .omap4 = {
47 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
48 .modulemode = MODULEMODE_SWCTRL,
49 },
50 },
51 };
52
53 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
54 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
55 };
56
57 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
58 .name = "wkup_m3",
59 .class = &am33xx_wkup_m3_hwmod_class,
60 .clkdm_name = "l4_wkup_aon_clkdm",
61
62 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
63 .main_clk = "sys_clkin_ck",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
67 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
68 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
69 .modulemode = MODULEMODE_SWCTRL,
70 },
71 },
72 .rst_lines = am33xx_wkup_m3_resets,
73 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
74 };
75
76 static struct omap_hwmod am43xx_control_hwmod = {
77 .name = "control",
78 .class = &am33xx_control_hwmod_class,
79 .clkdm_name = "l4_wkup_clkdm",
80 .flags = HWMOD_INIT_NO_IDLE,
81 .main_clk = "sys_clkin_ck",
82 .prcm = {
83 .omap4 = {
84 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
85 .modulemode = MODULEMODE_SWCTRL,
86 },
87 },
88 };
89
90 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
91 .rev_offs = 0x0,
92 .sysc_offs = 0x4,
93 .sysc_flags = SYSC_HAS_SIDLEMODE,
94 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
95 .sysc_fields = &omap_hwmod_sysc_type1,
96 };
97
98 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
99 .name = "synctimer",
100 .sysc = &am43xx_synctimer_sysc,
101 };
102
103 static struct omap_hwmod am43xx_synctimer_hwmod = {
104 .name = "counter_32k",
105 .class = &am43xx_synctimer_hwmod_class,
106 .clkdm_name = "l4_wkup_aon_clkdm",
107 .flags = HWMOD_SWSUP_SIDLE,
108 .main_clk = "synctimer_32kclk",
109 .prcm = {
110 .omap4 = {
111 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
112 .modulemode = MODULEMODE_SWCTRL,
113 },
114 },
115 };
116
117 static struct omap_hwmod am43xx_timer8_hwmod = {
118 .name = "timer8",
119 .class = &am33xx_timer_hwmod_class,
120 .clkdm_name = "l4ls_clkdm",
121 .main_clk = "timer8_fck",
122 .prcm = {
123 .omap4 = {
124 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
125 .modulemode = MODULEMODE_SWCTRL,
126 },
127 },
128 };
129
130 static struct omap_hwmod am43xx_timer9_hwmod = {
131 .name = "timer9",
132 .class = &am33xx_timer_hwmod_class,
133 .clkdm_name = "l4ls_clkdm",
134 .main_clk = "timer9_fck",
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
138 .modulemode = MODULEMODE_SWCTRL,
139 },
140 },
141 };
142
143 static struct omap_hwmod am43xx_timer10_hwmod = {
144 .name = "timer10",
145 .class = &am33xx_timer_hwmod_class,
146 .clkdm_name = "l4ls_clkdm",
147 .main_clk = "timer10_fck",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
151 .modulemode = MODULEMODE_SWCTRL,
152 },
153 },
154 };
155
156 static struct omap_hwmod am43xx_timer11_hwmod = {
157 .name = "timer11",
158 .class = &am33xx_timer_hwmod_class,
159 .clkdm_name = "l4ls_clkdm",
160 .main_clk = "timer11_fck",
161 .prcm = {
162 .omap4 = {
163 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
164 .modulemode = MODULEMODE_SWCTRL,
165 },
166 },
167 };
168
169 static struct omap_hwmod am43xx_epwmss3_hwmod = {
170 .name = "epwmss3",
171 .class = &am33xx_epwmss_hwmod_class,
172 .clkdm_name = "l4ls_clkdm",
173 .main_clk = "l4ls_gclk",
174 .prcm = {
175 .omap4 = {
176 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
177 .modulemode = MODULEMODE_SWCTRL,
178 },
179 },
180 };
181
182 static struct omap_hwmod am43xx_epwmss4_hwmod = {
183 .name = "epwmss4",
184 .class = &am33xx_epwmss_hwmod_class,
185 .clkdm_name = "l4ls_clkdm",
186 .main_clk = "l4ls_gclk",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
190 .modulemode = MODULEMODE_SWCTRL,
191 },
192 },
193 };
194
195 static struct omap_hwmod am43xx_epwmss5_hwmod = {
196 .name = "epwmss5",
197 .class = &am33xx_epwmss_hwmod_class,
198 .clkdm_name = "l4ls_clkdm",
199 .main_clk = "l4ls_gclk",
200 .prcm = {
201 .omap4 = {
202 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
203 .modulemode = MODULEMODE_SWCTRL,
204 },
205 },
206 };
207
208 static struct omap_hwmod am43xx_spi2_hwmod = {
209 .name = "spi2",
210 .class = &am33xx_spi_hwmod_class,
211 .clkdm_name = "l4ls_clkdm",
212 .main_clk = "dpll_per_m2_div4_ck",
213 .prcm = {
214 .omap4 = {
215 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
216 .modulemode = MODULEMODE_SWCTRL,
217 },
218 },
219 };
220
221 static struct omap_hwmod am43xx_spi3_hwmod = {
222 .name = "spi3",
223 .class = &am33xx_spi_hwmod_class,
224 .clkdm_name = "l4ls_clkdm",
225 .main_clk = "dpll_per_m2_div4_ck",
226 .prcm = {
227 .omap4 = {
228 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
229 .modulemode = MODULEMODE_SWCTRL,
230 },
231 },
232 };
233
234 static struct omap_hwmod am43xx_spi4_hwmod = {
235 .name = "spi4",
236 .class = &am33xx_spi_hwmod_class,
237 .clkdm_name = "l4ls_clkdm",
238 .main_clk = "dpll_per_m2_div4_ck",
239 .prcm = {
240 .omap4 = {
241 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
242 .modulemode = MODULEMODE_SWCTRL,
243 },
244 },
245 };
246
247 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
248 .name = "ocp2scp",
249 };
250
251 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
252 .name = "ocp2scp0",
253 .class = &am43xx_ocp2scp_hwmod_class,
254 .clkdm_name = "l4ls_clkdm",
255 .main_clk = "l4ls_gclk",
256 .prcm = {
257 .omap4 = {
258 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
259 .modulemode = MODULEMODE_SWCTRL,
260 },
261 },
262 };
263
264 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
265 .name = "ocp2scp1",
266 .class = &am43xx_ocp2scp_hwmod_class,
267 .clkdm_name = "l4ls_clkdm",
268 .main_clk = "l4ls_gclk",
269 .prcm = {
270 .omap4 = {
271 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL,
273 },
274 },
275 };
276
277 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
278 .rev_offs = 0x0000,
279 .sysc_offs = 0x0010,
280 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
281 SYSC_HAS_SIDLEMODE),
282 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
283 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
284 MSTANDBY_NO | MSTANDBY_SMART |
285 MSTANDBY_SMART_WKUP),
286 .sysc_fields = &omap_hwmod_sysc_type2,
287 };
288
289 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
290 .name = "usb_otg_ss",
291 .sysc = &am43xx_usb_otg_ss_sysc,
292 };
293
294 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
295 .name = "usb_otg_ss0",
296 .class = &am43xx_usb_otg_ss_hwmod_class,
297 .clkdm_name = "l3s_clkdm",
298 .main_clk = "l3s_gclk",
299 .prcm = {
300 .omap4 = {
301 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
302 .modulemode = MODULEMODE_SWCTRL,
303 },
304 },
305 };
306
307 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
308 .name = "usb_otg_ss1",
309 .class = &am43xx_usb_otg_ss_hwmod_class,
310 .clkdm_name = "l3s_clkdm",
311 .main_clk = "l3s_gclk",
312 .prcm = {
313 .omap4 = {
314 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
315 .modulemode = MODULEMODE_SWCTRL,
316 },
317 },
318 };
319
320 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
321 .rev_offs = 0,
322 .sysc_offs = 0x0010,
323 .sysc_flags = SYSC_HAS_SIDLEMODE,
324 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
325 SIDLE_SMART_WKUP),
326 .sysc_fields = &omap_hwmod_sysc_type2,
327 };
328
329 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
330 .name = "qspi",
331 .sysc = &am43xx_qspi_sysc,
332 };
333
334 static struct omap_hwmod am43xx_qspi_hwmod = {
335 .name = "qspi",
336 .class = &am43xx_qspi_hwmod_class,
337 .clkdm_name = "l3s_clkdm",
338 .main_clk = "l3s_gclk",
339 .prcm = {
340 .omap4 = {
341 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
342 .modulemode = MODULEMODE_SWCTRL,
343 },
344 },
345 };
346
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349
350
351 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
352 .rev_offs = 0x00,
353 .sysc_offs = 0x10,
354 .sysc_flags = SYSC_HAS_SIDLEMODE,
355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
356 SIDLE_SMART_WKUP),
357 .sysc_fields = &omap_hwmod_sysc_type2,
358 };
359
360 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
361 .name = "adc_tsc",
362 .sysc = &am43xx_adc_tsc_sysc,
363 };
364
365 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
366 .name = "adc_tsc",
367 .class = &am43xx_adc_tsc_hwmod_class,
368 .clkdm_name = "l3s_tsc_clkdm",
369 .main_clk = "adc_tsc_fck",
370 .prcm = {
371 .omap4 = {
372 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
373 .modulemode = MODULEMODE_SWCTRL,
374 },
375 },
376 };
377
378 static struct omap_hwmod_class_sysconfig am43xx_des_sysc = {
379 .rev_offs = 0x30,
380 .sysc_offs = 0x34,
381 .syss_offs = 0x38,
382 .sysc_flags = SYSS_HAS_RESET_STATUS,
383 };
384
385 static struct omap_hwmod_class am43xx_des_hwmod_class = {
386 .name = "des",
387 .sysc = &am43xx_des_sysc,
388 };
389
390 static struct omap_hwmod am43xx_des_hwmod = {
391 .name = "des",
392 .class = &am43xx_des_hwmod_class,
393 .clkdm_name = "l3_clkdm",
394 .main_clk = "l3_gclk",
395 .prcm = {
396 .omap4 = {
397 .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET,
398 .modulemode = MODULEMODE_SWCTRL,
399 },
400 },
401 };
402
403
404
405 static struct omap_hwmod am43xx_dss_core_hwmod = {
406 .name = "dss_core",
407 .class = &omap2_dss_hwmod_class,
408 .clkdm_name = "dss_clkdm",
409 .main_clk = "disp_clk",
410 .prcm = {
411 .omap4 = {
412 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
413 .modulemode = MODULEMODE_SWCTRL,
414 },
415 },
416 };
417
418
419
420 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
421 .manager_count = 1,
422 .has_framedonetv_irq = 0
423 };
424
425 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
426 .rev_offs = 0x0000,
427 .sysc_offs = 0x0010,
428 .syss_offs = 0x0014,
429 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
430 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
431 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435 };
436
437 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &am43xx_dispc_sysc,
440 };
441
442 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
443 .name = "dss_dispc",
444 .class = &am43xx_dispc_hwmod_class,
445 .clkdm_name = "dss_clkdm",
446 .main_clk = "disp_clk",
447 .prcm = {
448 .omap4 = {
449 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
450 },
451 },
452 .dev_attr = &am43xx_dss_dispc_dev_attr,
453 .parent_hwmod = &am43xx_dss_core_hwmod,
454 };
455
456
457
458 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
459 .name = "dss_rfbi",
460 .class = &omap2_rfbi_hwmod_class,
461 .clkdm_name = "dss_clkdm",
462 .main_clk = "disp_clk",
463 .prcm = {
464 .omap4 = {
465 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
466 },
467 },
468 .parent_hwmod = &am43xx_dss_core_hwmod,
469 };
470
471
472 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
473 .rev_offs = 0x0000,
474 .sysc_offs = 0x0014,
475 .syss_offs = 0x0018,
476 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
477 .sysc_fields = &omap_hwmod_sysc_type1,
478 };
479
480 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
481 .name = "hdq1w",
482 .sysc = &am43xx_hdq1w_sysc,
483 .reset = &omap_hdq1w_reset,
484 };
485
486 static struct omap_hwmod am43xx_hdq1w_hwmod = {
487 .name = "hdq1w",
488 .class = &am43xx_hdq1w_hwmod_class,
489 .clkdm_name = "l4ls_clkdm",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
493 .modulemode = MODULEMODE_SWCTRL,
494 },
495 },
496 };
497
498 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
499 .rev_offs = 0x0,
500 .sysc_offs = 0x104,
501 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
503 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
504 .sysc_fields = &omap_hwmod_sysc_type2,
505 };
506
507 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
508 .name = "vpfe",
509 .sysc = &am43xx_vpfe_sysc,
510 };
511
512 static struct omap_hwmod am43xx_vpfe0_hwmod = {
513 .name = "vpfe0",
514 .class = &am43xx_vpfe_hwmod_class,
515 .clkdm_name = "l3s_clkdm",
516 .prcm = {
517 .omap4 = {
518 .modulemode = MODULEMODE_SWCTRL,
519 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
520 },
521 },
522 };
523
524 static struct omap_hwmod am43xx_vpfe1_hwmod = {
525 .name = "vpfe1",
526 .class = &am43xx_vpfe_hwmod_class,
527 .clkdm_name = "l3s_clkdm",
528 .prcm = {
529 .omap4 = {
530 .modulemode = MODULEMODE_SWCTRL,
531 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
532 },
533 },
534 };
535
536
537 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
538 .master = &am33xx_l3_main_hwmod,
539 .slave = &am43xx_emif_hwmod,
540 .clk = "dpll_core_m4_ck",
541 .user = OCP_USER_MPU | OCP_USER_SDMA,
542 };
543
544 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
545 .master = &am33xx_l3_main_hwmod,
546 .slave = &am43xx_l4_hs_hwmod,
547 .clk = "l3s_gclk",
548 .user = OCP_USER_MPU | OCP_USER_SDMA,
549 };
550
551 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
552 .master = &am43xx_wkup_m3_hwmod,
553 .slave = &am33xx_l4_wkup_hwmod,
554 .clk = "sys_clkin_ck",
555 .user = OCP_USER_MPU | OCP_USER_SDMA,
556 };
557
558 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
559 .master = &am33xx_l4_wkup_hwmod,
560 .slave = &am43xx_wkup_m3_hwmod,
561 .clk = "sys_clkin_ck",
562 .user = OCP_USER_MPU | OCP_USER_SDMA,
563 };
564
565 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
566 .master = &am33xx_l3_main_hwmod,
567 .slave = &am33xx_pruss_hwmod,
568 .clk = "dpll_core_m4_ck",
569 .user = OCP_USER_MPU,
570 };
571
572 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
573 .master = &am33xx_l4_wkup_hwmod,
574 .slave = &am33xx_smartreflex0_hwmod,
575 .clk = "sys_clkin_ck",
576 .user = OCP_USER_MPU,
577 };
578
579 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
580 .master = &am33xx_l4_wkup_hwmod,
581 .slave = &am33xx_smartreflex1_hwmod,
582 .clk = "sys_clkin_ck",
583 .user = OCP_USER_MPU,
584 };
585
586 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
587 .master = &am33xx_l4_wkup_hwmod,
588 .slave = &am43xx_control_hwmod,
589 .clk = "sys_clkin_ck",
590 .user = OCP_USER_MPU,
591 };
592
593 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
594 .master = &am33xx_l4_wkup_hwmod,
595 .slave = &am43xx_adc_tsc_hwmod,
596 .clk = "dpll_core_m4_div2_ck",
597 .user = OCP_USER_MPU,
598 };
599
600 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
601 .master = &am33xx_l4_wkup_hwmod,
602 .slave = &am33xx_timer1_hwmod,
603 .clk = "sys_clkin_ck",
604 .user = OCP_USER_MPU,
605 };
606
607 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
608 .master = &am33xx_l4_wkup_hwmod,
609 .slave = &am33xx_wd_timer1_hwmod,
610 .clk = "sys_clkin_ck",
611 .user = OCP_USER_MPU,
612 };
613
614 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
615 .master = &am33xx_l4_wkup_hwmod,
616 .slave = &am43xx_synctimer_hwmod,
617 .clk = "sys_clkin_ck",
618 .user = OCP_USER_MPU,
619 };
620
621 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
622 .master = &am33xx_l4_ls_hwmod,
623 .slave = &am43xx_timer8_hwmod,
624 .clk = "l4ls_gclk",
625 .user = OCP_USER_MPU,
626 };
627
628 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
629 .master = &am33xx_l4_ls_hwmod,
630 .slave = &am43xx_timer9_hwmod,
631 .clk = "l4ls_gclk",
632 .user = OCP_USER_MPU,
633 };
634
635 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
636 .master = &am33xx_l4_ls_hwmod,
637 .slave = &am43xx_timer10_hwmod,
638 .clk = "l4ls_gclk",
639 .user = OCP_USER_MPU,
640 };
641
642 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
643 .master = &am33xx_l4_ls_hwmod,
644 .slave = &am43xx_timer11_hwmod,
645 .clk = "l4ls_gclk",
646 .user = OCP_USER_MPU,
647 };
648
649 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
650 .master = &am33xx_l4_ls_hwmod,
651 .slave = &am43xx_epwmss3_hwmod,
652 .clk = "l4ls_gclk",
653 .user = OCP_USER_MPU,
654 };
655
656 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
657 .master = &am33xx_l4_ls_hwmod,
658 .slave = &am43xx_epwmss4_hwmod,
659 .clk = "l4ls_gclk",
660 .user = OCP_USER_MPU,
661 };
662
663 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
664 .master = &am33xx_l4_ls_hwmod,
665 .slave = &am43xx_epwmss5_hwmod,
666 .clk = "l4ls_gclk",
667 .user = OCP_USER_MPU,
668 };
669
670 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
671 .master = &am33xx_l4_ls_hwmod,
672 .slave = &am43xx_spi2_hwmod,
673 .clk = "l4ls_gclk",
674 .user = OCP_USER_MPU,
675 };
676
677 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
678 .master = &am33xx_l4_ls_hwmod,
679 .slave = &am43xx_spi3_hwmod,
680 .clk = "l4ls_gclk",
681 .user = OCP_USER_MPU,
682 };
683
684 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
685 .master = &am33xx_l4_ls_hwmod,
686 .slave = &am43xx_spi4_hwmod,
687 .clk = "l4ls_gclk",
688 .user = OCP_USER_MPU,
689 };
690
691 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
692 .master = &am33xx_l4_ls_hwmod,
693 .slave = &am43xx_ocp2scp0_hwmod,
694 .clk = "l4ls_gclk",
695 .user = OCP_USER_MPU,
696 };
697
698 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
699 .master = &am33xx_l4_ls_hwmod,
700 .slave = &am43xx_ocp2scp1_hwmod,
701 .clk = "l4ls_gclk",
702 .user = OCP_USER_MPU,
703 };
704
705 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
706 .master = &am33xx_l3_s_hwmod,
707 .slave = &am43xx_usb_otg_ss0_hwmod,
708 .clk = "l3s_gclk",
709 .user = OCP_USER_MPU | OCP_USER_SDMA,
710 };
711
712 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
713 .master = &am33xx_l3_s_hwmod,
714 .slave = &am43xx_usb_otg_ss1_hwmod,
715 .clk = "l3s_gclk",
716 .user = OCP_USER_MPU | OCP_USER_SDMA,
717 };
718
719 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
720 .master = &am33xx_l3_s_hwmod,
721 .slave = &am43xx_qspi_hwmod,
722 .clk = "l3s_gclk",
723 .user = OCP_USER_MPU | OCP_USER_SDMA,
724 };
725
726 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
727 .master = &am43xx_dss_core_hwmod,
728 .slave = &am33xx_l3_main_hwmod,
729 .clk = "l3_gclk",
730 .user = OCP_USER_MPU | OCP_USER_SDMA,
731 };
732
733 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
734 .master = &am33xx_l4_ls_hwmod,
735 .slave = &am43xx_dss_core_hwmod,
736 .clk = "l4ls_gclk",
737 .user = OCP_USER_MPU | OCP_USER_SDMA,
738 };
739
740 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
741 .master = &am33xx_l4_ls_hwmod,
742 .slave = &am43xx_dss_dispc_hwmod,
743 .clk = "l4ls_gclk",
744 .user = OCP_USER_MPU | OCP_USER_SDMA,
745 };
746
747 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
748 .master = &am33xx_l4_ls_hwmod,
749 .slave = &am43xx_dss_rfbi_hwmod,
750 .clk = "l4ls_gclk",
751 .user = OCP_USER_MPU | OCP_USER_SDMA,
752 };
753
754 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
755 .master = &am33xx_l4_ls_hwmod,
756 .slave = &am43xx_hdq1w_hwmod,
757 .clk = "l4ls_gclk",
758 .user = OCP_USER_MPU | OCP_USER_SDMA,
759 };
760
761 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
762 .master = &am43xx_vpfe0_hwmod,
763 .slave = &am33xx_l3_main_hwmod,
764 .clk = "l3_gclk",
765 .user = OCP_USER_MPU | OCP_USER_SDMA,
766 };
767
768 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
769 .master = &am43xx_vpfe1_hwmod,
770 .slave = &am33xx_l3_main_hwmod,
771 .clk = "l3_gclk",
772 .user = OCP_USER_MPU | OCP_USER_SDMA,
773 };
774
775 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
776 .master = &am33xx_l4_ls_hwmod,
777 .slave = &am43xx_vpfe0_hwmod,
778 .clk = "l4ls_gclk",
779 .user = OCP_USER_MPU | OCP_USER_SDMA,
780 };
781
782 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
783 .master = &am33xx_l4_ls_hwmod,
784 .slave = &am43xx_vpfe1_hwmod,
785 .clk = "l4ls_gclk",
786 .user = OCP_USER_MPU | OCP_USER_SDMA,
787 };
788
789 static struct omap_hwmod_ocp_if am43xx_l3_main__des = {
790 .master = &am33xx_l3_main_hwmod,
791 .slave = &am43xx_des_hwmod,
792 .clk = "l3_gclk",
793 .user = OCP_USER_MPU,
794 };
795
796 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
797 &am33xx_l4_wkup__synctimer,
798 &am43xx_l4_ls__timer8,
799 &am43xx_l4_ls__timer9,
800 &am43xx_l4_ls__timer10,
801 &am43xx_l4_ls__timer11,
802 &am43xx_l4_ls__epwmss3,
803 &am43xx_l4_ls__epwmss4,
804 &am43xx_l4_ls__epwmss5,
805 &am43xx_l4_ls__mcspi2,
806 &am43xx_l4_ls__mcspi3,
807 &am43xx_l4_ls__mcspi4,
808 &am43xx_l3_main__pruss,
809 &am33xx_mpu__l3_main,
810 &am33xx_mpu__prcm,
811 &am33xx_l3_s__l4_ls,
812 &am33xx_l3_s__l4_wkup,
813 &am43xx_l3_main__l4_hs,
814 &am33xx_l3_main__l3_s,
815 &am33xx_l3_main__l3_instr,
816 &am33xx_l3_main__gfx,
817 &am33xx_l3_s__l3_main,
818 &am43xx_l3_main__emif,
819 &am33xx_pruss__l3_main,
820 &am43xx_wkup_m3__l4_wkup,
821 &am33xx_gfx__l3_main,
822 &am43xx_l4_wkup__wkup_m3,
823 &am43xx_l4_wkup__control,
824 &am43xx_l4_wkup__smartreflex0,
825 &am43xx_l4_wkup__smartreflex1,
826 &am43xx_l4_wkup__timer1,
827 &am43xx_l4_wkup__wd_timer1,
828 &am43xx_l4_wkup__adc_tsc,
829 &am43xx_l3_s__qspi,
830 &am33xx_l4_per__dcan0,
831 &am33xx_l4_per__dcan1,
832 &am33xx_l4_per__mailbox,
833 &am33xx_l4_per__rng,
834 &am33xx_l4_ls__mcasp0,
835 &am33xx_l4_ls__mcasp1,
836 &am33xx_l4_ls__timer2,
837 &am33xx_l4_ls__timer3,
838 &am33xx_l4_ls__timer4,
839 &am33xx_l4_ls__timer5,
840 &am33xx_l4_ls__timer6,
841 &am33xx_l4_ls__timer7,
842 &am33xx_l3_main__tpcc,
843 &am33xx_l4_ls__spinlock,
844 &am33xx_l4_ls__elm,
845 &am33xx_l4_ls__epwmss0,
846 &am33xx_l4_ls__epwmss1,
847 &am33xx_l4_ls__epwmss2,
848 &am33xx_l3_s__gpmc,
849 &am33xx_l4_ls__mcspi0,
850 &am33xx_l4_ls__mcspi1,
851 &am33xx_l3_main__tptc0,
852 &am33xx_l3_main__tptc1,
853 &am33xx_l3_main__tptc2,
854 &am33xx_l3_main__ocmc,
855 &am33xx_l3_main__sha0,
856 &am33xx_l3_main__aes0,
857 &am43xx_l3_main__des,
858 &am43xx_l4_ls__ocp2scp0,
859 &am43xx_l4_ls__ocp2scp1,
860 &am43xx_l3_s__usbotgss0,
861 &am43xx_l3_s__usbotgss1,
862 &am43xx_dss__l3_main,
863 &am43xx_l4_ls__dss,
864 &am43xx_l4_ls__dss_dispc,
865 &am43xx_l4_ls__dss_rfbi,
866 &am43xx_l4_ls__hdq1w,
867 &am43xx_l3__vpfe0,
868 &am43xx_l3__vpfe1,
869 &am43xx_l4_ls__vpfe0,
870 &am43xx_l4_ls__vpfe1,
871 NULL,
872 };
873
874 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
875 &am33xx_l4_wkup__rtc,
876 NULL,
877 };
878
879 int __init am43xx_hwmod_init(void)
880 {
881 int ret;
882
883 omap_hwmod_am43xx_reg();
884 omap_hwmod_init();
885 ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
886
887 if (!ret && of_machine_is_compatible("ti,am4372"))
888 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
889
890 return ret;
891 }