root/arch/arm/mach-omap2/sram243x.S

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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * linux/arch/arm/mach-omap2/sram243x.S
   4  *
   5  * Omap2 specific functions that need to be run in internal SRAM
   6  *
   7  * (C) Copyright 2004
   8  * Texas Instruments, <www.ti.com>
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * Richard Woodruff notes that any changes to this code must be carefully
  12  * audited and tested to ensure that they don't cause a TLB miss while
  13  * the SDRAM is inaccessible.  Such a situation will crash the system
  14  * since it will cause the ARM MMU to attempt to walk the page tables.
  15  * These crashes may be intermittent.
  16  */
  17 #include <linux/linkage.h>
  18 
  19 #include <asm/assembler.h>
  20 
  21 #include "soc.h"
  22 #include "iomap.h"
  23 #include "prm2xxx.h"
  24 #include "cm2xxx.h"
  25 #include "sdrc.h"
  26 
  27         .text
  28 
  29         .align  3
  30 ENTRY(omap243x_sram_ddr_init)
  31         stmfd   sp!, {r0 - r12, lr}     @ save registers on stack
  32 
  33         mov     r12, r2                 @ capture CS1 vs CS0
  34         mov     r8, r3                  @ capture force parameter
  35 
  36         /* frequency shift down */
  37         ldr     r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
  38         mov     r3, #0x1                @ value for 1x operation
  39         str     r3, [r2]                @ go to L1-freq operation
  40 
  41         /* voltage shift down */
  42         mov r9, #0x1                    @ set up for L1 voltage call
  43         bl voltage_shift                @ go drop voltage
  44 
  45         /* dll lock mode */
  46         ldr     r11, omap243x_sdi_sdrc_dlla_ctrl        @ addr of dlla ctrl
  47         ldr     r10, [r11]              @ get current val
  48         cmp     r12, #0x1               @ cs1 base (2422 es2.05/1)
  49         addeq   r11, r11, #0x8          @ if cs1 base, move to DLLB
  50         mvn     r9, #0x4                @ mask to get clear bit2
  51         and     r10, r10, r9            @ clear bit2 for lock mode.
  52         orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
  53         orr     r10, r10, #0x2          @ 90 degree phase for all below 133MHz
  54         str     r10, [r11]              @ commit to DLLA_CTRL
  55         bl      i_dll_wait              @ wait for dll to lock
  56 
  57         /* get dll value */
  58         add     r11, r11, #0x4          @ get addr of status reg
  59         ldr     r10, [r11]              @ get locked value
  60 
  61         /* voltage shift up */
  62         mov r9, #0x0                    @ shift back to L0-voltage
  63         bl voltage_shift                @ go raise voltage
  64 
  65         /* frequency shift up */
  66         mov     r3, #0x2                @ value for 2x operation
  67         str     r3, [r2]                @ go to L0-freq operation
  68 
  69         /* reset entry mode for dllctrl */
  70         sub     r11, r11, #0x4          @ move from status to ctrl
  71         cmp     r12, #0x1               @ normalize if cs1 based
  72         subeq   r11, r11, #0x8          @ possibly back to DLLA
  73         cmp     r8, #0x1                @ if forced unlock exit
  74         orreq   r1, r1, #0x4            @ make sure exit with unlocked value
  75         str     r1, [r11]               @ restore DLLA_CTRL high value
  76         add     r11, r11, #0x8          @ move to DLLB_CTRL addr
  77         str     r1, [r11]               @ set value DLLB_CTRL
  78         bl      i_dll_wait              @ wait for possible lock
  79 
  80         /* set up for return, DDR should be good */
  81         str r10, [r0]                   @ write dll_status and return counter
  82         ldmfd   sp!, {r0 - r12, pc}     @ restore regs and return
  83 
  84         /* ensure the DLL has relocked */
  85 i_dll_wait:
  86         mov     r4, #0x800              @ delay DLL relock, min 0x400 L3 clocks
  87 i_dll_delay:
  88         subs    r4, r4, #0x1
  89         bne     i_dll_delay
  90         ret     lr
  91 
  92         /*
  93          * shift up or down voltage, use R9 as input to tell level.
  94          * wait for it to finish, use 32k sync counter, 1tick=31uS.
  95          */
  96 voltage_shift:
  97         ldr     r4, omap243x_sdi_prcm_voltctrl  @ get addr of volt ctrl.
  98         ldr     r5, [r4]                @ get value.
  99         ldr     r6, prcm_mask_val       @ get value of mask
 100         and     r5, r5, r6              @ apply mask to clear bits
 101         orr     r5, r5, r9              @ bulld value for L0/L1-volt operation.
 102         str     r5, [r4]                @ set up for change.
 103         mov     r3, #0x4000             @ get val for force
 104         orr     r5, r5, r3              @ build value for force
 105         str     r5, [r4]                @ Force transition to L1
 106 
 107         ldr     r3, omap243x_sdi_timer_32ksynct_cr      @ get addr of counter
 108         ldr     r5, [r3]                @ get value
 109         add     r5, r5, #0x3            @ give it at most 93uS
 110 volt_delay:
 111         ldr     r7, [r3]                @ get timer value
 112         cmp     r5, r7                  @ time up?
 113         bhi     volt_delay              @ not yet->branch
 114         ret     lr                      @ back to caller.
 115 
 116 omap243x_sdi_cm_clksel2_pll:
 117         .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 118 omap243x_sdi_sdrc_dlla_ctrl:
 119         .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 120 omap243x_sdi_prcm_voltctrl:
 121         .word OMAP2430_PRCM_VOLTCTRL
 122 prcm_mask_val:
 123         .word 0xFFFF3FFC
 124 omap243x_sdi_timer_32ksynct_cr:
 125         .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 126 ENTRY(omap243x_sram_ddr_init_sz)
 127         .word   . - omap243x_sram_ddr_init
 128 
 129 /*
 130  * Reprograms memory timings.
 131  * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
 132  * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
 133  */
 134         .align  3
 135 ENTRY(omap243x_sram_reprogram_sdrc)
 136         stmfd   sp!, {r0 - r10, lr}     @ save registers on stack
 137         mov     r3, #0x0                @ clear for mrc call
 138         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier, finish ARM SDR/DDR
 139         nop
 140         nop
 141         ldr     r6, omap243x_srs_sdrc_rfr_ctrl  @ get addr of refresh reg
 142         ldr     r5, [r6]                @ get value
 143         mov     r5, r5, lsr #8          @ isolate rfr field and drop burst
 144 
 145         cmp     r0, #0x1                @ going to half speed?
 146         movne   r9, #0x0                @ if up set flag up for pre up, hi volt
 147 
 148         blne    voltage_shift_c         @ adjust voltage
 149 
 150         cmp     r0, #0x1                @ going to half speed (post branch link)
 151         moveq   r5, r5, lsr #1          @ divide by 2 if to half
 152         movne   r5, r5, lsl #1          @ mult by 2 if to full
 153         mov     r5, r5, lsl #8          @ put rfr field back into place
 154         add     r5, r5, #0x1            @ turn on burst of 1
 155         ldr     r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
 156         ldr     r3, [r4]                @ get curr value
 157         orr     r3, r3, #0x3
 158         bic     r3, r3, #0x3            @ clear lower bits
 159         orr     r3, r3, r0              @ new state value
 160         str     r3, [r4]                @ set new state (pll/x, x=1 or 2)
 161         nop
 162         nop
 163 
 164         moveq   r9, #0x1                @ if speed down, post down, drop volt
 165         bleq    voltage_shift_c
 166 
 167         mcr     p15, 0, r3, c7, c10, 4  @ memory barrier
 168         str     r5, [r6]                @ set new RFR_1 value
 169         add     r6, r6, #0x30           @ get RFR_2 addr
 170         str     r5, [r6]                @ set RFR_2
 171         nop
 172         cmp     r2, #0x1                @ (SDR or DDR) do we need to adjust DLL
 173         bne     freq_out                @ leave if SDR, no DLL function
 174 
 175         /* With DDR, we need to take care of the DLL for the frequency change */
 176         ldr     r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
 177         str     r1, [r2]                @ write out new SDRC_DLLA_CTRL
 178         add     r2, r2, #0x8            @ addr to SDRC_DLLB_CTRL
 179         str     r1, [r2]                @ commit to SDRC_DLLB_CTRL
 180         mov     r1, #0x2000             @ wait DLL relock, min 0x400 L3 clocks
 181 dll_wait:
 182         subs    r1, r1, #0x1
 183         bne     dll_wait
 184 freq_out:
 185         ldmfd   sp!, {r0 - r10, pc}     @ restore regs and return
 186 
 187     /*
 188      * shift up or down voltage, use R9 as input to tell level.
 189      *  wait for it to finish, use 32k sync counter, 1tick=31uS.
 190      */
 191 voltage_shift_c:
 192         ldr     r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
 193         ldr     r8, [r10]               @ get value
 194         ldr     r7, ddr_prcm_mask_val   @ get value of mask
 195         and     r8, r8, r7              @ apply mask to clear bits
 196         orr     r8, r8, r9              @ bulld value for L0/L1-volt operation.
 197         str     r8, [r10]               @ set up for change.
 198         mov     r7, #0x4000             @ get val for force
 199         orr     r8, r8, r7              @ build value for force
 200         str     r8, [r10]               @ Force transition to L1
 201 
 202         ldr     r10, omap243x_srs_timer_32ksynct        @ get addr of counter
 203         ldr     r8, [r10]               @ get value
 204         add     r8, r8, #0x2            @ give it at most 62uS (min 31+)
 205 volt_delay_c:
 206         ldr     r7, [r10]               @ get timer value
 207         cmp     r8, r7                  @ time up?
 208         bhi     volt_delay_c            @ not yet->branch
 209         ret     lr                      @ back to caller
 210 
 211 omap243x_srs_cm_clksel2_pll:
 212         .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
 213 omap243x_srs_sdrc_dlla_ctrl:
 214         .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 215 omap243x_srs_sdrc_rfr_ctrl:
 216         .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 217 omap243x_srs_prcm_voltctrl:
 218         .word OMAP2430_PRCM_VOLTCTRL
 219 ddr_prcm_mask_val:
 220         .word 0xFFFF3FFC
 221 omap243x_srs_timer_32ksynct:
 222         .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
 223 
 224 ENTRY(omap243x_sram_reprogram_sdrc_sz)
 225         .word   . - omap243x_sram_reprogram_sdrc
 226 
 227 /*
 228  * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
 229  */
 230         .align  3
 231 ENTRY(omap243x_sram_set_prcm)
 232         stmfd   sp!, {r0-r12, lr}       @ regs to stack
 233         adr     r4, pbegin              @ addr of preload start
 234         adr     r8, pend                @ addr of preload end
 235         mcrr    p15, 1, r8, r4, c12     @ preload into icache
 236 pbegin:
 237         /* move into fast relock bypass */
 238         ldr     r8, omap243x_ssp_pll_ctl        @ get addr
 239         ldr     r5, [r8]                @ get val
 240         mvn     r6, #0x3                @ clear mask
 241         and     r5, r5, r6              @ clear field
 242         orr     r7, r5, #0x2            @ fast relock val
 243         str     r7, [r8]                @ go to fast relock
 244         ldr     r4, omap243x_ssp_pll_stat       @ addr of stat
 245 block:
 246         /* wait for bypass */
 247         ldr     r8, [r4]                @ stat value
 248         and     r8, r8, #0x3            @ mask for stat
 249         cmp     r8, #0x1                @ there yet
 250         bne     block                   @ loop if not
 251 
 252         /* set new dpll dividers _after_ in bypass */
 253         ldr     r4, omap243x_ssp_pll_div        @ get addr
 254         str     r0, [r4]                @ set dpll ctrl val
 255 
 256         ldr     r4, omap243x_ssp_set_config     @ get addr
 257         mov     r8, #1                  @ valid cfg msk
 258         str     r8, [r4]                @ make dividers take
 259 
 260         mov     r4, #100                @ dead spin a bit
 261 wait_a_bit:
 262         subs    r4, r4, #1              @ dec loop
 263         bne     wait_a_bit              @ delay done?
 264 
 265         /* check if staying in bypass */
 266         cmp     r2, #0x1                @ stay in bypass?
 267         beq     pend                    @ jump over dpll relock
 268 
 269         /* relock DPLL with new vals */
 270         ldr     r5, omap243x_ssp_pll_stat       @ get addr
 271         ldr     r4, omap243x_ssp_pll_ctl        @ get addr
 272         orr     r8, r7, #0x3            @ val for lock dpll
 273         str     r8, [r4]                @ set val
 274         mov     r0, #1000               @ dead spin a bit
 275 wait_more:
 276         subs    r0, r0, #1              @ dec loop
 277         bne     wait_more               @ delay done?
 278 wait_lock:
 279         ldr     r8, [r5]                @ get lock val
 280         and     r8, r8, #3              @ isolate field
 281         cmp     r8, #2                  @ locked?
 282         bne     wait_lock               @ wait if not
 283 pend:
 284         /* update memory timings & briefly lock dll */
 285         ldr     r4, omap243x_ssp_sdrc_rfr       @ get addr
 286         str     r1, [r4]                @ update refresh timing
 287         ldr     r11, omap243x_ssp_dlla_ctrl     @ get addr of DLLA ctrl
 288         ldr     r10, [r11]              @ get current val
 289         mvn     r9, #0x4                @ mask to get clear bit2
 290         and     r10, r10, r9            @ clear bit2 for lock mode
 291         orr     r10, r10, #0x8          @ make sure DLL on (es2 bit pos)
 292         str     r10, [r11]              @ commit to DLLA_CTRL
 293         add     r11, r11, #0x8          @ move to dllb
 294         str     r10, [r11]              @ hit DLLB also
 295 
 296         mov     r4, #0x800              @ relock time (min 0x400 L3 clocks)
 297 wait_dll_lock:
 298         subs    r4, r4, #0x1
 299         bne     wait_dll_lock
 300         nop
 301         ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 302 
 303 omap243x_ssp_set_config:
 304         .word OMAP2430_PRCM_CLKCFG_CTRL
 305 omap243x_ssp_pll_ctl:
 306         .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
 307 omap243x_ssp_pll_stat:
 308         .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
 309 omap243x_ssp_pll_div:
 310         .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 311 omap243x_ssp_sdrc_rfr:
 312         .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 313 omap243x_ssp_dlla_ctrl:
 314         .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
 315 
 316 ENTRY(omap243x_sram_set_prcm_sz)
 317         .word   . - omap243x_sram_set_prcm

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