root/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Interconnects common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16 
  17 #include <linux/sizes.h>
  18 #include "omap_hwmod.h"
  19 #include "omap_hwmod_33xx_43xx_common_data.h"
  20 
  21 /* mpu -> l3 main */
  22 struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
  23         .master         = &am33xx_mpu_hwmod,
  24         .slave          = &am33xx_l3_main_hwmod,
  25         .clk            = "dpll_mpu_m2_ck",
  26         .user           = OCP_USER_MPU,
  27 };
  28 
  29 /* l3 main -> l3 s */
  30 struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
  31         .master         = &am33xx_l3_main_hwmod,
  32         .slave          = &am33xx_l3_s_hwmod,
  33         .clk            = "l3s_gclk",
  34         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  35 };
  36 
  37 /* l3 s -> l4 per/ls */
  38 struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
  39         .master         = &am33xx_l3_s_hwmod,
  40         .slave          = &am33xx_l4_ls_hwmod,
  41         .clk            = "l3s_gclk",
  42         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  43 };
  44 
  45 /* l3 s -> l4 wkup */
  46 struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
  47         .master         = &am33xx_l3_s_hwmod,
  48         .slave          = &am33xx_l4_wkup_hwmod,
  49         .clk            = "l3s_gclk",
  50         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  51 };
  52 
  53 /* l3 main -> l3 instr */
  54 struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
  55         .master         = &am33xx_l3_main_hwmod,
  56         .slave          = &am33xx_l3_instr_hwmod,
  57         .clk            = "l3s_gclk",
  58         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  59 };
  60 
  61 /* mpu -> prcm */
  62 struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
  63         .master         = &am33xx_mpu_hwmod,
  64         .slave          = &am33xx_prcm_hwmod,
  65         .clk            = "dpll_mpu_m2_ck",
  66         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  67 };
  68 
  69 /* l3 s -> l3 main*/
  70 struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
  71         .master         = &am33xx_l3_s_hwmod,
  72         .slave          = &am33xx_l3_main_hwmod,
  73         .clk            = "l3s_gclk",
  74         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  75 };
  76 
  77 /* pru-icss -> l3 main */
  78 struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
  79         .master         = &am33xx_pruss_hwmod,
  80         .slave          = &am33xx_l3_main_hwmod,
  81         .clk            = "l3_gclk",
  82         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  83 };
  84 
  85 /* gfx -> l3 main */
  86 struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
  87         .master         = &am33xx_gfx_hwmod,
  88         .slave          = &am33xx_l3_main_hwmod,
  89         .clk            = "dpll_core_m4_ck",
  90         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  91 };
  92 
  93 /* l3 main -> gfx */
  94 struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
  95         .master         = &am33xx_l3_main_hwmod,
  96         .slave          = &am33xx_gfx_hwmod,
  97         .clk            = "dpll_core_m4_ck",
  98         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  99 };
 100 
 101 /* l4 wkup -> rtc */
 102 struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
 103         .master         = &am33xx_l4_wkup_hwmod,
 104         .slave          = &am33xx_rtc_hwmod,
 105         .clk            = "clkdiv32k_ick",
 106         .user           = OCP_USER_MPU,
 107 };
 108 
 109 /* l4 per/ls -> DCAN0 */
 110 struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
 111         .master         = &am33xx_l4_ls_hwmod,
 112         .slave          = &am33xx_dcan0_hwmod,
 113         .clk            = "l4ls_gclk",
 114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 115 };
 116 
 117 /* l4 per/ls -> DCAN1 */
 118 struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
 119         .master         = &am33xx_l4_ls_hwmod,
 120         .slave          = &am33xx_dcan1_hwmod,
 121         .clk            = "l4ls_gclk",
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124 
 125 struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
 126         .master         = &am33xx_l4_ls_hwmod,
 127         .slave          = &am33xx_elm_hwmod,
 128         .clk            = "l4ls_gclk",
 129         .user           = OCP_USER_MPU,
 130 };
 131 
 132 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
 133         .master         = &am33xx_l4_ls_hwmod,
 134         .slave          = &am33xx_epwmss0_hwmod,
 135         .clk            = "l4ls_gclk",
 136         .user           = OCP_USER_MPU,
 137 };
 138 
 139 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
 140         .master         = &am33xx_l4_ls_hwmod,
 141         .slave          = &am33xx_epwmss1_hwmod,
 142         .clk            = "l4ls_gclk",
 143         .user           = OCP_USER_MPU,
 144 };
 145 
 146 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
 147         .master         = &am33xx_l4_ls_hwmod,
 148         .slave          = &am33xx_epwmss2_hwmod,
 149         .clk            = "l4ls_gclk",
 150         .user           = OCP_USER_MPU,
 151 };
 152 
 153 /* l3s cfg -> gpmc */
 154 struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 155         .master         = &am33xx_l3_s_hwmod,
 156         .slave          = &am33xx_gpmc_hwmod,
 157         .clk            = "l3s_gclk",
 158         .user           = OCP_USER_MPU,
 159 };
 160 
 161 /* l4 ls -> mailbox */
 162 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 163         .master         = &am33xx_l4_ls_hwmod,
 164         .slave          = &am33xx_mailbox_hwmod,
 165         .clk            = "l4ls_gclk",
 166         .user           = OCP_USER_MPU,
 167 };
 168 
 169 /* l4 ls -> spinlock */
 170 struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
 171         .master         = &am33xx_l4_ls_hwmod,
 172         .slave          = &am33xx_spinlock_hwmod,
 173         .clk            = "l4ls_gclk",
 174         .user           = OCP_USER_MPU,
 175 };
 176 
 177 /* l4 ls -> mcasp0 */
 178 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
 179         .master         = &am33xx_l4_ls_hwmod,
 180         .slave          = &am33xx_mcasp0_hwmod,
 181         .clk            = "l4ls_gclk",
 182         .user           = OCP_USER_MPU,
 183 };
 184 
 185 /* l4 ls -> mcasp1 */
 186 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
 187         .master         = &am33xx_l4_ls_hwmod,
 188         .slave          = &am33xx_mcasp1_hwmod,
 189         .clk            = "l4ls_gclk",
 190         .user           = OCP_USER_MPU,
 191 };
 192 
 193 /* l4 ls -> mcspi0 */
 194 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
 195         .master         = &am33xx_l4_ls_hwmod,
 196         .slave          = &am33xx_spi0_hwmod,
 197         .clk            = "l4ls_gclk",
 198         .user           = OCP_USER_MPU,
 199 };
 200 
 201 /* l4 ls -> mcspi1 */
 202 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
 203         .master         = &am33xx_l4_ls_hwmod,
 204         .slave          = &am33xx_spi1_hwmod,
 205         .clk            = "l4ls_gclk",
 206         .user           = OCP_USER_MPU,
 207 };
 208 
 209 /* l4 per -> timer2 */
 210 struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
 211         .master         = &am33xx_l4_ls_hwmod,
 212         .slave          = &am33xx_timer2_hwmod,
 213         .clk            = "l4ls_gclk",
 214         .user           = OCP_USER_MPU,
 215 };
 216 
 217 /* l4 per -> timer3 */
 218 struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
 219         .master         = &am33xx_l4_ls_hwmod,
 220         .slave          = &am33xx_timer3_hwmod,
 221         .clk            = "l4ls_gclk",
 222         .user           = OCP_USER_MPU,
 223 };
 224 
 225 /* l4 per -> timer4 */
 226 struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
 227         .master         = &am33xx_l4_ls_hwmod,
 228         .slave          = &am33xx_timer4_hwmod,
 229         .clk            = "l4ls_gclk",
 230         .user           = OCP_USER_MPU,
 231 };
 232 
 233 /* l4 per -> timer5 */
 234 struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
 235         .master         = &am33xx_l4_ls_hwmod,
 236         .slave          = &am33xx_timer5_hwmod,
 237         .clk            = "l4ls_gclk",
 238         .user           = OCP_USER_MPU,
 239 };
 240 
 241 /* l4 per -> timer6 */
 242 struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
 243         .master         = &am33xx_l4_ls_hwmod,
 244         .slave          = &am33xx_timer6_hwmod,
 245         .clk            = "l4ls_gclk",
 246         .user           = OCP_USER_MPU,
 247 };
 248 
 249 /* l4 per -> timer7 */
 250 struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
 251         .master         = &am33xx_l4_ls_hwmod,
 252         .slave          = &am33xx_timer7_hwmod,
 253         .clk            = "l4ls_gclk",
 254         .user           = OCP_USER_MPU,
 255 };
 256 
 257 /* l3 main -> tpcc */
 258 struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
 259         .master         = &am33xx_l3_main_hwmod,
 260         .slave          = &am33xx_tpcc_hwmod,
 261         .clk            = "l3_gclk",
 262         .user           = OCP_USER_MPU,
 263 };
 264 
 265 /* l3 main -> tpcc0 */
 266 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
 267         .master         = &am33xx_l3_main_hwmod,
 268         .slave          = &am33xx_tptc0_hwmod,
 269         .clk            = "l3_gclk",
 270         .user           = OCP_USER_MPU,
 271 };
 272 
 273 /* l3 main -> tpcc1 */
 274 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
 275         .master         = &am33xx_l3_main_hwmod,
 276         .slave          = &am33xx_tptc1_hwmod,
 277         .clk            = "l3_gclk",
 278         .user           = OCP_USER_MPU,
 279 };
 280 
 281 /* l3 main -> tpcc2 */
 282 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 283         .master         = &am33xx_l3_main_hwmod,
 284         .slave          = &am33xx_tptc2_hwmod,
 285         .clk            = "l3_gclk",
 286         .user           = OCP_USER_MPU,
 287 };
 288 
 289 /* l3 main -> ocmc */
 290 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
 291         .master         = &am33xx_l3_main_hwmod,
 292         .slave          = &am33xx_ocmcram_hwmod,
 293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 294 };
 295 
 296 /* l3 main -> sha0 HIB2 */
 297 struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
 298         .master         = &am33xx_l3_main_hwmod,
 299         .slave          = &am33xx_sha0_hwmod,
 300         .clk            = "sha0_fck",
 301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 302 };
 303 
 304 /* l3 main -> AES0 HIB2 */
 305 struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 306         .master         = &am33xx_l3_main_hwmod,
 307         .slave          = &am33xx_aes0_hwmod,
 308         .clk            = "aes0_fck",
 309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 310 };
 311 
 312 /* l4 per -> rng */
 313 struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
 314         .master         = &am33xx_l4_ls_hwmod,
 315         .slave          = &am33xx_rng_hwmod,
 316         .clk            = "rng_fck",
 317         .user           = OCP_USER_MPU,
 318 };