root/arch/arm/mach-omap2/omap_hwmod_44xx_data.c

DEFINITIONS

1. omap44xx_hwmod_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19 
  20 #include <linux/io.h>
  21 #include <linux/power/smartreflex.h>
  22 
  23 #include <linux/omap-dma.h>
  24 
  25 #include "omap_hwmod.h"
  26 #include "omap_hwmod_common_data.h"
  27 #include "cm1_44xx.h"
  28 #include "cm2_44xx.h"
  29 #include "prm44xx.h"
  30 #include "prm-regbits-44xx.h"
  31 
  32 /* Base offset for all OMAP4 interrupts external to MPUSS */
  33 #define OMAP44XX_IRQ_GIC_START  32
  34 
  35 /* Base offset for all OMAP4 dma requests */
  36 #define OMAP44XX_DMA_REQ_START  1
  37 
  38 /*
  39  * IP blocks
  40  */
  41 
  42 /*
  43  * 'dmm' class
  44  * instance(s): dmm
  45  */
  46 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  47         .name   = "dmm",
  48 };
  49 
  50 /* dmm */
  51 static struct omap_hwmod omap44xx_dmm_hwmod = {
  52         .name           = "dmm",
  53         .class          = &omap44xx_dmm_hwmod_class,
  54         .clkdm_name     = "l3_emif_clkdm",
  55         .prcm = {
  56                 .omap4 = {
  57                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  58                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  59                 },
  60         },
  61 };
  62 
  63 /*
  64  * 'l3' class
  65  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  66  */
  67 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  68         .name   = "l3",
  69 };
  70 
  71 /* l3_instr */
  72 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  73         .name           = "l3_instr",
  74         .class          = &omap44xx_l3_hwmod_class,
  75         .clkdm_name     = "l3_instr_clkdm",
  76         .prcm = {
  77                 .omap4 = {
  78                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  79                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  80                         .modulemode   = MODULEMODE_HWCTRL,
  81                 },
  82         },
  83 };
  84 
  85 /* l3_main_1 */
  86 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  87         .name           = "l3_main_1",
  88         .class          = &omap44xx_l3_hwmod_class,
  89         .clkdm_name     = "l3_1_clkdm",
  90         .prcm = {
  91                 .omap4 = {
  92                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  93                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  94                 },
  95         },
  96 };
  97 
  98 /* l3_main_2 */
  99 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 100         .name           = "l3_main_2",
 101         .class          = &omap44xx_l3_hwmod_class,
 102         .clkdm_name     = "l3_2_clkdm",
 103         .prcm = {
 104                 .omap4 = {
 105                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 106                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 107                 },
 108         },
 109 };
 110 
 111 /* l3_main_3 */
 112 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 113         .name           = "l3_main_3",
 114         .class          = &omap44xx_l3_hwmod_class,
 115         .clkdm_name     = "l3_instr_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 120                         .modulemode   = MODULEMODE_HWCTRL,
 121                 },
 122         },
 123 };
 124 
 125 /*
 126  * 'l4' class
 127  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 128  */
 129 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 130         .name   = "l4",
 131 };
 132 
 133 /* l4_abe */
 134 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 135         .name           = "l4_abe",
 136         .class          = &omap44xx_l4_hwmod_class,
 137         .clkdm_name     = "abe_clkdm",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 141                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 142                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 143                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 144                 },
 145         },
 146 };
 147 
 148 /* l4_cfg */
 149 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 150         .name           = "l4_cfg",
 151         .class          = &omap44xx_l4_hwmod_class,
 152         .clkdm_name     = "l4_cfg_clkdm",
 153         .prcm = {
 154                 .omap4 = {
 155                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 156                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 157                 },
 158         },
 159 };
 160 
 161 /* l4_per */
 162 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 163         .name           = "l4_per",
 164         .class          = &omap44xx_l4_hwmod_class,
 165         .clkdm_name     = "l4_per_clkdm",
 166         .prcm = {
 167                 .omap4 = {
 168                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 169                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 170                 },
 171         },
 172 };
 173 
 174 /* l4_wkup */
 175 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 176         .name           = "l4_wkup",
 177         .class          = &omap44xx_l4_hwmod_class,
 178         .clkdm_name     = "l4_wkup_clkdm",
 179         .prcm = {
 180                 .omap4 = {
 181                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 182                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 183                 },
 184         },
 185 };
 186 
 187 /*
 188  * 'mpu_bus' class
 189  * instance(s): mpu_private
 190  */
 191 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 192         .name   = "mpu_bus",
 193 };
 194 
 195 /* mpu_private */
 196 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 197         .name           = "mpu_private",
 198         .class          = &omap44xx_mpu_bus_hwmod_class,
 199         .clkdm_name     = "mpuss_clkdm",
 200         .prcm = {
 201                 .omap4 = {
 202                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 203                 },
 204         },
 205 };
 206 
 207 /*
 208  * 'ocp_wp_noc' class
 209  * instance(s): ocp_wp_noc
 210  */
 211 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 212         .name   = "ocp_wp_noc",
 213 };
 214 
 215 /* ocp_wp_noc */
 216 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 217         .name           = "ocp_wp_noc",
 218         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 219         .clkdm_name     = "l3_instr_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 224                         .modulemode   = MODULEMODE_HWCTRL,
 225                 },
 226         },
 227 };
 228 
 229 /*
 230  * Modules omap_hwmod structures
 231  *
 232  * The following IPs are excluded for the moment because:
 233  * - They do not need an explicit SW control using omap_hwmod API.
 234  * - They still need to be validated with the driver
 235  *   properly adapted to omap_hwmod / omap_device
 236  *
 237  * usim
 238  */
 239 
 240 /*
 241  * 'aess' class
 242  * audio engine sub system
 243  */
 244 
 245 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 246         .rev_offs       = 0x0000,
 247         .sysc_offs      = 0x0010,
 248         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 249         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 250                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 251                            MSTANDBY_SMART_WKUP),
 252         .sysc_fields    = &omap_hwmod_sysc_type2,
 253 };
 254 
 255 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 256         .name   = "aess",
 257         .sysc   = &omap44xx_aess_sysc,
 258         .enable_preprogram = omap_hwmod_aess_preprogram,
 259 };
 260 
 261 /* aess */
 262 static struct omap_hwmod omap44xx_aess_hwmod = {
 263         .name           = "aess",
 264         .class          = &omap44xx_aess_hwmod_class,
 265         .clkdm_name     = "abe_clkdm",
 266         .main_clk       = "aess_fclk",
 267         .prcm = {
 268                 .omap4 = {
 269                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 270                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 271                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 272                         .modulemode   = MODULEMODE_SWCTRL,
 273                 },
 274         },
 275 };
 276 
 277 /*
 278  * 'counter' class
 279  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 280  */
 281 
 282 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 283         .rev_offs       = 0x0000,
 284         .sysc_offs      = 0x0004,
 285         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 287         .sysc_fields    = &omap_hwmod_sysc_type1,
 288 };
 289 
 290 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 291         .name   = "counter",
 292         .sysc   = &omap44xx_counter_sysc,
 293 };
 294 
 295 /* counter_32k */
 296 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 297         .name           = "counter_32k",
 298         .class          = &omap44xx_counter_hwmod_class,
 299         .clkdm_name     = "l4_wkup_clkdm",
 300         .flags          = HWMOD_SWSUP_SIDLE,
 301         .main_clk       = "sys_32k_ck",
 302         .prcm = {
 303                 .omap4 = {
 304                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 305                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 306                 },
 307         },
 308 };
 309 
 310 /*
 311  * 'ctrl_module' class
 312  * attila core control module + core pad control module + wkup pad control
 313  * module + attila wkup control module
 314  */
 315 
 316 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 317         .rev_offs       = 0x0000,
 318         .sysc_offs      = 0x0010,
 319         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 321                            SIDLE_SMART_WKUP),
 322         .sysc_fields    = &omap_hwmod_sysc_type2,
 323 };
 324 
 325 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 326         .name   = "ctrl_module",
 327         .sysc   = &omap44xx_ctrl_module_sysc,
 328 };
 329 
 330 /* ctrl_module_core */
 331 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 332         .name           = "ctrl_module_core",
 333         .class          = &omap44xx_ctrl_module_hwmod_class,
 334         .clkdm_name     = "l4_cfg_clkdm",
 335         .prcm = {
 336                 .omap4 = {
 337                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 338                 },
 339         },
 340 };
 341 
 342 /* ctrl_module_pad_core */
 343 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 344         .name           = "ctrl_module_pad_core",
 345         .class          = &omap44xx_ctrl_module_hwmod_class,
 346         .clkdm_name     = "l4_cfg_clkdm",
 347         .prcm = {
 348                 .omap4 = {
 349                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 350                 },
 351         },
 352 };
 353 
 354 /* ctrl_module_wkup */
 355 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 356         .name           = "ctrl_module_wkup",
 357         .class          = &omap44xx_ctrl_module_hwmod_class,
 358         .clkdm_name     = "l4_wkup_clkdm",
 359         .prcm = {
 360                 .omap4 = {
 361                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 362                 },
 363         },
 364 };
 365 
 366 /* ctrl_module_pad_wkup */
 367 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 368         .name           = "ctrl_module_pad_wkup",
 369         .class          = &omap44xx_ctrl_module_hwmod_class,
 370         .clkdm_name     = "l4_wkup_clkdm",
 371         .prcm = {
 372                 .omap4 = {
 373                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374                 },
 375         },
 376 };
 377 
 378 /*
 379  * 'debugss' class
 380  * debug and emulation sub system
 381  */
 382 
 383 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 384         .name   = "debugss",
 385 };
 386 
 387 /* debugss */
 388 static struct omap_hwmod omap44xx_debugss_hwmod = {
 389         .name           = "debugss",
 390         .class          = &omap44xx_debugss_hwmod_class,
 391         .clkdm_name     = "emu_sys_clkdm",
 392         .main_clk       = "trace_clk_div_ck",
 393         .prcm = {
 394                 .omap4 = {
 395                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 396                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 397                 },
 398         },
 399 };
 400 
 401 /*
 402  * 'dma' class
 403  * dma controller for data exchange between memory to memory (i.e. internal or
 404  * external memory) and gp peripherals to memory or memory to gp peripherals
 405  */
 406 
 407 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 408         .rev_offs       = 0x0000,
 409         .sysc_offs      = 0x002c,
 410         .syss_offs      = 0x0028,
 411         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 412                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 413                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 414                            SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 416                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 417         .sysc_fields    = &omap_hwmod_sysc_type1,
 418 };
 419 
 420 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 421         .name   = "dma",
 422         .sysc   = &omap44xx_dma_sysc,
 423 };
 424 
 425 /* dma dev_attr */
 426 static struct omap_dma_dev_attr dma_dev_attr = {
 427         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 428                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 429         .lch_count      = 32,
 430 };
 431 
 432 /* dma_system */
 433 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 434         .name           = "dma_system",
 435         .class          = &omap44xx_dma_hwmod_class,
 436         .clkdm_name     = "l3_dma_clkdm",
 437         .main_clk       = "l3_div_ck",
 438         .prcm = {
 439                 .omap4 = {
 440                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 441                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 442                 },
 443         },
 444         .dev_attr       = &dma_dev_attr,
 445 };
 446 
 447 /*
 448  * 'dmic' class
 449  * digital microphone controller
 450  */
 451 
 452 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 453         .rev_offs       = 0x0000,
 454         .sysc_offs      = 0x0010,
 455         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 456                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 457         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 458                            SIDLE_SMART_WKUP),
 459         .sysc_fields    = &omap_hwmod_sysc_type2,
 460 };
 461 
 462 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 463         .name   = "dmic",
 464         .sysc   = &omap44xx_dmic_sysc,
 465 };
 466 
 467 /* dmic */
 468 static struct omap_hwmod omap44xx_dmic_hwmod = {
 469         .name           = "dmic",
 470         .class          = &omap44xx_dmic_hwmod_class,
 471         .clkdm_name     = "abe_clkdm",
 472         .main_clk       = "func_dmic_abe_gfclk",
 473         .prcm = {
 474                 .omap4 = {
 475                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 476                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 477                         .modulemode   = MODULEMODE_SWCTRL,
 478                 },
 479         },
 480 };
 481 
 482 /*
 483  * 'dsp' class
 484  * dsp sub-system
 485  */
 486 
 487 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 488         .name   = "dsp",
 489 };
 490 
 491 /* dsp */
 492 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 493         { .name = "dsp", .rst_shift = 0 },
 494 };
 495 
 496 static struct omap_hwmod omap44xx_dsp_hwmod = {
 497         .name           = "dsp",
 498         .class          = &omap44xx_dsp_hwmod_class,
 499         .clkdm_name     = "tesla_clkdm",
 500         .rst_lines      = omap44xx_dsp_resets,
 501         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 502         .main_clk       = "dpll_iva_m4x2_ck",
 503         .prcm = {
 504                 .omap4 = {
 505                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 506                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 507                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 508                         .modulemode   = MODULEMODE_HWCTRL,
 509                 },
 510         },
 511 };
 512 
 513 /*
 514  * 'dss' class
 515  * display sub-system
 516  */
 517 
 518 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 519         .rev_offs       = 0x0000,
 520         .syss_offs      = 0x0014,
 521         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 522 };
 523 
 524 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 525         .name   = "dss",
 526         .sysc   = &omap44xx_dss_sysc,
 527         .reset  = omap_dss_reset,
 528 };
 529 
 530 /* dss */
 531 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 532         { .role = "sys_clk", .clk = "dss_sys_clk" },
 533         { .role = "tv_clk", .clk = "dss_tv_clk" },
 534         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 535 };
 536 
 537 static struct omap_hwmod omap44xx_dss_hwmod = {
 538         .name           = "dss_core",
 539         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 540         .class          = &omap44xx_dss_hwmod_class,
 541         .clkdm_name     = "l3_dss_clkdm",
 542         .main_clk       = "dss_dss_clk",
 543         .prcm = {
 544                 .omap4 = {
 545                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 546                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 547                         .modulemode   = MODULEMODE_SWCTRL,
 548                 },
 549         },
 550         .opt_clks       = dss_opt_clks,
 551         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 552 };
 553 
 554 /*
 555  * 'dispc' class
 556  * display controller
 557  */
 558 
 559 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 560         .rev_offs       = 0x0000,
 561         .sysc_offs      = 0x0010,
 562         .syss_offs      = 0x0014,
 563         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 564                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 565                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 566                            SYSS_HAS_RESET_STATUS),
 567         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 568                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 569         .sysc_fields    = &omap_hwmod_sysc_type1,
 570 };
 571 
 572 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 573         .name   = "dispc",
 574         .sysc   = &omap44xx_dispc_sysc,
 575 };
 576 
 577 /* dss_dispc */
 578 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 579         .manager_count          = 3,
 580         .has_framedonetv_irq    = 1
 581 };
 582 
 583 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 584         .name           = "dss_dispc",
 585         .class          = &omap44xx_dispc_hwmod_class,
 586         .clkdm_name     = "l3_dss_clkdm",
 587         .main_clk       = "dss_dss_clk",
 588         .prcm = {
 589                 .omap4 = {
 590                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592                 },
 593         },
 594         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 595         .parent_hwmod   = &omap44xx_dss_hwmod,
 596 };
 597 
 598 /*
 599  * 'dsi' class
 600  * display serial interface controller
 601  */
 602 
 603 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 604         .rev_offs       = 0x0000,
 605         .sysc_offs      = 0x0010,
 606         .syss_offs      = 0x0014,
 607         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 608                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 609                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 610         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 611         .sysc_fields    = &omap_hwmod_sysc_type1,
 612 };
 613 
 614 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 615         .name   = "dsi",
 616         .sysc   = &omap44xx_dsi_sysc,
 617 };
 618 
 619 /* dss_dsi1 */
 620 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 621         { .role = "sys_clk", .clk = "dss_sys_clk" },
 622 };
 623 
 624 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 625         .name           = "dss_dsi1",
 626         .class          = &omap44xx_dsi_hwmod_class,
 627         .clkdm_name     = "l3_dss_clkdm",
 628         .main_clk       = "dss_dss_clk",
 629         .prcm = {
 630                 .omap4 = {
 631                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 632                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 633                 },
 634         },
 635         .opt_clks       = dss_dsi1_opt_clks,
 636         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 637         .parent_hwmod   = &omap44xx_dss_hwmod,
 638 };
 639 
 640 /* dss_dsi2 */
 641 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 642         { .role = "sys_clk", .clk = "dss_sys_clk" },
 643 };
 644 
 645 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 646         .name           = "dss_dsi2",
 647         .class          = &omap44xx_dsi_hwmod_class,
 648         .clkdm_name     = "l3_dss_clkdm",
 649         .main_clk       = "dss_dss_clk",
 650         .prcm = {
 651                 .omap4 = {
 652                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 653                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 654                 },
 655         },
 656         .opt_clks       = dss_dsi2_opt_clks,
 657         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 658         .parent_hwmod   = &omap44xx_dss_hwmod,
 659 };
 660 
 661 /*
 662  * 'hdmi' class
 663  * hdmi controller
 664  */
 665 
 666 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 667         .rev_offs       = 0x0000,
 668         .sysc_offs      = 0x0010,
 669         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 670                            SYSC_HAS_SOFTRESET),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 672                            SIDLE_SMART_WKUP),
 673         .sysc_fields    = &omap_hwmod_sysc_type2,
 674 };
 675 
 676 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 677         .name   = "hdmi",
 678         .sysc   = &omap44xx_hdmi_sysc,
 679 };
 680 
 681 /* dss_hdmi */
 682 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 685 };
 686 
 687 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 688         .name           = "dss_hdmi",
 689         .class          = &omap44xx_hdmi_hwmod_class,
 690         .clkdm_name     = "l3_dss_clkdm",
 691         /*
 692          * HDMI audio requires to use no-idle mode. Hence,
 693          * set idle mode by software.
 694          */
 695         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 696         .main_clk       = "dss_48mhz_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_hdmi_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 705         .parent_hwmod   = &omap44xx_dss_hwmod,
 706 };
 707 
 708 /*
 709  * 'rfbi' class
 710  * remote frame buffer interface
 711  */
 712 
 713 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 714         .rev_offs       = 0x0000,
 715         .sysc_offs      = 0x0010,
 716         .syss_offs      = 0x0014,
 717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 718                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722 
 723 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 724         .name   = "rfbi",
 725         .sysc   = &omap44xx_rfbi_sysc,
 726 };
 727 
 728 /* dss_rfbi */
 729 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 730         { .role = "ick", .clk = "l3_div_ck" },
 731 };
 732 
 733 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 734         .name           = "dss_rfbi",
 735         .class          = &omap44xx_rfbi_hwmod_class,
 736         .clkdm_name     = "l3_dss_clkdm",
 737         .main_clk       = "dss_dss_clk",
 738         .prcm = {
 739                 .omap4 = {
 740                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 741                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 742                 },
 743         },
 744         .opt_clks       = dss_rfbi_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 746         .parent_hwmod   = &omap44xx_dss_hwmod,
 747 };
 748 
 749 /*
 750  * 'venc' class
 751  * video encoder
 752  */
 753 
 754 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 755         .name   = "venc",
 756 };
 757 
 758 /* dss_venc */
 759 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 760         { .role = "tv_clk", .clk = "dss_tv_clk" },
 761 };
 762 
 763 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 764         .name           = "dss_venc",
 765         .class          = &omap44xx_venc_hwmod_class,
 766         .clkdm_name     = "l3_dss_clkdm",
 767         .main_clk       = "dss_tv_clk",
 768         .flags          = HWMOD_OPT_CLKS_NEEDED,
 769         .prcm = {
 770                 .omap4 = {
 771                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 772                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 773                 },
 774         },
 775         .parent_hwmod   = &omap44xx_dss_hwmod,
 776         .opt_clks       = dss_venc_opt_clks,
 777         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 778 };
 779 
 780 /* sha0 HIB2 (the 'P' (public) device) */
 781 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 782         .rev_offs       = 0x100,
 783         .sysc_offs      = 0x110,
 784         .syss_offs      = 0x114,
 785         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 786 };
 787 
 788 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 789         .name           = "sham",
 790         .sysc           = &omap44xx_sha0_sysc,
 791 };
 792 
 793 struct omap_hwmod omap44xx_sha0_hwmod = {
 794         .name           = "sham",
 795         .class          = &omap44xx_sha0_hwmod_class,
 796         .clkdm_name     = "l4_secure_clkdm",
 797         .main_clk       = "l3_div_ck",
 798         .prcm           = {
 799                 .omap4 = {
 800                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 801                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 802                         .modulemode   = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806 
 807 /*
 808  * 'elm' class
 809  * bch error location module
 810  */
 811 
 812 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 813         .rev_offs       = 0x0000,
 814         .sysc_offs      = 0x0010,
 815         .syss_offs      = 0x0014,
 816         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 817                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 818                            SYSS_HAS_RESET_STATUS),
 819         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 820         .sysc_fields    = &omap_hwmod_sysc_type1,
 821 };
 822 
 823 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 824         .name   = "elm",
 825         .sysc   = &omap44xx_elm_sysc,
 826 };
 827 
 828 /* elm */
 829 static struct omap_hwmod omap44xx_elm_hwmod = {
 830         .name           = "elm",
 831         .class          = &omap44xx_elm_hwmod_class,
 832         .clkdm_name     = "l4_per_clkdm",
 833         .prcm = {
 834                 .omap4 = {
 835                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 836                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 837                 },
 838         },
 839 };
 840 
 841 /*
 842  * 'emif' class
 843  * external memory interface no1
 844  */
 845 
 846 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 847         .rev_offs       = 0x0000,
 848 };
 849 
 850 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 851         .name   = "emif",
 852         .sysc   = &omap44xx_emif_sysc,
 853 };
 854 
 855 /* emif1 */
 856 static struct omap_hwmod omap44xx_emif1_hwmod = {
 857         .name           = "emif1",
 858         .class          = &omap44xx_emif_hwmod_class,
 859         .clkdm_name     = "l3_emif_clkdm",
 860         .flags          = HWMOD_INIT_NO_IDLE,
 861         .main_clk       = "ddrphy_ck",
 862         .prcm = {
 863                 .omap4 = {
 864                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 865                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 866                         .modulemode   = MODULEMODE_HWCTRL,
 867                 },
 868         },
 869 };
 870 
 871 /* emif2 */
 872 static struct omap_hwmod omap44xx_emif2_hwmod = {
 873         .name           = "emif2",
 874         .class          = &omap44xx_emif_hwmod_class,
 875         .clkdm_name     = "l3_emif_clkdm",
 876         .flags          = HWMOD_INIT_NO_IDLE,
 877         .main_clk       = "ddrphy_ck",
 878         .prcm = {
 879                 .omap4 = {
 880                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 881                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 882                         .modulemode   = MODULEMODE_HWCTRL,
 883                 },
 884         },
 885 };
 886 
 887 /*
 888     Crypto modules AES0/1 belong to:
 889         PD_L4_PER power domain
 890         CD_L4_SEC clock domain
 891         On the L3, the AES modules are mapped to
 892         L3_CLK2: Peripherals and multimedia sub clock domain
 893 */
 894 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 895         .rev_offs       = 0x80,
 896         .sysc_offs      = 0x84,
 897         .syss_offs      = 0x88,
 898         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 899 };
 900 
 901 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 902         .name           = "aes",
 903         .sysc           = &omap44xx_aes_sysc,
 904 };
 905 
 906 static struct omap_hwmod omap44xx_aes1_hwmod = {
 907         .name           = "aes1",
 908         .class          = &omap44xx_aes_hwmod_class,
 909         .clkdm_name     = "l4_secure_clkdm",
 910         .main_clk       = "l3_div_ck",
 911         .prcm           = {
 912                 .omap4  = {
 913                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 914                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 915                         .modulemode     = MODULEMODE_SWCTRL,
 916                 },
 917         },
 918 };
 919 
 920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 921         .master         = &omap44xx_l4_per_hwmod,
 922         .slave          = &omap44xx_aes1_hwmod,
 923         .clk            = "l3_div_ck",
 924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 925 };
 926 
 927 static struct omap_hwmod omap44xx_aes2_hwmod = {
 928         .name           = "aes2",
 929         .class          = &omap44xx_aes_hwmod_class,
 930         .clkdm_name     = "l4_secure_clkdm",
 931         .main_clk       = "l3_div_ck",
 932         .prcm           = {
 933                 .omap4  = {
 934                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 935                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 936                         .modulemode     = MODULEMODE_SWCTRL,
 937                 },
 938         },
 939 };
 940 
 941 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 942         .master         = &omap44xx_l4_per_hwmod,
 943         .slave          = &omap44xx_aes2_hwmod,
 944         .clk            = "l3_div_ck",
 945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 946 };
 947 
 948 /*
 949  * 'des' class for DES3DES module
 950  */
 951 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 952         .rev_offs       = 0x30,
 953         .sysc_offs      = 0x34,
 954         .syss_offs      = 0x38,
 955         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 956 };
 957 
 958 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 959         .name           = "des",
 960         .sysc           = &omap44xx_des_sysc,
 961 };
 962 
 963 static struct omap_hwmod omap44xx_des_hwmod = {
 964         .name           = "des",
 965         .class          = &omap44xx_des_hwmod_class,
 966         .clkdm_name     = "l4_secure_clkdm",
 967         .main_clk       = "l3_div_ck",
 968         .prcm           = {
 969                 .omap4  = {
 970                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 971                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 972                         .modulemode     = MODULEMODE_SWCTRL,
 973                 },
 974         },
 975 };
 976 
 977 struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
 978         .master         = &omap44xx_l3_main_2_hwmod,
 979         .slave          = &omap44xx_des_hwmod,
 980         .clk            = "l3_div_ck",
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983 
 984 /*
 985  * 'fdif' class
 986  * face detection hw accelerator module
 987  */
 988 
 989 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         /*
 993          * FDIF needs 100 OCP clk cycles delay after a softreset before
 994          * accessing sysconfig again.
 995          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 996          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 997          *
 998          * TODO: Indicate errata when available.
 999          */
1000         .srst_udelay    = 2,
1001         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1002                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1003         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1004                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1005         .sysc_fields    = &omap_hwmod_sysc_type2,
1006 };
1007 
1008 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1009         .name   = "fdif",
1010         .sysc   = &omap44xx_fdif_sysc,
1011 };
1012 
1013 /* fdif */
1014 static struct omap_hwmod omap44xx_fdif_hwmod = {
1015         .name           = "fdif",
1016         .class          = &omap44xx_fdif_hwmod_class,
1017         .clkdm_name     = "iss_clkdm",
1018         .main_clk       = "fdif_fck",
1019         .prcm = {
1020                 .omap4 = {
1021                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1022                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1023                         .modulemode   = MODULEMODE_SWCTRL,
1024                 },
1025         },
1026 };
1027 
1028 /*
1029  * 'gpmc' class
1030  * general purpose memory controller
1031  */
1032 
1033 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1034         .rev_offs       = 0x0000,
1035         .sysc_offs      = 0x0010,
1036         .syss_offs      = 0x0014,
1037         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1038                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1039         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1040         .sysc_fields    = &omap_hwmod_sysc_type1,
1041 };
1042 
1043 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1044         .name   = "gpmc",
1045         .sysc   = &omap44xx_gpmc_sysc,
1046 };
1047 
1048 /* gpmc */
1049 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1050         .name           = "gpmc",
1051         .class          = &omap44xx_gpmc_hwmod_class,
1052         .clkdm_name     = "l3_2_clkdm",
1053         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1054         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1055         .prcm = {
1056                 .omap4 = {
1057                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1058                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1059                         .modulemode   = MODULEMODE_HWCTRL,
1060                 },
1061         },
1062 };
1063 
1064 /*
1065  * 'hdq1w' class
1066  * hdq / 1-wire serial interface controller
1067  */
1068 
1069 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1070         .rev_offs       = 0x0000,
1071         .sysc_offs      = 0x0014,
1072         .syss_offs      = 0x0018,
1073         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1074                            SYSS_HAS_RESET_STATUS),
1075         .sysc_fields    = &omap_hwmod_sysc_type1,
1076 };
1077 
1078 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1079         .name   = "hdq1w",
1080         .sysc   = &omap44xx_hdq1w_sysc,
1081 };
1082 
1083 /* hdq1w */
1084 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1085         .name           = "hdq1w",
1086         .class          = &omap44xx_hdq1w_hwmod_class,
1087         .clkdm_name     = "l4_per_clkdm",
1088         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1089         .main_clk       = "func_12m_fclk",
1090         .prcm = {
1091                 .omap4 = {
1092                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1093                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1094                         .modulemode   = MODULEMODE_SWCTRL,
1095                 },
1096         },
1097 };
1098 
1099 /*
1100  * 'hsi' class
1101  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1102  * serial if)
1103  */
1104 
1105 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1106         .rev_offs       = 0x0000,
1107         .sysc_offs      = 0x0010,
1108         .syss_offs      = 0x0014,
1109         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1110                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1111                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1113                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1114                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1115         .sysc_fields    = &omap_hwmod_sysc_type1,
1116 };
1117 
1118 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1119         .name   = "hsi",
1120         .sysc   = &omap44xx_hsi_sysc,
1121 };
1122 
1123 /* hsi */
1124 static struct omap_hwmod omap44xx_hsi_hwmod = {
1125         .name           = "hsi",
1126         .class          = &omap44xx_hsi_hwmod_class,
1127         .clkdm_name     = "l3_init_clkdm",
1128         .main_clk       = "hsi_fck",
1129         .prcm = {
1130                 .omap4 = {
1131                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1132                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1133                         .modulemode   = MODULEMODE_HWCTRL,
1134                 },
1135         },
1136 };
1137 
1138 /*
1139  * 'ipu' class
1140  * imaging processor unit
1141  */
1142 
1143 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1144         .name   = "ipu",
1145 };
1146 
1147 /* ipu */
1148 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1149         { .name = "cpu0", .rst_shift = 0 },
1150         { .name = "cpu1", .rst_shift = 1 },
1151 };
1152 
1153 static struct omap_hwmod omap44xx_ipu_hwmod = {
1154         .name           = "ipu",
1155         .class          = &omap44xx_ipu_hwmod_class,
1156         .clkdm_name     = "ducati_clkdm",
1157         .rst_lines      = omap44xx_ipu_resets,
1158         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1159         .main_clk       = "ducati_clk_mux_ck",
1160         .prcm = {
1161                 .omap4 = {
1162                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1163                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1164                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168 };
1169 
1170 /*
1171  * 'iss' class
1172  * external images sensor pixel data processor
1173  */
1174 
1175 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1176         .rev_offs       = 0x0000,
1177         .sysc_offs      = 0x0010,
1178         /*
1179          * ISS needs 100 OCP clk cycles delay after a softreset before
1180          * accessing sysconfig again.
1181          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1182          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1183          *
1184          * TODO: Indicate errata when available.
1185          */
1186         .srst_udelay    = 2,
1187         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1188                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1189         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1190                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1191                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1192         .sysc_fields    = &omap_hwmod_sysc_type2,
1193 };
1194 
1195 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1196         .name   = "iss",
1197         .sysc   = &omap44xx_iss_sysc,
1198 };
1199 
1200 /* iss */
1201 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1202         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1203 };
1204 
1205 static struct omap_hwmod omap44xx_iss_hwmod = {
1206         .name           = "iss",
1207         .class          = &omap44xx_iss_hwmod_class,
1208         .clkdm_name     = "iss_clkdm",
1209         .main_clk       = "ducati_clk_mux_ck",
1210         .prcm = {
1211                 .omap4 = {
1212                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1213                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1214                         .modulemode   = MODULEMODE_SWCTRL,
1215                 },
1216         },
1217         .opt_clks       = iss_opt_clks,
1218         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1219 };
1220 
1221 /*
1222  * 'iva' class
1223  * multi-standard video encoder/decoder hardware accelerator
1224  */
1225 
1226 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1227         .name   = "iva",
1228 };
1229 
1230 /* iva */
1231 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1232         { .name = "seq0", .rst_shift = 0 },
1233         { .name = "seq1", .rst_shift = 1 },
1234         { .name = "logic", .rst_shift = 2 },
1235 };
1236 
1237 static struct omap_hwmod omap44xx_iva_hwmod = {
1238         .name           = "iva",
1239         .class          = &omap44xx_iva_hwmod_class,
1240         .clkdm_name     = "ivahd_clkdm",
1241         .rst_lines      = omap44xx_iva_resets,
1242         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1243         .main_clk       = "dpll_iva_m5x2_ck",
1244         .prcm = {
1245                 .omap4 = {
1246                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1247                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1248                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1249                         .modulemode   = MODULEMODE_HWCTRL,
1250                 },
1251         },
1252 };
1253 
1254 /*
1255  * 'kbd' class
1256  * keyboard controller
1257  */
1258 
1259 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1260         .rev_offs       = 0x0000,
1261         .sysc_offs      = 0x0010,
1262         .syss_offs      = 0x0014,
1263         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1264                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1265                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1266                            SYSS_HAS_RESET_STATUS),
1267         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1268         .sysc_fields    = &omap_hwmod_sysc_type1,
1269 };
1270 
1271 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1272         .name   = "kbd",
1273         .sysc   = &omap44xx_kbd_sysc,
1274 };
1275 
1276 /* kbd */
1277 static struct omap_hwmod omap44xx_kbd_hwmod = {
1278         .name           = "kbd",
1279         .class          = &omap44xx_kbd_hwmod_class,
1280         .clkdm_name     = "l4_wkup_clkdm",
1281         .main_clk       = "sys_32k_ck",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_SWCTRL,
1287                 },
1288         },
1289 };
1290 
1291 /*
1292  * 'mailbox' class
1293  * mailbox module allowing communication between the on-chip processors using a
1294  * queued mailbox-interrupt mechanism.
1295  */
1296 
1297 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1298         .rev_offs       = 0x0000,
1299         .sysc_offs      = 0x0010,
1300         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1301                            SYSC_HAS_SOFTRESET),
1302         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1303         .sysc_fields    = &omap_hwmod_sysc_type2,
1304 };
1305 
1306 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1307         .name   = "mailbox",
1308         .sysc   = &omap44xx_mailbox_sysc,
1309 };
1310 
1311 /* mailbox */
1312 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1313         .name           = "mailbox",
1314         .class          = &omap44xx_mailbox_hwmod_class,
1315         .clkdm_name     = "l4_cfg_clkdm",
1316         .prcm = {
1317                 .omap4 = {
1318                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1319                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1320                 },
1321         },
1322 };
1323 
1324 /*
1325  * 'mcasp' class
1326  * multi-channel audio serial port controller
1327  */
1328 
1329 /* The IP is not compliant to type1 / type2 scheme */
1330 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1331         .rev_offs       = 0,
1332         .sysc_offs      = 0x0004,
1333         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1335                            SIDLE_SMART_WKUP),
1336         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1337 };
1338 
1339 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1340         .name   = "mcasp",
1341         .sysc   = &omap44xx_mcasp_sysc,
1342 };
1343 
1344 /* mcasp */
1345 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1346         .name           = "mcasp",
1347         .class          = &omap44xx_mcasp_hwmod_class,
1348         .clkdm_name     = "abe_clkdm",
1349         .main_clk       = "func_mcasp_abe_gfclk",
1350         .prcm = {
1351                 .omap4 = {
1352                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1353                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1354                         .modulemode   = MODULEMODE_SWCTRL,
1355                 },
1356         },
1357 };
1358 
1359 /*
1360  * 'mcbsp' class
1361  * multi channel buffered serial port controller
1362  */
1363 
1364 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1365         .rev_offs       = -ENODEV,
1366         .sysc_offs      = 0x008c,
1367         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1368                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1369         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1370         .sysc_fields    = &omap_hwmod_sysc_type1,
1371 };
1372 
1373 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1374         .name   = "mcbsp",
1375         .sysc   = &omap44xx_mcbsp_sysc,
1376 };
1377 
1378 /* mcbsp1 */
1379 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1380         { .role = "pad_fck", .clk = "pad_clks_ck" },
1381         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1382 };
1383 
1384 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1385         .name           = "mcbsp1",
1386         .class          = &omap44xx_mcbsp_hwmod_class,
1387         .clkdm_name     = "abe_clkdm",
1388         .main_clk       = "func_mcbsp1_gfclk",
1389         .prcm = {
1390                 .omap4 = {
1391                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1392                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1393                         .modulemode   = MODULEMODE_SWCTRL,
1394                 },
1395         },
1396         .opt_clks       = mcbsp1_opt_clks,
1397         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1398 };
1399 
1400 /* mcbsp2 */
1401 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1402         { .role = "pad_fck", .clk = "pad_clks_ck" },
1403         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1404 };
1405 
1406 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1407         .name           = "mcbsp2",
1408         .class          = &omap44xx_mcbsp_hwmod_class,
1409         .clkdm_name     = "abe_clkdm",
1410         .main_clk       = "func_mcbsp2_gfclk",
1411         .prcm = {
1412                 .omap4 = {
1413                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1414                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1415                         .modulemode   = MODULEMODE_SWCTRL,
1416                 },
1417         },
1418         .opt_clks       = mcbsp2_opt_clks,
1419         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
1420 };
1421 
1422 /* mcbsp3 */
1423 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1424         { .role = "pad_fck", .clk = "pad_clks_ck" },
1425         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1426 };
1427 
1428 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1429         .name           = "mcbsp3",
1430         .class          = &omap44xx_mcbsp_hwmod_class,
1431         .clkdm_name     = "abe_clkdm",
1432         .main_clk       = "func_mcbsp3_gfclk",
1433         .prcm = {
1434                 .omap4 = {
1435                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1436                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1437                         .modulemode   = MODULEMODE_SWCTRL,
1438                 },
1439         },
1440         .opt_clks       = mcbsp3_opt_clks,
1441         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
1442 };
1443 
1444 /* mcbsp4 */
1445 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1446         { .role = "pad_fck", .clk = "pad_clks_ck" },
1447         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1448 };
1449 
1450 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1451         .name           = "mcbsp4",
1452         .class          = &omap44xx_mcbsp_hwmod_class,
1453         .clkdm_name     = "l4_per_clkdm",
1454         .main_clk       = "per_mcbsp4_gfclk",
1455         .prcm = {
1456                 .omap4 = {
1457                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1458                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1459                         .modulemode   = MODULEMODE_SWCTRL,
1460                 },
1461         },
1462         .opt_clks       = mcbsp4_opt_clks,
1463         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
1464 };
1465 
1466 /*
1467  * 'mcpdm' class
1468  * multi channel pdm controller (proprietary interface with phoenix power
1469  * ic)
1470  */
1471 
1472 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1473         .rev_offs       = 0x0000,
1474         .sysc_offs      = 0x0010,
1475         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1476                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1477         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1478                            SIDLE_SMART_WKUP),
1479         .sysc_fields    = &omap_hwmod_sysc_type2,
1480 };
1481 
1482 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1483         .name   = "mcpdm",
1484         .sysc   = &omap44xx_mcpdm_sysc,
1485 };
1486 
1487 /* mcpdm */
1488 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1489         .name           = "mcpdm",
1490         .class          = &omap44xx_mcpdm_hwmod_class,
1491         .clkdm_name     = "abe_clkdm",
1492         /*
1493          * It's suspected that the McPDM requires an off-chip main
1494          * functional clock, controlled via I2C.  This IP block is
1495          * currently reset very early during boot, before I2C is
1496          * available, so it doesn't seem that we have any choice in
1497          * the kernel other than to avoid resetting it.
1498          *
1499          * Also, McPDM needs to be configured to NO_IDLE mode when it
1500          * is in used otherwise vital clocks will be gated which
1501          * results 'slow motion' audio playback.
1502          */
1503         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1504         .main_clk       = "pad_clks_ck",
1505         .prcm = {
1506                 .omap4 = {
1507                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1508                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1509                         .modulemode   = MODULEMODE_SWCTRL,
1510                 },
1511         },
1512 };
1513 
1514 /*
1515  * 'mmu' class
1516  * The memory management unit performs virtual to physical address translation
1517  * for its requestors.
1518  */
1519 
1520 static struct omap_hwmod_class_sysconfig mmu_sysc = {
1521         .rev_offs       = 0x000,
1522         .sysc_offs      = 0x010,
1523         .syss_offs      = 0x014,
1524         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1525                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1526         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1527         .sysc_fields    = &omap_hwmod_sysc_type1,
1528 };
1529 
1530 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
1531         .name = "mmu",
1532         .sysc = &mmu_sysc,
1533 };
1534 
1535 /* mmu ipu */
1536 
1537 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
1538 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
1539         { .name = "mmu_cache", .rst_shift = 2 },
1540 };
1541 
1542 /* l3_main_2 -> mmu_ipu */
1543 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
1544         .master         = &omap44xx_l3_main_2_hwmod,
1545         .slave          = &omap44xx_mmu_ipu_hwmod,
1546         .clk            = "l3_div_ck",
1547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1548 };
1549 
1550 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
1551         .name           = "mmu_ipu",
1552         .class          = &omap44xx_mmu_hwmod_class,
1553         .clkdm_name     = "ducati_clkdm",
1554         .rst_lines      = omap44xx_mmu_ipu_resets,
1555         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
1556         .main_clk       = "ducati_clk_mux_ck",
1557         .prcm = {
1558                 .omap4 = {
1559                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1560                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1561                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1562                         .modulemode   = MODULEMODE_HWCTRL,
1563                 },
1564         },
1565 };
1566 
1567 /* mmu dsp */
1568 
1569 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
1570 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
1571         { .name = "mmu_cache", .rst_shift = 1 },
1572 };
1573 
1574 /* l4_cfg -> dsp */
1575 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
1576         .master         = &omap44xx_l4_cfg_hwmod,
1577         .slave          = &omap44xx_mmu_dsp_hwmod,
1578         .clk            = "l4_div_ck",
1579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1580 };
1581 
1582 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
1583         .name           = "mmu_dsp",
1584         .class          = &omap44xx_mmu_hwmod_class,
1585         .clkdm_name     = "tesla_clkdm",
1586         .rst_lines      = omap44xx_mmu_dsp_resets,
1587         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
1588         .main_clk       = "dpll_iva_m4x2_ck",
1589         .prcm = {
1590                 .omap4 = {
1591                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1592                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1593                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1594                         .modulemode   = MODULEMODE_HWCTRL,
1595                 },
1596         },
1597 };
1598 
1599 /*
1600  * 'mpu' class
1601  * mpu sub-system
1602  */
1603 
1604 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1605         .name   = "mpu",
1606 };
1607 
1608 /* mpu */
1609 static struct omap_hwmod omap44xx_mpu_hwmod = {
1610         .name           = "mpu",
1611         .class          = &omap44xx_mpu_hwmod_class,
1612         .clkdm_name     = "mpuss_clkdm",
1613         .flags          = HWMOD_INIT_NO_IDLE,
1614         .main_clk       = "dpll_mpu_m2_ck",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1619                 },
1620         },
1621 };
1622 
1623 /*
1624  * 'ocmc_ram' class
1625  * top-level core on-chip ram
1626  */
1627 
1628 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1629         .name   = "ocmc_ram",
1630 };
1631 
1632 /* ocmc_ram */
1633 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1634         .name           = "ocmc_ram",
1635         .class          = &omap44xx_ocmc_ram_hwmod_class,
1636         .clkdm_name     = "l3_2_clkdm",
1637         .prcm = {
1638                 .omap4 = {
1639                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1640                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1641                 },
1642         },
1643 };
1644 
1645 /*
1646  * 'ocp2scp' class
1647  * bridge to transform ocp interface protocol to scp (serial control port)
1648  * protocol
1649  */
1650 
1651 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
1652         .rev_offs       = 0x0000,
1653         .sysc_offs      = 0x0010,
1654         .syss_offs      = 0x0014,
1655         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1656                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1657         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1658         .sysc_fields    = &omap_hwmod_sysc_type1,
1659 };
1660 
1661 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
1662         .name   = "ocp2scp",
1663         .sysc   = &omap44xx_ocp2scp_sysc,
1664 };
1665 
1666 /* ocp2scp_usb_phy */
1667 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
1668         .name           = "ocp2scp_usb_phy",
1669         .class          = &omap44xx_ocp2scp_hwmod_class,
1670         .clkdm_name     = "l3_init_clkdm",
1671         /*
1672          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
1673          * block as an "optional clock," and normally should never be
1674          * specified as the main_clk for an OMAP IP block.  However it
1675          * turns out that this clock is actually the main clock for
1676          * the ocp2scp_usb_phy IP block:
1677          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
1678          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
1679          * to be the best workaround.
1680          */
1681         .main_clk       = "ocp2scp_usb_phy_phy_48m",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
1685                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
1686                         .modulemode   = MODULEMODE_HWCTRL,
1687                 },
1688         },
1689 };
1690 
1691 /*
1692  * 'prcm' class
1693  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1694  * + clock manager 1 (in always on power domain) + local prm in mpu
1695  */
1696 
1697 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1698         .name   = "prcm",
1699 };
1700 
1701 /* prcm_mpu */
1702 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1703         .name           = "prcm_mpu",
1704         .class          = &omap44xx_prcm_hwmod_class,
1705         .clkdm_name     = "l4_wkup_clkdm",
1706         .flags          = HWMOD_NO_IDLEST,
1707         .prcm = {
1708                 .omap4 = {
1709                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1710                 },
1711         },
1712 };
1713 
1714 /* cm_core_aon */
1715 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1716         .name           = "cm_core_aon",
1717         .class          = &omap44xx_prcm_hwmod_class,
1718         .flags          = HWMOD_NO_IDLEST,
1719         .prcm = {
1720                 .omap4 = {
1721                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1722                 },
1723         },
1724 };
1725 
1726 /* cm_core */
1727 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1728         .name           = "cm_core",
1729         .class          = &omap44xx_prcm_hwmod_class,
1730         .flags          = HWMOD_NO_IDLEST,
1731         .prcm = {
1732                 .omap4 = {
1733                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1734                 },
1735         },
1736 };
1737 
1738 /* prm */
1739 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1740         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1741         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1742 };
1743 
1744 static struct omap_hwmod omap44xx_prm_hwmod = {
1745         .name           = "prm",
1746         .class          = &omap44xx_prcm_hwmod_class,
1747         .rst_lines      = omap44xx_prm_resets,
1748         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1749 };
1750 
1751 /*
1752  * 'scrm' class
1753  * system clock and reset manager
1754  */
1755 
1756 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1757         .name   = "scrm",
1758 };
1759 
1760 /* scrm */
1761 static struct omap_hwmod omap44xx_scrm_hwmod = {
1762         .name           = "scrm",
1763         .class          = &omap44xx_scrm_hwmod_class,
1764         .clkdm_name     = "l4_wkup_clkdm",
1765         .prcm = {
1766                 .omap4 = {
1767                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1768                 },
1769         },
1770 };
1771 
1772 /*
1773  * 'sl2if' class
1774  * shared level 2 memory interface
1775  */
1776 
1777 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1778         .name   = "sl2if",
1779 };
1780 
1781 /* sl2if */
1782 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1783         .name           = "sl2if",
1784         .class          = &omap44xx_sl2if_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .prcm = {
1787                 .omap4 = {
1788                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1789                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1790                         .modulemode   = MODULEMODE_HWCTRL,
1791                 },
1792         },
1793 };
1794 
1795 /*
1796  * 'slimbus' class
1797  * bidirectional, multi-drop, multi-channel two-line serial interface between
1798  * the device and external components
1799  */
1800 
1801 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
1802         .rev_offs       = 0x0000,
1803         .sysc_offs      = 0x0010,
1804         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1805                            SYSC_HAS_SOFTRESET),
1806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1807                            SIDLE_SMART_WKUP),
1808         .sysc_fields    = &omap_hwmod_sysc_type2,
1809 };
1810 
1811 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
1812         .name   = "slimbus",
1813         .sysc   = &omap44xx_slimbus_sysc,
1814 };
1815 
1816 /* slimbus1 */
1817 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
1818         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
1819         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
1820         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
1821         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
1822 };
1823 
1824 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
1825         .name           = "slimbus1",
1826         .class          = &omap44xx_slimbus_hwmod_class,
1827         .clkdm_name     = "abe_clkdm",
1828         .prcm = {
1829                 .omap4 = {
1830                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
1831                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
1832                         .modulemode   = MODULEMODE_SWCTRL,
1833                 },
1834         },
1835         .opt_clks       = slimbus1_opt_clks,
1836         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
1837 };
1838 
1839 /* slimbus2 */
1840 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
1841         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
1842         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
1843         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
1844 };
1845 
1846 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
1847         .name           = "slimbus2",
1848         .class          = &omap44xx_slimbus_hwmod_class,
1849         .clkdm_name     = "l4_per_clkdm",
1850         .prcm = {
1851                 .omap4 = {
1852                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
1853                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
1854                         .modulemode   = MODULEMODE_SWCTRL,
1855                 },
1856         },
1857         .opt_clks       = slimbus2_opt_clks,
1858         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
1859 };
1860 
1861 /*
1862  * 'smartreflex' class
1863  * smartreflex module (monitor silicon performance and outputs a measure of
1864  * performance error)
1865  */
1866 
1867 /* The IP is not compliant to type1 / type2 scheme */
1868 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1869         .rev_offs       = -ENODEV,
1870         .sysc_offs      = 0x0038,
1871         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1873                            SIDLE_SMART_WKUP),
1874         .sysc_fields    = &omap36xx_sr_sysc_fields,
1875 };
1876 
1877 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1878         .name   = "smartreflex",
1879         .sysc   = &omap44xx_smartreflex_sysc,
1880 };
1881 
1882 /* smartreflex_core */
1883 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1884         .sensor_voltdm_name   = "core",
1885 };
1886 
1887 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1888         .name           = "smartreflex_core",
1889         .class          = &omap44xx_smartreflex_hwmod_class,
1890         .clkdm_name     = "l4_ao_clkdm",
1891 
1892         .main_clk       = "smartreflex_core_fck",
1893         .prcm = {
1894                 .omap4 = {
1895                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1896                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
1897                         .modulemode   = MODULEMODE_SWCTRL,
1898                 },
1899         },
1900         .dev_attr       = &smartreflex_core_dev_attr,
1901 };
1902 
1903 /* smartreflex_iva */
1904 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
1905         .sensor_voltdm_name     = "iva",
1906 };
1907 
1908 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1909         .name           = "smartreflex_iva",
1910         .class          = &omap44xx_smartreflex_hwmod_class,
1911         .clkdm_name     = "l4_ao_clkdm",
1912         .main_clk       = "smartreflex_iva_fck",
1913         .prcm = {
1914                 .omap4 = {
1915                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1916                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
1917                         .modulemode   = MODULEMODE_SWCTRL,
1918                 },
1919         },
1920         .dev_attr       = &smartreflex_iva_dev_attr,
1921 };
1922 
1923 /* smartreflex_mpu */
1924 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1925         .sensor_voltdm_name     = "mpu",
1926 };
1927 
1928 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1929         .name           = "smartreflex_mpu",
1930         .class          = &omap44xx_smartreflex_hwmod_class,
1931         .clkdm_name     = "l4_ao_clkdm",
1932         .main_clk       = "smartreflex_mpu_fck",
1933         .prcm = {
1934                 .omap4 = {
1935                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1936                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
1937                         .modulemode   = MODULEMODE_SWCTRL,
1938                 },
1939         },
1940         .dev_attr       = &smartreflex_mpu_dev_attr,
1941 };
1942 
1943 /*
1944  * 'spinlock' class
1945  * spinlock provides hardware assistance for synchronizing the processes
1946  * running on multiple processors
1947  */
1948 
1949 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
1950         .rev_offs       = 0x0000,
1951         .sysc_offs      = 0x0010,
1952         .syss_offs      = 0x0014,
1953         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1954                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1955                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1957         .sysc_fields    = &omap_hwmod_sysc_type1,
1958 };
1959 
1960 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
1961         .name   = "spinlock",
1962         .sysc   = &omap44xx_spinlock_sysc,
1963 };
1964 
1965 /* spinlock */
1966 static struct omap_hwmod omap44xx_spinlock_hwmod = {
1967         .name           = "spinlock",
1968         .class          = &omap44xx_spinlock_hwmod_class,
1969         .clkdm_name     = "l4_cfg_clkdm",
1970         .prcm = {
1971                 .omap4 = {
1972                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
1973                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
1974                 },
1975         },
1976 };
1977 
1978 /*
1979  * 'timer' class
1980  * general purpose timer module with accurate 1ms tick
1981  * This class contains several variants: ['timer_1ms', 'timer']
1982  */
1983 
1984 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1985         .rev_offs       = 0x0000,
1986         .sysc_offs      = 0x0010,
1987         .syss_offs      = 0x0014,
1988         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1989                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1990                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1991                            SYSS_HAS_RESET_STATUS),
1992         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1993         .sysc_fields    = &omap_hwmod_sysc_type1,
1994 };
1995 
1996 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1997         .name   = "timer",
1998         .sysc   = &omap44xx_timer_1ms_sysc,
1999 };
2000 
2001 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2002         .rev_offs       = 0x0000,
2003         .sysc_offs      = 0x0010,
2004         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2005                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2007                            SIDLE_SMART_WKUP),
2008         .sysc_fields    = &omap_hwmod_sysc_type2,
2009 };
2010 
2011 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2012         .name   = "timer",
2013         .sysc   = &omap44xx_timer_sysc,
2014 };
2015 
2016 /* timer1 */
2017 static struct omap_hwmod omap44xx_timer1_hwmod = {
2018         .name           = "timer1",
2019         .class          = &omap44xx_timer_1ms_hwmod_class,
2020         .clkdm_name     = "l4_wkup_clkdm",
2021         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2022         .main_clk       = "dmt1_clk_mux",
2023         .prcm = {
2024                 .omap4 = {
2025                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2026                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2027                         .modulemode   = MODULEMODE_SWCTRL,
2028                 },
2029         },
2030 };
2031 
2032 /* timer2 */
2033 static struct omap_hwmod omap44xx_timer2_hwmod = {
2034         .name           = "timer2",
2035         .class          = &omap44xx_timer_1ms_hwmod_class,
2036         .clkdm_name     = "l4_per_clkdm",
2037         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2038         .main_clk       = "cm2_dm2_mux",
2039         .prcm = {
2040                 .omap4 = {
2041                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2042                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2043                         .modulemode   = MODULEMODE_SWCTRL,
2044                 },
2045         },
2046 };
2047 
2048 /* timer3 */
2049 static struct omap_hwmod omap44xx_timer3_hwmod = {
2050         .name           = "timer3",
2051         .class          = &omap44xx_timer_hwmod_class,
2052         .clkdm_name     = "l4_per_clkdm",
2053         .main_clk       = "cm2_dm3_mux",
2054         .prcm = {
2055                 .omap4 = {
2056                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2057                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2058                         .modulemode   = MODULEMODE_SWCTRL,
2059                 },
2060         },
2061 };
2062 
2063 /* timer4 */
2064 static struct omap_hwmod omap44xx_timer4_hwmod = {
2065         .name           = "timer4",
2066         .class          = &omap44xx_timer_hwmod_class,
2067         .clkdm_name     = "l4_per_clkdm",
2068         .main_clk       = "cm2_dm4_mux",
2069         .prcm = {
2070                 .omap4 = {
2071                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2072                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2073                         .modulemode   = MODULEMODE_SWCTRL,
2074                 },
2075         },
2076 };
2077 
2078 /* timer5 */
2079 static struct omap_hwmod omap44xx_timer5_hwmod = {
2080         .name           = "timer5",
2081         .class          = &omap44xx_timer_hwmod_class,
2082         .clkdm_name     = "abe_clkdm",
2083         .main_clk       = "timer5_sync_mux",
2084         .prcm = {
2085                 .omap4 = {
2086                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2087                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2088                         .modulemode   = MODULEMODE_SWCTRL,
2089                 },
2090         },
2091 };
2092 
2093 /* timer6 */
2094 static struct omap_hwmod omap44xx_timer6_hwmod = {
2095         .name           = "timer6",
2096         .class          = &omap44xx_timer_hwmod_class,
2097         .clkdm_name     = "abe_clkdm",
2098         .main_clk       = "timer6_sync_mux",
2099         .prcm = {
2100                 .omap4 = {
2101                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2102                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2103                         .modulemode   = MODULEMODE_SWCTRL,
2104                 },
2105         },
2106 };
2107 
2108 /* timer7 */
2109 static struct omap_hwmod omap44xx_timer7_hwmod = {
2110         .name           = "timer7",
2111         .class          = &omap44xx_timer_hwmod_class,
2112         .clkdm_name     = "abe_clkdm",
2113         .main_clk       = "timer7_sync_mux",
2114         .prcm = {
2115                 .omap4 = {
2116                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2117                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2118                         .modulemode   = MODULEMODE_SWCTRL,
2119                 },
2120         },
2121 };
2122 
2123 /* timer8 */
2124 static struct omap_hwmod omap44xx_timer8_hwmod = {
2125         .name           = "timer8",
2126         .class          = &omap44xx_timer_hwmod_class,
2127         .clkdm_name     = "abe_clkdm",
2128         .main_clk       = "timer8_sync_mux",
2129         .prcm = {
2130                 .omap4 = {
2131                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2132                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2133                         .modulemode   = MODULEMODE_SWCTRL,
2134                 },
2135         },
2136 };
2137 
2138 /* timer9 */
2139 static struct omap_hwmod omap44xx_timer9_hwmod = {
2140         .name           = "timer9",
2141         .class          = &omap44xx_timer_hwmod_class,
2142         .clkdm_name     = "l4_per_clkdm",
2143         .main_clk       = "cm2_dm9_mux",
2144         .prcm = {
2145                 .omap4 = {
2146                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2147                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2148                         .modulemode   = MODULEMODE_SWCTRL,
2149                 },
2150         },
2151 };
2152 
2153 /* timer10 */
2154 static struct omap_hwmod omap44xx_timer10_hwmod = {
2155         .name           = "timer10",
2156         .class          = &omap44xx_timer_1ms_hwmod_class,
2157         .clkdm_name     = "l4_per_clkdm",
2158         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2159         .main_clk       = "cm2_dm10_mux",
2160         .prcm = {
2161                 .omap4 = {
2162                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2163                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2164                         .modulemode   = MODULEMODE_SWCTRL,
2165                 },
2166         },
2167 };
2168 
2169 /* timer11 */
2170 static struct omap_hwmod omap44xx_timer11_hwmod = {
2171         .name           = "timer11",
2172         .class          = &omap44xx_timer_hwmod_class,
2173         .clkdm_name     = "l4_per_clkdm",
2174         .main_clk       = "cm2_dm11_mux",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2178                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2179                         .modulemode   = MODULEMODE_SWCTRL,
2180                 },
2181         },
2182 };
2183 
2184 /*
2185  * 'usb_host_fs' class
2186  * full-speed usb host controller
2187  */
2188 
2189 /* The IP is not compliant to type1 / type2 scheme */
2190 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2191         .rev_offs       = 0x0000,
2192         .sysc_offs      = 0x0210,
2193         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2194                            SYSC_HAS_SOFTRESET),
2195         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2196                            SIDLE_SMART_WKUP),
2197         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
2198 };
2199 
2200 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2201         .name   = "usb_host_fs",
2202         .sysc   = &omap44xx_usb_host_fs_sysc,
2203 };
2204 
2205 /* usb_host_fs */
2206 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2207         .name           = "usb_host_fs",
2208         .class          = &omap44xx_usb_host_fs_hwmod_class,
2209         .clkdm_name     = "l3_init_clkdm",
2210         .main_clk       = "usb_host_fs_fck",
2211         .prcm = {
2212                 .omap4 = {
2213                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2214                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2215                         .modulemode   = MODULEMODE_SWCTRL,
2216                 },
2217         },
2218 };
2219 
2220 /*
2221  * 'usb_host_hs' class
2222  * high-speed multi-port usb host controller
2223  */
2224 
2225 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2226         .rev_offs       = 0x0000,
2227         .sysc_offs      = 0x0010,
2228         .syss_offs      = 0x0014,
2229         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2230                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2231         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2232                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2233                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2234         .sysc_fields    = &omap_hwmod_sysc_type2,
2235 };
2236 
2237 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2238         .name   = "usb_host_hs",
2239         .sysc   = &omap44xx_usb_host_hs_sysc,
2240 };
2241 
2242 /* usb_host_hs */
2243 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2244         .name           = "usb_host_hs",
2245         .class          = &omap44xx_usb_host_hs_hwmod_class,
2246         .clkdm_name     = "l3_init_clkdm",
2247         .main_clk       = "usb_host_hs_fck",
2248         .prcm = {
2249                 .omap4 = {
2250                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2251                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2252                         .modulemode   = MODULEMODE_SWCTRL,
2253                 },
2254         },
2255 
2256         /*
2257          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2258          * id: i660
2259          *
2260          * Description:
2261          * In the following configuration :
2262          * - USBHOST module is set to smart-idle mode
2263          * - PRCM asserts idle_req to the USBHOST module ( This typically
2264          *   happens when the system is going to a low power mode : all ports
2265          *   have been suspended, the master part of the USBHOST module has
2266          *   entered the standby state, and SW has cut the functional clocks)
2267          * - an USBHOST interrupt occurs before the module is able to answer
2268          *   idle_ack, typically a remote wakeup IRQ.
2269          * Then the USB HOST module will enter a deadlock situation where it
2270          * is no more accessible nor functional.
2271          *
2272          * Workaround:
2273          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2274          */
2275 
2276         /*
2277          * Errata: USB host EHCI may stall when entering smart-standby mode
2278          * Id: i571
2279          *
2280          * Description:
2281          * When the USBHOST module is set to smart-standby mode, and when it is
2282          * ready to enter the standby state (i.e. all ports are suspended and
2283          * all attached devices are in suspend mode), then it can wrongly assert
2284          * the Mstandby signal too early while there are still some residual OCP
2285          * transactions ongoing. If this condition occurs, the internal state
2286          * machine may go to an undefined state and the USB link may be stuck
2287          * upon the next resume.
2288          *
2289          * Workaround:
2290          * Don't use smart standby; use only force standby,
2291          * hence HWMOD_SWSUP_MSTANDBY
2292          */
2293 
2294         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2295 };
2296 
2297 /*
2298  * 'usb_otg_hs' class
2299  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2300  */
2301 
2302 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2303         .rev_offs       = 0x0400,
2304         .sysc_offs      = 0x0404,
2305         .syss_offs      = 0x0408,
2306         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2307                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2308                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2309         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2310                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2311                            MSTANDBY_SMART),
2312         .sysc_fields    = &omap_hwmod_sysc_type1,
2313 };
2314 
2315 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2316         .name   = "usb_otg_hs",
2317         .sysc   = &omap44xx_usb_otg_hs_sysc,
2318 };
2319 
2320 /* usb_otg_hs */
2321 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2322         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
2323 };
2324 
2325 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2326         .name           = "usb_otg_hs",
2327         .class          = &omap44xx_usb_otg_hs_hwmod_class,
2328         .clkdm_name     = "l3_init_clkdm",
2329         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2330         .main_clk       = "usb_otg_hs_ick",
2331         .prcm = {
2332                 .omap4 = {
2333                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2334                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2335                         .modulemode   = MODULEMODE_HWCTRL,
2336                 },
2337         },
2338         .opt_clks       = usb_otg_hs_opt_clks,
2339         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
2340 };
2341 
2342 /*
2343  * 'usb_tll_hs' class
2344  * usb_tll_hs module is the adapter on the usb_host_hs ports
2345  */
2346 
2347 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2348         .rev_offs       = 0x0000,
2349         .sysc_offs      = 0x0010,
2350         .syss_offs      = 0x0014,
2351         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2352                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2353                            SYSC_HAS_AUTOIDLE),
2354         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2355         .sysc_fields    = &omap_hwmod_sysc_type1,
2356 };
2357 
2358 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2359         .name   = "usb_tll_hs",
2360         .sysc   = &omap44xx_usb_tll_hs_sysc,
2361 };
2362 
2363 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2364         .name           = "usb_tll_hs",
2365         .class          = &omap44xx_usb_tll_hs_hwmod_class,
2366         .clkdm_name     = "l3_init_clkdm",
2367         .main_clk       = "usb_tll_hs_ick",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2371                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2372                         .modulemode   = MODULEMODE_HWCTRL,
2373                 },
2374         },
2375 };
2376 
2377 /*
2378  * interfaces
2379  */
2380 
2381 /* l3_main_1 -> dmm */
2382 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2383         .master         = &omap44xx_l3_main_1_hwmod,
2384         .slave          = &omap44xx_dmm_hwmod,
2385         .clk            = "l3_div_ck",
2386         .user           = OCP_USER_SDMA,
2387 };
2388 
2389 /* mpu -> dmm */
2390 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2391         .master         = &omap44xx_mpu_hwmod,
2392         .slave          = &omap44xx_dmm_hwmod,
2393         .clk            = "l3_div_ck",
2394         .user           = OCP_USER_MPU,
2395 };
2396 
2397 /* iva -> l3_instr */
2398 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2399         .master         = &omap44xx_iva_hwmod,
2400         .slave          = &omap44xx_l3_instr_hwmod,
2401         .clk            = "l3_div_ck",
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404 
2405 /* l3_main_3 -> l3_instr */
2406 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2407         .master         = &omap44xx_l3_main_3_hwmod,
2408         .slave          = &omap44xx_l3_instr_hwmod,
2409         .clk            = "l3_div_ck",
2410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2411 };
2412 
2413 /* ocp_wp_noc -> l3_instr */
2414 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
2415         .master         = &omap44xx_ocp_wp_noc_hwmod,
2416         .slave          = &omap44xx_l3_instr_hwmod,
2417         .clk            = "l3_div_ck",
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420 
2421 /* dsp -> l3_main_1 */
2422 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2423         .master         = &omap44xx_dsp_hwmod,
2424         .slave          = &omap44xx_l3_main_1_hwmod,
2425         .clk            = "l3_div_ck",
2426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428 
2429 /* dss -> l3_main_1 */
2430 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2431         .master         = &omap44xx_dss_hwmod,
2432         .slave          = &omap44xx_l3_main_1_hwmod,
2433         .clk            = "l3_div_ck",
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436 
2437 /* l3_main_2 -> l3_main_1 */
2438 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2439         .master         = &omap44xx_l3_main_2_hwmod,
2440         .slave          = &omap44xx_l3_main_1_hwmod,
2441         .clk            = "l3_div_ck",
2442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444 
2445 /* l4_cfg -> l3_main_1 */
2446 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2447         .master         = &omap44xx_l4_cfg_hwmod,
2448         .slave          = &omap44xx_l3_main_1_hwmod,
2449         .clk            = "l4_div_ck",
2450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2451 };
2452 
2453 /* mpu -> l3_main_1 */
2454 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2455         .master         = &omap44xx_mpu_hwmod,
2456         .slave          = &omap44xx_l3_main_1_hwmod,
2457         .clk            = "l3_div_ck",
2458         .user           = OCP_USER_MPU,
2459 };
2460 
2461 /* debugss -> l3_main_2 */
2462 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
2463         .master         = &omap44xx_debugss_hwmod,
2464         .slave          = &omap44xx_l3_main_2_hwmod,
2465         .clk            = "dbgclk_mux_ck",
2466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2467 };
2468 
2469 /* dma_system -> l3_main_2 */
2470 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
2471         .master         = &omap44xx_dma_system_hwmod,
2472         .slave          = &omap44xx_l3_main_2_hwmod,
2473         .clk            = "l3_div_ck",
2474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2475 };
2476 
2477 /* fdif -> l3_main_2 */
2478 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
2479         .master         = &omap44xx_fdif_hwmod,
2480         .slave          = &omap44xx_l3_main_2_hwmod,
2481         .clk            = "l3_div_ck",
2482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2483 };
2484 
2485 /* hsi -> l3_main_2 */
2486 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2487         .master         = &omap44xx_hsi_hwmod,
2488         .slave          = &omap44xx_l3_main_2_hwmod,
2489         .clk            = "l3_div_ck",
2490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2491 };
2492 
2493 /* ipu -> l3_main_2 */
2494 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2495         .master         = &omap44xx_ipu_hwmod,
2496         .slave          = &omap44xx_l3_main_2_hwmod,
2497         .clk            = "l3_div_ck",
2498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2499 };
2500 
2501 /* iss -> l3_main_2 */
2502 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
2503         .master         = &omap44xx_iss_hwmod,
2504         .slave          = &omap44xx_l3_main_2_hwmod,
2505         .clk            = "l3_div_ck",
2506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2507 };
2508 
2509 /* iva -> l3_main_2 */
2510 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
2511         .master         = &omap44xx_iva_hwmod,
2512         .slave          = &omap44xx_l3_main_2_hwmod,
2513         .clk            = "l3_div_ck",
2514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2515 };
2516 
2517 /* l3_main_1 -> l3_main_2 */
2518 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
2519         .master         = &omap44xx_l3_main_1_hwmod,
2520         .slave          = &omap44xx_l3_main_2_hwmod,
2521         .clk            = "l3_div_ck",
2522         .user           = OCP_USER_MPU,
2523 };
2524 
2525 /* l4_cfg -> l3_main_2 */
2526 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
2527         .master         = &omap44xx_l4_cfg_hwmod,
2528         .slave          = &omap44xx_l3_main_2_hwmod,
2529         .clk            = "l4_div_ck",
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532 
2533 /* usb_host_fs -> l3_main_2 */
2534 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
2535         .master         = &omap44xx_usb_host_fs_hwmod,
2536         .slave          = &omap44xx_l3_main_2_hwmod,
2537         .clk            = "l3_div_ck",
2538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2539 };
2540 
2541 /* usb_host_hs -> l3_main_2 */
2542 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
2543         .master         = &omap44xx_usb_host_hs_hwmod,
2544         .slave          = &omap44xx_l3_main_2_hwmod,
2545         .clk            = "l3_div_ck",
2546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2547 };
2548 
2549 /* usb_otg_hs -> l3_main_2 */
2550 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
2551         .master         = &omap44xx_usb_otg_hs_hwmod,
2552         .slave          = &omap44xx_l3_main_2_hwmod,
2553         .clk            = "l3_div_ck",
2554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556 
2557 /* l3_main_1 -> l3_main_3 */
2558 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
2559         .master         = &omap44xx_l3_main_1_hwmod,
2560         .slave          = &omap44xx_l3_main_3_hwmod,
2561         .clk            = "l3_div_ck",
2562         .user           = OCP_USER_MPU,
2563 };
2564 
2565 /* l3_main_2 -> l3_main_3 */
2566 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
2567         .master         = &omap44xx_l3_main_2_hwmod,
2568         .slave          = &omap44xx_l3_main_3_hwmod,
2569         .clk            = "l3_div_ck",
2570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2571 };
2572 
2573 /* l4_cfg -> l3_main_3 */
2574 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
2575         .master         = &omap44xx_l4_cfg_hwmod,
2576         .slave          = &omap44xx_l3_main_3_hwmod,
2577         .clk            = "l4_div_ck",
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580 
2581 /* aess -> l4_abe */
2582 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
2583         .master         = &omap44xx_aess_hwmod,
2584         .slave          = &omap44xx_l4_abe_hwmod,
2585         .clk            = "ocp_abe_iclk",
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588 
2589 /* dsp -> l4_abe */
2590 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
2591         .master         = &omap44xx_dsp_hwmod,
2592         .slave          = &omap44xx_l4_abe_hwmod,
2593         .clk            = "ocp_abe_iclk",
2594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596 
2597 /* l3_main_1 -> l4_abe */
2598 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
2599         .master         = &omap44xx_l3_main_1_hwmod,
2600         .slave          = &omap44xx_l4_abe_hwmod,
2601         .clk            = "l3_div_ck",
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604 
2605 /* mpu -> l4_abe */
2606 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
2607         .master         = &omap44xx_mpu_hwmod,
2608         .slave          = &omap44xx_l4_abe_hwmod,
2609         .clk            = "ocp_abe_iclk",
2610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2611 };
2612 
2613 /* l3_main_1 -> l4_cfg */
2614 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
2615         .master         = &omap44xx_l3_main_1_hwmod,
2616         .slave          = &omap44xx_l4_cfg_hwmod,
2617         .clk            = "l3_div_ck",
2618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620 
2621 /* l3_main_2 -> l4_per */
2622 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
2623         .master         = &omap44xx_l3_main_2_hwmod,
2624         .slave          = &omap44xx_l4_per_hwmod,
2625         .clk            = "l3_div_ck",
2626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2627 };
2628 
2629 /* l4_cfg -> l4_wkup */
2630 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
2631         .master         = &omap44xx_l4_cfg_hwmod,
2632         .slave          = &omap44xx_l4_wkup_hwmod,
2633         .clk            = "l4_div_ck",
2634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2635 };
2636 
2637 /* mpu -> mpu_private */
2638 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
2639         .master         = &omap44xx_mpu_hwmod,
2640         .slave          = &omap44xx_mpu_private_hwmod,
2641         .clk            = "l3_div_ck",
2642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2643 };
2644 
2645 /* l4_cfg -> ocp_wp_noc */
2646 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
2647         .master         = &omap44xx_l4_cfg_hwmod,
2648         .slave          = &omap44xx_ocp_wp_noc_hwmod,
2649         .clk            = "l4_div_ck",
2650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652 
2653 /* l4_abe -> aess */
2654 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
2655         .master         = &omap44xx_l4_abe_hwmod,
2656         .slave          = &omap44xx_aess_hwmod,
2657         .clk            = "ocp_abe_iclk",
2658         .user           = OCP_USER_MPU,
2659 };
2660 
2661 /* l4_abe -> aess (dma) */
2662 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
2663         .master         = &omap44xx_l4_abe_hwmod,
2664         .slave          = &omap44xx_aess_hwmod,
2665         .clk            = "ocp_abe_iclk",
2666         .user           = OCP_USER_SDMA,
2667 };
2668 
2669 /* l4_wkup -> counter_32k */
2670 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
2671         .master         = &omap44xx_l4_wkup_hwmod,
2672         .slave          = &omap44xx_counter_32k_hwmod,
2673         .clk            = "l4_wkup_clk_mux_ck",
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676 
2677 /* l4_cfg -> ctrl_module_core */
2678 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
2679         .master         = &omap44xx_l4_cfg_hwmod,
2680         .slave          = &omap44xx_ctrl_module_core_hwmod,
2681         .clk            = "l4_div_ck",
2682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2683 };
2684 
2685 /* l4_cfg -> ctrl_module_pad_core */
2686 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
2687         .master         = &omap44xx_l4_cfg_hwmod,
2688         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
2689         .clk            = "l4_div_ck",
2690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692 
2693 /* l4_wkup -> ctrl_module_wkup */
2694 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
2695         .master         = &omap44xx_l4_wkup_hwmod,
2696         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
2697         .clk            = "l4_wkup_clk_mux_ck",
2698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2699 };
2700 
2701 /* l4_wkup -> ctrl_module_pad_wkup */
2702 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
2703         .master         = &omap44xx_l4_wkup_hwmod,
2704         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
2705         .clk            = "l4_wkup_clk_mux_ck",
2706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2707 };
2708 
2709 /* l3_instr -> debugss */
2710 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
2711         .master         = &omap44xx_l3_instr_hwmod,
2712         .slave          = &omap44xx_debugss_hwmod,
2713         .clk            = "l3_div_ck",
2714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716 
2717 /* l4_cfg -> dma_system */
2718 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
2719         .master         = &omap44xx_l4_cfg_hwmod,
2720         .slave          = &omap44xx_dma_system_hwmod,
2721         .clk            = "l4_div_ck",
2722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2724 
2725 /* l4_abe -> dmic */
2726 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
2727         .master         = &omap44xx_l4_abe_hwmod,
2728         .slave          = &omap44xx_dmic_hwmod,
2729         .clk            = "ocp_abe_iclk",
2730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732 
2733 /* dsp -> iva */
2734 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
2735         .master         = &omap44xx_dsp_hwmod,
2736         .slave          = &omap44xx_iva_hwmod,
2737         .clk            = "dpll_iva_m5x2_ck",
2738         .user           = OCP_USER_DSP,
2739 };
2740 
2741 /* dsp -> sl2if */
2742 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
2743         .master         = &omap44xx_dsp_hwmod,
2744         .slave          = &omap44xx_sl2if_hwmod,
2745         .clk            = "dpll_iva_m5x2_ck",
2746         .user           = OCP_USER_DSP,
2747 };
2748 
2749 /* l4_cfg -> dsp */
2750 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
2751         .master         = &omap44xx_l4_cfg_hwmod,
2752         .slave          = &omap44xx_dsp_hwmod,
2753         .clk            = "l4_div_ck",
2754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2755 };
2756 
2757 /* l3_main_2 -> dss */
2758 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
2759         .master         = &omap44xx_l3_main_2_hwmod,
2760         .slave          = &omap44xx_dss_hwmod,
2761         .clk            = "l3_div_ck",
2762         .user           = OCP_USER_SDMA,
2763 };
2764 
2765 /* l4_per -> dss */
2766 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
2767         .master         = &omap44xx_l4_per_hwmod,
2768         .slave          = &omap44xx_dss_hwmod,
2769         .clk            = "l4_div_ck",
2770         .user           = OCP_USER_MPU,
2771 };
2772 
2773 /* l3_main_2 -> dss_dispc */
2774 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
2775         .master         = &omap44xx_l3_main_2_hwmod,
2776         .slave          = &omap44xx_dss_dispc_hwmod,
2777         .clk            = "l3_div_ck",
2778         .user           = OCP_USER_SDMA,
2779 };
2780 
2781 /* l4_per -> dss_dispc */
2782 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
2783         .master         = &omap44xx_l4_per_hwmod,
2784         .slave          = &omap44xx_dss_dispc_hwmod,
2785         .clk            = "l4_div_ck",
2786         .user           = OCP_USER_MPU,
2787 };
2788 
2789 /* l3_main_2 -> dss_dsi1 */
2790 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
2791         .master         = &omap44xx_l3_main_2_hwmod,
2792         .slave          = &omap44xx_dss_dsi1_hwmod,
2793         .clk            = "l3_div_ck",
2794         .user           = OCP_USER_SDMA,
2795 };
2796 
2797 /* l4_per -> dss_dsi1 */
2798 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
2799         .master         = &omap44xx_l4_per_hwmod,
2800         .slave          = &omap44xx_dss_dsi1_hwmod,
2801         .clk            = "l4_div_ck",
2802         .user           = OCP_USER_MPU,
2803 };
2804 
2805 /* l3_main_2 -> dss_dsi2 */
2806 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
2807         .master         = &omap44xx_l3_main_2_hwmod,
2808         .slave          = &omap44xx_dss_dsi2_hwmod,
2809         .clk            = "l3_div_ck",
2810         .user           = OCP_USER_SDMA,
2811 };
2812 
2813 /* l4_per -> dss_dsi2 */
2814 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
2815         .master         = &omap44xx_l4_per_hwmod,
2816         .slave          = &omap44xx_dss_dsi2_hwmod,
2817         .clk            = "l4_div_ck",
2818         .user           = OCP_USER_MPU,
2819 };
2820 
2821 /* l3_main_2 -> dss_hdmi */
2822 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
2823         .master         = &omap44xx_l3_main_2_hwmod,
2824         .slave          = &omap44xx_dss_hdmi_hwmod,
2825         .clk            = "l3_div_ck",
2826         .user           = OCP_USER_SDMA,
2827 };
2828 
2829 /* l4_per -> dss_hdmi */
2830 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
2831         .master         = &omap44xx_l4_per_hwmod,
2832         .slave          = &omap44xx_dss_hdmi_hwmod,
2833         .clk            = "l4_div_ck",
2834         .user           = OCP_USER_MPU,
2835 };
2836 
2837 /* l3_main_2 -> dss_rfbi */
2838 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
2839         .master         = &omap44xx_l3_main_2_hwmod,
2840         .slave          = &omap44xx_dss_rfbi_hwmod,
2841         .clk            = "l3_div_ck",
2842         .user           = OCP_USER_SDMA,
2843 };
2844 
2845 /* l4_per -> dss_rfbi */
2846 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
2847         .master         = &omap44xx_l4_per_hwmod,
2848         .slave          = &omap44xx_dss_rfbi_hwmod,
2849         .clk            = "l4_div_ck",
2850         .user           = OCP_USER_MPU,
2851 };
2852 
2853 /* l3_main_2 -> dss_venc */
2854 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
2855         .master         = &omap44xx_l3_main_2_hwmod,
2856         .slave          = &omap44xx_dss_venc_hwmod,
2857         .clk            = "l3_div_ck",
2858         .user           = OCP_USER_SDMA,
2859 };
2860 
2861 /* l4_per -> dss_venc */
2862 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
2863         .master         = &omap44xx_l4_per_hwmod,
2864         .slave          = &omap44xx_dss_venc_hwmod,
2865         .clk            = "l4_div_ck",
2866         .user           = OCP_USER_MPU,
2867 };
2868 
2869 /* l3_main_2 -> sham */
2870 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
2871         .master         = &omap44xx_l3_main_2_hwmod,
2872         .slave          = &omap44xx_sha0_hwmod,
2873         .clk            = "l3_div_ck",
2874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2875 };
2876 
2877 /* l4_per -> elm */
2878 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
2879         .master         = &omap44xx_l4_per_hwmod,
2880         .slave          = &omap44xx_elm_hwmod,
2881         .clk            = "l4_div_ck",
2882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2883 };
2884 
2885 /* l4_cfg -> fdif */
2886 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
2887         .master         = &omap44xx_l4_cfg_hwmod,
2888         .slave          = &omap44xx_fdif_hwmod,
2889         .clk            = "l4_div_ck",
2890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2891 };
2892 
2893 /* l3_main_2 -> gpmc */
2894 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
2895         .master         = &omap44xx_l3_main_2_hwmod,
2896         .slave          = &omap44xx_gpmc_hwmod,
2897         .clk            = "l3_div_ck",
2898         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2899 };
2900 
2901 /* l4_per -> hdq1w */
2902 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
2903         .master         = &omap44xx_l4_per_hwmod,
2904         .slave          = &omap44xx_hdq1w_hwmod,
2905         .clk            = "l4_div_ck",
2906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2907 };
2908 
2909 /* l4_cfg -> hsi */
2910 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2911         .master         = &omap44xx_l4_cfg_hwmod,
2912         .slave          = &omap44xx_hsi_hwmod,
2913         .clk            = "l4_div_ck",
2914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2915 };
2916 
2917 /* l3_main_2 -> ipu */
2918 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2919         .master         = &omap44xx_l3_main_2_hwmod,
2920         .slave          = &omap44xx_ipu_hwmod,
2921         .clk            = "l3_div_ck",
2922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2923 };
2924 
2925 /* l3_main_2 -> iss */
2926 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2927         .master         = &omap44xx_l3_main_2_hwmod,
2928         .slave          = &omap44xx_iss_hwmod,
2929         .clk            = "l3_div_ck",
2930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2931 };
2932 
2933 /* iva -> sl2if */
2934 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
2935         .master         = &omap44xx_iva_hwmod,
2936         .slave          = &omap44xx_sl2if_hwmod,
2937         .clk            = "dpll_iva_m5x2_ck",
2938         .user           = OCP_USER_IVA,
2939 };
2940 
2941 /* l3_main_2 -> iva */
2942 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2943         .master         = &omap44xx_l3_main_2_hwmod,
2944         .slave          = &omap44xx_iva_hwmod,
2945         .clk            = "l3_div_ck",
2946         .user           = OCP_USER_MPU,
2947 };
2948 
2949 /* l4_wkup -> kbd */
2950 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2951         .master         = &omap44xx_l4_wkup_hwmod,
2952         .slave          = &omap44xx_kbd_hwmod,
2953         .clk            = "l4_wkup_clk_mux_ck",
2954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956 
2957 /* l4_cfg -> mailbox */
2958 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2959         .master         = &omap44xx_l4_cfg_hwmod,
2960         .slave          = &omap44xx_mailbox_hwmod,
2961         .clk            = "l4_div_ck",
2962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2963 };
2964 
2965 /* l4_abe -> mcasp */
2966 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
2967         .master         = &omap44xx_l4_abe_hwmod,
2968         .slave          = &omap44xx_mcasp_hwmod,
2969         .clk            = "ocp_abe_iclk",
2970         .user           = OCP_USER_MPU,
2971 };
2972 
2973 /* l4_abe -> mcasp (dma) */
2974 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
2975         .master         = &omap44xx_l4_abe_hwmod,
2976         .slave          = &omap44xx_mcasp_hwmod,
2977         .clk            = "ocp_abe_iclk",
2978         .user           = OCP_USER_SDMA,
2979 };
2980 
2981 /* l4_abe -> mcbsp1 */
2982 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2983         .master         = &omap44xx_l4_abe_hwmod,
2984         .slave          = &omap44xx_mcbsp1_hwmod,
2985         .clk            = "ocp_abe_iclk",
2986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2987 };
2988 
2989 /* l4_abe -> mcbsp2 */
2990 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2991         .master         = &omap44xx_l4_abe_hwmod,
2992         .slave          = &omap44xx_mcbsp2_hwmod,
2993         .clk            = "ocp_abe_iclk",
2994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2995 };
2996 
2997 /* l4_abe -> mcbsp3 */
2998 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2999         .master         = &omap44xx_l4_abe_hwmod,
3000         .slave          = &omap44xx_mcbsp3_hwmod,
3001         .clk            = "ocp_abe_iclk",
3002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3003 };
3004 
3005 /* l4_per -> mcbsp4 */
3006 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3007         .master         = &omap44xx_l4_per_hwmod,
3008         .slave          = &omap44xx_mcbsp4_hwmod,
3009         .clk            = "l4_div_ck",
3010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3011 };
3012 
3013 /* l4_abe -> mcpdm */
3014 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3015         .master         = &omap44xx_l4_abe_hwmod,
3016         .slave          = &omap44xx_mcpdm_hwmod,
3017         .clk            = "ocp_abe_iclk",
3018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3019 };
3020 
3021 /* l3_main_2 -> ocmc_ram */
3022 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3023         .master         = &omap44xx_l3_main_2_hwmod,
3024         .slave          = &omap44xx_ocmc_ram_hwmod,
3025         .clk            = "l3_div_ck",
3026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3027 };
3028 
3029 /* l4_cfg -> ocp2scp_usb_phy */
3030 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3031         .master         = &omap44xx_l4_cfg_hwmod,
3032         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
3033         .clk            = "l4_div_ck",
3034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3035 };
3036 
3037 /* mpu_private -> prcm_mpu */
3038 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
3039         .master         = &omap44xx_mpu_private_hwmod,
3040         .slave          = &omap44xx_prcm_mpu_hwmod,
3041         .clk            = "l3_div_ck",
3042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3043 };
3044 
3045 /* l4_wkup -> cm_core_aon */
3046 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
3047         .master         = &omap44xx_l4_wkup_hwmod,
3048         .slave          = &omap44xx_cm_core_aon_hwmod,
3049         .clk            = "l4_wkup_clk_mux_ck",
3050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3051 };
3052 
3053 /* l4_cfg -> cm_core */
3054 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
3055         .master         = &omap44xx_l4_cfg_hwmod,
3056         .slave          = &omap44xx_cm_core_hwmod,
3057         .clk            = "l4_div_ck",
3058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3059 };
3060 
3061 /* l4_wkup -> prm */
3062 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
3063         .master         = &omap44xx_l4_wkup_hwmod,
3064         .slave          = &omap44xx_prm_hwmod,
3065         .clk            = "l4_wkup_clk_mux_ck",
3066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3067 };
3068 
3069 /* l4_wkup -> scrm */
3070 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
3071         .master         = &omap44xx_l4_wkup_hwmod,
3072         .slave          = &omap44xx_scrm_hwmod,
3073         .clk            = "l4_wkup_clk_mux_ck",
3074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3075 };
3076 
3077 /* l3_main_2 -> sl2if */
3078 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
3079         .master         = &omap44xx_l3_main_2_hwmod,
3080         .slave          = &omap44xx_sl2if_hwmod,
3081         .clk            = "l3_div_ck",
3082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3083 };
3084 
3085 /* l4_abe -> slimbus1 */
3086 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3087         .master         = &omap44xx_l4_abe_hwmod,
3088         .slave          = &omap44xx_slimbus1_hwmod,
3089         .clk            = "ocp_abe_iclk",
3090         .user           = OCP_USER_MPU,
3091 };
3092 
3093 /* l4_abe -> slimbus1 (dma) */
3094 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
3095         .master         = &omap44xx_l4_abe_hwmod,
3096         .slave          = &omap44xx_slimbus1_hwmod,
3097         .clk            = "ocp_abe_iclk",
3098         .user           = OCP_USER_SDMA,
3099 };
3100 
3101 /* l4_per -> slimbus2 */
3102 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
3103         .master         = &omap44xx_l4_per_hwmod,
3104         .slave          = &omap44xx_slimbus2_hwmod,
3105         .clk            = "l4_div_ck",
3106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3107 };
3108 
3109 /* l4_cfg -> smartreflex_core */
3110 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3111         .master         = &omap44xx_l4_cfg_hwmod,
3112         .slave          = &omap44xx_smartreflex_core_hwmod,
3113         .clk            = "l4_div_ck",
3114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3115 };
3116 
3117 /* l4_cfg -> smartreflex_iva */
3118 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3119         .master         = &omap44xx_l4_cfg_hwmod,
3120         .slave          = &omap44xx_smartreflex_iva_hwmod,
3121         .clk            = "l4_div_ck",
3122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3123 };
3124 
3125 /* l4_cfg -> smartreflex_mpu */
3126 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3127         .master         = &omap44xx_l4_cfg_hwmod,
3128         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3129         .clk            = "l4_div_ck",
3130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3131 };
3132 
3133 /* l4_cfg -> spinlock */
3134 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3135         .master         = &omap44xx_l4_cfg_hwmod,
3136         .slave          = &omap44xx_spinlock_hwmod,
3137         .clk            = "l4_div_ck",
3138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3139 };
3140 
3141 /* l4_wkup -> timer1 */
3142 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3143         .master         = &omap44xx_l4_wkup_hwmod,
3144         .slave          = &omap44xx_timer1_hwmod,
3145         .clk            = "l4_wkup_clk_mux_ck",
3146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3147 };
3148 
3149 /* l4_per -> timer2 */
3150 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3151         .master         = &omap44xx_l4_per_hwmod,
3152         .slave          = &omap44xx_timer2_hwmod,
3153         .clk            = "l4_div_ck",
3154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3155 };
3156 
3157 /* l4_per -> timer3 */
3158 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
3159         .master         = &omap44xx_l4_per_hwmod,
3160         .slave          = &omap44xx_timer3_hwmod,
3161         .clk            = "l4_div_ck",
3162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3163 };
3164 
3165 /* l4_per -> timer4 */
3166 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
3167         .master         = &omap44xx_l4_per_hwmod,
3168         .slave          = &omap44xx_timer4_hwmod,
3169         .clk            = "l4_div_ck",
3170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3171 };
3172 
3173 /* l4_abe -> timer5 */
3174 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
3175         .master         = &omap44xx_l4_abe_hwmod,
3176         .slave          = &omap44xx_timer5_hwmod,
3177         .clk            = "ocp_abe_iclk",
3178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3179 };
3180 
3181 /* l4_abe -> timer6 */
3182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
3183         .master         = &omap44xx_l4_abe_hwmod,
3184         .slave          = &omap44xx_timer6_hwmod,
3185         .clk            = "ocp_abe_iclk",
3186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3187 };
3188 
3189 /* l4_abe -> timer7 */
3190 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
3191         .master         = &omap44xx_l4_abe_hwmod,
3192         .slave          = &omap44xx_timer7_hwmod,
3193         .clk            = "ocp_abe_iclk",
3194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3195 };
3196 
3197 /* l4_abe -> timer8 */
3198 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3199         .master         = &omap44xx_l4_abe_hwmod,
3200         .slave          = &omap44xx_timer8_hwmod,
3201         .clk            = "ocp_abe_iclk",
3202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3203 };
3204 
3205 /* l4_per -> timer9 */
3206 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
3207         .master         = &omap44xx_l4_per_hwmod,
3208         .slave          = &omap44xx_timer9_hwmod,
3209         .clk            = "l4_div_ck",
3210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3212 
3213 /* l4_per -> timer10 */
3214 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
3215         .master         = &omap44xx_l4_per_hwmod,
3216         .slave          = &omap44xx_timer10_hwmod,
3217         .clk            = "l4_div_ck",
3218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3219 };
3220 
3221 /* l4_per -> timer11 */
3222 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
3223         .master         = &omap44xx_l4_per_hwmod,
3224         .slave          = &omap44xx_timer11_hwmod,
3225         .clk            = "l4_div_ck",
3226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3227 };
3228 
3229 /* l4_cfg -> usb_host_fs */
3230 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
3231         .master         = &omap44xx_l4_cfg_hwmod,
3232         .slave          = &omap44xx_usb_host_fs_hwmod,
3233         .clk            = "l4_div_ck",
3234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3235 };
3236 
3237 /* l4_cfg -> usb_host_hs */
3238 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
3239         .master         = &omap44xx_l4_cfg_hwmod,
3240         .slave          = &omap44xx_usb_host_hs_hwmod,
3241         .clk            = "l4_div_ck",
3242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3243 };
3244 
3245 /* l4_cfg -> usb_otg_hs */
3246 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
3247         .master         = &omap44xx_l4_cfg_hwmod,
3248         .slave          = &omap44xx_usb_otg_hs_hwmod,
3249         .clk            = "l4_div_ck",
3250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3251 };
3252 
3253 /* l4_cfg -> usb_tll_hs */
3254 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
3255         .master         = &omap44xx_l4_cfg_hwmod,
3256         .slave          = &omap44xx_usb_tll_hs_hwmod,
3257         .clk            = "l4_div_ck",
3258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3259 };
3260 
3261 /* mpu -> emif1 */
3262 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
3263         .master         = &omap44xx_mpu_hwmod,
3264         .slave          = &omap44xx_emif1_hwmod,
3265         .clk            = "l3_div_ck",
3266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3267 };
3268 
3269 /* mpu -> emif2 */
3270 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
3271         .master         = &omap44xx_mpu_hwmod,
3272         .slave          = &omap44xx_emif2_hwmod,
3273         .clk            = "l3_div_ck",
3274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276 
3277 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
3278         &omap44xx_l3_main_1__dmm,
3279         &omap44xx_mpu__dmm,
3280         &omap44xx_iva__l3_instr,
3281         &omap44xx_l3_main_3__l3_instr,
3282         &omap44xx_ocp_wp_noc__l3_instr,
3283         &omap44xx_dsp__l3_main_1,
3284         &omap44xx_dss__l3_main_1,
3285         &omap44xx_l3_main_2__l3_main_1,
3286         &omap44xx_l4_cfg__l3_main_1,
3287         &omap44xx_mpu__l3_main_1,
3288         &omap44xx_debugss__l3_main_2,
3289         &omap44xx_dma_system__l3_main_2,
3290         &omap44xx_fdif__l3_main_2,
3291         &omap44xx_hsi__l3_main_2,
3292         &omap44xx_ipu__l3_main_2,
3293         &omap44xx_iss__l3_main_2,
3294         &omap44xx_iva__l3_main_2,
3295         &omap44xx_l3_main_1__l3_main_2,
3296         &omap44xx_l4_cfg__l3_main_2,
3297         /* &omap44xx_usb_host_fs__l3_main_2, */
3298         &omap44xx_usb_host_hs__l3_main_2,
3299         &omap44xx_usb_otg_hs__l3_main_2,
3300         &omap44xx_l3_main_1__l3_main_3,
3301         &omap44xx_l3_main_2__l3_main_3,
3302         &omap44xx_l4_cfg__l3_main_3,
3303         &omap44xx_aess__l4_abe,
3304         &omap44xx_dsp__l4_abe,
3305         &omap44xx_l3_main_1__l4_abe,
3306         &omap44xx_mpu__l4_abe,
3307         &omap44xx_l3_main_1__l4_cfg,
3308         &omap44xx_l3_main_2__l4_per,
3309         &omap44xx_l4_cfg__l4_wkup,
3310         &omap44xx_mpu__mpu_private,
3311         &omap44xx_l4_cfg__ocp_wp_noc,
3312         &omap44xx_l4_abe__aess,
3313         &omap44xx_l4_abe__aess_dma,
3314         &omap44xx_l4_wkup__counter_32k,
3315         &omap44xx_l4_cfg__ctrl_module_core,
3316         &omap44xx_l4_cfg__ctrl_module_pad_core,
3317         &omap44xx_l4_wkup__ctrl_module_wkup,
3318         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
3319         &omap44xx_l3_instr__debugss,
3320         &omap44xx_l4_cfg__dma_system,
3321         &omap44xx_l4_abe__dmic,
3322         &omap44xx_dsp__iva,
3323         /* &omap44xx_dsp__sl2if, */
3324         &omap44xx_l4_cfg__dsp,
3325         &omap44xx_l3_main_2__dss,
3326         &omap44xx_l4_per__dss,
3327         &omap44xx_l3_main_2__dss_dispc,
3328         &omap44xx_l4_per__dss_dispc,
3329         &omap44xx_l3_main_2__dss_dsi1,
3330         &omap44xx_l4_per__dss_dsi1,
3331         &omap44xx_l3_main_2__dss_dsi2,
3332         &omap44xx_l4_per__dss_dsi2,
3333         &omap44xx_l3_main_2__dss_hdmi,
3334         &omap44xx_l4_per__dss_hdmi,
3335         &omap44xx_l3_main_2__dss_rfbi,
3336         &omap44xx_l4_per__dss_rfbi,
3337         &omap44xx_l3_main_2__dss_venc,
3338         &omap44xx_l4_per__dss_venc,
3339         &omap44xx_l4_per__elm,
3340         &omap44xx_l4_cfg__fdif,
3341         &omap44xx_l3_main_2__gpmc,
3342         &omap44xx_l4_per__hdq1w,
3343         &omap44xx_l4_cfg__hsi,
3344         &omap44xx_l3_main_2__ipu,
3345         &omap44xx_l3_main_2__iss,
3346         /* &omap44xx_iva__sl2if, */
3347         &omap44xx_l3_main_2__iva,
3348         &omap44xx_l4_wkup__kbd,
3349         &omap44xx_l4_cfg__mailbox,
3350         &omap44xx_l4_abe__mcasp,
3351         &omap44xx_l4_abe__mcasp_dma,
3352         &omap44xx_l4_abe__mcbsp1,
3353         &omap44xx_l4_abe__mcbsp2,
3354         &omap44xx_l4_abe__mcbsp3,
3355         &omap44xx_l4_per__mcbsp4,
3356         &omap44xx_l4_abe__mcpdm,
3357         &omap44xx_l3_main_2__mmu_ipu,
3358         &omap44xx_l4_cfg__mmu_dsp,
3359         &omap44xx_l3_main_2__ocmc_ram,
3360         &omap44xx_l4_cfg__ocp2scp_usb_phy,
3361         &omap44xx_mpu_private__prcm_mpu,
3362         &omap44xx_l4_wkup__cm_core_aon,
3363         &omap44xx_l4_cfg__cm_core,
3364         &omap44xx_l4_wkup__prm,
3365         &omap44xx_l4_wkup__scrm,
3366         /* &omap44xx_l3_main_2__sl2if, */
3367         &omap44xx_l4_abe__slimbus1,
3368         &omap44xx_l4_abe__slimbus1_dma,
3369         &omap44xx_l4_per__slimbus2,
3370         &omap44xx_l4_cfg__smartreflex_core,
3371         &omap44xx_l4_cfg__smartreflex_iva,
3372         &omap44xx_l4_cfg__smartreflex_mpu,
3373         &omap44xx_l4_cfg__spinlock,
3374         &omap44xx_l4_wkup__timer1,
3375         &omap44xx_l4_per__timer2,
3376         &omap44xx_l4_per__timer3,
3377         &omap44xx_l4_per__timer4,
3378         &omap44xx_l4_abe__timer5,
3379         &omap44xx_l4_abe__timer6,
3380         &omap44xx_l4_abe__timer7,
3381         &omap44xx_l4_abe__timer8,
3382         &omap44xx_l4_per__timer9,
3383         &omap44xx_l4_per__timer10,
3384         &omap44xx_l4_per__timer11,
3385         /* &omap44xx_l4_cfg__usb_host_fs, */
3386         &omap44xx_l4_cfg__usb_host_hs,
3387         &omap44xx_l4_cfg__usb_otg_hs,
3388         &omap44xx_l4_cfg__usb_tll_hs,
3389         &omap44xx_mpu__emif1,
3390         &omap44xx_mpu__emif2,
3391         &omap44xx_l3_main_2__aes1,
3392         &omap44xx_l3_main_2__aes2,
3393         &omap44xx_l3_main_2__des,
3394         &omap44xx_l3_main_2__sha0,
3395         NULL,
3396 };
3397 
3398 int __init omap44xx_hwmod_init(void)
3399 {
3400         omap_hwmod_init();
3401         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
3402 }
3403