1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * opp2420_data.c - old-style "OPP" table for OMAP2420
4 *
5 * Copyright (C) 2005-2009 Texas Instruments, Inc.
6 * Copyright (C) 2004-2009 Nokia Corporation
7 *
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
11 * These configurations are characterized by voltage and speed for clocks.
12 * The device is only validated for certain combinations. One way to express
13 * these combinations is via the 'ratios' which the clocks operate with
14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio.
16 *
17 * XXX Missing voltage data.
18 * XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
19 *
20 * THe format described in this file is deprecated. Once a reasonable
21 * OPP API exists, the data in this file should be converted to use it.
22 *
23 * This is technically part of the OMAP2xxx clock code.
24 *
25 * Considerable work is still needed to fully support dynamic frequency
26 * changes on OMAP2xxx-series chips. Readers interested in such a
27 * project are encouraged to review the Maemo Diablo RX-34 and RX-44
28 * kernel source at:
29 * http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
30 */
31
32 #include <linux/kernel.h>
33
34 #include "opp2xxx.h"
35 #include "sdrc.h"
36 #include "clock.h"
37
38 /*
39 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
40 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
41 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
42 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
43 *
44 * Filling in table based on H4 boards available. There are quite a
45 * few more rate combinations which could be defined.
46 *
47 * When multiple values are defined the start up will try and choose
48 * the fastest one. If a 'fast' value is defined, then automatically,
49 * the /2 one should be included as it can be used. Generally having
50 * more than one fast set does not make sense, as static timings need
51 * to be changed to change the set. The exception is the bypass
52 * setting which is available for low power bypass.
53 *
54 * Note: This table needs to be sorted, fastest to slowest.
55 **/
56 const struct prcm_config omap2420_rate_table[] = {
57 /* PRCM I - FAST */
58 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
59 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
60 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
61 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
62 RATE_IN_242X},
63
64 /* PRCM II - FAST */
65 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
66 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
67 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
68 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
69 RATE_IN_242X},
70
71 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
72 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
73 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
74 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
75 RATE_IN_242X},
76
77 /* PRCM III - FAST */
78 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
79 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
80 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
81 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
82 RATE_IN_242X},
83
84 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
85 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
86 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
87 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
88 RATE_IN_242X},
89
90 /* PRCM II - SLOW */
91 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
92 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
93 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
94 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
95 RATE_IN_242X},
96
97 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
98 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
99 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
100 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
101 RATE_IN_242X},
102
103 /* PRCM III - SLOW */
104 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
105 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
106 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
107 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
108 RATE_IN_242X},
109
110 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
111 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
112 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
113 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
114 RATE_IN_242X},
115
116 /* PRCM-VII (boot-bypass) */
117 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
118 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
119 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
120 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
121 RATE_IN_242X},
122
123 /* PRCM-VII (boot-bypass) */
124 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
125 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
126 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
127 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
128 RATE_IN_242X},
129
130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
131 };