This source file includes following definitions.
- omap_secure_dispatcher
- omap_secure_ram_reserve_memblock
- omap_secure_ram_mempool_base
- omap3_save_secure_ram
- rx51_secure_dispatcher
- rx51_secure_update_aux_cr
- rx51_secure_rng_call
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11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/memblock.h>
15
16 #include <asm/cacheflush.h>
17 #include <asm/memblock.h>
18
19 #include "omap-secure.h"
20
21 static phys_addr_t omap_secure_memblock_base;
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33 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
34 u32 arg3, u32 arg4)
35 {
36 u32 ret;
37 u32 param[5];
38
39 param[0] = nargs;
40 param[1] = arg1;
41 param[2] = arg2;
42 param[3] = arg3;
43 param[4] = arg4;
44
45
46
47
48
49 flush_cache_all();
50 outer_clean_range(__pa(param), __pa(param + 5));
51 ret = omap_smc2(idx, flag, __pa(param));
52
53 return ret;
54 }
55
56
57 int __init omap_secure_ram_reserve_memblock(void)
58 {
59 u32 size = OMAP_SECURE_RAM_STORAGE;
60
61 size = ALIGN(size, SECTION_SIZE);
62 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
63
64 return 0;
65 }
66
67 phys_addr_t omap_secure_ram_mempool_base(void)
68 {
69 return omap_secure_memblock_base;
70 }
71
72 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
73 u32 omap3_save_secure_ram(void __iomem *addr, int size)
74 {
75 u32 ret;
76 u32 param[5];
77
78 if (size != OMAP3_SAVE_SECURE_RAM_SZ)
79 return OMAP3_SAVE_SECURE_RAM_SZ;
80
81 param[0] = 4;
82 param[1] = __pa(addr);
83 param[2] = 0;
84 param[3] = 1;
85 param[4] = 1;
86
87 ret = save_secure_ram_context(__pa(param));
88
89 return ret;
90 }
91 #endif
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106 u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
107 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
108 {
109 u32 ret;
110 u32 param[5];
111
112 param[0] = nargs+1;
113 param[1] = arg1;
114 param[2] = arg2;
115 param[3] = arg3;
116 param[4] = arg4;
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121
122 local_irq_disable();
123 local_fiq_disable();
124 flush_cache_all();
125 outer_clean_range(__pa(param), __pa(param + 5));
126 ret = omap_smc3(idx, process, flag, __pa(param));
127 flush_cache_all();
128 local_fiq_enable();
129 local_irq_enable();
130
131 return ret;
132 }
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141 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
142 {
143 u32 acr;
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145
146 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
147 acr &= ~clear_bits;
148 acr |= set_bits;
149
150 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
151 0,
152 FLAG_START_CRITICAL,
153 1, acr, 0, 0, 0);
154 }
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159 u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
160 {
161 return rx51_secure_dispatcher(RX51_PPA_HWRNG,
162 0,
163 NO_FLAG,
164 3, ptr, count, flag, 0);
165 }