arch/arm/mach-omap2/dma.c

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This source file includes following definitions.
dma_write
dma_read
omap2_clear_dma
omap2_show_dma_caps
configure_dma_errata
omap2_system_dma_init_dev
omap2_system_dma_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP2+ DMA driver
   4  *
   5  * Copyright (C) 2003 - 2008 Nokia Corporation
   6  * Author: Juha Yrjölä <juha.yrjola@nokia.com>
   7  * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
   8  * Graphics DMA and LCD DMA graphics tranformations
   9  * by Imre Deak <imre.deak@nokia.com>
  10  * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
  11  * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  15  *
  16  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  17  * Converted DMA library into platform driver
  18  *      - G, Manjunath Kondaiah <manjugk@ti.com>
  19  */
  20 
  21 #include <linux/err.h>
  22 #include <linux/io.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/device.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/of.h>
  30 #include <linux/omap-dma.h>
  31 
  32 #include "soc.h"
  33 #include "omap_hwmod.h"
  34 #include "omap_device.h"
  35 
  36 static enum omap_reg_offsets dma_common_ch_end;
  37 
  38 static const struct omap_dma_reg reg_map[] = {
  39         [REVISION]      = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
  40         [GCR]           = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
  41         [IRQSTATUS_L0]  = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
  42         [IRQSTATUS_L1]  = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
  43         [IRQSTATUS_L2]  = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
  44         [IRQSTATUS_L3]  = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
  45         [IRQENABLE_L0]  = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
  46         [IRQENABLE_L1]  = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
  47         [IRQENABLE_L2]  = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
  48         [IRQENABLE_L3]  = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
  49         [SYSSTATUS]     = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
  50         [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
  51         [CAPS_0]        = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
  52         [CAPS_2]        = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
  53         [CAPS_3]        = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
  54         [CAPS_4]        = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
  55 
  56         /* Common register offsets */
  57         [CCR]           = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
  58         [CLNK_CTRL]     = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
  59         [CICR]          = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
  60         [CSR]           = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
  61         [CSDP]          = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
  62         [CEN]           = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
  63         [CFN]           = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
  64         [CSEI]          = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
  65         [CSFI]          = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
  66         [CDEI]          = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
  67         [CDFI]          = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
  68         [CSAC]          = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
  69         [CDAC]          = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
  70 
  71         /* Channel specific register offsets */
  72         [CSSA]          = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
  73         [CDSA]          = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
  74         [CCEN]          = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
  75         [CCFN]          = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
  76         [COLOR]         = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
  77 
  78         /* OMAP4 specific registers */
  79         [CDP]           = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
  80         [CNDP]          = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
  81         [CCDN]          = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
  82 };
  83 
  84 static void __iomem *dma_base;
  85 static inline void dma_write(u32 val, int reg, int lch)
  86 {
  87         void __iomem *addr = dma_base;
  88 
  89         addr += reg_map[reg].offset;
  90         addr += reg_map[reg].stride * lch;
  91 
  92         writel_relaxed(val, addr);
  93 }
  94 
  95 static inline u32 dma_read(int reg, int lch)
  96 {
  97         void __iomem *addr = dma_base;
  98 
  99         addr += reg_map[reg].offset;
 100         addr += reg_map[reg].stride * lch;
 101 
 102         return readl_relaxed(addr);
 103 }
 104 
 105 static void omap2_clear_dma(int lch)
 106 {
 107         int i;
 108 
 109         for (i = CSDP; i <= dma_common_ch_end; i += 1)
 110                 dma_write(0, i, lch);
 111 }
 112 
 113 static void omap2_show_dma_caps(void)
 114 {
 115         u8 revision = dma_read(REVISION, 0) & 0xff;
 116         printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
 117                                 revision >> 4, revision & 0xf);
 118 }
 119 
 120 static unsigned configure_dma_errata(void)
 121 {
 122         unsigned errata = 0;
 123 
 124         /*
 125          * Errata applicable for OMAP2430ES1.0 and all omap2420
 126          *
 127          * I.
 128          * Erratum ID: Not Available
 129          * Inter Frame DMA buffering issue DMA will wrongly
 130          * buffer elements if packing and bursting is enabled. This might
 131          * result in data gets stalled in FIFO at the end of the block.
 132          * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
 133          * guarantee no data will stay in the DMA FIFO in case inter frame
 134          * buffering occurs
 135          *
 136          * II.
 137          * Erratum ID: Not Available
 138          * DMA may hang when several channels are used in parallel
 139          * In the following configuration, DMA channel hanging can occur:
 140          * a. Channel i, hardware synchronized, is enabled
 141          * b. Another channel (Channel x), software synchronized, is enabled.
 142          * c. Channel i is disabled before end of transfer
 143          * d. Channel i is reenabled.
 144          * e. Steps 1 to 4 are repeated a certain number of times.
 145          * f. A third channel (Channel y), software synchronized, is enabled.
 146          * Channel x and Channel y may hang immediately after step 'f'.
 147          * Workaround:
 148          * For any channel used - make sure NextLCH_ID is set to the value j.
 149          */
 150         if (cpu_is_omap2420() || (cpu_is_omap2430() &&
 151                                 (omap_type() == OMAP2430_REV_ES1_0))) {
 152 
 153                 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
 154                 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
 155         }
 156 
 157         /*
 158          * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
 159          * after a transaction error.
 160          * Workaround: SW should explicitely disable the channel.
 161          */
 162         if (cpu_class_is_omap2())
 163                 SET_DMA_ERRATA(DMA_ERRATA_i378);
 164 
 165         /*
 166          * Erratum ID: i541: sDMA FIFO draining does not finish
 167          * If sDMA channel is disabled on the fly, sDMA enters standby even
 168          * through FIFO Drain is still in progress
 169          * Workaround: Put sDMA in NoStandby more before a logical channel is
 170          * disabled, then put it back to SmartStandby right after the channel
 171          * finishes FIFO draining.
 172          */
 173         if (cpu_is_omap34xx())
 174                 SET_DMA_ERRATA(DMA_ERRATA_i541);
 175 
 176         /*
 177          * Erratum ID: i88 : Special programming model needed to disable DMA
 178          * before end of block.
 179          * Workaround: software must ensure that the DMA is configured in No
 180          * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
 181          */
 182         if (omap_type() == OMAP3430_REV_ES1_0)
 183                 SET_DMA_ERRATA(DMA_ERRATA_i88);
 184 
 185         /*
 186          * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
 187          * read before the DMA controller finished disabling the channel.
 188          */
 189         SET_DMA_ERRATA(DMA_ERRATA_3_3);
 190 
 191         /*
 192          * Erratum ID: Not Available
 193          * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
 194          * after secure sram context save and restore.
 195          * Work around: Hence we need to manually clear those IRQs to avoid
 196          * spurious interrupts. This affects only secure devices.
 197          */
 198         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 199                 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
 200 
 201         return errata;
 202 }
 203 
 204 static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
 205         /* external DMA requests when tusb6010 is used */
 206         { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
 207         { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
 208         { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
 209         { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
 210         { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
 211         { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
 212 };
 213 
 214 static struct omap_system_dma_plat_info dma_plat_info __initdata = {
 215         .reg_map        = reg_map,
 216         .channel_stride = 0x60,
 217         .show_dma_caps  = omap2_show_dma_caps,
 218         .clear_dma      = omap2_clear_dma,
 219         .dma_write      = dma_write,
 220         .dma_read       = dma_read,
 221 };
 222 
 223 static struct platform_device_info omap_dma_dev_info __initdata = {
 224         .name = "omap-dma-engine",
 225         .id = -1,
 226         .dma_mask = DMA_BIT_MASK(32),
 227 };
 228 
 229 /* One time initializations */
 230 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
 231 {
 232         struct platform_device                  *pdev;
 233         struct omap_system_dma_plat_info        p;
 234         struct omap_dma_dev_attr                *d;
 235         struct resource                         *mem;
 236         char                                    *name = "omap_dma_system";
 237 
 238         p = dma_plat_info;
 239         p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
 240         p.errata = configure_dma_errata();
 241 
 242         if (soc_is_omap24xx()) {
 243                 /* DMA slave map for drivers not yet converted to DT */
 244                 p.slave_map = omap24xx_sdma_dt_map;
 245                 p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
 246         }
 247 
 248         pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
 249         if (IS_ERR(pdev)) {
 250                 pr_err("%s: Can't build omap_device for %s:%s.\n",
 251                         __func__, name, oh->name);
 252                 return PTR_ERR(pdev);
 253         }
 254 
 255         omap_dma_dev_info.res = pdev->resource;
 256         omap_dma_dev_info.num_res = pdev->num_resources;
 257 
 258         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 259         if (!mem) {
 260                 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
 261                 return -EINVAL;
 262         }
 263 
 264         dma_base = ioremap(mem->start, resource_size(mem));
 265         if (!dma_base) {
 266                 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
 267                 return -ENOMEM;
 268         }
 269 
 270         d = oh->dev_attr;
 271 
 272         if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
 273                 d->dev_caps |= HS_CHANNELS_RESERVED;
 274 
 275         if (platform_get_irq_byname(pdev, "0") < 0)
 276                 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
 277 
 278         /* Check the capabilities register for descriptor loading feature */
 279         if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
 280                 dma_common_ch_end = CCDN;
 281         else
 282                 dma_common_ch_end = CCFN;
 283 
 284         return 0;
 285 }
 286 
 287 static int __init omap2_system_dma_init(void)
 288 {
 289         return omap_hwmod_for_each_by_class("dma",
 290                         omap2_system_dma_init_dev, NULL);
 291 }
 292 omap_arch_initcall(omap2_system_dma_init);
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root/arch/arm/mach-omap2/dma.c

DEFINITIONS
