root/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

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DEFINITIONS

This source file includes following definitions.
  1. dra7xx_pciess_reset
  2. dra7xx_hwmod_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the DRA7xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16 
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19 
  20 #include <linux/omap-dma.h>
  21 
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_7xx.h"
  25 #include "cm2_7xx.h"
  26 #include "prm7xx.h"
  27 #include "wd_timer.h"
  28 #include "soc.h"
  29 
  30 /* Base offset for all DRA7XX interrupts external to MPUSS */
  31 #define DRA7XX_IRQ_GIC_START    32
  32 
  33 /* Base offset for all DRA7XX dma requests */
  34 #define DRA7XX_DMA_REQ_START    1
  35 
  36 
  37 /*
  38  * IP blocks
  39  */
  40 
  41 /*
  42  * 'dmm' class
  43  * instance(s): dmm
  44  */
  45 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  46         .name   = "dmm",
  47 };
  48 
  49 /* dmm */
  50 static struct omap_hwmod dra7xx_dmm_hwmod = {
  51         .name           = "dmm",
  52         .class          = &dra7xx_dmm_hwmod_class,
  53         .clkdm_name     = "emif_clkdm",
  54         .prcm = {
  55                 .omap4 = {
  56                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  57                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  58                 },
  59         },
  60 };
  61 
  62 /*
  63  * 'l3' class
  64  * instance(s): l3_instr, l3_main_1, l3_main_2
  65  */
  66 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  67         .name   = "l3",
  68 };
  69 
  70 /* l3_instr */
  71 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  72         .name           = "l3_instr",
  73         .class          = &dra7xx_l3_hwmod_class,
  74         .clkdm_name     = "l3instr_clkdm",
  75         .prcm = {
  76                 .omap4 = {
  77                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  78                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  79                         .modulemode   = MODULEMODE_HWCTRL,
  80                 },
  81         },
  82 };
  83 
  84 /* l3_main_1 */
  85 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  86         .name           = "l3_main_1",
  87         .class          = &dra7xx_l3_hwmod_class,
  88         .clkdm_name     = "l3main1_clkdm",
  89         .prcm = {
  90                 .omap4 = {
  91                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  92                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  93                 },
  94         },
  95 };
  96 
  97 /* l3_main_2 */
  98 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  99         .name           = "l3_main_2",
 100         .class          = &dra7xx_l3_hwmod_class,
 101         .clkdm_name     = "l3instr_clkdm",
 102         .prcm = {
 103                 .omap4 = {
 104                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
 105                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
 106                         .modulemode   = MODULEMODE_HWCTRL,
 107                 },
 108         },
 109 };
 110 
 111 /*
 112  * 'l4' class
 113  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 114  */
 115 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 116         .name   = "l4",
 117 };
 118 
 119 /* l4_cfg */
 120 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 121         .name           = "l4_cfg",
 122         .class          = &dra7xx_l4_hwmod_class,
 123         .clkdm_name     = "l4cfg_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 127                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 128                 },
 129         },
 130 };
 131 
 132 /* l4_per1 */
 133 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 134         .name           = "l4_per1",
 135         .class          = &dra7xx_l4_hwmod_class,
 136         .clkdm_name     = "l4per_clkdm",
 137         .prcm = {
 138                 .omap4 = {
 139                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 140                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 141                 },
 142         },
 143 };
 144 
 145 /* l4_per2 */
 146 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 147         .name           = "l4_per2",
 148         .class          = &dra7xx_l4_hwmod_class,
 149         .clkdm_name     = "l4per2_clkdm",
 150         .prcm = {
 151                 .omap4 = {
 152                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 153                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 154                 },
 155         },
 156 };
 157 
 158 /* l4_per3 */
 159 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 160         .name           = "l4_per3",
 161         .class          = &dra7xx_l4_hwmod_class,
 162         .clkdm_name     = "l4per3_clkdm",
 163         .prcm = {
 164                 .omap4 = {
 165                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 166                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 167                 },
 168         },
 169 };
 170 
 171 /* l4_wkup */
 172 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 173         .name           = "l4_wkup",
 174         .class          = &dra7xx_l4_hwmod_class,
 175         .clkdm_name     = "wkupaon_clkdm",
 176         .prcm = {
 177                 .omap4 = {
 178                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 179                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 180                 },
 181         },
 182 };
 183 
 184 /*
 185  * 'atl' class
 186  *
 187  */
 188 
 189 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 190         .name   = "atl",
 191 };
 192 
 193 /* atl */
 194 static struct omap_hwmod dra7xx_atl_hwmod = {
 195         .name           = "atl",
 196         .class          = &dra7xx_atl_hwmod_class,
 197         .clkdm_name     = "atl_clkdm",
 198         .main_clk       = "atl_gfclk_mux",
 199         .prcm = {
 200                 .omap4 = {
 201                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 202                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 203                         .modulemode   = MODULEMODE_SWCTRL,
 204                 },
 205         },
 206 };
 207 
 208 /*
 209  * 'bb2d' class
 210  *
 211  */
 212 
 213 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 214         .name   = "bb2d",
 215 };
 216 
 217 /* bb2d */
 218 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 219         .name           = "bb2d",
 220         .class          = &dra7xx_bb2d_hwmod_class,
 221         .clkdm_name     = "dss_clkdm",
 222         .main_clk       = "dpll_core_h24x2_ck",
 223         .prcm = {
 224                 .omap4 = {
 225                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 226                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 227                         .modulemode   = MODULEMODE_SWCTRL,
 228                 },
 229         },
 230 };
 231 
 232 /*
 233  * 'counter' class
 234  *
 235  */
 236 
 237 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 238         .rev_offs       = 0x0000,
 239         .sysc_offs      = 0x0010,
 240         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 241         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 242                            SIDLE_SMART_WKUP),
 243         .sysc_fields    = &omap_hwmod_sysc_type1,
 244 };
 245 
 246 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 247         .name   = "counter",
 248         .sysc   = &dra7xx_counter_sysc,
 249 };
 250 
 251 /* counter_32k */
 252 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 253         .name           = "counter_32k",
 254         .class          = &dra7xx_counter_hwmod_class,
 255         .clkdm_name     = "wkupaon_clkdm",
 256         .flags          = HWMOD_SWSUP_SIDLE,
 257         .main_clk       = "wkupaon_iclk_mux",
 258         .prcm = {
 259                 .omap4 = {
 260                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 261                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 262                 },
 263         },
 264 };
 265 
 266 /*
 267  * 'ctrl_module' class
 268  *
 269  */
 270 
 271 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 272         .name   = "ctrl_module",
 273 };
 274 
 275 /* ctrl_module_wkup */
 276 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 277         .name           = "ctrl_module_wkup",
 278         .class          = &dra7xx_ctrl_module_hwmod_class,
 279         .clkdm_name     = "wkupaon_clkdm",
 280         .prcm = {
 281                 .omap4 = {
 282                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 283                 },
 284         },
 285 };
 286 
 287 /*
 288  * 'dcan' class
 289  *
 290  */
 291 
 292 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 293         .name   = "dcan",
 294 };
 295 
 296 /* dcan1 */
 297 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 298         .name           = "dcan1",
 299         .class          = &dra7xx_dcan_hwmod_class,
 300         .clkdm_name     = "wkupaon_clkdm",
 301         .main_clk       = "dcan1_sys_clk_mux",
 302         .flags          = HWMOD_CLKDM_NOAUTO,
 303         .prcm = {
 304                 .omap4 = {
 305                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 306                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 307                         .modulemode   = MODULEMODE_SWCTRL,
 308                 },
 309         },
 310 };
 311 
 312 /* dcan2 */
 313 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 314         .name           = "dcan2",
 315         .class          = &dra7xx_dcan_hwmod_class,
 316         .clkdm_name     = "l4per2_clkdm",
 317         .main_clk       = "sys_clkin1",
 318         .flags          = HWMOD_CLKDM_NOAUTO,
 319         .prcm = {
 320                 .omap4 = {
 321                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 322                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 323                         .modulemode   = MODULEMODE_SWCTRL,
 324                 },
 325         },
 326 };
 327 
 328 /* pwmss  */
 329 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
 330         .rev_offs       = 0x0,
 331         .sysc_offs      = 0x4,
 332         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 333                           SYSC_HAS_RESET_STATUS,
 334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 335         .sysc_fields    = &omap_hwmod_sysc_type2,
 336 };
 337 
 338 /*
 339  * epwmss class
 340  */
 341 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
 342         .name           = "epwmss",
 343         .sysc           = &dra7xx_epwmss_sysc,
 344 };
 345 
 346 /* epwmss0 */
 347 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
 348         .name           = "epwmss0",
 349         .class          = &dra7xx_epwmss_hwmod_class,
 350         .clkdm_name     = "l4per2_clkdm",
 351         .main_clk       = "l4_root_clk_div",
 352         .prcm           = {
 353                 .omap4  = {
 354                         .modulemode     = MODULEMODE_SWCTRL,
 355                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
 356                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
 357                 },
 358         },
 359 };
 360 
 361 /* epwmss1 */
 362 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
 363         .name           = "epwmss1",
 364         .class          = &dra7xx_epwmss_hwmod_class,
 365         .clkdm_name     = "l4per2_clkdm",
 366         .main_clk       = "l4_root_clk_div",
 367         .prcm           = {
 368                 .omap4  = {
 369                         .modulemode     = MODULEMODE_SWCTRL,
 370                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
 371                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
 372                 },
 373         },
 374 };
 375 
 376 /* epwmss2 */
 377 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
 378         .name           = "epwmss2",
 379         .class          = &dra7xx_epwmss_hwmod_class,
 380         .clkdm_name     = "l4per2_clkdm",
 381         .main_clk       = "l4_root_clk_div",
 382         .prcm           = {
 383                 .omap4  = {
 384                         .modulemode     = MODULEMODE_SWCTRL,
 385                         .clkctrl_offs   = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
 386                         .context_offs   = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
 387                 },
 388         },
 389 };
 390 
 391 /*
 392  * 'dma' class
 393  *
 394  */
 395 
 396 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 397         .rev_offs       = 0x0000,
 398         .sysc_offs      = 0x002c,
 399         .syss_offs      = 0x0028,
 400         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 401                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 402                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 403                            SYSS_HAS_RESET_STATUS),
 404         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 405                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 406                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 407         .sysc_fields    = &omap_hwmod_sysc_type1,
 408 };
 409 
 410 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 411         .name   = "dma",
 412         .sysc   = &dra7xx_dma_sysc,
 413 };
 414 
 415 /* dma dev_attr */
 416 static struct omap_dma_dev_attr dma_dev_attr = {
 417         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 418                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 419         .lch_count      = 32,
 420 };
 421 
 422 /* dma_system */
 423 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 424         .name           = "dma_system",
 425         .class          = &dra7xx_dma_hwmod_class,
 426         .clkdm_name     = "dma_clkdm",
 427         .main_clk       = "l3_iclk_div",
 428         .prcm = {
 429                 .omap4 = {
 430                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 431                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 432                 },
 433         },
 434         .dev_attr       = &dma_dev_attr,
 435 };
 436 
 437 /*
 438  * 'tpcc' class
 439  *
 440  */
 441 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
 442         .name           = "tpcc",
 443 };
 444 
 445 static struct omap_hwmod dra7xx_tpcc_hwmod = {
 446         .name           = "tpcc",
 447         .class          = &dra7xx_tpcc_hwmod_class,
 448         .clkdm_name     = "l3main1_clkdm",
 449         .main_clk       = "l3_iclk_div",
 450         .prcm           = {
 451                 .omap4  = {
 452                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
 453                         .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
 454                 },
 455         },
 456 };
 457 
 458 /*
 459  * 'tptc' class
 460  *
 461  */
 462 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
 463         .name           = "tptc",
 464 };
 465 
 466 /* tptc0 */
 467 static struct omap_hwmod dra7xx_tptc0_hwmod = {
 468         .name           = "tptc0",
 469         .class          = &dra7xx_tptc_hwmod_class,
 470         .clkdm_name     = "l3main1_clkdm",
 471         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 472         .main_clk       = "l3_iclk_div",
 473         .prcm           = {
 474                 .omap4  = {
 475                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
 476                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
 477                         .modulemode   = MODULEMODE_HWCTRL,
 478                 },
 479         },
 480 };
 481 
 482 /* tptc1 */
 483 static struct omap_hwmod dra7xx_tptc1_hwmod = {
 484         .name           = "tptc1",
 485         .class          = &dra7xx_tptc_hwmod_class,
 486         .clkdm_name     = "l3main1_clkdm",
 487         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 488         .main_clk       = "l3_iclk_div",
 489         .prcm           = {
 490                 .omap4  = {
 491                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
 492                         .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
 493                         .modulemode   = MODULEMODE_HWCTRL,
 494                 },
 495         },
 496 };
 497 
 498 /*
 499  * 'dss' class
 500  *
 501  */
 502 
 503 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 504         .rev_offs       = 0x0000,
 505         .syss_offs      = 0x0014,
 506         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 507 };
 508 
 509 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 510         .name   = "dss",
 511         .sysc   = &dra7xx_dss_sysc,
 512         .reset  = omap_dss_reset,
 513 };
 514 
 515 /* dss */
 516 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 517         { .role = "dss_clk", .clk = "dss_dss_clk" },
 518         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 519         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 520         { .role = "video2_clk", .clk = "dss_video2_clk" },
 521         { .role = "video1_clk", .clk = "dss_video1_clk" },
 522         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 523         { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
 524 };
 525 
 526 static struct omap_hwmod dra7xx_dss_hwmod = {
 527         .name           = "dss_core",
 528         .class          = &dra7xx_dss_hwmod_class,
 529         .clkdm_name     = "dss_clkdm",
 530         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 531         .main_clk       = "dss_dss_clk",
 532         .prcm = {
 533                 .omap4 = {
 534                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 535                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 536                         .modulemode   = MODULEMODE_SWCTRL,
 537                 },
 538         },
 539         .opt_clks       = dss_opt_clks,
 540         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 541 };
 542 
 543 /*
 544  * 'dispc' class
 545  * display controller
 546  */
 547 
 548 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 549         .rev_offs       = 0x0000,
 550         .sysc_offs      = 0x0010,
 551         .syss_offs      = 0x0014,
 552         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 553                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 554                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 555                            SYSS_HAS_RESET_STATUS),
 556         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 557                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 558         .sysc_fields    = &omap_hwmod_sysc_type1,
 559 };
 560 
 561 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 562         .name   = "dispc",
 563         .sysc   = &dra7xx_dispc_sysc,
 564 };
 565 
 566 /* dss_dispc */
 567 /* dss_dispc dev_attr */
 568 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 569         .has_framedonetv_irq    = 1,
 570         .manager_count          = 4,
 571 };
 572 
 573 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 574         .name           = "dss_dispc",
 575         .class          = &dra7xx_dispc_hwmod_class,
 576         .clkdm_name     = "dss_clkdm",
 577         .main_clk       = "dss_dss_clk",
 578         .prcm = {
 579                 .omap4 = {
 580                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 581                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 582                 },
 583         },
 584         .dev_attr       = &dss_dispc_dev_attr,
 585         .parent_hwmod   = &dra7xx_dss_hwmod,
 586 };
 587 
 588 /*
 589  * 'hdmi' class
 590  * hdmi controller
 591  */
 592 
 593 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 594         .rev_offs       = 0x0000,
 595         .sysc_offs      = 0x0010,
 596         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 597                            SYSC_HAS_SOFTRESET),
 598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 599                            SIDLE_SMART_WKUP),
 600         .sysc_fields    = &omap_hwmod_sysc_type2,
 601 };
 602 
 603 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 604         .name   = "hdmi",
 605         .sysc   = &dra7xx_hdmi_sysc,
 606 };
 607 
 608 /* dss_hdmi */
 609 
 610 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 611         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 612 };
 613 
 614 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 615         .name           = "dss_hdmi",
 616         .class          = &dra7xx_hdmi_hwmod_class,
 617         .clkdm_name     = "dss_clkdm",
 618         .main_clk       = "dss_48mhz_clk",
 619         .prcm = {
 620                 .omap4 = {
 621                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 622                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 623                 },
 624         },
 625         .opt_clks       = dss_hdmi_opt_clks,
 626         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 627         .parent_hwmod   = &dra7xx_dss_hwmod,
 628 };
 629 
 630 /* AES (the 'P' (public) device) */
 631 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 632         .rev_offs       = 0x0080,
 633         .sysc_offs      = 0x0084,
 634         .syss_offs      = 0x0088,
 635         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 636 };
 637 
 638 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
 639         .name   = "aes",
 640         .sysc   = &dra7xx_aes_sysc,
 641 };
 642 
 643 /* AES1 */
 644 static struct omap_hwmod dra7xx_aes1_hwmod = {
 645         .name           = "aes1",
 646         .class          = &dra7xx_aes_hwmod_class,
 647         .clkdm_name     = "l4sec_clkdm",
 648         .main_clk       = "l3_iclk_div",
 649         .prcm = {
 650                 .omap4 = {
 651                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 652                         .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
 653                         .modulemode   = MODULEMODE_HWCTRL,
 654                 },
 655         },
 656 };
 657 
 658 /* AES2 */
 659 static struct omap_hwmod dra7xx_aes2_hwmod = {
 660         .name           = "aes2",
 661         .class          = &dra7xx_aes_hwmod_class,
 662         .clkdm_name     = "l4sec_clkdm",
 663         .main_clk       = "l3_iclk_div",
 664         .prcm = {
 665                 .omap4 = {
 666                         .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 667                         .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
 668                         .modulemode   = MODULEMODE_HWCTRL,
 669                 },
 670         },
 671 };
 672 
 673 /* sha0 HIB2 (the 'P' (public) device) */
 674 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 675         .rev_offs       = 0x100,
 676         .sysc_offs      = 0x110,
 677         .syss_offs      = 0x114,
 678         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 679 };
 680 
 681 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
 682         .name           = "sham",
 683         .sysc           = &dra7xx_sha0_sysc,
 684 };
 685 
 686 struct omap_hwmod dra7xx_sha0_hwmod = {
 687         .name           = "sham",
 688         .class          = &dra7xx_sha0_hwmod_class,
 689         .clkdm_name     = "l4sec_clkdm",
 690         .main_clk       = "l3_iclk_div",
 691         .prcm           = {
 692                 .omap4 = {
 693                         .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 694                         .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 695                         .modulemode   = MODULEMODE_HWCTRL,
 696                 },
 697         },
 698 };
 699 
 700 /*
 701  * 'elm' class
 702  *
 703  */
 704 
 705 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 706         .rev_offs       = 0x0000,
 707         .sysc_offs      = 0x0010,
 708         .syss_offs      = 0x0014,
 709         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 711                            SYSS_HAS_RESET_STATUS),
 712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 713                            SIDLE_SMART_WKUP),
 714         .sysc_fields    = &omap_hwmod_sysc_type1,
 715 };
 716 
 717 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 718         .name   = "elm",
 719         .sysc   = &dra7xx_elm_sysc,
 720 };
 721 
 722 /* elm */
 723 
 724 static struct omap_hwmod dra7xx_elm_hwmod = {
 725         .name           = "elm",
 726         .class          = &dra7xx_elm_hwmod_class,
 727         .clkdm_name     = "l4per_clkdm",
 728         .main_clk       = "l3_iclk_div",
 729         .prcm = {
 730                 .omap4 = {
 731                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 732                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 733                 },
 734         },
 735 };
 736 
 737 /*
 738  * 'gpmc' class
 739  *
 740  */
 741 
 742 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 743         .rev_offs       = 0x0000,
 744         .sysc_offs      = 0x0010,
 745         .syss_offs      = 0x0014,
 746         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 747                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 748         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 749         .sysc_fields    = &omap_hwmod_sysc_type1,
 750 };
 751 
 752 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 753         .name   = "gpmc",
 754         .sysc   = &dra7xx_gpmc_sysc,
 755 };
 756 
 757 /* gpmc */
 758 
 759 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 760         .name           = "gpmc",
 761         .class          = &dra7xx_gpmc_hwmod_class,
 762         .clkdm_name     = "l3main1_clkdm",
 763         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 764         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 765         .main_clk       = "l3_iclk_div",
 766         .prcm = {
 767                 .omap4 = {
 768                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 769                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 770                         .modulemode   = MODULEMODE_HWCTRL,
 771                 },
 772         },
 773 };
 774 
 775 /*
 776  * 'hdq1w' class
 777  *
 778  */
 779 
 780 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 781         .rev_offs       = 0x0000,
 782         .sysc_offs      = 0x0014,
 783         .syss_offs      = 0x0018,
 784         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 785                            SYSS_HAS_RESET_STATUS),
 786         .sysc_fields    = &omap_hwmod_sysc_type1,
 787 };
 788 
 789 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 790         .name   = "hdq1w",
 791         .sysc   = &dra7xx_hdq1w_sysc,
 792 };
 793 
 794 /* hdq1w */
 795 
 796 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 797         .name           = "hdq1w",
 798         .class          = &dra7xx_hdq1w_hwmod_class,
 799         .clkdm_name     = "l4per_clkdm",
 800         .flags          = HWMOD_INIT_NO_RESET,
 801         .main_clk       = "func_12m_fclk",
 802         .prcm = {
 803                 .omap4 = {
 804                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 805                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 806                         .modulemode   = MODULEMODE_SWCTRL,
 807                 },
 808         },
 809 };
 810 
 811 /*
 812  * 'mailbox' class
 813  *
 814  */
 815 
 816 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
 817         .rev_offs       = 0x0000,
 818         .sysc_offs      = 0x0010,
 819         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 820                            SYSC_HAS_SOFTRESET),
 821         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 822         .sysc_fields    = &omap_hwmod_sysc_type2,
 823 };
 824 
 825 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
 826         .name   = "mailbox",
 827         .sysc   = &dra7xx_mailbox_sysc,
 828 };
 829 
 830 /* mailbox1 */
 831 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
 832         .name           = "mailbox1",
 833         .class          = &dra7xx_mailbox_hwmod_class,
 834         .clkdm_name     = "l4cfg_clkdm",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
 838                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
 839                 },
 840         },
 841 };
 842 
 843 /* mailbox2 */
 844 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
 845         .name           = "mailbox2",
 846         .class          = &dra7xx_mailbox_hwmod_class,
 847         .clkdm_name     = "l4cfg_clkdm",
 848         .prcm = {
 849                 .omap4 = {
 850                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
 851                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
 852                 },
 853         },
 854 };
 855 
 856 /* mailbox3 */
 857 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
 858         .name           = "mailbox3",
 859         .class          = &dra7xx_mailbox_hwmod_class,
 860         .clkdm_name     = "l4cfg_clkdm",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
 864                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
 865                 },
 866         },
 867 };
 868 
 869 /* mailbox4 */
 870 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
 871         .name           = "mailbox4",
 872         .class          = &dra7xx_mailbox_hwmod_class,
 873         .clkdm_name     = "l4cfg_clkdm",
 874         .prcm = {
 875                 .omap4 = {
 876                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
 877                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
 878                 },
 879         },
 880 };
 881 
 882 /* mailbox5 */
 883 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
 884         .name           = "mailbox5",
 885         .class          = &dra7xx_mailbox_hwmod_class,
 886         .clkdm_name     = "l4cfg_clkdm",
 887         .prcm = {
 888                 .omap4 = {
 889                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
 890                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
 891                 },
 892         },
 893 };
 894 
 895 /* mailbox6 */
 896 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
 897         .name           = "mailbox6",
 898         .class          = &dra7xx_mailbox_hwmod_class,
 899         .clkdm_name     = "l4cfg_clkdm",
 900         .prcm = {
 901                 .omap4 = {
 902                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
 903                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
 904                 },
 905         },
 906 };
 907 
 908 /* mailbox7 */
 909 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
 910         .name           = "mailbox7",
 911         .class          = &dra7xx_mailbox_hwmod_class,
 912         .clkdm_name     = "l4cfg_clkdm",
 913         .prcm = {
 914                 .omap4 = {
 915                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
 916                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
 917                 },
 918         },
 919 };
 920 
 921 /* mailbox8 */
 922 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
 923         .name           = "mailbox8",
 924         .class          = &dra7xx_mailbox_hwmod_class,
 925         .clkdm_name     = "l4cfg_clkdm",
 926         .prcm = {
 927                 .omap4 = {
 928                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
 929                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
 930                 },
 931         },
 932 };
 933 
 934 /* mailbox9 */
 935 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
 936         .name           = "mailbox9",
 937         .class          = &dra7xx_mailbox_hwmod_class,
 938         .clkdm_name     = "l4cfg_clkdm",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
 942                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
 943                 },
 944         },
 945 };
 946 
 947 /* mailbox10 */
 948 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
 949         .name           = "mailbox10",
 950         .class          = &dra7xx_mailbox_hwmod_class,
 951         .clkdm_name     = "l4cfg_clkdm",
 952         .prcm = {
 953                 .omap4 = {
 954                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
 955                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
 956                 },
 957         },
 958 };
 959 
 960 /* mailbox11 */
 961 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
 962         .name           = "mailbox11",
 963         .class          = &dra7xx_mailbox_hwmod_class,
 964         .clkdm_name     = "l4cfg_clkdm",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
 968                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972 
 973 /* mailbox12 */
 974 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
 975         .name           = "mailbox12",
 976         .class          = &dra7xx_mailbox_hwmod_class,
 977         .clkdm_name     = "l4cfg_clkdm",
 978         .prcm = {
 979                 .omap4 = {
 980                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
 981                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
 982                 },
 983         },
 984 };
 985 
 986 /* mailbox13 */
 987 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
 988         .name           = "mailbox13",
 989         .class          = &dra7xx_mailbox_hwmod_class,
 990         .clkdm_name     = "l4cfg_clkdm",
 991         .prcm = {
 992                 .omap4 = {
 993                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
 994                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
 995                 },
 996         },
 997 };
 998 
 999 /*
1000  * 'mpu' class
1001  *
1002  */
1003 
1004 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1005         .name   = "mpu",
1006 };
1007 
1008 /* mpu */
1009 static struct omap_hwmod dra7xx_mpu_hwmod = {
1010         .name           = "mpu",
1011         .class          = &dra7xx_mpu_hwmod_class,
1012         .clkdm_name     = "mpu_clkdm",
1013         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1014         .main_clk       = "dpll_mpu_m2_ck",
1015         .prcm = {
1016                 .omap4 = {
1017                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1018                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1019                 },
1020         },
1021 };
1022 
1023 /*
1024  * 'ocp2scp' class
1025  *
1026  */
1027 
1028 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1029         .rev_offs       = 0x0000,
1030         .sysc_offs      = 0x0010,
1031         .syss_offs      = 0x0014,
1032         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1033                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1034         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1035         .sysc_fields    = &omap_hwmod_sysc_type1,
1036 };
1037 
1038 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1039         .name   = "ocp2scp",
1040         .sysc   = &dra7xx_ocp2scp_sysc,
1041 };
1042 
1043 /* ocp2scp1 */
1044 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1045         .name           = "ocp2scp1",
1046         .class          = &dra7xx_ocp2scp_hwmod_class,
1047         .clkdm_name     = "l3init_clkdm",
1048         .main_clk       = "l4_root_clk_div",
1049         .prcm = {
1050                 .omap4 = {
1051                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1052                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1053                         .modulemode   = MODULEMODE_HWCTRL,
1054                 },
1055         },
1056 };
1057 
1058 /* ocp2scp3 */
1059 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1060         .name           = "ocp2scp3",
1061         .class          = &dra7xx_ocp2scp_hwmod_class,
1062         .clkdm_name     = "l3init_clkdm",
1063         .main_clk       = "l4_root_clk_div",
1064         .prcm = {
1065                 .omap4 = {
1066                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1067                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1068                         .modulemode   = MODULEMODE_HWCTRL,
1069                 },
1070         },
1071 };
1072 
1073 /*
1074  * 'PCIE' class
1075  *
1076  */
1077 
1078 /*
1079  * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1080  * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1081  * associated with an IP automatically leaving the driver to handle that
1082  * by itself. This does not work for PCIeSS which needs the reset lines
1083  * deasserted for the driver to start accessing registers.
1084  *
1085  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1086  * lines after asserting them.
1087  */
1088 int dra7xx_pciess_reset(struct omap_hwmod *oh)
1089 {
1090         int i;
1091 
1092         for (i = 0; i < oh->rst_lines_cnt; i++) {
1093                 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1094                 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1095         }
1096 
1097         return 0;
1098 }
1099 
1100 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1101         .name   = "pcie",
1102         .reset  = dra7xx_pciess_reset,
1103 };
1104 
1105 /* pcie1 */
1106 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1107         { .name = "pcie", .rst_shift = 0 },
1108 };
1109 
1110 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1111         .name           = "pcie1",
1112         .class          = &dra7xx_pciess_hwmod_class,
1113         .clkdm_name     = "pcie_clkdm",
1114         .rst_lines      = dra7xx_pciess1_resets,
1115         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess1_resets),
1116         .main_clk       = "l4_root_clk_div",
1117         .prcm = {
1118                 .omap4 = {
1119                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1120                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1121                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1122                         .modulemode   = MODULEMODE_SWCTRL,
1123                 },
1124         },
1125 };
1126 
1127 /* pcie2 */
1128 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1129         { .name = "pcie", .rst_shift = 1 },
1130 };
1131 
1132 /* pcie2 */
1133 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1134         .name           = "pcie2",
1135         .class          = &dra7xx_pciess_hwmod_class,
1136         .clkdm_name     = "pcie_clkdm",
1137         .rst_lines      = dra7xx_pciess2_resets,
1138         .rst_lines_cnt  = ARRAY_SIZE(dra7xx_pciess2_resets),
1139         .main_clk       = "l4_root_clk_div",
1140         .prcm = {
1141                 .omap4 = {
1142                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1143                         .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1144                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1145                         .modulemode   = MODULEMODE_SWCTRL,
1146                 },
1147         },
1148 };
1149 
1150 /*
1151  * 'qspi' class
1152  *
1153  */
1154 
1155 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1156         .rev_offs       = 0,
1157         .sysc_offs      = 0x0010,
1158         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1160                            SIDLE_SMART_WKUP),
1161         .sysc_fields    = &omap_hwmod_sysc_type2,
1162 };
1163 
1164 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1165         .name   = "qspi",
1166         .sysc   = &dra7xx_qspi_sysc,
1167 };
1168 
1169 /* qspi */
1170 static struct omap_hwmod dra7xx_qspi_hwmod = {
1171         .name           = "qspi",
1172         .class          = &dra7xx_qspi_hwmod_class,
1173         .clkdm_name     = "l4per2_clkdm",
1174         .main_clk       = "qspi_gfclk_div",
1175         .prcm = {
1176                 .omap4 = {
1177                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1178                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1179                         .modulemode   = MODULEMODE_SWCTRL,
1180                 },
1181         },
1182 };
1183 
1184 /*
1185  * 'rtcss' class
1186  *
1187  */
1188 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1189         .rev_offs       = 0x0074,
1190         .sysc_offs      = 0x0078,
1191         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1192         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1193                            SIDLE_SMART_WKUP),
1194         .sysc_fields    = &omap_hwmod_sysc_type3,
1195 };
1196 
1197 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1198         .name   = "rtcss",
1199         .sysc   = &dra7xx_rtcss_sysc,
1200         .unlock = &omap_hwmod_rtc_unlock,
1201         .lock   = &omap_hwmod_rtc_lock,
1202 };
1203 
1204 /* rtcss */
1205 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1206         .name           = "rtcss",
1207         .class          = &dra7xx_rtcss_hwmod_class,
1208         .clkdm_name     = "rtc_clkdm",
1209         .main_clk       = "sys_32k_ck",
1210         .prcm = {
1211                 .omap4 = {
1212                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1213                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1214                         .modulemode   = MODULEMODE_SWCTRL,
1215                 },
1216         },
1217 };
1218 
1219 /*
1220  * 'sata' class
1221  *
1222  */
1223 
1224 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1225         .rev_offs       = 0x00fc,
1226         .sysc_offs      = 0x0000,
1227         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1228         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1229                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1230                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1231         .sysc_fields    = &omap_hwmod_sysc_type2,
1232 };
1233 
1234 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1235         .name   = "sata",
1236         .sysc   = &dra7xx_sata_sysc,
1237 };
1238 
1239 /* sata */
1240 
1241 static struct omap_hwmod dra7xx_sata_hwmod = {
1242         .name           = "sata",
1243         .class          = &dra7xx_sata_hwmod_class,
1244         .clkdm_name     = "l3init_clkdm",
1245         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1246         .main_clk       = "func_48m_fclk",
1247         .mpu_rt_idx     = 1,
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1251                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_SWCTRL,
1253                 },
1254         },
1255 };
1256 
1257 /*
1258  * 'smartreflex' class
1259  *
1260  */
1261 
1262 /* The IP is not compliant to type1 / type2 scheme */
1263 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1264         .rev_offs       = -ENODEV,
1265         .sysc_offs      = 0x0038,
1266         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1267         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1268                            SIDLE_SMART_WKUP),
1269         .sysc_fields    = &omap36xx_sr_sysc_fields,
1270 };
1271 
1272 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1273         .name   = "smartreflex",
1274         .sysc   = &dra7xx_smartreflex_sysc,
1275 };
1276 
1277 /* smartreflex_core */
1278 /* smartreflex_core dev_attr */
1279 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1280         .sensor_voltdm_name     = "core",
1281 };
1282 
1283 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1284         .name           = "smartreflex_core",
1285         .class          = &dra7xx_smartreflex_hwmod_class,
1286         .clkdm_name     = "coreaon_clkdm",
1287         .main_clk       = "wkupaon_iclk_mux",
1288         .prcm = {
1289                 .omap4 = {
1290                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1291                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1292                         .modulemode   = MODULEMODE_SWCTRL,
1293                 },
1294         },
1295         .dev_attr       = &smartreflex_core_dev_attr,
1296 };
1297 
1298 /* smartreflex_mpu */
1299 /* smartreflex_mpu dev_attr */
1300 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1301         .sensor_voltdm_name     = "mpu",
1302 };
1303 
1304 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1305         .name           = "smartreflex_mpu",
1306         .class          = &dra7xx_smartreflex_hwmod_class,
1307         .clkdm_name     = "coreaon_clkdm",
1308         .main_clk       = "wkupaon_iclk_mux",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1312                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1313                         .modulemode   = MODULEMODE_SWCTRL,
1314                 },
1315         },
1316         .dev_attr       = &smartreflex_mpu_dev_attr,
1317 };
1318 
1319 /*
1320  * 'spinlock' class
1321  *
1322  */
1323 
1324 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1325         .rev_offs       = 0x0000,
1326         .sysc_offs      = 0x0010,
1327         .syss_offs      = 0x0014,
1328         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1329                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1330                            SYSS_HAS_RESET_STATUS),
1331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332         .sysc_fields    = &omap_hwmod_sysc_type1,
1333 };
1334 
1335 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1336         .name   = "spinlock",
1337         .sysc   = &dra7xx_spinlock_sysc,
1338 };
1339 
1340 /* spinlock */
1341 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1342         .name           = "spinlock",
1343         .class          = &dra7xx_spinlock_hwmod_class,
1344         .clkdm_name     = "l4cfg_clkdm",
1345         .main_clk       = "l3_iclk_div",
1346         .prcm = {
1347                 .omap4 = {
1348                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1349                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1350                 },
1351         },
1352 };
1353 
1354 /*
1355  * 'timer' class
1356  *
1357  * This class contains several variants: ['timer_1ms', 'timer_secure',
1358  * 'timer']
1359  */
1360 
1361 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1362         .rev_offs       = 0x0000,
1363         .sysc_offs      = 0x0010,
1364         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1365                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1367                            SIDLE_SMART_WKUP),
1368         .sysc_fields    = &omap_hwmod_sysc_type2,
1369 };
1370 
1371 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1372         .name   = "timer",
1373         .sysc   = &dra7xx_timer_1ms_sysc,
1374 };
1375 
1376 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1377         .rev_offs       = 0x0000,
1378         .sysc_offs      = 0x0010,
1379         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1380                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1381         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1382                            SIDLE_SMART_WKUP),
1383         .sysc_fields    = &omap_hwmod_sysc_type2,
1384 };
1385 
1386 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1387         .name   = "timer",
1388         .sysc   = &dra7xx_timer_sysc,
1389 };
1390 
1391 /* timer1 */
1392 static struct omap_hwmod dra7xx_timer1_hwmod = {
1393         .name           = "timer1",
1394         .class          = &dra7xx_timer_1ms_hwmod_class,
1395         .clkdm_name     = "wkupaon_clkdm",
1396         .main_clk       = "timer1_gfclk_mux",
1397         .prcm = {
1398                 .omap4 = {
1399                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1400                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1401                         .modulemode   = MODULEMODE_SWCTRL,
1402                 },
1403         },
1404 };
1405 
1406 /* timer2 */
1407 static struct omap_hwmod dra7xx_timer2_hwmod = {
1408         .name           = "timer2",
1409         .class          = &dra7xx_timer_1ms_hwmod_class,
1410         .clkdm_name     = "l4per_clkdm",
1411         .main_clk       = "timer2_gfclk_mux",
1412         .prcm = {
1413                 .omap4 = {
1414                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1415                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1416                         .modulemode   = MODULEMODE_SWCTRL,
1417                 },
1418         },
1419 };
1420 
1421 /* timer3 */
1422 static struct omap_hwmod dra7xx_timer3_hwmod = {
1423         .name           = "timer3",
1424         .class          = &dra7xx_timer_hwmod_class,
1425         .clkdm_name     = "l4per_clkdm",
1426         .main_clk       = "timer3_gfclk_mux",
1427         .prcm = {
1428                 .omap4 = {
1429                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1430                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1431                         .modulemode   = MODULEMODE_SWCTRL,
1432                 },
1433         },
1434 };
1435 
1436 /* timer4 */
1437 static struct omap_hwmod dra7xx_timer4_hwmod = {
1438         .name           = "timer4",
1439         .class          = &dra7xx_timer_hwmod_class,
1440         .clkdm_name     = "l4per_clkdm",
1441         .main_clk       = "timer4_gfclk_mux",
1442         .prcm = {
1443                 .omap4 = {
1444                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1445                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1446                         .modulemode   = MODULEMODE_SWCTRL,
1447                 },
1448         },
1449 };
1450 
1451 /* timer5 */
1452 static struct omap_hwmod dra7xx_timer5_hwmod = {
1453         .name           = "timer5",
1454         .class          = &dra7xx_timer_hwmod_class,
1455         .clkdm_name     = "ipu_clkdm",
1456         .main_clk       = "timer5_gfclk_mux",
1457         .prcm = {
1458                 .omap4 = {
1459                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1460                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1461                         .modulemode   = MODULEMODE_SWCTRL,
1462                 },
1463         },
1464 };
1465 
1466 /* timer6 */
1467 static struct omap_hwmod dra7xx_timer6_hwmod = {
1468         .name           = "timer6",
1469         .class          = &dra7xx_timer_hwmod_class,
1470         .clkdm_name     = "ipu_clkdm",
1471         .main_clk       = "timer6_gfclk_mux",
1472         .prcm = {
1473                 .omap4 = {
1474                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1475                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1476                         .modulemode   = MODULEMODE_SWCTRL,
1477                 },
1478         },
1479 };
1480 
1481 /* timer7 */
1482 static struct omap_hwmod dra7xx_timer7_hwmod = {
1483         .name           = "timer7",
1484         .class          = &dra7xx_timer_hwmod_class,
1485         .clkdm_name     = "ipu_clkdm",
1486         .main_clk       = "timer7_gfclk_mux",
1487         .prcm = {
1488                 .omap4 = {
1489                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1490                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1491                         .modulemode   = MODULEMODE_SWCTRL,
1492                 },
1493         },
1494 };
1495 
1496 /* timer8 */
1497 static struct omap_hwmod dra7xx_timer8_hwmod = {
1498         .name           = "timer8",
1499         .class          = &dra7xx_timer_hwmod_class,
1500         .clkdm_name     = "ipu_clkdm",
1501         .main_clk       = "timer8_gfclk_mux",
1502         .prcm = {
1503                 .omap4 = {
1504                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1505                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1506                         .modulemode   = MODULEMODE_SWCTRL,
1507                 },
1508         },
1509 };
1510 
1511 /* timer9 */
1512 static struct omap_hwmod dra7xx_timer9_hwmod = {
1513         .name           = "timer9",
1514         .class          = &dra7xx_timer_hwmod_class,
1515         .clkdm_name     = "l4per_clkdm",
1516         .main_clk       = "timer9_gfclk_mux",
1517         .prcm = {
1518                 .omap4 = {
1519                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1520                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1521                         .modulemode   = MODULEMODE_SWCTRL,
1522                 },
1523         },
1524 };
1525 
1526 /* timer10 */
1527 static struct omap_hwmod dra7xx_timer10_hwmod = {
1528         .name           = "timer10",
1529         .class          = &dra7xx_timer_1ms_hwmod_class,
1530         .clkdm_name     = "l4per_clkdm",
1531         .main_clk       = "timer10_gfclk_mux",
1532         .prcm = {
1533                 .omap4 = {
1534                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1535                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1536                         .modulemode   = MODULEMODE_SWCTRL,
1537                 },
1538         },
1539 };
1540 
1541 /* timer11 */
1542 static struct omap_hwmod dra7xx_timer11_hwmod = {
1543         .name           = "timer11",
1544         .class          = &dra7xx_timer_hwmod_class,
1545         .clkdm_name     = "l4per_clkdm",
1546         .main_clk       = "timer11_gfclk_mux",
1547         .prcm = {
1548                 .omap4 = {
1549                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1550                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1551                         .modulemode   = MODULEMODE_SWCTRL,
1552                 },
1553         },
1554 };
1555 
1556 /* timer12 */
1557 static struct omap_hwmod dra7xx_timer12_hwmod = {
1558         .name           = "timer12",
1559         .class          = &dra7xx_timer_hwmod_class,
1560         .clkdm_name     = "wkupaon_clkdm",
1561         .main_clk       = "secure_32k_clk_src_ck",
1562         .prcm = {
1563                 .omap4 = {
1564                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
1565                         .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
1566                 },
1567         },
1568 };
1569 
1570 /* timer13 */
1571 static struct omap_hwmod dra7xx_timer13_hwmod = {
1572         .name           = "timer13",
1573         .class          = &dra7xx_timer_hwmod_class,
1574         .clkdm_name     = "l4per3_clkdm",
1575         .main_clk       = "timer13_gfclk_mux",
1576         .prcm = {
1577                 .omap4 = {
1578                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1579                         .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1580                         .modulemode   = MODULEMODE_SWCTRL,
1581                 },
1582         },
1583 };
1584 
1585 /* timer14 */
1586 static struct omap_hwmod dra7xx_timer14_hwmod = {
1587         .name           = "timer14",
1588         .class          = &dra7xx_timer_hwmod_class,
1589         .clkdm_name     = "l4per3_clkdm",
1590         .main_clk       = "timer14_gfclk_mux",
1591         .prcm = {
1592                 .omap4 = {
1593                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1594                         .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1595                         .modulemode   = MODULEMODE_SWCTRL,
1596                 },
1597         },
1598 };
1599 
1600 /* timer15 */
1601 static struct omap_hwmod dra7xx_timer15_hwmod = {
1602         .name           = "timer15",
1603         .class          = &dra7xx_timer_hwmod_class,
1604         .clkdm_name     = "l4per3_clkdm",
1605         .main_clk       = "timer15_gfclk_mux",
1606         .prcm = {
1607                 .omap4 = {
1608                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1609                         .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1610                         .modulemode   = MODULEMODE_SWCTRL,
1611                 },
1612         },
1613 };
1614 
1615 /* timer16 */
1616 static struct omap_hwmod dra7xx_timer16_hwmod = {
1617         .name           = "timer16",
1618         .class          = &dra7xx_timer_hwmod_class,
1619         .clkdm_name     = "l4per3_clkdm",
1620         .main_clk       = "timer16_gfclk_mux",
1621         .prcm = {
1622                 .omap4 = {
1623                         .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1624                         .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1625                         .modulemode   = MODULEMODE_SWCTRL,
1626                 },
1627         },
1628 };
1629 
1630 /* DES (the 'P' (public) device) */
1631 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
1632         .rev_offs       = 0x0030,
1633         .sysc_offs      = 0x0034,
1634         .syss_offs      = 0x0038,
1635         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1636 };
1637 
1638 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
1639         .name   = "des",
1640         .sysc   = &dra7xx_des_sysc,
1641 };
1642 
1643 /* DES */
1644 static struct omap_hwmod dra7xx_des_hwmod = {
1645         .name           = "des",
1646         .class          = &dra7xx_des_hwmod_class,
1647         .clkdm_name     = "l4sec_clkdm",
1648         .main_clk       = "l3_iclk_div",
1649         .prcm = {
1650                 .omap4 = {
1651                         .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1652                         .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1653                         .modulemode   = MODULEMODE_HWCTRL,
1654                 },
1655         },
1656 };
1657 
1658 /* rng */
1659 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
1660         .rev_offs       = 0x1fe0,
1661         .sysc_offs      = 0x1fe4,
1662         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
1663         .idlemodes      = SIDLE_FORCE | SIDLE_NO,
1664         .sysc_fields    = &omap_hwmod_sysc_type1,
1665 };
1666 
1667 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
1668         .name           = "rng",
1669         .sysc           = &dra7xx_rng_sysc,
1670 };
1671 
1672 static struct omap_hwmod dra7xx_rng_hwmod = {
1673         .name           = "rng",
1674         .class          = &dra7xx_rng_hwmod_class,
1675         .flags          = HWMOD_SWSUP_SIDLE,
1676         .clkdm_name     = "l4sec_clkdm",
1677         .prcm = {
1678                 .omap4 = {
1679                         .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
1680                         .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
1681                         .modulemode   = MODULEMODE_HWCTRL,
1682                 },
1683         },
1684 };
1685 
1686 /*
1687  * 'usb_otg_ss' class
1688  *
1689  */
1690 
1691 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
1692         .rev_offs       = 0x0000,
1693         .sysc_offs      = 0x0010,
1694         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1695                            SYSC_HAS_SIDLEMODE),
1696         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1697                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1698                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1699         .sysc_fields    = &omap_hwmod_sysc_type2,
1700 };
1701 
1702 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1703         .name   = "usb_otg_ss",
1704         .sysc   = &dra7xx_usb_otg_ss_sysc,
1705 };
1706 
1707 /* usb_otg_ss1 */
1708 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1709         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1710 };
1711 
1712 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1713         .name           = "usb_otg_ss1",
1714         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1715         .clkdm_name     = "l3init_clkdm",
1716         .main_clk       = "dpll_core_h13x2_ck",
1717         .flags          = HWMOD_CLKDM_NOAUTO,
1718         .prcm = {
1719                 .omap4 = {
1720                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1721                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1722                         .modulemode   = MODULEMODE_HWCTRL,
1723                 },
1724         },
1725         .opt_clks       = usb_otg_ss1_opt_clks,
1726         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1727 };
1728 
1729 /* usb_otg_ss2 */
1730 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1731         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1732 };
1733 
1734 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1735         .name           = "usb_otg_ss2",
1736         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1737         .clkdm_name     = "l3init_clkdm",
1738         .main_clk       = "dpll_core_h13x2_ck",
1739         .flags          = HWMOD_CLKDM_NOAUTO,
1740         .prcm = {
1741                 .omap4 = {
1742                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1743                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1744                         .modulemode   = MODULEMODE_HWCTRL,
1745                 },
1746         },
1747         .opt_clks       = usb_otg_ss2_opt_clks,
1748         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1749 };
1750 
1751 /* usb_otg_ss3 */
1752 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1753         .name           = "usb_otg_ss3",
1754         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1755         .clkdm_name     = "l3init_clkdm",
1756         .main_clk       = "dpll_core_h13x2_ck",
1757         .prcm = {
1758                 .omap4 = {
1759                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1760                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1761                         .modulemode   = MODULEMODE_HWCTRL,
1762                 },
1763         },
1764 };
1765 
1766 /* usb_otg_ss4 */
1767 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1768         .name           = "usb_otg_ss4",
1769         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1770         .clkdm_name     = "l3init_clkdm",
1771         .main_clk       = "dpll_core_h13x2_ck",
1772         .prcm = {
1773                 .omap4 = {
1774                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1775                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1776                         .modulemode   = MODULEMODE_HWCTRL,
1777                 },
1778         },
1779 };
1780 
1781 /*
1782  * 'vcp' class
1783  *
1784  */
1785 
1786 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1787         .name   = "vcp",
1788 };
1789 
1790 /* vcp1 */
1791 static struct omap_hwmod dra7xx_vcp1_hwmod = {
1792         .name           = "vcp1",
1793         .class          = &dra7xx_vcp_hwmod_class,
1794         .clkdm_name     = "l3main1_clkdm",
1795         .main_clk       = "l3_iclk_div",
1796         .prcm = {
1797                 .omap4 = {
1798                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1799                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1800                 },
1801         },
1802 };
1803 
1804 /* vcp2 */
1805 static struct omap_hwmod dra7xx_vcp2_hwmod = {
1806         .name           = "vcp2",
1807         .class          = &dra7xx_vcp_hwmod_class,
1808         .clkdm_name     = "l3main1_clkdm",
1809         .main_clk       = "l3_iclk_div",
1810         .prcm = {
1811                 .omap4 = {
1812                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1813                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1814                 },
1815         },
1816 };
1817 
1818 /*
1819  * 'wd_timer' class
1820  *
1821  */
1822 
1823 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1824         .rev_offs       = 0x0000,
1825         .sysc_offs      = 0x0010,
1826         .syss_offs      = 0x0014,
1827         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1828                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1830                            SIDLE_SMART_WKUP),
1831         .sysc_fields    = &omap_hwmod_sysc_type1,
1832 };
1833 
1834 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1835         .name           = "wd_timer",
1836         .sysc           = &dra7xx_wd_timer_sysc,
1837         .pre_shutdown   = &omap2_wd_timer_disable,
1838         .reset          = &omap2_wd_timer_reset,
1839 };
1840 
1841 /* wd_timer2 */
1842 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1843         .name           = "wd_timer2",
1844         .class          = &dra7xx_wd_timer_hwmod_class,
1845         .clkdm_name     = "wkupaon_clkdm",
1846         .main_clk       = "sys_32k_ck",
1847         .prcm = {
1848                 .omap4 = {
1849                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1850                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1851                         .modulemode   = MODULEMODE_SWCTRL,
1852                 },
1853         },
1854 };
1855 
1856 
1857 /*
1858  * Interfaces
1859  */
1860 
1861 /* l3_main_1 -> dmm */
1862 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
1863         .master         = &dra7xx_l3_main_1_hwmod,
1864         .slave          = &dra7xx_dmm_hwmod,
1865         .clk            = "l3_iclk_div",
1866         .user           = OCP_USER_SDMA,
1867 };
1868 
1869 /* l3_main_2 -> l3_instr */
1870 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1871         .master         = &dra7xx_l3_main_2_hwmod,
1872         .slave          = &dra7xx_l3_instr_hwmod,
1873         .clk            = "l3_iclk_div",
1874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1875 };
1876 
1877 /* l4_cfg -> l3_main_1 */
1878 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1879         .master         = &dra7xx_l4_cfg_hwmod,
1880         .slave          = &dra7xx_l3_main_1_hwmod,
1881         .clk            = "l3_iclk_div",
1882         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1883 };
1884 
1885 /* mpu -> l3_main_1 */
1886 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1887         .master         = &dra7xx_mpu_hwmod,
1888         .slave          = &dra7xx_l3_main_1_hwmod,
1889         .clk            = "l3_iclk_div",
1890         .user           = OCP_USER_MPU,
1891 };
1892 
1893 /* l3_main_1 -> l3_main_2 */
1894 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1895         .master         = &dra7xx_l3_main_1_hwmod,
1896         .slave          = &dra7xx_l3_main_2_hwmod,
1897         .clk            = "l3_iclk_div",
1898         .user           = OCP_USER_MPU,
1899 };
1900 
1901 /* l4_cfg -> l3_main_2 */
1902 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1903         .master         = &dra7xx_l4_cfg_hwmod,
1904         .slave          = &dra7xx_l3_main_2_hwmod,
1905         .clk            = "l3_iclk_div",
1906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1907 };
1908 
1909 /* l3_main_1 -> l4_cfg */
1910 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1911         .master         = &dra7xx_l3_main_1_hwmod,
1912         .slave          = &dra7xx_l4_cfg_hwmod,
1913         .clk            = "l3_iclk_div",
1914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1915 };
1916 
1917 /* l3_main_1 -> l4_per1 */
1918 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1919         .master         = &dra7xx_l3_main_1_hwmod,
1920         .slave          = &dra7xx_l4_per1_hwmod,
1921         .clk            = "l3_iclk_div",
1922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1923 };
1924 
1925 /* l3_main_1 -> l4_per2 */
1926 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1927         .master         = &dra7xx_l3_main_1_hwmod,
1928         .slave          = &dra7xx_l4_per2_hwmod,
1929         .clk            = "l3_iclk_div",
1930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1931 };
1932 
1933 /* l3_main_1 -> l4_per3 */
1934 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1935         .master         = &dra7xx_l3_main_1_hwmod,
1936         .slave          = &dra7xx_l4_per3_hwmod,
1937         .clk            = "l3_iclk_div",
1938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1939 };
1940 
1941 /* l3_main_1 -> l4_wkup */
1942 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1943         .master         = &dra7xx_l3_main_1_hwmod,
1944         .slave          = &dra7xx_l4_wkup_hwmod,
1945         .clk            = "wkupaon_iclk_mux",
1946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1947 };
1948 
1949 /* l4_per2 -> atl */
1950 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1951         .master         = &dra7xx_l4_per2_hwmod,
1952         .slave          = &dra7xx_atl_hwmod,
1953         .clk            = "l3_iclk_div",
1954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1955 };
1956 
1957 /* l3_main_1 -> bb2d */
1958 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1959         .master         = &dra7xx_l3_main_1_hwmod,
1960         .slave          = &dra7xx_bb2d_hwmod,
1961         .clk            = "l3_iclk_div",
1962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1963 };
1964 
1965 /* l4_wkup -> counter_32k */
1966 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1967         .master         = &dra7xx_l4_wkup_hwmod,
1968         .slave          = &dra7xx_counter_32k_hwmod,
1969         .clk            = "wkupaon_iclk_mux",
1970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1971 };
1972 
1973 /* l4_wkup -> ctrl_module_wkup */
1974 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1975         .master         = &dra7xx_l4_wkup_hwmod,
1976         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
1977         .clk            = "wkupaon_iclk_mux",
1978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1979 };
1980 
1981 /* l4_wkup -> dcan1 */
1982 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
1983         .master         = &dra7xx_l4_wkup_hwmod,
1984         .slave          = &dra7xx_dcan1_hwmod,
1985         .clk            = "wkupaon_iclk_mux",
1986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1987 };
1988 
1989 /* l4_per2 -> dcan2 */
1990 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
1991         .master         = &dra7xx_l4_per2_hwmod,
1992         .slave          = &dra7xx_dcan2_hwmod,
1993         .clk            = "l3_iclk_div",
1994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1995 };
1996 
1997 /* l4_cfg -> dma_system */
1998 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
1999         .master         = &dra7xx_l4_cfg_hwmod,
2000         .slave          = &dra7xx_dma_system_hwmod,
2001         .clk            = "l3_iclk_div",
2002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2003 };
2004 
2005 /* l3_main_1 -> tpcc */
2006 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2007         .master         = &dra7xx_l3_main_1_hwmod,
2008         .slave          = &dra7xx_tpcc_hwmod,
2009         .clk            = "l3_iclk_div",
2010         .user           = OCP_USER_MPU,
2011 };
2012 
2013 /* l3_main_1 -> tptc0 */
2014 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2015         .master         = &dra7xx_l3_main_1_hwmod,
2016         .slave          = &dra7xx_tptc0_hwmod,
2017         .clk            = "l3_iclk_div",
2018         .user           = OCP_USER_MPU,
2019 };
2020 
2021 /* l3_main_1 -> tptc1 */
2022 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2023         .master         = &dra7xx_l3_main_1_hwmod,
2024         .slave          = &dra7xx_tptc1_hwmod,
2025         .clk            = "l3_iclk_div",
2026         .user           = OCP_USER_MPU,
2027 };
2028 
2029 /* l3_main_1 -> dss */
2030 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2031         .master         = &dra7xx_l3_main_1_hwmod,
2032         .slave          = &dra7xx_dss_hwmod,
2033         .clk            = "l3_iclk_div",
2034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036 
2037 /* l3_main_1 -> dispc */
2038 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2039         .master         = &dra7xx_l3_main_1_hwmod,
2040         .slave          = &dra7xx_dss_dispc_hwmod,
2041         .clk            = "l3_iclk_div",
2042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2043 };
2044 
2045 /* l3_main_1 -> dispc */
2046 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2047         .master         = &dra7xx_l3_main_1_hwmod,
2048         .slave          = &dra7xx_dss_hdmi_hwmod,
2049         .clk            = "l3_iclk_div",
2050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2051 };
2052 
2053 /* l3_main_1 -> aes1 */
2054 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2055         .master         = &dra7xx_l3_main_1_hwmod,
2056         .slave          = &dra7xx_aes1_hwmod,
2057         .clk            = "l3_iclk_div",
2058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2059 };
2060 
2061 /* l3_main_1 -> aes2 */
2062 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
2063         .master         = &dra7xx_l3_main_1_hwmod,
2064         .slave          = &dra7xx_aes2_hwmod,
2065         .clk            = "l3_iclk_div",
2066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2067 };
2068 
2069 /* l3_main_1 -> sha0 */
2070 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
2071         .master         = &dra7xx_l3_main_1_hwmod,
2072         .slave          = &dra7xx_sha0_hwmod,
2073         .clk            = "l3_iclk_div",
2074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2075 };
2076 
2077 /* l4_per1 -> elm */
2078 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2079         .master         = &dra7xx_l4_per1_hwmod,
2080         .slave          = &dra7xx_elm_hwmod,
2081         .clk            = "l3_iclk_div",
2082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2083 };
2084 
2085 /* l3_main_1 -> gpmc */
2086 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2087         .master         = &dra7xx_l3_main_1_hwmod,
2088         .slave          = &dra7xx_gpmc_hwmod,
2089         .clk            = "l3_iclk_div",
2090         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2091 };
2092 
2093 /* l4_per1 -> hdq1w */
2094 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2095         .master         = &dra7xx_l4_per1_hwmod,
2096         .slave          = &dra7xx_hdq1w_hwmod,
2097         .clk            = "l3_iclk_div",
2098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2099 };
2100 
2101 /* l4_cfg -> mailbox1 */
2102 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2103         .master         = &dra7xx_l4_cfg_hwmod,
2104         .slave          = &dra7xx_mailbox1_hwmod,
2105         .clk            = "l3_iclk_div",
2106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108 
2109 /* l4_per3 -> mailbox2 */
2110 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2111         .master         = &dra7xx_l4_per3_hwmod,
2112         .slave          = &dra7xx_mailbox2_hwmod,
2113         .clk            = "l3_iclk_div",
2114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2115 };
2116 
2117 /* l4_per3 -> mailbox3 */
2118 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2119         .master         = &dra7xx_l4_per3_hwmod,
2120         .slave          = &dra7xx_mailbox3_hwmod,
2121         .clk            = "l3_iclk_div",
2122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124 
2125 /* l4_per3 -> mailbox4 */
2126 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2127         .master         = &dra7xx_l4_per3_hwmod,
2128         .slave          = &dra7xx_mailbox4_hwmod,
2129         .clk            = "l3_iclk_div",
2130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132 
2133 /* l4_per3 -> mailbox5 */
2134 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2135         .master         = &dra7xx_l4_per3_hwmod,
2136         .slave          = &dra7xx_mailbox5_hwmod,
2137         .clk            = "l3_iclk_div",
2138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140 
2141 /* l4_per3 -> mailbox6 */
2142 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2143         .master         = &dra7xx_l4_per3_hwmod,
2144         .slave          = &dra7xx_mailbox6_hwmod,
2145         .clk            = "l3_iclk_div",
2146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2147 };
2148 
2149 /* l4_per3 -> mailbox7 */
2150 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2151         .master         = &dra7xx_l4_per3_hwmod,
2152         .slave          = &dra7xx_mailbox7_hwmod,
2153         .clk            = "l3_iclk_div",
2154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2155 };
2156 
2157 /* l4_per3 -> mailbox8 */
2158 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2159         .master         = &dra7xx_l4_per3_hwmod,
2160         .slave          = &dra7xx_mailbox8_hwmod,
2161         .clk            = "l3_iclk_div",
2162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164 
2165 /* l4_per3 -> mailbox9 */
2166 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2167         .master         = &dra7xx_l4_per3_hwmod,
2168         .slave          = &dra7xx_mailbox9_hwmod,
2169         .clk            = "l3_iclk_div",
2170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172 
2173 /* l4_per3 -> mailbox10 */
2174 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2175         .master         = &dra7xx_l4_per3_hwmod,
2176         .slave          = &dra7xx_mailbox10_hwmod,
2177         .clk            = "l3_iclk_div",
2178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2179 };
2180 
2181 /* l4_per3 -> mailbox11 */
2182 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2183         .master         = &dra7xx_l4_per3_hwmod,
2184         .slave          = &dra7xx_mailbox11_hwmod,
2185         .clk            = "l3_iclk_div",
2186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2187 };
2188 
2189 /* l4_per3 -> mailbox12 */
2190 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2191         .master         = &dra7xx_l4_per3_hwmod,
2192         .slave          = &dra7xx_mailbox12_hwmod,
2193         .clk            = "l3_iclk_div",
2194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196 
2197 /* l4_per3 -> mailbox13 */
2198 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2199         .master         = &dra7xx_l4_per3_hwmod,
2200         .slave          = &dra7xx_mailbox13_hwmod,
2201         .clk            = "l3_iclk_div",
2202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2203 };
2204 
2205 /* l4_cfg -> mpu */
2206 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2207         .master         = &dra7xx_l4_cfg_hwmod,
2208         .slave          = &dra7xx_mpu_hwmod,
2209         .clk            = "l3_iclk_div",
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212 
2213 /* l4_cfg -> ocp2scp1 */
2214 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2215         .master         = &dra7xx_l4_cfg_hwmod,
2216         .slave          = &dra7xx_ocp2scp1_hwmod,
2217         .clk            = "l4_root_clk_div",
2218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220 
2221 /* l4_cfg -> ocp2scp3 */
2222 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2223         .master         = &dra7xx_l4_cfg_hwmod,
2224         .slave          = &dra7xx_ocp2scp3_hwmod,
2225         .clk            = "l4_root_clk_div",
2226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2227 };
2228 
2229 /* l3_main_1 -> pciess1 */
2230 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2231         .master         = &dra7xx_l3_main_1_hwmod,
2232         .slave          = &dra7xx_pciess1_hwmod,
2233         .clk            = "l3_iclk_div",
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236 
2237 /* l4_cfg -> pciess1 */
2238 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2239         .master         = &dra7xx_l4_cfg_hwmod,
2240         .slave          = &dra7xx_pciess1_hwmod,
2241         .clk            = "l4_root_clk_div",
2242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2243 };
2244 
2245 /* l3_main_1 -> pciess2 */
2246 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2247         .master         = &dra7xx_l3_main_1_hwmod,
2248         .slave          = &dra7xx_pciess2_hwmod,
2249         .clk            = "l3_iclk_div",
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252 
2253 /* l4_cfg -> pciess2 */
2254 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2255         .master         = &dra7xx_l4_cfg_hwmod,
2256         .slave          = &dra7xx_pciess2_hwmod,
2257         .clk            = "l4_root_clk_div",
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260 
2261 /* l3_main_1 -> qspi */
2262 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2263         .master         = &dra7xx_l3_main_1_hwmod,
2264         .slave          = &dra7xx_qspi_hwmod,
2265         .clk            = "l3_iclk_div",
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268 
2269 /* l4_per3 -> rtcss */
2270 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2271         .master         = &dra7xx_l4_per3_hwmod,
2272         .slave          = &dra7xx_rtcss_hwmod,
2273         .clk            = "l4_root_clk_div",
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276 
2277 /* l4_cfg -> sata */
2278 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2279         .master         = &dra7xx_l4_cfg_hwmod,
2280         .slave          = &dra7xx_sata_hwmod,
2281         .clk            = "l3_iclk_div",
2282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284 
2285 /* l4_cfg -> smartreflex_core */
2286 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2287         .master         = &dra7xx_l4_cfg_hwmod,
2288         .slave          = &dra7xx_smartreflex_core_hwmod,
2289         .clk            = "l4_root_clk_div",
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292 
2293 /* l4_cfg -> smartreflex_mpu */
2294 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2295         .master         = &dra7xx_l4_cfg_hwmod,
2296         .slave          = &dra7xx_smartreflex_mpu_hwmod,
2297         .clk            = "l4_root_clk_div",
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300 
2301 /* l4_cfg -> spinlock */
2302 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2303         .master         = &dra7xx_l4_cfg_hwmod,
2304         .slave          = &dra7xx_spinlock_hwmod,
2305         .clk            = "l3_iclk_div",
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308 
2309 /* l4_wkup -> timer1 */
2310 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2311         .master         = &dra7xx_l4_wkup_hwmod,
2312         .slave          = &dra7xx_timer1_hwmod,
2313         .clk            = "wkupaon_iclk_mux",
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316 
2317 /* l4_per1 -> timer2 */
2318 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2319         .master         = &dra7xx_l4_per1_hwmod,
2320         .slave          = &dra7xx_timer2_hwmod,
2321         .clk            = "l3_iclk_div",
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324 
2325 /* l4_per1 -> timer3 */
2326 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2327         .master         = &dra7xx_l4_per1_hwmod,
2328         .slave          = &dra7xx_timer3_hwmod,
2329         .clk            = "l3_iclk_div",
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332 
2333 /* l4_per1 -> timer4 */
2334 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2335         .master         = &dra7xx_l4_per1_hwmod,
2336         .slave          = &dra7xx_timer4_hwmod,
2337         .clk            = "l3_iclk_div",
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339 };
2340 
2341 /* l4_per3 -> timer5 */
2342 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2343         .master         = &dra7xx_l4_per3_hwmod,
2344         .slave          = &dra7xx_timer5_hwmod,
2345         .clk            = "l3_iclk_div",
2346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2347 };
2348 
2349 /* l4_per3 -> timer6 */
2350 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2351         .master         = &dra7xx_l4_per3_hwmod,
2352         .slave          = &dra7xx_timer6_hwmod,
2353         .clk            = "l3_iclk_div",
2354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356 
2357 /* l4_per3 -> timer7 */
2358 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2359         .master         = &dra7xx_l4_per3_hwmod,
2360         .slave          = &dra7xx_timer7_hwmod,
2361         .clk            = "l3_iclk_div",
2362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2363 };
2364 
2365 /* l4_per3 -> timer8 */
2366 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2367         .master         = &dra7xx_l4_per3_hwmod,
2368         .slave          = &dra7xx_timer8_hwmod,
2369         .clk            = "l3_iclk_div",
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372 
2373 /* l4_per1 -> timer9 */
2374 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2375         .master         = &dra7xx_l4_per1_hwmod,
2376         .slave          = &dra7xx_timer9_hwmod,
2377         .clk            = "l3_iclk_div",
2378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380 
2381 /* l4_per1 -> timer10 */
2382 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2383         .master         = &dra7xx_l4_per1_hwmod,
2384         .slave          = &dra7xx_timer10_hwmod,
2385         .clk            = "l3_iclk_div",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388 
2389 /* l4_per1 -> timer11 */
2390 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2391         .master         = &dra7xx_l4_per1_hwmod,
2392         .slave          = &dra7xx_timer11_hwmod,
2393         .clk            = "l3_iclk_div",
2394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2395 };
2396 
2397 /* l4_wkup -> timer12 */
2398 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
2399         .master         = &dra7xx_l4_wkup_hwmod,
2400         .slave          = &dra7xx_timer12_hwmod,
2401         .clk            = "wkupaon_iclk_mux",
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404 
2405 /* l4_per3 -> timer13 */
2406 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
2407         .master         = &dra7xx_l4_per3_hwmod,
2408         .slave          = &dra7xx_timer13_hwmod,
2409         .clk            = "l3_iclk_div",
2410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2411 };
2412 
2413 /* l4_per3 -> timer14 */
2414 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
2415         .master         = &dra7xx_l4_per3_hwmod,
2416         .slave          = &dra7xx_timer14_hwmod,
2417         .clk            = "l3_iclk_div",
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420 
2421 /* l4_per3 -> timer15 */
2422 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
2423         .master         = &dra7xx_l4_per3_hwmod,
2424         .slave          = &dra7xx_timer15_hwmod,
2425         .clk            = "l3_iclk_div",
2426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428 
2429 /* l4_per3 -> timer16 */
2430 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
2431         .master         = &dra7xx_l4_per3_hwmod,
2432         .slave          = &dra7xx_timer16_hwmod,
2433         .clk            = "l3_iclk_div",
2434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436 
2437 /* l4_per1 -> des */
2438 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
2439         .master         = &dra7xx_l4_per1_hwmod,
2440         .slave          = &dra7xx_des_hwmod,
2441         .clk            = "l3_iclk_div",
2442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444 
2445 /* l4_per1 -> rng */
2446 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
2447         .master         = &dra7xx_l4_per1_hwmod,
2448         .slave          = &dra7xx_rng_hwmod,
2449         .user           = OCP_USER_MPU,
2450 };
2451 
2452 /* l4_per3 -> usb_otg_ss1 */
2453 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2454         .master         = &dra7xx_l4_per3_hwmod,
2455         .slave          = &dra7xx_usb_otg_ss1_hwmod,
2456         .clk            = "dpll_core_h13x2_ck",
2457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2458 };
2459 
2460 /* l4_per3 -> usb_otg_ss2 */
2461 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2462         .master         = &dra7xx_l4_per3_hwmod,
2463         .slave          = &dra7xx_usb_otg_ss2_hwmod,
2464         .clk            = "dpll_core_h13x2_ck",
2465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467 
2468 /* l4_per3 -> usb_otg_ss3 */
2469 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2470         .master         = &dra7xx_l4_per3_hwmod,
2471         .slave          = &dra7xx_usb_otg_ss3_hwmod,
2472         .clk            = "dpll_core_h13x2_ck",
2473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2474 };
2475 
2476 /* l4_per3 -> usb_otg_ss4 */
2477 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2478         .master         = &dra7xx_l4_per3_hwmod,
2479         .slave          = &dra7xx_usb_otg_ss4_hwmod,
2480         .clk            = "dpll_core_h13x2_ck",
2481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2482 };
2483 
2484 /* l3_main_1 -> vcp1 */
2485 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2486         .master         = &dra7xx_l3_main_1_hwmod,
2487         .slave          = &dra7xx_vcp1_hwmod,
2488         .clk            = "l3_iclk_div",
2489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2490 };
2491 
2492 /* l4_per2 -> vcp1 */
2493 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2494         .master         = &dra7xx_l4_per2_hwmod,
2495         .slave          = &dra7xx_vcp1_hwmod,
2496         .clk            = "l3_iclk_div",
2497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499 
2500 /* l3_main_1 -> vcp2 */
2501 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2502         .master         = &dra7xx_l3_main_1_hwmod,
2503         .slave          = &dra7xx_vcp2_hwmod,
2504         .clk            = "l3_iclk_div",
2505         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2506 };
2507 
2508 /* l4_per2 -> vcp2 */
2509 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2510         .master         = &dra7xx_l4_per2_hwmod,
2511         .slave          = &dra7xx_vcp2_hwmod,
2512         .clk            = "l3_iclk_div",
2513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2514 };
2515 
2516 /* l4_wkup -> wd_timer2 */
2517 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2518         .master         = &dra7xx_l4_wkup_hwmod,
2519         .slave          = &dra7xx_wd_timer2_hwmod,
2520         .clk            = "wkupaon_iclk_mux",
2521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2522 };
2523 
2524 /* l4_per2 -> epwmss0 */
2525 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
2526         .master         = &dra7xx_l4_per2_hwmod,
2527         .slave          = &dra7xx_epwmss0_hwmod,
2528         .clk            = "l4_root_clk_div",
2529         .user           = OCP_USER_MPU,
2530 };
2531 
2532 /* l4_per2 -> epwmss1 */
2533 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
2534         .master         = &dra7xx_l4_per2_hwmod,
2535         .slave          = &dra7xx_epwmss1_hwmod,
2536         .clk            = "l4_root_clk_div",
2537         .user           = OCP_USER_MPU,
2538 };
2539 
2540 /* l4_per2 -> epwmss2 */
2541 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
2542         .master         = &dra7xx_l4_per2_hwmod,
2543         .slave          = &dra7xx_epwmss2_hwmod,
2544         .clk            = "l4_root_clk_div",
2545         .user           = OCP_USER_MPU,
2546 };
2547 
2548 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2549         &dra7xx_l3_main_1__dmm,
2550         &dra7xx_l3_main_2__l3_instr,
2551         &dra7xx_l4_cfg__l3_main_1,
2552         &dra7xx_mpu__l3_main_1,
2553         &dra7xx_l3_main_1__l3_main_2,
2554         &dra7xx_l4_cfg__l3_main_2,
2555         &dra7xx_l3_main_1__l4_cfg,
2556         &dra7xx_l3_main_1__l4_per1,
2557         &dra7xx_l3_main_1__l4_per2,
2558         &dra7xx_l3_main_1__l4_per3,
2559         &dra7xx_l3_main_1__l4_wkup,
2560         &dra7xx_l4_per2__atl,
2561         &dra7xx_l3_main_1__bb2d,
2562         &dra7xx_l4_wkup__counter_32k,
2563         &dra7xx_l4_wkup__ctrl_module_wkup,
2564         &dra7xx_l4_wkup__dcan1,
2565         &dra7xx_l4_per2__dcan2,
2566         &dra7xx_l4_cfg__dma_system,
2567         &dra7xx_l3_main_1__tpcc,
2568         &dra7xx_l3_main_1__tptc0,
2569         &dra7xx_l3_main_1__tptc1,
2570         &dra7xx_l3_main_1__dss,
2571         &dra7xx_l3_main_1__dispc,
2572         &dra7xx_l3_main_1__hdmi,
2573         &dra7xx_l3_main_1__aes1,
2574         &dra7xx_l3_main_1__aes2,
2575         &dra7xx_l3_main_1__sha0,
2576         &dra7xx_l4_per1__elm,
2577         &dra7xx_l3_main_1__gpmc,
2578         &dra7xx_l4_per1__hdq1w,
2579         &dra7xx_l4_cfg__mailbox1,
2580         &dra7xx_l4_per3__mailbox2,
2581         &dra7xx_l4_per3__mailbox3,
2582         &dra7xx_l4_per3__mailbox4,
2583         &dra7xx_l4_per3__mailbox5,
2584         &dra7xx_l4_per3__mailbox6,
2585         &dra7xx_l4_per3__mailbox7,
2586         &dra7xx_l4_per3__mailbox8,
2587         &dra7xx_l4_per3__mailbox9,
2588         &dra7xx_l4_per3__mailbox10,
2589         &dra7xx_l4_per3__mailbox11,
2590         &dra7xx_l4_per3__mailbox12,
2591         &dra7xx_l4_per3__mailbox13,
2592         &dra7xx_l4_cfg__mpu,
2593         &dra7xx_l4_cfg__ocp2scp1,
2594         &dra7xx_l4_cfg__ocp2scp3,
2595         &dra7xx_l3_main_1__pciess1,
2596         &dra7xx_l4_cfg__pciess1,
2597         &dra7xx_l3_main_1__pciess2,
2598         &dra7xx_l4_cfg__pciess2,
2599         &dra7xx_l3_main_1__qspi,
2600         &dra7xx_l4_cfg__sata,
2601         &dra7xx_l4_cfg__smartreflex_core,
2602         &dra7xx_l4_cfg__smartreflex_mpu,
2603         &dra7xx_l4_cfg__spinlock,
2604         &dra7xx_l4_wkup__timer1,
2605         &dra7xx_l4_per1__timer2,
2606         &dra7xx_l4_per1__timer3,
2607         &dra7xx_l4_per1__timer4,
2608         &dra7xx_l4_per3__timer5,
2609         &dra7xx_l4_per3__timer6,
2610         &dra7xx_l4_per3__timer7,
2611         &dra7xx_l4_per3__timer8,
2612         &dra7xx_l4_per1__timer9,
2613         &dra7xx_l4_per1__timer10,
2614         &dra7xx_l4_per1__timer11,
2615         &dra7xx_l4_per3__timer13,
2616         &dra7xx_l4_per3__timer14,
2617         &dra7xx_l4_per3__timer15,
2618         &dra7xx_l4_per3__timer16,
2619         &dra7xx_l4_per1__des,
2620         &dra7xx_l4_per3__usb_otg_ss1,
2621         &dra7xx_l4_per3__usb_otg_ss2,
2622         &dra7xx_l4_per3__usb_otg_ss3,
2623         &dra7xx_l3_main_1__vcp1,
2624         &dra7xx_l4_per2__vcp1,
2625         &dra7xx_l3_main_1__vcp2,
2626         &dra7xx_l4_per2__vcp2,
2627         &dra7xx_l4_wkup__wd_timer2,
2628         &dra7xx_l4_per2__epwmss0,
2629         &dra7xx_l4_per2__epwmss1,
2630         &dra7xx_l4_per2__epwmss2,
2631         NULL,
2632 };
2633 
2634 /* GP-only hwmod links */
2635 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
2636         &dra7xx_l4_wkup__timer12,
2637         &dra7xx_l4_per1__rng,
2638         NULL,
2639 };
2640 
2641 /* SoC variant specific hwmod links */
2642 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
2643         &dra7xx_l4_per3__usb_otg_ss4,
2644         NULL,
2645 };
2646 
2647 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
2648         NULL,
2649 };
2650 
2651 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
2652         &dra7xx_l4_per3__usb_otg_ss4,
2653         NULL,
2654 };
2655 
2656 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
2657         NULL,
2658 };
2659 
2660 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
2661         &dra7xx_l4_per3__rtcss,
2662         NULL,
2663 };
2664 
2665 int __init dra7xx_hwmod_init(void)
2666 {
2667         int ret;
2668 
2669         omap_hwmod_init();
2670         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2671 
2672         if (!ret && soc_is_dra74x()) {
2673                 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
2674                 if (!ret)
2675                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
2676         } else if (!ret && soc_is_dra72x()) {
2677                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
2678                 if (!ret && !of_machine_is_compatible("ti,dra718"))
2679                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
2680         } else if (!ret && soc_is_dra76x()) {
2681                 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
2682 
2683                 if (!ret && soc_is_dra76x_acd()) {
2684                         ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
2685                 } else if (!ret && soc_is_dra76x_abz()) {
2686                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
2687                 }
2688         }
2689 
2690         if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
2691                 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
2692 
2693         return ret;
2694 }

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