root/arch/arm/mach-omap2/cm1_44xx.h

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   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * OMAP44xx CM1 instance offset macros
   4  *
   5  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley (paul@pwsan.com)
   9  * Rajendra Nayak (rnayak@ti.com)
  10  * Benoit Cousson (b-cousson@ti.com)
  11  *
  12  * This file is automatically generated from the OMAP hardware databases.
  13  * We respectfully ask that any modifications to this file be coordinated
  14  * with the public linux-omap@vger.kernel.org mailing list and the
  15  * authors above to ensure that the autogeneration scripts are kept
  16  * up-to-date with the file contents.
  17  *
  18  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  19  *     or "OMAP4430".
  20  */
  21 
  22 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  23 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  24 
  25 /* CM1 base address */
  26 #define OMAP4430_CM1_BASE               0x4a004000
  27 
  28 #define OMAP44XX_CM1_REGADDR(inst, reg)                         \
  29         OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
  30 
  31 /* CM1 instances */
  32 #define OMAP4430_CM1_OCP_SOCKET_INST    0x0000
  33 #define OMAP4430_CM1_CKGEN_INST         0x0100
  34 #define OMAP4430_CM1_MPU_INST           0x0300
  35 #define OMAP4430_CM1_TESLA_INST         0x0400
  36 #define OMAP4430_CM1_ABE_INST           0x0500
  37 #define OMAP4430_CM1_RESTORE_INST       0x0e00
  38 #define OMAP4430_CM1_INSTR_INST         0x0f00
  39 
  40 /* CM1 clockdomain register offsets (from instance start) */
  41 #define OMAP4430_CM1_MPU_MPU_CDOFFS     0x0000
  42 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
  43 #define OMAP4430_CM1_ABE_ABE_CDOFFS     0x0000
  44 
  45 /* CM1 */
  46 
  47 /* CM1.OCP_SOCKET_CM1 register offsets */
  48 #define OMAP4_REVISION_CM1_OFFSET                       0x0000
  49 #define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
  50 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
  51 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
  52 
  53 /* CM1.CKGEN_CM1 register offsets */
  54 #define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
  55 #define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
  56 #define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
  57 #define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
  58 #define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
  59 #define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
  60 #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
  61 #define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
  62 #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
  63 #define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
  64 #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
  65 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
  66 #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
  67 #define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
  68 #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
  69 #define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
  70 #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
  71 #define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
  72 #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
  73 #define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
  74 #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
  75 #define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
  76 #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
  77 #define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
  78 #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
  79 #define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
  80 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
  81 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
  82 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
  83 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
  84 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
  85 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
  86 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
  87 #define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
  88 #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
  89 #define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
  90 #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
  91 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
  92 #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
  93 #define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
  94 #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
  95 #define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
  96 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
  97 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
  98 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
  99 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
 100 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
 101 #define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
 102 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
 103 #define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
 104 #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
 105 #define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
 106 #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
 107 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
 108 #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
 109 #define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
 110 #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
 111 #define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
 112 #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
 113 #define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
 114 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
 115 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
 116 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
 117 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
 118 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
 119 #define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
 120 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
 121 #define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
 122 #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
 123 #define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
 124 #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
 125 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
 126 #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
 127 #define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
 128 #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
 129 #define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
 130 #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
 131 #define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
 132 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
 133 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
 134 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
 135 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
 136 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
 137 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
 138 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
 139 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
 140 #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
 141 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
 142 #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
 143 #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
 144 #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
 145 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
 146 #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
 147 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
 148 #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
 149 #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
 150 #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
 151 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
 152 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
 153 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
 154 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
 155 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
 156 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
 157 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
 158 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
 159 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
 160 #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
 161 #define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
 162 #define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
 163 #define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
 164 
 165 /* CM1.MPU_CM1 register offsets */
 166 #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
 167 #define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
 168 #define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
 169 #define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
 170 #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
 171 #define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
 172 #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
 173 #define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
 174 
 175 /* CM1.TESLA_CM1 register offsets */
 176 #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
 177 #define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
 178 #define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
 179 #define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
 180 #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
 181 #define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
 182 #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
 183 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
 184 
 185 /* CM1.ABE_CM1 register offsets */
 186 #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
 187 #define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
 188 #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
 189 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
 190 #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
 191 #define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
 192 #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
 193 #define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
 194 #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
 195 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
 196 #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
 197 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
 198 #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
 199 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
 200 #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
 201 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
 202 #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
 203 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
 204 #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
 205 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
 206 #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
 207 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
 208 #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
 209 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
 210 #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
 211 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
 212 #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
 213 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
 214 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 215 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 216 
 217 #endif
/* [<][>][^][v][top][bottom][index][help] */