root/arch/arm/mach-mmp/regs-usb.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   4  */
   5 
   6 #ifndef __ASM_ARCH_REGS_USB_H
   7 #define __ASM_ARCH_REGS_USB_H
   8 
   9 #define PXA168_U2O_REGBASE      (0xd4208000)
  10 #define PXA168_U2O_PHYBASE      (0xd4207000)
  11 
  12 #define PXA168_U2H_REGBASE      (0xd4209000)
  13 #define PXA168_U2H_PHYBASE      (0xd4206000)
  14 
  15 #define MMP3_HSIC1_REGBASE      (0xf0001000)
  16 #define MMP3_HSIC1_PHYBASE      (0xf0001800)
  17 
  18 #define MMP3_HSIC2_REGBASE      (0xf0002000)
  19 #define MMP3_HSIC2_PHYBASE      (0xf0002800)
  20 
  21 #define MMP3_FSIC_REGBASE       (0xf0003000)
  22 #define MMP3_FSIC_PHYBASE       (0xf0003800)
  23 
  24 
  25 #define USB_REG_RANGE           (0x1ff)
  26 #define USB_PHY_RANGE           (0xff)
  27 
  28 /* registers */
  29 #define U2x_CAPREGS_OFFSET       0x100
  30 
  31 /* phy regs */
  32 #define UTMI_REVISION           0x0
  33 #define UTMI_CTRL               0x4
  34 #define UTMI_PLL                0x8
  35 #define UTMI_TX                 0xc
  36 #define UTMI_RX                 0x10
  37 #define UTMI_IVREF              0x14
  38 #define UTMI_T0                 0x18
  39 #define UTMI_T1                 0x1c
  40 #define UTMI_T2                 0x20
  41 #define UTMI_T3                 0x24
  42 #define UTMI_T4                 0x28
  43 #define UTMI_T5                 0x2c
  44 #define UTMI_RESERVE            0x30
  45 #define UTMI_USB_INT            0x34
  46 #define UTMI_DBG_CTL            0x38
  47 #define UTMI_OTG_ADDON          0x3c
  48 
  49 /* For UTMICTRL Register */
  50 #define UTMI_CTRL_USB_CLK_EN                    (1 << 31)
  51 /* pxa168 */
  52 #define UTMI_CTRL_SUSPEND_SET1                  (1 << 30)
  53 #define UTMI_CTRL_SUSPEND_SET2                  (1 << 29)
  54 #define UTMI_CTRL_RXBUF_PDWN                    (1 << 24)
  55 #define UTMI_CTRL_TXBUF_PDWN                    (1 << 11)
  56 
  57 #define UTMI_CTRL_INPKT_DELAY_SHIFT             30
  58 #define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT         28
  59 #define UTMI_CTRL_PU_REF_SHIFT                  20
  60 #define UTMI_CTRL_ARC_PULLDN_SHIFT              12
  61 #define UTMI_CTRL_PLL_PWR_UP_SHIFT              1
  62 #define UTMI_CTRL_PWR_UP_SHIFT                  0
  63 
  64 /* For UTMI_PLL Register */
  65 #define UTMI_PLL_PLLCALI12_SHIFT                29
  66 #define UTMI_PLL_PLLCALI12_MASK                 (0x3 << 29)
  67 
  68 #define UTMI_PLL_PLLVDD18_SHIFT                 27
  69 #define UTMI_PLL_PLLVDD18_MASK                  (0x3 << 27)
  70 
  71 #define UTMI_PLL_PLLVDD12_SHIFT                 25
  72 #define UTMI_PLL_PLLVDD12_MASK                  (0x3 << 25)
  73 
  74 #define UTMI_PLL_CLK_BLK_EN_SHIFT               24
  75 #define CLK_BLK_EN                              (0x1 << 24)
  76 #define PLL_READY                               (0x1 << 23)
  77 #define KVCO_EXT                                (0x1 << 22)
  78 #define VCOCAL_START                            (0x1 << 21)
  79 
  80 #define UTMI_PLL_KVCO_SHIFT                     15
  81 #define UTMI_PLL_KVCO_MASK                      (0x7 << 15)
  82 
  83 #define UTMI_PLL_ICP_SHIFT                      12
  84 #define UTMI_PLL_ICP_MASK                       (0x7 << 12)
  85 
  86 #define UTMI_PLL_FBDIV_SHIFT                    4
  87 #define UTMI_PLL_FBDIV_MASK                     (0xFF << 4)
  88 
  89 #define UTMI_PLL_REFDIV_SHIFT                   0
  90 #define UTMI_PLL_REFDIV_MASK                    (0xF << 0)
  91 
  92 /* For UTMI_TX Register */
  93 #define UTMI_TX_REG_EXT_FS_RCAL_SHIFT           27
  94 #define UTMI_TX_REG_EXT_FS_RCAL_MASK            (0xf << 27)
  95 
  96 #define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT        26
  97 #define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK         (0x1 << 26)
  98 
  99 #define UTMI_TX_TXVDD12_SHIFT                   22
 100 #define UTMI_TX_TXVDD12_MASK                    (0x3 << 22)
 101 
 102 #define UTMI_TX_CK60_PHSEL_SHIFT                17
 103 #define UTMI_TX_CK60_PHSEL_MASK                 (0xf << 17)
 104 
 105 #define UTMI_TX_IMPCAL_VTH_SHIFT                14
 106 #define UTMI_TX_IMPCAL_VTH_MASK                 (0x7 << 14)
 107 
 108 #define REG_RCAL_START                          (0x1 << 12)
 109 
 110 #define UTMI_TX_LOW_VDD_EN_SHIFT                11
 111 
 112 #define UTMI_TX_AMP_SHIFT                       0
 113 #define UTMI_TX_AMP_MASK                        (0x7 << 0)
 114 
 115 /* For UTMI_RX Register */
 116 #define UTMI_REG_SQ_LENGTH_SHIFT                15
 117 #define UTMI_REG_SQ_LENGTH_MASK                 (0x3 << 15)
 118 
 119 #define UTMI_RX_SQ_THRESH_SHIFT                 4
 120 #define UTMI_RX_SQ_THRESH_MASK                  (0xf << 4)
 121 
 122 #define UTMI_OTG_ADDON_OTG_ON                   (1 << 0)
 123 
 124 /* For MMP3 USB Phy */
 125 #define USB2_PLL_REG0           0x4
 126 #define USB2_PLL_REG1           0x8
 127 #define USB2_TX_REG0            0x10
 128 #define USB2_TX_REG1            0x14
 129 #define USB2_TX_REG2            0x18
 130 #define USB2_RX_REG0            0x20
 131 #define USB2_RX_REG1            0x24
 132 #define USB2_RX_REG2            0x28
 133 #define USB2_ANA_REG0           0x30
 134 #define USB2_ANA_REG1           0x34
 135 #define USB2_ANA_REG2           0x38
 136 #define USB2_DIG_REG0           0x3C
 137 #define USB2_DIG_REG1           0x40
 138 #define USB2_DIG_REG2           0x44
 139 #define USB2_DIG_REG3           0x48
 140 #define USB2_TEST_REG0          0x4C
 141 #define USB2_TEST_REG1          0x50
 142 #define USB2_TEST_REG2          0x54
 143 #define USB2_CHARGER_REG0       0x58
 144 #define USB2_OTG_REG0           0x5C
 145 #define USB2_PHY_MON0           0x60
 146 #define USB2_RESETVE_REG0       0x64
 147 #define USB2_ICID_REG0          0x78
 148 #define USB2_ICID_REG1          0x7C
 149 
 150 /* USB2_PLL_REG0 */
 151 /* This is for Ax stepping */
 152 #define USB2_PLL_FBDIV_SHIFT_MMP3               0
 153 #define USB2_PLL_FBDIV_MASK_MMP3                (0xFF << 0)
 154 
 155 #define USB2_PLL_REFDIV_SHIFT_MMP3              8
 156 #define USB2_PLL_REFDIV_MASK_MMP3               (0xF << 8)
 157 
 158 #define USB2_PLL_VDD12_SHIFT_MMP3               12
 159 #define USB2_PLL_VDD18_SHIFT_MMP3               14
 160 
 161 /* This is for B0 stepping */
 162 #define USB2_PLL_FBDIV_SHIFT_MMP3_B0            0
 163 #define USB2_PLL_REFDIV_SHIFT_MMP3_B0           9
 164 #define USB2_PLL_VDD18_SHIFT_MMP3_B0            14
 165 #define USB2_PLL_FBDIV_MASK_MMP3_B0             0x01FF
 166 #define USB2_PLL_REFDIV_MASK_MMP3_B0            0x3E00
 167 
 168 #define USB2_PLL_CAL12_SHIFT_MMP3               0
 169 #define USB2_PLL_CALI12_MASK_MMP3               (0x3 << 0)
 170 
 171 #define USB2_PLL_VCOCAL_START_SHIFT_MMP3        2
 172 
 173 #define USB2_PLL_KVCO_SHIFT_MMP3                4
 174 #define USB2_PLL_KVCO_MASK_MMP3                 (0x7<<4)
 175 
 176 #define USB2_PLL_ICP_SHIFT_MMP3                 8
 177 #define USB2_PLL_ICP_MASK_MMP3                  (0x7<<8)
 178 
 179 #define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3         12
 180 
 181 #define USB2_PLL_PU_PLL_SHIFT_MMP3              13
 182 #define USB2_PLL_PU_PLL_MASK                    (0x1 << 13)
 183 
 184 #define USB2_PLL_READY_MASK_MMP3                (0x1 << 15)
 185 
 186 /* USB2_TX_REG0 */
 187 #define USB2_TX_IMPCAL_VTH_SHIFT_MMP3           8
 188 #define USB2_TX_IMPCAL_VTH_MASK_MMP3            (0x7 << 8)
 189 
 190 #define USB2_TX_RCAL_START_SHIFT_MMP3           13
 191 
 192 /* USB2_TX_REG1 */
 193 #define USB2_TX_CK60_PHSEL_SHIFT_MMP3           0
 194 #define USB2_TX_CK60_PHSEL_MASK_MMP3            (0xf << 0)
 195 
 196 #define USB2_TX_AMP_SHIFT_MMP3                  4
 197 #define USB2_TX_AMP_MASK_MMP3                   (0x7 << 4)
 198 
 199 #define USB2_TX_VDD12_SHIFT_MMP3                8
 200 #define USB2_TX_VDD12_MASK_MMP3                 (0x3 << 8)
 201 
 202 /* USB2_TX_REG2 */
 203 #define USB2_TX_DRV_SLEWRATE_SHIFT              10
 204 
 205 /* USB2_RX_REG0 */
 206 #define USB2_RX_SQ_THRESH_SHIFT_MMP3            4
 207 #define USB2_RX_SQ_THRESH_MASK_MMP3             (0xf << 4)
 208 
 209 #define USB2_RX_SQ_LENGTH_SHIFT_MMP3            10
 210 #define USB2_RX_SQ_LENGTH_MASK_MMP3             (0x3 << 10)
 211 
 212 /* USB2_ANA_REG1*/
 213 #define USB2_ANA_PU_ANA_SHIFT_MMP3              14
 214 
 215 /* USB2_OTG_REG0 */
 216 #define USB2_OTG_PU_OTG_SHIFT_MMP3              3
 217 
 218 /* fsic registers */
 219 #define FSIC_MISC                       0x4
 220 #define FSIC_INT                        0x28
 221 #define FSIC_CTRL                       0x30
 222 
 223 /* HSIC registers */
 224 #define HSIC_PAD_CTRL                   0x4
 225 
 226 #define HSIC_CTRL                       0x8
 227 #define HSIC_CTRL_HSIC_ENABLE           (1<<7)
 228 #define HSIC_CTRL_PLL_BYPASS            (1<<4)
 229 
 230 #define TEST_GRP_0                      0xc
 231 #define TEST_GRP_1                      0x10
 232 
 233 #define HSIC_INT                        0x14
 234 #define HSIC_INT_READY_INT_EN           (1<<10)
 235 #define HSIC_INT_CONNECT_INT_EN         (1<<9)
 236 #define HSIC_INT_CORE_INT_EN            (1<<8)
 237 #define HSIC_INT_HS_READY               (1<<2)
 238 #define HSIC_INT_CONNECT                (1<<1)
 239 #define HSIC_INT_CORE                   (1<<0)
 240 
 241 #define HSIC_CONFIG                     0x18
 242 #define USBHSIC_CTRL                    0x20
 243 
 244 #define HSIC_USB_CTRL                   0x28
 245 #define HSIC_USB_CTRL_CLKEN             1
 246 #define HSIC_USB_CLK_PHY                0x0
 247 #define HSIC_USB_CLK_PMU                0x1
 248 
 249 #endif /* __ASM_ARCH_PXA_U2O_H */