1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <linux/clkdev.h>
4
5 struct clkops {
6 void (*enable)(struct clk *);
7 void (*disable)(struct clk *);
8 unsigned long (*getrate)(struct clk *);
9 int (*setrate)(struct clk *, unsigned long);
10 };
11
12 struct clk {
13 const struct clkops *ops;
14
15 void __iomem *clk_rst; /* clock reset control register */
16 int fnclksel; /* functional clock select (APBC) */
17 uint32_t enable_val; /* value for clock enable (APMU) */
18 unsigned long rate;
19 int enabled;
20 };
21
22 extern struct clkops apbc_clk_ops;
23 extern struct clkops apmu_clk_ops;
24
25 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \
26 struct clk clk_##_name = { \
27 .clk_rst = APBC_##_reg, \
28 .fnclksel = _fnclksel, \
29 .rate = _rate, \
30 .ops = &apbc_clk_ops, \
31 }
32
33 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \
34 struct clk clk_##_name = { \
35 .clk_rst = APBC_##_reg, \
36 .fnclksel = _fnclksel, \
37 .rate = _rate, \
38 .ops = _ops, \
39 }
40
41 #define APMU_CLK(_name, _reg, _eval, _rate) \
42 struct clk clk_##_name = { \
43 .clk_rst = APMU_##_reg, \
44 .enable_val = _eval, \
45 .rate = _rate, \
46 .ops = &apmu_clk_ops, \
47 }
48
49 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \
50 struct clk clk_##_name = { \
51 .clk_rst = APMU_##_reg, \
52 .enable_val = _eval, \
53 .rate = _rate, \
54 .ops = _ops, \
55 }
56
57 #define INIT_CLKREG(_clk, _devname, _conname) \
58 { \
59 .clk = _clk, \
60 .dev_id = _devname, \
61 .con_id = _conname, \
62 }
63
64 extern struct clk clk_pxa168_gpio;
65 extern struct clk clk_pxa168_timers;