root/arch/arm/mach-imx/mx3x.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5 
   6 
   7 #ifndef __MACH_MX3x_H__
   8 #define __MACH_MX3x_H__
   9 
  10 /*
  11  * MX31 memory map:
  12  *
  13  * Virt         Phys            Size    What
  14  * ---------------------------------------------------------------------------
  15  * FC000000     43F00000        1M      AIPS 1
  16  * FC100000     50000000        1M      SPBA
  17  * FC200000     53F00000        1M      AIPS 2
  18  * FC500000     60000000        128M    ROMPATCH
  19  * FC400000     68000000        128M    AVIC
  20  *              70000000        256M    IPU (MAX M2)
  21  *              80000000        256M    CSD0 SDRAM/DDR
  22  *              90000000        256M    CSD1 SDRAM/DDR
  23  *              A0000000        128M    CS0 Flash
  24  *              A8000000        128M    CS1 Flash
  25  *              B0000000        32M     CS2
  26  *              B2000000        32M     CS3
  27  * F4000000     B4000000        32M     CS4
  28  *              B6000000        32M     CS5
  29  * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
  30  *              C0000000        64M     PCMCIA/CF
  31  */
  32 
  33 /*
  34  * L2CC
  35  */
  36 #define MX3x_L2CC_BASE_ADDR             0x30000000
  37 #define MX3x_L2CC_SIZE                  SZ_1M
  38 
  39 /*
  40  * AIPS 1
  41  */
  42 #define MX3x_AIPS1_BASE_ADDR            0x43f00000
  43 #define MX3x_AIPS1_SIZE                 SZ_1M
  44 #define MX3x_MAX_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x04000)
  45 #define MX3x_EVTMON_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x08000)
  46 #define MX3x_CLKCTL_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x0c000)
  47 #define MX3x_ETB_SLOT4_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x10000)
  48 #define MX3x_ETB_SLOT5_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x14000)
  49 #define MX3x_ECT_CTIO_BASE_ADDR                 (MX3x_AIPS1_BASE_ADDR + 0x18000)
  50 #define MX3x_I2C_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x80000)
  51 #define MX3x_I2C3_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x84000)
  52 #define MX3x_UART1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x90000)
  53 #define MX3x_UART2_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x94000)
  54 #define MX3x_I2C2_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x98000)
  55 #define MX3x_OWIRE_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x9c000)
  56 #define MX3x_SSI1_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0xa0000)
  57 #define MX3x_CSPI1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0xa4000)
  58 #define MX3x_KPP_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0xa8000)
  59 #define MX3x_IOMUXC_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0xac000)
  60 #define MX3x_ECT_IP1_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xb8000)
  61 #define MX3x_ECT_IP2_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xbc000)
  62 
  63 /*
  64  * SPBA global module enabled #0
  65  */
  66 #define MX3x_SPBA0_BASE_ADDR            0x50000000
  67 #define MX3x_SPBA0_SIZE                 SZ_1M
  68 #define MX3x_UART3_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x0c000)
  69 #define MX3x_CSPI2_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x10000)
  70 #define MX3x_SSI2_BASE_ADDR                     (MX3x_SPBA0_BASE_ADDR + 0x14000)
  71 #define MX3x_ATA_DMA_BASE_ADDR                  (MX3x_SPBA0_BASE_ADDR + 0x20000)
  72 #define MX3x_MSHC1_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x24000)
  73 #define MX3x_SPBA_CTRL_BASE_ADDR                (MX3x_SPBA0_BASE_ADDR + 0x3c000)
  74 
  75 /*
  76  * AIPS 2
  77  */
  78 #define MX3x_AIPS2_BASE_ADDR            0x53f00000
  79 #define MX3x_AIPS2_SIZE                 SZ_1M
  80 #define MX3x_CCM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0x80000)
  81 #define MX3x_GPT1_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0x90000)
  82 #define MX3x_EPIT1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x94000)
  83 #define MX3x_EPIT2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x98000)
  84 #define MX3x_GPIO3_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xa4000)
  85 #define MX3x_SCC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xac000)
  86 #define MX3x_RNGA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xb0000)
  87 #define MX3x_IPU_CTRL_BASE_ADDR                 (MX3x_AIPS2_BASE_ADDR + 0xc0000)
  88 #define MX3x_AUDMUX_BASE_ADDR                   (MX3x_AIPS2_BASE_ADDR + 0xc4000)
  89 #define MX3x_GPIO1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xcc000)
  90 #define MX3x_GPIO2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xd0000)
  91 #define MX3x_SDMA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xd4000)
  92 #define MX3x_RTC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xd8000)
  93 #define MX3x_WDOG_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xdc000)
  94 #define MX3x_PWM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xe0000)
  95 #define MX3x_RTIC_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xec000)
  96 
  97 /*
  98  * ROMP and AVIC
  99  */
 100 #define MX3x_ROMP_BASE_ADDR             0x60000000
 101 #define MX3x_ROMP_SIZE                  SZ_1M
 102 
 103 #define MX3x_AVIC_BASE_ADDR             0x68000000
 104 #define MX3x_AVIC_SIZE                  SZ_1M
 105 
 106 /*
 107  * Memory regions and CS
 108  */
 109 #define MX3x_IPU_MEM_BASE_ADDR          0x70000000
 110 #define MX3x_CSD0_BASE_ADDR             0x80000000
 111 #define MX3x_CSD1_BASE_ADDR             0x90000000
 112 
 113 #define MX3x_CS0_BASE_ADDR              0xa0000000
 114 #define MX3x_CS1_BASE_ADDR              0xa8000000
 115 #define MX3x_CS2_BASE_ADDR              0xb0000000
 116 #define MX3x_CS3_BASE_ADDR              0xb2000000
 117 
 118 #define MX3x_CS4_BASE_ADDR              0xb4000000
 119 #define MX3x_CS4_BASE_ADDR_VIRT         0xf6000000
 120 #define MX3x_CS4_SIZE                   SZ_32M
 121 
 122 #define MX3x_CS5_BASE_ADDR              0xb6000000
 123 #define MX3x_CS5_BASE_ADDR_VIRT         0xf8000000
 124 #define MX3x_CS5_SIZE                   SZ_32M
 125 
 126 /*
 127  * NAND, SDRAM, WEIM, M3IF, EMI controllers
 128  */
 129 #define MX3x_X_MEMC_BASE_ADDR           0xb8000000
 130 #define MX3x_X_MEMC_SIZE                SZ_64K
 131 #define MX3x_ESDCTL_BASE_ADDR                   (MX3x_X_MEMC_BASE_ADDR + 0x1000)
 132 #define MX3x_WEIM_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x2000)
 133 #define MX3x_M3IF_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x3000)
 134 #define MX3x_EMI_CTL_BASE_ADDR                  (MX3x_X_MEMC_BASE_ADDR + 0x4000)
 135 #define MX3x_PCMCIA_CTL_BASE_ADDR               MX3x_EMI_CTL_BASE_ADDR
 136 
 137 #define MX3x_PCMCIA_MEM_BASE_ADDR       0xbc000000
 138 
 139 /*
 140  * Interrupt numbers
 141  */
 142 #include <asm/irq.h>
 143 #define MX3x_INT_I2C3           (NR_IRQS_LEGACY + 3)
 144 #define MX3x_INT_I2C2           (NR_IRQS_LEGACY + 4)
 145 #define MX3x_INT_RTIC           (NR_IRQS_LEGACY + 6)
 146 #define MX3x_INT_I2C            (NR_IRQS_LEGACY + 10)
 147 #define MX3x_INT_CSPI2          (NR_IRQS_LEGACY + 13)
 148 #define MX3x_INT_CSPI1          (NR_IRQS_LEGACY + 14)
 149 #define MX3x_INT_ATA            (NR_IRQS_LEGACY + 15)
 150 #define MX3x_INT_UART3          (NR_IRQS_LEGACY + 18)
 151 #define MX3x_INT_IIM            (NR_IRQS_LEGACY + 19)
 152 #define MX3x_INT_RNGA           (NR_IRQS_LEGACY + 22)
 153 #define MX3x_INT_EVTMON         (NR_IRQS_LEGACY + 23)
 154 #define MX3x_INT_KPP            (NR_IRQS_LEGACY + 24)
 155 #define MX3x_INT_RTC            (NR_IRQS_LEGACY + 25)
 156 #define MX3x_INT_PWM            (NR_IRQS_LEGACY + 26)
 157 #define MX3x_INT_EPIT2          (NR_IRQS_LEGACY + 27)
 158 #define MX3x_INT_EPIT1          (NR_IRQS_LEGACY + 28)
 159 #define MX3x_INT_GPT            (NR_IRQS_LEGACY + 29)
 160 #define MX3x_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
 161 #define MX3x_INT_UART2          (NR_IRQS_LEGACY + 32)
 162 #define MX3x_INT_NANDFC         (NR_IRQS_LEGACY + 33)
 163 #define MX3x_INT_SDMA           (NR_IRQS_LEGACY + 34)
 164 #define MX3x_INT_MSHC1          (NR_IRQS_LEGACY + 39)
 165 #define MX3x_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
 166 #define MX3x_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
 167 #define MX3x_INT_UART1          (NR_IRQS_LEGACY + 45)
 168 #define MX3x_INT_ECT            (NR_IRQS_LEGACY + 48)
 169 #define MX3x_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
 170 #define MX3x_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
 171 #define MX3x_INT_GPIO2          (NR_IRQS_LEGACY + 51)
 172 #define MX3x_INT_GPIO1          (NR_IRQS_LEGACY + 52)
 173 #define MX3x_INT_WDOG           (NR_IRQS_LEGACY + 55)
 174 #define MX3x_INT_GPIO3          (NR_IRQS_LEGACY + 56)
 175 #define MX3x_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
 176 #define MX3x_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
 177 #define MX3x_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
 178 #define MX3x_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
 179 #define MX3x_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
 180 #define MX3x_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
 181 
 182 #define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 183 
 184 #endif /* ifndef __MACH_MX3x_H__ */
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