root/arch/arm/mach-imx/ehci-imx35.c

DEFINITIONS

1. mx35_initialize_usb_hw

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   4  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   5  */
   6 
   7 #include <linux/platform_device.h>
   8 #include <linux/io.h>
   9 #include <linux/platform_data/usb-ehci-mxc.h>
  10 
  11 #include "ehci.h"
  12 #include "hardware.h"
  13 
  14 #define USBCTRL_OTGBASE_OFFSET  0x600
  15 
  16 #define MX35_OTG_SIC_SHIFT      29
  17 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
  18 #define MX35_OTG_PM_BIT         (1 << 24)
  19 #define MX35_OTG_PP_BIT         (1 << 11)
  20 #define MX35_OTG_OCPOL_BIT      (1 << 3)
  21 
  22 #define MX35_H1_SIC_SHIFT       21
  23 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
  24 #define MX35_H1_PP_BIT          (1 << 18)
  25 #define MX35_H1_PM_BIT          (1 << 16)
  26 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
  27 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
  28 #define MX35_H1_TLL_BIT         (1 << 5)
  29 #define MX35_H1_USBTE_BIT       (1 << 4)
  30 #define MX35_H1_OCPOL_BIT       (1 << 2)
  31 
  32 int mx35_initialize_usb_hw(int port, unsigned int flags)
  33 {
  34         unsigned int v;
  35 
  36         v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  37 
  38         switch (port) {
  39         case 0: /* OTG port */
  40                 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
  41                         MX35_OTG_OCPOL_BIT);
  42                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
  43 
  44                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  45                         v |= MX35_OTG_PM_BIT;
  46 
  47                 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  48                         v |= MX35_OTG_PP_BIT;
  49 
  50                 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  51                         v |= MX35_OTG_OCPOL_BIT;
  52 
  53                 break;
  54         case 1: /* H1 port */
  55                 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
  56                         MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
  57                         MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
  58                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
  59 
  60                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  61                         v |= MX35_H1_PM_BIT;
  62 
  63                 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  64                         v |= MX35_H1_PP_BIT;
  65 
  66                 if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  67                         v |= MX35_H1_OCPOL_BIT;
  68 
  69                 if (!(flags & MXC_EHCI_TTL_ENABLED))
  70                         v |= MX35_H1_TLL_BIT;
  71 
  72                 if (flags & MXC_EHCI_INTERNAL_PHY)
  73                         v |= MX35_H1_USBTE_BIT;
  74 
  75                 if (flags & MXC_EHCI_IPPUE_DOWN)
  76                         v |= MX35_H1_IPPUE_DOWN_BIT;
  77 
  78                 if (flags & MXC_EHCI_IPPUE_UP)
  79                         v |= MX35_H1_IPPUE_UP_BIT;
  80 
  81                 break;
  82         default:
  83                 return -EINVAL;
  84         }
  85 
  86         writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
  87 
  88         return 0;
  89 }