root/arch/arm/mach-imx/avic.c

DEFINITIONS

1. avic_set_irq_fiq
2. avic_irq_suspend
3. avic_irq_resume
4. avic_init_gc
5. avic_handle_irq
6. mxc_init_irq

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   4  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   5  */
   6 
   7 #include <linux/module.h>
   8 #include <linux/irq.h>
   9 #include <linux/irqdomain.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <asm/mach/irq.h>
  14 #include <asm/exception.h>
  15 
  16 #include "common.h"
  17 #include "hardware.h"
  18 #include "irq-common.h"
  19 
  20 #define AVIC_INTCNTL            0x00    /* int control reg */
  21 #define AVIC_NIMASK             0x04    /* int mask reg */
  22 #define AVIC_INTENNUM           0x08    /* int enable number reg */
  23 #define AVIC_INTDISNUM          0x0C    /* int disable number reg */
  24 #define AVIC_INTENABLEH         0x10    /* int enable reg high */
  25 #define AVIC_INTENABLEL         0x14    /* int enable reg low */
  26 #define AVIC_INTTYPEH           0x18    /* int type reg high */
  27 #define AVIC_INTTYPEL           0x1C    /* int type reg low */
  28 #define AVIC_NIPRIORITY(x)      (0x20 + 4 * (7 - (x))) /* int priority */
  29 #define AVIC_NIVECSR            0x40    /* norm int vector/status */
  30 #define AVIC_FIVECSR            0x44    /* fast int vector/status */
  31 #define AVIC_INTSRCH            0x48    /* int source reg high */
  32 #define AVIC_INTSRCL            0x4C    /* int source reg low */
  33 #define AVIC_INTFRCH            0x50    /* int force reg high */
  34 #define AVIC_INTFRCL            0x54    /* int force reg low */
  35 #define AVIC_NIPNDH             0x58    /* norm int pending high */
  36 #define AVIC_NIPNDL             0x5C    /* norm int pending low */
  37 #define AVIC_FIPNDH             0x60    /* fast int pending high */
  38 #define AVIC_FIPNDL             0x64    /* fast int pending low */
  39 
  40 #define AVIC_NUM_IRQS 64
  41 
  42 /* low power interrupt mask registers */
  43 #define MX25_CCM_LPIMR0 0x68
  44 #define MX25_CCM_LPIMR1 0x6C
  45 
  46 static void __iomem *avic_base;
  47 static void __iomem *mx25_ccm_base;
  48 static struct irq_domain *domain;
  49 
  50 #ifdef CONFIG_FIQ
  51 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
  52 {
  53         unsigned int irqt;
  54 
  55         if (hwirq >= AVIC_NUM_IRQS)
  56                 return -EINVAL;
  57 
  58         if (hwirq < AVIC_NUM_IRQS / 2) {
  59                 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
  60                 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
  61         } else {
  62                 hwirq -= AVIC_NUM_IRQS / 2;
  63                 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
  64                 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
  65         }
  66 
  67         return 0;
  68 }
  69 #endif /* CONFIG_FIQ */
  70 
  71 
  72 static struct mxc_extra_irq avic_extra_irq = {
  73 #ifdef CONFIG_FIQ
  74         .set_irq_fiq = avic_set_irq_fiq,
  75 #endif
  76 };
  77 
  78 #ifdef CONFIG_PM
  79 static u32 avic_saved_mask_reg[2];
  80 
  81 static void avic_irq_suspend(struct irq_data *d)
  82 {
  83         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  84         struct irq_chip_type *ct = gc->chip_types;
  85         int idx = d->hwirq >> 5;
  86 
  87         avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
  88         imx_writel(gc->wake_active, avic_base + ct->regs.mask);
  89 
  90         if (mx25_ccm_base) {
  91                 u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
  92                         MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
  93                 /*
  94                  * The interrupts which are still enabled will be used as wakeup
  95                  * sources. Allow those interrupts in low-power mode.
  96                  * The LPIMR registers use 0 to allow an interrupt, the AVIC
  97                  * registers use 1.
  98                  */
  99                 imx_writel(~gc->wake_active, mx25_ccm_base + offs);
 100         }
 101 }
 102 
 103 static void avic_irq_resume(struct irq_data *d)
 104 {
 105         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 106         struct irq_chip_type *ct = gc->chip_types;
 107         int idx = d->hwirq >> 5;
 108 
 109         imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 110 
 111         if (mx25_ccm_base) {
 112                 u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
 113                         MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
 114 
 115                 imx_writel(0xffffffff, mx25_ccm_base + offs);
 116         }
 117 }
 118 
 119 #else
 120 #define avic_irq_suspend NULL
 121 #define avic_irq_resume NULL
 122 #endif
 123 
 124 static __init void avic_init_gc(int idx, unsigned int irq_start)
 125 {
 126         struct irq_chip_generic *gc;
 127         struct irq_chip_type *ct;
 128 
 129         gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
 130                                     handle_level_irq);
 131         gc->private = &avic_extra_irq;
 132         gc->wake_enabled = IRQ_MSK(32);
 133 
 134         ct = gc->chip_types;
 135         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 136         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 137         ct->chip.irq_ack = irq_gc_mask_clr_bit;
 138         ct->chip.irq_set_wake = irq_gc_set_wake;
 139         ct->chip.irq_suspend = avic_irq_suspend;
 140         ct->chip.irq_resume = avic_irq_resume;
 141         ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
 142         ct->regs.ack = ct->regs.mask;
 143 
 144         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 145 }
 146 
 147 static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
 148 {
 149         u32 nivector;
 150 
 151         do {
 152                 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
 153                 if (nivector == 0xffff)
 154                         break;
 155 
 156                 handle_domain_irq(domain, nivector, regs);
 157         } while (1);
 158 }
 159 
 160 /*
 161  * This function initializes the AVIC hardware and disables all the
 162  * interrupts. It registers the interrupt enable and disable functions
 163  * to the kernel for each interrupt source.
 164  */
 165 void __init mxc_init_irq(void __iomem *irqbase)
 166 {
 167         struct device_node *np;
 168         int irq_base;
 169         int i;
 170 
 171         avic_base = irqbase;
 172 
 173         np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
 174         mx25_ccm_base = of_iomap(np, 0);
 175 
 176         if (mx25_ccm_base) {
 177                 /*
 178                  * By default, we mask all interrupts. We set the actual mask
 179                  * before we go into low-power mode.
 180                  */
 181                 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
 182                 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
 183         }
 184 
 185         /* put the AVIC into the reset value with
 186          * all interrupts disabled
 187          */
 188         imx_writel(0, avic_base + AVIC_INTCNTL);
 189         imx_writel(0x1f, avic_base + AVIC_NIMASK);
 190 
 191         /* disable all interrupts */
 192         imx_writel(0, avic_base + AVIC_INTENABLEH);
 193         imx_writel(0, avic_base + AVIC_INTENABLEL);
 194 
 195         /* all IRQ no FIQ */
 196         imx_writel(0, avic_base + AVIC_INTTYPEH);
 197         imx_writel(0, avic_base + AVIC_INTTYPEL);
 198 
 199         irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
 200         WARN_ON(irq_base < 0);
 201 
 202         np = of_find_compatible_node(NULL, NULL, "fsl,avic");
 203         domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
 204                                        &irq_domain_simple_ops, NULL);
 205         WARN_ON(!domain);
 206 
 207         for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
 208                 avic_init_gc(i, irq_base);
 209 
 210         /* Set default priority value (0) for all IRQ's */
 211         for (i = 0; i < 8; i++)
 212                 imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
 213 
 214         set_handle_irq(avic_handle_irq);
 215 
 216 #ifdef CONFIG_FIQ
 217         /* Initialize FIQ */
 218         init_FIQ(FIQ_START);
 219 #endif
 220 
 221         printk(KERN_INFO "MXC IRQ initialized\n");
 222 }