1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BPF Jit compiler for s390.
4 *
5 * Minimum build requirements:
6 *
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
10 * - PACK_STACK
11 * - 64BIT
12 *
13 * Copyright IBM Corp. 2012,2015
14 *
15 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
16 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
17 */
18
19 #define KMSG_COMPONENT "bpf_jit"
20 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21
22 #include <linux/netdevice.h>
23 #include <linux/filter.h>
24 #include <linux/init.h>
25 #include <linux/bpf.h>
26 #include <linux/mm.h>
27 #include <asm/cacheflush.h>
28 #include <asm/dis.h>
29 #include <asm/facility.h>
30 #include <asm/nospec-branch.h>
31 #include <asm/set_memory.h>
32 #include "bpf_jit.h"
33
34 struct bpf_jit {
35 u32 seen; /* Flags to remember seen eBPF instructions */
36 u32 seen_reg[16]; /* Array to remember which registers are used */
37 u32 *addrs; /* Array with relative instruction addresses */
38 u8 *prg_buf; /* Start of program */
39 int size; /* Size of program and literal pool */
40 int size_prg; /* Size of program */
41 int prg; /* Current position in program */
42 int lit_start; /* Start of literal pool */
43 int lit; /* Current position in literal pool */
44 int base_ip; /* Base address for literal pool */
45 int ret0_ip; /* Address of return 0 */
46 int exit_ip; /* Address of exit */
47 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
48 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
49 int tail_call_start; /* Tail call start offset */
50 int labels[1]; /* Labels for local jumps */
51 };
52
53 #define BPF_SIZE_MAX 0xffff /* Max size for program (16 bit branches) */
54
55 #define SEEN_MEM (1 << 0) /* use mem[] for temporary storage */
56 #define SEEN_RET0 (1 << 1) /* ret0_ip points to a valid return 0 */
57 #define SEEN_LITERAL (1 << 2) /* code uses literals */
58 #define SEEN_FUNC (1 << 3) /* calls C functions */
59 #define SEEN_TAIL_CALL (1 << 4) /* code uses tail calls */
60 #define SEEN_REG_AX (1 << 5) /* code uses constant blinding */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
62
63 /*
64 * s390 registers
65 */
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
68 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
69 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
70 #define REG_0 REG_W0 /* Register 0 */
71 #define REG_1 REG_W1 /* Register 1 */
72 #define REG_2 BPF_REG_1 /* Register 2 */
73 #define REG_14 BPF_REG_0 /* Register 14 */
74
75 /*
76 * Mapping of BPF registers to s390 registers
77 */
78 static const int reg2hex[] = {
79 /* Return code */
80 [BPF_REG_0] = 14,
81 /* Function parameters */
82 [BPF_REG_1] = 2,
83 [BPF_REG_2] = 3,
84 [BPF_REG_3] = 4,
85 [BPF_REG_4] = 5,
86 [BPF_REG_5] = 6,
87 /* Call saved registers */
88 [BPF_REG_6] = 7,
89 [BPF_REG_7] = 8,
90 [BPF_REG_8] = 9,
91 [BPF_REG_9] = 10,
92 /* BPF stack pointer */
93 [BPF_REG_FP] = 13,
94 /* Register for blinding */
95 [BPF_REG_AX] = 12,
96 /* Work registers for s390x backend */
97 [REG_W0] = 0,
98 [REG_W1] = 1,
99 [REG_L] = 11,
100 [REG_15] = 15,
101 };
102
103 static inline u32 reg(u32 dst_reg, u32 src_reg)
104 {
105 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
106 }
107
108 static inline u32 reg_high(u32 reg)
109 {
110 return reg2hex[reg] << 4;
111 }
112
113 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
114 {
115 u32 r1 = reg2hex[b1];
116
117 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15)
118 jit->seen_reg[r1] = 1;
119 }
120
121 #define REG_SET_SEEN(b1) \
122 ({ \
123 reg_set_seen(jit, b1); \
124 })
125
126 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
127
128 /*
129 * EMIT macros for code generation
130 */
131
132 #define _EMIT2(op) \
133 ({ \
134 if (jit->prg_buf) \
135 *(u16 *) (jit->prg_buf + jit->prg) = op; \
136 jit->prg += 2; \
137 })
138
139 #define EMIT2(op, b1, b2) \
140 ({ \
141 _EMIT2(op | reg(b1, b2)); \
142 REG_SET_SEEN(b1); \
143 REG_SET_SEEN(b2); \
144 })
145
146 #define _EMIT4(op) \
147 ({ \
148 if (jit->prg_buf) \
149 *(u32 *) (jit->prg_buf + jit->prg) = op; \
150 jit->prg += 4; \
151 })
152
153 #define EMIT4(op, b1, b2) \
154 ({ \
155 _EMIT4(op | reg(b1, b2)); \
156 REG_SET_SEEN(b1); \
157 REG_SET_SEEN(b2); \
158 })
159
160 #define EMIT4_RRF(op, b1, b2, b3) \
161 ({ \
162 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \
163 REG_SET_SEEN(b1); \
164 REG_SET_SEEN(b2); \
165 REG_SET_SEEN(b3); \
166 })
167
168 #define _EMIT4_DISP(op, disp) \
169 ({ \
170 unsigned int __disp = (disp) & 0xfff; \
171 _EMIT4(op | __disp); \
172 })
173
174 #define EMIT4_DISP(op, b1, b2, disp) \
175 ({ \
176 _EMIT4_DISP(op | reg_high(b1) << 16 | \
177 reg_high(b2) << 8, disp); \
178 REG_SET_SEEN(b1); \
179 REG_SET_SEEN(b2); \
180 })
181
182 #define EMIT4_IMM(op, b1, imm) \
183 ({ \
184 unsigned int __imm = (imm) & 0xffff; \
185 _EMIT4(op | reg_high(b1) << 16 | __imm); \
186 REG_SET_SEEN(b1); \
187 })
188
189 #define EMIT4_PCREL(op, pcrel) \
190 ({ \
191 long __pcrel = ((pcrel) >> 1) & 0xffff; \
192 _EMIT4(op | __pcrel); \
193 })
194
195 #define _EMIT6(op1, op2) \
196 ({ \
197 if (jit->prg_buf) { \
198 *(u32 *) (jit->prg_buf + jit->prg) = op1; \
199 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
200 } \
201 jit->prg += 6; \
202 })
203
204 #define _EMIT6_DISP(op1, op2, disp) \
205 ({ \
206 unsigned int __disp = (disp) & 0xfff; \
207 _EMIT6(op1 | __disp, op2); \
208 })
209
210 #define _EMIT6_DISP_LH(op1, op2, disp) \
211 ({ \
212 u32 _disp = (u32) disp; \
213 unsigned int __disp_h = _disp & 0xff000; \
214 unsigned int __disp_l = _disp & 0x00fff; \
215 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
216 })
217
218 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
219 ({ \
220 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \
221 reg_high(b3) << 8, op2, disp); \
222 REG_SET_SEEN(b1); \
223 REG_SET_SEEN(b2); \
224 REG_SET_SEEN(b3); \
225 })
226
227 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \
228 ({ \
229 int rel = (jit->labels[label] - jit->prg) >> 1; \
230 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \
231 op2 | mask << 12); \
232 REG_SET_SEEN(b1); \
233 REG_SET_SEEN(b2); \
234 })
235
236 #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \
237 ({ \
238 int rel = (jit->labels[label] - jit->prg) >> 1; \
239 _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \
240 (rel & 0xffff), op2 | (imm & 0xff) << 8); \
241 REG_SET_SEEN(b1); \
242 BUILD_BUG_ON(((unsigned long) imm) > 0xff); \
243 })
244
245 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
246 ({ \
247 /* Branch instruction needs 6 bytes */ \
248 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\
249 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \
250 REG_SET_SEEN(b1); \
251 REG_SET_SEEN(b2); \
252 })
253
254 #define EMIT6_PCREL_RILB(op, b, target) \
255 ({ \
256 int rel = (target - jit->prg) / 2; \
257 _EMIT6(op | reg_high(b) << 16 | rel >> 16, rel & 0xffff); \
258 REG_SET_SEEN(b); \
259 })
260
261 #define EMIT6_PCREL_RIL(op, target) \
262 ({ \
263 int rel = (target - jit->prg) / 2; \
264 _EMIT6(op | rel >> 16, rel & 0xffff); \
265 })
266
267 #define _EMIT6_IMM(op, imm) \
268 ({ \
269 unsigned int __imm = (imm); \
270 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \
271 })
272
273 #define EMIT6_IMM(op, b1, imm) \
274 ({ \
275 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \
276 REG_SET_SEEN(b1); \
277 })
278
279 #define EMIT_CONST_U32(val) \
280 ({ \
281 unsigned int ret; \
282 ret = jit->lit - jit->base_ip; \
283 jit->seen |= SEEN_LITERAL; \
284 if (jit->prg_buf) \
285 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \
286 jit->lit += 4; \
287 ret; \
288 })
289
290 #define EMIT_CONST_U64(val) \
291 ({ \
292 unsigned int ret; \
293 ret = jit->lit - jit->base_ip; \
294 jit->seen |= SEEN_LITERAL; \
295 if (jit->prg_buf) \
296 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \
297 jit->lit += 8; \
298 ret; \
299 })
300
301 #define EMIT_ZERO(b1) \
302 ({ \
303 if (!fp->aux->verifier_zext) { \
304 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
305 EMIT4(0xb9160000, b1, b1); \
306 REG_SET_SEEN(b1); \
307 } \
308 })
309
310 /*
311 * Fill whole space with illegal instructions
312 */
313 static void jit_fill_hole(void *area, unsigned int size)
314 {
315 memset(area, 0, size);
316 }
317
318 /*
319 * Save registers from "rs" (register start) to "re" (register end) on stack
320 */
321 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
322 {
323 u32 off = STK_OFF_R6 + (rs - 6) * 8;
324
325 if (rs == re)
326 /* stg %rs,off(%r15) */
327 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
328 else
329 /* stmg %rs,%re,off(%r15) */
330 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
331 }
332
333 /*
334 * Restore registers from "rs" (register start) to "re" (register end) on stack
335 */
336 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
337 {
338 u32 off = STK_OFF_R6 + (rs - 6) * 8;
339
340 if (jit->seen & SEEN_STACK)
341 off += STK_OFF + stack_depth;
342
343 if (rs == re)
344 /* lg %rs,off(%r15) */
345 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
346 else
347 /* lmg %rs,%re,off(%r15) */
348 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
349 }
350
351 /*
352 * Return first seen register (from start)
353 */
354 static int get_start(struct bpf_jit *jit, int start)
355 {
356 int i;
357
358 for (i = start; i <= 15; i++) {
359 if (jit->seen_reg[i])
360 return i;
361 }
362 return 0;
363 }
364
365 /*
366 * Return last seen register (from start) (gap >= 2)
367 */
368 static int get_end(struct bpf_jit *jit, int start)
369 {
370 int i;
371
372 for (i = start; i < 15; i++) {
373 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
374 return i - 1;
375 }
376 return jit->seen_reg[15] ? 15 : 14;
377 }
378
379 #define REGS_SAVE 1
380 #define REGS_RESTORE 0
381 /*
382 * Save and restore clobbered registers (6-15) on stack.
383 * We save/restore registers in chunks with gap >= 2 registers.
384 */
385 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
386 {
387
388 int re = 6, rs;
389
390 do {
391 rs = get_start(jit, re);
392 if (!rs)
393 break;
394 re = get_end(jit, rs + 1);
395 if (op == REGS_SAVE)
396 save_regs(jit, rs, re);
397 else
398 restore_regs(jit, rs, re, stack_depth);
399 re++;
400 } while (re <= 15);
401 }
402
403 /*
404 * Emit function prologue
405 *
406 * Save registers and create stack frame if necessary.
407 * See stack frame layout desription in "bpf_jit.h"!
408 */
409 static void bpf_jit_prologue(struct bpf_jit *jit, u32 stack_depth)
410 {
411 if (jit->seen & SEEN_TAIL_CALL) {
412 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
413 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
414 } else {
415 /* j tail_call_start: NOP if no tail calls are used */
416 EMIT4_PCREL(0xa7f40000, 6);
417 _EMIT2(0);
418 }
419 /* Tail calls have to skip above initialization */
420 jit->tail_call_start = jit->prg;
421 /* Save registers */
422 save_restore_regs(jit, REGS_SAVE, stack_depth);
423 /* Setup literal pool */
424 if (jit->seen & SEEN_LITERAL) {
425 /* basr %r13,0 */
426 EMIT2(0x0d00, REG_L, REG_0);
427 jit->base_ip = jit->prg;
428 }
429 /* Setup stack and backchain */
430 if (jit->seen & SEEN_STACK) {
431 if (jit->seen & SEEN_FUNC)
432 /* lgr %w1,%r15 (backchain) */
433 EMIT4(0xb9040000, REG_W1, REG_15);
434 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
435 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
436 /* aghi %r15,-STK_OFF */
437 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
438 if (jit->seen & SEEN_FUNC)
439 /* stg %w1,152(%r15) (backchain) */
440 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
441 REG_15, 152);
442 }
443 }
444
445 /*
446 * Function epilogue
447 */
448 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
449 {
450 /* Return 0 */
451 if (jit->seen & SEEN_RET0) {
452 jit->ret0_ip = jit->prg;
453 /* lghi %b0,0 */
454 EMIT4_IMM(0xa7090000, BPF_REG_0, 0);
455 }
456 jit->exit_ip = jit->prg;
457 /* Load exit code: lgr %r2,%b0 */
458 EMIT4(0xb9040000, REG_2, BPF_REG_0);
459 /* Restore registers */
460 save_restore_regs(jit, REGS_RESTORE, stack_depth);
461 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
462 jit->r14_thunk_ip = jit->prg;
463 /* Generate __s390_indirect_jump_r14 thunk */
464 if (test_facility(35)) {
465 /* exrl %r0,.+10 */
466 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
467 } else {
468 /* larl %r1,.+14 */
469 EMIT6_PCREL_RILB(0xc0000000, REG_1, jit->prg + 14);
470 /* ex 0,0(%r1) */
471 EMIT4_DISP(0x44000000, REG_0, REG_1, 0);
472 }
473 /* j . */
474 EMIT4_PCREL(0xa7f40000, 0);
475 }
476 /* br %r14 */
477 _EMIT2(0x07fe);
478
479 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable &&
480 (jit->seen & SEEN_FUNC)) {
481 jit->r1_thunk_ip = jit->prg;
482 /* Generate __s390_indirect_jump_r1 thunk */
483 if (test_facility(35)) {
484 /* exrl %r0,.+10 */
485 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
486 /* j . */
487 EMIT4_PCREL(0xa7f40000, 0);
488 /* br %r1 */
489 _EMIT2(0x07f1);
490 } else {
491 /* ex 0,S390_lowcore.br_r1_tampoline */
492 EMIT4_DISP(0x44000000, REG_0, REG_0,
493 offsetof(struct lowcore, br_r1_trampoline));
494 /* j . */
495 EMIT4_PCREL(0xa7f40000, 0);
496 }
497 }
498 }
499
500 /*
501 * Compile one eBPF instruction into s390x code
502 *
503 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
504 * stack space for the large switch statement.
505 */
506 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
507 int i, bool extra_pass)
508 {
509 struct bpf_insn *insn = &fp->insnsi[i];
510 int jmp_off, last, insn_count = 1;
511 u32 dst_reg = insn->dst_reg;
512 u32 src_reg = insn->src_reg;
513 u32 *addrs = jit->addrs;
514 s32 imm = insn->imm;
515 s16 off = insn->off;
516 unsigned int mask;
517
518 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
519 jit->seen |= SEEN_REG_AX;
520 switch (insn->code) {
521 /*
522 * BPF_MOV
523 */
524 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
525 /* llgfr %dst,%src */
526 EMIT4(0xb9160000, dst_reg, src_reg);
527 if (insn_is_zext(&insn[1]))
528 insn_count = 2;
529 break;
530 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
531 /* lgr %dst,%src */
532 EMIT4(0xb9040000, dst_reg, src_reg);
533 break;
534 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
535 /* llilf %dst,imm */
536 EMIT6_IMM(0xc00f0000, dst_reg, imm);
537 if (insn_is_zext(&insn[1]))
538 insn_count = 2;
539 break;
540 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
541 /* lgfi %dst,imm */
542 EMIT6_IMM(0xc0010000, dst_reg, imm);
543 break;
544 /*
545 * BPF_LD 64
546 */
547 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
548 {
549 /* 16 byte instruction that uses two 'struct bpf_insn' */
550 u64 imm64;
551
552 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
553 /* lg %dst,<d(imm)>(%l) */
554 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L,
555 EMIT_CONST_U64(imm64));
556 insn_count = 2;
557 break;
558 }
559 /*
560 * BPF_ADD
561 */
562 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
563 /* ar %dst,%src */
564 EMIT2(0x1a00, dst_reg, src_reg);
565 EMIT_ZERO(dst_reg);
566 break;
567 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
568 /* agr %dst,%src */
569 EMIT4(0xb9080000, dst_reg, src_reg);
570 break;
571 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
572 if (!imm)
573 break;
574 /* alfi %dst,imm */
575 EMIT6_IMM(0xc20b0000, dst_reg, imm);
576 EMIT_ZERO(dst_reg);
577 break;
578 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
579 if (!imm)
580 break;
581 /* agfi %dst,imm */
582 EMIT6_IMM(0xc2080000, dst_reg, imm);
583 break;
584 /*
585 * BPF_SUB
586 */
587 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
588 /* sr %dst,%src */
589 EMIT2(0x1b00, dst_reg, src_reg);
590 EMIT_ZERO(dst_reg);
591 break;
592 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
593 /* sgr %dst,%src */
594 EMIT4(0xb9090000, dst_reg, src_reg);
595 break;
596 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
597 if (!imm)
598 break;
599 /* alfi %dst,-imm */
600 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
601 EMIT_ZERO(dst_reg);
602 break;
603 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
604 if (!imm)
605 break;
606 /* agfi %dst,-imm */
607 EMIT6_IMM(0xc2080000, dst_reg, -imm);
608 break;
609 /*
610 * BPF_MUL
611 */
612 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
613 /* msr %dst,%src */
614 EMIT4(0xb2520000, dst_reg, src_reg);
615 EMIT_ZERO(dst_reg);
616 break;
617 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
618 /* msgr %dst,%src */
619 EMIT4(0xb90c0000, dst_reg, src_reg);
620 break;
621 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
622 if (imm == 1)
623 break;
624 /* msfi %r5,imm */
625 EMIT6_IMM(0xc2010000, dst_reg, imm);
626 EMIT_ZERO(dst_reg);
627 break;
628 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
629 if (imm == 1)
630 break;
631 /* msgfi %dst,imm */
632 EMIT6_IMM(0xc2000000, dst_reg, imm);
633 break;
634 /*
635 * BPF_DIV / BPF_MOD
636 */
637 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
638 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
639 {
640 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
641
642 /* lhi %w0,0 */
643 EMIT4_IMM(0xa7080000, REG_W0, 0);
644 /* lr %w1,%dst */
645 EMIT2(0x1800, REG_W1, dst_reg);
646 /* dlr %w0,%src */
647 EMIT4(0xb9970000, REG_W0, src_reg);
648 /* llgfr %dst,%rc */
649 EMIT4(0xb9160000, dst_reg, rc_reg);
650 if (insn_is_zext(&insn[1]))
651 insn_count = 2;
652 break;
653 }
654 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
655 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
656 {
657 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
658
659 /* lghi %w0,0 */
660 EMIT4_IMM(0xa7090000, REG_W0, 0);
661 /* lgr %w1,%dst */
662 EMIT4(0xb9040000, REG_W1, dst_reg);
663 /* dlgr %w0,%dst */
664 EMIT4(0xb9870000, REG_W0, src_reg);
665 /* lgr %dst,%rc */
666 EMIT4(0xb9040000, dst_reg, rc_reg);
667 break;
668 }
669 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
670 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
671 {
672 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
673
674 if (imm == 1) {
675 if (BPF_OP(insn->code) == BPF_MOD)
676 /* lhgi %dst,0 */
677 EMIT4_IMM(0xa7090000, dst_reg, 0);
678 break;
679 }
680 /* lhi %w0,0 */
681 EMIT4_IMM(0xa7080000, REG_W0, 0);
682 /* lr %w1,%dst */
683 EMIT2(0x1800, REG_W1, dst_reg);
684 /* dl %w0,<d(imm)>(%l) */
685 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
686 EMIT_CONST_U32(imm));
687 /* llgfr %dst,%rc */
688 EMIT4(0xb9160000, dst_reg, rc_reg);
689 if (insn_is_zext(&insn[1]))
690 insn_count = 2;
691 break;
692 }
693 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
694 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
695 {
696 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
697
698 if (imm == 1) {
699 if (BPF_OP(insn->code) == BPF_MOD)
700 /* lhgi %dst,0 */
701 EMIT4_IMM(0xa7090000, dst_reg, 0);
702 break;
703 }
704 /* lghi %w0,0 */
705 EMIT4_IMM(0xa7090000, REG_W0, 0);
706 /* lgr %w1,%dst */
707 EMIT4(0xb9040000, REG_W1, dst_reg);
708 /* dlg %w0,<d(imm)>(%l) */
709 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
710 EMIT_CONST_U64(imm));
711 /* lgr %dst,%rc */
712 EMIT4(0xb9040000, dst_reg, rc_reg);
713 break;
714 }
715 /*
716 * BPF_AND
717 */
718 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
719 /* nr %dst,%src */
720 EMIT2(0x1400, dst_reg, src_reg);
721 EMIT_ZERO(dst_reg);
722 break;
723 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
724 /* ngr %dst,%src */
725 EMIT4(0xb9800000, dst_reg, src_reg);
726 break;
727 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
728 /* nilf %dst,imm */
729 EMIT6_IMM(0xc00b0000, dst_reg, imm);
730 EMIT_ZERO(dst_reg);
731 break;
732 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
733 /* ng %dst,<d(imm)>(%l) */
734 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L,
735 EMIT_CONST_U64(imm));
736 break;
737 /*
738 * BPF_OR
739 */
740 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
741 /* or %dst,%src */
742 EMIT2(0x1600, dst_reg, src_reg);
743 EMIT_ZERO(dst_reg);
744 break;
745 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
746 /* ogr %dst,%src */
747 EMIT4(0xb9810000, dst_reg, src_reg);
748 break;
749 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
750 /* oilf %dst,imm */
751 EMIT6_IMM(0xc00d0000, dst_reg, imm);
752 EMIT_ZERO(dst_reg);
753 break;
754 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
755 /* og %dst,<d(imm)>(%l) */
756 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L,
757 EMIT_CONST_U64(imm));
758 break;
759 /*
760 * BPF_XOR
761 */
762 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
763 /* xr %dst,%src */
764 EMIT2(0x1700, dst_reg, src_reg);
765 EMIT_ZERO(dst_reg);
766 break;
767 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
768 /* xgr %dst,%src */
769 EMIT4(0xb9820000, dst_reg, src_reg);
770 break;
771 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
772 if (!imm)
773 break;
774 /* xilf %dst,imm */
775 EMIT6_IMM(0xc0070000, dst_reg, imm);
776 EMIT_ZERO(dst_reg);
777 break;
778 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
779 /* xg %dst,<d(imm)>(%l) */
780 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L,
781 EMIT_CONST_U64(imm));
782 break;
783 /*
784 * BPF_LSH
785 */
786 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
787 /* sll %dst,0(%src) */
788 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
789 EMIT_ZERO(dst_reg);
790 break;
791 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
792 /* sllg %dst,%dst,0(%src) */
793 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
794 break;
795 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
796 if (imm == 0)
797 break;
798 /* sll %dst,imm(%r0) */
799 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
800 EMIT_ZERO(dst_reg);
801 break;
802 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
803 if (imm == 0)
804 break;
805 /* sllg %dst,%dst,imm(%r0) */
806 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
807 break;
808 /*
809 * BPF_RSH
810 */
811 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
812 /* srl %dst,0(%src) */
813 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
814 EMIT_ZERO(dst_reg);
815 break;
816 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
817 /* srlg %dst,%dst,0(%src) */
818 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
819 break;
820 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
821 if (imm == 0)
822 break;
823 /* srl %dst,imm(%r0) */
824 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
825 EMIT_ZERO(dst_reg);
826 break;
827 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
828 if (imm == 0)
829 break;
830 /* srlg %dst,%dst,imm(%r0) */
831 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
832 break;
833 /*
834 * BPF_ARSH
835 */
836 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
837 /* sra %dst,%dst,0(%src) */
838 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
839 EMIT_ZERO(dst_reg);
840 break;
841 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
842 /* srag %dst,%dst,0(%src) */
843 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
844 break;
845 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
846 if (imm == 0)
847 break;
848 /* sra %dst,imm(%r0) */
849 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
850 EMIT_ZERO(dst_reg);
851 break;
852 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
853 if (imm == 0)
854 break;
855 /* srag %dst,%dst,imm(%r0) */
856 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
857 break;
858 /*
859 * BPF_NEG
860 */
861 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
862 /* lcr %dst,%dst */
863 EMIT2(0x1300, dst_reg, dst_reg);
864 EMIT_ZERO(dst_reg);
865 break;
866 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
867 /* lcgr %dst,%dst */
868 EMIT4(0xb9030000, dst_reg, dst_reg);
869 break;
870 /*
871 * BPF_FROM_BE/LE
872 */
873 case BPF_ALU | BPF_END | BPF_FROM_BE:
874 /* s390 is big endian, therefore only clear high order bytes */
875 switch (imm) {
876 case 16: /* dst = (u16) cpu_to_be16(dst) */
877 /* llghr %dst,%dst */
878 EMIT4(0xb9850000, dst_reg, dst_reg);
879 if (insn_is_zext(&insn[1]))
880 insn_count = 2;
881 break;
882 case 32: /* dst = (u32) cpu_to_be32(dst) */
883 if (!fp->aux->verifier_zext)
884 /* llgfr %dst,%dst */
885 EMIT4(0xb9160000, dst_reg, dst_reg);
886 break;
887 case 64: /* dst = (u64) cpu_to_be64(dst) */
888 break;
889 }
890 break;
891 case BPF_ALU | BPF_END | BPF_FROM_LE:
892 switch (imm) {
893 case 16: /* dst = (u16) cpu_to_le16(dst) */
894 /* lrvr %dst,%dst */
895 EMIT4(0xb91f0000, dst_reg, dst_reg);
896 /* srl %dst,16(%r0) */
897 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
898 /* llghr %dst,%dst */
899 EMIT4(0xb9850000, dst_reg, dst_reg);
900 if (insn_is_zext(&insn[1]))
901 insn_count = 2;
902 break;
903 case 32: /* dst = (u32) cpu_to_le32(dst) */
904 /* lrvr %dst,%dst */
905 EMIT4(0xb91f0000, dst_reg, dst_reg);
906 if (!fp->aux->verifier_zext)
907 /* llgfr %dst,%dst */
908 EMIT4(0xb9160000, dst_reg, dst_reg);
909 break;
910 case 64: /* dst = (u64) cpu_to_le64(dst) */
911 /* lrvgr %dst,%dst */
912 EMIT4(0xb90f0000, dst_reg, dst_reg);
913 break;
914 }
915 break;
916 /*
917 * BPF_ST(X)
918 */
919 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
920 /* stcy %src,off(%dst) */
921 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
922 jit->seen |= SEEN_MEM;
923 break;
924 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
925 /* sthy %src,off(%dst) */
926 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
927 jit->seen |= SEEN_MEM;
928 break;
929 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
930 /* sty %src,off(%dst) */
931 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
932 jit->seen |= SEEN_MEM;
933 break;
934 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
935 /* stg %src,off(%dst) */
936 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
937 jit->seen |= SEEN_MEM;
938 break;
939 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
940 /* lhi %w0,imm */
941 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
942 /* stcy %w0,off(dst) */
943 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
944 jit->seen |= SEEN_MEM;
945 break;
946 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
947 /* lhi %w0,imm */
948 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
949 /* sthy %w0,off(dst) */
950 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
951 jit->seen |= SEEN_MEM;
952 break;
953 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
954 /* llilf %w0,imm */
955 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
956 /* sty %w0,off(%dst) */
957 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
958 jit->seen |= SEEN_MEM;
959 break;
960 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
961 /* lgfi %w0,imm */
962 EMIT6_IMM(0xc0010000, REG_W0, imm);
963 /* stg %w0,off(%dst) */
964 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
965 jit->seen |= SEEN_MEM;
966 break;
967 /*
968 * BPF_STX XADD (atomic_add)
969 */
970 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */
971 /* laal %w0,%src,off(%dst) */
972 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg,
973 dst_reg, off);
974 jit->seen |= SEEN_MEM;
975 break;
976 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */
977 /* laalg %w0,%src,off(%dst) */
978 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg,
979 dst_reg, off);
980 jit->seen |= SEEN_MEM;
981 break;
982 /*
983 * BPF_LDX
984 */
985 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
986 /* llgc %dst,0(off,%src) */
987 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
988 jit->seen |= SEEN_MEM;
989 if (insn_is_zext(&insn[1]))
990 insn_count = 2;
991 break;
992 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
993 /* llgh %dst,0(off,%src) */
994 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
995 jit->seen |= SEEN_MEM;
996 if (insn_is_zext(&insn[1]))
997 insn_count = 2;
998 break;
999 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1000 /* llgf %dst,off(%src) */
1001 jit->seen |= SEEN_MEM;
1002 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1003 if (insn_is_zext(&insn[1]))
1004 insn_count = 2;
1005 break;
1006 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1007 /* lg %dst,0(off,%src) */
1008 jit->seen |= SEEN_MEM;
1009 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1010 break;
1011 /*
1012 * BPF_JMP / CALL
1013 */
1014 case BPF_JMP | BPF_CALL:
1015 {
1016 u64 func;
1017 bool func_addr_fixed;
1018 int ret;
1019
1020 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1021 &func, &func_addr_fixed);
1022 if (ret < 0)
1023 return -1;
1024
1025 REG_SET_SEEN(BPF_REG_5);
1026 jit->seen |= SEEN_FUNC;
1027 /* lg %w1,<d(imm)>(%l) */
1028 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_W1, REG_0, REG_L,
1029 EMIT_CONST_U64(func));
1030 if (__is_defined(CC_USING_EXPOLINE) && !nospec_disable) {
1031 /* brasl %r14,__s390_indirect_jump_r1 */
1032 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
1033 } else {
1034 /* basr %r14,%w1 */
1035 EMIT2(0x0d00, REG_14, REG_W1);
1036 }
1037 /* lgr %b0,%r2: load return value into %b0 */
1038 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1039 break;
1040 }
1041 case BPF_JMP | BPF_TAIL_CALL:
1042 /*
1043 * Implicit input:
1044 * B1: pointer to ctx
1045 * B2: pointer to bpf_array
1046 * B3: index in bpf_array
1047 */
1048 jit->seen |= SEEN_TAIL_CALL;
1049
1050 /*
1051 * if (index >= array->map.max_entries)
1052 * goto out;
1053 */
1054
1055 /* llgf %w1,map.max_entries(%b2) */
1056 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1057 offsetof(struct bpf_array, map.max_entries));
1058 /* clrj %b3,%w1,0xa,label0: if (u32)%b3 >= (u32)%w1 goto out */
1059 EMIT6_PCREL_LABEL(0xec000000, 0x0077, BPF_REG_3,
1060 REG_W1, 0, 0xa);
1061
1062 /*
1063 * if (tail_call_cnt++ > MAX_TAIL_CALL_CNT)
1064 * goto out;
1065 */
1066
1067 if (jit->seen & SEEN_STACK)
1068 off = STK_OFF_TCCNT + STK_OFF + fp->aux->stack_depth;
1069 else
1070 off = STK_OFF_TCCNT;
1071 /* lhi %w0,1 */
1072 EMIT4_IMM(0xa7080000, REG_W0, 1);
1073 /* laal %w1,%w0,off(%r15) */
1074 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1075 /* clij %w1,MAX_TAIL_CALL_CNT,0x2,label0 */
1076 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007f, REG_W1,
1077 MAX_TAIL_CALL_CNT, 0, 0x2);
1078
1079 /*
1080 * prog = array->ptrs[index];
1081 * if (prog == NULL)
1082 * goto out;
1083 */
1084
1085 /* llgfr %r1,%b3: %r1 = (u32) index */
1086 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1087 /* sllg %r1,%r1,3: %r1 *= 8 */
1088 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1089 /* lg %r1,prog(%b2,%r1) */
1090 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, BPF_REG_2,
1091 REG_1, offsetof(struct bpf_array, ptrs));
1092 /* clgij %r1,0,0x8,label0 */
1093 EMIT6_PCREL_IMM_LABEL(0xec000000, 0x007d, REG_1, 0, 0, 0x8);
1094
1095 /*
1096 * Restore registers before calling function
1097 */
1098 save_restore_regs(jit, REGS_RESTORE, fp->aux->stack_depth);
1099
1100 /*
1101 * goto *(prog->bpf_func + tail_call_start);
1102 */
1103
1104 /* lg %r1,bpf_func(%r1) */
1105 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1106 offsetof(struct bpf_prog, bpf_func));
1107 /* bc 0xf,tail_call_start(%r1) */
1108 _EMIT4(0x47f01000 + jit->tail_call_start);
1109 /* out: */
1110 jit->labels[0] = jit->prg;
1111 break;
1112 case BPF_JMP | BPF_EXIT: /* return b0 */
1113 last = (i == fp->len - 1) ? 1 : 0;
1114 if (last && !(jit->seen & SEEN_RET0))
1115 break;
1116 /* j <exit> */
1117 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg);
1118 break;
1119 /*
1120 * Branch relative (number of skipped instructions) to offset on
1121 * condition.
1122 *
1123 * Condition code to mask mapping:
1124 *
1125 * CC | Description | Mask
1126 * ------------------------------
1127 * 0 | Operands equal | 8
1128 * 1 | First operand low | 4
1129 * 2 | First operand high | 2
1130 * 3 | Unused | 1
1131 *
1132 * For s390x relative branches: ip = ip + off_bytes
1133 * For BPF relative branches: insn = insn + off_insns + 1
1134 *
1135 * For example for s390x with offset 0 we jump to the branch
1136 * instruction itself (loop) and for BPF with offset 0 we
1137 * branch to the instruction behind the branch.
1138 */
1139 case BPF_JMP | BPF_JA: /* if (true) */
1140 mask = 0xf000; /* j */
1141 goto branch_oc;
1142 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1143 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1144 mask = 0x2000; /* jh */
1145 goto branch_ks;
1146 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1147 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1148 mask = 0x4000; /* jl */
1149 goto branch_ks;
1150 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1151 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1152 mask = 0xa000; /* jhe */
1153 goto branch_ks;
1154 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1155 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1156 mask = 0xc000; /* jle */
1157 goto branch_ks;
1158 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1159 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1160 mask = 0x2000; /* jh */
1161 goto branch_ku;
1162 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1163 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1164 mask = 0x4000; /* jl */
1165 goto branch_ku;
1166 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1167 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1168 mask = 0xa000; /* jhe */
1169 goto branch_ku;
1170 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1171 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1172 mask = 0xc000; /* jle */
1173 goto branch_ku;
1174 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1175 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1176 mask = 0x7000; /* jne */
1177 goto branch_ku;
1178 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1179 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1180 mask = 0x8000; /* je */
1181 goto branch_ku;
1182 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1183 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1184 mask = 0x7000; /* jnz */
1185 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1186 /* llilf %w1,imm (load zero extend imm) */
1187 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1188 /* nr %w1,%dst */
1189 EMIT2(0x1400, REG_W1, dst_reg);
1190 } else {
1191 /* lgfi %w1,imm (load sign extend imm) */
1192 EMIT6_IMM(0xc0010000, REG_W1, imm);
1193 /* ngr %w1,%dst */
1194 EMIT4(0xb9800000, REG_W1, dst_reg);
1195 }
1196 goto branch_oc;
1197
1198 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1199 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1200 mask = 0x2000; /* jh */
1201 goto branch_xs;
1202 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1203 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1204 mask = 0x4000; /* jl */
1205 goto branch_xs;
1206 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1207 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1208 mask = 0xa000; /* jhe */
1209 goto branch_xs;
1210 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1211 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1212 mask = 0xc000; /* jle */
1213 goto branch_xs;
1214 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1215 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1216 mask = 0x2000; /* jh */
1217 goto branch_xu;
1218 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1219 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1220 mask = 0x4000; /* jl */
1221 goto branch_xu;
1222 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1223 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1224 mask = 0xa000; /* jhe */
1225 goto branch_xu;
1226 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1227 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1228 mask = 0xc000; /* jle */
1229 goto branch_xu;
1230 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1231 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1232 mask = 0x7000; /* jne */
1233 goto branch_xu;
1234 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1235 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1236 mask = 0x8000; /* je */
1237 goto branch_xu;
1238 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1239 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1240 {
1241 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1242
1243 mask = 0x7000; /* jnz */
1244 /* nrk or ngrk %w1,%dst,%src */
1245 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1246 REG_W1, dst_reg, src_reg);
1247 goto branch_oc;
1248 branch_ks:
1249 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1250 /* lgfi %w1,imm (load sign extend imm) */
1251 EMIT6_IMM(0xc0010000, REG_W1, imm);
1252 /* crj or cgrj %dst,%w1,mask,off */
1253 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1254 dst_reg, REG_W1, i, off, mask);
1255 break;
1256 branch_ku:
1257 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1258 /* lgfi %w1,imm (load sign extend imm) */
1259 EMIT6_IMM(0xc0010000, REG_W1, imm);
1260 /* clrj or clgrj %dst,%w1,mask,off */
1261 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1262 dst_reg, REG_W1, i, off, mask);
1263 break;
1264 branch_xs:
1265 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1266 /* crj or cgrj %dst,%src,mask,off */
1267 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1268 dst_reg, src_reg, i, off, mask);
1269 break;
1270 branch_xu:
1271 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1272 /* clrj or clgrj %dst,%src,mask,off */
1273 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1274 dst_reg, src_reg, i, off, mask);
1275 break;
1276 branch_oc:
1277 /* brc mask,jmp_off (branch instruction needs 4 bytes) */
1278 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4);
1279 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off);
1280 break;
1281 }
1282 default: /* too complex, give up */
1283 pr_err("Unknown opcode %02x\n", insn->code);
1284 return -1;
1285 }
1286 return insn_count;
1287 }
1288
1289 /*
1290 * Compile eBPF program into s390x code
1291 */
1292 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1293 bool extra_pass)
1294 {
1295 int i, insn_count;
1296
1297 jit->lit = jit->lit_start;
1298 jit->prg = 0;
1299
1300 bpf_jit_prologue(jit, fp->aux->stack_depth);
1301 for (i = 0; i < fp->len; i += insn_count) {
1302 insn_count = bpf_jit_insn(jit, fp, i, extra_pass);
1303 if (insn_count < 0)
1304 return -1;
1305 /* Next instruction address */
1306 jit->addrs[i + insn_count] = jit->prg;
1307 }
1308 bpf_jit_epilogue(jit, fp->aux->stack_depth);
1309
1310 jit->lit_start = jit->prg;
1311 jit->size = jit->lit;
1312 jit->size_prg = jit->prg;
1313 return 0;
1314 }
1315
1316 bool bpf_jit_needs_zext(void)
1317 {
1318 return true;
1319 }
1320
1321 struct s390_jit_data {
1322 struct bpf_binary_header *header;
1323 struct bpf_jit ctx;
1324 int pass;
1325 };
1326
1327 /*
1328 * Compile eBPF program "fp"
1329 */
1330 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1331 {
1332 struct bpf_prog *tmp, *orig_fp = fp;
1333 struct bpf_binary_header *header;
1334 struct s390_jit_data *jit_data;
1335 bool tmp_blinded = false;
1336 bool extra_pass = false;
1337 struct bpf_jit jit;
1338 int pass;
1339
1340 if (!fp->jit_requested)
1341 return orig_fp;
1342
1343 tmp = bpf_jit_blind_constants(fp);
1344 /*
1345 * If blinding was requested and we failed during blinding,
1346 * we must fall back to the interpreter.
1347 */
1348 if (IS_ERR(tmp))
1349 return orig_fp;
1350 if (tmp != fp) {
1351 tmp_blinded = true;
1352 fp = tmp;
1353 }
1354
1355 jit_data = fp->aux->jit_data;
1356 if (!jit_data) {
1357 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1358 if (!jit_data) {
1359 fp = orig_fp;
1360 goto out;
1361 }
1362 fp->aux->jit_data = jit_data;
1363 }
1364 if (jit_data->ctx.addrs) {
1365 jit = jit_data->ctx;
1366 header = jit_data->header;
1367 extra_pass = true;
1368 pass = jit_data->pass + 1;
1369 goto skip_init_ctx;
1370 }
1371
1372 memset(&jit, 0, sizeof(jit));
1373 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1374 if (jit.addrs == NULL) {
1375 fp = orig_fp;
1376 goto out;
1377 }
1378 /*
1379 * Three initial passes:
1380 * - 1/2: Determine clobbered registers
1381 * - 3: Calculate program size and addrs arrray
1382 */
1383 for (pass = 1; pass <= 3; pass++) {
1384 if (bpf_jit_prog(&jit, fp, extra_pass)) {
1385 fp = orig_fp;
1386 goto free_addrs;
1387 }
1388 }
1389 /*
1390 * Final pass: Allocate and generate program
1391 */
1392 if (jit.size >= BPF_SIZE_MAX) {
1393 fp = orig_fp;
1394 goto free_addrs;
1395 }
1396
1397 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole);
1398 if (!header) {
1399 fp = orig_fp;
1400 goto free_addrs;
1401 }
1402 skip_init_ctx:
1403 if (bpf_jit_prog(&jit, fp, extra_pass)) {
1404 bpf_jit_binary_free(header);
1405 fp = orig_fp;
1406 goto free_addrs;
1407 }
1408 if (bpf_jit_enable > 1) {
1409 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1410 print_fn_code(jit.prg_buf, jit.size_prg);
1411 }
1412 if (!fp->is_func || extra_pass) {
1413 bpf_jit_binary_lock_ro(header);
1414 } else {
1415 jit_data->header = header;
1416 jit_data->ctx = jit;
1417 jit_data->pass = pass;
1418 }
1419 fp->bpf_func = (void *) jit.prg_buf;
1420 fp->jited = 1;
1421 fp->jited_len = jit.size;
1422
1423 if (!fp->is_func || extra_pass) {
1424 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1425 free_addrs:
1426 kvfree(jit.addrs);
1427 kfree(jit_data);
1428 fp->aux->jit_data = NULL;
1429 }
1430 out:
1431 if (tmp_blinded)
1432 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1433 tmp : orig_fp);
1434 return fp;
1435 }