root/arch/s390/crypto/crc32be-vx.S

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Hardware-accelerated CRC-32 variants for Linux on z Systems
   4  *
   5  * Use the z/Architecture Vector Extension Facility to accelerate the
   6  * computing of CRC-32 checksums.
   7  *
   8  * This CRC-32 implementation algorithm processes the most-significant
   9  * bit first (BE).
  10  *
  11  * Copyright IBM Corp. 2015
  12  * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
  13  */
  14 
  15 #include <linux/linkage.h>
  16 #include <asm/nospec-insn.h>
  17 #include <asm/vx-insn.h>
  18 
  19 /* Vector register range containing CRC-32 constants */
  20 #define CONST_R1R2              %v9
  21 #define CONST_R3R4              %v10
  22 #define CONST_R5                %v11
  23 #define CONST_R6                %v12
  24 #define CONST_RU_POLY           %v13
  25 #define CONST_CRC_POLY          %v14
  26 
  27 .data
  28 .align 8
  29 
  30 /*
  31  * The CRC-32 constant block contains reduction constants to fold and
  32  * process particular chunks of the input data stream in parallel.
  33  *
  34  * For the CRC-32 variants, the constants are precomputed according to
  35  * these defintions:
  36  *
  37  *      R1 = x4*128+64 mod P(x)
  38  *      R2 = x4*128    mod P(x)
  39  *      R3 = x128+64   mod P(x)
  40  *      R4 = x128      mod P(x)
  41  *      R5 = x96       mod P(x)
  42  *      R6 = x64       mod P(x)
  43  *
  44  *      Barret reduction constant, u, is defined as floor(x**64 / P(x)).
  45  *
  46  *      where P(x) is the polynomial in the normal domain and the P'(x) is the
  47  *      polynomial in the reversed (bitreflected) domain.
  48  *
  49  * Note that the constant definitions below are extended in order to compute
  50  * intermediate results with a single VECTOR GALOIS FIELD MULTIPLY instruction.
  51  * The righmost doubleword can be 0 to prevent contribution to the result or
  52  * can be multiplied by 1 to perform an XOR without the need for a separate
  53  * VECTOR EXCLUSIVE OR instruction.
  54  *
  55  * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
  56  *
  57  *      P(x)  = 0x04C11DB7
  58  *      P'(x) = 0xEDB88320
  59  */
  60 
  61 .Lconstants_CRC_32_BE:
  62         .quad           0x08833794c, 0x0e6228b11        # R1, R2
  63         .quad           0x0c5b9cd4c, 0x0e8a45605        # R3, R4
  64         .quad           0x0f200aa66, 1 << 32            # R5, x32
  65         .quad           0x0490d678d, 1                  # R6, 1
  66         .quad           0x104d101df, 0                  # u
  67         .quad           0x104C11DB7, 0                  # P(x)
  68 
  69 .previous
  70 
  71         GEN_BR_THUNK %r14
  72 
  73 .text
  74 /*
  75  * The CRC-32 function(s) use these calling conventions:
  76  *
  77  * Parameters:
  78  *
  79  *      %r2:    Initial CRC value, typically ~0; and final CRC (return) value.
  80  *      %r3:    Input buffer pointer, performance might be improved if the
  81  *              buffer is on a doubleword boundary.
  82  *      %r4:    Length of the buffer, must be 64 bytes or greater.
  83  *
  84  * Register usage:
  85  *
  86  *      %r5:    CRC-32 constant pool base pointer.
  87  *      V0:     Initial CRC value and intermediate constants and results.
  88  *      V1..V4: Data for CRC computation.
  89  *      V5..V8: Next data chunks that are fetched from the input buffer.
  90  *
  91  *      V9..V14: CRC-32 constants.
  92  */
  93 ENTRY(crc32_be_vgfm_16)
  94         /* Load CRC-32 constants */
  95         larl    %r5,.Lconstants_CRC_32_BE
  96         VLM     CONST_R1R2,CONST_CRC_POLY,0,%r5
  97 
  98         /* Load the initial CRC value into the leftmost word of V0. */
  99         VZERO   %v0
 100         VLVGF   %v0,%r2,0
 101 
 102         /* Load a 64-byte data chunk and XOR with CRC */
 103         VLM     %v1,%v4,0,%r3           /* 64-bytes into V1..V4 */
 104         VX      %v1,%v0,%v1             /* V1 ^= CRC */
 105         aghi    %r3,64                  /* BUF = BUF + 64 */
 106         aghi    %r4,-64                 /* LEN = LEN - 64 */
 107 
 108         /* Check remaining buffer size and jump to proper folding method */
 109         cghi    %r4,64
 110         jl      .Lless_than_64bytes
 111 
 112 .Lfold_64bytes_loop:
 113         /* Load the next 64-byte data chunk into V5 to V8 */
 114         VLM     %v5,%v8,0,%r3
 115 
 116         /*
 117          * Perform a GF(2) multiplication of the doublewords in V1 with
 118          * the reduction constants in V0.  The intermediate result is
 119          * then folded (accumulated) with the next data chunk in V5 and
 120          * stored in V1.  Repeat this step for the register contents
 121          * in V2, V3, and V4 respectively.
 122          */
 123         VGFMAG  %v1,CONST_R1R2,%v1,%v5
 124         VGFMAG  %v2,CONST_R1R2,%v2,%v6
 125         VGFMAG  %v3,CONST_R1R2,%v3,%v7
 126         VGFMAG  %v4,CONST_R1R2,%v4,%v8
 127 
 128         /* Adjust buffer pointer and length for next loop */
 129         aghi    %r3,64                  /* BUF = BUF + 64 */
 130         aghi    %r4,-64                 /* LEN = LEN - 64 */
 131 
 132         cghi    %r4,64
 133         jnl     .Lfold_64bytes_loop
 134 
 135 .Lless_than_64bytes:
 136         /* Fold V1 to V4 into a single 128-bit value in V1 */
 137         VGFMAG  %v1,CONST_R3R4,%v1,%v2
 138         VGFMAG  %v1,CONST_R3R4,%v1,%v3
 139         VGFMAG  %v1,CONST_R3R4,%v1,%v4
 140 
 141         /* Check whether to continue with 64-bit folding */
 142         cghi    %r4,16
 143         jl      .Lfinal_fold
 144 
 145 .Lfold_16bytes_loop:
 146 
 147         VL      %v2,0,,%r3              /* Load next data chunk */
 148         VGFMAG  %v1,CONST_R3R4,%v1,%v2  /* Fold next data chunk */
 149 
 150         /* Adjust buffer pointer and size for folding next data chunk */
 151         aghi    %r3,16
 152         aghi    %r4,-16
 153 
 154         /* Process remaining data chunks */
 155         cghi    %r4,16
 156         jnl     .Lfold_16bytes_loop
 157 
 158 .Lfinal_fold:
 159         /*
 160          * The R5 constant is used to fold a 128-bit value into an 96-bit value
 161          * that is XORed with the next 96-bit input data chunk.  To use a single
 162          * VGFMG instruction, multiply the rightmost 64-bit with x^32 (1<<32) to
 163          * form an intermediate 96-bit value (with appended zeros) which is then
 164          * XORed with the intermediate reduction result.
 165          */
 166         VGFMG   %v1,CONST_R5,%v1
 167 
 168         /*
 169          * Further reduce the remaining 96-bit value to a 64-bit value using a
 170          * single VGFMG, the rightmost doubleword is multiplied with 0x1. The
 171          * intermediate result is then XORed with the product of the leftmost
 172          * doubleword with R6.  The result is a 64-bit value and is subject to
 173          * the Barret reduction.
 174          */
 175         VGFMG   %v1,CONST_R6,%v1
 176 
 177         /*
 178          * The input values to the Barret reduction are the degree-63 polynomial
 179          * in V1 (R(x)), degree-32 generator polynomial, and the reduction
 180          * constant u.  The Barret reduction result is the CRC value of R(x) mod
 181          * P(x).
 182          *
 183          * The Barret reduction algorithm is defined as:
 184          *
 185          *    1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
 186          *    2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)
 187          *    3. C(x)  = R(x) XOR T2(x) mod x^32
 188          *
 189          * Note: To compensate the division by x^32, use the vector unpack
 190          * instruction to move the leftmost word into the leftmost doubleword
 191          * of the vector register.  The rightmost doubleword is multiplied
 192          * with zero to not contribute to the intermedate results.
 193          */
 194 
 195         /* T1(x) = floor( R(x) / x^32 ) GF2MUL u */
 196         VUPLLF  %v2,%v1
 197         VGFMG   %v2,CONST_RU_POLY,%v2
 198 
 199         /*
 200          * Compute the GF(2) product of the CRC polynomial in VO with T1(x) in
 201          * V2 and XOR the intermediate result, T2(x),  with the value in V1.
 202          * The final result is in the rightmost word of V2.
 203          */
 204         VUPLLF  %v2,%v2
 205         VGFMAG  %v2,CONST_CRC_POLY,%v2,%v1
 206 
 207 .Ldone:
 208         VLGVF   %r2,%v2,3
 209         BR_EX   %r14
 210 ENDPROC(crc32_be_vgfm_16)
 211 
 212 .previous

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