root/arch/s390/include/asm/pci_clp.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_S390_PCI_CLP_H
   3 #define _ASM_S390_PCI_CLP_H
   4 
   5 #include <asm/clp.h>
   6 
   7 /*
   8  * Call Logical Processor - Command Codes
   9  */
  10 #define CLP_LIST_PCI            0x0002
  11 #define CLP_QUERY_PCI_FN        0x0003
  12 #define CLP_QUERY_PCI_FNGRP     0x0004
  13 #define CLP_SET_PCI_FN          0x0005
  14 
  15 /* PCI function handle list entry */
  16 struct clp_fh_list_entry {
  17         u16 device_id;
  18         u16 vendor_id;
  19         u32 config_state :  1;
  20         u32              : 31;
  21         u32 fid;                /* PCI function id */
  22         u32 fh;                 /* PCI function handle */
  23 } __packed;
  24 
  25 #define CLP_RC_SETPCIFN_FH      0x0101  /* Invalid PCI fn handle */
  26 #define CLP_RC_SETPCIFN_FHOP    0x0102  /* Fn handle not valid for op */
  27 #define CLP_RC_SETPCIFN_DMAAS   0x0103  /* Invalid DMA addr space */
  28 #define CLP_RC_SETPCIFN_RES     0x0104  /* Insufficient resources */
  29 #define CLP_RC_SETPCIFN_ALRDY   0x0105  /* Fn already in requested state */
  30 #define CLP_RC_SETPCIFN_ERR     0x0106  /* Fn in permanent error state */
  31 #define CLP_RC_SETPCIFN_RECPND  0x0107  /* Error recovery pending */
  32 #define CLP_RC_SETPCIFN_BUSY    0x0108  /* Fn busy */
  33 #define CLP_RC_LISTPCI_BADRT    0x010a  /* Resume token not recognized */
  34 #define CLP_RC_QUERYPCIFG_PFGID 0x010b  /* Unrecognized PFGID */
  35 
  36 /* request or response block header length */
  37 #define LIST_PCI_HDR_LEN        32
  38 
  39 /* Number of function handles fitting in response block */
  40 #define CLP_FH_LIST_NR_ENTRIES                          \
  41         ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)          \
  42                 / sizeof(struct clp_fh_list_entry))
  43 
  44 #define CLP_SET_ENABLE_PCI_FN   0       /* Yes, 0 enables it */
  45 #define CLP_SET_DISABLE_PCI_FN  1       /* Yes, 1 disables it */
  46 #define CLP_SET_ENABLE_MIO      2
  47 #define CLP_SET_DISABLE_MIO     3
  48 
  49 #define CLP_UTIL_STR_LEN        64
  50 #define CLP_PFIP_NR_SEGMENTS    4
  51 
  52 extern bool zpci_unique_uid;
  53 
  54 /* List PCI functions request */
  55 struct clp_req_list_pci {
  56         struct clp_req_hdr hdr;
  57         u64 resume_token;
  58         u64 reserved2;
  59 } __packed;
  60 
  61 /* List PCI functions response */
  62 struct clp_rsp_list_pci {
  63         struct clp_rsp_hdr hdr;
  64         u64 resume_token;
  65         u32 reserved2;
  66         u16 max_fn;
  67         u8                      : 7;
  68         u8 uid_checking         : 1;
  69         u8 entry_size;
  70         struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
  71 } __packed;
  72 
  73 struct mio_info {
  74         u32 valid : 6;
  75         u32 : 26;
  76         u32 : 32;
  77         struct {
  78                 u64 wb;
  79                 u64 wt;
  80         } addr[PCI_BAR_COUNT];
  81         u32 reserved[6];
  82 } __packed;
  83 
  84 /* Query PCI function request */
  85 struct clp_req_query_pci {
  86         struct clp_req_hdr hdr;
  87         u32 fh;                         /* function handle */
  88         u32 reserved2;
  89         u64 reserved3;
  90 } __packed;
  91 
  92 /* Query PCI function response */
  93 struct clp_rsp_query_pci {
  94         struct clp_rsp_hdr hdr;
  95         u16 vfn;                        /* virtual fn number */
  96         u16                     :  6;
  97         u16 mio_addr_avail      :  1;
  98         u16 util_str_avail      :  1;   /* utility string available? */
  99         u16 pfgid               :  8;   /* pci function group id */
 100         u32 fid;                        /* pci function id */
 101         u8 bar_size[PCI_BAR_COUNT];
 102         u16 pchid;
 103         __le32 bar[PCI_BAR_COUNT];
 104         u8 pfip[CLP_PFIP_NR_SEGMENTS];  /* pci function internal path */
 105         u32                     : 16;
 106         u8 fmb_len;
 107         u8 pft;                         /* pci function type */
 108         u64 sdma;                       /* start dma as */
 109         u64 edma;                       /* end dma as */
 110         u32 reserved[11];
 111         u32 uid;                        /* user defined id */
 112         u8 util_str[CLP_UTIL_STR_LEN];  /* utility string */
 113         u32 reserved2[16];
 114         struct mio_info mio;
 115 } __packed;
 116 
 117 /* Query PCI function group request */
 118 struct clp_req_query_pci_grp {
 119         struct clp_req_hdr hdr;
 120         u32 reserved2           : 24;
 121         u32 pfgid               :  8;   /* function group id */
 122         u32 reserved3;
 123         u64 reserved4;
 124 } __packed;
 125 
 126 /* Query PCI function group response */
 127 struct clp_rsp_query_pci_grp {
 128         struct clp_rsp_hdr hdr;
 129         u16                     :  4;
 130         u16 noi                 : 12;   /* number of interrupts */
 131         u8 version;
 132         u8                      :  6;
 133         u8 frame                :  1;
 134         u8 refresh              :  1;   /* TLB refresh mode */
 135         u16 reserved2;
 136         u16 mui;
 137         u16                     : 16;
 138         u16 maxfaal;
 139         u16                     :  4;
 140         u16 dnoi                : 12;
 141         u16 maxcpu;
 142         u64 dasm;                       /* dma address space mask */
 143         u64 msia;                       /* MSI address */
 144         u64 reserved4;
 145         u64 reserved5;
 146 } __packed;
 147 
 148 /* Set PCI function request */
 149 struct clp_req_set_pci {
 150         struct clp_req_hdr hdr;
 151         u32 fh;                         /* function handle */
 152         u16 reserved2;
 153         u8 oc;                          /* operation controls */
 154         u8 ndas;                        /* number of dma spaces */
 155         u64 reserved3;
 156 } __packed;
 157 
 158 /* Set PCI function response */
 159 struct clp_rsp_set_pci {
 160         struct clp_rsp_hdr hdr;
 161         u32 fh;                         /* function handle */
 162         u32 reserved1;
 163         u64 reserved2;
 164         struct mio_info mio;
 165 } __packed;
 166 
 167 /* Combined request/response block structures used by clp insn */
 168 struct clp_req_rsp_list_pci {
 169         struct clp_req_list_pci request;
 170         struct clp_rsp_list_pci response;
 171 } __packed;
 172 
 173 struct clp_req_rsp_set_pci {
 174         struct clp_req_set_pci request;
 175         struct clp_rsp_set_pci response;
 176 } __packed;
 177 
 178 struct clp_req_rsp_query_pci {
 179         struct clp_req_query_pci request;
 180         struct clp_rsp_query_pci response;
 181 } __packed;
 182 
 183 struct clp_req_rsp_query_pci_grp {
 184         struct clp_req_query_pci_grp request;
 185         struct clp_rsp_query_pci_grp response;
 186 } __packed;
 187 
 188 #endif