This source file includes following definitions.
- merge_attr
- cpumf_cf_event_group
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7 #include <linux/slab.h>
8 #include <linux/perf_event.h>
9 #include <asm/cpu_mf.h>
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13
14 CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
15 CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
16 CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
17 CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
18 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
19 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
20 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
21 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
22 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
23 CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
24 CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
25 CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
26 CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
27 CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
28 CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
29 CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
30 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
31 CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
32 CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
33 CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
34 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040);
35 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041);
36 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042);
37 CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043);
38 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044);
39 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045);
40 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046);
41 CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047);
42 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048);
43 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049);
44 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a);
45 CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b);
46 CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c);
47 CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d);
48 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e);
49 CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f);
50 CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050);
51 CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051);
52 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052);
53 CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053);
54 CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
55 CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
56 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
57 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
58 CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
59 CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
60 CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
61 CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
62 CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
63 CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
64 CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
65 CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
66 CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
67 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
68 CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
69 CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
70 CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
71 CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
72 CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
73 CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
74 CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
75 CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
76 CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
77 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
78 CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
79 CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
80 CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
81 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
82 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
83 CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
84 CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
85 CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
86 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
87 CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
88 CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
89 CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
90 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
91 CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
92 CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
93 CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
94 CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
95 CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
96 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
97 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
98 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
99 CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
100 CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
101 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
102 CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
103 CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
104 CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
105 CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
106 CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
107 CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
108 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
109 CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
110 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
111 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
112 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
113 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
114 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
115 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
116 CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
117 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
118 CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
119 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
120 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
121 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
122 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
123 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
124 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
125 CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
126 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
127 CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
128 CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
129 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
130 CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
131 CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080);
132 CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081);
133 CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082);
134 CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083);
135 CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084);
136 CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085);
137 CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086);
138 CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087);
139 CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088);
140 CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089);
141 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a);
142 CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b);
143 CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c);
144 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d);
145 CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f);
146 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
147 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091);
148 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092);
149 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093);
150 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094);
151 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095);
152 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096);
153 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097);
154 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098);
155 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099);
156 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a);
157 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b);
158 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c);
159 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d);
160 CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e);
161 CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f);
162 CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0);
163 CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1);
164 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
165 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3);
166 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4);
167 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5);
168 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6);
169 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7);
170 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8);
171 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9);
172 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa);
173 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab);
174 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac);
175 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad);
176 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae);
177 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af);
178 CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0);
179 CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1);
180 CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2);
181 CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3);
182 CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da);
183 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
184 CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
185 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
186 CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
187 CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080);
188 CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
189 CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
190 CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
191 CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
192 CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
193 CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
194 CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
195 CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
196 CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
197 CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
198 CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
199 CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
200 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
201 CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
202 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
203 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
204 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
205 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
206 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
207 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
208 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
209 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
210 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
211 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
212 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
213 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
214 CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
215 CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
216 CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
217 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
218 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
219 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
220 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
221 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
222 CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
223 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
224 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
225 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
226 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
227 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
228 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
229 CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
230 CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
231 CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
232 CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
233 CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
234 CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8);
235 CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
236 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237 CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239 CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240
241 static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
242 CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
243 CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
244 CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
245 CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
246 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
247 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
248 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
249 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
250 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
251 CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
252 CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
253 CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
254 NULL,
255 };
256
257 static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
258 CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
259 CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
260 CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
261 CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
262 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
263 CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
264 CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
265 CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
266 NULL,
267 };
268
269 static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
270 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
271 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
272 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
273 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
274 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
275 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
276 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
277 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
278 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
279 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
280 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
281 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
282 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
283 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
284 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
285 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
286 NULL,
287 };
288
289 static struct attribute *cpumcf_svn_6_pmu_event_attr[] __initdata = {
290 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
291 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
292 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
293 CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES),
294 CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS),
295 CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES),
296 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS),
297 CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES),
298 CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS),
299 CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES),
300 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS),
301 CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES),
302 CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS),
303 CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES),
304 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS),
305 CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES),
306 CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT),
307 CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT),
308 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT),
309 CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT),
310 NULL,
311 };
312
313 static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
314 CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
315 CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
316 CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
317 CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
318 CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
319 CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
320 CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
321 CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
322 CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
323 CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
324 CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
325 CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
326 CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
327 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
328 CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
329 CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
330 CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
331 CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
332 NULL,
333 };
334
335 static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
336 CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
337 CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
338 CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
339 CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
340 CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
341 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
342 CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
343 CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
344 CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
345 CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
346 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
347 CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
348 CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
349 CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
350 CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
351 CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
352 CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
353 CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
354 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
355 CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
356 CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
357 CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
358 CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
359 CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
360 NULL,
361 };
362
363 static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
364 CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
365 CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
366 CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
367 CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
368 CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
369 CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
370 CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
371 CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
372 CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
373 CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
374 CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
375 CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
376 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
377 CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
378 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
379 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
380 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
381 CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
382 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
383 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
384 CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
385 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
386 CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
387 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
388 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
389 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
390 CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
391 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
392 CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
393 CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
394 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
395 CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
396 CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
397 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
398 CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
399 NULL,
400 };
401
402 static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
403 CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES),
404 CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES),
405 CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES),
406 CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES),
407 CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES),
408 CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES),
409 CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES),
410 CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES),
411 CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES),
412 CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES),
413 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES),
414 CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES),
415 CPUMF_EVENT_PTR(cf_z13, TX_C_TEND),
416 CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND),
417 CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES),
418 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES),
419 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
420 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES),
421 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV),
422 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES),
423 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES),
424 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV),
425 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES),
426 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
427 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
428 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
429 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
430 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
431 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
432 CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES),
433 CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES),
434 CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES),
435 CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES),
436 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES),
437 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
438 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES),
439 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV),
440 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES),
441 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES),
442 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV),
443 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES),
444 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES),
445 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV),
446 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES),
447 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES),
448 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV),
449 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES),
450 CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES),
451 CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES),
452 CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES),
453 CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES),
454 CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT),
455 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL),
456 CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL),
457 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
458 CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
459 NULL,
460 };
461
462 static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
463 CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES),
464 CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
465 CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
466 CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
467 CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
468 CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
469 CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
470 CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
471 CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
472 CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
473 CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
474 CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
475 CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
476 CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
477 CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
478 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
479 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
480 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
481 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
482 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
483 CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
484 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
485 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
486 CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
487 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
488 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
489 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
490 CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
491 CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
492 CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
493 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
494 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
495 CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
496 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
497 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
498 CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
499 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
500 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
501 CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
502 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
503 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
504 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
505 CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
506 CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
507 CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
508 CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
509 CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
510 CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
511 CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
512 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
513 CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
514 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
515 CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
516 NULL,
517 };
518
519
520
521 static struct attribute_group cpumcf_pmu_events_group = {
522 .name = "events",
523 };
524
525 PMU_FORMAT_ATTR(event, "config:0-63");
526
527 static struct attribute *cpumcf_pmu_format_attr[] = {
528 &format_attr_event.attr,
529 NULL,
530 };
531
532 static struct attribute_group cpumcf_pmu_format_group = {
533 .name = "format",
534 .attrs = cpumcf_pmu_format_attr,
535 };
536
537 static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
538 &cpumcf_pmu_events_group,
539 &cpumcf_pmu_format_group,
540 NULL,
541 };
542
543
544 static __init struct attribute **merge_attr(struct attribute **a,
545 struct attribute **b,
546 struct attribute **c)
547 {
548 struct attribute **new;
549 int j, i;
550
551 for (j = 0; a[j]; j++)
552 ;
553 for (i = 0; b[i]; i++)
554 j++;
555 for (i = 0; c[i]; i++)
556 j++;
557 j++;
558
559 new = kmalloc_array(j, sizeof(struct attribute *), GFP_KERNEL);
560 if (!new)
561 return NULL;
562 j = 0;
563 for (i = 0; a[i]; i++)
564 new[j++] = a[i];
565 for (i = 0; b[i]; i++)
566 new[j++] = b[i];
567 for (i = 0; c[i]; i++)
568 new[j++] = c[i];
569 new[j] = NULL;
570
571 return new;
572 }
573
574 __init const struct attribute_group **cpumf_cf_event_group(void)
575 {
576 struct attribute **combined, **model, **cfvn, **csvn;
577 struct attribute *none[] = { NULL };
578 struct cpumf_ctr_info ci;
579 struct cpuid cpu_id;
580
581
582 qctri(&ci);
583 switch (ci.cfvn) {
584 case 1:
585 cfvn = cpumcf_fvn1_pmu_event_attr;
586 break;
587 case 3:
588 cfvn = cpumcf_fvn3_pmu_event_attr;
589 break;
590 default:
591 cfvn = none;
592 }
593
594
595 switch (ci.csvn) {
596 case 1 ... 5:
597 csvn = cpumcf_svn_12345_pmu_event_attr;
598 break;
599 case 6:
600 csvn = cpumcf_svn_6_pmu_event_attr;
601 break;
602 default:
603 csvn = none;
604 }
605
606
607 get_cpu_id(&cpu_id);
608 switch (cpu_id.machine) {
609 case 0x2097:
610 case 0x2098:
611 model = cpumcf_z10_pmu_event_attr;
612 break;
613 case 0x2817:
614 case 0x2818:
615 model = cpumcf_z196_pmu_event_attr;
616 break;
617 case 0x2827:
618 case 0x2828:
619 model = cpumcf_zec12_pmu_event_attr;
620 break;
621 case 0x2964:
622 case 0x2965:
623 model = cpumcf_z13_pmu_event_attr;
624 break;
625 case 0x3906:
626 case 0x3907:
627 case 0x8561:
628 case 0x8562:
629 model = cpumcf_z14_pmu_event_attr;
630 break;
631 default:
632 model = none;
633 break;
634 }
635
636 combined = merge_attr(cfvn, csvn, model);
637 if (combined)
638 cpumcf_pmu_events_group.attrs = combined;
639 return cpumcf_pmu_attr_groups;
640 }