arch/alpha/include/asm/core

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This source file includes following definitions.
__mcpcia_is_mmio
mcpcia_ioread8
mcpcia_iowrite8
mcpcia_ioread16
mcpcia_iowrite16
mcpcia_ioread32
mcpcia_iowrite32
mcpcia_ioportmap
mcpcia_ioremap
mcpcia_is_ioaddr
mcpcia_is_mmio
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ALPHA_MCPCIA__H__
   3 #define __ALPHA_MCPCIA__H__
   4 
   5 /* Define to experiment with fitting everything into one 128MB HAE window.
   6    One window per bus, that is.  */
   7 #define MCPCIA_ONE_HAE_WINDOW 1
   8 
   9 #include <linux/types.h>
  10 #include <asm/compiler.h>
  11 #include <asm/mce.h>
  12 
  13 /*
  14  * MCPCIA is the internal name for a core logic chipset which provides
  15  * PCI access for the RAWHIDE family of systems.
  16  *
  17  * This file is based on:
  18  *
  19  * RAWHIDE System Programmer's Manual
  20  * 16-May-96
  21  * Rev. 1.4
  22  *
  23  */
  24 
  25 /*------------------------------------------------------------------------**
  26 **                                                                        **
  27 **  I/O procedures                                                        **
  28 **                                                                        **
  29 **      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
  30 **      inportbxt: 8 bits only                                            **
  31 **      inport:    alias of inportw                                       **
  32 **      outport:   alias of outportw                                      **
  33 **                                                                        **
  34 **      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
  35 **      inmembxt: 8 bits only                                             **
  36 **      inmem:    alias of inmemw                                         **
  37 **      outmem:   alias of outmemw                                        **
  38 **                                                                        **
  39 **------------------------------------------------------------------------*/
  40 
  41 
  42 /* MCPCIA ADDRESS BIT DEFINITIONS
  43  *
  44  *  3333 3333 3322 2222 2222 1111 1111 11
  45  *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
  46  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
  47  *  1                                             000
  48  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
  49  *  |                                             |\|
  50  *  |                               Byte Enable --+ |
  51  *  |                             Transfer Length --+
  52  *  +-- IO space, not cached
  53  *
  54  *   Byte      Transfer
  55  *   Enable    Length    Transfer  Byte    Address
  56  *   adr<6:5>  adr<4:3>  Length    Enable  Adder
  57  *   ---------------------------------------------
  58  *      00        00      Byte      1110   0x000
  59  *      01        00      Byte      1101   0x020
  60  *      10        00      Byte      1011   0x040
  61  *      11        00      Byte      0111   0x060
  62  *
  63  *      00        01      Word      1100   0x008
  64  *      01        01      Word      1001   0x028 <= Not supported in this code.
  65  *      10        01      Word      0011   0x048
  66  *
  67  *      00        10      Tribyte   1000   0x010
  68  *      01        10      Tribyte   0001   0x030
  69  *
  70  *      10        11      Longword  0000   0x058
  71  *
  72  *      Note that byte enables are asserted low.
  73  *
  74  */
  75 
  76 #define MCPCIA_MAX_HOSES 4
  77 
  78 #define MCPCIA_MID(m)           ((unsigned long)(m) << 33)
  79 
  80 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. 
  81    Durango adds PCI2 and PCI3 at MID 6 and 7 respectively.  */
  82 #define MCPCIA_HOSE2MID(h)      ((h) + 4)
  83 
  84 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
  85 
  86 /*
  87  * Memory spaces:
  88  */
  89 #define MCPCIA_SPARSE(m)        (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
  90 #define MCPCIA_DENSE(m)         (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
  91 #define MCPCIA_IO(m)            (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
  92 #define MCPCIA_CONF(m)          (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
  93 #define MCPCIA_CSR(m)           (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
  94 #define MCPCIA_IO_IACK(m)       (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
  95 #define MCPCIA_DENSE_IO(m)      (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
  96 #define MCPCIA_DENSE_CONF(m)    (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
  97 
  98 /*
  99  *  General Registers
 100  */
 101 #define MCPCIA_REV(m)           (MCPCIA_CSR(m) + 0x000)
 102 #define MCPCIA_WHOAMI(m)        (MCPCIA_CSR(m) + 0x040)
 103 #define MCPCIA_PCI_LAT(m)       (MCPCIA_CSR(m) + 0x080)
 104 #define MCPCIA_CAP_CTRL(m)      (MCPCIA_CSR(m) + 0x100)
 105 #define MCPCIA_HAE_MEM(m)       (MCPCIA_CSR(m) + 0x400)
 106 #define MCPCIA_HAE_IO(m)        (MCPCIA_CSR(m) + 0x440)
 107 #define _MCPCIA_IACK_SC(m)      (MCPCIA_CSR(m) + 0x480)
 108 #define MCPCIA_HAE_DENSE(m)     (MCPCIA_CSR(m) + 0x4C0)
 109 
 110 /*
 111  * Interrupt Control registers
 112  */
 113 #define MCPCIA_INT_CTL(m)       (MCPCIA_CSR(m) + 0x500)
 114 #define MCPCIA_INT_REQ(m)       (MCPCIA_CSR(m) + 0x540)
 115 #define MCPCIA_INT_TARG(m)      (MCPCIA_CSR(m) + 0x580)
 116 #define MCPCIA_INT_ADR(m)       (MCPCIA_CSR(m) + 0x5C0)
 117 #define MCPCIA_INT_ADR_EXT(m)   (MCPCIA_CSR(m) + 0x600)
 118 #define MCPCIA_INT_MASK0(m)     (MCPCIA_CSR(m) + 0x640)
 119 #define MCPCIA_INT_MASK1(m)     (MCPCIA_CSR(m) + 0x680)
 120 #define MCPCIA_INT_ACK0(m)      (MCPCIA_CSR(m) + 0x10003f00)
 121 #define MCPCIA_INT_ACK1(m)      (MCPCIA_CSR(m) + 0x10003f40)
 122 
 123 /*
 124  * Performance Monitor registers
 125  */
 126 #define MCPCIA_PERF_MON(m)      (MCPCIA_CSR(m) + 0x300)
 127 #define MCPCIA_PERF_CONT(m)     (MCPCIA_CSR(m) + 0x340)
 128 
 129 /*
 130  * Diagnostic Registers
 131  */
 132 #define MCPCIA_CAP_DIAG(m)      (MCPCIA_CSR(m) + 0x700)
 133 #define MCPCIA_TOP_OF_MEM(m)    (MCPCIA_CSR(m) + 0x7C0)
 134 
 135 /*
 136  * Error registers
 137  */
 138 #define MCPCIA_MC_ERR0(m)       (MCPCIA_CSR(m) + 0x800)
 139 #define MCPCIA_MC_ERR1(m)       (MCPCIA_CSR(m) + 0x840)
 140 #define MCPCIA_CAP_ERR(m)       (MCPCIA_CSR(m) + 0x880)
 141 #define MCPCIA_PCI_ERR1(m)      (MCPCIA_CSR(m) + 0x1040)
 142 #define MCPCIA_MDPA_STAT(m)     (MCPCIA_CSR(m) + 0x4000)
 143 #define MCPCIA_MDPA_SYN(m)      (MCPCIA_CSR(m) + 0x4040)
 144 #define MCPCIA_MDPA_DIAG(m)     (MCPCIA_CSR(m) + 0x4080)
 145 #define MCPCIA_MDPB_STAT(m)     (MCPCIA_CSR(m) + 0x8000)
 146 #define MCPCIA_MDPB_SYN(m)      (MCPCIA_CSR(m) + 0x8040)
 147 #define MCPCIA_MDPB_DIAG(m)     (MCPCIA_CSR(m) + 0x8080)
 148 
 149 /*
 150  * PCI Address Translation Registers.
 151  */
 152 #define MCPCIA_SG_TBIA(m)       (MCPCIA_CSR(m) + 0x1300)
 153 #define MCPCIA_HBASE(m)         (MCPCIA_CSR(m) + 0x1340)
 154 
 155 #define MCPCIA_W0_BASE(m)       (MCPCIA_CSR(m) + 0x1400)
 156 #define MCPCIA_W0_MASK(m)       (MCPCIA_CSR(m) + 0x1440)
 157 #define MCPCIA_T0_BASE(m)       (MCPCIA_CSR(m) + 0x1480)
 158 
 159 #define MCPCIA_W1_BASE(m)       (MCPCIA_CSR(m) + 0x1500)
 160 #define MCPCIA_W1_MASK(m)       (MCPCIA_CSR(m) + 0x1540)
 161 #define MCPCIA_T1_BASE(m)       (MCPCIA_CSR(m) + 0x1580)
 162 
 163 #define MCPCIA_W2_BASE(m)       (MCPCIA_CSR(m) + 0x1600)
 164 #define MCPCIA_W2_MASK(m)       (MCPCIA_CSR(m) + 0x1640)
 165 #define MCPCIA_T2_BASE(m)       (MCPCIA_CSR(m) + 0x1680)
 166 
 167 #define MCPCIA_W3_BASE(m)       (MCPCIA_CSR(m) + 0x1700)
 168 #define MCPCIA_W3_MASK(m)       (MCPCIA_CSR(m) + 0x1740)
 169 #define MCPCIA_T3_BASE(m)       (MCPCIA_CSR(m) + 0x1780)
 170 
 171 /* Hack!  Only words for bus 0.  */
 172 
 173 #ifndef MCPCIA_ONE_HAE_WINDOW
 174 #define MCPCIA_HAE_ADDRESS      MCPCIA_HAE_MEM(4)
 175 #endif
 176 #define MCPCIA_IACK_SC          _MCPCIA_IACK_SC(4)
 177 
 178 /* 
 179  * The canonical non-remaped I/O and MEM addresses have these values
 180  * subtracted out.  This is arranged so that folks manipulating ISA
 181  * devices can use their familiar numbers and have them map to bus 0.
 182  */
 183 
 184 #define MCPCIA_IO_BIAS          MCPCIA_IO(4)
 185 #define MCPCIA_MEM_BIAS         MCPCIA_DENSE(4)
 186 
 187 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
 188 #define MCPCIA_DAC_OFFSET       (1UL << 40)
 189 
 190 /*
 191  * Data structure for handling MCPCIA machine checks:
 192  */
 193 struct el_MCPCIA_uncorrected_frame_mcheck {
 194         struct el_common header;
 195         struct el_common_EV5_uncorrectable_mcheck procdata;
 196 };
 197 
 198 
 199 #ifdef __KERNEL__
 200 
 201 #ifndef __EXTERN_INLINE
 202 #define __EXTERN_INLINE extern inline
 203 #define __IO_EXTERN_INLINE
 204 #endif
 205 
 206 /*
 207  * I/O functions:
 208  *
 209  * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
 210  * and EV56 (21164a) processors, can use either a sparse address mapping
 211  * scheme, or the so-called byte-word PCI address space, to get at PCI memory
 212  * and I/O.
 213  *
 214  * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
 215  */
 216 
 217 /*
 218  * Memory functions.  64-bit and 32-bit accesses are done through
 219  * dense memory space, everything else through sparse space.
 220  *
 221  * For reading and writing 8 and 16 bit quantities we need to
 222  * go through one of the three sparse address mapping regions
 223  * and use the HAE_MEM CSR to provide some bits of the address.
 224  * The following few routines use only sparse address region 1
 225  * which gives 1Gbyte of accessible space which relates exactly
 226  * to the amount of PCI memory mapping *into* system address space.
 227  * See p 6-17 of the specification but it looks something like this:
 228  *
 229  * 21164 Address:
 230  *
 231  *          3         2         1
 232  * 9876543210987654321098765432109876543210
 233  * 1ZZZZ0.PCI.QW.Address............BBLL
 234  *
 235  * ZZ = SBZ
 236  * BB = Byte offset
 237  * LL = Transfer length
 238  *
 239  * PCI Address:
 240  *
 241  * 3         2         1
 242  * 10987654321098765432109876543210
 243  * HHH....PCI.QW.Address........ 00
 244  *
 245  * HHH = 31:29 HAE_MEM CSR
 246  *
 247  */
 248 
 249 #define vip     volatile int __force *
 250 #define vuip    volatile unsigned int __force *
 251 
 252 #ifndef MCPCIA_ONE_HAE_WINDOW
 253 #define MCPCIA_FROB_MMIO                                                \
 254         if (__mcpcia_is_mmio(hose)) {                                   \
 255                 set_hae(hose & 0xffffffff);                             \
 256                 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);       \
 257         }
 258 #else
 259 #define MCPCIA_FROB_MMIO                                                \
 260         if (__mcpcia_is_mmio(hose)) {                                   \
 261                 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);       \
 262         }
 263 #endif
 264 
 265 extern inline int __mcpcia_is_mmio(unsigned long addr)
 266 {
 267         return (addr & 0x80000000UL) == 0;
 268 }
 269 
 270 __EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
 271 {
 272         unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
 273         unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
 274         unsigned long result;
 275 
 276         MCPCIA_FROB_MMIO;
 277 
 278         result = *(vip) ((addr << 5) + hose + 0x00);
 279         return __kernel_extbl(result, addr & 3);
 280 }
 281 
 282 __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
 283 {
 284         unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
 285         unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
 286         unsigned long w;
 287 
 288         MCPCIA_FROB_MMIO;
 289 
 290         w = __kernel_insbl(b, addr & 3);
 291         *(vuip) ((addr << 5) + hose + 0x00) = w;
 292 }
 293 
 294 __EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
 295 {
 296         unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
 297         unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
 298         unsigned long result;
 299 
 300         MCPCIA_FROB_MMIO;
 301 
 302         result = *(vip) ((addr << 5) + hose + 0x08);
 303         return __kernel_extwl(result, addr & 3);
 304 }
 305 
 306 __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
 307 {
 308         unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
 309         unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
 310         unsigned long w;
 311 
 312         MCPCIA_FROB_MMIO;
 313 
 314         w = __kernel_inswl(b, addr & 3);
 315         *(vuip) ((addr << 5) + hose + 0x08) = w;
 316 }
 317 
 318 __EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
 319 {
 320         unsigned long addr = (unsigned long)xaddr;
 321 
 322         if (!__mcpcia_is_mmio(addr))
 323                 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
 324 
 325         return *(vuip)addr;
 326 }
 327 
 328 __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
 329 {
 330         unsigned long addr = (unsigned long)xaddr;
 331 
 332         if (!__mcpcia_is_mmio(addr))
 333                 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
 334 
 335         *(vuip)addr = b;
 336 }
 337 
 338 
 339 __EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
 340 {
 341         return (void __iomem *)(addr + MCPCIA_IO_BIAS);
 342 }
 343 
 344 __EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
 345                                              unsigned long size)
 346 {
 347         return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
 348 }
 349 
 350 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
 351 {
 352         return addr >= MCPCIA_SPARSE(0);
 353 }
 354 
 355 __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
 356 {
 357         unsigned long addr = (unsigned long) xaddr;
 358         return __mcpcia_is_mmio(addr);
 359 }
 360 
 361 #undef MCPCIA_FROB_MMIO
 362 
 363 #undef vip
 364 #undef vuip
 365 
 366 #undef __IO_PREFIX
 367 #define __IO_PREFIX             mcpcia
 368 #define mcpcia_trivial_rw_bw    2
 369 #define mcpcia_trivial_rw_lq    1
 370 #define mcpcia_trivial_io_bw    0
 371 #define mcpcia_trivial_io_lq    0
 372 #define mcpcia_trivial_iounmap  1
 373 #include <asm/io_trivial.h>
 374 
 375 #ifdef __IO_EXTERN_INLINE
 376 #undef __EXTERN_INLINE
 377 #undef __IO_EXTERN_INLINE
 378 #endif
 379 
 380 #endif /* __KERNEL__ */
 381 
 382 #endif /* __ALPHA_MCPCIA__H__ */
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root/arch/alpha/include/asm/core_mcpcia.h

INCLUDED FROM

DEFINITIONS
