root/arch/alpha/include/asm/core_polaris.h

INCLUDED FROM

DEFINITIONS

1. polaris_ioportmap
2. polaris_ioremap
3. polaris_is_ioaddr
4. polaris_is_mmio

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ALPHA_POLARIS__H__
   3 #define __ALPHA_POLARIS__H__
   4 
   5 #include <linux/types.h>
   6 #include <asm/compiler.h>
   7 
   8 /*
   9  * POLARIS is the internal name for a core logic chipset which provides
  10  * memory controller and PCI access for the 21164PC chip based systems.
  11  *
  12  * This file is based on:
  13  *
  14  * Polaris System Controller
  15  * Device Functional Specification
  16  * 22-Jan-98
  17  * Rev. 4.2
  18  *
  19  */
  20 
  21 /* Polaris memory regions */
  22 #define POLARIS_SPARSE_MEM_BASE         (IDENT_ADDR + 0xf800000000UL)
  23 #define POLARIS_DENSE_MEM_BASE          (IDENT_ADDR + 0xf900000000UL)
  24 #define POLARIS_SPARSE_IO_BASE          (IDENT_ADDR + 0xf980000000UL)
  25 #define POLARIS_SPARSE_CONFIG_BASE      (IDENT_ADDR + 0xf9c0000000UL)
  26 #define POLARIS_IACK_BASE               (IDENT_ADDR + 0xf9f8000000UL)
  27 #define POLARIS_DENSE_IO_BASE           (IDENT_ADDR + 0xf9fc000000UL)
  28 #define POLARIS_DENSE_CONFIG_BASE       (IDENT_ADDR + 0xf9fe000000UL)
  29 
  30 #define POLARIS_IACK_SC                 POLARIS_IACK_BASE
  31 
  32 /* The Polaris command/status registers live in PCI Config space for
  33  * bus 0/device 0.  As such, they may be bytes, words, or doublewords.
  34  */
  35 #define POLARIS_W_VENID         (POLARIS_DENSE_CONFIG_BASE)
  36 #define POLARIS_W_DEVID         (POLARIS_DENSE_CONFIG_BASE+2)
  37 #define POLARIS_W_CMD           (POLARIS_DENSE_CONFIG_BASE+4)
  38 #define POLARIS_W_STATUS        (POLARIS_DENSE_CONFIG_BASE+6)
  39 
  40 /*
  41  * Data structure for handling POLARIS machine checks:
  42  */
  43 struct el_POLARIS_sysdata_mcheck {
  44     u_long      psc_status;
  45     u_long      psc_pcictl0;
  46     u_long      psc_pcictl1;
  47     u_long      psc_pcictl2;
  48 };
  49 
  50 #ifdef __KERNEL__
  51 
  52 #ifndef __EXTERN_INLINE
  53 #define __EXTERN_INLINE extern inline
  54 #define __IO_EXTERN_INLINE
  55 #endif
  56 
  57 /*
  58  * I/O functions:
  59  *
  60  * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)
  61  * processors, can use either a sparse address  mapping scheme, or the 
  62  * so-called byte-word PCI address space, to get at PCI memory and I/O.
  63  *
  64  * However, we will support only the BWX form.
  65  */
  66 
  67 /*
  68  * Memory functions.  Polaris allows all accesses (byte/word
  69  * as well as long/quad) to be done through dense space.
  70  *
  71  * We will only support DENSE access via BWX insns.
  72  */
  73 
  74 __EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr)
  75 {
  76         return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE);
  77 }
  78 
  79 __EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr,
  80                                               unsigned long size)
  81 {
  82         return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE);
  83 }
  84 
  85 __EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr)
  86 {
  87         return addr >= POLARIS_SPARSE_MEM_BASE;
  88 }
  89 
  90 __EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr)
  91 {
  92         return (unsigned long)addr < POLARIS_SPARSE_IO_BASE;
  93 }
  94 
  95 #undef __IO_PREFIX
  96 #define __IO_PREFIX             polaris
  97 #define polaris_trivial_rw_bw   1
  98 #define polaris_trivial_rw_lq   1
  99 #define polaris_trivial_io_bw   1
 100 #define polaris_trivial_io_lq   1
 101 #define polaris_trivial_iounmap 1
 102 #include <asm/io_trivial.h>
 103 
 104 #ifdef __IO_EXTERN_INLINE
 105 #undef __EXTERN_INLINE
 106 #undef __IO_EXTERN_INLINE
 107 #endif
 108 
 109 #endif /* __KERNEL__ */
 110 
 111 #endif /* __ALPHA_POLARIS__H__ */