arch/alpha/kernel/sys

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
sio_init_irq
alphabook1_init_arch
sio_pci_route
sio_pci_dev_irq_needs_level
sio_collect_irq_levels
__sio_fixup_irq_levels
sio_fixup_irq_levels
noname_map_irq
p2k_map_irq
noname_init_pci
alphabook1_init_pci
sio_kill_arch
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      linux/arch/alpha/kernel/sys_sio.c
   4  *
   5  *      Copyright (C) 1995 David A Rusling
   6  *      Copyright (C) 1996 Jay A Estabrook
   7  *      Copyright (C) 1998, 1999 Richard Henderson
   8  *
   9  * Code for all boards that route the PCI interrupts through the SIO
  10  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  11  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  12  */
  13 
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/sched.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/screen_info.h>
  21 
  22 #include <asm/compiler.h>
  23 #include <asm/ptrace.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31 #include <asm/tlbflush.h>
  32 
  33 #include "proto.h"
  34 #include "irq_impl.h"
  35 #include "pci_impl.h"
  36 #include "machvec_impl.h"
  37 #include "pc873xx.h"
  38 
  39 #if defined(ALPHA_RESTORE_SRM_SETUP)
  40 /* Save LCA configuration data as the console had it set up.  */
  41 struct 
  42 {
  43         unsigned int orig_route_tab; /* for SAVE/RESTORE */
  44 } saved_config __attribute((common));
  45 #endif
  46 
  47 
  48 static void __init
  49 sio_init_irq(void)
  50 {
  51         if (alpha_using_srm)
  52                 alpha_mv.device_interrupt = srm_device_interrupt;
  53 
  54         init_i8259a_irqs();
  55         common_init_isa_dma();
  56 }
  57 
  58 static inline void __init
  59 alphabook1_init_arch(void)
  60 {
  61         /* The AlphaBook1 has LCD video fixed at 800x600,
  62            37 rows and 100 cols. */
  63         screen_info.orig_y = 37;
  64         screen_info.orig_video_cols = 100;
  65         screen_info.orig_video_lines = 37;
  66 
  67         lca_init_arch();
  68 }
  69 
  70 
  71 /*
  72  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
  73  *              PIRQ0 -> irq 15
  74  *              PIRQ1 -> irq  9
  75  *              PIRQ2 -> irq 10
  76  *              PIRQ3 -> irq 11
  77  *
  78  * This probably ought to be configurable via MILO.  For
  79  * example, sound boards seem to like using IRQ 9.
  80  *
  81  * This is NOT how we should do it. PIRQ0-X should have
  82  * their own IRQs, the way intel uses the IO-APIC IRQs.
  83  */
  84 
  85 static void __init
  86 sio_pci_route(void)
  87 {
  88         unsigned int orig_route_tab;
  89 
  90         /* First, ALWAYS read and print the original setting. */
  91         pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
  92                                   &orig_route_tab);
  93         printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
  94                orig_route_tab, alpha_mv.sys.sio.route_tab);
  95 
  96 #if defined(ALPHA_RESTORE_SRM_SETUP)
  97         saved_config.orig_route_tab = orig_route_tab;
  98 #endif
  99 
 100         /* Now override with desired setting. */
 101         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 102                                    alpha_mv.sys.sio.route_tab);
 103 }
 104 
 105 static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
 106 {
 107         if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 108             (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 109                 return false;
 110 
 111         return true;
 112 }
 113 
 114 static unsigned int __init
 115 sio_collect_irq_levels(void)
 116 {
 117         unsigned int level_bits = 0;
 118         struct pci_dev *dev = NULL;
 119 
 120         /* Iterate through the devices, collecting IRQ levels.  */
 121         for_each_pci_dev(dev) {
 122                 if (!sio_pci_dev_irq_needs_level(dev))
 123                         continue;
 124 
 125                 if (dev->irq)
 126                         level_bits |= (1 << dev->irq);
 127         }
 128         return level_bits;
 129 }
 130 
 131 static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
 132 {
 133         unsigned int old_level_bits;
 134 
 135         /*
 136          * Now, make all PCI interrupts level sensitive.  Notice:
 137          * these registers must be accessed byte-wise.  inw()/outw()
 138          * don't work.
 139          *
 140          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 141          *  so that the only bits getting set are for devices actually found.
 142          * Note that we do preserve the remainder of the bits, which we hope
 143          *  will be set correctly by ARC/SRM.
 144          *
 145          * Note: we at least preserve any level-set bits on AlphaBook1
 146          */
 147         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 148 
 149         if (reset)
 150                 old_level_bits &= 0x71ff;
 151 
 152         level_bits |= old_level_bits;
 153 
 154         outb((level_bits >> 0) & 0xff, 0x4d0);
 155         outb((level_bits >> 8) & 0xff, 0x4d1);
 156 }
 157 
 158 static inline void
 159 sio_fixup_irq_levels(unsigned int level_bits)
 160 {
 161         __sio_fixup_irq_levels(level_bits, true);
 162 }
 163 
 164 static inline int
 165 noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 166 {
 167         /*
 168          * The Noname board has 5 PCI slots with each of the 4
 169          * interrupt pins routed to different pins on the PCI/ISA
 170          * bridge (PIRQ0-PIRQ3).  The table below is based on
 171          * information available at:
 172          *
 173          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 174          *
 175          * I have no information on the Avanti interrupt routing, but
 176          * the routing seems to be identical to the Noname except
 177          * that the Avanti has an additional slot whose routing I'm
 178          * unsure of.
 179          *
 180          * pirq_tab[0] is a fake entry to deal with old PCI boards
 181          * that have the interrupt pin number hardwired to 0 (meaning
 182          * that they use the default INTA line, if they are interrupt
 183          * driven at all).
 184          */
 185         static char irq_tab[][5] = {
 186                 /*INT A   B   C   D */
 187                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */ 
 188                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 189                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 190                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 191                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 192                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 193                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 194                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 195                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 196         };
 197         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 198         int irq = COMMON_TABLE_LOOKUP, tmp;
 199         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 200 
 201         irq = irq >= 0 ? tmp : -1;
 202 
 203         /* Fixup IRQ level if an actual IRQ mapping is detected */
 204         if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
 205                 __sio_fixup_irq_levels(1 << irq, false);
 206 
 207         return irq;
 208 }
 209 
 210 static inline int
 211 p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 212 {
 213         static char irq_tab[][5] = {
 214                 /*INT A   B   C   D */
 215                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 216                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 217                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 218                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 219                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 220                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 221                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 222         };
 223         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 224         int irq = COMMON_TABLE_LOOKUP, tmp;
 225         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 226         return irq >= 0 ? tmp : -1;
 227 }
 228 
 229 static inline void __init
 230 noname_init_pci(void)
 231 {
 232         common_init_pci();
 233         sio_pci_route();
 234         sio_fixup_irq_levels(sio_collect_irq_levels());
 235 
 236         if (pc873xx_probe() == -1) {
 237                 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
 238         } else {
 239                 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
 240                         pc873xx_get_model(), pc873xx_get_base());
 241 
 242                 /* Enabling things in the Super IO chip doesn't actually
 243                  * configure and enable things, the legacy drivers still
 244                  * need to do the actual configuration and enabling.
 245                  * This only unblocks them.
 246                  */
 247 
 248 #if !defined(CONFIG_ALPHA_AVANTI)
 249                 /* Don't bother on the Avanti family.
 250                  * None of them had on-board IDE.
 251                  */
 252                 pc873xx_enable_ide();
 253 #endif
 254                 pc873xx_enable_epp19();
 255         }
 256 }
 257 
 258 static inline void __init
 259 alphabook1_init_pci(void)
 260 {
 261         struct pci_dev *dev;
 262         unsigned char orig, config;
 263 
 264         common_init_pci();
 265         sio_pci_route();
 266 
 267         /*
 268          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 269          * is sensitive to PCI bus bursts, so we must DISABLE
 270          * burst mode for the NCR 8xx SCSI... :-(
 271          *
 272          * Note that the NCR810 SCSI driver must preserve the
 273          * setting of the bit in order for this to work.  At the
 274          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 275          * 53c7,8xx.c DOES.
 276          */
 277 
 278         dev = NULL;
 279         while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
 280                 if (dev->device == PCI_DEVICE_ID_NCR_53C810
 281                     || dev->device == PCI_DEVICE_ID_NCR_53C815
 282                     || dev->device == PCI_DEVICE_ID_NCR_53C820
 283                     || dev->device == PCI_DEVICE_ID_NCR_53C825) {
 284                         unsigned long io_port;
 285                         unsigned char ctest4;
 286 
 287                         io_port = dev->resource[0].start;
 288                         ctest4 = inb(io_port+0x21);
 289                         if (!(ctest4 & 0x80)) {
 290                                 printk("AlphaBook1 NCR init: setting"
 291                                        " burst disable\n");
 292                                 outb(ctest4 | 0x80, io_port+0x21);
 293                         }
 294                 }
 295         }
 296 
 297         /* Do not set *ANY* level triggers for AlphaBook1. */
 298         sio_fixup_irq_levels(0);
 299 
 300         /* Make sure that register PR1 indicates 1Mb mem */
 301         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 302         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 303         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 304         if ((config & 0xc0) != 0xc0) {
 305                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 306                 config |= 0xc0;
 307                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 308         }
 309         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 310 }
 311 
 312 void
 313 sio_kill_arch(int mode)
 314 {
 315 #if defined(ALPHA_RESTORE_SRM_SETUP)
 316         /* Since we cannot read the PCI DMA Window CSRs, we
 317          * cannot restore them here.
 318          *
 319          * However, we CAN read the PIRQ route register, so restore it
 320          * now...
 321          */
 322         pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
 323                                    saved_config.orig_route_tab);
 324 #endif
 325 }
 326 
 327 
 328 /*
 329  * The System Vectors
 330  */
 331 
 332 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 333 struct alpha_machine_vector alphabook1_mv __initmv = {
 334         .vector_name            = "AlphaBook1",
 335         DO_EV4_MMU,
 336         DO_DEFAULT_RTC,
 337         DO_LCA_IO,
 338         .machine_check          = lca_machine_check,
 339         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 340         .min_io_address         = DEFAULT_IO_BASE,
 341         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 342 
 343         .nr_irqs                = 16,
 344         .device_interrupt       = isa_device_interrupt,
 345 
 346         .init_arch              = alphabook1_init_arch,
 347         .init_irq               = sio_init_irq,
 348         .init_rtc               = common_init_rtc,
 349         .init_pci               = alphabook1_init_pci,
 350         .kill_arch              = sio_kill_arch,
 351         .pci_map_irq            = noname_map_irq,
 352         .pci_swizzle            = common_swizzle,
 353 
 354         .sys = { .sio = {
 355                 /* NCR810 SCSI is 14, PCMCIA controller is 15.  */
 356                 .route_tab      = 0x0e0f0a0a,
 357         }}
 358 };
 359 ALIAS_MV(alphabook1)
 360 #endif
 361 
 362 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 363 struct alpha_machine_vector avanti_mv __initmv = {
 364         .vector_name            = "Avanti",
 365         DO_EV4_MMU,
 366         DO_DEFAULT_RTC,
 367         DO_APECS_IO,
 368         .machine_check          = apecs_machine_check,
 369         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 370         .min_io_address         = DEFAULT_IO_BASE,
 371         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 372 
 373         .nr_irqs                = 16,
 374         .device_interrupt       = isa_device_interrupt,
 375 
 376         .init_arch              = apecs_init_arch,
 377         .init_irq               = sio_init_irq,
 378         .init_rtc               = common_init_rtc,
 379         .init_pci               = noname_init_pci,
 380         .kill_arch              = sio_kill_arch,
 381         .pci_map_irq            = noname_map_irq,
 382         .pci_swizzle            = common_swizzle,
 383 
 384         .sys = { .sio = {
 385                 .route_tab      = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
 386         }}
 387 };
 388 ALIAS_MV(avanti)
 389 #endif
 390 
 391 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 392 struct alpha_machine_vector noname_mv __initmv = {
 393         .vector_name            = "Noname",
 394         DO_EV4_MMU,
 395         DO_DEFAULT_RTC,
 396         DO_LCA_IO,
 397         .machine_check          = lca_machine_check,
 398         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 399         .min_io_address         = DEFAULT_IO_BASE,
 400         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 401 
 402         .nr_irqs                = 16,
 403         .device_interrupt       = srm_device_interrupt,
 404 
 405         .init_arch              = lca_init_arch,
 406         .init_irq               = sio_init_irq,
 407         .init_rtc               = common_init_rtc,
 408         .init_pci               = noname_init_pci,
 409         .kill_arch              = sio_kill_arch,
 410         .pci_map_irq            = noname_map_irq,
 411         .pci_swizzle            = common_swizzle,
 412 
 413         .sys = { .sio = {
 414                 /* For UDB, the only available PCI slot must not map to IRQ 9,
 415                    since that's the builtin MSS sound chip. That PCI slot
 416                    will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 417                    instead.
 418 
 419                    Unfortunately we have to do this for NONAME as well, since
 420                    they are co-indicated when the platform type "Noname" is
 421                    selected... :-(  */
 422 
 423                 .route_tab      = 0x0b0a0f0d,
 424         }}
 425 };
 426 ALIAS_MV(noname)
 427 #endif
 428 
 429 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 430 struct alpha_machine_vector p2k_mv __initmv = {
 431         .vector_name            = "Platform2000",
 432         DO_EV4_MMU,
 433         DO_DEFAULT_RTC,
 434         DO_LCA_IO,
 435         .machine_check          = lca_machine_check,
 436         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 437         .min_io_address         = DEFAULT_IO_BASE,
 438         .min_mem_address        = APECS_AND_LCA_DEFAULT_MEM_BASE,
 439 
 440         .nr_irqs                = 16,
 441         .device_interrupt       = srm_device_interrupt,
 442 
 443         .init_arch              = lca_init_arch,
 444         .init_irq               = sio_init_irq,
 445         .init_rtc               = common_init_rtc,
 446         .init_pci               = noname_init_pci,
 447         .kill_arch              = sio_kill_arch,
 448         .pci_map_irq            = p2k_map_irq,
 449         .pci_swizzle            = common_swizzle,
 450 
 451         .sys = { .sio = {
 452                 .route_tab      = 0x0b0a090f,
 453         }}
 454 };
 455 ALIAS_MV(p2k)
 456 #endif
 457 
 458 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 459 struct alpha_machine_vector xl_mv __initmv = {
 460         .vector_name            = "XL",
 461         DO_EV4_MMU,
 462         DO_DEFAULT_RTC,
 463         DO_APECS_IO,
 464         .machine_check          = apecs_machine_check,
 465         .max_isa_dma_address    = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
 466         .min_io_address         = DEFAULT_IO_BASE,
 467         .min_mem_address        = XL_DEFAULT_MEM_BASE,
 468 
 469         .nr_irqs                = 16,
 470         .device_interrupt       = isa_device_interrupt,
 471 
 472         .init_arch              = apecs_init_arch,
 473         .init_irq               = sio_init_irq,
 474         .init_rtc               = common_init_rtc,
 475         .init_pci               = noname_init_pci,
 476         .kill_arch              = sio_kill_arch,
 477         .pci_map_irq            = noname_map_irq,
 478         .pci_swizzle            = common_swizzle,
 479 
 480         .sys = { .sio = {
 481                 .route_tab      = 0x0b0a090f,
 482         }}
 483 };
 484 ALIAS_MV(xl)
 485 #endif
/* [<][>][^][v][top][bottom][index][help] */
root/arch/alpha/kernel/sys_sio.c

DEFINITIONS
