root/arch/alpha/kernel/sys_nautilus.c

DEFINITIONS

1. nautilus_init_irq
2. nautilus_map_irq
3. nautilus_kill_arch
4. naut_sys_machine_check
5. nautilus_machine_check
6. nautilus_init_pci

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      linux/arch/alpha/kernel/sys_nautilus.c
   4  *
   5  *      Copyright (C) 1995 David A Rusling
   6  *      Copyright (C) 1998 Richard Henderson
   7  *      Copyright (C) 1999 Alpha Processor, Inc.,
   8  *              (David Daniel, Stig Telfer, Soohoon Lee)
   9  *
  10  * Code supporting NAUTILUS systems.
  11  *
  12  *
  13  * NAUTILUS has the following I/O features:
  14  *
  15  * a) Driven by AMD 751 aka IRONGATE (northbridge):
  16  *     4 PCI slots
  17  *     1 AGP slot
  18  *
  19  * b) Driven by ALI M1543C (southbridge)
  20  *     2 ISA slots
  21  *     2 IDE connectors
  22  *     1 dual drive capable FDD controller
  23  *     2 serial ports
  24  *     1 ECP/EPP/SP parallel port
  25  *     2 USB ports
  26  */
  27 
  28 #include <linux/kernel.h>
  29 #include <linux/types.h>
  30 #include <linux/mm.h>
  31 #include <linux/sched.h>
  32 #include <linux/pci.h>
  33 #include <linux/init.h>
  34 #include <linux/reboot.h>
  35 #include <linux/memblock.h>
  36 #include <linux/bitops.h>
  37 
  38 #include <asm/ptrace.h>
  39 #include <asm/dma.h>
  40 #include <asm/irq.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/io.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/core_irongate.h>
  45 #include <asm/hwrpb.h>
  46 #include <asm/tlbflush.h>
  47 
  48 #include "proto.h"
  49 #include "err_impl.h"
  50 #include "irq_impl.h"
  51 #include "pci_impl.h"
  52 #include "machvec_impl.h"
  53 
  54 
  55 static void __init
  56 nautilus_init_irq(void)
  57 {
  58         if (alpha_using_srm) {
  59                 alpha_mv.device_interrupt = srm_device_interrupt;
  60         }
  61 
  62         init_i8259a_irqs();
  63         common_init_isa_dma();
  64 }
  65 
  66 static int
  67 nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  68 {
  69         /* Preserve the IRQ set up by the console.  */
  70 
  71         u8 irq;
  72         /* UP1500: AGP INTA is actually routed to IRQ 5, not IRQ 10 as
  73            console reports. Check the device id of AGP bridge to distinguish
  74            UP1500 from UP1000/1100. Note: 'pin' is 2 due to bridge swizzle. */
  75         if (slot == 1 && pin == 2 &&
  76             dev->bus->self && dev->bus->self->device == 0x700f)
  77                 return 5;
  78         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
  79         return irq;
  80 }
  81 
  82 void
  83 nautilus_kill_arch(int mode)
  84 {
  85         struct pci_bus *bus = pci_isa_hose->bus;
  86         u32 pmuport;
  87         int off;
  88 
  89         switch (mode) {
  90         case LINUX_REBOOT_CMD_RESTART:
  91                 if (! alpha_using_srm) {
  92                         u8 t8;
  93                         pci_bus_read_config_byte(bus, 0x38, 0x43, &t8);
  94                         pci_bus_write_config_byte(bus, 0x38, 0x43, t8 | 0x80);
  95                         outb(1, 0x92);
  96                         outb(0, 0x92);
  97                         /* NOTREACHED */
  98                 }
  99                 break;
 100 
 101         case LINUX_REBOOT_CMD_POWER_OFF:
 102                 /* Assume M1543C */
 103                 off = 0x2000;           /* SLP_TYPE = 0, SLP_EN = 1 */
 104                 pci_bus_read_config_dword(bus, 0x88, 0x10, &pmuport);
 105                 if (!pmuport) {
 106                         /* M1535D/D+ */
 107                         off = 0x3400;   /* SLP_TYPE = 5, SLP_EN = 1 */
 108                         pci_bus_read_config_dword(bus, 0x88, 0xe0, &pmuport);
 109                 }
 110                 pmuport &= 0xfffe;
 111                 outw(0xffff, pmuport);  /* Clear pending events. */
 112                 outw(off, pmuport + 4);
 113                 /* NOTREACHED */
 114                 break;
 115         }
 116 }
 117 
 118 /* Perform analysis of a machine check that arrived from the system (NMI) */
 119 
 120 static void
 121 naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
 122                        struct pt_regs *regs)
 123 {
 124         printk("PC %lx RA %lx\n", regs->pc, regs->r26);
 125         irongate_pci_clr_err();
 126 }
 127 
 128 /* Machine checks can come from two sources - those on the CPU and those
 129    in the system.  They are analysed separately but all starts here.  */
 130 
 131 void
 132 nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
 133 {
 134         char *mchk_class;
 135 
 136         /* Now for some analysis.  Machine checks fall into two classes --
 137            those picked up by the system, and those picked up by the CPU.
 138            Add to that the two levels of severity - correctable or not.  */
 139 
 140         if (vector == SCB_Q_SYSMCHK
 141             && ((IRONGATE0->dramms & 0x300) == 0x300)) {
 142                 unsigned long nmi_ctl;
 143 
 144                 /* Clear ALI NMI */
 145                 nmi_ctl = inb(0x61);
 146                 nmi_ctl |= 0x0c;
 147                 outb(nmi_ctl, 0x61);
 148                 nmi_ctl &= ~0x0c;
 149                 outb(nmi_ctl, 0x61);
 150 
 151                 /* Write again clears error bits.  */
 152                 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
 153                 mb();
 154                 IRONGATE0->stat_cmd;
 155 
 156                 /* Write again clears error bits.  */
 157                 IRONGATE0->dramms = IRONGATE0->dramms;
 158                 mb();
 159                 IRONGATE0->dramms;
 160 
 161                 draina();
 162                 wrmces(0x7);
 163                 mb();
 164                 return;
 165         }
 166 
 167         if (vector == SCB_Q_SYSERR)
 168                 mchk_class = "Correctable";
 169         else if (vector == SCB_Q_SYSMCHK)
 170                 mchk_class = "Fatal";
 171         else {
 172                 ev6_machine_check(vector, la_ptr);
 173                 return;
 174         }
 175 
 176         printk(KERN_CRIT "NAUTILUS Machine check 0x%lx "
 177                          "[%s System Machine Check (NMI)]\n",
 178                vector, mchk_class);
 179 
 180         naut_sys_machine_check(vector, la_ptr, get_irq_regs());
 181 
 182         /* Tell the PALcode to clear the machine check */
 183         draina();
 184         wrmces(0x7);
 185         mb();
 186 }
 187 
 188 extern void pcibios_claim_one_bus(struct pci_bus *);
 189 
 190 static struct resource irongate_io = {
 191         .name   = "Irongate PCI IO",
 192         .flags  = IORESOURCE_IO,
 193 };
 194 static struct resource irongate_mem = {
 195         .name   = "Irongate PCI MEM",
 196         .flags  = IORESOURCE_MEM,
 197 };
 198 static struct resource busn_resource = {
 199         .name   = "PCI busn",
 200         .start  = 0,
 201         .end    = 255,
 202         .flags  = IORESOURCE_BUS,
 203 };
 204 
 205 void __init
 206 nautilus_init_pci(void)
 207 {
 208         struct pci_controller *hose = hose_head;
 209         struct pci_host_bridge *bridge;
 210         struct pci_bus *bus;
 211         struct pci_dev *irongate;
 212         unsigned long bus_align, bus_size, pci_mem;
 213         unsigned long memtop = max_low_pfn << PAGE_SHIFT;
 214         int ret;
 215 
 216         bridge = pci_alloc_host_bridge(0);
 217         if (!bridge)
 218                 return;
 219 
 220         pci_add_resource(&bridge->windows, &ioport_resource);
 221         pci_add_resource(&bridge->windows, &iomem_resource);
 222         pci_add_resource(&bridge->windows, &busn_resource);
 223         bridge->dev.parent = NULL;
 224         bridge->sysdata = hose;
 225         bridge->busnr = 0;
 226         bridge->ops = alpha_mv.pci_ops;
 227         bridge->swizzle_irq = alpha_mv.pci_swizzle;
 228         bridge->map_irq = alpha_mv.pci_map_irq;
 229 
 230         /* Scan our single hose.  */
 231         ret = pci_scan_root_bus_bridge(bridge);
 232         if (ret) {
 233                 pci_free_host_bridge(bridge);
 234                 return;
 235         }
 236 
 237         bus = hose->bus = bridge->bus;
 238         pcibios_claim_one_bus(bus);
 239 
 240         irongate = pci_get_domain_bus_and_slot(pci_domain_nr(bus), 0, 0);
 241         bus->self = irongate;
 242         bus->resource[0] = &irongate_io;
 243         bus->resource[1] = &irongate_mem;
 244 
 245         pci_bus_size_bridges(bus);
 246 
 247         /* IO port range. */
 248         bus->resource[0]->start = 0;
 249         bus->resource[0]->end = 0xffff;
 250 
 251         /* Set up PCI memory range - limit is hardwired to 0xffffffff,
 252            base must be at aligned to 16Mb. */
 253         bus_align = bus->resource[1]->start;
 254         bus_size = bus->resource[1]->end + 1 - bus_align;
 255         if (bus_align < 0x1000000UL)
 256                 bus_align = 0x1000000UL;
 257 
 258         pci_mem = (0x100000000UL - bus_size) & -bus_align;
 259 
 260         bus->resource[1]->start = pci_mem;
 261         bus->resource[1]->end = 0xffffffffUL;
 262         if (request_resource(&iomem_resource, bus->resource[1]) < 0)
 263                 printk(KERN_ERR "Failed to request MEM on hose 0\n");
 264 
 265         if (pci_mem < memtop)
 266                 memtop = pci_mem;
 267         if (memtop > alpha_mv.min_mem_address) {
 268                 free_reserved_area(__va(alpha_mv.min_mem_address),
 269                                    __va(memtop), -1, NULL);
 270                 printk("nautilus_init_pci: %ldk freed\n",
 271                         (memtop - alpha_mv.min_mem_address) >> 10);
 272         }
 273 
 274         if ((IRONGATE0->dev_vendor >> 16) > 0x7006)     /* Albacore? */
 275                 IRONGATE0->pci_mem = pci_mem;
 276 
 277         pci_bus_assign_resources(bus);
 278 
 279         /* pci_common_swizzle() relies on bus->self being NULL
 280            for the root bus, so just clear it. */
 281         bus->self = NULL;
 282         pci_bus_add_devices(bus);
 283 }
 284 
 285 /*
 286  * The System Vectors
 287  */
 288 
 289 struct alpha_machine_vector nautilus_mv __initmv = {
 290         .vector_name            = "Nautilus",
 291         DO_EV6_MMU,
 292         DO_DEFAULT_RTC,
 293         DO_IRONGATE_IO,
 294         .machine_check          = nautilus_machine_check,
 295         .max_isa_dma_address    = ALPHA_MAX_ISA_DMA_ADDRESS,
 296         .min_io_address         = DEFAULT_IO_BASE,
 297         .min_mem_address        = IRONGATE_DEFAULT_MEM_BASE,
 298 
 299         .nr_irqs                = 16,
 300         .device_interrupt       = isa_device_interrupt,
 301 
 302         .init_arch              = irongate_init_arch,
 303         .init_irq               = nautilus_init_irq,
 304         .init_rtc               = common_init_rtc,
 305         .init_pci               = nautilus_init_pci,
 306         .kill_arch              = nautilus_kill_arch,
 307         .pci_map_irq            = nautilus_map_irq,
 308         .pci_swizzle            = common_swizzle,
 309 };
 310 ALIAS_MV(nautilus)