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10 #include <asm/pgalloc.h>
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16 #define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
17 #define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
18 #define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
19 #define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
20 #define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
21 #define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
22
23 #ifdef CIA_ONE_HAE_WINDOW
24 #define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
25 #endif
26 #ifdef MCPCIA_ONE_HAE_WINDOW
27 #define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
28 #endif
29 #ifdef T2_ONE_HAE_WINDOW
30 #define T2_HAE_ADDRESS (&alpha_mv.hae_cache)
31 #endif
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35
36 #define JENSEN_IACK_SC 1
37 #define T2_IACK_SC 1
38 #define WILDFIRE_IACK_SC 1
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43
44 #define CAT1(x,y) x##y
45 #define CAT(x,y) CAT1(x,y)
46
47 #define DO_DEFAULT_RTC .rtc_port = 0x70
48
49 #define DO_EV4_MMU \
50 .max_asn = EV4_MAX_ASN, \
51 .mv_switch_mm = ev4_switch_mm, \
52 .mv_activate_mm = ev4_activate_mm, \
53 .mv_flush_tlb_current = ev4_flush_tlb_current, \
54 .mv_flush_tlb_current_page = ev4_flush_tlb_current_page
55
56 #define DO_EV5_MMU \
57 .max_asn = EV5_MAX_ASN, \
58 .mv_switch_mm = ev5_switch_mm, \
59 .mv_activate_mm = ev5_activate_mm, \
60 .mv_flush_tlb_current = ev5_flush_tlb_current, \
61 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
62
63 #define DO_EV6_MMU \
64 .max_asn = EV6_MAX_ASN, \
65 .mv_switch_mm = ev5_switch_mm, \
66 .mv_activate_mm = ev5_activate_mm, \
67 .mv_flush_tlb_current = ev5_flush_tlb_current, \
68 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
69
70 #define DO_EV7_MMU \
71 .max_asn = EV6_MAX_ASN, \
72 .mv_switch_mm = ev5_switch_mm, \
73 .mv_activate_mm = ev5_activate_mm, \
74 .mv_flush_tlb_current = ev5_flush_tlb_current, \
75 .mv_flush_tlb_current_page = ev5_flush_tlb_current_page
76
77 #define IO_LITE(UP,low) \
78 .hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \
79 .iack_sc = CAT(UP,_IACK_SC), \
80 .mv_ioread8 = CAT(low,_ioread8), \
81 .mv_ioread16 = CAT(low,_ioread16), \
82 .mv_ioread32 = CAT(low,_ioread32), \
83 .mv_iowrite8 = CAT(low,_iowrite8), \
84 .mv_iowrite16 = CAT(low,_iowrite16), \
85 .mv_iowrite32 = CAT(low,_iowrite32), \
86 .mv_readb = CAT(low,_readb), \
87 .mv_readw = CAT(low,_readw), \
88 .mv_readl = CAT(low,_readl), \
89 .mv_readq = CAT(low,_readq), \
90 .mv_writeb = CAT(low,_writeb), \
91 .mv_writew = CAT(low,_writew), \
92 .mv_writel = CAT(low,_writel), \
93 .mv_writeq = CAT(low,_writeq), \
94 .mv_ioportmap = CAT(low,_ioportmap), \
95 .mv_ioremap = CAT(low,_ioremap), \
96 .mv_iounmap = CAT(low,_iounmap), \
97 .mv_is_ioaddr = CAT(low,_is_ioaddr), \
98 .mv_is_mmio = CAT(low,_is_mmio) \
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100 #define IO(UP,low) \
101 IO_LITE(UP,low), \
102 .pci_ops = &CAT(low,_pci_ops), \
103 .mv_pci_tbi = CAT(low,_pci_tbi)
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105 #define DO_APECS_IO IO(APECS,apecs)
106 #define DO_CIA_IO IO(CIA,cia)
107 #define DO_IRONGATE_IO IO(IRONGATE,irongate)
108 #define DO_LCA_IO IO(LCA,lca)
109 #define DO_MARVEL_IO IO(MARVEL,marvel)
110 #define DO_MCPCIA_IO IO(MCPCIA,mcpcia)
111 #define DO_POLARIS_IO IO(POLARIS,polaris)
112 #define DO_T2_IO IO(T2,t2)
113 #define DO_TSUNAMI_IO IO(TSUNAMI,tsunami)
114 #define DO_TITAN_IO IO(TITAN,titan)
115 #define DO_WILDFIRE_IO IO(WILDFIRE,wildfire)
116
117 #define DO_PYXIS_IO IO_LITE(CIA,cia_bwx), \
118 .pci_ops = &cia_pci_ops, \
119 .mv_pci_tbi = cia_pci_tbi
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137 #ifdef CONFIG_ALPHA_GENERIC
138 #define __initmv __initdata
139 #define ALIAS_MV(x)
140 #else
141 #define __initmv __refdata
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145
146 #if 0
147 #define ALIAS_MV(system) \
148 struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
149 EXPORT_SYMBOL(alpha_mv);
150 #else
151 #define ALIAS_MV(system) \
152 asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
153 EXPORT_SYMBOL(alpha_mv);
154 #endif
155 #endif