mcif_wb          1362 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mcif_wb *mcif_wb;
mcif_wb          1368 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
mcif_wb          1375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
mcif_wb          1376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
mcif_wb          1378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->enable_mcif(mcif_wb);
mcif_wb          1389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct mcif_wb *mcif_wb;
mcif_wb          1393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
mcif_wb          1396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	mcif_wb->funcs->disable_mcif(mcif_wb);
mcif_wb          2084 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
mcif_wb            76 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb,
mcif_wb            80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           153 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c static void mmhubbub2_config_mcif_arb(struct mcif_wb *mcif_wb,
mcif_wb           156 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
mcif_wb           210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb)
mcif_wb           223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb)
mcif_wb           231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
mcif_wb           282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c 	struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
mcif_wb           513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h 	struct mcif_wb base;
mcif_wb           519 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb,
mcif_wb           522 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb);
mcif_wb           524 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb);
mcif_wb           526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h void mcifwb2_dump_frame(struct mcif_wb *mcif_wb,
mcif_wb          1377 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.mcif_wb[i] != NULL) {
mcif_wb          1378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
mcif_wb          1379 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pool->base.mcif_wb[i] = NULL;
mcif_wb          3064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->mcif_wb[i] = &mcif_wb20->base;
mcif_wb           905 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.mcif_wb[i] != NULL) {
mcif_wb           906 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
mcif_wb           907 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pool->base.mcif_wb[i] = NULL;
mcif_wb           183 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
mcif_wb           315 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct mcif_wb *mcif_wb;
mcif_wb            35 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h struct mcif_wb;
mcif_wb           113 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h 	struct mcif_wb *mcif;
mcif_wb            75 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 	void (*enable_mcif)(struct mcif_wb *mcif_wb);
mcif_wb            77 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 	void (*disable_mcif)(struct mcif_wb *mcif_wb);
mcif_wb            80 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 		struct mcif_wb *mcif_wb,
mcif_wb            85 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 		struct mcif_wb *mcif_wb,
mcif_wb            89 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 		struct mcif_wb *mcif_wb,
mcif_wb            93 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h 		struct mcif_wb *mcif_wb,