CNTR_ODD          812 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
CNTR_ODD          813 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          815 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
CNTR_ODD          821 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
CNTR_ODD          822 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          824 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
CNTR_ODD          828 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          829 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          831 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CACHE_REFERENCES]    = { 0x45, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          832 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CACHE_MISSES]        = { 0x48, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          833 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          834 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_MISSES]       = { 0x16, CNTR_EVEN | CNTR_ODD },
CNTR_ODD          839 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
CNTR_ODD          841 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
CNTR_ODD          856 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          857 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          858 arch/mips/kernel/perf_event_mipsxx.c 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
CNTR_ODD          884 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          888 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
CNTR_ODD          894 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
CNTR_ODD          898 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
CNTR_ODD          910 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
CNTR_ODD          914 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_ODD, P },
CNTR_ODD          921 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
CNTR_ODD          925 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
CNTR_ODD          931 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
CNTR_ODD          935 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
CNTR_ODD          942 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
CNTR_ODD          946 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
CNTR_ODD          964 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
CNTR_ODD          965 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
CNTR_ODD          968 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
CNTR_ODD          969 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
CNTR_ODD          975 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
CNTR_ODD          979 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
CNTR_ODD          991 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
CNTR_ODD          995 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },
CNTR_ODD         1007 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
CNTR_ODD         1011 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
CNTR_ODD         1018 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
CNTR_ODD         1022 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
CNTR_ODD         1033 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x46, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1034 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x49, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1037 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x47, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1038 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x4a, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1043 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x84, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1044 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x85, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1050 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1051 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1054 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1055 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1061 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1062 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN | CNTR_ODD },
CNTR_ODD         1079 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
CNTR_ODD         1082 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x04, CNTR_ODD },
CNTR_ODD         1095 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
CNTR_ODD         1098 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x09, CNTR_ODD },
CNTR_ODD         1103 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
CNTR_ODD         1106 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x0c, CNTR_ODD },
CNTR_ODD         1113 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
CNTR_ODD         1117 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]        = { 0x02, CNTR_ODD },
CNTR_ODD         1136 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
CNTR_ODD         1140 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
CNTR_ODD         1146 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
CNTR_ODD         1150 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
CNTR_ODD         1163 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
CNTR_ODD         1167 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 28, CNTR_ODD, P },
CNTR_ODD         1173 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
CNTR_ODD         1176 arch/mips/kernel/perf_event_mipsxx.c 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
CNTR_ODD         1521 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1524 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1535 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1538 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1551 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1554 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1561 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1564 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1575 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1578 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1587 arch/mips/kernel/perf_event_mipsxx.c 		raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1591 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1594 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1606 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1609 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1621 arch/mips/kernel/perf_event_mipsxx.c 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
CNTR_ODD         1624 arch/mips/kernel/perf_event_mipsxx.c 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
CNTR_ODD         1627 arch/mips/kernel/perf_event_mipsxx.c 		raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;