mcde 65 drivers/gpu/drm/mcde/mcde_display.c void mcde_display_irq(struct mcde *mcde) mcde 71 drivers/gpu/drm/mcde/mcde_display.c mispp = readl(mcde->regs + MCDE_MISPP); mcde 72 drivers/gpu/drm/mcde/mcde_display.c misovl = readl(mcde->regs + MCDE_MISOVL); mcde 73 drivers/gpu/drm/mcde/mcde_display.c mischnl = readl(mcde->regs + MCDE_MISCHNL); mcde 83 drivers/gpu/drm/mcde/mcde_display.c if (mcde_dsi_irq(mcde->mdsi)) { mcde 92 drivers/gpu/drm/mcde/mcde_display.c if (mcde->oneshot_mode) { mcde 93 drivers/gpu/drm/mcde/mcde_display.c spin_lock(&mcde->flow_lock); mcde 94 drivers/gpu/drm/mcde/mcde_display.c if (--mcde->flow_active == 0) { mcde 95 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "TE0 IRQ\n"); mcde 97 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + MCDE_CRA0); mcde 99 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_CRA0); mcde 101 drivers/gpu/drm/mcde/mcde_display.c spin_unlock(&mcde->flow_lock); mcde 107 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl A vblank IRQ\n"); mcde 111 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl B vblank IRQ\n"); mcde 115 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n"); mcde 117 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n"); mcde 119 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl C0 TE IRQ\n"); mcde 121 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "chnl C1 TE IRQ\n"); mcde 122 drivers/gpu/drm/mcde/mcde_display.c writel(mispp, mcde->regs + MCDE_RISPP); mcde 125 drivers/gpu/drm/mcde/mcde_display.c drm_crtc_handle_vblank(&mcde->pipe.crtc); mcde 128 drivers/gpu/drm/mcde/mcde_display.c dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl); mcde 129 drivers/gpu/drm/mcde/mcde_display.c writel(misovl, mcde->regs + MCDE_RISOVL); mcde 132 drivers/gpu/drm/mcde/mcde_display.c dev_info(mcde->dev, "some stray channel error IRQ %08x\n", mcde 134 drivers/gpu/drm/mcde/mcde_display.c writel(mischnl, mcde->regs + MCDE_RISCHNL); mcde 137 drivers/gpu/drm/mcde/mcde_display.c void mcde_display_disable_irqs(struct mcde *mcde) mcde 140 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + MCDE_IMSCPP); mcde 141 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + MCDE_IMSCOVL); mcde 142 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + MCDE_IMSCCHNL); mcde 145 drivers/gpu/drm/mcde/mcde_display.c writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); mcde 146 drivers/gpu/drm/mcde/mcde_display.c writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL); mcde 147 drivers/gpu/drm/mcde/mcde_display.c writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL); mcde 187 drivers/gpu/drm/mcde/mcde_display.c static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src, mcde 318 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", mcde 322 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf); mcde 327 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); mcde 332 drivers/gpu/drm/mcde/mcde_display.c static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, mcde 401 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf1); mcde 425 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", mcde 431 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf2); mcde 434 drivers/gpu/drm/mcde/mcde_display.c writel(mcde->stride, mcde->regs + ljinc); mcde 436 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + crop); mcde 448 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); mcde 455 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + comp); mcde 458 drivers/gpu/drm/mcde/mcde_display.c static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch, mcde 501 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) { mcde 519 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + sync); mcde 524 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf); mcde 532 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + stat); mcde 533 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + bgcol); mcde 539 drivers/gpu/drm/mcde/mcde_display.c mcde->regs + mux); mcde 543 drivers/gpu/drm/mcde/mcde_display.c mcde->regs + mux); mcde 548 drivers/gpu/drm/mcde/mcde_display.c static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo, mcde 576 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + ctrl); mcde 581 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr0); mcde 589 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr1); mcde 592 drivers/gpu/drm/mcde/mcde_display.c static void mcde_configure_dsi_formatter(struct mcde *mcde, mcde 640 drivers/gpu/drm/mcde/mcde_display.c if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) mcde 642 drivers/gpu/drm/mcde/mcde_display.c switch (mcde->mdsi->format) { mcde 660 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "unknown DSI format\n"); mcde 663 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + conf0); mcde 665 drivers/gpu/drm/mcde/mcde_display.c writel(formatter_frame, mcde->regs + frame); mcde 666 drivers/gpu/drm/mcde/mcde_display.c writel(pkt_size, mcde->regs + pkt); mcde 667 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + sync); mcde 673 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cmdw); mcde 679 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + delay0); mcde 680 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + delay1); mcde 683 drivers/gpu/drm/mcde/mcde_display.c static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo) mcde 696 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "cannot enable FIFO %c\n", mcde 701 drivers/gpu/drm/mcde/mcde_display.c spin_lock(&mcde->flow_lock); mcde 702 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + cr); mcde 704 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); mcde 705 drivers/gpu/drm/mcde/mcde_display.c mcde->flow_active++; mcde 706 drivers/gpu/drm/mcde/mcde_display.c spin_unlock(&mcde->flow_lock); mcde 709 drivers/gpu/drm/mcde/mcde_display.c static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo, mcde 724 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "cannot disable FIFO %c\n", mcde 729 drivers/gpu/drm/mcde/mcde_display.c spin_lock(&mcde->flow_lock); mcde 730 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + cr); mcde 732 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + cr); mcde 733 drivers/gpu/drm/mcde/mcde_display.c mcde->flow_active = 0; mcde 734 drivers/gpu/drm/mcde/mcde_display.c spin_unlock(&mcde->flow_lock); mcde 740 drivers/gpu/drm/mcde/mcde_display.c while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) { mcde 743 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, mcde 754 drivers/gpu/drm/mcde/mcde_display.c static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo, mcde 785 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + ctrl); mcde 787 drivers/gpu/drm/mcde/mcde_display.c dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n"); mcde 789 drivers/gpu/drm/mcde/mcde_display.c mcde_enable_fifo(mcde, fifo); mcde 791 drivers/gpu/drm/mcde/mcde_display.c writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw); mcde 793 drivers/gpu/drm/mcde/mcde_display.c mcde_disable_fifo(mcde, fifo, true); mcde 819 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 836 drivers/gpu/drm/mcde/mcde_display.c if (!mcde->mdsi) { mcde 843 drivers/gpu/drm/mcde/mcde_display.c (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? mcde 845 drivers/gpu/drm/mcde/mcde_display.c mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format)); mcde 847 drivers/gpu/drm/mcde/mcde_display.c mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8; mcde 864 drivers/gpu/drm/mcde/mcde_display.c if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { mcde 879 drivers/gpu/drm/mcde/mcde_display.c if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)) mcde 886 drivers/gpu/drm/mcde/mcde_display.c mcde->stride = mode->hdisplay * cpp; mcde 888 drivers/gpu/drm/mcde/mcde_display.c mcde->stride); mcde 894 drivers/gpu/drm/mcde/mcde_display.c mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0); mcde 903 drivers/gpu/drm/mcde/mcde_display.c mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format); mcde 910 drivers/gpu/drm/mcde/mcde_display.c mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0, mcde 917 drivers/gpu/drm/mcde/mcde_display.c mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode); mcde 920 drivers/gpu/drm/mcde/mcde_display.c mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0, mcde 924 drivers/gpu/drm/mcde/mcde_display.c mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0, mcde 927 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) { mcde 932 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_VSCRC0); mcde 934 drivers/gpu/drm/mcde/mcde_display.c val = readl(mcde->regs + MCDE_CRC); mcde 936 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_CRC); mcde 948 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 950 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) mcde 954 drivers/gpu/drm/mcde/mcde_display.c mcde_disable_fifo(mcde, MCDE_FIFO_A, true); mcde 959 drivers/gpu/drm/mcde/mcde_display.c static void mcde_display_send_one_frame(struct mcde *mcde) mcde 962 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) mcde 963 drivers/gpu/drm/mcde/mcde_display.c mcde_dsi_te_request(mcde->mdsi); mcde 966 drivers/gpu/drm/mcde/mcde_display.c mcde_enable_fifo(mcde, MCDE_FIFO_A); mcde 968 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) { mcde 975 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "sent TE0 framebuffer update\n"); mcde 981 drivers/gpu/drm/mcde/mcde_display.c mcde->regs + MCDE_CHNL0SYNCHSW); mcde 990 drivers/gpu/drm/mcde/mcde_display.c mcde_disable_fifo(mcde, MCDE_FIFO_A, true); mcde 992 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "sent SW framebuffer update\n"); mcde 995 drivers/gpu/drm/mcde/mcde_display.c static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address) mcde 998 drivers/gpu/drm/mcde/mcde_display.c writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0); mcde 1003 drivers/gpu/drm/mcde/mcde_display.c writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1); mcde 1011 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 1034 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "arm vblank event\n"); mcde 1037 drivers/gpu/drm/mcde/mcde_display.c dev_dbg(mcde->dev, "insert fake vblank event\n"); mcde 1050 drivers/gpu/drm/mcde/mcde_display.c mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0)); mcde 1052 drivers/gpu/drm/mcde/mcde_display.c mcde_display_send_one_frame(mcde); mcde 1053 drivers/gpu/drm/mcde/mcde_display.c dev_info_once(mcde->dev, "sent first display update\n"); mcde 1060 drivers/gpu/drm/mcde/mcde_display.c dev_info(mcde->dev, "ignored a display update\n"); mcde 1068 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 1078 drivers/gpu/drm/mcde/mcde_display.c writel(val, mcde->regs + MCDE_IMSCPP); mcde 1087 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 1090 drivers/gpu/drm/mcde/mcde_display.c writel(0, mcde->regs + MCDE_IMSCPP); mcde 1092 drivers/gpu/drm/mcde/mcde_display.c writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); mcde 1105 drivers/gpu/drm/mcde/mcde_display.c struct mcde *mcde = drm->dev_private; mcde 1127 drivers/gpu/drm/mcde/mcde_display.c if (mcde->te_sync) { mcde 1132 drivers/gpu/drm/mcde/mcde_display.c ret = drm_simple_display_pipe_init(drm, &mcde->pipe, mcde 1136 drivers/gpu/drm/mcde/mcde_display.c mcde->connector); mcde 40 drivers/gpu/drm/mcde/mcde_drm.h void mcde_display_irq(struct mcde *mcde); mcde 41 drivers/gpu/drm/mcde/mcde_drm.h void mcde_display_disable_irqs(struct mcde *mcde); mcde 148 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = data; mcde 151 drivers/gpu/drm/mcde/mcde_drv.c val = readl(mcde->regs + MCDE_MISERR); mcde 153 drivers/gpu/drm/mcde/mcde_drv.c mcde_display_irq(mcde); mcde 156 drivers/gpu/drm/mcde/mcde_drv.c dev_info(mcde->dev, "some error IRQ\n"); mcde 157 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_RISERR); mcde 165 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; mcde 168 drivers/gpu/drm/mcde/mcde_drv.c if (!mcde->bridge) { mcde 188 drivers/gpu/drm/mcde/mcde_drv.c if (mcde->te_sync) { mcde 209 drivers/gpu/drm/mcde/mcde_drv.c ret = drm_simple_display_pipe_attach_bridge(&mcde->pipe, mcde 210 drivers/gpu/drm/mcde/mcde_drv.c mcde->bridge); mcde 229 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; mcde 233 drivers/gpu/drm/mcde/mcde_drv.c kfree(mcde); mcde 319 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde; mcde 328 drivers/gpu/drm/mcde/mcde_drv.c mcde = kzalloc(sizeof(*mcde), GFP_KERNEL); mcde 329 drivers/gpu/drm/mcde/mcde_drv.c if (!mcde) mcde 331 drivers/gpu/drm/mcde/mcde_drv.c mcde->dev = dev; mcde 333 drivers/gpu/drm/mcde/mcde_drv.c ret = drm_dev_init(&mcde->drm, &mcde_drm_driver, dev); mcde 335 drivers/gpu/drm/mcde/mcde_drv.c kfree(mcde); mcde 338 drivers/gpu/drm/mcde/mcde_drv.c drm = &mcde->drm; mcde 339 drivers/gpu/drm/mcde/mcde_drv.c drm->dev_private = mcde; mcde 343 drivers/gpu/drm/mcde/mcde_drv.c mcde->te_sync = true; mcde 345 drivers/gpu/drm/mcde/mcde_drv.c mcde->oneshot_mode = false; mcde 346 drivers/gpu/drm/mcde/mcde_drv.c drm->dev_private = mcde; mcde 349 drivers/gpu/drm/mcde/mcde_drv.c mcde->epod = devm_regulator_get(dev, "epod"); mcde 350 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->epod)) { mcde 351 drivers/gpu/drm/mcde/mcde_drv.c ret = PTR_ERR(mcde->epod); mcde 355 drivers/gpu/drm/mcde/mcde_drv.c ret = regulator_enable(mcde->epod); mcde 360 drivers/gpu/drm/mcde/mcde_drv.c mcde->vana = devm_regulator_get(dev, "vana"); mcde 361 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->vana)) { mcde 362 drivers/gpu/drm/mcde/mcde_drv.c ret = PTR_ERR(mcde->vana); mcde 366 drivers/gpu/drm/mcde/mcde_drv.c ret = regulator_enable(mcde->vana); mcde 377 drivers/gpu/drm/mcde/mcde_drv.c mcde->mcde_clk = devm_clk_get(dev, "mcde"); mcde 378 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->mcde_clk)) { mcde 380 drivers/gpu/drm/mcde/mcde_drv.c ret = PTR_ERR(mcde->mcde_clk); mcde 383 drivers/gpu/drm/mcde/mcde_drv.c ret = clk_prepare_enable(mcde->mcde_clk); mcde 388 drivers/gpu/drm/mcde/mcde_drv.c dev_info(dev, "MCDE clk rate %lu Hz\n", clk_get_rate(mcde->mcde_clk)); mcde 390 drivers/gpu/drm/mcde/mcde_drv.c mcde->lcd_clk = devm_clk_get(dev, "lcd"); mcde 391 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->lcd_clk)) { mcde 393 drivers/gpu/drm/mcde/mcde_drv.c ret = PTR_ERR(mcde->lcd_clk); mcde 396 drivers/gpu/drm/mcde/mcde_drv.c mcde->hdmi_clk = devm_clk_get(dev, "hdmi"); mcde 397 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->hdmi_clk)) { mcde 399 drivers/gpu/drm/mcde/mcde_drv.c ret = PTR_ERR(mcde->hdmi_clk); mcde 404 drivers/gpu/drm/mcde/mcde_drv.c mcde->regs = devm_ioremap_resource(dev, res); mcde 405 drivers/gpu/drm/mcde/mcde_drv.c if (IS_ERR(mcde->regs)) { mcde 417 drivers/gpu/drm/mcde/mcde_drv.c ret = devm_request_irq(dev, irq, mcde_irq, 0, "mcde", mcde); mcde 429 drivers/gpu/drm/mcde/mcde_drv.c pid = readl(mcde->regs + MCDE_PID); mcde 458 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_CONF0); mcde 461 drivers/gpu/drm/mcde/mcde_drv.c val = readl(mcde->regs + MCDE_CR); mcde 463 drivers/gpu/drm/mcde/mcde_drv.c writel(val, mcde->regs + MCDE_CR); mcde 466 drivers/gpu/drm/mcde/mcde_drv.c mcde_display_disable_irqs(mcde); mcde 467 drivers/gpu/drm/mcde/mcde_drv.c writel(0, mcde->regs + MCDE_IMSCERR); mcde 468 drivers/gpu/drm/mcde/mcde_drv.c writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR); mcde 504 drivers/gpu/drm/mcde/mcde_drv.c clk_disable_unprepare(mcde->mcde_clk); mcde 506 drivers/gpu/drm/mcde/mcde_drv.c regulator_disable(mcde->vana); mcde 508 drivers/gpu/drm/mcde/mcde_drv.c regulator_disable(mcde->epod); mcde 518 drivers/gpu/drm/mcde/mcde_drv.c struct mcde *mcde = drm->dev_private; mcde 521 drivers/gpu/drm/mcde/mcde_drv.c clk_disable_unprepare(mcde->mcde_clk); mcde 522 drivers/gpu/drm/mcde/mcde_drv.c regulator_disable(mcde->vana); mcde 523 drivers/gpu/drm/mcde/mcde_drv.c regulator_disable(mcde->epod); mcde 40 drivers/gpu/drm/mcde/mcde_dsi.c struct mcde *mcde; mcde 150 drivers/gpu/drm/mcde/mcde_dsi.c if (d->mcde) mcde 151 drivers/gpu/drm/mcde/mcde_dsi.c d->mcde->mdsi = mdsi; mcde 162 drivers/gpu/drm/mcde/mcde_dsi.c if (d->mcde) mcde 163 drivers/gpu/drm/mcde/mcde_dsi.c d->mcde->mdsi = NULL; mcde 890 drivers/gpu/drm/mcde/mcde_dsi.c struct mcde *mcde = drm->dev_private; mcde 901 drivers/gpu/drm/mcde/mcde_dsi.c d->mcde = mcde; mcde 904 drivers/gpu/drm/mcde/mcde_dsi.c d->mcde->mdsi = d->mdsi; mcde 976 drivers/gpu/drm/mcde/mcde_dsi.c mcde->bridge = &d->bridge;