CNTR_ID_WDOG       47 drivers/watchdog/armada_37xx_wdt.c #define WDT_TIMER_SELECT_VAL		BIT(CNTR_ID_WDOG)
CNTR_ID_WDOG      161 drivers/watchdog/armada_37xx_wdt.c 	res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
CNTR_ID_WDOG      193 drivers/watchdog/armada_37xx_wdt.c 	reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
CNTR_ID_WDOG      209 drivers/watchdog/armada_37xx_wdt.c 	init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
CNTR_ID_WDOG      211 drivers/watchdog/armada_37xx_wdt.c 	set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
CNTR_ID_WDOG      214 drivers/watchdog/armada_37xx_wdt.c 	counter_enable(dev, CNTR_ID_WDOG);
CNTR_ID_WDOG      226 drivers/watchdog/armada_37xx_wdt.c 	counter_disable(dev, CNTR_ID_WDOG);