CNTR_EVEN 812 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, CNTR_EVEN 813 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 814 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, CNTR_EVEN 821 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, CNTR_EVEN 822 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 823 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, CNTR_EVEN 828 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 829 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 831 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 832 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 833 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 834 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 838 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN }, CNTR_EVEN 840 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN }, CNTR_EVEN 856 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 857 arch/mips/kernel/perf_event_mipsxx.c [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 883 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, CNTR_EVEN 884 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 887 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, CNTR_EVEN 888 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, CNTR_EVEN 893 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, CNTR_EVEN 897 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, CNTR_EVEN 901 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, CNTR_EVEN 911 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, CNTR_EVEN 915 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, CNTR_EVEN 920 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, CNTR_EVEN 924 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, CNTR_EVEN 930 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, CNTR_EVEN 934 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, CNTR_EVEN 941 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, CNTR_EVEN 945 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, CNTR_EVEN 974 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, CNTR_EVEN 978 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, CNTR_EVEN 982 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, CNTR_EVEN 992 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, CNTR_EVEN 996 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, CNTR_EVEN 1006 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, CNTR_EVEN 1010 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, CNTR_EVEN 1017 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, CNTR_EVEN 1021 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, CNTR_EVEN 1033 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1034 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1037 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1038 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1043 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1044 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1050 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1051 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1054 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1055 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1061 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1062 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD }, CNTR_EVEN 1087 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, CNTR_EVEN 1090 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_MISS)] = { 0x04, CNTR_EVEN }, CNTR_EVEN 1112 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN }, CNTR_EVEN 1116 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN }, CNTR_EVEN 1135 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, CNTR_EVEN 1139 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, CNTR_EVEN 1145 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, CNTR_EVEN 1149 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, CNTR_EVEN 1153 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T }, CNTR_EVEN 1162 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, CNTR_EVEN 1166 arch/mips/kernel/perf_event_mipsxx.c [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, CNTR_EVEN 1521 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1524 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1535 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1538 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1551 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1554 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1561 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1564 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1575 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1578 arch/mips/kernel/perf_event_mipsxx.c raw_id > 255 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1587 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1591 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1594 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1606 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1609 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1621 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; CNTR_EVEN 1624 arch/mips/kernel/perf_event_mipsxx.c raw_id > 127 ? CNTR_ODD : CNTR_EVEN; CNTR_EVEN 1627 arch/mips/kernel/perf_event_mipsxx.c raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;