maximum_number_of_surfaces 382 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h for (i = 0; i < maximum_number_of_surfaces; i++) { maximum_number_of_surfaces 536 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h for (i = 0; i < maximum_number_of_surfaces; i++) { maximum_number_of_surfaces 109 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c enum bw_defines v_filter_init_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 110 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c enum bw_defines tiling_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 111 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c enum bw_defines surface_type[maximum_number_of_surfaces]; maximum_number_of_surfaces 291 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 4; i <= maximum_number_of_surfaces - 3; i++) { maximum_number_of_surfaces 349 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 2] = 0; maximum_number_of_surfaces 350 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_enable_for_pipe[maximum_number_of_surfaces - 1] = 0; maximum_number_of_surfaces 352 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->enable[maximum_number_of_surfaces - 2] = 1; maximum_number_of_surfaces 353 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->enable[maximum_number_of_surfaces - 1] = 1; maximum_number_of_surfaces 356 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->enable[maximum_number_of_surfaces - 2] = 0; maximum_number_of_surfaces 357 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->enable[maximum_number_of_surfaces - 1] = 0; maximum_number_of_surfaces 359 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c surface_type[maximum_number_of_surfaces - 2] = bw_def_display_write_back420_luma; maximum_number_of_surfaces 360 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c surface_type[maximum_number_of_surfaces - 1] = bw_def_display_write_back420_chroma; maximum_number_of_surfaces 361 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->lb_size_per_component[maximum_number_of_surfaces - 2] = dceip->underlay420_luma_lb_size_per_component; maximum_number_of_surfaces 362 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->lb_size_per_component[maximum_number_of_surfaces - 1] = dceip->underlay420_chroma_lb_size_per_component; maximum_number_of_surfaces 363 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->bytes_per_pixel[maximum_number_of_surfaces - 2] = 1; maximum_number_of_surfaces 364 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->bytes_per_pixel[maximum_number_of_surfaces - 1] = 2; maximum_number_of_surfaces 365 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->interlace_mode[maximum_number_of_surfaces - 2] = data->interlace_mode[5]; maximum_number_of_surfaces 366 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->interlace_mode[maximum_number_of_surfaces - 1] = data->interlace_mode[5]; maximum_number_of_surfaces 367 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); maximum_number_of_surfaces 368 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); maximum_number_of_surfaces 369 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); maximum_number_of_surfaces 370 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); maximum_number_of_surfaces 371 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->rotation_angle[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0); maximum_number_of_surfaces 372 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->rotation_angle[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0); maximum_number_of_surfaces 373 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[maximum_number_of_surfaces - 2] = bw_def_linear; maximum_number_of_surfaces 374 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c tiling_mode[maximum_number_of_surfaces - 1] = bw_def_linear; maximum_number_of_surfaces 375 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->lb_bpc[maximum_number_of_surfaces - 2] = 8; maximum_number_of_surfaces 376 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->lb_bpc[maximum_number_of_surfaces - 1] = 8; maximum_number_of_surfaces 377 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->compression_rate[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); maximum_number_of_surfaces 378 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->compression_rate[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); maximum_number_of_surfaces 379 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->access_one_channel_only[maximum_number_of_surfaces - 2] = 0; maximum_number_of_surfaces 380 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->access_one_channel_only[maximum_number_of_surfaces - 1] = 0; maximum_number_of_surfaces 382 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_total[maximum_number_of_surfaces - 2] = data->h_total[5]; maximum_number_of_surfaces 383 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_total[maximum_number_of_surfaces - 1] = data->h_total[5]; maximum_number_of_surfaces 384 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5]; maximum_number_of_surfaces 385 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5]; maximum_number_of_surfaces 386 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pixel_rate[maximum_number_of_surfaces - 2] = data->pixel_rate[5]; maximum_number_of_surfaces 387 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pixel_rate[maximum_number_of_surfaces - 1] = data->pixel_rate[5]; maximum_number_of_surfaces 388 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[maximum_number_of_surfaces - 2] = data->src_width[5]; maximum_number_of_surfaces 389 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[maximum_number_of_surfaces - 1] = data->src_width[5]; maximum_number_of_surfaces 390 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[maximum_number_of_surfaces - 2] = data->src_height[5]; maximum_number_of_surfaces 391 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[maximum_number_of_surfaces - 1] = data->src_height[5]; maximum_number_of_surfaces 392 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pitch_in_pixels[maximum_number_of_surfaces - 2] = data->src_width[5]; maximum_number_of_surfaces 393 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pitch_in_pixels[maximum_number_of_surfaces - 1] = data->src_width[5]; maximum_number_of_surfaces 394 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); maximum_number_of_surfaces 395 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); maximum_number_of_surfaces 396 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); maximum_number_of_surfaces 397 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); maximum_number_of_surfaces 398 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->stereo_mode[maximum_number_of_surfaces - 2] = bw_def_mono; maximum_number_of_surfaces 399 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->stereo_mode[maximum_number_of_surfaces - 1] = bw_def_mono; maximum_number_of_surfaces 400 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->cursor_width_pixels[maximum_number_of_surfaces - 2] = bw_int_to_fixed(0); maximum_number_of_surfaces 401 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->cursor_width_pixels[maximum_number_of_surfaces - 1] = bw_int_to_fixed(0); maximum_number_of_surfaces 402 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->use_alpha[maximum_number_of_surfaces - 2] = 0; maximum_number_of_surfaces 403 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->use_alpha[maximum_number_of_surfaces - 1] = 0; maximum_number_of_surfaces 418 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 504 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 524 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 539 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 573 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 579 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 631 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 788 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 863 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 876 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 932 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 947 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 952 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 962 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 992 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1078 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1096 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1117 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1123 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1136 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1167 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1194 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1279 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1285 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1300 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1319 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1365 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1383 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1418 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1427 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1439 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1442 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (j = 0; j <= maximum_number_of_surfaces - 1; j++) { maximum_number_of_surfaces 1451 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1475 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1483 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1497 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1657 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1707 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1719 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1792 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 1814 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1831 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1848 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1855 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1890 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1927 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1937 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1965 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 1989 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (i = 0; i <= maximum_number_of_surfaces - 1; i++) { maximum_number_of_surfaces 2006 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { maximum_number_of_surfaces 363 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool fbc_en[maximum_number_of_surfaces]; maximum_number_of_surfaces 364 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool lpt_en[maximum_number_of_surfaces]; maximum_number_of_surfaces 365 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool displays_match_flag[maximum_number_of_surfaces]; maximum_number_of_surfaces 366 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool use_alpha[maximum_number_of_surfaces]; maximum_number_of_surfaces 367 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool orthogonal_rotation[maximum_number_of_surfaces]; maximum_number_of_surfaces 368 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool enable[maximum_number_of_surfaces]; maximum_number_of_surfaces 369 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool access_one_channel_only[maximum_number_of_surfaces]; maximum_number_of_surfaces 370 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; maximum_number_of_surfaces 371 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool interlace_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 372 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool display_pstate_change_enable[maximum_number_of_surfaces]; maximum_number_of_surfaces 373 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h bool line_buffer_prefetch[maximum_number_of_surfaces]; maximum_number_of_surfaces 374 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t bytes_per_pixel[maximum_number_of_surfaces]; maximum_number_of_surfaces 375 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 376 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t lb_bpc[maximum_number_of_surfaces]; maximum_number_of_surfaces 377 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bpphdmi[maximum_number_of_surfaces]; maximum_number_of_surfaces 378 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; maximum_number_of_surfaces 379 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; maximum_number_of_surfaces 380 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; maximum_number_of_surfaces 381 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h enum bw_defines stereo_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 382 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; maximum_number_of_surfaces 383 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; maximum_number_of_surfaces 384 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; maximum_number_of_surfaces 385 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; maximum_number_of_surfaces 386 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; maximum_number_of_surfaces 387 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; maximum_number_of_surfaces 388 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed h_total[maximum_number_of_surfaces]; maximum_number_of_surfaces 389 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed v_total[maximum_number_of_surfaces]; maximum_number_of_surfaces 390 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pixel_rate[maximum_number_of_surfaces]; maximum_number_of_surfaces 391 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_width[maximum_number_of_surfaces]; maximum_number_of_surfaces 392 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; maximum_number_of_surfaces 393 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; maximum_number_of_surfaces 394 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_height[maximum_number_of_surfaces]; maximum_number_of_surfaces 395 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scale_ratio[maximum_number_of_surfaces]; maximum_number_of_surfaces 396 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed h_taps[maximum_number_of_surfaces]; maximum_number_of_surfaces 397 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed v_taps[maximum_number_of_surfaces]; maximum_number_of_surfaces 398 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; maximum_number_of_surfaces 399 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; maximum_number_of_surfaces 400 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed rotation_angle[maximum_number_of_surfaces]; maximum_number_of_surfaces 401 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed compression_rate[maximum_number_of_surfaces]; maximum_number_of_surfaces 402 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed hsr[maximum_number_of_surfaces]; maximum_number_of_surfaces 403 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed vsr[maximum_number_of_surfaces]; maximum_number_of_surfaces 404 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; maximum_number_of_surfaces 405 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; maximum_number_of_surfaces 406 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; maximum_number_of_surfaces 407 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; maximum_number_of_surfaces 408 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; maximum_number_of_surfaces 409 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; maximum_number_of_surfaces 410 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; maximum_number_of_surfaces 411 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; maximum_number_of_surfaces 412 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; maximum_number_of_surfaces 413 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lb_partitions[maximum_number_of_surfaces]; maximum_number_of_surfaces 414 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; maximum_number_of_surfaces 415 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; maximum_number_of_surfaces 416 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; maximum_number_of_surfaces 417 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; maximum_number_of_surfaces 418 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; maximum_number_of_surfaces 419 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; maximum_number_of_surfaces 420 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; maximum_number_of_surfaces 421 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed v_filter_init[maximum_number_of_surfaces]; maximum_number_of_surfaces 422 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; maximum_number_of_surfaces 423 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; maximum_number_of_surfaces 424 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; maximum_number_of_surfaces 425 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; maximum_number_of_surfaces 426 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; maximum_number_of_surfaces 427 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; maximum_number_of_surfaces 428 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; maximum_number_of_surfaces 429 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; maximum_number_of_surfaces 430 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; maximum_number_of_surfaces 431 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; maximum_number_of_surfaces 432 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; maximum_number_of_surfaces 433 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; maximum_number_of_surfaces 434 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; maximum_number_of_surfaces 435 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; maximum_number_of_surfaces 436 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; maximum_number_of_surfaces 437 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; maximum_number_of_surfaces 438 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; maximum_number_of_surfaces 439 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; maximum_number_of_surfaces 440 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; maximum_number_of_surfaces 441 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; maximum_number_of_surfaces 442 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; maximum_number_of_surfaces 443 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; maximum_number_of_surfaces 444 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; maximum_number_of_surfaces 445 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; maximum_number_of_surfaces 446 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; maximum_number_of_surfaces 447 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; maximum_number_of_surfaces 448 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed active_time[maximum_number_of_surfaces]; maximum_number_of_surfaces 449 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; maximum_number_of_surfaces 450 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; maximum_number_of_surfaces 451 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; maximum_number_of_surfaces 455 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; maximum_number_of_surfaces 456 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8];