max_lane_count    927 drivers/gpu/drm/amd/display/dc/dc.h 	union max_lane_count max_ln_count;
max_lane_count    791 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
max_lane_count   1612 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		video_info->max_lane_count = 0x04;
max_lane_count   1622 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 				     &video_info->max_lane_count);
max_lane_count    143 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h 	enum link_lane_count_type max_lane_count;
max_lane_count     54 drivers/gpu/drm/bridge/parade-ps8622.c 	u32 max_lane_count;
max_lane_count    186 drivers/gpu/drm/bridge/parade-ps8622.c 	err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count);
max_lane_count    565 drivers/gpu/drm/bridge/parade-ps8622.c 	ps8622->max_lane_count = id->driver_data;
max_lane_count    569 drivers/gpu/drm/bridge/parade-ps8622.c 		ps8622->lane_count = ps8622->max_lane_count;
max_lane_count    570 drivers/gpu/drm/bridge/parade-ps8622.c 	} else if (ps8622->lane_count > ps8622->max_lane_count) {
max_lane_count    573 drivers/gpu/drm/bridge/parade-ps8622.c 		ps8622->lane_count = ps8622->max_lane_count;
max_lane_count    327 drivers/gpu/drm/gma500/cdv_intel_dp.c 	int max_lane_count = 4;
max_lane_count    330 drivers/gpu/drm/gma500/cdv_intel_dp.c 		max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
max_lane_count    331 drivers/gpu/drm/gma500/cdv_intel_dp.c 		switch (max_lane_count) {
max_lane_count    335 drivers/gpu/drm/gma500/cdv_intel_dp.c 			max_lane_count = 4;
max_lane_count    338 drivers/gpu/drm/gma500/cdv_intel_dp.c 	return max_lane_count;
max_lane_count    902 drivers/gpu/drm/gma500/cdv_intel_dp.c 	int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
max_lane_count    914 drivers/gpu/drm/gma500/cdv_intel_dp.c 	for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
max_lane_count    932 drivers/gpu/drm/gma500/cdv_intel_dp.c 		intel_dp->lane_count = max_lane_count;
max_lane_count   1923 drivers/gpu/drm/i915/display/intel_dp.c 			limits->min_lane_count = limits->max_lane_count =
max_lane_count   1960 drivers/gpu/drm/i915/display/intel_dp.c 			     lane_count <= limits->max_lane_count;
max_lane_count   2029 drivers/gpu/drm/i915/display/intel_dp.c 	pipe_config->lane_count = limits->max_lane_count;
max_lane_count   2122 drivers/gpu/drm/i915/display/intel_dp.c 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
max_lane_count   2135 drivers/gpu/drm/i915/display/intel_dp.c 		limits.min_lane_count = limits.max_lane_count;
max_lane_count   2143 drivers/gpu/drm/i915/display/intel_dp.c 		      limits.max_lane_count,
max_lane_count     28 drivers/gpu/drm/i915/display/intel_dp.h 	int min_lane_count, max_lane_count;
max_lane_count     57 drivers/gpu/drm/i915/display/intel_dp_mst.c 	crtc_state->lane_count = limits->max_lane_count;
max_lane_count    128 drivers/gpu/drm/i915/display/intel_dp_mst.c 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);