CNL_PORT_CL1CM_DW5  144 drivers/gpu/drm/i915/display/intel_combo_phy.c 	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
CNL_PORT_CL1CM_DW5  165 drivers/gpu/drm/i915/display/intel_combo_phy.c 	val = I915_READ(CNL_PORT_CL1CM_DW5);
CNL_PORT_CL1CM_DW5  167 drivers/gpu/drm/i915/display/intel_combo_phy.c 	I915_WRITE(CNL_PORT_CL1CM_DW5, val);
CNL_PORT_CL1CM_DW5 2441 drivers/gpu/drm/i915/display/intel_ddi.c 	val = I915_READ(CNL_PORT_CL1CM_DW5);
CNL_PORT_CL1CM_DW5 2443 drivers/gpu/drm/i915/display/intel_ddi.c 	I915_WRITE(CNL_PORT_CL1CM_DW5, val);