mask 19 Documentation/usb/usbdevfs-drop-permissions.c void drop_privileges(int fd, uint32_t mask) mask 23 Documentation/usb/usbdevfs-drop-permissions.c res = ioctl(fd, USBDEVFS_DROP_PRIVILEGES, &mask); mask 58 Documentation/usb/usbdevfs-drop-permissions.c uint32_t mask, caps; mask 102 Documentation/usb/usbdevfs-drop-permissions.c scanf("%x", &mask); mask 103 Documentation/usb/usbdevfs-drop-permissions.c drop_privileges(fd, mask); mask 192 arch/alpha/include/asm/bitops.h unsigned long mask = 1 << (nr & 0x1f); mask 196 arch/alpha/include/asm/bitops.h *m = old | mask; mask 197 arch/alpha/include/asm/bitops.h return (old & mask) != 0; mask 236 arch/alpha/include/asm/bitops.h unsigned long mask = 1 << (nr & 0x1f); mask 240 arch/alpha/include/asm/bitops.h *m = old & ~mask; mask 241 arch/alpha/include/asm/bitops.h return (old & mask) != 0; mask 278 arch/alpha/include/asm/bitops.h unsigned long mask = 1 << (nr & 0x1f); mask 282 arch/alpha/include/asm/bitops.h *m = old ^ mask; mask 283 arch/alpha/include/asm/bitops.h return (old & mask) != 0; mask 49 arch/alpha/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 37 arch/alpha/include/asm/special_insns.h #define amask(mask) \ mask 38 arch/alpha/include/asm/special_insns.h ({ unsigned long __amask, __input = (mask); \ mask 56 arch/alpha/include/asm/word-at-a-time.h #define zero_bytemask(mask) ((2ul << (find_zero(mask) * 8)) - 1) mask 280 arch/alpha/kernel/core_apecs.c long mask; mask 286 arch/alpha/kernel/core_apecs.c mask = (size - 1) * 8; mask 288 arch/alpha/kernel/core_apecs.c addr = (pci_addr << 5) + mask + APECS_CONF; mask 299 arch/alpha/kernel/core_apecs.c long mask; mask 304 arch/alpha/kernel/core_apecs.c mask = (size - 1) * 8; mask 305 arch/alpha/kernel/core_apecs.c addr = (pci_addr << 5) + mask + APECS_CONF; mask 213 arch/alpha/kernel/core_cia.c long mask; mask 220 arch/alpha/kernel/core_cia.c mask = (size - 1) * 8; mask 222 arch/alpha/kernel/core_cia.c addr = (pci_addr << 5) + mask + CIA_CONF; mask 232 arch/alpha/kernel/core_cia.c long mask; mask 238 arch/alpha/kernel/core_cia.c mask = (size - 1) * 8; mask 239 arch/alpha/kernel/core_cia.c addr = (pci_addr << 5) + mask + CIA_CONF; mask 1089 arch/alpha/kernel/core_cia.c unsigned long mask; mask 1096 arch/alpha/kernel/core_cia.c mask = (cia->cpu_err1 >> 12) & 0xF; mask 1101 arch/alpha/kernel/core_cia.c printk(KERN_CRIT " Address: %#010lx, Mask: %#lx\n", addr, mask); mask 206 arch/alpha/kernel/core_lca.c long mask; mask 213 arch/alpha/kernel/core_lca.c mask = (size - 1) * 8; mask 214 arch/alpha/kernel/core_lca.c addr = (pci_addr << 5) + mask + LCA_CONF; mask 224 arch/alpha/kernel/core_lca.c long mask; mask 229 arch/alpha/kernel/core_lca.c mask = (size - 1) * 8; mask 230 arch/alpha/kernel/core_lca.c addr = (pci_addr << 5) + mask + LCA_CONF; mask 290 arch/alpha/kernel/core_t2.c long mask; mask 295 arch/alpha/kernel/core_t2.c mask = (size - 1) * 8; mask 297 arch/alpha/kernel/core_t2.c addr = (pci_addr << 5) + mask + T2_CONF; mask 308 arch/alpha/kernel/core_t2.c long mask; mask 313 arch/alpha/kernel/core_t2.c mask = (size - 1) * 8; mask 314 arch/alpha/kernel/core_t2.c addr = (pci_addr << 5) + mask + T2_CONF; mask 28 arch/alpha/kernel/irq_i8259.c i8259_update_irq_hw(unsigned int irq, unsigned long mask) mask 31 arch/alpha/kernel/irq_i8259.c if (irq & 8) mask >>= 8; mask 33 arch/alpha/kernel/irq_i8259.c outb(mask, port); mask 25 arch/alpha/kernel/irq_pyxis.c pyxis_update_irq_hw(unsigned long mask) mask 27 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK = mask; mask 48 arch/alpha/kernel/irq_pyxis.c unsigned long mask = cached_irq_mask &= ~bit; mask 51 arch/alpha/kernel/irq_pyxis.c *(vulp)PYXIS_INT_MASK = mask; mask 135 arch/alpha/kernel/pci_iommu.c long n, long mask) mask 154 arch/alpha/kernel/pci_iommu.c p = ALIGN(arena->next_entry, mask + 1); mask 160 arch/alpha/kernel/pci_iommu.c p = ALIGN(p + 1, mask + 1); mask 165 arch/alpha/kernel/pci_iommu.c p = ALIGN(p + i + 1, mask + 1), i = 0; mask 197 arch/alpha/kernel/pci_iommu.c long i, p, mask; mask 203 arch/alpha/kernel/pci_iommu.c mask = max(align, arena->align_entry) - 1; mask 204 arch/alpha/kernel/pci_iommu.c p = iommu_arena_find_pages(dev, arena, n, mask); mask 238 arch/alpha/kernel/pci_iommu.c static int pci_dac_dma_supported(struct pci_dev *dev, u64 mask) mask 822 arch/alpha/kernel/pci_iommu.c static int alpha_pci_supported(struct device *dev, u64 mask) mask 832 arch/alpha/kernel/pci_iommu.c && (__direct_map_base + __direct_map_size - 1 <= mask || mask 833 arch/alpha/kernel/pci_iommu.c __direct_map_base + (max_low_pfn << PAGE_SHIFT) - 1 <= mask)) mask 839 arch/alpha/kernel/pci_iommu.c if (arena && arena->dma_base + arena->size - 1 <= mask) mask 842 arch/alpha/kernel/pci_iommu.c if (arena && arena->dma_base + arena->size - 1 <= mask) mask 846 arch/alpha/kernel/pci_iommu.c if (!__direct_map_base && MAX_DMA_ADDRESS - IDENT_ADDR - 1 <= mask) mask 47 arch/alpha/kernel/signal.c sigset_t mask; mask 50 arch/alpha/kernel/signal.c siginitset(&mask, newmask & _BLOCKABLE); mask 51 arch/alpha/kernel/signal.c res = sigprocmask(how, &mask, &oldmask); mask 67 arch/alpha/kernel/signal.c old_sigset_t mask; mask 71 arch/alpha/kernel/signal.c __get_user(mask, &act->sa_mask)) mask 73 arch/alpha/kernel/signal.c siginitset(&new_ka.sa.sa_mask, mask); mask 272 arch/alpha/kernel/signal.c unsigned long mask, unsigned long sp) mask 278 arch/alpha/kernel/signal.c err |= __put_user(mask, &sc->sc_mask); mask 597 arch/alpha/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 599 arch/alpha/kernel/smp.c send_ipi_message(mask, IPI_CALL_FUNC); mask 40 arch/alpha/kernel/sys_alcor.c alcor_update_irq_hw(unsigned long mask) mask 42 arch/alpha/kernel/sys_alcor.c *(vuip)GRU_INT_MASK = mask; mask 42 arch/alpha/kernel/sys_cabriolet.c cabriolet_update_irq_hw(unsigned int irq, unsigned long mask) mask 45 arch/alpha/kernel/sys_cabriolet.c outb(mask >> (16 + ofs * 8), 0x804 + ofs); mask 48 arch/alpha/kernel/sys_dp264.c tsunami_update_irq_hw(unsigned long mask) mask 58 arch/alpha/kernel/sys_dp264.c mask &= ~isa_enable; mask 59 arch/alpha/kernel/sys_dp264.c mask0 = mask & cpu_irq_affinity[0]; mask 60 arch/alpha/kernel/sys_dp264.c mask1 = mask & cpu_irq_affinity[1]; mask 61 arch/alpha/kernel/sys_dp264.c mask2 = mask & cpu_irq_affinity[2]; mask 62 arch/alpha/kernel/sys_dp264.c mask3 = mask & cpu_irq_affinity[3]; mask 94 arch/alpha/kernel/sys_dp264.c *dimB = mask | isa_enable; mask 41 arch/alpha/kernel/sys_eb64p.c eb64p_update_irq_hw(unsigned int irq, unsigned long mask) mask 43 arch/alpha/kernel/sys_eb64p.c outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26)); mask 43 arch/alpha/kernel/sys_eiger.c eiger_update_irq_hw(unsigned long irq, unsigned long mask) mask 47 arch/alpha/kernel/sys_eiger.c mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); mask 49 arch/alpha/kernel/sys_eiger.c outl(mask & 0xffff0000UL, regaddr); mask 56 arch/alpha/kernel/sys_eiger.c unsigned long mask; mask 57 arch/alpha/kernel/sys_eiger.c mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); mask 58 arch/alpha/kernel/sys_eiger.c eiger_update_irq_hw(irq, mask); mask 65 arch/alpha/kernel/sys_eiger.c unsigned long mask; mask 66 arch/alpha/kernel/sys_eiger.c mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); mask 67 arch/alpha/kernel/sys_eiger.c eiger_update_irq_hw(irq, mask); mask 41 arch/alpha/kernel/sys_mikasa.c mikasa_update_irq_hw(int mask) mask 43 arch/alpha/kernel/sys_mikasa.c outw(mask, 0x536); mask 41 arch/alpha/kernel/sys_noritake.c noritake_update_irq_hw(int irq, int mask) mask 45 arch/alpha/kernel/sys_noritake.c mask >>= 16; mask 48 arch/alpha/kernel/sys_noritake.c outw(mask, port); mask 48 arch/alpha/kernel/sys_rawhide.c rawhide_update_irq_hw(int hose, int mask) mask 50 arch/alpha/kernel/sys_rawhide.c *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; mask 61 arch/alpha/kernel/sys_rawhide.c unsigned int mask, hose; mask 70 arch/alpha/kernel/sys_rawhide.c mask = 1 << irq; mask 73 arch/alpha/kernel/sys_rawhide.c mask |= cached_irq_masks[hose]; mask 74 arch/alpha/kernel/sys_rawhide.c cached_irq_masks[hose] = mask; mask 75 arch/alpha/kernel/sys_rawhide.c rawhide_update_irq_hw(hose, mask); mask 82 arch/alpha/kernel/sys_rawhide.c unsigned int mask, hose; mask 91 arch/alpha/kernel/sys_rawhide.c mask = ~(1 << irq) | hose_irq_masks[hose]; mask 94 arch/alpha/kernel/sys_rawhide.c mask &= cached_irq_masks[hose]; mask 95 arch/alpha/kernel/sys_rawhide.c cached_irq_masks[hose] = mask; mask 96 arch/alpha/kernel/sys_rawhide.c rawhide_update_irq_hw(hose, mask); mask 103 arch/alpha/kernel/sys_rawhide.c unsigned int mask, mask1, hose; mask 113 arch/alpha/kernel/sys_rawhide.c mask = ~mask1 | hose_irq_masks[hose]; mask 117 arch/alpha/kernel/sys_rawhide.c mask &= cached_irq_masks[hose]; mask 118 arch/alpha/kernel/sys_rawhide.c cached_irq_masks[hose] = mask; mask 119 arch/alpha/kernel/sys_rawhide.c rawhide_update_irq_hw(hose, mask); mask 175 arch/alpha/kernel/sys_rawhide.c unsigned int mask = hose_irq_masks[h]; mask 177 arch/alpha/kernel/sys_rawhide.c cached_irq_masks[h] = mask; mask 178 arch/alpha/kernel/sys_rawhide.c *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; mask 39 arch/alpha/kernel/sys_rx164.c rx164_update_irq_hw(unsigned long mask) mask 44 arch/alpha/kernel/sys_rx164.c *irq_mask = mask; mask 43 arch/alpha/kernel/sys_sable.c void (*update_irq_hw)(unsigned long bit, unsigned long mask); mask 94 arch/alpha/kernel/sys_sable.c sable_update_irq_hw(unsigned long bit, unsigned long mask) mask 100 arch/alpha/kernel/sys_sable.c mask >>= 16; mask 103 arch/alpha/kernel/sys_sable.c mask >>= 8; mask 106 arch/alpha/kernel/sys_sable.c outb(mask, port); mask 293 arch/alpha/kernel/sys_sable.c lynx_update_irq_hw(unsigned long bit, unsigned long mask) mask 303 arch/alpha/kernel/sys_sable.c *(vulp)T2_DIR = mask; mask 448 arch/alpha/kernel/sys_sable.c unsigned long bit, mask; mask 452 arch/alpha/kernel/sys_sable.c mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit); mask 453 arch/alpha/kernel/sys_sable.c sable_lynx_irq_swizzle->update_irq_hw(bit, mask); mask 457 arch/alpha/kernel/sys_sable.c __func__, mask, bit, irq); mask 464 arch/alpha/kernel/sys_sable.c unsigned long bit, mask; mask 468 arch/alpha/kernel/sys_sable.c mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; mask 469 arch/alpha/kernel/sys_sable.c sable_lynx_irq_swizzle->update_irq_hw(bit, mask); mask 473 arch/alpha/kernel/sys_sable.c __func__, mask, bit, irq); mask 480 arch/alpha/kernel/sys_sable.c unsigned long bit, mask; mask 484 arch/alpha/kernel/sys_sable.c mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; mask 485 arch/alpha/kernel/sys_sable.c sable_lynx_irq_swizzle->update_irq_hw(bit, mask); mask 38 arch/alpha/kernel/sys_takara.c takara_update_irq_hw(unsigned long irq, unsigned long mask) mask 42 arch/alpha/kernel/sys_takara.c mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); mask 44 arch/alpha/kernel/sys_takara.c outl(mask & 0xffff0000UL, regaddr); mask 51 arch/alpha/kernel/sys_takara.c unsigned long mask; mask 52 arch/alpha/kernel/sys_takara.c mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); mask 53 arch/alpha/kernel/sys_takara.c takara_update_irq_hw(irq, mask); mask 60 arch/alpha/kernel/sys_takara.c unsigned long mask; mask 61 arch/alpha/kernel/sys_takara.c mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); mask 62 arch/alpha/kernel/sys_takara.c takara_update_irq_hw(irq, mask); mask 61 arch/alpha/kernel/sys_titan.c titan_update_irq_hw(unsigned long mask) mask 73 arch/alpha/kernel/sys_titan.c mask &= ~isa_enable; mask 74 arch/alpha/kernel/sys_titan.c mask0 = mask & titan_cpu_irq_affinity[0]; mask 75 arch/alpha/kernel/sys_titan.c mask1 = mask & titan_cpu_irq_affinity[1]; mask 76 arch/alpha/kernel/sys_titan.c mask2 = mask & titan_cpu_irq_affinity[2]; mask 77 arch/alpha/kernel/sys_titan.c mask3 = mask & titan_cpu_irq_affinity[3]; mask 109 arch/alpha/kernel/sys_titan.c *dimB = mask | isa_enable; mask 236 arch/alpha/kernel/sys_titan.c titan_dispatch_irqs(u64 mask) mask 243 arch/alpha/kernel/sys_titan.c mask &= titan_cpu_irq_affinity[smp_processor_id()]; mask 248 arch/alpha/kernel/sys_titan.c while (mask) { mask 250 arch/alpha/kernel/sys_titan.c vector = 63 - __kernel_ctlz(mask); mask 251 arch/alpha/kernel/sys_titan.c mask &= ~(1UL << vector); /* clear it out */ mask 147 arch/alpha/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 273 arch/alpha/kernel/time.c .mask = CLOCKSOURCE_MASK(32), mask 159 arch/alpha/oprofile/op_model_ev5.c unsigned long values, mask, not_pk, reset_values; mask 161 arch/alpha/oprofile/op_model_ev5.c mask = (ctr == 0 ? 0xfffful << 48 mask 171 arch/alpha/oprofile/op_model_ev5.c values = (reset_values & mask) | (values & ~mask & -2); mask 176 arch/alpha/oprofile/op_model_ev5.c values = (reset_values & mask) | (values & ~mask & -2); mask 245 arch/arc/include/asm/bitops.h unsigned long mask; mask 249 arch/arc/include/asm/bitops.h mask = 1UL << (nr & 0x1f); mask 251 arch/arc/include/asm/bitops.h return ((mask & *addr) != 0); mask 24 arch/arc/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 324 arch/arc/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 326 arch/arc/kernel/smp.c ipi_send_msg(mask, IPI_CALL_FUNC); mask 67 arch/arc/mm/fault.c unsigned int write = 0, exec = 0, mask; mask 117 arch/arc/mm/fault.c mask = VM_READ; mask 119 arch/arc/mm/fault.c mask = VM_WRITE; mask 121 arch/arc/mm/fault.c mask = VM_EXEC; mask 123 arch/arc/mm/fault.c if (!(vma->vm_flags & mask)) { mask 423 arch/arm/common/bL_switcher.c unsigned int cpu, cluster, mask; mask 427 arch/arm/common/bL_switcher.c mask = 0; mask 437 arch/arm/common/bL_switcher.c mask |= (1 << cluster); mask 439 arch/arm/common/bL_switcher.c if (mask != 3) { mask 226 arch/arm/common/dmabounce.c unsigned long limit, mask = *dev->dma_mask; mask 228 arch/arm/common/dmabounce.c limit = (mask + 1) & ~mask; mask 236 arch/arm/common/dmabounce.c if ((dma_addr | (dma_addr + size - 1)) & ~mask) mask 197 arch/arm/common/it8152.c u32 v, vtemp, mask = 0; mask 201 arch/arm/common/it8152.c mask = 0xff; mask 203 arch/arm/common/it8152.c mask = 0xffff; mask 210 arch/arm/common/it8152.c if (mask) mask 211 arch/arm/common/it8152.c vtemp &= ~(mask << (8 * shift)); mask 274 arch/arm/common/it8152.c int dma_set_coherent_mask(struct device *dev, u64 mask) mask 276 arch/arm/common/it8152.c if (mask >= PHYS_OFFSET + SZ_64M - 1) mask 294 arch/arm/common/sa1111.c u32 ip, mask = sa1111_irqmask(d); mask 299 arch/arm/common/sa1111.c writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0); mask 301 arch/arm/common/sa1111.c if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask) mask 315 arch/arm/common/sa1111.c u32 ip, mask = sa1111_irqmask(d); mask 325 arch/arm/common/sa1111.c ip &= ~mask; mask 327 arch/arm/common/sa1111.c ip |= mask; mask 338 arch/arm/common/sa1111.c u32 we, mask = sa1111_irqmask(d); mask 342 arch/arm/common/sa1111.c we |= mask; mask 344 arch/arm/common/sa1111.c we &= ~mask; mask 507 arch/arm/common/sa1111.c static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set) mask 512 arch/arm/common/sa1111.c val &= ~mask; mask 513 arch/arm/common/sa1111.c val |= mask & set; mask 521 arch/arm/common/sa1111.c u32 mask = sa1111_gpio_map_bit(offset); mask 523 arch/arm/common/sa1111.c return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask); mask 531 arch/arm/common/sa1111.c u32 mask = sa1111_gpio_map_bit(offset); mask 534 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask); mask 535 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask); mask 547 arch/arm/common/sa1111.c u32 mask = sa1111_gpio_map_bit(offset); mask 550 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); mask 551 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); mask 552 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0); mask 553 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0); mask 563 arch/arm/common/sa1111.c u32 mask = sa1111_gpio_map_bit(offset); mask 565 arch/arm/common/sa1111.c return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask); mask 573 arch/arm/common/sa1111.c u32 mask = sa1111_gpio_map_bit(offset); mask 576 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0); mask 577 arch/arm/common/sa1111.c sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0); mask 581 arch/arm/common/sa1111.c static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 589 arch/arm/common/sa1111.c msk = *mask; mask 85 arch/arm/include/asm/barrier.h unsigned long mask; mask 91 arch/arm/include/asm/barrier.h : "=r" (mask) mask 95 arch/arm/include/asm/barrier.h return mask; mask 39 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 44 arch/arm/include/asm/bitops.h *p |= mask; mask 51 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 56 arch/arm/include/asm/bitops.h *p &= ~mask; mask 63 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 68 arch/arm/include/asm/bitops.h *p ^= mask; mask 77 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 83 arch/arm/include/asm/bitops.h *p = res | mask; mask 86 arch/arm/include/asm/bitops.h return (res & mask) != 0; mask 94 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 100 arch/arm/include/asm/bitops.h *p = res & ~mask; mask 103 arch/arm/include/asm/bitops.h return (res & mask) != 0; mask 111 arch/arm/include/asm/bitops.h unsigned long mask = BIT_MASK(bit); mask 117 arch/arm/include/asm/bitops.h *p = res ^ mask; mask 120 arch/arm/include/asm/bitops.h return (res & mask) != 0; mask 54 arch/arm/include/asm/cachetype.h static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) mask 56 arch/arm/include/asm/cachetype.h return (__CACHEID_ALWAYS & mask) | mask 57 arch/arm/include/asm/cachetype.h (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid); mask 19 arch/arm/include/asm/dma-direct.h u64 limit, mask; mask 24 arch/arm/include/asm/dma-direct.h mask = *dev->dma_mask; mask 26 arch/arm/include/asm/dma-direct.h limit = (mask + 1) & ~mask; mask 30 arch/arm/include/asm/dma-direct.h if ((addr | (addr + size - 1)) & ~mask) mask 36 arch/arm/include/asm/dma-iommu.h int arm_dma_supported(struct device *dev, u64 mask); mask 38 arch/arm/include/asm/io.h extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set); mask 39 arch/arm/include/asm/io.h extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set); mask 34 arch/arm/include/asm/irq.h extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, mask 260 arch/arm/include/asm/kvm_host.h void force_vm_exit(const cpumask_t *mask); mask 38 arch/arm/include/asm/mmu_context.h cpumask_t *mask); mask 41 arch/arm/include/asm/mmu_context.h cpumask_t *mask) mask 250 arch/arm/include/asm/pgtable-3level.h const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY | mask 252 arch/arm/include/asm/pgtable-3level.h pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask); mask 113 arch/arm/include/asm/pgtable.h #define __pgprot_modify(prot,mask,bits) \ mask 114 arch/arm/include/asm/pgtable.h __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) mask 237 arch/arm/include/asm/pgtable.h pteval_t mask = L_PTE_PRESENT | L_PTE_USER; mask 238 arch/arm/include/asm/pgtable.h pteval_t needed = mask; mask 241 arch/arm/include/asm/pgtable.h mask |= L_PTE_RDONLY; mask 243 arch/arm/include/asm/pgtable.h return (pte_val(pte) & mask) == needed; mask 323 arch/arm/include/asm/pgtable.h const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER | mask 325 arch/arm/include/asm/pgtable.h pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); mask 75 arch/arm/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 76 arch/arm/include/asm/smp.h extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); mask 96 arch/arm/include/asm/smp_plat.h u32 mask; /* used by sleep.S */ mask 22 arch/arm/include/asm/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 23 arch/arm/include/asm/word-at-a-time.h *bits = mask; mask 24 arch/arm/include/asm/word-at-a-time.h return mask; mask 35 arch/arm/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 41 arch/arm/include/asm/word-at-a-time.h ret = fls(mask) >> 3; mask 44 arch/arm/include/asm/word-at-a-time.h ret = (0x0ff0001 + mask) >> 23; mask 46 arch/arm/include/asm/word-at-a-time.h ret &= mask; mask 52 arch/arm/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 15 arch/arm/kernel/io.c void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) mask 21 arch/arm/kernel/io.c value = readl_relaxed(reg) & ~mask; mask 22 arch/arm/kernel/io.c value |= (set & mask); mask 28 arch/arm/kernel/io.c void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) mask 34 arch/arm/kernel/io.c value = readl_relaxed(reg) & ~mask; mask 35 arch/arm/kernel/io.c value |= (set & mask); mask 271 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, evt, flags; mask 278 arch/arm/kernel/perf_event_v6.c mask = 0; mask 281 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_EVT_COUNT0_MASK; mask 285 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_EVT_COUNT1_MASK; mask 299 arch/arm/kernel/perf_event_v6.c val &= ~mask; mask 422 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, evt, flags; mask 429 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_CCOUNT_IEN; mask 432 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; mask 435 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; mask 449 arch/arm/kernel/perf_event_v6.c val &= ~mask; mask 457 arch/arm/kernel/perf_event_v6.c unsigned long val, mask, flags, evt = 0; mask 464 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_CCOUNT_IEN; mask 466 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_COUNT0_IEN; mask 468 arch/arm/kernel/perf_event_v6.c mask = ARMV6_PMCR_COUNT1_IEN; mask 480 arch/arm/kernel/perf_event_v6.c val &= ~mask; mask 1418 arch/arm/kernel/perf_event_v7.c u32 mask; mask 1427 arch/arm/kernel/perf_event_v7.c mask = 0xff << group_shift; mask 1442 arch/arm/kernel/perf_event_v7.c val &= ~mask; mask 1449 arch/arm/kernel/perf_event_v7.c val &= ~mask; mask 1458 arch/arm/kernel/perf_event_v7.c u32 mask; mask 1462 arch/arm/kernel/perf_event_v7.c mask = 0xff << group_shift; mask 1463 arch/arm/kernel/perf_event_v7.c val &= ~mask; mask 1765 arch/arm/kernel/perf_event_v7.c u32 mask; mask 1774 arch/arm/kernel/perf_event_v7.c mask = 0xff << group_shift; mask 1791 arch/arm/kernel/perf_event_v7.c val &= ~mask; mask 1798 arch/arm/kernel/perf_event_v7.c val &= ~mask; mask 206 arch/arm/kernel/perf_event_xscale.c unsigned long val, mask, evt, flags; mask 214 arch/arm/kernel/perf_event_xscale.c mask = 0; mask 218 arch/arm/kernel/perf_event_xscale.c mask = XSCALE1_COUNT0_EVT_MASK; mask 223 arch/arm/kernel/perf_event_xscale.c mask = XSCALE1_COUNT1_EVT_MASK; mask 234 arch/arm/kernel/perf_event_xscale.c val &= ~mask; mask 242 arch/arm/kernel/perf_event_xscale.c unsigned long val, mask, evt, flags; mask 250 arch/arm/kernel/perf_event_xscale.c mask = XSCALE1_CCOUNT_INT_EN; mask 254 arch/arm/kernel/perf_event_xscale.c mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; mask 258 arch/arm/kernel/perf_event_xscale.c mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; mask 268 arch/arm/kernel/perf_event_xscale.c val &= ~mask; mask 21 arch/arm/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 23 arch/arm/kernel/perf_regs.c if (!mask || mask & REG_RESERVED) mask 422 arch/arm/kernel/setup.c unsigned int mask; mask 424 arch/arm/kernel/setup.c mask = IS_ENABLED(CONFIG_THUMB2_KERNEL) ? HWCAP_IDIVT : HWCAP_IDIVA; mask 425 arch/arm/kernel/setup.c if (!(elf_hwcap & mask)) mask 616 arch/arm/kernel/setup.c u32 fs[3], bits[3], ls, mask = 0; mask 622 arch/arm/kernel/setup.c mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); mask 623 arch/arm/kernel/setup.c pr_debug("mask of set bits 0x%x\n", mask); mask 629 arch/arm/kernel/setup.c affinity = MPIDR_AFFINITY_LEVEL(mask, i); mask 653 arch/arm/kernel/setup.c mpidr_hash.mask = mask; mask 659 arch/arm/kernel/setup.c mpidr_hash.mask, mask 556 arch/arm/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 558 arch/arm/kernel/smp.c smp_cross_call(mask, IPI_CALL_FUNC); mask 561 arch/arm/kernel/smp.c void arch_send_wakeup_ipi_mask(const struct cpumask *mask) mask 563 arch/arm/kernel/smp.c smp_cross_call(mask, IPI_WAKEUP); mask 580 arch/arm/kernel/smp.c void tick_broadcast(const struct cpumask *mask) mask 582 arch/arm/kernel/smp.c smp_cross_call(mask, IPI_TIMER); mask 711 arch/arm/kernel/smp.c struct cpumask mask; mask 713 arch/arm/kernel/smp.c cpumask_copy(&mask, cpu_online_mask); mask 714 arch/arm/kernel/smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 715 arch/arm/kernel/smp.c if (!cpumask_empty(&mask)) mask 716 arch/arm/kernel/smp.c smp_cross_call(&mask, IPI_CPU_STOP); mask 808 arch/arm/kernel/smp.c static void raise_nmi(cpumask_t *mask) mask 810 arch/arm/kernel/smp.c __smp_cross_call(mask, IPI_CPU_BACKTRACE); mask 813 arch/arm/kernel/smp.c void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) mask 815 arch/arm/kernel/smp.c nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_nmi); mask 167 arch/arm/kernel/smp_tlb.c cpumask_t mask = { CPU_BITS_NONE }; mask 173 arch/arm/kernel/smp_tlb.c a15_erratum_get_cpumask(this_cpu, mm, &mask); mask 174 arch/arm/kernel/smp_tlb.c smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1); mask 245 arch/arm/kernel/unwind.c unsigned long mask) mask 250 arch/arm/kernel/unwind.c load_sp = mask & (1 << (13 - 4)); mask 251 arch/arm/kernel/unwind.c while (mask) { mask 252 arch/arm/kernel/unwind.c if (mask & 1) mask 255 arch/arm/kernel/unwind.c mask >>= 1; mask 285 arch/arm/kernel/unwind.c unsigned long mask) mask 291 arch/arm/kernel/unwind.c while (mask) { mask 292 arch/arm/kernel/unwind.c if (mask & 1) mask 295 arch/arm/kernel/unwind.c mask >>= 1; mask 318 arch/arm/kernel/unwind.c unsigned long mask; mask 321 arch/arm/kernel/unwind.c mask = insn & 0x0fff; mask 322 arch/arm/kernel/unwind.c if (mask == 0) { mask 328 arch/arm/kernel/unwind.c ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask); mask 344 arch/arm/kernel/unwind.c unsigned long mask = unwind_get_byte(ctrl); mask 346 arch/arm/kernel/unwind.c if (mask == 0 || mask & 0xf0) { mask 348 arch/arm/kernel/unwind.c (insn << 8) | mask); mask 352 arch/arm/kernel/unwind.c ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask); mask 334 arch/arm/kernel/vdso.c vdso_data->cs_mask = tk->tkr_mono.mask; mask 40 arch/arm/lib/bitops.h mov r3, r2, lsl r3 @ create mask mask 62 arch/arm/mach-bcm/bcm63xx_pmb.c u32 shift, u32 mask, u32 cond) mask 76 arch/arm/mach-bcm/bcm63xx_pmb.c } while (((*val >> shift) & mask) != cond); mask 96 arch/arm/mach-bcm/platsmp-brcmstb.c static void pwr_ctrl_set(unsigned int cpu, u32 val, u32 mask) mask 99 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) | val, base); mask 102 arch/arm/mach-bcm/platsmp-brcmstb.c static void pwr_ctrl_clr(unsigned int cpu, u32 val, u32 mask) mask 105 arch/arm/mach-bcm/platsmp-brcmstb.c writel((readl(base) & mask) & ~val, base); mask 109 arch/arm/mach-bcm/platsmp-brcmstb.c static int pwr_ctrl_wait_tmout(unsigned int cpu, u32 set, u32 mask) mask 115 arch/arm/mach-bcm/platsmp-brcmstb.c tmp = pwr_ctrl_rd(cpu) & mask; mask 120 arch/arm/mach-bcm/platsmp-brcmstb.c tmp = pwr_ctrl_rd(cpu) & mask; mask 90 arch/arm/mach-cns3xxx/pcie.c u32 mask = (0x1ull << (size * 8)) - 1; mask 102 arch/arm/mach-cns3xxx/pcie.c *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask; mask 217 arch/arm/mach-cns3xxx/pcie.c u32 mask = (0x1ull << (size * 8)) - 1; mask 222 arch/arm/mach-cns3xxx/pcie.c v &= ~(mask << shift); mask 223 arch/arm/mach-cns3xxx/pcie.c v |= (val & mask) << shift; mask 604 arch/arm/mach-davinci/board-dm365-evm.c u8 mask; mask 627 arch/arm/mach-davinci/board-dm365-evm.c reg &= ~led->mask; mask 629 arch/arm/mach-davinci/board-dm365-evm.c reg |= led->mask; mask 638 arch/arm/mach-davinci/board-dm365-evm.c return (reg & led->mask) ? LED_OFF : LED_FULL; mask 661 arch/arm/mach-davinci/board-dm365-evm.c led->mask = BIT(i); mask 27 arch/arm/mach-davinci/include/mach/mux.h const unsigned char mask; mask 40 arch/arm/mach-davinci/mux.c unsigned int mask, warn = 0; mask 66 arch/arm/mach-davinci/mux.c if (cfg->mask) { mask 72 arch/arm/mach-davinci/mux.c mask = (cfg->mask << cfg->mask_offset); mask 73 arch/arm/mach-davinci/mux.c tmp1 = reg_orig & mask; mask 74 arch/arm/mach-davinci/mux.c reg = reg_orig & ~mask; mask 25 arch/arm/mach-davinci/mux.h .mask = mode_mask, \ mask 36 arch/arm/mach-davinci/mux.h .mask = mode_mask, \ mask 47 arch/arm/mach-davinci/mux.h .mask = mode_mask, \ mask 273 arch/arm/mach-davinci/time.c .mask = CLOCKSOURCE_MASK(32), mask 29 arch/arm/mach-exynos/common.h #define IS_SAMSUNG_CPU(name, id, mask) \ mask 32 arch/arm/mach-exynos/common.h return ((samsung_cpu_id & mask) == (id & mask)); \ mask 120 arch/arm/mach-exynos/pm.c static void exynos_set_wakeupmask(long mask) mask 122 arch/arm/mach-exynos/pm.c pmu_raw_writel(mask, S5P_WAKEUP_MASK); mask 47 arch/arm/mach-exynos/suspend.c u32 mask; mask 110 arch/arm/mach-exynos/suspend.c while (wkup_irq->mask) { mask 113 arch/arm/mach-exynos/suspend.c exynos_irqwake_intmask |= wkup_irq->mask; mask 115 arch/arm/mach-exynos/suspend.c exynos_irqwake_intmask &= ~wkup_irq->mask; mask 25 arch/arm/mach-footbridge/dc21285-timer.c return cs->mask - *CSR_TIMER2_VALUE; mask 30 arch/arm/mach-footbridge/dc21285-timer.c *CSR_TIMER2_LOAD = cs->mask; mask 47 arch/arm/mach-footbridge/dc21285-timer.c .mask = CLOCKSOURCE_MASK(24), mask 29 arch/arm/mach-footbridge/ebsa285.c u8 mask; mask 55 arch/arm/mach-footbridge/ebsa285.c hw_led_state |= led->mask; mask 57 arch/arm/mach-footbridge/ebsa285.c hw_led_state &= ~led->mask; mask 66 arch/arm/mach-footbridge/ebsa285.c return hw_led_state & led->mask ? LED_OFF : LED_FULL; mask 95 arch/arm/mach-footbridge/ebsa285.c led->mask = BIT(i); mask 90 arch/arm/mach-footbridge/include/mach/hardware.h extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); mask 91 arch/arm/mach-footbridge/include/mach/hardware.h extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); mask 93 arch/arm/mach-footbridge/include/mach/hardware.h extern void nw_cpld_modify(unsigned int mask, unsigned int set); mask 32 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 34 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); mask 39 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 41 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); mask 47 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 49 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); mask 60 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 62 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); mask 67 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 69 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); mask 76 arch/arm/mach-footbridge/isa-irq.c unsigned int mask = 1 << (d->irq & 7); mask 78 arch/arm/mach-footbridge/isa-irq.c outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); mask 74 arch/arm/mach-footbridge/netwinder-hw.c void nw_gpio_modify_op(unsigned int mask, unsigned int set) mask 78 arch/arm/mach-footbridge/netwinder-hw.c new_gpio = (current_gpio_op & ~mask) | set; mask 89 arch/arm/mach-footbridge/netwinder-hw.c static inline void __gpio_modify_io(int mask, int in) mask 94 arch/arm/mach-footbridge/netwinder-hw.c new_gpio = (current_gpio_io & ~mask) | in; mask 120 arch/arm/mach-footbridge/netwinder-hw.c void nw_gpio_modify_io(unsigned int mask, unsigned int in) mask 125 arch/arm/mach-footbridge/netwinder-hw.c __gpio_modify_io(mask, in); mask 363 arch/arm/mach-footbridge/netwinder-hw.c void nw_cpld_modify(unsigned int mask, unsigned int set) mask 367 arch/arm/mach-footbridge/netwinder-hw.c current_cpld = (current_cpld & ~mask) | set; mask 668 arch/arm/mach-footbridge/netwinder-hw.c u8 mask; mask 699 arch/arm/mach-footbridge/netwinder-hw.c reg &= ~led->mask; mask 701 arch/arm/mach-footbridge/netwinder-hw.c reg |= led->mask; mask 702 arch/arm/mach-footbridge/netwinder-hw.c nw_gpio_modify_op(led->mask, reg); mask 717 arch/arm/mach-footbridge/netwinder-hw.c return (reg & led->mask) ? LED_OFF : LED_FULL; mask 740 arch/arm/mach-footbridge/netwinder-hw.c led->mask = GPIO_GREEN_LED; mask 742 arch/arm/mach-footbridge/netwinder-hw.c led->mask = GPIO_RED_LED; mask 87 arch/arm/mach-imx/avic.c avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); mask 88 arch/arm/mach-imx/avic.c imx_writel(gc->wake_active, avic_base + ct->regs.mask); mask 109 arch/arm/mach-imx/avic.c imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); mask 141 arch/arm/mach-imx/avic.c ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH; mask 142 arch/arm/mach-imx/avic.c ct->regs.ack = ct->regs.mask; mask 92 arch/arm/mach-imx/gpc.c u32 mask; mask 94 arch/arm/mach-imx/gpc.c mask = 1 << d->hwirq % 32; mask 95 arch/arm/mach-imx/gpc.c gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : mask 96 arch/arm/mach-imx/gpc.c gpc_wake_irqs[idx] & ~mask; mask 37 arch/arm/mach-imx/iomux-v1.c unsigned long mask, unsigned long value) mask 41 arch/arm/mach-imx/iomux-v1.c reg &= ~mask; mask 50 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 1 << pin; mask 52 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); mask 58 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 1 << pin; mask 60 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); mask 66 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 1 << pin; mask 68 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); mask 74 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 1 << pin; mask 76 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); mask 83 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 3 << shift; mask 87 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(offset, mask, value); mask 94 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 3 << shift; mask 98 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(offset, mask, value); mask 105 arch/arm/mach-imx/iomux-v1.c unsigned long mask = 3 << shift; mask 109 arch/arm/mach-imx/iomux-v1.c imx_iomuxv1_rmwl(offset, mask, value); mask 229 arch/arm/mach-imx/mach-imx6q.c unsigned int mask; mask 237 arch/arm/mach-imx/mach-imx6q.c mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | mask 243 arch/arm/mach-imx/mach-imx6q.c regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); mask 81 arch/arm/mach-imx/src.c u32 mask, val; mask 84 arch/arm/mach-imx/src.c mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); mask 87 arch/arm/mach-imx/src.c val = enable ? val | mask : val & ~mask; mask 54 arch/arm/mach-imx/tzic.c unsigned int index, mask, value; mask 59 arch/arm/mach-imx/tzic.c mask = 1U << (hwirq & 0x1F); mask 61 arch/arm/mach-imx/tzic.c value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; mask 63 arch/arm/mach-imx/tzic.c value &= ~mask; mask 49 arch/arm/mach-integrator/core.c void cm_control(u32 mask, u32 set) mask 55 arch/arm/mach-integrator/core.c val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; mask 41 arch/arm/mach-integrator/impd1.c void impd1_tweak_control(struct device *dev, u32 mask, u32 val) mask 46 arch/arm/mach-integrator/impd1.c val &= mask; mask 47 arch/arm/mach-integrator/impd1.c cur = readl(impd1->base + IMPD1_CTRL) & ~mask; mask 15 arch/arm/mach-integrator/impd1.h void impd1_tweak_control(struct device *dev, u32 mask, u32 val); mask 47 arch/arm/mach-iop32x/time.c .mask = CLOCKSOURCE_MASK(32), mask 317 arch/arm/mach-ixp4xx/common.c int dma_set_coherent_mask(struct device *dev, u64 mask) mask 320 arch/arm/mach-ixp4xx/common.c mask &= DMA_BIT_MASK(28); /* 64 MB */ mask 322 arch/arm/mach-ixp4xx/common.c if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) { mask 323 arch/arm/mach-ixp4xx/common.c dev->coherent_dma_mask = mask; mask 85 arch/arm/mach-mmp/pxa168.c uint32_t mask = APMU_PXA168_KP_WAKE_CLR; mask 89 arch/arm/mach-mmp/pxa168.c __raw_writel(val | mask, APMU_WAKE_CLR); mask 148 arch/arm/mach-mmp/time.c .mask = CLOCKSOURCE_MASK(32), mask 59 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_setl(u32 mask, void __iomem *reg) mask 61 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_SET_ADDR); mask 64 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_clrl(u32 mask, void __iomem *reg) mask 66 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_CLR_ADDR); mask 69 arch/arm/mach-mxs/mach-mxs.c static inline void __mxs_togl(u32 mask, void __iomem *reg) mask 71 arch/arm/mach-mxs/mach-mxs.c __raw_writel(mask, reg + MXS_TOG_ADDR); mask 22 arch/arm/mach-omap1/board-nand.c unsigned long mask; mask 27 arch/arm/mach-omap1/board-nand.c mask = (ctrl & NAND_CLE) ? 0x02 : 0; mask 29 arch/arm/mach-omap1/board-nand.c mask |= 0x04; mask 31 arch/arm/mach-omap1/board-nand.c writeb(cmd, this->legacy.IO_ADDR_W + mask); mask 30 arch/arm/mach-omap1/include/mach/mux.h .mask = mode, mask 44 arch/arm/mach-omap1/include/mach/mux.h .mask = mode, mask 55 arch/arm/mach-omap1/include/mach/mux.h .mask = mode, mask 67 arch/arm/mach-omap1/include/mach/mux.h .mask = mode, mask 110 arch/arm/mach-omap1/include/mach/mux.h const unsigned char mask; mask 187 arch/arm/mach-omap1/irq.c ct->regs.mask = IRQ_MIR_REG_OFFSET; mask 338 arch/arm/mach-omap1/mux.c unsigned int mask, warn = 0; mask 348 arch/arm/mach-omap1/mux.c mask = (0x7 << cfg->mask_offset); mask 349 arch/arm/mach-omap1/mux.c tmp1 = reg_orig & mask; mask 350 arch/arm/mach-omap1/mux.c reg = reg_orig & ~mask; mask 352 arch/arm/mach-omap1/mux.c tmp2 = (cfg->mask << cfg->mask_offset); mask 367 arch/arm/mach-omap1/mux.c mask = 1 << cfg->pull_bit; mask 370 arch/arm/mach-omap1/mux.c if (!(pu_pd_orig & mask)) mask 373 arch/arm/mach-omap1/mux.c pu_pd = pu_pd_orig | mask; mask 375 arch/arm/mach-omap1/mux.c if (pu_pd_orig & mask) mask 378 arch/arm/mach-omap1/mux.c pu_pd = pu_pd_orig & ~mask; mask 389 arch/arm/mach-omap1/mux.c mask = 1 << cfg->pull_bit; mask 392 arch/arm/mach-omap1/mux.c if (pull_orig & mask) mask 395 arch/arm/mach-omap1/mux.c pull = pull_orig & ~mask; mask 397 arch/arm/mach-omap1/mux.c if (!(pull_orig & mask)) mask 400 arch/arm/mach-omap1/mux.c pull = pull_orig | mask; mask 43 arch/arm/mach-omap2/cm2xxx.c static void _write_clktrctrl(u8 c, s16 module, u32 mask) mask 48 arch/arm/mach-omap2/cm2xxx.c v &= ~mask; mask 49 arch/arm/mach-omap2/cm2xxx.c v |= c << __ffs(mask); mask 53 arch/arm/mach-omap2/cm2xxx.c static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) mask 58 arch/arm/mach-omap2/cm2xxx.c v &= mask; mask 59 arch/arm/mach-omap2/cm2xxx.c v >>= __ffs(mask); mask 64 arch/arm/mach-omap2/cm2xxx.c static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) mask 66 arch/arm/mach-omap2/cm2xxx.c _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); mask 69 arch/arm/mach-omap2/cm2xxx.c static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) mask 71 arch/arm/mach-omap2/cm2xxx.c _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); mask 102 arch/arm/mach-omap2/cm2xxx.c static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) mask 107 arch/arm/mach-omap2/cm2xxx.c v &= ~mask; mask 108 arch/arm/mach-omap2/cm2xxx.c v |= m << __ffs(mask); mask 250 arch/arm/mach-omap2/cm2xxx.c u32 mask; mask 257 arch/arm/mach-omap2/cm2xxx.c mask = 1 << idlest_shift; mask 258 arch/arm/mach-omap2/cm2xxx.c ena = mask; mask 261 arch/arm/mach-omap2/cm2xxx.c mask) == ena), MAX_MODULE_READY_TIME, i); mask 61 arch/arm/mach-omap2/cm2xxx_3xxx.h static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, mask 67 arch/arm/mach-omap2/cm2xxx_3xxx.h v &= ~mask; mask 75 arch/arm/mach-omap2/cm2xxx_3xxx.h static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) mask 80 arch/arm/mach-omap2/cm2xxx_3xxx.h v &= mask; mask 81 arch/arm/mach-omap2/cm2xxx_3xxx.h v >>= __ffs(mask); mask 63 arch/arm/mach-omap2/cm33xx.c static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) mask 68 arch/arm/mach-omap2/cm33xx.c v &= ~mask; mask 75 arch/arm/mach-omap2/cm33xx.c static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) mask 80 arch/arm/mach-omap2/cm33xx.c v &= mask; mask 81 arch/arm/mach-omap2/cm33xx.c v >>= __ffs(mask); mask 32 arch/arm/mach-omap2/cm3xxx.c static void _write_clktrctrl(u8 c, s16 module, u32 mask) mask 37 arch/arm/mach-omap2/cm3xxx.c v &= ~mask; mask 38 arch/arm/mach-omap2/cm3xxx.c v |= c << __ffs(mask); mask 42 arch/arm/mach-omap2/cm3xxx.c static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) mask 47 arch/arm/mach-omap2/cm3xxx.c v &= mask; mask 48 arch/arm/mach-omap2/cm3xxx.c v >>= __ffs(mask); mask 53 arch/arm/mach-omap2/cm3xxx.c static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) mask 55 arch/arm/mach-omap2/cm3xxx.c _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); mask 58 arch/arm/mach-omap2/cm3xxx.c static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) mask 60 arch/arm/mach-omap2/cm3xxx.c _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); mask 63 arch/arm/mach-omap2/cm3xxx.c static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) mask 65 arch/arm/mach-omap2/cm3xxx.c _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); mask 68 arch/arm/mach-omap2/cm3xxx.c static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) mask 70 arch/arm/mach-omap2/cm3xxx.c _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); mask 93 arch/arm/mach-omap2/cm3xxx.c u32 mask; mask 100 arch/arm/mach-omap2/cm3xxx.c mask = 1 << idlest_shift; mask 104 arch/arm/mach-omap2/cm3xxx.c mask) == ena), MAX_MODULE_READY_TIME, i); mask 175 arch/arm/mach-omap2/cm3xxx.c u32 mask = 0; mask 181 arch/arm/mach-omap2/cm3xxx.c mask |= 1 << cd->clkdm->dep_bit; mask 184 arch/arm/mach-omap2/cm3xxx.c omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, mask 131 arch/arm/mach-omap2/cminst44xx.c static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst, mask 137 arch/arm/mach-omap2/cminst44xx.c v &= ~mask; mask 155 arch/arm/mach-omap2/cminst44xx.c static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask) mask 160 arch/arm/mach-omap2/cminst44xx.c v &= mask; mask 161 arch/arm/mach-omap2/cminst44xx.c v >>= __ffs(mask); mask 383 arch/arm/mach-omap2/cminst44xx.c u32 mask = 0; mask 392 arch/arm/mach-omap2/cminst44xx.c mask |= 1 << cd->clkdm->dep_bit; mask 396 arch/arm/mach-omap2/cminst44xx.c omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, mask 588 arch/arm/mach-omap2/control.c u16 mask, padconf; mask 596 arch/arm/mach-omap2/control.c mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ mask 598 arch/arm/mach-omap2/control.c padconf |= mask; mask 602 arch/arm/mach-omap2/control.c padconf |= mask; mask 500 arch/arm/mach-omap2/prcm-common.h u16 mask; mask 38 arch/arm/mach-omap2/prcm_mpu44xx.c u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) mask 43 arch/arm/mach-omap2/prcm_mpu44xx.c v &= ~mask; mask 29 arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, mask 55 arch/arm/mach-omap2/prm2xxx_3xxx.c u32 mask; mask 57 arch/arm/mach-omap2/prm2xxx_3xxx.c mask = 1 << shift; mask 58 arch/arm/mach-omap2/prm2xxx_3xxx.c omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); mask 222 arch/arm/mach-omap2/prm2xxx_3xxx.c u32 mask = 0; mask 229 arch/arm/mach-omap2/prm2xxx_3xxx.c mask |= 1 << cd->clkdm->dep_bit; mask 233 arch/arm/mach-omap2/prm2xxx_3xxx.c omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, mask 64 arch/arm/mach-omap2/prm2xxx_3xxx.h static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, mask 70 arch/arm/mach-omap2/prm2xxx_3xxx.h v &= ~mask; mask 78 arch/arm/mach-omap2/prm2xxx_3xxx.h static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) mask 83 arch/arm/mach-omap2/prm2xxx_3xxx.h v &= mask; mask 84 arch/arm/mach-omap2/prm2xxx_3xxx.h v >>= __ffs(mask); mask 43 arch/arm/mach-omap2/prm33xx.c static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) mask 48 arch/arm/mach-omap2/prm33xx.c v &= ~mask; mask 96 arch/arm/mach-omap2/prm33xx.c u32 mask = 1 << shift; mask 98 arch/arm/mach-omap2/prm33xx.c am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); mask 127 arch/arm/mach-omap2/prm33xx.c u32 mask = 1 << st_shift; mask 134 arch/arm/mach-omap2/prm33xx.c am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); mask 137 arch/arm/mach-omap2/prm33xx.c mask = 1 << shift; mask 139 arch/arm/mach-omap2/prm33xx.c am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); mask 43 arch/arm/mach-omap2/prm3xxx.c .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, mask 125 arch/arm/mach-omap2/prm3xxx.c u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) mask 127 arch/arm/mach-omap2/prm3xxx.c return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); mask 155 arch/arm/mach-omap2/prm3xxx.c u32 mask, st; mask 158 arch/arm/mach-omap2/prm3xxx.c mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); mask 161 arch/arm/mach-omap2/prm3xxx.c events[0] = mask & st; mask 138 arch/arm/mach-omap2/prm3xxx.h extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); mask 47 arch/arm/mach-omap2/prm44xx.c .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, mask 108 arch/arm/mach-omap2/prm44xx.c static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) mask 113 arch/arm/mach-omap2/prm44xx.c v &= ~mask; mask 190 arch/arm/mach-omap2/prm44xx.c u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) mask 197 arch/arm/mach-omap2/prm44xx.c return omap4_prminst_rmw_inst_reg_bits(mask, bits, mask 205 arch/arm/mach-omap2/prm44xx.c u32 mask, st; mask 208 arch/arm/mach-omap2/prm44xx.c mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, mask 212 arch/arm/mach-omap2/prm44xx.c return mask & st; mask 228 arch/arm/mach-omap2/prm44xx.c events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask + mask 263 arch/arm/mach-omap2/prm44xx.c reg = omap4_prcm_irq_setup.mask + i * 4; mask 293 arch/arm/mach-omap2/prm44xx.c omap4_prcm_irq_setup.mask + i * 4); mask 752 arch/arm/mach-omap2/prm44xx.c omap4_prcm_irq_setup.mask); mask 763 arch/arm/mach-omap2/prm44xx.c omap4_prcm_irq_setup.mask); mask 825 arch/arm/mach-omap2/prm44xx.c omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET; mask 33 arch/arm/mach-omap2/prm44xx_54xx.h extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); mask 262 arch/arm/mach-omap2/prm_common.c u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; mask 294 arch/arm/mach-omap2/prm_common.c memset(mask, 0, sizeof(mask)); mask 298 arch/arm/mach-omap2/prm_common.c mask[offset >> 5] |= 1 << (offset & 0x1f); mask 331 arch/arm/mach-omap2/prm_common.c ct->regs.mask = irq_setup->mask + i * 4; mask 333 arch/arm/mach-omap2/prm_common.c irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0); mask 76 arch/arm/mach-omap2/prminst44xx.c u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, mask 82 arch/arm/mach-omap2/prminst44xx.c v &= ~mask; mask 126 arch/arm/mach-omap2/prminst44xx.c u32 mask = 1 << shift; mask 128 arch/arm/mach-omap2/prminst44xx.c omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs); mask 156 arch/arm/mach-omap2/prminst44xx.c u32 mask = 1 << shift; mask 168 arch/arm/mach-omap2/prminst44xx.c omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); mask 22 arch/arm/mach-omap2/prminst44xx.h extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, mask 360 arch/arm/mach-omap2/timer.c void tick_broadcast(const struct cpumask *mask) mask 424 arch/arm/mach-omap2/timer.c .mask = CLOCKSOURCE_MASK(32), mask 487 arch/arm/mach-omap2/vc.c static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask) mask 494 arch/arm/mach-omap2/vc.c if (val > mask) mask 495 arch/arm/mach-omap2/vc.c val = mask; mask 76 arch/arm/mach-omap2/voltage.h u32 (*rmw)(u32 mask, u32 bits, u8 offset); mask 85 arch/arm/mach-orion5x/common.h #define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r)) mask 86 arch/arm/mach-orion5x/common.h #define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r)) mask 33 arch/arm/mach-pxa/generic.c void clear_reset_status(unsigned int mask) mask 36 arch/arm/mach-pxa/generic.c pxa2xx_clear_reset_status(mask); mask 39 arch/arm/mach-pxa/generic.c ARSR = mask; mask 56 arch/arm/mach-pxa/generic.h static inline void pxa2xx_clear_reset_status(unsigned int mask) {} mask 200 arch/arm/mach-pxa/idp.c u8 mask; mask 223 arch/arm/mach-pxa/idp.c reg &= ~led->mask; mask 225 arch/arm/mach-pxa/idp.c reg |= led->mask; mask 235 arch/arm/mach-pxa/idp.c return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL; mask 258 arch/arm/mach-pxa/idp.c led->mask = IDP_HB_LED; mask 260 arch/arm/mach-pxa/idp.c led->mask = IDP_BUSY_LED; mask 12 arch/arm/mach-pxa/include/mach/reset.h extern void clear_reset_status(unsigned int mask); mask 93 arch/arm/mach-pxa/irq.c uint32_t icip, icmr, mask; mask 98 arch/arm/mach-pxa/irq.c mask = icip & icmr; mask 100 arch/arm/mach-pxa/irq.c if (mask == 0) mask 103 arch/arm/mach-pxa/irq.c handle_IRQ(PXA_IRQ(fls(mask) - 1), regs); mask 119 arch/arm/mach-pxa/lubbock.c static void lubbock_set_misc_wr(unsigned int mask, unsigned int set) mask 121 arch/arm/mach-pxa/lubbock.c unsigned long m = mask, v = set; mask 545 arch/arm/mach-pxa/lubbock.c u8 mask; mask 574 arch/arm/mach-pxa/lubbock.c reg |= led->mask; mask 576 arch/arm/mach-pxa/lubbock.c reg &= ~led->mask; mask 587 arch/arm/mach-pxa/lubbock.c return (reg & led->mask) ? LED_FULL : LED_OFF; mask 610 arch/arm/mach-pxa/lubbock.c led->mask = BIT(i); mask 633 arch/arm/mach-pxa/mainstone.c u8 mask; mask 662 arch/arm/mach-pxa/mainstone.c reg |= led->mask; mask 664 arch/arm/mach-pxa/mainstone.c reg &= ~led->mask; mask 675 arch/arm/mach-pxa/mainstone.c return (reg & led->mask) ? LED_FULL : LED_OFF; mask 698 arch/arm/mach-pxa/mainstone.c led->mask = BIT(i); mask 43 arch/arm/mach-pxa/mfp-pxa2xx.c unsigned int mask; /* bit mask in PWER or PKWR */ mask 54 arch/arm/mach-pxa/mfp-pxa2xx.c unsigned long gafr, mask = GPIO_bit(gpio); mask 74 arch/arm/mach-pxa/mfp-pxa2xx.c GPDR(gpio) |= mask; mask 76 arch/arm/mach-pxa/mfp-pxa2xx.c GPDR(gpio) &= ~mask; mask 81 arch/arm/mach-pxa/mfp-pxa2xx.c PGSR(bank) |= mask; mask 85 arch/arm/mach-pxa/mfp-pxa2xx.c PGSR(bank) &= ~mask; mask 99 arch/arm/mach-pxa/mfp-pxa2xx.c gpdr_lpm[bank] |= mask; mask 101 arch/arm/mach-pxa/mfp-pxa2xx.c gpdr_lpm[bank] &= ~mask; mask 190 arch/arm/mach-pxa/mfp-pxa2xx.c PKWR |= d->mask; mask 192 arch/arm/mach-pxa/mfp-pxa2xx.c PKWR &= ~d->mask; mask 196 arch/arm/mach-pxa/mfp-pxa2xx.c mux_taken = (PWER & d->mux_mask) & (~d->mask); mask 202 arch/arm/mach-pxa/mfp-pxa2xx.c PWER = (PWER & ~d->mux_mask) | d->mask; mask 205 arch/arm/mach-pxa/mfp-pxa2xx.c PRER |= d->mask; mask 207 arch/arm/mach-pxa/mfp-pxa2xx.c PRER &= ~d->mask; mask 210 arch/arm/mach-pxa/mfp-pxa2xx.c PFER |= d->mask; mask 212 arch/arm/mach-pxa/mfp-pxa2xx.c PFER &= ~d->mask; mask 214 arch/arm/mach-pxa/mfp-pxa2xx.c PWER &= ~d->mask; mask 215 arch/arm/mach-pxa/mfp-pxa2xx.c PRER &= ~d->mask; mask 216 arch/arm/mach-pxa/mfp-pxa2xx.c PFER &= ~d->mask; mask 238 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[i].mask = GPIO_bit(i); mask 259 arch/arm/mach-pxa/mfp-pxa2xx.c unsigned int i, gpio, mask = 0; mask 272 arch/arm/mach-pxa/mfp-pxa2xx.c mask |= gpio_desc[gpio].mask; mask 276 arch/arm/mach-pxa/mfp-pxa2xx.c PKWR |= mask; mask 278 arch/arm/mach-pxa/mfp-pxa2xx.c PKWR &= ~mask; mask 294 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \ mask 318 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[gpio].mask = 1 << i; mask 328 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[i].mask = GPIO_bit(i); mask 332 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[35].mask = PWER_WE35; mask 122 arch/arm/mach-pxa/pxa25x.c uint32_t mask = 0; mask 128 arch/arm/mach-pxa/pxa25x.c mask = PWER_RTC; mask 136 arch/arm/mach-pxa/pxa25x.c PWER |= mask; mask 138 arch/arm/mach-pxa/pxa25x.c PWER &=~mask; mask 205 arch/arm/mach-pxa/pxa27x.c uint32_t mask; mask 215 arch/arm/mach-pxa/pxa27x.c mask = PWER_RTC; mask 218 arch/arm/mach-pxa/pxa27x.c mask = 1u << 26; mask 225 arch/arm/mach-pxa/pxa27x.c PWER |= mask; mask 227 arch/arm/mach-pxa/pxa27x.c PWER &=~mask; mask 21 arch/arm/mach-pxa/pxa2xx.c void pxa2xx_clear_reset_status(unsigned int mask) mask 24 arch/arm/mach-pxa/pxa2xx.c RCSR = mask; mask 201 arch/arm/mach-pxa/pxa3xx.c unsigned long flags, mask = 0; mask 205 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WSSP3; mask 208 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WMSL0; mask 212 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WUSBH; mask 215 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WKP; mask 218 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WAC97; mask 221 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WUSIM0; mask 224 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WSSP2; mask 227 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WI2C; mask 230 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WUART3; mask 233 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WUART2; mask 236 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WUART1; mask 239 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WMMC1; mask 242 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WSSP1; mask 245 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WRTC; mask 248 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WSSP4; mask 251 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WTSI; mask 254 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WUSIM1; mask 257 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WMMC2; mask 260 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_WFLASH; mask 263 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WUSB2; mask 266 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WEXTWAKE0; mask 269 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_WEXTWAKE1; mask 272 arch/arm/mach-pxa/pxa3xx.c mask = ADXER_MFP_GEN12; mask 280 arch/arm/mach-pxa/pxa3xx.c wakeup_src |= mask; mask 282 arch/arm/mach-pxa/pxa3xx.c wakeup_src &= ~mask; mask 24 arch/arm/mach-rpc/irq.c static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask) mask 28 arch/arm/mach-rpc/irq.c d->mask = mask; mask 35 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; mask 38 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); mask 39 arch/arm/mach-rpc/irq.c writeb(mask, base + CLR); mask 45 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; mask 48 arch/arm/mach-rpc/irq.c writeb(val & ~mask, base + MASK); mask 54 arch/arm/mach-rpc/irq.c unsigned int val, mask = d->mask; mask 57 arch/arm/mach-rpc/irq.c writeb(val | mask, base + MASK); mask 69 arch/arm/mach-rpc/time.c .mask = CLOCKSOURCE_MASK(32), mask 52 arch/arm/mach-s3c24xx/include/mach/pm-core.h unsigned long mask) mask 56 arch/arm/mach-s3c24xx/include/mach/pm-core.h which &= ~mask; mask 299 arch/arm/mach-s3c24xx/mach-anubis.c .mask = 0x0, mask 303 arch/arm/mach-s3c24xx/mach-anubis.c .mask = 0x1F1F00, mask 307 arch/arm/mach-s3c24xx/mach-anubis.c .mask = 0, mask 251 arch/arm/mach-s3c64xx/common.c u32 mask; mask 253 arch/arm/mach-s3c64xx/common.c mask = __raw_readl(S3C64XX_EINT0MASK); mask 254 arch/arm/mach-s3c64xx/common.c mask |= (u32)data->chip_data; mask 255 arch/arm/mach-s3c64xx/common.c __raw_writel(mask, S3C64XX_EINT0MASK); mask 260 arch/arm/mach-s3c64xx/common.c u32 mask; mask 262 arch/arm/mach-s3c64xx/common.c mask = __raw_readl(S3C64XX_EINT0MASK); mask 263 arch/arm/mach-s3c64xx/common.c mask &= ~((u32)data->chip_data); mask 264 arch/arm/mach-s3c64xx/common.c __raw_writel(mask, S3C64XX_EINT0MASK); mask 284 arch/arm/mach-s3c64xx/common.c u32 ctrl, mask; mask 330 arch/arm/mach-s3c64xx/common.c mask = 0x7 << shift; mask 333 arch/arm/mach-s3c64xx/common.c ctrl &= ~mask; mask 374 arch/arm/mach-s3c64xx/common.c u32 mask = __raw_readl(S3C64XX_EINT0MASK); mask 377 arch/arm/mach-s3c64xx/common.c status &= ~mask; mask 50 arch/arm/mach-s3c64xx/irq-pm.c u32 mask; mask 75 arch/arm/mach-s3c64xx/irq-pm.c grp->mask = __raw_readl(S3C64XX_EINT12MASK + (i * 4)); mask 96 arch/arm/mach-s3c64xx/irq-pm.c __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); mask 80 arch/arm/mach-sa1100/assabet.c void ASSABET_BCR_frob(unsigned int mask, unsigned int val) mask 82 arch/arm/mach-sa1100/assabet.c unsigned long m = mask, v = val; mask 206 arch/arm/mach-sa1100/assabet.c static void assabet_codec_reset(unsigned mask, int set) mask 214 arch/arm/mach-sa1100/assabet.c codec_nreset &= ~mask; mask 216 arch/arm/mach-sa1100/assabet.c codec_nreset |= mask; mask 68 arch/arm/mach-sa1100/include/mach/assabet.h extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); mask 14 arch/arm/mach-sa1100/include/mach/reset.h static inline void clear_reset_status(unsigned int mask) mask 16 arch/arm/mach-sa1100/include/mach/reset.h RCSR = mask; mask 123 arch/arm/mach-sa1100/neponset.c void neponset_ncr_frob(unsigned int mask, unsigned int val) mask 126 arch/arm/mach-sa1100/neponset.c unsigned long m = mask, v = val; mask 65 arch/arm/mach-shmobile/platsmp-scu.c unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); mask 67 arch/arm/mach-shmobile/platsmp-scu.c if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) mask 62 arch/arm/mach-versatile/versatile_dt.c u32 mask; mask 65 arch/arm/mach-versatile/versatile_dt.c mask = 1; mask 67 arch/arm/mach-versatile/versatile_dt.c mask = 2; mask 69 arch/arm/mach-versatile/versatile_dt.c return readl(versatile_sys_base + VERSATILE_SYS_MCI_OFFSET) & mask; mask 160 arch/arm/mach-vexpress/spc.c u32 mask, reg; mask 165 arch/arm/mach-vexpress/spc.c mask = BIT(cpu); mask 168 arch/arm/mach-vexpress/spc.c mask <<= 4; mask 173 arch/arm/mach-vexpress/spc.c reg |= mask; mask 175 arch/arm/mach-vexpress/spc.c reg &= ~mask; mask 245 arch/arm/mach-vexpress/spc.c u32 mask = standbywfi_cpu_mask(cpu, cluster); mask 253 arch/arm/mach-vexpress/spc.c __func__, STANDBYWFI_STAT, ret, mask); mask 255 arch/arm/mach-vexpress/spc.c return ret & mask; mask 116 arch/arm/mach-vexpress/tc2_pm.c u32 mask = cluster ? mask 120 arch/arm/mach-vexpress/tc2_pm.c return !(readl_relaxed(scc + RESET_CTRL) & mask); mask 177 arch/arm/mach-zynq/slcr.c u32 state, mask; mask 180 arch/arm/mach-zynq/slcr.c mask = 1 << (31 - cpu); mask 182 arch/arm/mach-zynq/slcr.c state |= mask; mask 184 arch/arm/mach-zynq/slcr.c state &= ~mask; mask 120 arch/arm/mm/cache-l2x0-pmu.c u64 prev_count, new_count, mask; mask 127 arch/arm/mm/cache-l2x0-pmu.c mask = GENMASK_ULL(31, 0); mask 128 arch/arm/mm/cache-l2x0-pmu.c local64_add((new_count - prev_count) & mask, &event->count); mask 54 arch/arm/mm/cache-l2x0.c static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) mask 57 arch/arm/mm/cache-l2x0.c while (readl_relaxed(reg) & mask) mask 947 arch/arm/mm/cache-l2x0.c u32 mask = 0, val = 0; mask 1016 arch/arm/mm/cache-l2x0.c mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; mask 1019 arch/arm/mm/cache-l2x0.c *aux_val &= ~mask; mask 1021 arch/arm/mm/cache-l2x0.c *aux_mask &= ~mask; mask 1032 arch/arm/mm/cache-l2x0.c u32 val = 0, mask = 0; mask 1038 arch/arm/mm/cache-l2x0.c mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; mask 1045 arch/arm/mm/cache-l2x0.c mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | mask 1053 arch/arm/mm/cache-l2x0.c mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; mask 1058 arch/arm/mm/cache-l2x0.c mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; mask 1061 arch/arm/mm/cache-l2x0.c mask &= ~L2C_AUX_CTRL_PARITY_ENABLE; mask 1065 arch/arm/mm/cache-l2x0.c mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE; mask 1077 arch/arm/mm/cache-l2x0.c mask |= L2X0_AUX_CTRL_ASSOC_MASK; mask 1081 arch/arm/mm/cache-l2x0.c *aux_val &= ~mask; mask 1083 arch/arm/mm/cache-l2x0.c *aux_mask &= ~mask; mask 1483 arch/arm/mm/cache-l2x0.c u32 mask = AURORA_ACR_REPLACEMENT_MASK; mask 1493 arch/arm/mm/cache-l2x0.c mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; mask 1497 arch/arm/mm/cache-l2x0.c mask |= AURORA_ACR_ECC_EN; mask 1502 arch/arm/mm/cache-l2x0.c mask |= AURORA_ACR_PARITY_EN; mask 1505 arch/arm/mm/cache-l2x0.c mask |= AURORA_ACR_PARITY_EN; mask 1508 arch/arm/mm/cache-l2x0.c *aux_val &= ~mask; mask 1510 arch/arm/mm/cache-l2x0.c *aux_mask &= ~mask; mask 52 arch/arm/mm/context.c cpumask_t *mask) mask 71 arch/arm/mm/context.c cpumask_set_cpu(cpu, mask); mask 222 arch/arm/mm/dma-mapping.c static int __dma_supported(struct device *dev, u64 mask, bool warn) mask 230 arch/arm/mm/dma-mapping.c if (dma_to_pfn(dev, mask) < max_dma_pfn) { mask 233 arch/arm/mm/dma-mapping.c mask, mask 234 arch/arm/mm/dma-mapping.c dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, mask 244 arch/arm/mm/dma-mapping.c u64 mask = (u64)DMA_BIT_MASK(32); mask 247 arch/arm/mm/dma-mapping.c mask = dev->coherent_dma_mask; mask 253 arch/arm/mm/dma-mapping.c if (mask == 0) { mask 258 arch/arm/mm/dma-mapping.c if (!__dma_supported(dev, mask, true)) mask 262 arch/arm/mm/dma-mapping.c return mask; mask 691 arch/arm/mm/dma-mapping.c u64 mask = get_coherent_dma_mask(dev); mask 707 arch/arm/mm/dma-mapping.c u64 limit = (mask + 1) & ~mask; mask 710 arch/arm/mm/dma-mapping.c size, mask); mask 715 arch/arm/mm/dma-mapping.c if (!mask) mask 723 arch/arm/mm/dma-mapping.c if (mask < 0xffffffffULL) mask 1096 arch/arm/mm/dma-mapping.c int arm_dma_supported(struct device *dev, u64 mask) mask 1098 arch/arm/mm/dma-mapping.c return __dma_supported(dev, mask, false); mask 57 arch/arm/mm/dump.c u64 mask; mask 67 arch/arm/mm/dump.c .mask = L_PTE_USER, mask 72 arch/arm/mm/dump.c .mask = L_PTE_RDONLY, mask 78 arch/arm/mm/dump.c .mask = L_PTE_XN, mask 84 arch/arm/mm/dump.c .mask = L_PTE_SHARED, mask 89 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 93 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 97 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 101 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 106 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 111 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 115 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 120 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 125 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 129 arch/arm/mm/dump.c .mask = L_PTE_MT_MASK, mask 138 arch/arm/mm/dump.c .mask = PMD_SECT_USER, mask 142 arch/arm/mm/dump.c .mask = L_PMD_SECT_RDONLY | PMD_SECT_AP2, mask 149 arch/arm/mm/dump.c .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 154 arch/arm/mm/dump.c .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 158 arch/arm/mm/dump.c .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 162 arch/arm/mm/dump.c .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 168 arch/arm/mm/dump.c .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 173 arch/arm/mm/dump.c .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 177 arch/arm/mm/dump.c .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 181 arch/arm/mm/dump.c .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE, mask 186 arch/arm/mm/dump.c .mask = PMD_SECT_XN, mask 192 arch/arm/mm/dump.c .mask = PMD_SECT_S, mask 202 arch/arm/mm/dump.c u64 mask; mask 227 arch/arm/mm/dump.c if ((st->current_prot & bits->mask) == bits->val) mask 241 arch/arm/mm/dump.c if ((st->current_prot & pg_level[st->level].ro_bit->mask) == mask 244 arch/arm/mm/dump.c if ((st->current_prot & pg_level[st->level].nx_bit->mask) == mask 258 arch/arm/mm/dump.c u64 prot = val & pg_level[level].mask; mask 410 arch/arm/mm/dump.c pg_level[i].mask |= pg_level[i].bits[j].mask; mask 192 arch/arm/mm/fault.c unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; mask 195 arch/arm/mm/fault.c mask = VM_WRITE; mask 197 arch/arm/mm/fault.c mask = VM_EXEC; mask 199 arch/arm/mm/fault.c return vma->vm_flags & mask ? false : true; mask 44 arch/arm/mm/init.c unsigned long __init __clear_cr(unsigned long mask) mask 46 arch/arm/mm/init.c cr_alignment = cr_alignment & ~mask; mask 511 arch/arm/mm/init.c pmdval_t mask; mask 525 arch/arm/mm/init.c .mask = ~PMD_SECT_XN, mask 533 arch/arm/mm/init.c .mask = ~PMD_SECT_XN, mask 541 arch/arm/mm/init.c .mask = ~PMD_SECT_XN, mask 553 arch/arm/mm/init.c .mask = ~(L_PMD_SECT_RDONLY | PMD_SECT_AP2), mask 556 arch/arm/mm/init.c .mask = ~(PMD_SECT_APX | PMD_SECT_AP_WRITE), mask 568 arch/arm/mm/init.c static inline void section_update(unsigned long addr, pmdval_t mask, mask 576 arch/arm/mm/init.c pmd[0] = __pmd((pmd_val(pmd[0]) & mask) | prot); mask 579 arch/arm/mm/init.c pmd[1] = __pmd((pmd_val(pmd[1]) & mask) | prot); mask 581 arch/arm/mm/init.c pmd[0] = __pmd((pmd_val(pmd[0]) & mask) | prot); mask 617 arch/arm/mm/init.c section_update(addr, perms[i].mask, mask 99 arch/arm/mm/mm.h unsigned long __clear_cr(unsigned long mask); mask 125 arch/arm/mm/proc-v7-bugs.c u32 mask, const char *msg) mask 131 arch/arm/mm/proc-v7-bugs.c if ((aux_cr & mask) != mask) { mask 198 arch/arm/nwfpe/fpopcode.h #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask)) mask 50 arch/arm/plat-omap/debug-leds.c u16 mask; mask 87 arch/arm/plat-omap/debug-leds.c reg |= led->mask; mask 89 arch/arm/plat-omap/debug-leds.c reg &= ~led->mask; mask 99 arch/arm/plat-omap/debug-leds.c return (reg & led->mask) ? LED_FULL : LED_OFF; mask 125 arch/arm/plat-omap/debug-leds.c led->mask = BIT(i); mask 500 arch/arm/plat-orion/gpio.c u32 mask = d->mask; mask 503 arch/arm/plat-orion/gpio.c reg_val = irq_reg_readl(gc, ct->regs.mask); mask 504 arch/arm/plat-orion/gpio.c reg_val |= mask; mask 505 arch/arm/plat-orion/gpio.c irq_reg_writel(gc, reg_val, ct->regs.mask); mask 513 arch/arm/plat-orion/gpio.c u32 mask = d->mask; mask 517 arch/arm/plat-orion/gpio.c reg_val = irq_reg_readl(gc, ct->regs.mask); mask 518 arch/arm/plat-orion/gpio.c reg_val &= ~mask; mask 519 arch/arm/plat-orion/gpio.c irq_reg_writel(gc, reg_val, ct->regs.mask); mask 590 arch/arm/plat-orion/gpio.c ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; mask 598 arch/arm/plat-orion/gpio.c ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; mask 184 arch/arm/plat-orion/pcie.c u32 mask; mask 203 arch/arm/plat-orion/pcie.c mask = readl(base + PCIE_MASK_OFF); mask 204 arch/arm/plat-orion/pcie.c mask |= 0x0f000000; mask 205 arch/arm/plat-orion/pcie.c writel(mask, base + PCIE_MASK_OFF); mask 35 arch/arm/plat-samsung/include/plat/cpu.h #define IS_SAMSUNG_CPU(name, id, mask) \ mask 38 arch/arm/plat-samsung/include/plat/cpu.h return ((samsung_cpu_id & mask) == (id & mask)); \ mask 127 arch/arm/plat-samsung/pm-gpio.c u32 gpcon, old, new, mask; mask 139 arch/arm/plat-samsung/pm-gpio.c for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { mask 140 arch/arm/plat-samsung/pm-gpio.c old = (old_gpcon & mask) >> nr; mask 141 arch/arm/plat-samsung/pm-gpio.c new = (gps_gpcon & mask) >> nr; mask 166 arch/arm/plat-samsung/pm-gpio.c change_mask |= mask; mask 204 arch/arm/plat-samsung/pm-gpio.c u32 old, new, mask; mask 208 arch/arm/plat-samsung/pm-gpio.c for (nr = 0, mask = 0x0f; nr < 16; nr += 4, mask <<= 4) { mask 209 arch/arm/plat-samsung/pm-gpio.c old = (old_gpcon & mask) >> nr; mask 210 arch/arm/plat-samsung/pm-gpio.c new = (gps_gpcon & mask) >> nr; mask 235 arch/arm/plat-samsung/pm-gpio.c change_mask |= mask; mask 246 arch/arm/plat-samsung/pm-gpio.c u32 gpcon, mask; mask 248 arch/arm/plat-samsung/pm-gpio.c mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); mask 250 arch/arm/plat-samsung/pm-gpio.c gpcon = old_gpcon & ~mask; mask 251 arch/arm/plat-samsung/pm-gpio.c gpcon |= gps_gpcon & mask; mask 62 arch/arm/plat-samsung/pm.c #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) mask 18 arch/arm/plat-samsung/wakeup-mask.c const struct samsung_wakeup_mask *mask, int nr_mask) mask 25 arch/arm/plat-samsung/wakeup-mask.c for (; nr_mask > 0; nr_mask--, mask++) { mask 26 arch/arm/plat-samsung/wakeup-mask.c if (mask->irq == NO_WAKEUP_IRQ) { mask 27 arch/arm/plat-samsung/wakeup-mask.c val |= mask->bit; mask 31 arch/arm/plat-samsung/wakeup-mask.c data = irq_get_irq_data(mask->irq); mask 35 arch/arm/plat-samsung/wakeup-mask.c val &= ~mask->bit; mask 37 arch/arm/plat-samsung/wakeup-mask.c val |= mask->bit; mask 95 arch/arm/probes/decode-arm.c unsigned long mask = 0xf8ff03df; /* Mask out execution state */ mask 96 arch/arm/probes/decode-arm.c regs->uregs[rd] = regs->ARM_cpsr & mask; mask 261 arch/arm/probes/decode.c probes_opcode_t mask = 0xf; /* Start at least significant nibble */ mask 263 arch/arm/probes/decode.c for (; regs != 0; regs >>= 4, mask <<= 4) { mask 284 arch/arm/probes/decode.c if ((insn ^ 0xdddddddd) & mask) mask 290 arch/arm/probes/decode.c if ((insn ^ 0xffffffff) & mask) mask 296 arch/arm/probes/decode.c if (((insn ^ 0xdddddddd) & mask) == 0) mask 303 arch/arm/probes/decode.c if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0) mask 314 arch/arm/probes/decode.c if (((insn ^ 0xffffffff) & mask) == 0) mask 320 arch/arm/probes/decode.c insn &= ~mask; mask 321 arch/arm/probes/decode.c insn |= new_bits & mask; mask 455 arch/arm/probes/decode.c if (!matched && (insn & h->mask.bits) != h->value.bits) mask 52 arch/arm/probes/decode.h const unsigned long mask = 0x06001c00; /* Mask ITSTATE<4:0> */ mask 53 arch/arm/probes/decode.h unsigned long it = cpsr & mask; mask 56 arch/arm/probes/decode.h it &= mask; mask 57 arch/arm/probes/decode.h cpsr &= ~mask; mask 48 arch/arm/probes/kprobes/actions-thumb.c unsigned long mask = 0xf8ff03df; /* Mask out execution state */ mask 49 arch/arm/probes/kprobes/actions-thumb.c regs->uregs[rd] = regs->ARM_cpsr & mask; mask 623 arch/arm/probes/kprobes/test-core.c message, h->mask.bits, h->value.bits); mask 638 arch/arm/probes/kprobes/test-core.c if (h->value.bits & ~h->mask.bits) mask 641 arch/arm/probes/kprobes/test-core.c if ((h->mask.bits & a->parent_mask) != a->parent_mask) mask 650 arch/arm/probes/kprobes/test-core.c args2.parent_mask = h->mask.bits; mask 860 arch/arm/probes/kprobes/test-core.c if ((insn & h->mask.bits) != h->value.bits) mask 895 arch/arm/probes/kprobes/test-core.c u32 mask = entry->header->mask.bits; mask 900 arch/arm/probes/kprobes/test-core.c mask, value, entry->regs); mask 905 arch/arm/probes/kprobes/test-core.c mask, value); mask 1054 arch/arm/probes/kprobes/test-core.c unsigned mask = x / 7 + 2; /* ITSTATE<4:0>, bits reversed */ mask 1056 arch/arm/probes/kprobes/test-core.c if (mask > 0x1f) { mask 1059 arch/arm/probes/kprobes/test-core.c mask = 0x4; mask 1065 arch/arm/probes/kprobes/test-core.c cpsr |= (mask & 0x1) << 12; /* ITSTATE<4> */ mask 1066 arch/arm/probes/kprobes/test-core.c cpsr |= (mask & 0x2) << 10; /* ITSTATE<3> */ mask 1067 arch/arm/probes/kprobes/test-core.c cpsr |= (mask & 0x4) << 8; /* ITSTATE<2> */ mask 1068 arch/arm/probes/kprobes/test-core.c cpsr |= (mask & 0x8) << 23; /* ITSTATE<1> */ mask 1069 arch/arm/probes/kprobes/test-core.c cpsr |= (mask & 0x10) << 21; /* ITSTATE<0> */ mask 402 arch/arm/probes/kprobes/test-core.h #define TEST_RMASKED(code1, reg, mask, code2) \ mask 404 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG_MASKED(reg, mask) \ mask 21 arch/arm/probes/uprobes/actions-arm.c probes_opcode_t mask; mask 49 arch/arm/probes/uprobes/actions-arm.c mask = 0xf; mask 51 arch/arm/probes/uprobes/actions-arm.c for (; regs; regs >>= 4, mask <<= 4, free <<= 4, temp >>= 4) { mask 58 arch/arm/probes/uprobes/actions-arm.c insn &= ~mask; mask 59 arch/arm/probes/uprobes/actions-arm.c insn |= free & mask; mask 47 arch/arm64/include/asm/barrier.h unsigned long mask; mask 52 arch/arm64/include/asm/barrier.h : "=r" (mask) mask 57 arch/arm64/include/asm/barrier.h return mask; mask 91 arch/arm64/include/asm/debug-monitors.h u16 mask; /* These bits are ignored when comparing with imm */ mask 259 arch/arm64/include/asm/insn.h #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ mask 262 arch/arm64/include/asm/insn.h BUILD_BUG_ON(~(mask) & (val)); \ mask 263 arch/arm64/include/asm/insn.h return (code & (mask)) == (val); \ mask 472 arch/arm64/include/asm/kvm_host.h void force_vm_exit(const cpumask_t *mask); mask 407 arch/arm64/include/asm/pgtable.h #define __pgprot_modify(prot,mask,bits) \ mask 408 arch/arm64/include/asm/pgtable.h __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) mask 660 arch/arm64/include/asm/pgtable.h const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | mask 665 arch/arm64/include/asm/pgtable.h pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); mask 98 arch/arm64/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 101 arch/arm64/include/asm/smp.h extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask); mask 103 arch/arm64/include/asm/smp.h static inline void arch_send_wakeup_ipi_mask(const struct cpumask *mask) mask 16 arch/arm64/include/asm/smp_plat.h u64 mask; mask 36 arch/arm64/include/asm/vdso/vsyscall.h vdata[CS_HRES_COARSE].mask = VDSO_PRECISION_MASK; mask 37 arch/arm64/include/asm/vdso/vsyscall.h vdata[CS_RAW].mask = VDSO_PRECISION_MASK; mask 23 arch/arm64/include/asm/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 24 arch/arm64/include/asm/word-at-a-time.h *bits = mask; mask 25 arch/arm64/include/asm/word-at-a-time.h return mask; mask 36 arch/arm64/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 38 arch/arm64/include/asm/word-at-a-time.h return fls64(mask) >> 3; mask 41 arch/arm64/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 108 arch/arm64/kernel/asm-offsets.c DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask)); mask 62 arch/arm64/kernel/cpu_errata.c u64 mask = arm64_ftr_reg_ctrel0.strict_mask; mask 63 arch/arm64/kernel/cpu_errata.c u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; mask 84 arch/arm64/kernel/cpu_errata.c ctr_raw = read_cpuid_cachetype() & mask; mask 85 arch/arm64/kernel/cpu_errata.c ctr_real = read_cpuid_effective_cachetype() & mask; mask 93 arch/arm64/kernel/cpu_errata.c u64 mask = arm64_ftr_reg_ctrel0.strict_mask; mask 97 arch/arm64/kernel/cpu_errata.c if ((read_cpuid_cachetype() & mask) != mask 98 arch/arm64/kernel/cpu_errata.c (arm64_ftr_reg_ctrel0.sys_val & mask)) mask 464 arch/arm64/kernel/cpufeature.c u64 mask = arm64_ftr_mask(ftrp); mask 466 arch/arm64/kernel/cpufeature.c reg &= ~mask; mask 467 arch/arm64/kernel/cpufeature.c reg |= (ftr_val << ftrp->shift) & mask; mask 315 arch/arm64/kernel/debug-monitors.c if ((comment & ~hook->mask) == hook->imm) mask 200 arch/arm64/kernel/hibernate.c void *(*allocator)(gfp_t mask), mask 201 arch/arm64/kernel/hibernate.c gfp_t mask) mask 209 arch/arm64/kernel/hibernate.c unsigned long dst = (unsigned long)allocator(mask); mask 219 arch/arm64/kernel/hibernate.c trans_pgd = allocator(mask); mask 227 arch/arm64/kernel/hibernate.c pudp = allocator(mask); mask 237 arch/arm64/kernel/hibernate.c pmdp = allocator(mask); mask 247 arch/arm64/kernel/hibernate.c ptep = allocator(mask); mask 231 arch/arm64/kernel/insn.c u32 mask; mask 236 arch/arm64/kernel/insn.c mask = BIT(26) - 1; mask 240 arch/arm64/kernel/insn.c mask = BIT(19) - 1; mask 244 arch/arm64/kernel/insn.c mask = BIT(16) - 1; mask 248 arch/arm64/kernel/insn.c mask = BIT(14) - 1; mask 252 arch/arm64/kernel/insn.c mask = BIT(12) - 1; mask 256 arch/arm64/kernel/insn.c mask = BIT(9) - 1; mask 260 arch/arm64/kernel/insn.c mask = BIT(7) - 1; mask 265 arch/arm64/kernel/insn.c mask = BIT(6) - 1; mask 269 arch/arm64/kernel/insn.c mask = BIT(6) - 1; mask 273 arch/arm64/kernel/insn.c mask = 1; mask 280 arch/arm64/kernel/insn.c *maskp = mask; mask 295 arch/arm64/kernel/insn.c u32 immlo, immhi, mask; mask 304 arch/arm64/kernel/insn.c mask = ADR_IMM_SIZE - 1; mask 307 arch/arm64/kernel/insn.c if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) { mask 314 arch/arm64/kernel/insn.c return (insn >> shift) & mask; mask 320 arch/arm64/kernel/insn.c u32 immlo, immhi, mask; mask 333 arch/arm64/kernel/insn.c mask = ((ADR_IMM_LOMASK << ADR_IMM_LOSHIFT) | mask 337 arch/arm64/kernel/insn.c if (aarch64_get_imm_shift_mask(type, &mask, &shift) < 0) { mask 345 arch/arm64/kernel/insn.c insn &= ~(mask << shift); mask 346 arch/arm64/kernel/insn.c insn |= (imm & mask) << shift; mask 904 arch/arm64/kernel/insn.c u32 mask; mask 923 arch/arm64/kernel/insn.c mask = GENMASK(4, 0); mask 927 arch/arm64/kernel/insn.c mask = GENMASK(5, 0); mask 934 arch/arm64/kernel/insn.c if (immr & ~mask) { mask 938 arch/arm64/kernel/insn.c if (imms & ~mask) { mask 1511 arch/arm64/kernel/insn.c u64 mask = ~0UL; mask 1543 arch/arm64/kernel/insn.c mask = emask; mask 1550 arch/arm64/kernel/insn.c imm &= mask; mask 1579 arch/arm64/kernel/insn.c imm |= ~mask; mask 76 arch/arm64/kernel/kaslr.c u64 seed, offset, mask, module_range; mask 123 arch/arm64/kernel/kaslr.c mask = ((1UL << (VA_BITS_MIN - 2)) - 1) & ~(SZ_2M - 1); mask 124 arch/arm64/kernel/kaslr.c offset = BIT(VA_BITS_MIN - 3) + (seed & mask); mask 40 arch/arm64/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 42 arch/arm64/kernel/perf_regs.c if (!mask || mask & REG_RESERVED) mask 973 arch/arm64/kernel/ptrace.c unsigned long mask = ptrauth_user_pac_mask(); mask 975 arch/arm64/kernel/ptrace.c .data_mask = mask, mask 976 arch/arm64/kernel/ptrace.c .insn_mask = mask, mask 115 arch/arm64/kernel/setup.c u64 mask = 0; mask 121 arch/arm64/kernel/setup.c mask |= (cpu_logical_map(i) ^ cpu_logical_map(0)); mask 122 arch/arm64/kernel/setup.c pr_debug("mask of set bits %#llx\n", mask); mask 128 arch/arm64/kernel/setup.c affinity = MPIDR_AFFINITY_LEVEL(mask, i); mask 154 arch/arm64/kernel/setup.c mpidr_hash.mask = mask; mask 161 arch/arm64/kernel/setup.c mpidr_hash.mask, mask 805 arch/arm64/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 807 arch/arm64/kernel/smp.c smp_cross_call(mask, IPI_CALL_FUNC); mask 816 arch/arm64/kernel/smp.c void arch_send_wakeup_ipi_mask(const struct cpumask *mask) mask 818 arch/arm64/kernel/smp.c smp_cross_call(mask, IPI_WAKEUP); mask 952 arch/arm64/kernel/smp.c void tick_broadcast(const struct cpumask *mask) mask 954 arch/arm64/kernel/smp.c smp_cross_call(mask, IPI_TIMER); mask 974 arch/arm64/kernel/smp.c cpumask_t mask; mask 976 arch/arm64/kernel/smp.c cpumask_copy(&mask, cpu_online_mask); mask 977 arch/arm64/kernel/smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 981 arch/arm64/kernel/smp.c smp_cross_call(&mask, IPI_CPU_STOP); mask 1000 arch/arm64/kernel/smp.c cpumask_t mask; mask 1021 arch/arm64/kernel/smp.c cpumask_copy(&mask, cpu_online_mask); mask 1022 arch/arm64/kernel/smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 1027 arch/arm64/kernel/smp.c smp_cross_call(&mask, IPI_CPU_CRASH_STOP); mask 1036 arch/arm64/kernel/smp.c cpumask_pr_args(&mask)); mask 1023 arch/arm64/kernel/traps.c .mask = KASAN_BRK_MASK, mask 858 arch/arm64/kvm/sys_regs.c u64 val, mask; mask 866 arch/arm64/kvm/sys_regs.c mask = kvm_pmu_valid_counter_mask(vcpu); mask 868 arch/arm64/kvm/sys_regs.c val = p->regval & mask; mask 880 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; mask 889 arch/arm64/kvm/sys_regs.c u64 mask = kvm_pmu_valid_counter_mask(vcpu); mask 900 arch/arm64/kvm/sys_regs.c u64 val = p->regval & mask; mask 909 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; mask 918 arch/arm64/kvm/sys_regs.c u64 mask = kvm_pmu_valid_counter_mask(vcpu); mask 929 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); mask 932 arch/arm64/kvm/sys_regs.c __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); mask 934 arch/arm64/kvm/sys_regs.c p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; mask 943 arch/arm64/kvm/sys_regs.c u64 mask; mask 954 arch/arm64/kvm/sys_regs.c mask = kvm_pmu_valid_counter_mask(vcpu); mask 955 arch/arm64/kvm/sys_regs.c kvm_pmu_software_increment(vcpu, p->regval & mask); mask 89 arch/arm64/mm/dump.c u64 mask; mask 97 arch/arm64/mm/dump.c .mask = PTE_VALID, mask 102 arch/arm64/mm/dump.c .mask = PTE_USER, mask 107 arch/arm64/mm/dump.c .mask = PTE_RDONLY, mask 112 arch/arm64/mm/dump.c .mask = PTE_PXN, mask 117 arch/arm64/mm/dump.c .mask = PTE_SHARED, mask 122 arch/arm64/mm/dump.c .mask = PTE_AF, mask 127 arch/arm64/mm/dump.c .mask = PTE_NG, mask 132 arch/arm64/mm/dump.c .mask = PTE_CONT, mask 137 arch/arm64/mm/dump.c .mask = PTE_TABLE_BIT, mask 142 arch/arm64/mm/dump.c .mask = PTE_UXN, mask 146 arch/arm64/mm/dump.c .mask = PTE_ATTRINDX_MASK, mask 150 arch/arm64/mm/dump.c .mask = PTE_ATTRINDX_MASK, mask 154 arch/arm64/mm/dump.c .mask = PTE_ATTRINDX_MASK, mask 158 arch/arm64/mm/dump.c .mask = PTE_ATTRINDX_MASK, mask 162 arch/arm64/mm/dump.c .mask = PTE_ATTRINDX_MASK, mask 172 arch/arm64/mm/dump.c u64 mask; mask 204 arch/arm64/mm/dump.c if ((st->current_prot & bits->mask) == bits->val) mask 247 arch/arm64/mm/dump.c u64 prot = val & pg_level[level].mask; mask 383 arch/arm64/mm/dump.c pg_level[i].mask |= pg_level[i].bits[j].mask; mask 123 arch/arm64/mm/mmu.c static const pteval_t mask = PTE_PXN | PTE_RDONLY | PTE_WRITE | PTE_NG; mask 137 arch/arm64/mm/mmu.c return ((old ^ new) & ~mask) == 0; mask 52 arch/c6x/include/asm/special_insns.h #define set_iexcept(mask) set_creg(IERR, (mask)) mask 18 arch/c6x/kernel/module.c long mask = (1 << maskbits) - 1; mask 23 arch/c6x/kernel/module.c opcode &= ~(mask << shift); mask 24 arch/c6x/kernel/module.c opcode |= ((delta & mask) << shift); mask 98 arch/c6x/kernel/signal.c unsigned long mask) mask 102 arch/c6x/kernel/signal.c err |= __put_user(mask, &sc->sc_mask); mask 35 arch/c6x/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 43 arch/c6x/platforms/dscr.c u32 mask; mask 266 arch/c6x/platforms/dscr.c if (r->mask == 0) mask 273 arch/c6x/platforms/dscr.c dscr_write(r->reg, val | r->mask); mask 275 arch/c6x/platforms/dscr.c dscr_write(r->reg, val & ~(r->mask)); mask 359 arch/c6x/platforms/dscr.c dscr.rmii_resets[i].mask = be32_to_cpup(p++); mask 311 arch/c6x/platforms/megamod-pic.c u32 mask; mask 314 arch/c6x/platforms/megamod-pic.c mask = soc_readl(&mm_pic->regs->mexpflag[i]); mask 315 arch/c6x/platforms/megamod-pic.c if (mask) { mask 316 arch/c6x/platforms/megamod-pic.c bit = __ffs(mask); mask 16 arch/csky/include/asm/smp.h void arch_send_call_function_ipi_mask(struct cpumask *mask); mask 20 arch/csky/include/asm/smp.h void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq); mask 21 arch/csky/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 23 arch/csky/kernel/perf_regs.c if (!mask || mask & REG_RESERVED) mask 62 arch/csky/kernel/smp.c static void (*send_arch_ipi)(const struct cpumask *mask); mask 65 arch/csky/kernel/smp.c void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq) mask 86 arch/csky/kernel/smp.c void arch_send_call_function_ipi_mask(struct cpumask *mask) mask 88 arch/csky/kernel/smp.c send_ipi_message(mask, IPI_CALL_FUNC); mask 166 arch/csky/kernel/smp.c unsigned long mask = 1 << cpu; mask 181 arch/csky/kernel/smp.c if (mask & mfcr("cr<29, 0>")) { mask 185 arch/csky/kernel/smp.c mask |= mfcr("cr<29, 0>"); mask 186 arch/csky/kernel/smp.c mtcr("cr<29, 0>", mask); mask 134 arch/h8300/kernel/signal.c unsigned long mask) mask 148 arch/h8300/kernel/signal.c err |= __put_user(mask, &sc->sc_mask); mask 26 arch/hexagon/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 238 arch/hexagon/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 240 arch/hexagon/kernel/smp.c send_ipi(mask, IPI_CALL_FUNC); mask 71 arch/hexagon/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 89 arch/hexagon/kernel/time.c static void broadcast(const struct cpumask *mask) mask 91 arch/hexagon/kernel/time.c send_ipi(mask, IPI_TIMER); mask 88 arch/hexagon/lib/checksum.c int i, start, mid, end, mask; mask 97 arch/hexagon/lib/checksum.c mask = 0x7fffffffUL >> HEXAGON_R_cl0_R(len); mask 98 arch/hexagon/lib/checksum.c start = start & mask ; mask 536 arch/ia64/hp/common/sba_iommu.c unsigned long mask, base_mask; mask 539 arch/ia64/hp/common/sba_iommu.c mask = base_mask << bitshiftcnt; mask 544 arch/ia64/hp/common/sba_iommu.c DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); mask 545 arch/ia64/hp/common/sba_iommu.c ASSERT(0 != mask); mask 546 arch/ia64/hp/common/sba_iommu.c for (; mask ; mask <<= o, bitshiftcnt += o) { mask 551 arch/ia64/hp/common/sba_iommu.c if ((0 == ((*res_ptr) & mask)) && !ret) { mask 552 arch/ia64/hp/common/sba_iommu.c *res_ptr |= mask; /* mark resources busy! */ mask 560 arch/ia64/hp/common/sba_iommu.c mask = base_mask; mask 2058 arch/ia64/hp/common/sba_iommu.c static int sba_dma_supported (struct device *dev, u64 mask) mask 2061 arch/ia64/hp/common/sba_iommu.c return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL); mask 83 arch/ia64/include/asm/bitops.h __u32 mask, old, new; mask 88 arch/ia64/include/asm/bitops.h mask = ~(1 << (nr & 31)); mask 92 arch/ia64/include/asm/bitops.h new = old & mask; mask 107 arch/ia64/include/asm/bitops.h __u32 mask, old, new; mask 112 arch/ia64/include/asm/bitops.h mask = ~(1 << (nr & 31)); mask 116 arch/ia64/include/asm/bitops.h new = old & mask; mask 257 arch/ia64/include/asm/bitops.h __u32 mask, old, new; mask 262 arch/ia64/include/asm/bitops.h mask = ~(1 << (nr & 31)); mask 266 arch/ia64/include/asm/bitops.h new = old & mask; mask 268 arch/ia64/include/asm/bitops.h return (old & ~mask) != 0; mask 18 arch/ia64/include/asm/patch.h extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */ mask 600 arch/ia64/include/asm/processor.h __u64 mask = 1UL << bit; mask 602 arch/ia64/include/asm/processor.h *unat = (*unat & ~mask) | (nat << bit); mask 130 arch/ia64/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 498 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory") mask 499 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory") mask 500 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory") mask 501 arch/ia64/include/uapi/asm/gcc_intrin.h #define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory") mask 34 arch/ia64/kernel/cyclone.c .mask = (1LL << 40) - 1, mask 358 arch/ia64/kernel/efi.c u64 vaddr, mask; mask 378 arch/ia64/kernel/efi.c mask = ~((1 << KERNEL_TR_PAGE_SHIFT) - 1); mask 394 arch/ia64/kernel/efi.c if ((vaddr & mask) == (KERNEL_START & mask)) { mask 404 arch/ia64/kernel/efi.c mask = ~((1 << IA64_GRANULE_SHIFT) - 1); mask 410 arch/ia64/kernel/efi.c vaddr & mask, (vaddr & mask) + IA64_GRANULE_SIZE); mask 214 arch/ia64/kernel/iosapic.c set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) mask 243 arch/ia64/kernel/iosapic.c ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) | mask 324 arch/ia64/kernel/iosapic.c iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask, mask 337 arch/ia64/kernel/iosapic.c cpu = cpumask_first_and(cpu_online_mask, mask); mask 714 arch/ia64/kernel/iosapic.c int irq, mask = 1, err; mask 765 arch/ia64/kernel/iosapic.c mask = 0; mask 766 arch/ia64/kernel/iosapic.c set_rte(gsi, irq, dest, mask); mask 862 arch/ia64/kernel/iosapic.c int irq, vector, mask = 0; mask 887 arch/ia64/kernel/iosapic.c mask = 1; mask 905 arch/ia64/kernel/iosapic.c set_rte(gsi, irq, dest, mask); mask 107 arch/ia64/kernel/irq_ia64.c cpumask_t mask; mask 110 arch/ia64/kernel/irq_ia64.c cpumask_and(&mask, &domain, cpu_online_mask); mask 111 arch/ia64/kernel/irq_ia64.c if (cpumask_empty(&mask)) mask 116 arch/ia64/kernel/irq_ia64.c cpumask_and(&mask, &domain, &vector_table[vector]); mask 117 arch/ia64/kernel/irq_ia64.c if (!cpumask_empty(&mask)) mask 126 arch/ia64/kernel/irq_ia64.c cpumask_t mask; mask 133 arch/ia64/kernel/irq_ia64.c cpumask_and(&mask, &domain, cpu_online_mask); mask 134 arch/ia64/kernel/irq_ia64.c if (cpumask_empty(&mask)) mask 140 arch/ia64/kernel/irq_ia64.c for_each_cpu(cpu, &mask) mask 117 arch/ia64/kernel/msi_ia64.c const struct cpumask *mask, bool force) mask 122 arch/ia64/kernel/msi_ia64.c int cpu = cpumask_first_and(mask, cpu_online_mask); mask 135 arch/ia64/kernel/msi_ia64.c cpumask_copy(irq_data_get_affinity_mask(data), mask); mask 45 arch/ia64/kernel/patch.c ia64_patch (u64 insn_addr, u64 mask, u64 val) mask 54 arch/ia64/kernel/patch.c m1 = mask << (shift - 64); mask 57 arch/ia64/kernel/patch.c m0 = mask << shift; m1 = mask >> (64 - shift); mask 223 arch/ia64/kernel/patch.c u64 ip, mask, imm; mask 226 arch/ia64/kernel/patch.c mask = (0x3fUL << 27) | (0x7f << 13); mask 231 arch/ia64/kernel/patch.c ia64_patch(ip, mask, imm); mask 130 arch/ia64/kernel/perfmon.c #define CTX_USED_PMD(ctx, mask) (ctx)->ctx_used_pmds[0] |= (mask) mask 133 arch/ia64/kernel/perfmon.c #define CTX_USED_MONITOR(ctx, mask) (ctx)->ctx_used_monitors[0] |= (mask) mask 258 arch/ia64/kernel/perfmon.c unsigned long mask; /* mask for random-number generator */ mask 881 arch/ia64/kernel/perfmon.c unsigned long mask, val, ovfl_mask; mask 906 arch/ia64/kernel/perfmon.c mask = ctx->ctx_used_pmds[0]; mask 907 arch/ia64/kernel/perfmon.c for (i = 0; mask; i++, mask>>=1) { mask 909 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0) continue; mask 933 arch/ia64/kernel/perfmon.c mask = ctx->ctx_used_monitors[0] >> PMU_FIRST_COUNTER; mask 934 arch/ia64/kernel/perfmon.c for(i= PMU_FIRST_COUNTER; mask; i++, mask>>=1) { mask 935 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0UL) continue; mask 955 arch/ia64/kernel/perfmon.c unsigned long mask, ovfl_mask; mask 992 arch/ia64/kernel/perfmon.c mask = ctx->ctx_used_pmds[0]; mask 993 arch/ia64/kernel/perfmon.c for (i = 0; mask; i++, mask>>=1) { mask 995 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0) continue; mask 1017 arch/ia64/kernel/perfmon.c mask = ctx->ctx_used_monitors[0] >> PMU_FIRST_COUNTER; mask 1018 arch/ia64/kernel/perfmon.c for(i= PMU_FIRST_COUNTER; mask; i++, mask>>=1) { mask 1019 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0UL) continue; mask 1048 arch/ia64/kernel/perfmon.c pfm_save_pmds(unsigned long *pmds, unsigned long mask) mask 1054 arch/ia64/kernel/perfmon.c for (i=0; mask; i++, mask>>=1) { mask 1055 arch/ia64/kernel/perfmon.c if (mask & 0x1) pmds[i] = ia64_get_pmd(i); mask 1063 arch/ia64/kernel/perfmon.c pfm_restore_pmds(unsigned long *pmds, unsigned long mask) mask 1068 arch/ia64/kernel/perfmon.c for (i=0; mask; i++, mask>>=1) { mask 1069 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0) continue; mask 1083 arch/ia64/kernel/perfmon.c unsigned long mask = ctx->ctx_all_pmds[0]; mask 1087 arch/ia64/kernel/perfmon.c DPRINT(("mask=0x%lx\n", mask)); mask 1089 arch/ia64/kernel/perfmon.c for (i=0; mask; i++, mask>>=1) { mask 1118 arch/ia64/kernel/perfmon.c unsigned long mask = ctx->ctx_all_pmcs[0]; mask 1121 arch/ia64/kernel/perfmon.c DPRINT(("mask=0x%lx\n", mask)); mask 1123 arch/ia64/kernel/perfmon.c for (i=0; mask; i++, mask>>=1) { mask 1133 arch/ia64/kernel/perfmon.c pfm_restore_pmcs(unsigned long *pmcs, unsigned long mask) mask 1137 arch/ia64/kernel/perfmon.c for (i=0; mask; i++, mask>>=1) { mask 1138 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0) continue; mask 1607 arch/ia64/kernel/perfmon.c __poll_t mask = 0; mask 1628 arch/ia64/kernel/perfmon.c mask = EPOLLIN | EPOLLRDNORM; mask 1632 arch/ia64/kernel/perfmon.c DPRINT(("pfm_poll ctx_fd=%d mask=0x%x\n", ctx->ctx_fd, mask)); mask 1634 arch/ia64/kernel/perfmon.c return mask; mask 2663 arch/ia64/kernel/perfmon.c unsigned long new_seed, old_seed = reg->seed, mask = reg->mask; mask 2668 arch/ia64/kernel/perfmon.c val -= (old_seed & mask); /* counter values are negative numbers! */ mask 2669 arch/ia64/kernel/perfmon.c if ((mask >> 32) != 0) mask 2681 arch/ia64/kernel/perfmon.c unsigned long mask = ovfl_regs[0]; mask 2689 arch/ia64/kernel/perfmon.c mask >>= PMU_FIRST_COUNTER; mask 2690 arch/ia64/kernel/perfmon.c for(i = PMU_FIRST_COUNTER; mask; i++, mask >>= 1) { mask 2692 arch/ia64/kernel/perfmon.c if ((mask & 0x1UL) == 0UL) continue; mask 2717 arch/ia64/kernel/perfmon.c unsigned long mask = ovfl_regs[0]; mask 2732 arch/ia64/kernel/perfmon.c mask >>= PMU_FIRST_COUNTER; mask 2733 arch/ia64/kernel/perfmon.c for(i = PMU_FIRST_COUNTER; mask; i++, mask >>= 1) { mask 2735 arch/ia64/kernel/perfmon.c if ((mask & 0x1UL) == 0UL) continue; mask 3106 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[cnum].mask = req->reg_random_mask; mask 3169 arch/ia64/kernel/perfmon.c ctx->ctx_pmds[cnum].mask, mask 5124 arch/ia64/kernel/perfmon.c unsigned long mask; mask 5140 arch/ia64/kernel/perfmon.c mask = pmc0 >> PMU_FIRST_COUNTER; mask 5157 arch/ia64/kernel/perfmon.c for (i = PMU_FIRST_COUNTER; mask ; i++, mask >>= 1) { mask 5160 arch/ia64/kernel/perfmon.c if ((mask & 0x1) == 0) continue; mask 5217 arch/ia64/kernel/perfmon.c mask = 1UL << i; mask 5222 arch/ia64/kernel/perfmon.c ovfl_arg->ovfl_notify = ovfl_notify & mask ? 1 : 0; mask 5264 arch/ia64/kernel/perfmon.c if (ovfl_arg->ovfl_ctrl.bits.reset_ovfl_pmds) reset_pmds |= mask; mask 446 arch/ia64/kernel/process.c unsigned long mask, sp, nat_bits = 0, ar_rnat, urbs_end, cfm; mask 481 arch/ia64/kernel/process.c for (i = 1, mask = (1UL << i); i < 32; ++i) { mask 484 arch/ia64/kernel/process.c nat_bits |= mask; mask 485 arch/ia64/kernel/process.c mask <<= 1; mask 83 arch/ia64/kernel/ptrace.c unsigned long mask = MASK(nbits) << first; \ mask 89 arch/ia64/kernel/ptrace.c ia64_rotr(unat, dist) & mask; \ mask 122 arch/ia64/kernel/ptrace.c unsigned long mask = MASK(nbits) << first; \ mask 128 arch/ia64/kernel/ptrace.c ia64_rotl(nat & mask, dist); \ mask 257 arch/ia64/kernel/ptrace.c unsigned long umask = 0, mask, m; mask 270 arch/ia64/kernel/ptrace.c mask = MASK(nbits); mask 285 arch/ia64/kernel/ptrace.c umask = MASK(ia64_rse_slot_num(ubspstore)) & mask; mask 287 arch/ia64/kernel/ptrace.c mask &= ~umask; mask 288 arch/ia64/kernel/ptrace.c if (!mask) mask 292 arch/ia64/kernel/ptrace.c m = mask << shift; mask 299 arch/ia64/kernel/ptrace.c m = mask >> (63 - shift); mask 316 arch/ia64/kernel/ptrace.c unsigned long rnat0 = 0, rnat1 = 0, *slot0_kaddr, umask = 0, mask, m; mask 343 arch/ia64/kernel/ptrace.c mask = MASK(nbits); mask 359 arch/ia64/kernel/ptrace.c umask = MASK(ia64_rse_slot_num(ubspstore)) & mask; mask 361 arch/ia64/kernel/ptrace.c mask &= ~umask; mask 362 arch/ia64/kernel/ptrace.c if (!mask) mask 370 arch/ia64/kernel/ptrace.c m = mask << shift; mask 377 arch/ia64/kernel/ptrace.c m = mask >> (63 - shift); mask 665 arch/ia64/kernel/setup.c unsigned long mask; mask 674 arch/ia64/kernel/setup.c unsigned long mask; mask 678 arch/ia64/kernel/setup.c mask = c->features; mask 686 arch/ia64/kernel/setup.c if (mask & feature_bits[i].mask) { mask 690 arch/ia64/kernel/setup.c mask &= ~feature_bits[i].mask; mask 694 arch/ia64/kernel/setup.c if (mask && size > 1) { mask 696 arch/ia64/kernel/setup.c snprintf(cp, size, "%s0x%lx", sep, mask); mask 166 arch/ia64/kernel/signal.c setup_sigcontext (struct sigcontext __user *sc, sigset_t *mask, struct sigscratch *scr) mask 189 arch/ia64/kernel/signal.c err |= PUT_SIGSET(mask, &sc->sc_mask); mask 169 arch/ia64/kernel/smp.c send_IPI_mask(const struct cpumask *mask, int op) mask 173 arch/ia64/kernel/smp.c for_each_cpu(cpu, mask) { mask 324 arch/ia64/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 326 arch/ia64/kernel/smp.c send_IPI_mask(mask, IPI_CALL_FUNC); mask 610 arch/ia64/kernel/smpboot.c const struct cpumask *mask; mask 623 arch/ia64/kernel/smpboot.c mask = cpumask_of(new_cpei_cpu); mask 633 arch/ia64/kernel/smpboot.c data->chip->irq_set_affinity(data, mask, false); mask 55 arch/ia64/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 436 arch/ia64/kernel/time.c fsyscall_gtod_data.clk_mask = tk->tkr_mono.mask; mask 771 arch/ia64/kernel/unwind.c unsigned char kind, mask = 0, *cp = sr->imask; mask 784 arch/ia64/kernel/unwind.c mask = *cp++; mask 785 arch/ia64/kernel/unwind.c kind = (mask >> 2*(3-(t & 3))) & 3; mask 807 arch/ia64/kernel/unwind.c desc_prologue (int body, unw_word rlen, unsigned char mask, unsigned char grsave, mask 837 arch/ia64/kernel/unwind.c if (mask & 0x8) mask 840 arch/ia64/kernel/unwind.c mask <<= 1; mask 175 arch/ia64/kernel/unwind_decoder.c unsigned char byte1, mask, grsave; mask 180 arch/ia64/kernel/unwind_decoder.c mask = ((code & 0x7) << 1) | ((byte1 >> 7) & 1); mask 183 arch/ia64/kernel/unwind_decoder.c UNW_DEC_PROLOGUE_GR(R2, rlen, mask, grsave, arg); mask 259 arch/ia64/kernel/unwind_decoder.c unsigned char mask = (code & 0x0f); mask 262 arch/ia64/kernel/unwind_decoder.c UNW_DEC_GR_MEM(P6, mask, arg); mask 264 arch/ia64/kernel/unwind_decoder.c UNW_DEC_FR_MEM(P6, mask, arg); mask 66 arch/ia64/mm/fault.c unsigned long mask; mask 70 arch/ia64/mm/fault.c mask = ((((isr >> IA64_ISR_X_BIT) & 1UL) << VM_EXEC_BIT) mask 102 arch/ia64/mm/fault.c if (mask & VM_WRITE) mask 134 arch/ia64/mm/fault.c if ((vma->vm_flags & mask) != mask) mask 39 arch/ia64/mm/tlb.c u64 mask; /* mask of supported purge page-sizes */ mask 327 arch/ia64/mm/tlb.c while (unlikely (((1UL << nbits) & purge.mask) == 0) && mask 379 arch/ia64/mm/tlb.c if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) { mask 382 arch/ia64/mm/tlb.c purge.mask = 0x115557000UL; mask 384 arch/ia64/mm/tlb.c purge.max_bits = ia64_fls(purge.mask); mask 392 arch/ia64/pci/pci.c pcibios_enable_device (struct pci_dev *dev, int mask) mask 396 arch/ia64/pci/pci.c ret = pci_enable_resources(dev, mask); mask 80 arch/m68k/68000/ints.c int mask; mask 88 arch/m68k/68000/ints.c mask = 0x00000001; mask 91 arch/m68k/68000/ints.c mask = 0x00000010; mask 96 arch/m68k/68000/ints.c mask = 0x00000100; mask 99 arch/m68k/68000/ints.c mask = 0x00001000; mask 106 arch/m68k/68000/ints.c mask = 0x00010000; mask 109 arch/m68k/68000/ints.c mask = 0x00100000; mask 114 arch/m68k/68000/ints.c mask = 0x01000000; mask 117 arch/m68k/68000/ints.c mask = 0x10000000; mask 123 arch/m68k/68000/ints.c while (! (mask & pend)) { mask 124 arch/m68k/68000/ints.c mask <<=1; mask 129 arch/m68k/68000/ints.c pend &= ~mask; mask 97 arch/m68k/68000/timers.c .mask = CLOCKSOURCE_MASK(32), mask 51 arch/m68k/amiga/cia.c unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) mask 56 arch/m68k/amiga/cia.c if (mask & CIA_ICR_SETCLR) mask 57 arch/m68k/amiga/cia.c base->icr_data |= mask; mask 59 arch/m68k/amiga/cia.c base->icr_data &= ~mask; mask 69 arch/m68k/amiga/cia.c unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) mask 75 arch/m68k/amiga/cia.c base->cia->icr = mask; mask 76 arch/m68k/amiga/cia.c if (mask & CIA_ICR_SETCLR) mask 77 arch/m68k/amiga/cia.c base->icr_mask |= mask; mask 79 arch/m68k/amiga/cia.c base->icr_mask &= ~mask; mask 114 arch/m68k/amiga/cia.c unsigned char mask; mask 117 arch/m68k/amiga/cia.c mask = 1 << (irq - IRQ_AMIGA_CIAB); mask 118 arch/m68k/amiga/cia.c cia_set_irq(&ciab_base, mask); mask 119 arch/m68k/amiga/cia.c cia_able_irq(&ciab_base, CIA_ICR_SETCLR | mask); mask 121 arch/m68k/amiga/cia.c mask = 1 << (irq - IRQ_AMIGA_CIAA); mask 122 arch/m68k/amiga/cia.c cia_set_irq(&ciaa_base, mask); mask 123 arch/m68k/amiga/cia.c cia_able_irq(&ciaa_base, CIA_ICR_SETCLR | mask); mask 471 arch/m68k/amiga/config.c .mask = CLOCKSOURCE_MASK(32), mask 39 arch/m68k/atari/atasound.c tt_microwire.mask = 0x7ff; mask 43 arch/m68k/atari/atasound.c while( tt_microwire.mask != 0x7ff) mask 344 arch/m68k/atari/config.c hwreg_present(&tt_microwire.mask) && mask 345 arch/m68k/atari/config.c (tt_microwire.mask = 0x7ff, mask 351 arch/m68k/atari/config.c while (tt_microwire.mask != 0x7ff) mask 34 arch/m68k/atari/time.c .mask = CLOCKSOURCE_MASK(32), mask 157 arch/m68k/bvme6000/config.c .mask = CLOCKSOURCE_MASK(32), mask 47 arch/m68k/coldfire/dma_timer.c .mask = CLOCKSOURCE_MASK(32), mask 59 arch/m68k/coldfire/intc.c void mcf_maskimr(unsigned int mask) mask 63 arch/m68k/coldfire/intc.c imr |= mask; mask 83 arch/m68k/coldfire/intc.c void mcf_maskimr(unsigned int mask) mask 87 arch/m68k/coldfire/intc.c imr |= mask; mask 142 arch/m68k/coldfire/pit.c .mask = CLOCKSOURCE_MASK(32), mask 123 arch/m68k/coldfire/sltimers.c .mask = CLOCKSOURCE_MASK(32), mask 113 arch/m68k/coldfire/timers.c .mask = CLOCKSOURCE_MASK(32), mask 132 arch/m68k/emu/nfeth.c int i, m, mask; mask 134 arch/m68k/emu/nfeth.c mask = nf_call(nfEtherID + XIF_IRQ, 0); mask 136 arch/m68k/emu/nfeth.c if (mask & m && nfeth_dev[i]) { mask 29 arch/m68k/hp300/time.c .mask = CLOCKSOURCE_MASK(32), mask 110 arch/m68k/include/asm/amigaints.h extern unsigned char cia_set_irq(struct ciabase *base, unsigned char mask); mask 111 arch/m68k/include/asm/amigaints.h extern unsigned char cia_able_irq(struct ciabase *base, unsigned char mask); mask 747 arch/m68k/include/asm/atarihw.h u_short mask; mask 117 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; mask 119 arch/m68k/include/asm/atariints.h mask = 1 << (irq & 7); mask 122 arch/m68k/include/asm/atariints.h return( *reg & mask ); mask 127 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; mask 129 arch/m68k/include/asm/atariints.h mask = 1 << (irq & 7); mask 133 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); mask 138 arch/m68k/include/asm/atariints.h { unsigned char mask, *reg; mask 140 arch/m68k/include/asm/atariints.h mask = ~(1 << (irq & 7)); mask 145 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); mask 148 arch/m68k/include/asm/atariints.h : : "di" (mask), "m" (*reg) : "memory" ); mask 108 arch/m68k/include/asm/fbio.h char __user *mask; /* cursor mask bits */ mask 324 arch/m68k/include/asm/fbio.h u32 mask; /* cursor mask bits */ mask 57 arch/m68k/include/asm/nettel.h static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) mask 61 arch/m68k/include/asm/nettel.h ppdata = (ppdata & ~mask) | bits; mask 94 arch/m68k/include/asm/nettel.h static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) mask 96 arch/m68k/include/asm/nettel.h writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT); mask 45 arch/m68k/kernel/pcibios.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 56 arch/m68k/kernel/pcibios.c if (!(mask & (1 << idx))) mask 833 arch/m68k/kernel/signal.c unsigned long mask) mask 835 arch/m68k/kernel/signal.c sc->sc_mask = mask; mask 593 arch/m68k/mac/via.c .mask = CLOCKSOURCE_MASK(32), mask 453 arch/m68k/math-emu/fp_arith.c unsigned long mask; mask 510 arch/m68k/math-emu/fp_arith.c mask = 1 << (0x401d - dest->exp); mask 511 arch/m68k/math-emu/fp_arith.c if (!(oldmant.m32[0] & mask)) mask 513 arch/m68k/math-emu/fp_arith.c if (oldmant.m32[0] & (mask << 1)) mask 528 arch/m68k/math-emu/fp_arith.c mask = 1 << (0x403d - dest->exp); mask 529 arch/m68k/math-emu/fp_arith.c if (!(oldmant.m32[1] & mask)) mask 531 arch/m68k/math-emu/fp_arith.c if (oldmant.m32[1] & (mask << 1)) mask 554 arch/m68k/math-emu/fp_arith.c mask = 1 << (0x401e - dest->exp); mask 555 arch/m68k/math-emu/fp_arith.c if (dest->mant.m32[0] += mask) mask 561 arch/m68k/math-emu/fp_arith.c mask = 1 << (0x403e - dest->exp); mask 562 arch/m68k/math-emu/fp_arith.c if (dest->mant.m32[1] += mask) mask 42 arch/m68k/mm/memory.c unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE); mask 45 arch/m68k/mm/memory.c if (!(PD_MARKBITS(dp) & mask)) { mask 50 arch/m68k/mm/memory.c PD_MARKBITS(dp) &= ~mask; mask 63 arch/m68k/mm/memory.c unsigned char mask = PD_MARKBITS (dp); mask 73 arch/m68k/mm/memory.c if (mask == 0) { mask 90 arch/m68k/mm/memory.c for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE) mask 92 arch/m68k/mm/memory.c PD_MARKBITS(dp) = mask & ~tmp; mask 104 arch/m68k/mm/memory.c unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE); mask 107 arch/m68k/mm/memory.c if (PD_MARKBITS (dp) & mask) mask 110 arch/m68k/mm/memory.c PD_MARKBITS (dp) |= mask; mask 102 arch/m68k/mvme147/config.c .mask = CLOCKSOURCE_MASK(32), mask 353 arch/m68k/mvme16x/config.c .mask = CLOCKSOURCE_MASK(32), mask 172 arch/m68k/q40/q40ints.c struct IRQ_TABLE{ unsigned mask; int irq ;}; mask 180 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ3_MASK, .irq = 3 }, /* ser 1 */ mask 181 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ4_MASK, .irq = 4 }, /* ser 2 */ mask 182 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ14_MASK, .irq = 14 }, /* IDE 1 */ mask 183 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ15_MASK, .irq = 15 }, /* IDE 2 */ mask 184 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ6_MASK, .irq = 6 }, /* floppy, handled elsewhere */ mask 185 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ7_MASK, .irq = 7 }, /* par */ mask 186 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ5_MASK, .irq = 5 }, mask 187 arch/m68k/q40/q40ints.c { .mask = Q40_IRQ10_MASK, .irq = 10 }, mask 235 arch/m68k/q40/q40ints.c for (i = 0; eirqs[i].mask; i++) { mask 236 arch/m68k/q40/q40ints.c if (mer & eirqs[i].mask) { mask 37 arch/microblaze/include/asm/setup.h extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); mask 121 arch/microblaze/kernel/signal.c unsigned long mask) mask 139 arch/microblaze/kernel/signal.c err |= __put_user(mask, &sc->oldmask); mask 210 arch/microblaze/kernel/timer.c .mask = CLOCKSOURCE_MASK(32), mask 228 arch/microblaze/kernel/timer.c .mask = CLOCKSOURCE_MASK(32), mask 361 arch/microblaze/mm/init.c void * __ref zalloc_maybe_bootmem(size_t size, gfp_t mask) mask 366 arch/microblaze/mm/init.c p = kzalloc(size, mask); mask 43 arch/mips/alchemy/common/time.c .mask = CLOCKSOURCE_MASK(32), mask 47 arch/mips/ath25/ar2315.c static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) mask 51 arch/mips/ath25/ar2315.c ret &= ~mask; mask 48 arch/mips/ath25/ar5312.c static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) mask 52 arch/mips/ath25/ar5312.c ret &= ~mask; mask 87 arch/mips/ath79/common.c void ath79_device_reset_set(u32 mask) mask 114 arch/mips/ath79/common.c ath79_reset_wr(reg, t | mask); mask 119 arch/mips/ath79/common.c void ath79_device_reset_clear(u32 mask) mask 146 arch/mips/ath79/common.c ath79_reset_wr(reg, t & ~mask); mask 21 arch/mips/ath79/early_printk.c static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) mask 27 arch/mips/ath79/early_printk.c if ((t & mask) == val) mask 43 arch/mips/bcm63xx/clk.c static void bcm_hwclock_set(u32 mask, int enable) mask 49 arch/mips/bcm63xx/clk.c reg |= mask; mask 51 arch/mips/bcm63xx/clk.c reg &= ~mask; mask 60 arch/mips/bcm63xx/clk.c u32 mask; mask 63 arch/mips/bcm63xx/clk.c mask = CKCTL_6338_ENET_EN; mask 65 arch/mips/bcm63xx/clk.c mask = CKCTL_6345_ENET_EN; mask 67 arch/mips/bcm63xx/clk.c mask = CKCTL_6348_ENET_EN; mask 70 arch/mips/bcm63xx/clk.c mask = CKCTL_6358_EMUSB_EN; mask 71 arch/mips/bcm63xx/clk.c bcm_hwclock_set(mask, enable); mask 90 arch/mips/bcm63xx/clk.c u32 mask; mask 93 arch/mips/bcm63xx/clk.c mask = CKCTL_6358_ENET0_EN; mask 95 arch/mips/bcm63xx/clk.c mask = CKCTL_6358_ENET1_EN; mask 96 arch/mips/bcm63xx/clk.c bcm_hwclock_set(mask, enable); mask 245 arch/mips/bcm63xx/clk.c u32 mask; mask 248 arch/mips/bcm63xx/clk.c mask = CKCTL_6338_SPI_EN; mask 250 arch/mips/bcm63xx/clk.c mask = CKCTL_6348_SPI_EN; mask 252 arch/mips/bcm63xx/clk.c mask = CKCTL_6358_SPI_EN; mask 254 arch/mips/bcm63xx/clk.c mask = CKCTL_6362_SPI_EN; mask 257 arch/mips/bcm63xx/clk.c mask = CKCTL_6368_SPI_EN; mask 258 arch/mips/bcm63xx/clk.c bcm_hwclock_set(mask, enable); mask 270 arch/mips/bcm63xx/clk.c u32 mask; mask 273 arch/mips/bcm63xx/clk.c mask = CKCTL_6328_HSSPI_EN; mask 275 arch/mips/bcm63xx/clk.c mask = CKCTL_6362_HSSPI_EN; mask 279 arch/mips/bcm63xx/clk.c bcm_hwclock_set(mask, enable); mask 42 arch/mips/bcm63xx/gpio.c u32 mask; mask 51 arch/mips/bcm63xx/gpio.c mask = 1 << gpio; mask 55 arch/mips/bcm63xx/gpio.c mask = 1 << (gpio - 32); mask 61 arch/mips/bcm63xx/gpio.c *v |= mask; mask 63 arch/mips/bcm63xx/gpio.c *v &= ~mask; mask 71 arch/mips/bcm63xx/gpio.c u32 mask; mask 78 arch/mips/bcm63xx/gpio.c mask = 1 << gpio; mask 81 arch/mips/bcm63xx/gpio.c mask = 1 << (gpio - 32); mask 84 arch/mips/bcm63xx/gpio.c return !!(bcm_gpio_readl(reg) & mask); mask 91 arch/mips/bcm63xx/gpio.c u32 mask; mask 100 arch/mips/bcm63xx/gpio.c mask = 1 << gpio; mask 103 arch/mips/bcm63xx/gpio.c mask = 1 << (gpio - 32); mask 109 arch/mips/bcm63xx/gpio.c tmp &= ~mask; mask 111 arch/mips/bcm63xx/gpio.c tmp |= mask; mask 23 arch/mips/bcm63xx/prom.c u32 reg, mask; mask 33 arch/mips/bcm63xx/prom.c mask = CKCTL_3368_ALL_SAFE_EN; mask 35 arch/mips/bcm63xx/prom.c mask = CKCTL_6328_ALL_SAFE_EN; mask 37 arch/mips/bcm63xx/prom.c mask = CKCTL_6338_ALL_SAFE_EN; mask 39 arch/mips/bcm63xx/prom.c mask = CKCTL_6345_ALL_SAFE_EN; mask 41 arch/mips/bcm63xx/prom.c mask = CKCTL_6348_ALL_SAFE_EN; mask 43 arch/mips/bcm63xx/prom.c mask = CKCTL_6358_ALL_SAFE_EN; mask 45 arch/mips/bcm63xx/prom.c mask = CKCTL_6362_ALL_SAFE_EN; mask 47 arch/mips/bcm63xx/prom.c mask = CKCTL_6368_ALL_SAFE_EN; mask 49 arch/mips/bcm63xx/prom.c mask = 0; mask 52 arch/mips/bcm63xx/prom.c reg &= ~mask; mask 193 arch/mips/bcm63xx/reset.c static void __bcm63xx_core_set_reset(u32 mask, int enable) mask 198 arch/mips/bcm63xx/reset.c if (!mask) mask 205 arch/mips/bcm63xx/reset.c val &= ~mask; mask 207 arch/mips/bcm63xx/reset.c val |= mask; mask 110 arch/mips/cavium-octeon/csrc-octeon.c .mask = CLOCKSOURCE_MASK(64), mask 52 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c int mask; mask 60 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c mask = 0xf; /* Set enables for 4 ports */ mask 62 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c mask = 0x7; /* Set enables for 3 ports */ mask 66 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c csr.s.txpsh = mask; mask 67 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c csr.s.txpop = mask; mask 68 arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c csr.s.ovrflw = mask; mask 84 arch/mips/cavium-octeon/executive/cvmx-l2c.c int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask) mask 91 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask &= valid_mask; mask 94 arch/mips/cavium-octeon/executive/cvmx-l2c.c if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) mask 102 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask); mask 121 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask << field); mask 126 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask << field); mask 131 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask << field); mask 136 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask << field); mask 142 arch/mips/cavium-octeon/executive/cvmx-l2c.c int cvmx_l2c_set_hw_way_partition(uint32_t mask) mask 147 arch/mips/cavium-octeon/executive/cvmx-l2c.c mask &= valid_mask; mask 150 arch/mips/cavium-octeon/executive/cvmx-l2c.c if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX)) mask 154 arch/mips/cavium-octeon/executive/cvmx-l2c.c cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask); mask 157 arch/mips/cavium-octeon/executive/cvmx-l2c.c (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask); mask 183 arch/mips/cavium-octeon/octeon-irq.c unsigned int mask = 0x100 << cd->bit; mask 189 arch/mips/cavium-octeon/octeon-irq.c set_c0_status(mask); mask 191 arch/mips/cavium-octeon/octeon-irq.c clear_c0_status(mask); mask 266 arch/mips/cavium-octeon/octeon-irq.c struct cpumask *mask = irq_data_get_affinity_mask(data); mask 267 arch/mips/cavium-octeon/octeon-irq.c int weight = cpumask_weight(mask); mask 273 arch/mips/cavium-octeon/octeon-irq.c cpu = cpumask_next(cpu, mask); mask 282 arch/mips/cavium-octeon/octeon-irq.c cpu = cpumask_first(mask); mask 463 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 468 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 477 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); mask 481 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); mask 490 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 496 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 498 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); mask 506 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 512 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 514 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); mask 519 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 525 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 527 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_SUM2_PPX_IP4(index), mask); mask 534 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 537 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 542 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(coreid), mask); mask 552 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 556 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 561 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); mask 565 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); mask 571 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 575 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 580 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); mask 584 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); mask 593 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 597 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 601 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); mask 603 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); mask 614 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 618 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 625 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); mask 632 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); mask 644 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 648 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 655 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); mask 662 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); mask 747 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 750 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->gpio_line); mask 752 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); mask 761 arch/mips/cavium-octeon/octeon-irq.c struct cpumask *mask = irq_data_get_affinity_mask(data); mask 763 arch/mips/cavium-octeon/octeon-irq.c if (!cpumask_test_cpu(cpu, mask)) mask 766 arch/mips/cavium-octeon/octeon-irq.c if (cpumask_weight(mask) > 1) { mask 771 arch/mips/cavium-octeon/octeon-irq.c cpumask_copy(&new_affinity, mask); mask 848 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 855 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << cd->bit; mask 864 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); mask 867 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); mask 877 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); mask 880 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); mask 893 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 900 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << cd->bit; mask 907 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1S(index), mask); mask 909 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(CVMX_CIU_EN2_PPX_IP4_W1C(index), mask); mask 1636 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1642 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1646 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1652 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1659 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1663 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1668 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1674 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1678 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1684 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1690 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1694 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1700 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1706 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1709 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1716 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1720 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (cd->bit); mask 1725 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1732 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1734 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); mask 1739 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1746 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1748 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); mask 1753 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1759 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1763 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); mask 1765 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1770 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1774 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << (data->irq - OCTEON_IRQ_MBOX0); mask 1776 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 1785 arch/mips/cavium-octeon/octeon-irq.c u64 mask; mask 1792 arch/mips/cavium-octeon/octeon-irq.c mask = 1ull << cd->bit; mask 1806 arch/mips/cavium-octeon/octeon-irq.c cvmx_write_csr(en_addr, mask); mask 400 arch/mips/cavium-octeon/setup.c unsigned long long mask; mask 404 arch/mips/cavium-octeon/setup.c mask = 0x1f00000000ull; mask 406 arch/mips/cavium-octeon/setup.c if (bist_val & mask) mask 416 arch/mips/cavium-octeon/setup.c mask = 0xfc00000000000000ull; mask 418 arch/mips/cavium-octeon/setup.c if (bist_val & mask) mask 109 arch/mips/cavium-octeon/smp.c static inline void octeon_send_ipi_mask(const struct cpumask *mask, mask 114 arch/mips/cavium-octeon/smp.c for_each_cpu(i, mask) mask 312 arch/mips/cavium-octeon/smp.c uint32_t mask, new_mask; mask 323 arch/mips/cavium-octeon/smp.c mask = 1 << coreid; mask 332 arch/mips/cavium-octeon/smp.c labi->avail_coremask |= mask; mask 337 arch/mips/cavium-octeon/smp.c *p |= mask; mask 487 arch/mips/cavium-octeon/smp.c static void octeon_78xx_send_ipi_mask(const struct cpumask *mask, mask 492 arch/mips/cavium-octeon/smp.c for_each_cpu(cpu, mask) mask 81 arch/mips/include/asm/irq.h void arch_trigger_cpumask_backtrace(const struct cpumask *mask, mask 499 arch/mips/include/asm/kvm_host.h __KVMT##type mask, \ mask 502 arch/mips/include/asm/kvm_host.h unsigned long _mask = mask; \ mask 520 arch/mips/include/asm/kvm_host.h __KVMT##type mask, \ mask 523 arch/mips/include/asm/kvm_host.h _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \ mask 557 arch/mips/include/asm/kvm_host.h __KVMT##type mask, \ mask 560 arch/mips/include/asm/kvm_host.h change_gc0_##name(mask, val); \ mask 604 arch/mips/include/asm/kvm_host.h __KVMT##type mask, \ mask 607 arch/mips/include/asm/kvm_host.h kvm_change_##name2(cop0, mask, val); \ mask 175 arch/mips/include/asm/mach-ath79/ath79.h void ath79_device_reset_set(u32 mask); mask 176 arch/mips/include/asm/mach-ath79/ath79.h void ath79_device_reset_clear(u32 mask); mask 220 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); mask 222 arch/mips/include/asm/mach-au1x00/gpio-au1000.h alchemy_wrsys(mask, r); mask 227 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); mask 228 arch/mips/include/asm/mach-au1x00/gpio-au1000.h return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask; mask 233 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); mask 234 arch/mips/include/asm/mach-au1x00/gpio-au1000.h alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR); mask 287 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); mask 291 arch/mips/include/asm/mach-au1x00/gpio-au1000.h d |= mask; mask 293 arch/mips/include/asm/mach-au1x00/gpio-au1000.h d &= ~mask; mask 301 arch/mips/include/asm/mach-au1x00/gpio-au1000.h unsigned long mask; mask 302 arch/mips/include/asm/mach-au1x00/gpio-au1000.h mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); mask 303 arch/mips/include/asm/mach-au1x00/gpio-au1000.h __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); mask 73 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h u32 const mask, mask 89 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h : "ir" (~mask), "ir" (value), GCC_OFF_SMALL_ASM() (*addr)); mask 96 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h u32 const mask) mask 110 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr)); mask 117 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h u32 const mask) mask 131 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h : "ir" (~mask), GCC_OFF_SMALL_ASM() (*addr)); mask 138 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h u32 const mask) mask 152 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h : "ir" (mask), GCC_OFF_SMALL_ASM() (*addr)); mask 159 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h u32 const mask) mask 170 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h : "m" (*addr), "ir" (mask)); mask 626 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h #define DDRC_INDIRECT_WRITE(reg, mask, value) \ mask 628 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regs.h *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ mask 13 arch/mips/include/asm/mach-ralink/pinmux.h { .name = _name, .mask = _mask, .shift = _shift, \ mask 18 arch/mips/include/asm/mach-ralink/pinmux.h { .name = _name, .mask = _mask, .shift = _shift, \ mask 43 arch/mips/include/asm/mach-ralink/pinmux.h const char mask; mask 55 arch/mips/include/asm/mach-rc32434/rb.h u32 mask; mask 71 arch/mips/include/asm/mips-cps.h static inline void change_##unit##_##name(uint##sz##_t mask, \ mask 75 arch/mips/include/asm/mips-cps.h reg_val &= ~mask; \ mask 204 arch/mips/include/asm/mips-gic.h GIC_ACCESSOR_RO_INTR_BIT(0x400, mask) mask 230 arch/mips/include/asm/mips-gic.h GIC_VX_ACCESSOR_RO(32, 0x008, mask) mask 76 arch/mips/include/asm/mips-r2-to-r6-emul.h u32 mask; mask 2315 arch/mips/include/asm/mipsregs.h #define rddsp(mask) \ mask 2326 arch/mips/include/asm/mipsregs.h : "i" (mask)); \ mask 2330 arch/mips/include/asm/mipsregs.h #define wrdsp(val, mask) \ mask 2339 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (mask)); \ mask 2545 arch/mips/include/asm/mipsregs.h #define rddsp(mask) \ mask 2558 arch/mips/include/asm/mipsregs.h : "i" (mask)); \ mask 2562 arch/mips/include/asm/mipsregs.h #define wrdsp(val, mask) \ mask 2573 arch/mips/include/asm/mipsregs.h : "r" (val), "i" (mask)); \ mask 228 arch/mips/include/asm/netlogic/xlr/fmn.h static inline void nlm_msgwait(unsigned int mask) mask 237 arch/mips/include/asm/netlogic/xlr/fmn.h : : "r" (mask) : "$1" mask 306 arch/mips/include/asm/nile4.h extern void nile4_clear_irq_mask(u32 mask); mask 400 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 408 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 419 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 427 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 595 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 603 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 614 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 622 arch/mips/include/asm/octeon/cvmx-iob-defs.h uint64_t mask:8; mask 209 arch/mips/include/asm/octeon/cvmx-l2c.h int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask); mask 235 arch/mips/include/asm/octeon/cvmx-l2c.h int cvmx_l2c_set_hw_way_partition(uint32_t mask); mask 278 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:64; mask 280 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:64; mask 290 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:8; mask 292 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:8; mask 302 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:64; mask 304 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:64; mask 314 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:8; mask 316 arch/mips/include/asm/octeon/cvmx-lmcx-defs.h uint64_t mask:8; mask 78 arch/mips/include/asm/octeon/cvmx-pemx-defs.h uint64_t mask:35; mask 82 arch/mips/include/asm/octeon/cvmx-pemx-defs.h uint64_t mask:35; mask 1984 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2000 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2007 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2023 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2030 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2046 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2523 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 2525 arch/mips/include/asm/octeon/cvmx-pip-defs.h uint64_t mask:16; mask 1775 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:20; mask 1777 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:20; mask 1784 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:10; mask 1786 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:10; mask 1793 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:14; mask 1795 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:14; mask 1802 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:12; mask 1804 arch/mips/include/asm/octeon/cvmx-pko-defs.h uint64_t mask:12; mask 1851 arch/mips/include/asm/octeon/cvmx-pow.h static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask) mask 1856 arch/mips/include/asm/octeon/cvmx-pow.h grp_msk.s.grp_msk = mask; mask 26 arch/mips/include/asm/smp-ops.h void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action); mask 52 arch/mips/include/asm/smp-ops.h extern void mips_smp_send_ipi_mask(const struct cpumask *mask, mask 115 arch/mips/include/asm/smp.h int mips_smp_ipi_allocate(const struct cpumask *mask); mask 122 arch/mips/include/asm/smp.h int mips_smp_ipi_free(const struct cpumask *mask); mask 131 arch/mips/include/asm/smp.h static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 135 arch/mips/include/asm/smp.h mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); mask 83 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_piuint(uint16_t mask); mask 84 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_piuint(uint16_t mask); mask 94 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_aiuint(uint16_t mask); mask 95 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_aiuint(uint16_t mask); mask 101 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_kiuint(uint16_t mask); mask 102 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_kiuint(uint16_t mask); mask 110 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_dsiuint(uint16_t mask); mask 111 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_dsiuint(uint16_t mask); mask 119 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_firint(uint16_t mask); mask 120 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_firint(uint16_t mask); mask 136 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_enable_csiint(uint16_t mask); mask 137 arch/mips/include/asm/vr41xx/vr41xx.h extern void vr41xx_disable_csiint(uint16_t mask); mask 29 arch/mips/jazz/irq.c unsigned int mask = 1 << (d->irq - JAZZ_IRQ_START); mask 33 arch/mips/jazz/irq.c mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE); mask 34 arch/mips/jazz/irq.c r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask); mask 40 arch/mips/jazz/irq.c unsigned int mask = ~(1 << (d->irq - JAZZ_IRQ_START)); mask 44 arch/mips/jazz/irq.c mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE); mask 45 arch/mips/jazz/irq.c r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask); mask 45 arch/mips/kernel/cevt-txx9.c .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS), mask 12 arch/mips/kernel/cmpxchg.c u32 old32, new32, load32, mask; mask 20 arch/mips/kernel/cmpxchg.c mask = GENMASK((size * BITS_PER_BYTE) - 1, 0); mask 21 arch/mips/kernel/cmpxchg.c val &= mask; mask 32 arch/mips/kernel/cmpxchg.c mask <<= shift; mask 43 arch/mips/kernel/cmpxchg.c new32 = (load32 & ~mask) | (val << shift); mask 47 arch/mips/kernel/cmpxchg.c return (load32 & mask) >> shift; mask 53 arch/mips/kernel/cmpxchg.c u32 mask, old32, new32, load32, load; mask 61 arch/mips/kernel/cmpxchg.c mask = GENMASK((size * BITS_PER_BYTE) - 1, 0); mask 62 arch/mips/kernel/cmpxchg.c old &= mask; mask 63 arch/mips/kernel/cmpxchg.c new &= mask; mask 74 arch/mips/kernel/cmpxchg.c mask <<= shift; mask 88 arch/mips/kernel/cmpxchg.c load = (load32 & mask) >> shift; mask 98 arch/mips/kernel/cmpxchg.c old32 = (load32 & ~mask) | (old << shift); mask 99 arch/mips/kernel/cmpxchg.c new32 = (load32 & ~mask) | (new << shift); mask 64 arch/mips/kernel/cpu-probe.c unsigned long sr, mask, fcsr, fcsr0, fcsr1; mask 67 arch/mips/kernel/cpu-probe.c mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; mask 72 arch/mips/kernel/cpu-probe.c fcsr0 = fcsr & mask; mask 76 arch/mips/kernel/cpu-probe.c fcsr1 = fcsr | ~mask; mask 84 arch/mips/kernel/cpu-probe.c c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; mask 28 arch/mips/kernel/csrc-bcm1480.c .mask = CLOCKSOURCE_MASK(64), mask 24 arch/mips/kernel/csrc-ioasic.c .mask = CLOCKSOURCE_MASK(32), mask 22 arch/mips/kernel/csrc-r4k.c .mask = CLOCKSOURCE_MASK(32), mask 44 arch/mips/kernel/csrc-sb1250.c .mask = CLOCKSOURCE_MASK(23), mask 34 arch/mips/kernel/irq-gt641xx.c u32 mask; mask 37 arch/mips/kernel/irq-gt641xx.c mask = GT_READ(GT_INTRMASK_OFS); mask 38 arch/mips/kernel/irq-gt641xx.c mask &= ~GT641XX_IRQ_TO_BIT(d->irq); mask 39 arch/mips/kernel/irq-gt641xx.c GT_WRITE(GT_INTRMASK_OFS, mask); mask 46 arch/mips/kernel/irq-gt641xx.c u32 cause, mask; mask 49 arch/mips/kernel/irq-gt641xx.c mask = GT_READ(GT_INTRMASK_OFS); mask 50 arch/mips/kernel/irq-gt641xx.c mask &= ~GT641XX_IRQ_TO_BIT(d->irq); mask 51 arch/mips/kernel/irq-gt641xx.c GT_WRITE(GT_INTRMASK_OFS, mask); mask 62 arch/mips/kernel/irq-gt641xx.c u32 mask; mask 65 arch/mips/kernel/irq-gt641xx.c mask = GT_READ(GT_INTRMASK_OFS); mask 66 arch/mips/kernel/irq-gt641xx.c mask |= GT641XX_IRQ_TO_BIT(d->irq); mask 67 arch/mips/kernel/irq-gt641xx.c GT_WRITE(GT_INTRMASK_OFS, mask); mask 81 arch/mips/kernel/irq-gt641xx.c u32 cause, mask; mask 85 arch/mips/kernel/irq-gt641xx.c mask = GT_READ(GT_INTRMASK_OFS); mask 86 arch/mips/kernel/irq-gt641xx.c cause &= mask; mask 161 arch/mips/kernel/mips-mt-fpaff.c cpumask_t allowed, mask; mask 165 arch/mips/kernel/mips-mt-fpaff.c real_len = sizeof(mask); mask 181 arch/mips/kernel/mips-mt-fpaff.c cpumask_and(&mask, &allowed, cpu_active_mask); mask 188 arch/mips/kernel/mips-mt-fpaff.c if (copy_to_user(user_mask_ptr, &mask, real_len)) mask 892 arch/mips/kernel/mips-r2-to-r6-emul.c if ((inst & p->mask) == p->code) { mask 193 arch/mips/kernel/module.c unsigned long mask = GENMASK(bits - 1, 0); mask 204 arch/mips/kernel/module.c offset = base & mask; mask 205 arch/mips/kernel/module.c offset |= (offset & BIT(bits - 1)) ? ~mask : 0; mask 211 arch/mips/kernel/module.c if ((offset & ~mask) != (se_bits & ~mask)) { mask 216 arch/mips/kernel/module.c *location = (*location & ~mask) | (offset & mask); mask 693 arch/mips/kernel/process.c static void raise_backtrace(cpumask_t *mask) mask 698 arch/mips/kernel/process.c for_each_cpu(cpu, mask) { mask 717 arch/mips/kernel/process.c void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) mask 719 arch/mips/kernel/process.c nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); mask 351 arch/mips/kernel/ptrace.c u32 mask; mask 354 arch/mips/kernel/ptrace.c mask = boot_cpu_data.fpu_msk31; mask 355 arch/mips/kernel/ptrace.c child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); mask 342 arch/mips/kernel/rtlx.c __poll_t mask = 0; mask 352 arch/mips/kernel/rtlx.c mask |= EPOLLIN | EPOLLRDNORM; mask 356 arch/mips/kernel/rtlx.c mask |= EPOLLOUT | EPOLLWRNORM; mask 358 arch/mips/kernel/rtlx.c return mask; mask 591 arch/mips/kernel/signal.c old_sigset_t mask; mask 597 arch/mips/kernel/signal.c err |= __get_user(mask, &act->sa_mask.sig[0]); mask 601 arch/mips/kernel/signal.c siginitset(&new_ka.sa.sa_mask, mask); mask 46 arch/mips/kernel/signal32.c old_sigset_t mask; mask 54 arch/mips/kernel/signal32.c err |= __get_user(mask, &act->sa_mask.sig[0]); mask 58 arch/mips/kernel/signal32.c siginitset(&new_ka.sa.sa_mask, mask); mask 298 arch/mips/kernel/smp-bmips.c static void bmips5000_send_ipi_mask(const struct cpumask *mask, mask 303 arch/mips/kernel/smp-bmips.c for_each_cpu(i, mask) mask 350 arch/mips/kernel/smp-bmips.c static void bmips43xx_send_ipi_mask(const struct cpumask *mask, mask 355 arch/mips/kernel/smp-bmips.c for_each_cpu(i, mask) mask 482 arch/mips/kernel/smp-bmips.c u32 mask = ~(0xffff << shift), val = info->val >> 16; mask 494 arch/mips/kernel/smp-bmips.c write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | mask 21 arch/mips/kernel/smp-up.c static inline void up_send_ipi_mask(const struct cpumask *mask, mask 154 arch/mips/kernel/smp.c void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) mask 164 arch/mips/kernel/smp.c __ipi_send_mask(call_desc, mask); mask 168 arch/mips/kernel/smp.c __ipi_send_mask(sched_desc, mask); mask 176 arch/mips/kernel/smp.c for_each_cpu(cpu, mask) { mask 234 arch/mips/kernel/smp.c int mips_smp_ipi_allocate(const struct cpumask *mask) mask 267 arch/mips/kernel/smp.c virq = irq_reserve_ipi(ipidomain, mask); mask 272 arch/mips/kernel/smp.c virq = irq_reserve_ipi(ipidomain, mask); mask 280 arch/mips/kernel/smp.c for_each_cpu(cpu, mask) { mask 292 arch/mips/kernel/smp.c int mips_smp_ipi_free(const struct cpumask *mask) mask 313 arch/mips/kernel/smp.c for_each_cpu(cpu, mask) { mask 318 arch/mips/kernel/smp.c irq_destroy_ipi(call_virq, mask); mask 319 arch/mips/kernel/smp.c irq_destroy_ipi(sched_virq, mask); mask 702 arch/mips/kernel/smp.c void tick_broadcast(const struct cpumask *mask) mask 708 arch/mips/kernel/smp.c for_each_cpu(cpu, mask) { mask 1189 arch/mips/kvm/emulate.c unsigned int mask = 0; mask 1193 arch/mips/kvm/emulate.c mask |= MIPS_CONF1_FP; mask 1195 arch/mips/kvm/emulate.c return mask; mask 1208 arch/mips/kvm/emulate.c unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI; mask 1212 arch/mips/kvm/emulate.c mask |= MIPS_CONF3_MSA; mask 1214 arch/mips/kvm/emulate.c return mask; mask 1227 arch/mips/kvm/emulate.c unsigned int mask = MIPS_CONF_M; mask 1230 arch/mips/kvm/emulate.c mask |= 0xfc << MIPS_CONF4_KSCREXIST_SHIFT; mask 1232 arch/mips/kvm/emulate.c return mask; mask 1244 arch/mips/kvm/emulate.c unsigned int mask = 0; mask 1248 arch/mips/kvm/emulate.c mask |= MIPS_CONF5_MSAEN; mask 1256 arch/mips/kvm/emulate.c mask |= MIPS_CONF5_FRE; mask 1260 arch/mips/kvm/emulate.c return mask; mask 1511 arch/mips/kvm/emulate.c u32 mask = MIPS_HWRENA_CPUNUM | mask 1518 arch/mips/kvm/emulate.c mask |= MIPS_HWRENA_ULR; mask 1519 arch/mips/kvm/emulate.c cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask; mask 443 arch/mips/kvm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 446 arch/mips/kvm/mmu.c gfn_t start = base_gfn + __ffs(mask); mask 447 arch/mips/kvm/mmu.c gfn_t end = base_gfn + __fls(mask); mask 109 arch/mips/kvm/vz.c unsigned int mask = MIPS_CONF5_K | MIPS_CONF5_CV | MIPS_CONF5_SBRI; mask 113 arch/mips/kvm/vz.c mask |= MIPS_CONF5_MSAEN; mask 121 arch/mips/kvm/vz.c mask |= MIPS_CONF5_UFR; mask 123 arch/mips/kvm/vz.c mask |= MIPS_CONF5_FRE | MIPS_CONF5_UFE; mask 126 arch/mips/kvm/vz.c return mask; mask 147 arch/mips/kvm/vz.c unsigned int mask = kvm_vz_config1_guest_wrmask(vcpu) | MIPS_CONF_M; mask 151 arch/mips/kvm/vz.c mask |= MIPS_CONF1_FP; mask 153 arch/mips/kvm/vz.c return mask; mask 163 arch/mips/kvm/vz.c unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M | mask 168 arch/mips/kvm/vz.c mask |= MIPS_CONF3_MSA; mask 170 arch/mips/kvm/vz.c return mask; mask 723 arch/mips/kvm/vz.c unsigned long mask, pa; mask 729 arch/mips/kvm/vz.c mask = (unsigned long)0xfc0000000ull; mask 734 arch/mips/kvm/vz.c mask = (unsigned long)0xfc0000000ull; mask 738 arch/mips/kvm/vz.c mask = (unsigned long)0xfe0000000ull; mask 742 arch/mips/kvm/vz.c mask = (unsigned long)0xfe0000000ull; mask 746 arch/mips/kvm/vz.c mask = (unsigned long)0xfe0000000ull; mask 750 arch/mips/kvm/vz.c mask = (unsigned long)0xfe0000000ull; mask 765 arch/mips/kvm/vz.c pa = (segctl << 20) & mask; mask 766 arch/mips/kvm/vz.c pa |= gva32 & ~mask; mask 868 arch/mips/kvm/vz.c unsigned long mask = 0xfffff000 | MIPS_MAAR_S | MIPS_MAAR_VL; mask 871 arch/mips/kvm/vz.c mask |= 0x00ffffff00000000ull; mask 873 arch/mips/kvm/vz.c mask |= MIPS_MAAR_VH; mask 886 arch/mips/kvm/vz.c return val & mask; mask 1792 arch/mips/kvm/vz.c s64 mask, ret = v; mask 1799 arch/mips/kvm/vz.c mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI; mask 1800 arch/mips/kvm/vz.c ret &= ~mask; mask 1801 arch/mips/kvm/vz.c ret |= ((s64)v & mask) << 32; mask 1808 arch/mips/kvm/vz.c unsigned long mask, ret = v; mask 1815 arch/mips/kvm/vz.c mask = MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI; mask 1816 arch/mips/kvm/vz.c ret &= ~mask; mask 1817 arch/mips/kvm/vz.c ret |= (v >> 32) & mask; mask 86 arch/mips/lasat/at93c.c u32 mask = (1 << shift); mask 89 arch/mips/lasat/at93c.c at93c_write_databit((data & mask) >> shift); mask 24 arch/mips/lib/bitops.c unsigned long mask; mask 28 arch/mips/lib/bitops.c mask = 1UL << bit; mask 30 arch/mips/lib/bitops.c *a |= mask; mask 46 arch/mips/lib/bitops.c unsigned long mask; mask 50 arch/mips/lib/bitops.c mask = 1UL << bit; mask 52 arch/mips/lib/bitops.c *a &= ~mask; mask 68 arch/mips/lib/bitops.c unsigned long mask; mask 72 arch/mips/lib/bitops.c mask = 1UL << bit; mask 74 arch/mips/lib/bitops.c *a ^= mask; mask 91 arch/mips/lib/bitops.c unsigned long mask; mask 96 arch/mips/lib/bitops.c mask = 1UL << bit; mask 98 arch/mips/lib/bitops.c res = (mask & *a) != 0; mask 99 arch/mips/lib/bitops.c *a |= mask; mask 117 arch/mips/lib/bitops.c unsigned long mask; mask 122 arch/mips/lib/bitops.c mask = 1UL << bit; mask 124 arch/mips/lib/bitops.c res = (mask & *a) != 0; mask 125 arch/mips/lib/bitops.c *a |= mask; mask 142 arch/mips/lib/bitops.c unsigned long mask; mask 147 arch/mips/lib/bitops.c mask = 1UL << bit; mask 149 arch/mips/lib/bitops.c res = (mask & *a) != 0; mask 150 arch/mips/lib/bitops.c *a &= ~mask; mask 167 arch/mips/lib/bitops.c unsigned long mask; mask 172 arch/mips/lib/bitops.c mask = 1UL << bit; mask 174 arch/mips/lib/bitops.c res = (mask & *a) != 0; mask 175 arch/mips/lib/bitops.c *a ^= mask; mask 47 arch/mips/lib/dump_tlb.c static inline const char *msk2str(unsigned int mask) mask 49 arch/mips/lib/dump_tlb.c switch (mask) { mask 112 arch/mips/loongson32/common/time.c .mask = CLOCKSOURCE_MASK(24), mask 196 arch/mips/loongson64/common/cs5536/cs5536_mfgpt.c .mask = CLOCKSOURCE_MASK(32), mask 274 arch/mips/loongson64/loongson-3/hpet.c .mask = CLOCKSOURCE_MASK(32), mask 240 arch/mips/loongson64/loongson-3/smp.c loongson3_send_ipi_mask(const struct cpumask *mask, unsigned int action) mask 244 arch/mips/loongson64/loongson-3/smp.c for_each_cpu(i, mask) mask 910 arch/mips/math-emu/cp1emu.c u32 mask; mask 923 arch/mips/math-emu/cp1emu.c mask = boot_cpu_data.fpu_msk31; mask 924 arch/mips/math-emu/cp1emu.c fcr31 = (value & ~mask) | (fcr31 & mask); mask 70 arch/mips/mm/c-octeon.c cpumask_t mask; mask 84 arch/mips/mm/c-octeon.c mask = *mm_cpumask(vma->vm_mm); mask 86 arch/mips/mm/c-octeon.c mask = *cpu_online_mask; mask 87 arch/mips/mm/c-octeon.c cpumask_clear_cpu(cpu, &mask); mask 88 arch/mips/mm/c-octeon.c for_each_cpu(cpu, &mask) mask 541 arch/mips/mm/c-r4k.c const cpumask_t *mask = cpu_present_mask; mask 554 arch/mips/mm/c-r4k.c mask = &cpu_sibling_map[smp_processor_id()]; mask 556 arch/mips/mm/c-r4k.c for_each_cpu(i, mask) mask 426 arch/mips/mm/tlb-r4k.c static unsigned int mask = -1; mask 428 arch/mips/mm/tlb-r4k.c if (mask == -1) { /* first call comes during __init */ mask 434 arch/mips/mm/tlb-r4k.c mask = read_c0_pagemask(); mask 438 arch/mips/mm/tlb-r4k.c return mask == PM_HUGE_MASK; mask 999 arch/mips/mm/tlbex.c unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); mask 1019 arch/mips/mm/tlbex.c uasm_i_andi(p, ctx, ctx, mask); mask 172 arch/mips/mti-malta/malta-init.c u32 start, map, mask, data; mask 248 arch/mips/mti-malta/malta-init.c mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH; mask 249 arch/mips/mti-malta/malta-init.c MSC_WRITE(MSC01_PCI_BAR0, mask); mask 250 arch/mips/mti-malta/malta-init.c MSC_WRITE(MSC01_PCI_HEAD4, mask); mask 252 arch/mips/mti-malta/malta-init.c mask &= MSC01_PCI_BAR0_SIZE_MSK; mask 253 arch/mips/mti-malta/malta-init.c MSC_WRITE(MSC01_PCI_P2SCMSKL, mask); mask 254 arch/mips/mti-malta/malta-init.c MSC_WRITE(MSC01_PCI_P2SCMAPL, mask); mask 76 arch/mips/netlogic/common/smp.c void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) mask 80 arch/mips/netlogic/common/smp.c for_each_cpu(cpu, mask) { mask 88 arch/mips/netlogic/common/time.c csrc_pic.mask = CLOCKSOURCE_MASK(32); mask 91 arch/mips/netlogic/common/time.c csrc_pic.mask = CLOCKSOURCE_MASK(64); mask 113 arch/mips/netlogic/xlp/wakeup.c uint32_t syscoremask, mask, fusemask; mask 140 arch/mips/netlogic/xlp/wakeup.c mask = 0xff; mask 144 arch/mips/netlogic/xlp/wakeup.c mask = 0xfffff; mask 152 arch/mips/netlogic/xlp/wakeup.c mask = 0xf; mask 155 arch/mips/netlogic/xlp/wakeup.c mask = 0x3; mask 159 arch/mips/netlogic/xlp/wakeup.c mask = 0xff; mask 168 arch/mips/netlogic/xlp/wakeup.c syscoremask = (1 << hweight32(~fusemask & mask)) - 1; mask 145 arch/mips/netlogic/xlr/platform-flash.c u32 base, mask; mask 148 arch/mips/netlogic/xlr/platform-flash.c mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); mask 151 arch/mips/netlogic/xlr/platform-flash.c res->end = res->start + (mask + 1) * 64 * 1024; mask 68 arch/mips/paravirt/paravirt-irq.c unsigned int mask = 0x100 << cd->bit; mask 74 arch/mips/paravirt/paravirt-irq.c set_c0_status(mask); mask 76 arch/mips/paravirt/paravirt-irq.c clear_c0_status(mask); mask 175 arch/mips/paravirt/paravirt-irq.c u32 mask = 1u << data->irq; mask 177 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); mask 182 arch/mips/paravirt/paravirt-irq.c u32 mask = 1u << data->irq; mask 184 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); mask 193 arch/mips/paravirt/paravirt-irq.c u32 mask = 1u << data->irq; mask 195 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); mask 200 arch/mips/paravirt/paravirt-irq.c u32 mask = 1u << data->irq; mask 202 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); mask 218 arch/mips/paravirt/paravirt-irq.c u32 mask; mask 224 arch/mips/paravirt/paravirt-irq.c mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox); mask 225 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); mask 241 arch/mips/paravirt/paravirt-irq.c u32 mask; mask 246 arch/mips/paravirt/paravirt-irq.c mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox); mask 247 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32)); mask 253 arch/mips/paravirt/paravirt-irq.c u32 mask; mask 257 arch/mips/paravirt/paravirt-irq.c mask = actions << (cpuid * MBOX_BITS_PER_CPU); mask 258 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32)); mask 265 arch/mips/paravirt/paravirt-irq.c u32 mask; mask 269 arch/mips/paravirt/paravirt-irq.c mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox); mask 270 arch/mips/paravirt/paravirt-irq.c __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); mask 75 arch/mips/paravirt/paravirt-smp.c static void paravirt_send_ipi_mask(const struct cpumask *mask, unsigned int action) mask 79 arch/mips/paravirt/paravirt-smp.c for_each_cpu(cpu, mask) mask 21 arch/mips/pci/ops-nile4.c u32 adr, mask, err; mask 40 arch/mips/pci/ops-nile4.c mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; mask 67 arch/mips/pci/ops-nile4.c vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; mask 202 arch/mips/pci/pci-ar2315.c u32 mask, u32 val) mask 206 arch/mips/pci/pci-ar2315.c ret &= ~mask; mask 217 arch/mips/pci/pci-ar2315.c u32 mask = 0xffffffff >> 8 * (4 - size); mask 241 arch/mips/pci/pci-ar2315.c value = (value & ~(mask << sh)) | *ptr << sh; mask 247 arch/mips/pci/pci-ar2315.c *ptr = (value >> sh) & mask; mask 247 arch/mips/pci/pci-legacy.c static int pcibios_enable_resources(struct pci_dev *dev, int mask) mask 257 arch/mips/pci/pci-legacy.c if (!(mask & (1<<idx))) mask 283 arch/mips/pci/pci-legacy.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 287 arch/mips/pci/pci-legacy.c if ((err = pcibios_enable_resources(dev, mask)) < 0) mask 81 arch/mips/pci/pci-malta.c resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; mask 117 arch/mips/pci/pci-malta.c mask = ~(start ^ end); mask 120 arch/mips/pci/pci-malta.c mask != ~((mask & -mask) - 1)); mask 123 arch/mips/pci/pci-malta.c gt64120_controller.mem_offset = (start & mask) - (map & mask); mask 134 arch/mips/pci/pci-malta.c mask = ~(start ^ end); mask 137 arch/mips/pci/pci-malta.c mask != ~((mask & -mask) - 1)); mask 138 arch/mips/pci/pci-malta.c gt64120_io_resource.start = map & mask; mask 139 arch/mips/pci/pci-malta.c gt64120_io_resource.end = (map & mask) | ~mask; mask 187 arch/mips/pci/pci-malta.c MSC_READ(MSC01_PCI_SC2PMMSKL, mask); mask 189 arch/mips/pci/pci-malta.c msc_mem_resource.start = start & mask; mask 190 arch/mips/pci/pci-malta.c msc_mem_resource.end = (start & mask) | ~mask; mask 191 arch/mips/pci/pci-malta.c msc_controller.mem_offset = (start & mask) - (map & mask); mask 194 arch/mips/pci/pci-malta.c write_gcr_reg0_mask(mask | mask 198 arch/mips/pci/pci-malta.c MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); mask 200 arch/mips/pci/pci-malta.c msc_io_resource.start = map & mask; mask 201 arch/mips/pci/pci-malta.c msc_io_resource.end = (map & mask) | ~mask; mask 203 arch/mips/pci/pci-malta.c ioport_resource.end = ~mask; mask 206 arch/mips/pci/pci-malta.c write_gcr_reg1_mask(mask | mask 210 arch/mips/pci/pci-malta.c start = start & mask; mask 211 arch/mips/pci/pci-malta.c end = start | ~mask; mask 21 arch/mips/pci/pci-vr41xx.h #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U) mask 23 arch/mips/pci/pci-vr41xx.h #define TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U) mask 25 arch/mips/pci/pci-xtalk-bridge.c u32 cf, shift, mask; mask 42 arch/mips/pci/pci-xtalk-bridge.c mask = 0xffffffffU >> ((4 - size) << 3); mask 43 arch/mips/pci/pci-xtalk-bridge.c *value = (cf >> shift) & mask; mask 50 arch/mips/pci/pci-xtalk-bridge.c u32 cf, shift, mask, smask; mask 59 arch/mips/pci/pci-xtalk-bridge.c mask = (0xffffffffU >> ((4 - size) << 3)); mask 60 arch/mips/pci/pci-xtalk-bridge.c smask = mask << shift; mask 62 arch/mips/pci/pci-xtalk-bridge.c cf = (cf & ~smask) | ((value & mask) << shift); mask 275 arch/mips/pci/pci-xtalk-bridge.c static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask, mask 284 arch/mips/pci/pci-xtalk-bridge.c ret = irq_chip_set_affinity_parent(d, mask, force); mask 286 arch/mips/pci/pci-xtalk-bridge.c cpu = cpumask_first_and(mask, cpu_online_mask); mask 295 arch/mips/pci/pci-xtalk-bridge.c return irq_chip_set_affinity_parent(d, mask, force); mask 26 arch/mips/pic32/pic32mzda/config.c static u32 pic32_conf_get_reg_field(u32 offset, u32 rshift, u32 mask) mask 32 arch/mips/pic32/pic32mzda/config.c v &= mask; mask 37 arch/mips/pic32/pic32mzda/config.c static u32 pic32_conf_modify_atomic(u32 offset, u32 mask, u32 set) mask 44 arch/mips/pic32/pic32mzda/config.c v &= ~mask; mask 45 arch/mips/pic32/pic32mzda/config.c v |= (set & mask); mask 64 arch/mips/pic32/pic32mzda/config.c u32 mask = mode ? BIT(30) : 0; mask 66 arch/mips/pic32/pic32mzda/config.c return pic32_conf_modify_atomic(PIC32_CFGCON2, BIT(30), mask); mask 100 arch/mips/pnx833x/common/interrupts.c unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE; mask 102 arch/mips/pnx833x/common/interrupts.c while ((pin = ffs(mask & 0xffff))) { mask 105 arch/mips/pnx833x/common/interrupts.c mask &= ~(1 << pin); mask 49 arch/mips/rb532/irq.c u32 mask; /* mask of valid bits in pending/mask registers */ mask 61 arch/mips/rb532/irq.c .mask = 0x0000efff, mask 64 arch/mips/rb532/irq.c .mask = 0x00001fff, mask 67 arch/mips/rb532/irq.c .mask = 0x00000007, mask 70 arch/mips/rb532/irq.c .mask = 0x0003ffff, mask 73 arch/mips/rb532/irq.c .mask = 0xffffffff, mask 135 arch/mips/rb532/irq.c unsigned int group, intr_bit, mask, irq_nr = d->irq; mask 147 arch/mips/rb532/irq.c mask = READ_MASK(addr); mask 148 arch/mips/rb532/irq.c mask |= intr_bit; mask 149 arch/mips/rb532/irq.c WRITE_MASK(addr, mask); mask 159 arch/mips/rb532/irq.c if (mask == intr_group[group].mask) mask 113 arch/mips/sgi-ip22/ip22-int.c u8 mask = sgint->istat0 & sgint->imask0; mask 117 arch/mips/sgi-ip22/ip22-int.c if (mask & SGINT_ISTAT0_LIO2) { mask 121 arch/mips/sgi-ip22/ip22-int.c irq = lc0msk_to_irqnr[mask]; mask 135 arch/mips/sgi-ip22/ip22-int.c u8 mask = sgint->istat1 & sgint->imask1; mask 139 arch/mips/sgi-ip22/ip22-int.c if (mask & SGINT_ISTAT1_LIO3) { mask 143 arch/mips/sgi-ip22/ip22-int.c irq = lc1msk_to_irqnr[mask]; mask 53 arch/mips/sgi-ip27/ip27-irq.c unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); mask 55 arch/mips/sgi-ip27/ip27-irq.c set_bit(d->hwirq, mask); mask 56 arch/mips/sgi-ip27/ip27-irq.c __raw_writeq(mask[0], hd->irq_mask[0]); mask 57 arch/mips/sgi-ip27/ip27-irq.c __raw_writeq(mask[1], hd->irq_mask[1]); mask 63 arch/mips/sgi-ip27/ip27-irq.c unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); mask 65 arch/mips/sgi-ip27/ip27-irq.c clear_bit(d->hwirq, mask); mask 66 arch/mips/sgi-ip27/ip27-irq.c __raw_writeq(mask[0], hd->irq_mask[0]); mask 67 arch/mips/sgi-ip27/ip27-irq.c __raw_writeq(mask[1], hd->irq_mask[1]); mask 70 arch/mips/sgi-ip27/ip27-irq.c static void setup_hub_mask(struct hub_irq_data *hd, const struct cpumask *mask) mask 75 arch/mips/sgi-ip27/ip27-irq.c cpu = cpumask_first_and(mask, cpu_online_mask); mask 90 arch/mips/sgi-ip27/ip27-irq.c static int set_affinity_hub_irq(struct irq_data *d, const struct cpumask *mask, mask 101 arch/mips/sgi-ip27/ip27-irq.c setup_hub_mask(hd, mask); mask 190 arch/mips/sgi-ip27/ip27-irq.c unsigned long *mask = per_cpu(irq_enable_mask, cpu); mask 198 arch/mips/sgi-ip27/ip27-irq.c pend0 &= mask[0]; /* Pick intrs we should look at */ mask 232 arch/mips/sgi-ip27/ip27-irq.c unsigned long *mask = per_cpu(irq_enable_mask, cpu); mask 240 arch/mips/sgi-ip27/ip27-irq.c pend1 &= mask[1]; /* Pick intrs we should look at */ mask 257 arch/mips/sgi-ip27/ip27-irq.c unsigned long *mask = per_cpu(irq_enable_mask, cpu); mask 262 arch/mips/sgi-ip27/ip27-irq.c set_bit(resched, mask); mask 266 arch/mips/sgi-ip27/ip27-irq.c set_bit(call, mask); mask 270 arch/mips/sgi-ip27/ip27-irq.c LOCAL_HUB_S(PI_INT_MASK0_A, mask[0]); mask 271 arch/mips/sgi-ip27/ip27-irq.c LOCAL_HUB_S(PI_INT_MASK1_A, mask[1]); mask 273 arch/mips/sgi-ip27/ip27-irq.c LOCAL_HUB_S(PI_INT_MASK0_B, mask[0]); mask 274 arch/mips/sgi-ip27/ip27-irq.c LOCAL_HUB_S(PI_INT_MASK1_B, mask[1]); mask 172 arch/mips/sgi-ip27/ip27-smp.c static void ip27_send_ipi_mask(const struct cpumask *mask, unsigned int action) mask 176 arch/mips/sgi-ip27/ip27-smp.c for_each_cpu(i, mask) mask 129 arch/mips/sgi-ip27/ip27-timer.c .mask = CLOCKSOURCE_MASK(52), mask 77 arch/mips/sibyte/bcm1480/irq.c static int bcm1480_set_affinity(struct irq_data *d, const struct cpumask *mask, mask 85 arch/mips/sibyte/bcm1480/irq.c i = cpumask_first_and(mask, cpu_online_mask); mask 72 arch/mips/sibyte/bcm1480/smp.c static void bcm1480_send_ipi_mask(const struct cpumask *mask, mask 77 arch/mips/sibyte/bcm1480/smp.c for_each_cpu(i, mask) mask 70 arch/mips/sibyte/sb1250/irq.c static int sb1250_set_affinity(struct irq_data *d, const struct cpumask *mask, mask 78 arch/mips/sibyte/sb1250/irq.c i = cpumask_first_and(mask, cpu_online_mask); mask 280 arch/mips/sibyte/sb1250/irq.c unsigned long long mask; mask 287 arch/mips/sibyte/sb1250/irq.c mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu, mask 289 arch/mips/sibyte/sb1250/irq.c if (mask) mask 290 arch/mips/sibyte/sb1250/irq.c do_IRQ(fls64(mask) - 1); mask 61 arch/mips/sibyte/sb1250/smp.c static inline void sb1250_send_ipi_mask(const struct cpumask *mask, mask 66 arch/mips/sibyte/sb1250/smp.c for_each_cpu(i, mask) mask 201 arch/mips/sni/pcimt.c unsigned int mask = 1 << (d->irq - PCIMT_IRQ_INT2); mask 203 arch/mips/sni/pcimt.c *(volatile u8 *) PCIMT_IRQSEL |= mask; mask 208 arch/mips/sni/pcimt.c unsigned int mask = ~(1 << (d->irq - PCIMT_IRQ_INT2)); mask 210 arch/mips/sni/pcimt.c *(volatile u8 *) PCIMT_IRQSEL &= mask; mask 163 arch/mips/sni/pcit.c u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); mask 165 arch/mips/sni/pcit.c *(volatile u32 *)SNI_PCIT_INT_REG |= mask; mask 170 arch/mips/sni/pcit.c u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24); mask 172 arch/mips/sni/pcit.c *(volatile u32 *)SNI_PCIT_INT_REG &= ~mask; mask 160 arch/mips/sni/rm200.c unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; mask 163 arch/mips/sni/rm200.c mask = 1 << irq; mask 165 arch/mips/sni/rm200.c rm200_cached_irq_mask |= mask; mask 175 arch/mips/sni/rm200.c unsigned int mask, irq = d->irq - RM200_I8259A_IRQ_BASE; mask 178 arch/mips/sni/rm200.c mask = ~(1 << irq); mask 180 arch/mips/sni/rm200.c rm200_cached_irq_mask &= mask; mask 432 arch/mips/sni/rm200.c unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); mask 434 arch/mips/sni/rm200.c *(volatile u8 *)SNI_RM200_INT_ENA_REG &= ~mask; mask 439 arch/mips/sni/rm200.c unsigned int mask = 1 << (d->irq - SNI_RM200_INT_START); mask 441 arch/mips/sni/rm200.c *(volatile u8 *)SNI_RM200_INT_ENA_REG |= mask; mask 453 arch/mips/sni/rm200.c u8 mask; mask 461 arch/mips/sni/rm200.c mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; mask 463 arch/mips/sni/rm200.c irq = ffs(stat & mask & 0x1f); mask 142 arch/mips/vr41xx/common/icu.c void vr41xx_enable_piuint(uint16_t mask) mask 150 arch/mips/vr41xx/common/icu.c icu1_set(MPIUINTREG, mask); mask 157 arch/mips/vr41xx/common/icu.c void vr41xx_disable_piuint(uint16_t mask) mask 165 arch/mips/vr41xx/common/icu.c icu1_clear(MPIUINTREG, mask); mask 172 arch/mips/vr41xx/common/icu.c void vr41xx_enable_aiuint(uint16_t mask) mask 180 arch/mips/vr41xx/common/icu.c icu1_set(MAIUINTREG, mask); mask 187 arch/mips/vr41xx/common/icu.c void vr41xx_disable_aiuint(uint16_t mask) mask 195 arch/mips/vr41xx/common/icu.c icu1_clear(MAIUINTREG, mask); mask 202 arch/mips/vr41xx/common/icu.c void vr41xx_enable_kiuint(uint16_t mask) mask 210 arch/mips/vr41xx/common/icu.c icu1_set(MKIUINTREG, mask); mask 217 arch/mips/vr41xx/common/icu.c void vr41xx_disable_kiuint(uint16_t mask) mask 225 arch/mips/vr41xx/common/icu.c icu1_clear(MKIUINTREG, mask); mask 232 arch/mips/vr41xx/common/icu.c void vr41xx_enable_macint(uint16_t mask) mask 238 arch/mips/vr41xx/common/icu.c icu1_set(MMACINTREG, mask); mask 244 arch/mips/vr41xx/common/icu.c void vr41xx_disable_macint(uint16_t mask) mask 250 arch/mips/vr41xx/common/icu.c icu1_clear(MMACINTREG, mask); mask 256 arch/mips/vr41xx/common/icu.c void vr41xx_enable_dsiuint(uint16_t mask) mask 262 arch/mips/vr41xx/common/icu.c icu1_set(MDSIUINTREG, mask); mask 268 arch/mips/vr41xx/common/icu.c void vr41xx_disable_dsiuint(uint16_t mask) mask 274 arch/mips/vr41xx/common/icu.c icu1_clear(MDSIUINTREG, mask); mask 280 arch/mips/vr41xx/common/icu.c void vr41xx_enable_firint(uint16_t mask) mask 286 arch/mips/vr41xx/common/icu.c icu2_set(MFIRINTREG, mask); mask 292 arch/mips/vr41xx/common/icu.c void vr41xx_disable_firint(uint16_t mask) mask 298 arch/mips/vr41xx/common/icu.c icu2_clear(MFIRINTREG, mask); mask 368 arch/mips/vr41xx/common/icu.c void vr41xx_enable_csiint(uint16_t mask) mask 377 arch/mips/vr41xx/common/icu.c icu2_set(MCSIINTREG, mask); mask 384 arch/mips/vr41xx/common/icu.c void vr41xx_disable_csiint(uint16_t mask) mask 393 arch/mips/vr41xx/common/icu.c icu2_clear(MCSIINTREG, mask); mask 374 arch/nds32/include/asm/pgtable.h const unsigned long mask = 0xfff; mask 375 arch/nds32/include/asm/pgtable.h pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); mask 160 arch/nds32/kernel/perf_event_cpu.c u32 mask = 0; mask 164 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_OVF[0]; mask 167 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_OVF[1]; mask 170 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_OVF[2]; mask 176 arch/nds32/kernel/perf_event_cpu.c return pfm & mask; mask 295 arch/nds32/kernel/perf_event_cpu.c u32 mask = 0; mask 297 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_EN[idx]; mask 298 arch/nds32/kernel/perf_event_cpu.c val &= ~mask; mask 373 arch/nds32/kernel/perf_event_cpu.c u32 mask = 0; mask 375 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_EN[idx]; mask 376 arch/nds32/kernel/perf_event_cpu.c val |= mask; mask 385 arch/nds32/kernel/perf_event_cpu.c u32 mask = 0; mask 387 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_IE[idx]; mask 388 arch/nds32/kernel/perf_event_cpu.c val |= mask; mask 397 arch/nds32/kernel/perf_event_cpu.c u32 mask = 0; mask 399 arch/nds32/kernel/perf_event_cpu.c mask = PFM_CTL_IE[idx]; mask 400 arch/nds32/kernel/perf_event_cpu.c val &= ~mask; mask 212 arch/nds32/kernel/vdso.c vdso_data->cs_mask = tk->tkr_mono.mask; mask 78 arch/nds32/mm/fault.c unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; mask 170 arch/nds32/mm/fault.c mask = VM_EXEC; mask 172 arch/nds32/mm/fault.c mask = VM_READ | VM_WRITE; mask 177 arch/nds32/mm/fault.c mask = VM_READ; mask 180 arch/nds32/mm/fault.c mask = VM_WRITE; mask 184 arch/nds32/mm/fault.c mask = VM_EXEC; mask 187 arch/nds32/mm/fault.c mask = VM_WRITE; mask 197 arch/nds32/mm/fault.c if (!(vma->vm_flags & mask)) mask 19 arch/nios2/include/asm/asm-macros.h .macro ANDI32 reg1, reg2, mask mask 39 arch/nios2/include/asm/asm-macros.h .macro ORI32 reg1, reg2, mask mask 58 arch/nios2/include/asm/asm-macros.h .macro XORI32 reg1, reg2, mask mask 262 arch/nios2/include/asm/asm-macros.h .macro TSTBZ reg1, reg2, mask, label mask 274 arch/nios2/include/asm/asm-macros.h .macro TSTBNZ reg1, reg2, mask, label mask 181 arch/nios2/include/asm/pgtable.h const unsigned long mask = _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC; mask 183 arch/nios2/include/asm/pgtable.h pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); mask 103 arch/nios2/kernel/time.c .mask = CLOCKSOURCE_MASK(32), mask 14 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 25 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(mask) mask 31 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 42 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(~mask) mask 48 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 59 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(mask) mask 65 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 77 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(mask) mask 80 arch/openrisc/include/asm/bitops/atomic.h return (old & mask) != 0; mask 85 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 97 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(~mask) mask 100 arch/openrisc/include/asm/bitops/atomic.h return (old & mask) != 0; mask 105 arch/openrisc/include/asm/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 117 arch/openrisc/include/asm/bitops/atomic.h : "r"(p), "r"(mask) mask 120 arch/openrisc/include/asm/bitops/atomic.h return (old & mask) != 0; mask 21 arch/openrisc/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 233 arch/openrisc/kernel/setup.c static inline unsigned long extract_value(unsigned long reg, unsigned long mask) mask 235 arch/openrisc/kernel/setup.c while (!(mask & 0x1)) { mask 237 arch/openrisc/kernel/setup.c mask = mask >> 1; mask 239 arch/openrisc/kernel/setup.c return mask & reg; mask 242 arch/openrisc/kernel/setup.c void __init detect_unit_config(unsigned long upr, unsigned long mask, mask 248 arch/openrisc/kernel/setup.c if (upr & mask) { mask 210 arch/openrisc/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 212 arch/openrisc/kernel/smp.c smp_cross_call(mask, IPI_CALL_FUNC); mask 145 arch/openrisc/kernel/time.c .mask = CLOCKSOURCE_MASK(32), mask 38 arch/parisc/include/asm/bitops.h unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); mask 43 arch/parisc/include/asm/bitops.h *addr |= mask; mask 49 arch/parisc/include/asm/bitops.h unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr)); mask 54 arch/parisc/include/asm/bitops.h *addr &= mask; mask 60 arch/parisc/include/asm/bitops.h unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); mask 65 arch/parisc/include/asm/bitops.h *addr ^= mask; mask 71 arch/parisc/include/asm/bitops.h unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); mask 79 arch/parisc/include/asm/bitops.h set = (old & mask) ? 1 : 0; mask 81 arch/parisc/include/asm/bitops.h *addr = old | mask; mask 89 arch/parisc/include/asm/bitops.h unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); mask 97 arch/parisc/include/asm/bitops.h set = (old & mask) ? 1 : 0; mask 99 arch/parisc/include/asm/bitops.h *addr = old & ~mask; mask 107 arch/parisc/include/asm/bitops.h unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr); mask 114 arch/parisc/include/asm/bitops.h *addr = oldbit ^ mask; mask 117 arch/parisc/include/asm/bitops.h return (oldbit & mask) ? 1 : 0; mask 33 arch/parisc/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 1225 arch/parisc/kernel/hardware.c unsigned short mask; mask 1368 arch/parisc/kernel/hardware.c for (ptr = hp_cpu_type_mask_list; 0 != ptr->mask; ptr++) { mask 1369 arch/parisc/kernel/hardware.c if (ptr->model == (model & ptr->mask)) mask 72 arch/parisc/kernel/irq.c unsigned long mask = EIEM_MASK(d->irq); mask 76 arch/parisc/kernel/irq.c per_cpu(local_ack_eiem, cpu) &= ~mask; mask 82 arch/parisc/kernel/irq.c mtctl(mask, 23); mask 87 arch/parisc/kernel/irq.c unsigned long mask = EIEM_MASK(d->irq); mask 91 arch/parisc/kernel/irq.c per_cpu(local_ack_eiem, cpu) |= mask; mask 589 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); mask 594 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); mask 610 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); mask 615 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); mask 726 arch/parisc/kernel/module.c *loc = mask(*loc, 21) | reassemble_21(val); mask 736 arch/parisc/kernel/module.c *loc = mask(*loc, 14) | reassemble_14(val); mask 225 arch/parisc/kernel/pci-dma.c #define PCXL_SEARCH_LOOP(idx, mask, size) \ mask 228 arch/parisc/kernel/pci-dma.c if(0 == ((*res_ptr) & mask)) { \ mask 229 arch/parisc/kernel/pci-dma.c *res_ptr |= mask; \ mask 236 arch/parisc/kernel/pci-dma.c #define PCXL_FIND_FREE_MAPPING(idx, mask, size) { \ mask 239 arch/parisc/kernel/pci-dma.c PCXL_SEARCH_LOOP(idx, mask, size); \ mask 241 arch/parisc/kernel/pci-dma.c PCXL_SEARCH_LOOP(idx, mask, size); \ mask 248 arch/parisc/kernel/pci-dma.c u_long mask, flags; mask 251 arch/parisc/kernel/pci-dma.c mask = (u_long) -1L; mask 252 arch/parisc/kernel/pci-dma.c mask >>= BITS_PER_LONG - pages_needed; mask 255 arch/parisc/kernel/pci-dma.c size, pages_needed, mask); mask 260 arch/parisc/kernel/pci-dma.c PCXL_FIND_FREE_MAPPING(res_idx, mask, 8); mask 262 arch/parisc/kernel/pci-dma.c PCXL_FIND_FREE_MAPPING(res_idx, mask, 16); mask 264 arch/parisc/kernel/pci-dma.c PCXL_FIND_FREE_MAPPING(res_idx, mask, 32); mask 277 arch/parisc/kernel/pci-dma.c res_idx, mask, pcxl_res_hint); mask 303 arch/parisc/kernel/pci-dma.c u_long mask, flags; mask 307 arch/parisc/kernel/pci-dma.c mask = (u_long) -1L; mask 308 arch/parisc/kernel/pci-dma.c mask >>= BITS_PER_LONG - pages_mapped; mask 311 arch/parisc/kernel/pci-dma.c res_idx, size, pages_mapped, mask); mask 316 arch/parisc/kernel/pci-dma.c PCXL_FREE_MAPPINGS(res_idx, mask, 8); mask 318 arch/parisc/kernel/pci-dma.c PCXL_FREE_MAPPINGS(res_idx, mask, 16); mask 320 arch/parisc/kernel/pci-dma.c PCXL_FREE_MAPPINGS(res_idx, mask, 32); mask 201 arch/parisc/kernel/pci.c resource_size_t mask, align, start = res->start; mask 212 arch/parisc/kernel/pci.c mask = max(alignment, align) - 1; mask 213 arch/parisc/kernel/pci.c start += mask; mask 214 arch/parisc/kernel/pci.c start &= ~mask; mask 227 arch/parisc/kernel/pci.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 232 arch/parisc/kernel/pci.c err = pci_enable_resources(dev, mask); mask 201 arch/parisc/kernel/smp.c send_IPI_mask(const struct cpumask *mask, enum ipi_message_type op) mask 205 arch/parisc/kernel/smp.c for_each_cpu(cpu, mask) mask 241 arch/parisc/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 243 arch/parisc/kernel/smp.c send_IPI_mask(mask, IPI_CALL_FUNC); mask 152 arch/parisc/kernel/time.c .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), mask 56 arch/parisc/kernel/traps.c unsigned long mask = 1UL << (nbits - 1); mask 57 arch/parisc/kernel/traps.c while (mask != 0) { mask 58 arch/parisc/kernel/traps.c *buf++ = (mask & x ? '1' : '0'); mask 59 arch/parisc/kernel/traps.c mask >>= 1; mask 159 arch/powerpc/boot/4xx.c #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) mask 67 arch/powerpc/include/asm/bitops.h static __inline__ void fn(unsigned long mask, \ mask 80 arch/powerpc/include/asm/bitops.h : "r" (mask), "r" (p) \ mask 113 arch/powerpc/include/asm/bitops.h unsigned long mask, \ mask 127 arch/powerpc/include/asm/bitops.h : "r" (mask), "r" (p) \ mask 129 arch/powerpc/include/asm/bitops.h return (old & mask); \ mask 172 arch/powerpc/include/asm/bitops.h unsigned long mask = BIT_MASK(nr); mask 182 arch/powerpc/include/asm/bitops.h : "r" (mask), "r" (p) mask 187 arch/powerpc/include/asm/book3s/64/hash.h __be64 old, tmp, val, mask; mask 189 arch/powerpc/include/asm/book3s/64/hash.h mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE | mask 192 arch/powerpc/include/asm/book3s/64/hash.h val = pte_raw(entry) & mask; mask 423 arch/powerpc/include/asm/book3s/64/mmu-hash.h unsigned long mask; mask 426 arch/powerpc/include/asm/book3s/64/mmu-hash.h mask = (1ul << (s_shift - VPN_SHIFT)) - 1; mask 427 arch/powerpc/include/asm/book3s/64/mmu-hash.h return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); mask 436 arch/powerpc/include/asm/book3s/64/mmu-hash.h unsigned long mask; mask 441 arch/powerpc/include/asm/book3s/64/mmu-hash.h mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; mask 443 arch/powerpc/include/asm/book3s/64/mmu-hash.h ((vpn & mask) >> (shift - VPN_SHIFT)); mask 445 arch/powerpc/include/asm/book3s/64/mmu-hash.h mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; mask 448 arch/powerpc/include/asm/book3s/64/mmu-hash.h ((vpn & mask) >> (shift - VPN_SHIFT)) ; mask 706 arch/powerpc/include/asm/book3s/64/pgtable.h u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); mask 708 arch/powerpc/include/asm/book3s/64/pgtable.h return (pte_raw(pte) & mask) == mask; mask 84 arch/powerpc/include/asm/cell-pmu.h extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask); mask 226 arch/powerpc/include/asm/eeh.h unsigned long addr, unsigned long mask); mask 320 arch/powerpc/include/asm/eeh.h unsigned long addr, unsigned long mask); mask 200 arch/powerpc/include/asm/epapr_hcalls.h unsigned int mask) mask 208 arch/powerpc/include/asm/epapr_hcalls.h r4 = mask; mask 226 arch/powerpc/include/asm/epapr_hcalls.h unsigned int *mask) mask 240 arch/powerpc/include/asm/epapr_hcalls.h *mask = r4; mask 37 arch/powerpc/include/asm/fsl_pm.h void (*set_ip_power)(bool enable, u32 mask); mask 42 arch/powerpc/include/asm/hvsi.h __be32 mask; mask 83 arch/powerpc/include/asm/hw_irq.h static inline notrace void irq_soft_mask_set(unsigned long mask) mask 100 arch/powerpc/include/asm/hw_irq.h WARN_ON(mask && !(mask & IRQS_DISABLED)); mask 106 arch/powerpc/include/asm/hw_irq.h : "r" (mask), mask 111 arch/powerpc/include/asm/hw_irq.h static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask) mask 116 arch/powerpc/include/asm/hw_irq.h WARN_ON(mask && !(mask & IRQS_DISABLED)); mask 123 arch/powerpc/include/asm/hw_irq.h "r" (mask) mask 129 arch/powerpc/include/asm/hw_irq.h static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask) mask 137 arch/powerpc/include/asm/hw_irq.h "r" (mask) mask 141 arch/powerpc/include/asm/hw_irq.h WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED)); mask 147 arch/powerpc/include/asm/iommu.h extern int dma_iommu_dma_supported(struct device *dev, u64 mask); mask 245 arch/powerpc/include/asm/iommu.h static inline int dma_iommu_dma_supported(struct device *dev, u64 mask) mask 254 arch/powerpc/include/asm/iommu.h unsigned long mask, mask 265 arch/powerpc/include/asm/iommu.h unsigned long mask, gfp_t flag, int node); mask 270 arch/powerpc/include/asm/iommu.h size_t size, unsigned long mask, mask 70 arch/powerpc/include/asm/ipic.h extern void ipic_clear_mcp_status(u32 mask); mask 65 arch/powerpc/include/asm/irq.h int irq_choose_cpu(const struct cpumask *mask); mask 264 arch/powerpc/include/asm/kvm_book3s.h unsigned long mask); mask 489 arch/powerpc/include/asm/kvm_book3s_64.h unsigned long mask = (pagesize >> PAGE_SHIFT) - 1; mask 493 arch/powerpc/include/asm/kvm_book3s_64.h return !(memslot->base_gfn & mask) && !(memslot->npages & mask); mask 366 arch/powerpc/include/asm/kvm_ppc.h u32 mask; mask 370 arch/powerpc/include/asm/kvm_ppc.h mask = (1 << (lsb - msb + 1)) - 1; mask 371 arch/powerpc/include/asm/kvm_ppc.h r = (inst >> (63 - lsb)) & mask; mask 382 arch/powerpc/include/asm/kvm_ppc.h u32 mask; mask 386 arch/powerpc/include/asm/kvm_ppc.h mask = ((1 << (lsb - msb + 1)) - 1) << (63 - lsb); mask 387 arch/powerpc/include/asm/kvm_ppc.h r = (inst & ~mask) | ((value << (63 - lsb)) & mask); mask 12 arch/powerpc/include/asm/nmi.h extern void arch_trigger_cpumask_backtrace(const cpumask_t *mask, mask 94 arch/powerpc/include/asm/opal.h uint32_t func, uint64_t addr, uint64_t mask); mask 21 arch/powerpc/include/asm/pci-bridge.h u64 mask); mask 64 arch/powerpc/include/asm/pmac_pfunc.h int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask); mask 65 arch/powerpc/include/asm/pmac_pfunc.h int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor); mask 67 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask); mask 69 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask); mask 71 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask); mask 76 arch/powerpc/include/asm/pmac_pfunc.h int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask); mask 77 arch/powerpc/include/asm/pmac_pfunc.h int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask); mask 78 arch/powerpc/include/asm/pmac_pfunc.h int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask); mask 97 arch/powerpc/include/asm/pmac_pfunc.h int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, mask 99 arch/powerpc/include/asm/pmac_pfunc.h int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, mask 101 arch/powerpc/include/asm/pmac_pfunc.h int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, mask 104 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask); mask 105 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask); mask 106 arch/powerpc/include/asm/pmac_pfunc.h int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask); mask 509 arch/powerpc/include/asm/ps3.h void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask); mask 592 arch/powerpc/include/asm/ps3av.h u32 mask; /* in: mask */ mask 14 arch/powerpc/include/asm/setup.h extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); mask 239 arch/powerpc/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 20 arch/powerpc/include/asm/spu_priv1.h void (*int_mask_and) (struct spu *spu, int class, u64 mask); mask 21 arch/powerpc/include/asm/spu_priv1.h void (*int_mask_or) (struct spu *spu, int class, u64 mask); mask 22 arch/powerpc/include/asm/spu_priv1.h void (*int_mask_set) (struct spu *spu, int class, u64 mask); mask 45 arch/powerpc/include/asm/spu_priv1.h spu_int_mask_and (struct spu *spu, int class, u64 mask) mask 47 arch/powerpc/include/asm/spu_priv1.h spu_priv1_ops->int_mask_and(spu, class, mask); mask 51 arch/powerpc/include/asm/spu_priv1.h spu_int_mask_or (struct spu *spu, int class, u64 mask) mask 53 arch/powerpc/include/asm/spu_priv1.h spu_priv1_ops->int_mask_or(spu, class, mask); mask 57 arch/powerpc/include/asm/spu_priv1.h spu_int_mask_set (struct spu *spu, int class, u64 mask) mask 59 arch/powerpc/include/asm/spu_priv1.h spu_priv1_ops->int_mask_set(spu, class, mask); mask 77 arch/powerpc/include/asm/syscall.h unsigned long val, mask = -1UL; mask 82 arch/powerpc/include/asm/syscall.h mask = 0xffffffff; mask 90 arch/powerpc/include/asm/syscall.h args[n] = val & mask; mask 23 arch/powerpc/include/asm/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; mask 24 arch/powerpc/include/asm/word-at-a-time.h return ~(mask | rhs); mask 27 arch/powerpc/include/asm/word-at-a-time.h #define create_zero_mask(mask) (mask) mask 29 arch/powerpc/include/asm/word-at-a-time.h static inline long find_zero(unsigned long mask) mask 33 arch/powerpc/include/asm/word-at-a-time.h asm (PPC_CNTLZL "%0,%1" : "=r" (leading_zero_bits) : "r" (mask)); mask 44 arch/powerpc/include/asm/word-at-a-time.h static inline unsigned long zero_bytemask(unsigned long mask) mask 46 arch/powerpc/include/asm/word-at-a-time.h return ~1ul << __fls(mask); mask 91 arch/powerpc/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 93 arch/powerpc/include/asm/word-at-a-time.h return mask >> 3; mask 97 arch/powerpc/include/asm/word-at-a-time.h static inline unsigned long zero_bytemask(unsigned long mask) mask 99 arch/powerpc/include/asm/word-at-a-time.h return (1UL << mask) - 1; mask 119 arch/powerpc/include/asm/word-at-a-time.h static inline long count_masked_bytes(long mask) mask 122 arch/powerpc/include/asm/word-at-a-time.h long a = (0x0ff0001+mask) >> 23; mask 124 arch/powerpc/include/asm/word-at-a-time.h return a & mask; mask 133 arch/powerpc/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 135 arch/powerpc/include/asm/word-at-a-time.h return count_masked_bytes(mask); mask 141 arch/powerpc/include/asm/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 142 arch/powerpc/include/asm/word-at-a-time.h *bits = mask; mask 143 arch/powerpc/include/asm/word-at-a-time.h return mask; mask 152 arch/powerpc/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 654 arch/powerpc/kernel/cacheinfo.c const struct cpumask *mask; mask 662 arch/powerpc/kernel/cacheinfo.c mask = get_big_core_shared_cpu_map(cpu, cache); mask 664 arch/powerpc/kernel/cacheinfo.c mask = &cache->shared_cpu_map; mask 668 arch/powerpc/kernel/cacheinfo.c cpumask_pr_args(mask)); mask 111 arch/powerpc/kernel/dma-iommu.c static bool dma_iommu_bypass_supported(struct device *dev, u64 mask) mask 117 arch/powerpc/kernel/dma-iommu.c phb->controller_ops.iommu_bypass_supported(pdev, mask); mask 121 arch/powerpc/kernel/dma-iommu.c int dma_iommu_dma_supported(struct device *dev, u64 mask) mask 125 arch/powerpc/kernel/dma-iommu.c if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) { mask 132 arch/powerpc/kernel/dma-iommu.c dev_err(dev, "Warning: IOMMU dma not supported: mask 0x%08llx, table unavailable\n", mask); mask 136 arch/powerpc/kernel/dma-iommu.c if (tbl->it_offset > (mask >> tbl->it_page_shift)) { mask 139 arch/powerpc/kernel/dma-iommu.c mask, tbl->it_offset << tbl->it_page_shift); mask 151 arch/powerpc/kernel/dma-iommu.c u64 mask; mask 163 arch/powerpc/kernel/dma-iommu.c mask = 1ULL < (fls_long(tbl->it_offset + tbl->it_size) - 1); mask 164 arch/powerpc/kernel/dma-iommu.c mask += mask - 1; mask 166 arch/powerpc/kernel/dma-iommu.c return mask; mask 1747 arch/powerpc/kernel/eeh.c unsigned long addr, unsigned long mask) mask 1765 arch/powerpc/kernel/eeh.c return eeh_ops->err_inject(pe, type, func, addr, mask); mask 167 arch/powerpc/kernel/iommu.c unsigned long mask, mask 223 arch/powerpc/kernel/iommu.c if (limit + tbl->it_offset > mask) { mask 224 arch/powerpc/kernel/iommu.c limit = mask - tbl->it_offset + 1; mask 229 arch/powerpc/kernel/iommu.c if ((start & mask) >= limit || pass > 0) { mask 235 arch/powerpc/kernel/iommu.c start &= mask; mask 296 arch/powerpc/kernel/iommu.c unsigned long mask, unsigned int align_order, mask 303 arch/powerpc/kernel/iommu.c entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order); mask 420 arch/powerpc/kernel/iommu.c unsigned long mask, enum dma_data_direction direction, mask 463 arch/powerpc/kernel/iommu.c mask >> tbl->it_page_shift, align); mask 796 arch/powerpc/kernel/iommu.c unsigned long mask, enum dma_data_direction direction, mask 817 arch/powerpc/kernel/iommu.c mask >> tbl->it_page_shift, align, mask 854 arch/powerpc/kernel/iommu.c unsigned long mask, gfp_t flag, int node) mask 890 arch/powerpc/kernel/iommu.c mask >> tbl->it_page_shift, io_order, 0); mask 989 arch/powerpc/kernel/iommu.c unsigned long mask = (1UL << page_shift) - 1; mask 991 arch/powerpc/kernel/iommu.c if (ioba & mask) mask 1007 arch/powerpc/kernel/iommu.c unsigned long mask = (1UL << page_shift) - 1; mask 1009 arch/powerpc/kernel/iommu.c if (gpa & mask) mask 232 arch/powerpc/kernel/irq.c notrace void arch_local_irq_restore(unsigned long mask) mask 238 arch/powerpc/kernel/irq.c irq_soft_mask_set(mask); mask 239 arch/powerpc/kernel/irq.c if (mask) mask 695 arch/powerpc/kernel/irq.c int irq_choose_cpu(const struct cpumask *mask) mask 699 arch/powerpc/kernel/irq.c if (cpumask_equal(mask, cpu_online_mask)) { mask 716 arch/powerpc/kernel/irq.c cpuid = cpumask_first_and(mask, cpu_online_mask); mask 724 arch/powerpc/kernel/irq.c int irq_choose_cpu(const struct cpumask *mask) mask 1451 arch/powerpc/kernel/pci-common.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 1459 arch/powerpc/kernel/pci-common.c return pci_enable_resources(dev, mask); mask 911 arch/powerpc/kernel/prom_init.c struct { u32 mask, val; } pvrs[12]; mask 937 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xfffe0000), /* POWER5/POWER5+ */ mask 941 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER6 */ mask 945 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER7 */ mask 949 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER8E */ mask 953 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER8NVL */ mask 957 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER8 */ mask 961 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffff0000), /* POWER9 */ mask 965 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */ mask 969 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffffffff), /* all 2.07-compliant */ mask 973 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffffffff), /* all 2.06-compliant */ mask 977 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xffffffff), /* all 2.05-compliant */ mask 981 arch/powerpc/kernel/prom_init.c .mask = cpu_to_be32(0xfffffffe), /* all 2.04-compliant and earlier */ mask 342 arch/powerpc/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 346 arch/powerpc/kernel/smp.c for_each_cpu(cpu, mask) mask 539 arch/powerpc/kernel/smp.c void tick_broadcast(const struct cpumask *mask) mask 543 arch/powerpc/kernel/smp.c for_each_cpu(cpu, mask) mask 1372 arch/powerpc/kernel/smp.c power9_topology[0].mask = smallcore_smt_mask; mask 1373 arch/powerpc/kernel/smp.c powerpc_topology[0].mask = smallcore_smt_mask; mask 231 arch/powerpc/kernel/stacktrace.c static void raise_backtrace_ipi(cpumask_t *mask) mask 235 arch/powerpc/kernel/stacktrace.c for_each_cpu(cpu, mask) { mask 242 arch/powerpc/kernel/stacktrace.c for_each_cpu(cpu, mask) { mask 245 arch/powerpc/kernel/stacktrace.c cpumask_clear_cpu(cpu, mask); mask 267 arch/powerpc/kernel/stacktrace.c void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) mask 269 arch/powerpc/kernel/stacktrace.c nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace_ipi); mask 83 arch/powerpc/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 92 arch/powerpc/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 223 arch/powerpc/kernel/vecemu.c int exp, mask; mask 235 arch/powerpc/kernel/vecemu.c mask = 0x7fffff >> exp; mask 238 arch/powerpc/kernel/vecemu.c return (x + mask) & ~mask; mask 547 arch/powerpc/kvm/book3s_64_mmu.c u64 mask = 0xFFFFFFFFFULL; mask 563 arch/powerpc/kvm/book3s_64_mmu.c mask = 0xFFFFFFFF0ULL; /* 64k page */ mask 565 arch/powerpc/kvm/book3s_64_mmu.c mask = 0xFFFFFF000ULL; /* 16M page */ mask 570 arch/powerpc/kvm/book3s_64_mmu.c mask = 0xFFFFFF000ULL; mask 574 arch/powerpc/kvm/book3s_64_mmu.c kvmppc_mmu_pte_vflush(v, va >> 12, mask); mask 214 arch/powerpc/kvm/book3s_64_mmu_host.c u64 mask = 0xfffffffffULL; mask 219 arch/powerpc/kvm/book3s_64_mmu_host.c mask = 0xffffffff0ULL; mask 220 arch/powerpc/kvm/book3s_64_mmu_host.c kvmppc_mmu_pte_vflush(vcpu, pte->vpage, mask); mask 313 arch/powerpc/kvm/book3s_64_mmu_hv.c u64 mask; mask 321 arch/powerpc/kvm/book3s_64_mmu_hv.c mask = ESID_MASK_1T; mask 323 arch/powerpc/kvm/book3s_64_mmu_hv.c mask = ESID_MASK; mask 325 arch/powerpc/kvm/book3s_64_mmu_hv.c if (((vcpu->arch.slb[i].orige ^ eaddr) & mask) == 0) mask 420 arch/powerpc/kvm/book3s_64_mmu_hv.c unsigned int mask; mask 422 arch/powerpc/kvm/book3s_64_mmu_hv.c mask = 0x10000000; mask 424 arch/powerpc/kvm/book3s_64_mmu_hv.c mask = 0x100; /* major opcode 31 */ mask 425 arch/powerpc/kvm/book3s_64_mmu_hv.c return (instr & mask) != 0; mask 1579 arch/powerpc/kvm/book3s_hv.c u64 mask; mask 1605 arch/powerpc/kvm/book3s_hv.c mask = LPCR_DPFD | LPCR_ILE | LPCR_TC; mask 1607 arch/powerpc/kvm/book3s_hv.c mask |= LPCR_AIL; mask 1613 arch/powerpc/kvm/book3s_hv.c mask |= LPCR_LD; mask 1617 arch/powerpc/kvm/book3s_hv.c mask &= 0xFFFFFFFF; mask 1618 arch/powerpc/kvm/book3s_hv.c vc->lpcr = (vc->lpcr & ~mask) | (new_lpcr & mask); mask 4524 arch/powerpc/kvm/book3s_hv.c void kvmppc_update_lpcr(struct kvm *kvm, unsigned long lpcr, unsigned long mask) mask 4529 arch/powerpc/kvm/book3s_hv.c if ((kvm->arch.lpcr & mask) == lpcr) mask 4532 arch/powerpc/kvm/book3s_hv.c kvm->arch.lpcr = (kvm->arch.lpcr & ~mask) | lpcr; mask 4539 arch/powerpc/kvm/book3s_hv.c vc->lpcr = (vc->lpcr & ~mask) | lpcr; mask 228 arch/powerpc/kvm/book3s_hv_nested.c u64 mask; mask 279 arch/powerpc/kvm/book3s_hv_nested.c mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD | mask 281 arch/powerpc/kvm/book3s_hv_nested.c lpcr = (vc->lpcr & ~mask) | (l2_hv.lpcr & mask); mask 793 arch/powerpc/kvm/book3s_hv_nested.c unsigned long hpa, unsigned long mask) mask 814 arch/powerpc/kvm/book3s_hv_nested.c if (ptep && pte_present(*ptep) && ((pte_val(*ptep) & mask) == hpa)) { mask 830 arch/powerpc/kvm/book3s_hv_nested.c unsigned long rmap, mask; mask 835 arch/powerpc/kvm/book3s_hv_nested.c mask = PTE_RPN_MASK & ~(nbytes - 1); mask 836 arch/powerpc/kvm/book3s_hv_nested.c hpa &= mask; mask 839 arch/powerpc/kvm/book3s_hv_nested.c kvmhv_update_nest_rmap_rc(kvm, rmap, clr, set, hpa, mask); mask 843 arch/powerpc/kvm/book3s_hv_nested.c unsigned long hpa, unsigned long mask) mask 859 arch/powerpc/kvm/book3s_hv_nested.c if (ptep && pte_present(*ptep) && ((pte_val(*ptep) & mask) == hpa)) mask 864 arch/powerpc/kvm/book3s_hv_nested.c unsigned long hpa, unsigned long mask) mask 871 arch/powerpc/kvm/book3s_hv_nested.c kvmhv_remove_nest_rmap(kvm, rmap, hpa, mask); mask 1398 arch/powerpc/kvm/book3s_hv_nested.c u64 mask; mask 1402 arch/powerpc/kvm/book3s_hv_nested.c mask = (1UL << shift) - (1UL << actual_shift); mask 1403 arch/powerpc/kvm/book3s_hv_nested.c pte = __pte(pte_val(pte) | (gpa & mask)); mask 692 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long v, r, rb, mask, bits; mask 718 arch/powerpc/kvm/book3s_hv_rm_mmu.c mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | mask 722 arch/powerpc/kvm/book3s_hv_rm_mmu.c r = (rev->guest_rpte & ~mask) | bits; mask 734 arch/powerpc/kvm/book3s_hv_rm_mmu.c r = (pte_r & ~mask) | bits; mask 1124 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long mask, val; mask 1128 arch/powerpc/kvm/book3s_hv_rm_mmu.c mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY; mask 1132 arch/powerpc/kvm/book3s_hv_rm_mmu.c mask |= HPTE_V_LARGE; mask 1164 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (!(v & valid) || (v & mask) != val) mask 1180 arch/powerpc/kvm/book3s_hv_rm_mmu.c if ((v & valid) && (v & mask) == val && mask 586 arch/powerpc/kvm/mpic.c uint32_t mask = normal_mask; mask 591 arch/powerpc/kvm/mpic.c crit_mask = mask << crit_shift; mask 592 arch/powerpc/kvm/mpic.c mask |= crit_mask | IDR_EP; mask 595 arch/powerpc/kvm/mpic.c src->idr = val & mask; mask 642 arch/powerpc/kvm/mpic.c uint32_t mask; mask 647 arch/powerpc/kvm/mpic.c mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | mask 652 arch/powerpc/kvm/mpic.c (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); mask 10 arch/powerpc/lib/alloc.c void * __ref zalloc_maybe_bootmem(size_t size, gfp_t mask) mask 15 arch/powerpc/lib/alloc.c p = kzalloc(size, mask); mask 26 arch/powerpc/lib/feature-fixups.c unsigned long mask; mask 79 arch/powerpc/lib/feature-fixups.c if ((value & fcur->mask) == fcur->value) mask 494 arch/powerpc/lib/feature-fixups.c fixup.value = fixup.mask = 8; mask 526 arch/powerpc/lib/feature-fixups.c fixup.value = fixup.mask = 0xF; mask 558 arch/powerpc/lib/feature-fixups.c fixup.value = fixup.mask = 0xC; mask 588 arch/powerpc/lib/feature-fixups.c fixup.value = fixup.mask = flag; mask 1042 arch/powerpc/lib/sstep.c unsigned long long out_val, mask; mask 1047 arch/powerpc/lib/sstep.c mask = 0xffUL << (i * 8); mask 1048 arch/powerpc/lib/sstep.c if ((v1 & mask) == (v2 & mask)) mask 1049 arch/powerpc/lib/sstep.c out_val |= mask; mask 12 arch/powerpc/math-emu/mtfsf.c u32 mask; mask 16 arch/powerpc/math-emu/mtfsf.c mask = 0x0f; mask 18 arch/powerpc/math-emu/mtfsf.c mask = ~0; mask 20 arch/powerpc/math-emu/mtfsf.c mask = ((FM & 1) | mask 30 arch/powerpc/math-emu/mtfsf.c fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) & mask 12 arch/powerpc/math-emu/mtfsfi.c u32 mask = 0xf; mask 15 arch/powerpc/math-emu/mtfsfi.c mask = 9; mask 17 arch/powerpc/math-emu/mtfsfi.c __FPU_FPSCR &= ~(mask << ((7 - crfD) << 2)); mask 750 arch/powerpc/mm/book3s64/radix_pgtable.c unsigned long mask = ~(size - 1); mask 751 arch/powerpc/mm/book3s64/radix_pgtable.c unsigned long aligned_start = addr & mask; mask 503 arch/powerpc/mm/hugetlbpage.c unsigned long mask; mask 517 arch/powerpc/mm/hugetlbpage.c mask = (1UL << shift) - 1; mask 519 arch/powerpc/mm/hugetlbpage.c page += ((address & mask) >> PAGE_SHIFT); mask 14 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_SH, mask 19 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_RO | _PAGE_NA, mask 23 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_RO | _PAGE_NA, mask 27 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_RO | _PAGE_NA, mask 31 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_EXEC, mask 36 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_PRESENT, mask 41 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_GUARDED, mask 46 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_DIRTY, mask 51 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_ACCESSED, mask 56 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_NO_CACHE, mask 61 arch/powerpc/mm/ptdump/8xx.c .mask = _PAGE_SPECIAL, mask 14 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_PRIVILEGED, mask 19 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_READ, mask 24 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_WRITE, mask 29 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_EXEC, mask 34 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_PTE, mask 39 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_PRESENT, mask 44 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_PRESENT | _PAGE_INVALID, mask 49 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_HASHPTE, mask 54 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_DIRTY, mask 59 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_ACCESSED, mask 64 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_NON_IDEMPOTENT, mask 69 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_TOLERANT, mask 74 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_BUSY, mask 79 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_COMBO, mask 83 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_4K_PFN, mask 88 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_F_GIX, mask 94 arch/powerpc/mm/ptdump/book3s64.c .mask = H_PAGE_F_SECOND, mask 99 arch/powerpc/mm/ptdump/book3s64.c .mask = _PAGE_SPECIAL, mask 54 arch/powerpc/mm/ptdump/hashpagetable.c u64 mask; mask 64 arch/powerpc/mm/ptdump/hashpagetable.c .mask = SLB_VSID_B, mask 69 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_V_SECONDARY, mask 74 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_V_VALID, mask 79 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_V_BOLTED, mask 88 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_PP0 | HPTE_R_PP, mask 92 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_PP0 | HPTE_R_PP, mask 96 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_PP0 | HPTE_R_PP, mask 100 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_PP0 | HPTE_R_PP, mask 104 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_PP0 | HPTE_R_PP, mask 108 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_KEY_HI | HPTE_R_KEY_LO, mask 114 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_R, mask 119 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_C, mask 124 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_N, mask 128 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_WIMG, mask 132 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_WIMG, mask 136 arch/powerpc/mm/ptdump/hashpagetable.c .mask = HPTE_R_WIMG, mask 165 arch/powerpc/mm/ptdump/hashpagetable.c if (flag->mask == 0) mask 174 arch/powerpc/mm/ptdump/hashpagetable.c if ((pte & flag->mask) == flag->val) mask 281 arch/powerpc/mm/ptdump/hashpagetable.c unsigned long arpn, mask, lp; mask 302 arch/powerpc/mm/ptdump/hashpagetable.c mask = (0x1 << (shift)) - 1; mask 303 arch/powerpc/mm/ptdump/hashpagetable.c if ((lp & mask) == penc) { mask 305 arch/powerpc/mm/ptdump/hashpagetable.c *lp_bits = lp & mask; mask 124 arch/powerpc/mm/ptdump/ptdump.c if (flag->mask == 0) mask 133 arch/powerpc/mm/ptdump/ptdump.c if ((pte & flag->mask) == flag->val) mask 140 arch/powerpc/mm/ptdump/ptdump.c st->current_flags &= ~flag->mask; mask 194 arch/powerpc/mm/ptdump/ptdump.c u64 flag = val & pg_level[level].mask; mask 391 arch/powerpc/mm/ptdump/ptdump.c pg_level[i].mask |= pg_level[i].flag[j].mask; mask 5 arch/powerpc/mm/ptdump/ptdump.h u64 mask; mask 16 arch/powerpc/mm/ptdump/ptdump.h u64 mask; mask 14 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_USER, mask 19 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_RW, mask 24 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_EXEC, mask 29 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_PRESENT, mask 34 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_GUARDED, mask 39 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_DIRTY, mask 44 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_ACCESSED, mask 49 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_WRITETHRU, mask 54 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_NO_CACHE, mask 59 arch/powerpc/mm/ptdump/shared.c .mask = _PAGE_SPECIAL, mask 34 arch/powerpc/mm/slice.c static void slice_print_mask(const char *label, const struct slice_mask *mask) mask 39 arch/powerpc/mm/slice.c (int)SLICE_NUM_LOW, &mask->low_slices); mask 41 arch/powerpc/mm/slice.c (int)SLICE_NUM_HIGH, mask->high_slices); mask 48 arch/powerpc/mm/slice.c static void slice_print_mask(const char *label, const struct slice_mask *mask) {} mask 188 arch/powerpc/mm/slice.c const struct slice_mask *mask, int psize) mask 198 arch/powerpc/mm/slice.c slice_print_mask(" mask", mask); mask 209 arch/powerpc/mm/slice.c if (!(mask->low_slices & (1u << i))) mask 228 arch/powerpc/mm/slice.c if (!test_bit(i, mask->high_slices)) mask 385 arch/powerpc/mm/slice.c const struct slice_mask *mask, int psize, mask 389 arch/powerpc/mm/slice.c return slice_find_area_topdown(mm, len, mask, psize, high_limit); mask 391 arch/powerpc/mm/slice.c return slice_find_area_bottomup(mm, len, mask, psize, high_limit); mask 684 arch/powerpc/mm/slice.c struct slice_mask *mask; mask 709 arch/powerpc/mm/slice.c mask = slice_mask_for_size(&mm->context, psize); mask 710 arch/powerpc/mm/slice.c mask->low_slices = ~0UL; mask 712 arch/powerpc/mm/slice.c bitmap_fill(mask->high_slices, SLICE_NUM_HIGH); mask 732 arch/powerpc/mm/slice.c struct slice_mask mask; mask 736 arch/powerpc/mm/slice.c slice_range_to_mask(start, len, &mask); mask 737 arch/powerpc/mm/slice.c slice_convert(mm, &mask, psize); mask 870 arch/powerpc/perf/core-book3s.c unsigned long mask, value, nv; mask 894 arch/powerpc/perf/core-book3s.c value = mask = 0; mask 899 arch/powerpc/perf/core-book3s.c if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) mask 907 arch/powerpc/perf/core-book3s.c mask |= cpuhw->amasks[i][0]; mask 910 arch/powerpc/perf/core-book3s.c if ((value & mask & grp_mask) != (mask & grp_val)) mask 932 arch/powerpc/perf/core-book3s.c value = mask = nv = 0; mask 937 arch/powerpc/perf/core-book3s.c mask = smasks[i]; mask 947 arch/powerpc/perf/core-book3s.c if ((((nv + tadd) ^ value) & mask) == 0 && mask 969 arch/powerpc/perf/core-book3s.c smasks[i] = mask; mask 971 arch/powerpc/perf/core-book3s.c mask |= cpuhw->amasks[i][j]; mask 245 arch/powerpc/perf/isa207-common.c unsigned long mask, value; mask 247 arch/powerpc/perf/isa207-common.c mask = value = 0; mask 270 arch/powerpc/perf/isa207-common.c mask |= CNST_PMC_MASK(pmc); mask 281 arch/powerpc/perf/isa207-common.c mask |= CNST_NC_MASK; mask 287 arch/powerpc/perf/isa207-common.c mask |= CNST_CACHE_GROUP_MASK; mask 290 arch/powerpc/perf/isa207-common.c mask |= CNST_CACHE_PMC4_MASK; mask 307 arch/powerpc/perf/isa207-common.c mask |= CNST_L1_QUAL_MASK; mask 312 arch/powerpc/perf/isa207-common.c mask |= CNST_SAMPLE_MASK; mask 318 arch/powerpc/perf/isa207-common.c mask |= CNST_THRESH_MASK; mask 327 arch/powerpc/perf/isa207-common.c mask |= CNST_FAB_MATCH_MASK; mask 333 arch/powerpc/perf/isa207-common.c mask |= CNST_THRESH_MASK; mask 347 arch/powerpc/perf/isa207-common.c mask |= CNST_IFM_MASK; mask 356 arch/powerpc/perf/isa207-common.c mask |= CNST_EBB_VAL(ebb); mask 359 arch/powerpc/perf/isa207-common.c *maskp = mask; mask 154 arch/powerpc/perf/mpc7450-pmu.c u32 mask, value; mask 162 arch/powerpc/perf/mpc7450-pmu.c mask = pmcbits[pmc - 1][0]; mask 165 arch/powerpc/perf/mpc7450-pmu.c mask = classbits[class][0]; mask 172 arch/powerpc/perf/mpc7450-pmu.c mask |= 0x3f << 24; mask 175 arch/powerpc/perf/mpc7450-pmu.c mask |= 0x40000000; mask 181 arch/powerpc/perf/mpc7450-pmu.c *maskp = mask; mask 91 arch/powerpc/perf/perf_regs.c int perf_reg_validate(u64 mask) mask 93 arch/powerpc/perf/perf_regs.c if (!mask || mask & REG_RESERVED) mask 137 arch/powerpc/perf/power5+-pmu.c unsigned long mask = 0, value = 0; mask 144 arch/powerpc/perf/power5+-pmu.c mask |= 2 << sh; mask 155 arch/powerpc/perf/power5+-pmu.c mask |= unit_cons[unit][0]; mask 169 arch/powerpc/perf/power5+-pmu.c mask |= (unsigned long)fmask << sh; mask 174 arch/powerpc/perf/power5+-pmu.c mask |= 0xfUL << (24 - 4 * byte); mask 179 arch/powerpc/perf/power5+-pmu.c mask |= 0x8000000000000ul; mask 182 arch/powerpc/perf/power5+-pmu.c *maskp = mask; mask 405 arch/powerpc/perf/power5+-pmu.c u32 mask; mask 439 arch/powerpc/perf/power5+-pmu.c mask = 0x5dff00; mask 443 arch/powerpc/perf/power5+-pmu.c mask = 0x5f11c000; mask 447 arch/powerpc/perf/power5+-pmu.c return (mask >> (byte * 8 + bit)) & 1; mask 141 arch/powerpc/perf/power5-pmu.c unsigned long mask = 0, value = 0; mask 149 arch/powerpc/perf/power5-pmu.c mask |= 2 << sh; mask 162 arch/powerpc/perf/power5-pmu.c mask |= unit_cons[unit][0]; mask 176 arch/powerpc/perf/power5-pmu.c mask |= (unsigned long)fmask << sh; mask 187 arch/powerpc/perf/power5-pmu.c mask |= 0xfUL << (24 - 4 * byte); mask 192 arch/powerpc/perf/power5-pmu.c mask |= 0x200000000ul; mask 196 arch/powerpc/perf/power5-pmu.c mask |= 0x40000000ul; mask 201 arch/powerpc/perf/power5-pmu.c mask |= 0x8000000000000ul; mask 204 arch/powerpc/perf/power5-pmu.c *maskp = mask; mask 341 arch/powerpc/perf/power5-pmu.c u32 mask; mask 370 arch/powerpc/perf/power5-pmu.c mask = 0x5dff00; mask 374 arch/powerpc/perf/power5-pmu.c mask = 0x5f00c0aa; mask 378 arch/powerpc/perf/power5-pmu.c return (mask >> (byte * 8 + bit)) & 1; mask 139 arch/powerpc/perf/power6-pmu.c u32 mask; mask 166 arch/powerpc/perf/power6-pmu.c mask = marked_bus_events[unit]; mask 167 arch/powerpc/perf/power6-pmu.c return (mask >> (byte * 8 + bit)) & 1; mask 270 arch/powerpc/perf/power6-pmu.c unsigned long mask = 0, value = 0; mask 277 arch/powerpc/perf/power6-pmu.c mask |= 2 << sh; mask 283 arch/powerpc/perf/power6-pmu.c mask |= PM_UNIT_MSKS << sh; mask 287 arch/powerpc/perf/power6-pmu.c mask |= (unsigned long)PM_SUBUNIT_MSK << 32; mask 292 arch/powerpc/perf/power6-pmu.c mask |= 0x8000; /* add field for count of PMC1-4 uses */ mask 295 arch/powerpc/perf/power6-pmu.c *maskp = mask; mask 85 arch/powerpc/perf/power7-pmu.c unsigned long mask = 0, value = 0; mask 92 arch/powerpc/perf/power7-pmu.c mask |= 2 << sh; mask 99 arch/powerpc/perf/power7-pmu.c mask |= 0x8000; mask 107 arch/powerpc/perf/power7-pmu.c mask |= 0x7 << 16; mask 111 arch/powerpc/perf/power7-pmu.c *maskp = mask; mask 146 arch/powerpc/perf/ppc970-pmu.c unsigned int mask; mask 164 arch/powerpc/perf/ppc970-pmu.c mask = 0; mask 167 arch/powerpc/perf/ppc970-pmu.c mask = 0x4c; /* byte 0 bits 2,3,6 */ mask 171 arch/powerpc/perf/ppc970-pmu.c mask = 0x085dff00; mask 174 arch/powerpc/perf/ppc970-pmu.c mask = 0x50 << 24; /* byte 3 bits 4,6 */ mask 177 arch/powerpc/perf/ppc970-pmu.c return (mask >> (byte * 8 + bit)) & 1; mask 194 arch/powerpc/perf/ppc970-pmu.c unsigned long mask = 0, value = 0; mask 202 arch/powerpc/perf/ppc970-pmu.c mask |= 2 << sh; mask 210 arch/powerpc/perf/ppc970-pmu.c mask |= unit_cons[unit][0]; mask 220 arch/powerpc/perf/ppc970-pmu.c mask |= 0xfULL << (28 - 4 * byte); mask 225 arch/powerpc/perf/ppc970-pmu.c mask |= 0x8000000000ull; mask 229 arch/powerpc/perf/ppc970-pmu.c mask |= 0x800000000ull; mask 234 arch/powerpc/perf/ppc970-pmu.c mask |= 3ull << 48; mask 237 arch/powerpc/perf/ppc970-pmu.c *maskp = mask; mask 58 arch/powerpc/platforms/4xx/cpm.c static unsigned int cpm_set(unsigned int cpm_reg, unsigned int mask) mask 70 arch/powerpc/platforms/4xx/cpm.c dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask); mask 92 arch/powerpc/platforms/4xx/cpm.c static void cpm_idle_sleep(unsigned int mask) mask 97 arch/powerpc/platforms/4xx/cpm.c er_save = cpm_set(CPM_ER, mask); mask 200 arch/powerpc/platforms/4xx/cpm.c static void cpm_suspend_standby(unsigned int mask) mask 209 arch/powerpc/platforms/4xx/cpm.c cpm_idle_sleep(mask); mask 666 arch/powerpc/platforms/4xx/pci.c unsigned int mask, mask 674 arch/powerpc/platforms/4xx/pci.c if ((val & mask) == value) { mask 1375 arch/powerpc/platforms/4xx/pci.c u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT); mask 1390 arch/powerpc/platforms/4xx/pci.c if ((val & mask) == mask) mask 124 arch/powerpc/platforms/4xx/uic.c u32 tr, pr, mask; mask 147 arch/powerpc/platforms/4xx/uic.c mask = ~(1 << (31 - src)); mask 152 arch/powerpc/platforms/4xx/uic.c tr = (tr & mask) | (trigger << (31-src)); mask 153 arch/powerpc/platforms/4xx/uic.c pr = (pr & mask) | (polarity << (31-src)); mask 157 arch/powerpc/platforms/4xx/uic.c mtdcr(uic->dcrbase + UIC_SR, ~mask); mask 90 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c u8 mask = in_8(maskp); mask 93 arch/powerpc/platforms/512x/mpc5121_ads_cpld.c status |= (ignore | mask); mask 179 arch/powerpc/platforms/52xx/mpc52xx_common.c u32 mask; mask 187 arch/powerpc/platforms/52xx/mpc52xx_common.c case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break; mask 188 arch/powerpc/platforms/52xx/mpc52xx_common.c case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break; mask 189 arch/powerpc/platforms/52xx/mpc52xx_common.c case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break; mask 190 arch/powerpc/platforms/52xx/mpc52xx_common.c case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break; mask 199 arch/powerpc/platforms/52xx/mpc52xx_common.c out_be32(&mpc52xx_cdm->clk_enables, val | mask); mask 168 arch/powerpc/platforms/52xx/mpc52xx_pci.c u32 value, mask; mask 210 arch/powerpc/platforms/52xx/mpc52xx_pci.c mask = (0xffffffff >> (32 - (len << 3))); mask 211 arch/powerpc/platforms/52xx/mpc52xx_pci.c mask <<= offset; mask 213 arch/powerpc/platforms/52xx/mpc52xx_pci.c value &= ~mask; mask 214 arch/powerpc/platforms/52xx/mpc52xx_pci.c val = value | ((val << offset) & mask); mask 32 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c u32 mask; mask 47 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c setbits32(&priv->regs->mask, 1 << irq); mask 63 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c clrbits32(&priv->regs->mask, 1 << irq); mask 81 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c u32 stat, mask, pend; mask 86 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c mask = in_be32(&priv->regs->mask); mask 88 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c pend = stat & ~mask; mask 152 arch/powerpc/platforms/82xx/pq2ads-pci-pic.c out_be32(&priv->regs->mask, ~0); mask 153 arch/powerpc/platforms/83xx/misc.c u32 mask = 1 << (31 - IPIC_MCP_WDT); mask 155 arch/powerpc/platforms/83xx/misc.c if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask)) mask 157 arch/powerpc/platforms/83xx/misc.c ipic_clear_mcp_status(mask); mask 48 arch/powerpc/platforms/83xx/suspend.c u32 mask; mask 205 arch/powerpc/platforms/83xx/suspend.c out_be32(&pmc_regs->mask, PMCER_ALL); mask 217 arch/powerpc/platforms/83xx/suspend.c out_be32(&pmc_regs->mask, PMCER_PMCI); mask 221 arch/powerpc/platforms/83xx/suspend.c out_be32(&pmc_regs->mask, PMCER_PMCI); mask 293 arch/powerpc/platforms/83xx/suspend.c out_be32(&pmc_regs->mask, PMCER_PMCI); mask 55 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c uint32_t mask; mask 57 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1; mask 59 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c setbits32(&guts->devdisr, mask); mask 61 arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c clrbits32(&guts->devdisr, mask); mask 110 arch/powerpc/platforms/85xx/socrates_fpga_pic.c uint32_t mask; mask 114 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask 116 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask |= (1 << (hwirq + 16)); mask 117 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); mask 126 arch/powerpc/platforms/85xx/socrates_fpga_pic.c u32 mask; mask 130 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask 132 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask &= ~(1 << hwirq); mask 133 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); mask 142 arch/powerpc/platforms/85xx/socrates_fpga_pic.c u32 mask; mask 146 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask 148 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask &= ~(1 << hwirq); mask 149 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask |= (1 << (hwirq + 16)); mask 150 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); mask 159 arch/powerpc/platforms/85xx/socrates_fpga_pic.c u32 mask; mask 163 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask 165 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask |= (1 << hwirq); mask 166 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); mask 175 arch/powerpc/platforms/85xx/socrates_fpga_pic.c u32 mask; mask 179 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) mask 181 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask |= (1 << (hwirq + 16)); mask 182 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); mask 192 arch/powerpc/platforms/85xx/socrates_fpga_pic.c u32 mask; mask 208 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask = socrates_fpga_pic_read(FPGA_PIC_IRQCFG); mask 210 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask |= (1 << hwirq); mask 212 arch/powerpc/platforms/85xx/socrates_fpga_pic.c mask &= ~(1 << hwirq); mask 213 arch/powerpc/platforms/85xx/socrates_fpga_pic.c socrates_fpga_pic_write(FPGA_PIC_IRQCFG, mask); mask 402 arch/powerpc/platforms/8xx/cpm1.c u32 mask = 7; mask 509 arch/powerpc/platforms/8xx/cpm1.c mask <<= shift; mask 514 arch/powerpc/platforms/8xx/cpm1.c mask |= mask << 3; mask 517 arch/powerpc/platforms/8xx/cpm1.c mask <<= 3; mask 521 arch/powerpc/platforms/8xx/cpm1.c out_be32(reg, (in_be32(reg) & ~mask) | bits); mask 639 arch/powerpc/platforms/8xx/cpm1.c u16 mask; mask 647 arch/powerpc/platforms/8xx/cpm1.c if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { mask 651 arch/powerpc/platforms/8xx/cpm1.c if (mask & (1 << (15 - i))) mask 14 arch/powerpc/platforms/8xx/pic.h static inline uint mk_int_int_mask(uint mask) mask 16 arch/powerpc/platforms/8xx/pic.h return (1 << (7 - (mask/2))); mask 854 arch/powerpc/platforms/cell/iommu.c static bool cell_pci_iommu_bypass_supported(struct pci_dev *pdev, u64 mask) mask 856 arch/powerpc/platforms/cell/iommu.c return mask == DMA_BIT_MASK(64) && mask 343 arch/powerpc/platforms/cell/pmu.c void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask) mask 349 arch/powerpc/platforms/cell/pmu.c if (mask) mask 350 arch/powerpc/platforms/cell/pmu.c cbe_write_pm(cpu, pm_status, mask); mask 283 arch/powerpc/platforms/cell/spu_base.c unsigned long stat, mask; mask 288 arch/powerpc/platforms/cell/spu_base.c mask = spu_int_mask_get(spu, 0); mask 289 arch/powerpc/platforms/cell/spu_base.c stat = spu_int_stat_get(spu, 0) & mask; mask 307 arch/powerpc/platforms/cell/spu_base.c unsigned long stat, mask, dar, dsisr; mask 313 arch/powerpc/platforms/cell/spu_base.c mask = spu_int_mask_get(spu, 1); mask 314 arch/powerpc/platforms/cell/spu_base.c stat = spu_int_stat_get(spu, 1) & mask; mask 321 arch/powerpc/platforms/cell/spu_base.c pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat, mask 349 arch/powerpc/platforms/cell/spu_base.c unsigned long mask; mask 356 arch/powerpc/platforms/cell/spu_base.c mask = spu_int_mask_get(spu, 2); mask 358 arch/powerpc/platforms/cell/spu_base.c stat &= mask; mask 366 arch/powerpc/platforms/cell/spu_base.c pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); mask 27 arch/powerpc/platforms/cell/spu_priv1_mmio.c static void int_mask_and(struct spu *spu, int class, u64 mask) mask 32 arch/powerpc/platforms/cell/spu_priv1_mmio.c out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); mask 35 arch/powerpc/platforms/cell/spu_priv1_mmio.c static void int_mask_or(struct spu *spu, int class, u64 mask) mask 40 arch/powerpc/platforms/cell/spu_priv1_mmio.c out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); mask 43 arch/powerpc/platforms/cell/spu_priv1_mmio.c static void int_mask_set(struct spu *spu, int class, u64 mask) mask 45 arch/powerpc/platforms/cell/spu_priv1_mmio.c out_be64(&spu->priv1->int_mask_RW[class], mask); mask 317 arch/powerpc/platforms/cell/spufs/backing_ops.c static int spu_backing_set_mfc_query(struct spu_context * ctx, u32 mask, mask 329 arch/powerpc/platforms/cell/spufs/backing_ops.c prob->dma_querymask_RW = mask; mask 336 arch/powerpc/platforms/cell/spufs/backing_ops.c ctx->csa.prob.dma_tagstatus_R &= mask; mask 758 arch/powerpc/platforms/cell/spufs/file.c __poll_t mask; mask 767 arch/powerpc/platforms/cell/spufs/file.c mask = ctx->ops->mbox_stat_poll(ctx, EPOLLIN | EPOLLRDNORM); mask 770 arch/powerpc/platforms/cell/spufs/file.c return mask; mask 894 arch/powerpc/platforms/cell/spufs/file.c __poll_t mask; mask 903 arch/powerpc/platforms/cell/spufs/file.c mask = ctx->ops->mbox_stat_poll(ctx, EPOLLOUT | EPOLLWRNORM); mask 906 arch/powerpc/platforms/cell/spufs/file.c return mask; mask 1687 arch/powerpc/platforms/cell/spufs/file.c __poll_t mask; mask 1701 arch/powerpc/platforms/cell/spufs/file.c mask = 0; mask 1703 arch/powerpc/platforms/cell/spufs/file.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1705 arch/powerpc/platforms/cell/spufs/file.c mask |= EPOLLIN | EPOLLRDNORM; mask 1710 arch/powerpc/platforms/cell/spufs/file.c return mask; mask 2451 arch/powerpc/platforms/cell/spufs/file.c __poll_t mask = 0; mask 2461 arch/powerpc/platforms/cell/spufs/file.c mask |= EPOLLIN; mask 2465 arch/powerpc/platforms/cell/spufs/file.c return mask; mask 247 arch/powerpc/platforms/cell/spufs/hw_ops.c static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode) mask 257 arch/powerpc/platforms/cell/spufs/hw_ops.c out_be32(&prob->dma_querymask_RW, mask); mask 158 arch/powerpc/platforms/cell/spufs/sched.c const struct cpumask *mask = cpumask_of_node(node); mask 160 arch/powerpc/platforms/cell/spufs/sched.c if (cpumask_intersects(mask, &ctx->cpus_allowed)) mask 196 arch/powerpc/platforms/cell/spufs/spufs.h int (*set_mfc_query)(struct spu_context * ctx, u32 mask, u32 mode); mask 250 arch/powerpc/platforms/cell/spufs/switch.c const u64 mask = MFC_CNTL_DECREMENTER_RUNNING | mask 259 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW &= ~mask; mask 260 arch/powerpc/platforms/cell/spufs/switch.c csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask; mask 899 arch/powerpc/platforms/cell/spufs/switch.c u32 mask = MFC_TAGID_TO_TAGMASK(0); mask 911 arch/powerpc/platforms/cell/spufs/switch.c POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask); mask 1205 arch/powerpc/platforms/cell/spufs/switch.c u32 mask; mask 1217 arch/powerpc/platforms/cell/spufs/switch.c mask = SPU_STATUS_INVALID_INSTR | mask 1221 arch/powerpc/platforms/cell/spufs/switch.c if (!(csa->prob.spu_status_R & mask)) { mask 1324 arch/powerpc/platforms/cell/spufs/switch.c u32 mask; mask 1330 arch/powerpc/platforms/cell/spufs/switch.c mask = SPU_STATUS_INVALID_INSTR | mask 1333 arch/powerpc/platforms/cell/spufs/switch.c if (csa->prob.spu_status_R & mask) { mask 1344 arch/powerpc/platforms/cell/spufs/switch.c u32 mask; mask 1352 arch/powerpc/platforms/cell/spufs/switch.c mask = SPU_STATUS_INVALID_INSTR | mask 1356 arch/powerpc/platforms/cell/spufs/switch.c if (!(csa->prob.spu_status_R & mask)) { mask 49 arch/powerpc/platforms/embedded6xx/flipper-pic.c u32 mask = 1 << irq; mask 51 arch/powerpc/platforms/embedded6xx/flipper-pic.c clrbits32(io_base + FLIPPER_IMR, mask); mask 53 arch/powerpc/platforms/embedded6xx/flipper-pic.c out_be32(io_base + FLIPPER_ICR, mask); mask 46 arch/powerpc/platforms/embedded6xx/hlwd-pic.c u32 mask = 1 << irq; mask 48 arch/powerpc/platforms/embedded6xx/hlwd-pic.c clrbits32(io_base + HW_BROADWAY_IMR, mask); mask 49 arch/powerpc/platforms/embedded6xx/hlwd-pic.c out_be32(io_base + HW_BROADWAY_ICR, mask); mask 137 arch/powerpc/platforms/powermac/feature.c int reg, u32 mask, int value) mask 147 arch/powerpc/platforms/powermac/feature.c MACIO_BIS(reg, mask); mask 149 arch/powerpc/platforms/powermac/feature.c MACIO_BIC(reg, mask); mask 1297 arch/powerpc/platforms/powermac/low_i2c.c u32 len, const u8 *mask, const u8 *val) mask 1303 arch/powerpc/platforms/powermac/low_i2c.c inst->scratch[i] = (inst->buffer[i] & mask[i]) | val[i]; mask 1306 arch/powerpc/platforms/powermac/low_i2c.c inst->scratch[i] = (inst->buffer[i] & ~mask[i]) mask 1307 arch/powerpc/platforms/powermac/low_i2c.c | (val[i] & mask[i]); mask 44 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask) mask 57 arch/powerpc/platforms/powermac/pfunc_base.c tmp = (tmp & ~mask) | (value & mask); mask 66 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_gpio_read(PMF_STD_ARGS, u8 mask, int rshift, u8 xor) mask 76 arch/powerpc/platforms/powermac/pfunc_base.c *args->u[0].p = ((value & mask) >> rshift) ^ xor; mask 144 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) mask 150 arch/powerpc/platforms/powermac/pfunc_base.c MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask)); mask 167 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask) mask 173 arch/powerpc/platforms/powermac/pfunc_base.c MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask)); mask 190 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask, mask 199 arch/powerpc/platforms/powermac/pfunc_base.c *args->u[0].p = ((MACIO_IN32(offset) & mask) >> shift) ^ xor; mask 203 arch/powerpc/platforms/powermac/pfunc_base.c static int macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask, mask 212 arch/powerpc/platforms/powermac/pfunc_base.c *((u8 *)(args->u[0].p)) = ((MACIO_IN8(offset) & mask) >> shift) ^ xor; mask 217 arch/powerpc/platforms/powermac/pfunc_base.c u32 mask) mask 230 arch/powerpc/platforms/powermac/pfunc_base.c tmp = (tmp & ~mask) | (val & mask); mask 237 arch/powerpc/platforms/powermac/pfunc_base.c u32 mask) mask 250 arch/powerpc/platforms/powermac/pfunc_base.c tmp = (tmp & ~mask) | (val & mask); mask 278 arch/powerpc/platforms/powermac/pfunc_base.c static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) mask 286 arch/powerpc/platforms/powermac/pfunc_base.c UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask)); mask 140 arch/powerpc/platforms/powermac/pfunc_core.c u8 mask = (u8)pmf_next32(cmd); mask 142 arch/powerpc/platforms/powermac/pfunc_core.c LOG_PARSE("pmf: write_gpio(value: %02x, mask: %02x)\n", value, mask); mask 144 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_gpio, cmd, h, value, mask); mask 149 arch/powerpc/platforms/powermac/pfunc_core.c u8 mask = (u8)pmf_next32(cmd); mask 154 arch/powerpc/platforms/powermac/pfunc_core.c mask, rshift, xor); mask 156 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(read_gpio, cmd, h, mask, rshift, xor); mask 163 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 166 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 168 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg32, cmd, h, offset, value, mask); mask 185 arch/powerpc/platforms/powermac/pfunc_core.c u16 mask = (u16)pmf_next32(cmd); mask 188 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 190 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg16, cmd, h, offset, value, mask); mask 207 arch/powerpc/platforms/powermac/pfunc_core.c u8 mask = (u16)pmf_next32(cmd); mask 210 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 212 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg8, cmd, h, offset, value, mask); mask 237 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 240 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 242 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(wait_reg32, cmd, h, offset, value, mask); mask 249 arch/powerpc/platforms/powermac/pfunc_core.c u16 mask = (u16)pmf_next32(cmd); mask 252 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 254 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(wait_reg16, cmd, h, offset, value, mask); mask 261 arch/powerpc/platforms/powermac/pfunc_core.c u8 mask = (u8)pmf_next32(cmd); mask 264 arch/powerpc/platforms/powermac/pfunc_core.c offset, value, mask); mask 266 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(wait_reg8, cmd, h, offset, value, mask); mask 408 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 413 arch/powerpc/platforms/powermac/pfunc_core.c " xor: %x\n", offset, mask, shift, xor); mask 415 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(read_reg32_msrx, cmd, h, offset, mask, shift, xor); mask 422 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 427 arch/powerpc/platforms/powermac/pfunc_core.c " xor: %x\n", offset, mask, shift, xor); mask 429 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(read_reg16_msrx, cmd, h, offset, mask, shift, xor); mask 435 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 440 arch/powerpc/platforms/powermac/pfunc_core.c " xor: %x\n", offset, mask, shift, xor); mask 442 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(read_reg8_msrx, cmd, h, offset, mask, shift, xor); mask 450 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 453 arch/powerpc/platforms/powermac/pfunc_core.c offset, shift, mask); mask 455 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg32_slm, cmd, h, offset, shift, mask); mask 463 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 466 arch/powerpc/platforms/powermac/pfunc_core.c offset, shift, mask); mask 468 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg16_slm, cmd, h, offset, shift, mask); mask 476 arch/powerpc/platforms/powermac/pfunc_core.c u32 mask = pmf_next32(cmd); mask 479 arch/powerpc/platforms/powermac/pfunc_core.c offset, shift, mask); mask 481 arch/powerpc/platforms/powermac/pfunc_core.c PMF_PARSE_CALL(write_reg8_slm, cmd, h, offset, shift, mask); mask 126 arch/powerpc/platforms/powernv/eeh-powernv.c unsigned long addr, mask; mask 140 arch/powerpc/platforms/powernv/eeh-powernv.c &pe_no, &type, &func, &addr, &mask); mask 150 arch/powerpc/platforms/powernv/eeh-powernv.c ret = eeh_ops->err_inject(pe, type, func, addr, mask); mask 954 arch/powerpc/platforms/powernv/eeh-powernv.c int pos, u16 mask) mask 961 arch/powerpc/platforms/powernv/eeh-powernv.c if (!(status & mask)) mask 1211 arch/powerpc/platforms/powernv/eeh-powernv.c unsigned long addr, unsigned long mask) mask 1240 arch/powerpc/platforms/powernv/eeh-powernv.c type, func, addr, mask); mask 34 arch/powerpc/platforms/powernv/opal-irqchip.c unsigned long mask; mask 46 arch/powerpc/platforms/powernv/opal-irqchip.c e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask; mask 68 arch/powerpc/platforms/powernv/opal-irqchip.c e = be64_to_cpu(events) & opal_event_irqchip.mask; mask 75 arch/powerpc/platforms/powernv/opal-irqchip.c if (last_outstanding_events & opal_event_irqchip.mask) mask 82 arch/powerpc/platforms/powernv/opal-irqchip.c clear_bit(d->hwirq, &opal_event_irqchip.mask); mask 87 arch/powerpc/platforms/powernv/opal-irqchip.c set_bit(d->hwirq, &opal_event_irqchip.mask); mask 112 arch/powerpc/platforms/powernv/opal-irqchip.c .mask = 0, mask 60 arch/powerpc/platforms/powernv/pci-ioda-tce.c unsigned long mask = (tbl->it_level_size - 1) << (level * shift); mask 63 arch/powerpc/platforms/powernv/pci-ioda-tce.c int n = (idx & mask) >> (level * shift); mask 88 arch/powerpc/platforms/powernv/pci-ioda-tce.c idx &= ~mask; mask 89 arch/powerpc/platforms/powernv/pci-ioda-tce.c mask >>= shift; mask 2687 arch/powerpc/platforms/powernv/pci-ioda.c unsigned long mask = 0; mask 2693 arch/powerpc/platforms/powernv/pci-ioda.c mask = SZ_4K | SZ_64K; mask 2697 arch/powerpc/platforms/powernv/pci-ioda.c mask |= SZ_16M | SZ_256M; mask 2698 arch/powerpc/platforms/powernv/pci-ioda.c return mask; mask 2705 arch/powerpc/platforms/powernv/pci-ioda.c mask |= 1ULL << val; mask 2708 arch/powerpc/platforms/powernv/pci-ioda.c return mask; mask 26 arch/powerpc/platforms/powernv/rng.c unsigned long mask; mask 49 arch/powerpc/platforms/powernv/rng.c val ^= rng->mask; mask 52 arch/powerpc/platforms/powernv/rng.c rng->mask = (rng->mask << 1) | (parity & 1); mask 158 arch/powerpc/platforms/powernv/rng.c rng->mask = val; mask 174 arch/powerpc/platforms/powernv/subcore.c u64 hid0, mask; mask 177 arch/powerpc/platforms/powernv/subcore.c mask = HID0_POWER8_2LPARMODE | HID0_POWER8_4LPARMODE; mask 181 arch/powerpc/platforms/powernv/subcore.c while (mfspr(SPRN_HID0) & mask) mask 193 arch/powerpc/platforms/powernv/subcore.c while (mfspr(SPRN_HID0) & mask) mask 205 arch/powerpc/platforms/powernv/subcore.c struct { u64 value; u64 mask; } split_parms[2] = { mask 231 arch/powerpc/platforms/powernv/subcore.c while (!(mfspr(SPRN_HID0) & split_parms[i].mask)) mask 277 arch/powerpc/platforms/powernv/subcore.c int mask = sibling_mask_first_cpu << offset; mask 279 arch/powerpc/platforms/powernv/subcore.c paca_ptrs[cpu]->subcore_sibling_mask = mask; mask 61 arch/powerpc/platforms/ps3/interrupt.c unsigned long mask; mask 103 arch/powerpc/platforms/ps3/interrupt.c clear_bit(63 - d->irq, &pd->bmp.mask); mask 124 arch/powerpc/platforms/ps3/interrupt.c set_bit(63 - d->irq, &pd->bmp.mask); mask 640 arch/powerpc/platforms/ps3/interrupt.c _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line); mask 651 arch/powerpc/platforms/ps3/interrupt.c _dump_64_bmp("mask", (u64*)&pd->bmp.mask, pd->thread_id, func, line); mask 704 arch/powerpc/platforms/ps3/interrupt.c u64 x = (pd->bmp.status & pd->bmp.mask); mask 462 arch/powerpc/platforms/ps3/spu.c static void int_mask_and(struct spu *spu, int class, u64 mask) mask 468 arch/powerpc/platforms/ps3/spu.c spu_int_mask_set(spu, class, old_mask & mask); mask 471 arch/powerpc/platforms/ps3/spu.c static void int_mask_or(struct spu *spu, int class, u64 mask) mask 476 arch/powerpc/platforms/ps3/spu.c spu_int_mask_set(spu, class, old_mask | mask); mask 479 arch/powerpc/platforms/ps3/spu.c static void int_mask_set(struct spu *spu, int class, u64 mask) mask 481 arch/powerpc/platforms/ps3/spu.c spu_pdata(spu)->cache.masks[class] = mask; mask 684 arch/powerpc/platforms/ps3/system-bus.c static int ps3_dma_supported(struct device *_dev, u64 mask) mask 686 arch/powerpc/platforms/ps3/system-bus.c return mask >= DMA_BIT_MASK(32); mask 129 arch/powerpc/platforms/pseries/ibmebus.c static int ibmebus_dma_supported(struct device *dev, u64 mask) mask 131 arch/powerpc/platforms/pseries/ibmebus.c return mask == DMA_BIT_MASK(64); mask 436 arch/powerpc/platforms/pseries/lpar.c static void set_global_dtl_mask(u8 mask) mask 440 arch/powerpc/platforms/pseries/lpar.c dtl_mask = mask; mask 146 arch/powerpc/sysdev/cpm2.c u32 mask = 7; mask 253 arch/powerpc/sysdev/cpm2.c mask <<= shift; mask 257 arch/powerpc/sysdev/cpm2.c mask |= mask << 3; mask 260 arch/powerpc/sysdev/cpm2.c mask <<= 3; mask 263 arch/powerpc/sysdev/cpm2.c out_be32(reg, (in_be32(reg) & ~mask) | bits); mask 276 arch/powerpc/sysdev/cpm2.c u8 mask = 3; mask 294 arch/powerpc/sysdev/cpm2.c mask = 3; mask 299 arch/powerpc/sysdev/cpm2.c mask = 3; mask 317 arch/powerpc/sysdev/cpm2.c mask <<= shift; mask 319 arch/powerpc/sysdev/cpm2.c out_8(reg, (in_8(reg) & ~mask) | bits); mask 385 arch/powerpc/sysdev/dart_iommu.c static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask) mask 389 arch/powerpc/sysdev/dart_iommu.c mask >= DMA_BIT_MASK(40); mask 30 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 32 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmimr, mask); mask 33 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmcimr, mask); mask 34 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmmcmr, mask); mask 35 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cpmnmimr, mask); mask 41 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 43 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmimr0, mask); mask 44 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmcimr0, mask); mask 45 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmmcmr0, mask); mask 46 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tpmnmimr0, mask); mask 52 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 54 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cpmimr, mask); mask 55 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cpmcimr, mask); mask 56 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cpmmcmr, mask); mask 57 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cpmnmimr, mask); mask 63 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 65 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v2_regs->tpmimr0, mask); mask 66 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v2_regs->tpmcimr0, mask); mask 67 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v2_regs->tpmmcmr0, mask); mask 68 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v2_regs->tpmnmimr0, mask); mask 71 arch/powerpc/sysdev/fsl_rcpm.c static void rcpm_v1_set_ip_power(bool enable, u32 mask) mask 74 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->ippdexpcr, mask); mask 76 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->ippdexpcr, mask); mask 79 arch/powerpc/sysdev/fsl_rcpm.c static void rcpm_v2_set_ip_power(bool enable, u32 mask) mask 82 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->ippdexpcr[0], mask); mask 84 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask); mask 90 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 94 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cdozcr, mask); mask 97 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v1_regs->cnapcr, mask); mask 108 arch/powerpc/sysdev/fsl_rcpm.c u32 mask = 1 << cpu_core_index_of_thread(cpu); mask 116 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph15setr, mask); mask 119 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph20setr, mask); mask 122 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph30setr, mask); mask 167 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; mask 171 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cdozcr, mask); mask 174 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(&rcpm_v1_regs->cnapcr, mask); mask 191 arch/powerpc/sysdev/fsl_rcpm.c u32 mask = 1 << cpu_core_index_of_thread(cpu); mask 198 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph15clrr, mask); mask 201 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph20clrr, mask); mask 204 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->pcph30clrr, mask); mask 286 arch/powerpc/sysdev/fsl_rcpm.c static u32 mask; mask 289 arch/powerpc/sysdev/fsl_rcpm.c mask = in_be32(tben_reg); mask 290 arch/powerpc/sysdev/fsl_rcpm.c clrbits32(tben_reg, mask); mask 292 arch/powerpc/sysdev/fsl_rcpm.c setbits32(tben_reg, mask); mask 115 arch/powerpc/sysdev/ge/ge_pic.c u32 mask; mask 118 arch/powerpc/sysdev/ge/ge_pic.c mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask 119 arch/powerpc/sysdev/ge/ge_pic.c mask &= ~(1 << hwirq); mask 120 arch/powerpc/sysdev/ge/ge_pic.c out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); mask 136 arch/powerpc/sysdev/ge/ge_pic.c u32 mask; mask 139 arch/powerpc/sysdev/ge/ge_pic.c mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask 140 arch/powerpc/sysdev/ge/ge_pic.c mask |= (1 << hwirq); mask 141 arch/powerpc/sysdev/ge/ge_pic.c out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask); mask 230 arch/powerpc/sysdev/ge/ge_pic.c u32 cause, mask, active; mask 236 arch/powerpc/sysdev/ge/ge_pic.c mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); mask 238 arch/powerpc/sysdev/ge/ge_pic.c active = cause & mask; mask 34 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 41 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 48 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 55 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 62 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 69 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 76 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 83 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 90 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 97 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 104 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 111 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 118 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 125 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 132 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 139 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 147 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 155 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 163 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 171 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 179 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 187 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 195 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 202 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 209 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 216 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 223 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 230 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 237 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 244 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 251 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 258 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 265 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 272 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 279 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 286 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 293 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 300 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 307 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_H, mask 315 arch/powerpc/sysdev/ipic.c .mask = IPIC_SEMSR, mask 322 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 329 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 336 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 343 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 350 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 357 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 364 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 371 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 378 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 384 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 390 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 396 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 402 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 408 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 414 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 420 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 426 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 432 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 438 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 444 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 450 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 456 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 462 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 468 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 474 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 480 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 486 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 492 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 498 arch/powerpc/sysdev/ipic.c .mask = IPIC_SIMSR_L, mask 529 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); mask 531 arch/powerpc/sysdev/ipic.c ipic_write(ipic->regs, ipic_info[src].mask, temp); mask 545 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); mask 547 arch/powerpc/sysdev/ipic.c ipic_write(ipic->regs, ipic_info[src].mask, temp); mask 584 arch/powerpc/sysdev/ipic.c temp = ipic_read(ipic->regs, ipic_info[src].mask); mask 586 arch/powerpc/sysdev/ipic.c ipic_write(ipic->regs, ipic_info[src].mask, temp); mask 785 arch/powerpc/sysdev/ipic.c void ipic_clear_mcp_status(u32 mask) mask 787 arch/powerpc/sysdev/ipic.c ipic_write(primary_ipic->regs, IPIC_SERSR, mask); mask 48 arch/powerpc/sysdev/ipic.h u8 mask; /* mask register offset from base */ mask 381 arch/powerpc/sysdev/mpic.c unsigned int mask = 1U << (fixup->index & 0x1f); mask 382 arch/powerpc/sysdev/mpic.c writel(mask, fixup->applebase + soff); mask 627 arch/powerpc/sysdev/mpic.c u32 mask = 0; mask 630 arch/powerpc/sysdev/mpic.c mask |= (cpumask & 1) << get_hard_smp_processor_id(i); mask 631 arch/powerpc/sysdev/mpic.c return mask; mask 835 arch/powerpc/sysdev/mpic.c u32 mask = cpumask_bits(cpumask)[0]; mask 837 arch/powerpc/sysdev/mpic.c mask &= cpumask_bits(cpu_online_mask)[0]; mask 840 arch/powerpc/sysdev/mpic.c mpic_physmask(mask)); mask 1140 arch/powerpc/sysdev/mpic.c u32 mask = 0x3; mask 1153 arch/powerpc/sysdev/mpic.c mask = 0x1; mask 1154 arch/powerpc/sysdev/mpic.c *out_flags = map_mpic_senses[intspec[1] & mask]; mask 275 arch/powerpc/sysdev/tsi108_pci.c static int mask = 0; mask 287 arch/powerpc/sysdev/tsi108_pci.c for (i = 0; i < 4; i++, mask++) { mask 288 arch/powerpc/sysdev/tsi108_pci.c if (temp & (1 << mask % 4)) { mask 289 arch/powerpc/sysdev/tsi108_pci.c irq = IRQ_PCI_INTA + mask % 4; mask 290 arch/powerpc/sysdev/tsi108_pci.c mask++; mask 433 arch/powerpc/sysdev/xive/common.c bool mask) mask 445 arch/powerpc/sysdev/xive/common.c if (mask) { mask 509 arch/powerpc/sysdev/xive/common.c static int xive_find_target_in_mask(const struct cpumask *mask, mask 515 arch/powerpc/sysdev/xive/common.c num = min_t(int, cpumask_weight(mask), nr_cpu_ids); mask 519 arch/powerpc/sysdev/xive/common.c cpu = cpumask_first(mask); mask 521 arch/powerpc/sysdev/xive/common.c cpu = cpumask_next(cpu, mask); mask 541 arch/powerpc/sysdev/xive/common.c cpu = cpumask_next(cpu, mask); mask 544 arch/powerpc/sysdev/xive/common.c cpu = cpumask_first(mask); mask 560 arch/powerpc/sysdev/xive/common.c cpumask_var_t mask; mask 568 arch/powerpc/sysdev/xive/common.c zalloc_cpumask_var(&mask, GFP_ATOMIC)) { mask 573 arch/powerpc/sysdev/xive/common.c cpumask_set_cpu(cpu, mask); mask 576 arch/powerpc/sysdev/xive/common.c if (cpumask_empty(mask)) mask 579 arch/powerpc/sysdev/xive/common.c cpu = xive_find_target_in_mask(mask, fuzz++); mask 580 arch/powerpc/sysdev/xive/common.c free_cpumask_var(mask); mask 94 arch/powerpc/xmon/ppc-dis.c if ((insn & opcode->mask) != opcode->opcode mask 1458 arch/powerpc/xmon/ppc-opc.c long mask = (insn >> 12) & 0xff; mask 1464 arch/powerpc/xmon/ppc-opc.c if (mask == 0 || (mask & -mask) != mask) mask 1471 arch/powerpc/xmon/ppc-opc.c if (mask != 0) mask 1474 arch/powerpc/xmon/ppc-opc.c mask = -1; mask 1477 arch/powerpc/xmon/ppc-opc.c return mask; mask 1566 arch/powerpc/xmon/ppc-opc.c unsigned long uval, mask; mask 1589 arch/powerpc/xmon/ppc-opc.c for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) mask 1591 arch/powerpc/xmon/ppc-opc.c if ((uval & mask) && !last) mask 1597 arch/powerpc/xmon/ppc-opc.c else if (!(uval & mask) && last) mask 45 arch/powerpc/xmon/ppc.h unsigned long mask; mask 3015 arch/powerpc/xmon/xmon.c static unsigned mask; mask 3031 arch/powerpc/xmon/xmon.c mask = ~0; mask 3033 arch/powerpc/xmon/xmon.c scanhex((void *)&mask); mask 3039 arch/powerpc/xmon/xmon.c && ((GETWORD(val) ^ mval) & mask) == 0) { mask 32 arch/riscv/include/asm/smp.h void arch_send_call_function_ipi_mask(struct cpumask *mask); mask 23 arch/riscv/include/asm/word-at-a-time.h unsigned long mask = ((val - c->one_bits) & ~val) & c->high_bits; mask 24 arch/riscv/include/asm/word-at-a-time.h *bits = mask; mask 25 arch/riscv/include/asm/word-at-a-time.h return mask; mask 40 arch/riscv/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 42 arch/riscv/include/asm/word-at-a-time.h return fls64(mask) >> 3; mask 46 arch/riscv/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 21 arch/riscv/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 23 arch/riscv/kernel/perf_regs.c if (!mask || mask & REG_RESERVED) mask 84 arch/riscv/kernel/smp.c static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) mask 90 arch/riscv/kernel/smp.c for_each_cpu(cpu, mask) mask 94 arch/riscv/kernel/smp.c riscv_cpuid_to_hartid_mask(mask, &hartid_mask); mask 172 arch/riscv/kernel/smp.c void arch_send_call_function_ipi_mask(struct cpumask *mask) mask 174 arch/riscv/kernel/smp.c send_ipi_mask(mask, IPI_CALL_FUNC); mask 187 arch/riscv/kernel/smp.c cpumask_t mask; mask 189 arch/riscv/kernel/smp.c cpumask_copy(&mask, cpu_online_mask); mask 190 arch/riscv/kernel/smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 194 arch/riscv/kernel/smp.c send_ipi_mask(&mask, IPI_CPU_STOP); mask 32 arch/riscv/mm/cacheflush.c cpumask_t others, hmask, *mask; mask 37 arch/riscv/mm/cacheflush.c mask = &mm->context.icache_stale_mask; mask 38 arch/riscv/mm/cacheflush.c cpumask_setall(mask); mask 41 arch/riscv/mm/cacheflush.c cpumask_clear_cpu(cpu, mask); mask 28 arch/riscv/mm/context.c cpumask_t *mask = &mm->context.icache_stale_mask; mask 30 arch/riscv/mm/context.c if (cpumask_test_cpu(cpu, mask)) { mask 31 arch/riscv/mm/context.c cpumask_clear_cpu(cpu, mask); mask 119 arch/s390/boot/mem_detect.c S390_lowcore.program_new_psw.mask = __extract_psw(); mask 46 arch/s390/boot/pgm_check_info.c p = add_val_as_hex(p, S390_lowcore.psw_save_area.mask); mask 62 arch/s390/include/asm/barrier.h unsigned long mask; mask 67 arch/s390/include/asm/barrier.h :"=d" (mask) : "d" (size-1), "d" (index) :"cc"); mask 68 arch/s390/include/asm/barrier.h return mask; mask 72 arch/s390/include/asm/barrier.h :"=d" (mask) : "d" (size), "d" (index) :"cc"); mask 73 arch/s390/include/asm/barrier.h return ~mask; mask 62 arch/s390/include/asm/bitops.h unsigned long mask; mask 76 arch/s390/include/asm/bitops.h mask = 1UL << (nr & (BITS_PER_LONG - 1)); mask 77 arch/s390/include/asm/bitops.h __atomic64_or(mask, (long *)addr); mask 83 arch/s390/include/asm/bitops.h unsigned long mask; mask 97 arch/s390/include/asm/bitops.h mask = ~(1UL << (nr & (BITS_PER_LONG - 1))); mask 98 arch/s390/include/asm/bitops.h __atomic64_and(mask, (long *)addr); mask 105 arch/s390/include/asm/bitops.h unsigned long mask; mask 119 arch/s390/include/asm/bitops.h mask = 1UL << (nr & (BITS_PER_LONG - 1)); mask 120 arch/s390/include/asm/bitops.h __atomic64_xor(mask, (long *)addr); mask 127 arch/s390/include/asm/bitops.h unsigned long old, mask; mask 129 arch/s390/include/asm/bitops.h mask = 1UL << (nr & (BITS_PER_LONG - 1)); mask 130 arch/s390/include/asm/bitops.h old = __atomic64_or_barrier(mask, (long *)addr); mask 131 arch/s390/include/asm/bitops.h return (old & mask) != 0; mask 138 arch/s390/include/asm/bitops.h unsigned long old, mask; mask 140 arch/s390/include/asm/bitops.h mask = ~(1UL << (nr & (BITS_PER_LONG - 1))); mask 141 arch/s390/include/asm/bitops.h old = __atomic64_and_barrier(mask, (long *)addr); mask 142 arch/s390/include/asm/bitops.h return (old & ~mask) != 0; mask 149 arch/s390/include/asm/bitops.h unsigned long old, mask; mask 151 arch/s390/include/asm/bitops.h mask = 1UL << (nr & (BITS_PER_LONG - 1)); mask 152 arch/s390/include/asm/bitops.h old = __atomic64_xor_barrier(mask, (long *)addr); mask 153 arch/s390/include/asm/bitops.h return (old & mask) != 0; mask 365 arch/s390/include/asm/bitops.h unsigned long mask = 2 * BITS_PER_LONG - 1; mask 368 arch/s390/include/asm/bitops.h return (1 + (__flogr(-val & val) ^ (BITS_PER_LONG - 1))) & mask; mask 395 arch/s390/include/asm/bitops.h unsigned long mask = 2 * BITS_PER_LONG - 1; mask 397 arch/s390/include/asm/bitops.h return (1 + (__flogr(word) ^ (BITS_PER_LONG - 1))) & mask; mask 208 arch/s390/include/asm/ccwdev.h int ccw_device_get_mdc(struct ccw_device *cdev, u8 mask); mask 354 arch/s390/include/asm/cio.h static inline u8 pathmask_to_pos(u8 mask) mask 356 arch/s390/include/asm/cio.h return 8 - ffs(mask); mask 70 arch/s390/include/asm/compat.h u32 mask; mask 174 arch/s390/include/asm/cpacf.h static __always_inline void __cpacf_query(unsigned int opcode, cpacf_mask_t *mask) mask 177 arch/s390/include/asm/cpacf.h register unsigned long r1 asm("1") = (unsigned long) mask; mask 184 arch/s390/include/asm/cpacf.h : "=m" (*mask) mask 214 arch/s390/include/asm/cpacf.h static __always_inline int cpacf_query(unsigned int opcode, cpacf_mask_t *mask) mask 217 arch/s390/include/asm/cpacf.h __cpacf_query(opcode, mask); mask 220 arch/s390/include/asm/cpacf.h memset(mask, 0, sizeof(*mask)); mask 224 arch/s390/include/asm/cpacf.h static inline int cpacf_test_func(cpacf_mask_t *mask, unsigned int func) mask 226 arch/s390/include/asm/cpacf.h return (mask->bytes[func >> 3] & (0x80 >> (func & 7))) != 0; mask 231 arch/s390/include/asm/cpacf.h cpacf_mask_t mask; mask 233 arch/s390/include/asm/cpacf.h if (cpacf_query(opcode, &mask)) mask 234 arch/s390/include/asm/cpacf.h return cpacf_test_func(&mask, func); mask 97 arch/s390/include/asm/fpu/api.h state->mask = S390_lowcore.fpu_flags; mask 101 arch/s390/include/asm/fpu/api.h else if (state->mask & flags) mask 109 arch/s390/include/asm/fpu/api.h S390_lowcore.fpu_flags = state->mask; mask 110 arch/s390/include/asm/fpu/api.h if (state->mask & flags) mask 30 arch/s390/include/asm/fpu/types.h u32 mask; mask 830 arch/s390/include/asm/kvm_host.h u8 mask; mask 172 arch/s390/include/asm/processor.h regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \ mask 179 arch/s390/include/asm/processor.h regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \ mask 257 arch/s390/include/asm/processor.h static __no_kasan_or_inline void __load_psw_mask(unsigned long mask) mask 262 arch/s390/include/asm/processor.h psw.mask = mask; mask 298 arch/s390/include/asm/processor.h unsigned long mask; mask 300 arch/s390/include/asm/processor.h mask = (psw.mask & PSW_MASK_EA) ? -1UL : mask 301 arch/s390/include/asm/processor.h (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 : mask 303 arch/s390/include/asm/processor.h return (psw.addr - ilc) & mask; mask 318 arch/s390/include/asm/processor.h psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA; mask 161 arch/s390/include/asm/ptrace.h #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0) mask 24 arch/s390/include/asm/smp.h extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 56 arch/s390/include/asm/syscall.h unsigned long mask = -1UL; mask 61 arch/s390/include/asm/syscall.h mask = 0xffffffff; mask 65 arch/s390/include/asm/syscall.h args[n] = regs->gprs[2 + n] & mask; mask 67 arch/s390/include/asm/syscall.h args[0] = regs->orig_gpr2 & mask; mask 162 arch/s390/include/asm/sysinfo.h unsigned long mask; mask 66 arch/s390/include/uapi/asm/kvm.h __u8 mask; mask 212 arch/s390/include/uapi/asm/ptrace.h unsigned long mask; mask 230 arch/s390/include/uapi/asm/sie.h #define INSN_DECODE_IPA0(ipa0, insn, rshift, mask) \ mask 232 arch/s390/include/uapi/asm/sie.h ((ipa0 << 8) | ((insn >> rshift) & mask)) : mask 43 arch/s390/include/uapi/asm/sigcontext.h unsigned long mask; mask 37 arch/s390/kernel/compat_linux.h __u32 mask; mask 71 arch/s390/kernel/compat_signal.c user_sregs.regs.psw.mask = (__u32)(regs->psw.mask >> 32); mask 72 arch/s390/kernel/compat_signal.c user_sregs.regs.psw.mask &= PSW32_MASK_USER | PSW32_MASK_RI; mask 73 arch/s390/kernel/compat_signal.c user_sregs.regs.psw.mask |= PSW32_USER_BITS; mask 75 arch/s390/kernel/compat_signal.c (__u32)(regs->psw.mask & PSW_MASK_BA); mask 97 arch/s390/kernel/compat_signal.c if (!is_ri_task(current) && (user_sregs.regs.psw.mask & PSW32_MASK_RI)) mask 105 arch/s390/kernel/compat_signal.c regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) | mask 106 arch/s390/kernel/compat_signal.c (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_USER) << 32 | mask 107 arch/s390/kernel/compat_signal.c (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_RI) << 32 | mask 110 arch/s390/kernel/compat_signal.c if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) mask 111 arch/s390/kernel/compat_signal.c regs->psw.mask = PSW_ASC_PRIMARY | mask 112 arch/s390/kernel/compat_signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 317 arch/s390/kernel/compat_signal.c regs->psw.mask = PSW_MASK_BA | mask 319 arch/s390/kernel/compat_signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 399 arch/s390/kernel/compat_signal.c regs->psw.mask = PSW_MASK_BA | mask 401 arch/s390/kernel/compat_signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 67 arch/s390/kernel/dis.c unsigned char mask; mask 410 arch/s390/kernel/dis.c opfrag = *(code + entry->byte) & entry->mask; mask 152 arch/s390/kernel/dumpstack.c printk("%s PSW : %px %px", mode, (void *)regs->psw.mask, (void *)regs->psw.addr); mask 171 arch/s390/kernel/early.c psw.mask = PSW_MASK_BASE | PSW_DEFAULT_KEY | PSW_MASK_EA | PSW_MASK_BA; mask 22 arch/s390/kernel/fpu.c flags &= state->mask; mask 104 arch/s390/kernel/fpu.c flags &= state->mask; mask 213 arch/s390/kernel/kprobes.c kcb->kprobe_saved_imask = regs->psw.mask & mask 218 arch/s390/kernel/kprobes.c regs->psw.mask |= PSW_MASK_PER; mask 219 arch/s390/kernel/kprobes.c regs->psw.mask &= ~(PSW_MASK_IO | PSW_MASK_EXT); mask 230 arch/s390/kernel/kprobes.c regs->psw.mask &= ~PSW_MASK_PER; mask 231 arch/s390/kernel/kprobes.c regs->psw.mask |= kcb->kprobe_saved_imask; mask 526 arch/s390/kernel/kprobes.c if (regs->psw.mask & PSW_MASK_PER) mask 598 arch/s390/kernel/kprobes.c if (regs->psw.mask & (PSW_MASK_IO | PSW_MASK_EXT)) mask 601 arch/s390/kernel/kprobes.c if (regs->psw.mask & (PSW_MASK_IO | PSW_MASK_EXT)) mask 602 arch/s390/kernel/kprobes.c local_irq_restore(regs->psw.mask & ~PSW_MASK_PER); mask 617 arch/s390/kernel/kprobes.c if (regs->psw.mask & (PSW_MASK_IO | PSW_MASK_EXT)) mask 638 arch/s390/kernel/kprobes.c if (regs->psw.mask & (PSW_MASK_IO | PSW_MASK_EXT)) mask 639 arch/s390/kernel/kprobes.c local_irq_restore(regs->psw.mask & ~PSW_MASK_PER); mask 70 arch/s390/kernel/perf_event.c return sie_block(regs)->gpsw.mask & PSW_MASK_PSTATE; mask 29 arch/s390/kernel/perf_regs.c return regs->psw.mask; mask 39 arch/s390/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 41 arch/s390/kernel/perf_regs.c if (!mask || mask & REG_RESERVED) mask 120 arch/s390/kernel/process.c frame->childregs.psw.mask = PSW_KERNEL_BITS | PSW_MASK_DAT | mask 139 arch/s390/kernel/process.c frame->childregs.psw.mask &= ~PSW_MASK_RI; mask 108 arch/s390/kernel/ptrace.c regs->psw.mask &= ~PSW_MASK_PER; mask 111 arch/s390/kernel/ptrace.c regs->psw.mask |= PSW_MASK_PER; mask 211 arch/s390/kernel/ptrace.c if (addr == (addr_t) &dummy->regs.psw.mask) { mask 281 arch/s390/kernel/ptrace.c addr_t tmp, mask; mask 287 arch/s390/kernel/ptrace.c mask = __ADDR_MASK; mask 290 arch/s390/kernel/ptrace.c mask = 3; mask 291 arch/s390/kernel/ptrace.c if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK) mask 342 arch/s390/kernel/ptrace.c if (addr == (addr_t) &dummy->regs.psw.mask) { mask 343 arch/s390/kernel/ptrace.c unsigned long mask = PSW_MASK_USER; mask 345 arch/s390/kernel/ptrace.c mask |= is_ri_task(child) ? PSW_MASK_RI : 0; mask 346 arch/s390/kernel/ptrace.c if ((data ^ PSW_USER_BITS) & ~mask) mask 423 arch/s390/kernel/ptrace.c addr_t mask; mask 429 arch/s390/kernel/ptrace.c mask = __ADDR_MASK; mask 432 arch/s390/kernel/ptrace.c mask = 3; mask 433 arch/s390/kernel/ptrace.c if ((addr & mask) || addr > sizeof(struct user) - __ADDR_MASK) mask 589 arch/s390/kernel/ptrace.c if (addr == (addr_t) &dummy32->regs.psw.mask) { mask 591 arch/s390/kernel/ptrace.c tmp = (__u32)(regs->psw.mask >> 32); mask 597 arch/s390/kernel/ptrace.c (__u32)(regs->psw.mask & PSW_MASK_BA); mask 701 arch/s390/kernel/ptrace.c if (addr == (addr_t) &dummy32->regs.psw.mask) { mask 702 arch/s390/kernel/ptrace.c __u32 mask = PSW32_MASK_USER; mask 704 arch/s390/kernel/ptrace.c mask |= is_ri_task(child) ? PSW32_MASK_RI : 0; mask 706 arch/s390/kernel/ptrace.c if ((tmp ^ PSW32_USER_BITS) & ~mask) mask 712 arch/s390/kernel/ptrace.c regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | mask 713 arch/s390/kernel/ptrace.c (regs->psw.mask & PSW_MASK_BA) | mask 714 arch/s390/kernel/ptrace.c (__u64)(tmp & mask) << 32; mask 719 arch/s390/kernel/ptrace.c regs->psw.mask = (regs->psw.mask & ~PSW_MASK_BA) | mask 840 arch/s390/kernel/ptrace.c unsigned long mask = -1UL; mask 868 arch/s390/kernel/ptrace.c mask = 0xffffffff; mask 870 arch/s390/kernel/ptrace.c audit_syscall_entry(regs->gprs[2], regs->orig_gpr2 & mask, mask 871 arch/s390/kernel/ptrace.c regs->gprs[3] &mask, regs->gprs[4] &mask, mask 872 arch/s390/kernel/ptrace.c regs->gprs[5] &mask); mask 50 arch/s390/kernel/runtime_instr.c regs->psw.mask &= ~PSW_MASK_RI; mask 394 arch/s390/kernel/setup.c lc->restart_psw.mask = PSW_KERNEL_BITS; mask 396 arch/s390/kernel/setup.c lc->external_new_psw.mask = PSW_KERNEL_BITS | PSW_MASK_MCHECK; mask 398 arch/s390/kernel/setup.c lc->svc_new_psw.mask = PSW_KERNEL_BITS | mask 401 arch/s390/kernel/setup.c lc->program_new_psw.mask = PSW_KERNEL_BITS | PSW_MASK_MCHECK; mask 403 arch/s390/kernel/setup.c lc->mcck_new_psw.mask = PSW_KERNEL_BITS; mask 405 arch/s390/kernel/setup.c lc->io_new_psw.mask = PSW_KERNEL_BITS | PSW_MASK_MCHECK; mask 471 arch/s390/kernel/setup.c S390_lowcore.external_new_psw.mask |= PSW_MASK_DAT; mask 472 arch/s390/kernel/setup.c S390_lowcore.svc_new_psw.mask |= PSW_MASK_DAT; mask 473 arch/s390/kernel/setup.c S390_lowcore.program_new_psw.mask |= PSW_MASK_DAT; mask 474 arch/s390/kernel/setup.c S390_lowcore.io_new_psw.mask |= PSW_MASK_DAT; mask 126 arch/s390/kernel/signal.c user_sregs.regs.psw.mask = PSW_USER_BITS | mask 127 arch/s390/kernel/signal.c (regs->psw.mask & (PSW_MASK_USER | PSW_MASK_RI)); mask 148 arch/s390/kernel/signal.c if (!is_ri_task(current) && (user_sregs.regs.psw.mask & PSW_MASK_RI)) mask 156 arch/s390/kernel/signal.c regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) | mask 157 arch/s390/kernel/signal.c (user_sregs.regs.psw.mask & (PSW_MASK_USER | PSW_MASK_RI)); mask 159 arch/s390/kernel/signal.c if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) mask 160 arch/s390/kernel/signal.c regs->psw.mask = PSW_ASC_PRIMARY | mask 161 arch/s390/kernel/signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 163 arch/s390/kernel/signal.c if (regs->psw.mask & PSW_MASK_EA) mask 164 arch/s390/kernel/signal.c regs->psw.mask |= PSW_MASK_BA; mask 349 arch/s390/kernel/signal.c regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA | mask 351 arch/s390/kernel/signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 427 arch/s390/kernel/signal.c regs->psw.mask = PSW_MASK_EA | PSW_MASK_BA | mask 429 arch/s390/kernel/signal.c (regs->psw.mask & ~PSW_MASK_ASC); mask 168 arch/s390/kernel/smp.c static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) mask 172 arch/s390/kernel/smp.c for_each_cpu(cpu, mask) mask 512 arch/s390/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 516 arch/s390/kernel/smp.c for_each_cpu(cpu, mask) mask 217 arch/s390/kernel/suspend.c S390_lowcore.external_new_psw.mask &= ~PSW_MASK_MCHECK; mask 218 arch/s390/kernel/suspend.c S390_lowcore.svc_new_psw.mask &= ~PSW_MASK_MCHECK; mask 219 arch/s390/kernel/suspend.c S390_lowcore.io_new_psw.mask &= ~PSW_MASK_MCHECK; mask 220 arch/s390/kernel/suspend.c S390_lowcore.program_new_psw.mask &= ~PSW_MASK_MCHECK; mask 225 arch/s390/kernel/suspend.c S390_lowcore.external_new_psw.mask |= PSW_MASK_MCHECK; mask 226 arch/s390/kernel/suspend.c S390_lowcore.svc_new_psw.mask |= PSW_MASK_MCHECK; mask 227 arch/s390/kernel/suspend.c S390_lowcore.io_new_psw.mask |= PSW_MASK_MCHECK; mask 228 arch/s390/kernel/suspend.c S390_lowcore.program_new_psw.mask |= PSW_MASK_MCHECK; mask 265 arch/s390/kernel/time.c .mask = -1ULL, mask 45 arch/s390/kernel/topology.c cpumask_t mask; mask 70 arch/s390/kernel/topology.c cpumask_t mask; mask 72 arch/s390/kernel/topology.c cpumask_copy(&mask, cpumask_of(cpu)); mask 76 arch/s390/kernel/topology.c if (cpumask_test_cpu(cpu, &info->mask)) { mask 77 arch/s390/kernel/topology.c mask = info->mask; mask 82 arch/s390/kernel/topology.c if (cpumask_empty(&mask)) mask 83 arch/s390/kernel/topology.c cpumask_copy(&mask, cpumask_of(cpu)); mask 86 arch/s390/kernel/topology.c cpumask_copy(&mask, cpu_present_mask); mask 91 arch/s390/kernel/topology.c cpumask_copy(&mask, cpumask_of(cpu)); mask 94 arch/s390/kernel/topology.c return mask; mask 99 arch/s390/kernel/topology.c cpumask_t mask; mask 102 arch/s390/kernel/topology.c cpumask_copy(&mask, cpumask_of(cpu)); mask 104 arch/s390/kernel/topology.c return mask; mask 108 arch/s390/kernel/topology.c cpumask_set_cpu(cpu + i, &mask); mask 109 arch/s390/kernel/topology.c return mask; mask 122 arch/s390/kernel/topology.c for_each_set_bit(core, &tl_core->mask, TOPOLOGY_CORE_BITS) { mask 138 arch/s390/kernel/topology.c cpumask_set_cpu(lcpu + i, &drawer->mask); mask 139 arch/s390/kernel/topology.c cpumask_set_cpu(lcpu + i, &book->mask); mask 140 arch/s390/kernel/topology.c cpumask_set_cpu(lcpu + i, &socket->mask); mask 153 arch/s390/kernel/topology.c cpumask_clear(&info->mask); mask 158 arch/s390/kernel/topology.c cpumask_clear(&info->mask); mask 163 arch/s390/kernel/topology.c cpumask_clear(&info->mask); mask 514 arch/s390/kernel/topology.c struct mask_info *mask, int offset) mask 523 arch/s390/kernel/topology.c mask->next = memblock_alloc(sizeof(*mask->next), 8); mask 524 arch/s390/kernel/topology.c if (!mask->next) mask 526 arch/s390/kernel/topology.c __func__, sizeof(*mask->next), 8); mask 527 arch/s390/kernel/topology.c mask = mask->next; mask 243 arch/s390/kernel/traps.c regs->psw.mask |= PSW_ASC_HOME; mask 29 arch/s390/kernel/unwind_bc.c unsigned long *mask = &state->stack_mask; mask 32 arch/s390/kernel/unwind_bc.c if (get_stack_info(sp, state->task, info, mask) != 0 || mask 86 arch/s390/kernel/unwind_bc.c if (READ_ONCE_NOCHECK(regs->psw.mask) & PSW_MASK_PSTATE) mask 119 arch/s390/kernel/unwind_bc.c unsigned long *mask = &state->stack_mask; mask 135 arch/s390/kernel/unwind_bc.c if (get_stack_info(sp, task, info, mask) != 0 || mask 57 arch/s390/kernel/uprobes.c if (!(regs->psw.mask & PSW_MASK_PER)) mask 175 arch/s390/kernel/uprobes.c unsigned int mask = sizeof(*(ptr)) - 1; \ mask 181 arch/s390/kernel/uprobes.c else if ((u64 __force)ptr & mask) \ mask 192 arch/s390/kernel/uprobes.c unsigned int mask = sizeof(*(ptr)) - 1; \ mask 198 arch/s390/kernel/uprobes.c else if ((u64 __force)__ptr & mask) \ mask 205 arch/s390/kernel/uprobes.c mask + 1); \ mask 211 arch/s390/kernel/uprobes.c unsigned int mask = sizeof(*(ptr)) - 1; \ mask 217 arch/s390/kernel/uprobes.c else if ((u64 __force)ptr & mask) \ mask 252 arch/s390/kernel/uprobes.c if (!(regs->psw.mask & PSW_MASK_PER)) mask 242 arch/s390/kvm/diag.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 495 arch/s390/kvm/guestdbg.c (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PER) mask 281 arch/s390/kvm/intercept.c (newpsw.mask & PSW_MASK_EXT)) mask 438 arch/s390/kvm/intercept.c !(newpsw.mask & PSW_MASK_WAIT) && mask 439 arch/s390/kvm/intercept.c !(oldpsw.mask & PSW_MASK_PSTATE) && mask 440 arch/s390/kvm/intercept.c (newpsw.mask & PSW_MASK_ASC) == (oldpsw.mask & PSW_MASK_ASC) && mask 441 arch/s390/kvm/intercept.c (newpsw.mask & PSW_MASK_DAT) == (oldpsw.mask & PSW_MASK_DAT)) mask 146 arch/s390/kvm/interrupt.c return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_EXT); mask 151 arch/s390/kvm/interrupt.c return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_IO); mask 156 arch/s390/kvm/interrupt.c return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_MCHECK); mask 290 arch/s390/kvm/interrupt.c alert_mask = READ_ONCE(gi->alert.mask); mask 2456 arch/s390/kvm/interrupt.c ret = kvm_s390_mask_adapter(dev->kvm, req.id, req.mask); mask 3089 arch/s390/kvm/interrupt.c gi->alert.mask = 0; mask 3105 arch/s390/kvm/interrupt.c if (gi->alert.mask) mask 3107 arch/s390/kvm/interrupt.c kvm, gi->alert.mask); mask 3143 arch/s390/kvm/interrupt.c gi->alert.mask |= 0x80 >> gisc; mask 3144 arch/s390/kvm/interrupt.c gisa_set_iam(gi->origin, gi->alert.mask); mask 3187 arch/s390/kvm/interrupt.c gi->alert.mask &= ~(0x80 >> gisc); mask 3188 arch/s390/kvm/interrupt.c gisa_set_iam(gi->origin, gi->alert.mask); mask 2111 arch/s390/kvm/kvm-s390.c unsigned long hva, mask, pgstev, i; mask 2115 arch/s390/kvm/kvm-s390.c mask = args->mask; mask 2150 arch/s390/kvm/kvm-s390.c mask &= _PGSTE_GPS_USAGE_MASK | _PGSTE_GPS_NODAT; mask 2151 arch/s390/kvm/kvm-s390.c set_pgste_bits(kvm->mm, hva, mask, pgstev); mask 2856 arch/s390/kvm/kvm-s390.c vcpu->arch.sie_block->gpsw.mask = 0UL; mask 3100 arch/s390/kvm/kvm-s390.c return !(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE); mask 3386 arch/s390/kvm/kvm-s390.c vcpu->run->psw_mask = psw.mask; mask 3673 arch/s390/kvm/kvm-s390.c if ((vcpu->arch.sie_block->gpsw.mask & vcpu->arch.pfault_select) != mask 3874 arch/s390/kvm/kvm-s390.c vcpu->arch.sie_block->gpsw.mask = kvm_run->psw_mask; mask 3961 arch/s390/kvm/kvm-s390.c kvm_run->psw_mask = vcpu->arch.sie_block->gpsw.mask; mask 44 arch/s390/kvm/kvm-s390.h d_vcpu->arch.sie_block->gpsw.mask, d_vcpu->arch.sie_block->gpsw.addr,\ mask 165 arch/s390/kvm/kvm-s390.h vcpu->arch.sie_block->gpsw.mask &= ~(3UL << 44); mask 166 arch/s390/kvm/kvm-s390.h vcpu->arch.sie_block->gpsw.mask |= cc << 44; mask 95 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 121 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 159 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 189 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 256 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 303 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 354 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 445 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 571 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 638 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 688 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 712 arch/s390/kvm/priv.c if (psw->mask & PSW_MASK_UNASSIGNED) mask 714 arch/s390/kvm/priv.c if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_BA) { mask 718 arch/s390/kvm/priv.c if (!(psw->mask & PSW_MASK_ADDR_MODE) && (psw->addr & ~PSW_ADDR_24)) mask 720 arch/s390/kvm/priv.c if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_EA) mask 737 arch/s390/kvm/priv.c if (gpsw->mask & PSW_MASK_PSTATE) mask 747 arch/s390/kvm/priv.c if (!(new_psw.mask & PSW32_MASK_BASE)) mask 749 arch/s390/kvm/priv.c gpsw->mask = (new_psw.mask & ~PSW32_MASK_BASE) << 32; mask 750 arch/s390/kvm/priv.c gpsw->mask |= new_psw.addr & PSW32_ADDR_AMODE; mask 766 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 790 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 857 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 988 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; mask 992 arch/s390/kvm/priv.c vcpu->arch.sie_block->gpsw.mask & 0x00000000ffffffffUL; mask 1021 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1198 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1285 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1324 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1358 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1396 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1445 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 1455 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) mask 1485 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT) mask 1506 arch/s390/kvm/priv.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 82 arch/s390/kvm/sigp.c || (psw->mask & psw_int_mask) != psw_int_mask mask 419 arch/s390/kvm/sigp.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 27 arch/s390/kvm/trace.h __entry->pswmask = vcpu->arch.sie_block->gpsw.mask; \ mask 1294 arch/s390/kvm/vsie.c if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) mask 282 arch/s390/mm/fault.c if (regs->psw.mask & PSW_MASK_PSTATE) { mask 340 arch/s390/mm/gmap.c unsigned long offset, mask; mask 344 arch/s390/mm/gmap.c mask = ~(PTRS_PER_PMD * sizeof(pmd_t) - 1); mask 345 arch/s390/mm/gmap.c page = virt_to_page((void *)((unsigned long) entry & mask)); mask 113 arch/s390/mm/init.c psw.mask = __extract_psw(); mask 116 arch/s390/mm/init.c __load_psw_mask(psw.mask); mask 221 arch/s390/mm/kasan_init.c psw.mask = __extract_psw(); mask 224 arch/s390/mm/kasan_init.c __load_psw_mask(psw.mask); mask 60 arch/s390/mm/pageattr.c unsigned long table, mask; mask 62 arch/s390/mm/pageattr.c mask = 0; mask 66 arch/s390/mm/pageattr.c mask = ~(PTRS_PER_PUD * sizeof(pud_t) - 1); mask 69 arch/s390/mm/pageattr.c mask = ~(PTRS_PER_PMD * sizeof(pmd_t) - 1); mask 72 arch/s390/mm/pageattr.c mask = ~(PTRS_PER_PTE * sizeof(pte_t) - 1); mask 75 arch/s390/mm/pageattr.c table = (unsigned long)old & mask; mask 196 arch/s390/mm/pgalloc.c unsigned int mask, bit; mask 205 arch/s390/mm/pgalloc.c mask = atomic_read(&page->_refcount) >> 24; mask 206 arch/s390/mm/pgalloc.c mask = (mask | (mask >> 4)) & 3; mask 207 arch/s390/mm/pgalloc.c if (mask != 3) { mask 209 arch/s390/mm/pgalloc.c bit = mask & 1; /* =1 -> second 2K */ mask 251 arch/s390/mm/pgalloc.c unsigned int bit, mask; mask 258 arch/s390/mm/pgalloc.c mask = atomic_xor_bits(&page->_refcount, 1U << (bit + 24)); mask 259 arch/s390/mm/pgalloc.c mask >>= 24; mask 260 arch/s390/mm/pgalloc.c if (mask & 3) mask 265 arch/s390/mm/pgalloc.c if (mask != 0) mask 280 arch/s390/mm/pgalloc.c unsigned int bit, mask; mask 292 arch/s390/mm/pgalloc.c mask = atomic_xor_bits(&page->_refcount, 0x11U << (bit + 24)); mask 293 arch/s390/mm/pgalloc.c mask >>= 24; mask 294 arch/s390/mm/pgalloc.c if (mask & 3) mask 305 arch/s390/mm/pgalloc.c unsigned int mask = (unsigned long) _table & 3; mask 306 arch/s390/mm/pgalloc.c void *table = (void *)((unsigned long) _table ^ mask); mask 309 arch/s390/mm/pgalloc.c switch (mask) { mask 315 arch/s390/mm/pgalloc.c mask = atomic_xor_bits(&page->_refcount, mask << (4 + 24)); mask 316 arch/s390/mm/pgalloc.c mask >>= 24; mask 317 arch/s390/mm/pgalloc.c if (mask != 0) mask 321 arch/s390/mm/pgalloc.c if (mask & 3) mask 830 arch/s390/mm/pgtable.c unsigned char tmp, mask = _PAGE_ACC_BITS | _PAGE_FP_BIT; mask 841 arch/s390/mm/pgtable.c mask |= _PAGE_REFERENCED; mask 843 arch/s390/mm/pgtable.c mask |= _PAGE_CHANGED; mask 844 arch/s390/mm/pgtable.c if (!((tmp ^ key) & mask)) mask 227 arch/s390/net/bpf_jit_comp.c #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ mask 231 arch/s390/net/bpf_jit_comp.c op2 | mask << 12); \ mask 236 arch/s390/net/bpf_jit_comp.c #define EMIT6_PCREL_IMM_LABEL(op1, op2, b1, imm, label, mask) \ mask 239 arch/s390/net/bpf_jit_comp.c _EMIT6(op1 | (reg_high(b1) | mask) << 16 | \ mask 245 arch/s390/net/bpf_jit_comp.c #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ mask 249 arch/s390/net/bpf_jit_comp.c _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ mask 516 arch/s390/net/bpf_jit_comp.c unsigned int mask; mask 1140 arch/s390/net/bpf_jit_comp.c mask = 0xf000; /* j */ mask 1144 arch/s390/net/bpf_jit_comp.c mask = 0x2000; /* jh */ mask 1148 arch/s390/net/bpf_jit_comp.c mask = 0x4000; /* jl */ mask 1152 arch/s390/net/bpf_jit_comp.c mask = 0xa000; /* jhe */ mask 1156 arch/s390/net/bpf_jit_comp.c mask = 0xc000; /* jle */ mask 1160 arch/s390/net/bpf_jit_comp.c mask = 0x2000; /* jh */ mask 1164 arch/s390/net/bpf_jit_comp.c mask = 0x4000; /* jl */ mask 1168 arch/s390/net/bpf_jit_comp.c mask = 0xa000; /* jhe */ mask 1172 arch/s390/net/bpf_jit_comp.c mask = 0xc000; /* jle */ mask 1176 arch/s390/net/bpf_jit_comp.c mask = 0x7000; /* jne */ mask 1180 arch/s390/net/bpf_jit_comp.c mask = 0x8000; /* je */ mask 1184 arch/s390/net/bpf_jit_comp.c mask = 0x7000; /* jnz */ mask 1200 arch/s390/net/bpf_jit_comp.c mask = 0x2000; /* jh */ mask 1204 arch/s390/net/bpf_jit_comp.c mask = 0x4000; /* jl */ mask 1208 arch/s390/net/bpf_jit_comp.c mask = 0xa000; /* jhe */ mask 1212 arch/s390/net/bpf_jit_comp.c mask = 0xc000; /* jle */ mask 1216 arch/s390/net/bpf_jit_comp.c mask = 0x2000; /* jh */ mask 1220 arch/s390/net/bpf_jit_comp.c mask = 0x4000; /* jl */ mask 1224 arch/s390/net/bpf_jit_comp.c mask = 0xa000; /* jhe */ mask 1228 arch/s390/net/bpf_jit_comp.c mask = 0xc000; /* jle */ mask 1232 arch/s390/net/bpf_jit_comp.c mask = 0x7000; /* jne */ mask 1236 arch/s390/net/bpf_jit_comp.c mask = 0x8000; /* je */ mask 1243 arch/s390/net/bpf_jit_comp.c mask = 0x7000; /* jnz */ mask 1254 arch/s390/net/bpf_jit_comp.c dst_reg, REG_W1, i, off, mask); mask 1262 arch/s390/net/bpf_jit_comp.c dst_reg, REG_W1, i, off, mask); mask 1268 arch/s390/net/bpf_jit_comp.c dst_reg, src_reg, i, off, mask); mask 1274 arch/s390/net/bpf_jit_comp.c dst_reg, src_reg, i, off, mask); mask 1279 arch/s390/net/bpf_jit_comp.c EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); mask 344 arch/s390/numa/mode_emu.c WARN_ON(cpumask_weight(&phys->mask)); mask 368 arch/s390/numa/mode_emu.c cpumask_set_cpu(cpu, &core->mask); mask 382 arch/s390/numa/mode_emu.c for_each_cpu(cpu, &core->mask) { mask 384 arch/s390/numa/mode_emu.c cpumask_copy(&top->thread_mask, &core->mask); mask 385 arch/s390/numa/mode_emu.c cpumask_copy(&top->core_mask, &core_mc(core)->mask); mask 386 arch/s390/numa/mode_emu.c cpumask_copy(&top->book_mask, &core_book(core)->mask); mask 387 arch/s390/numa/mode_emu.c cpumask_copy(&top->drawer_mask, &core_drawer(core)->mask); mask 43 arch/s390/numa/toptree.c cpumask_clear(&res->mask); mask 104 arch/s390/numa/toptree.c cpumask_clear(&cand->mask); mask 106 arch/s390/numa/toptree.c cpumask_or(&cand->mask, &cand->mask, &child->mask); mask 169 arch/s390/numa/toptree.c if (!cpumask_empty(&child->mask)) { mask 18 arch/s390/numa/toptree.h cpumask_t mask; mask 591 arch/s390/pci/pci.c int pcibios_enable_device(struct pci_dev *pdev, int mask) mask 598 arch/s390/pci/pci.c return pci_enable_resources(pdev, mask); mask 51 arch/s390/pci/pci_clp.c unsigned long mask; mask 60 arch/s390/pci/pci_clp.c : [cc] "+d" (cc), [mask] "=d" (mask) : [cmd] "a" (1) mask 62 arch/s390/pci/pci_clp.c *ilp = mask; mask 292 arch/s390/pci/pci_irq.c (cpumask_first(&msi->affinity->mask) << 8) : 0; mask 18 arch/s390/tools/gen_opcode_table.c unsigned char mask; mask 69 arch/s390/tools/gen_opcode_table.c .mask = 0xff, mask 84 arch/s390/tools/gen_opcode_table.c .mask = 0x0f, mask 94 arch/s390/tools/gen_opcode_table.c .mask = 0xff, mask 109 arch/s390/tools/gen_opcode_table.c .mask = 0xff, mask 313 arch/s390/tools/gen_opcode_table.c group->opcode, group->type->mask, group->type->byte, group->offset, group->count); mask 196 arch/sh/boards/board-sh7785lcr.c .mask = 0x0, mask 57 arch/sh/boards/mach-cayman/irq.c unsigned long mask; mask 65 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); mask 66 arch/sh/boards/mach-cayman/irq.c mask |= bit; mask 67 arch/sh/boards/mach-cayman/irq.c __raw_writel(mask, reg); mask 75 arch/sh/boards/mach-cayman/irq.c unsigned long mask; mask 83 arch/sh/boards/mach-cayman/irq.c mask = __raw_readl(reg); mask 84 arch/sh/boards/mach-cayman/irq.c mask &= ~bit; mask 85 arch/sh/boards/mach-cayman/irq.c __raw_writel(mask, reg); mask 67 arch/sh/boards/mach-dreamcast/irq.c __u32 mask; mask 69 arch/sh/boards/mach-dreamcast/irq.c mask = inl(emr); mask 70 arch/sh/boards/mach-dreamcast/irq.c mask &= ~(1 << EVENT_BIT(irq)); mask 71 arch/sh/boards/mach-dreamcast/irq.c outl(mask, emr); mask 79 arch/sh/boards/mach-dreamcast/irq.c __u32 mask; mask 81 arch/sh/boards/mach-dreamcast/irq.c mask = inl(emr); mask 82 arch/sh/boards/mach-dreamcast/irq.c mask |= (1 << EVENT_BIT(irq)); mask 83 arch/sh/boards/mach-dreamcast/irq.c outl(mask, emr); mask 21 arch/sh/boards/mach-highlander/psw.c unsigned int l, mask; mask 32 arch/sh/boards/mach-highlander/psw.c mask = l & 0x70; mask 34 arch/sh/boards/mach-highlander/psw.c if (mask & (1 << psw_info->bit)) { mask 35 arch/sh/boards/mach-highlander/psw.c psw->state = !!(mask & (1 << psw_info->bit)); mask 50 arch/sh/boards/mach-sdk7786/nmi.c unsigned int source, mask, tmp; mask 55 arch/sh/boards/mach-sdk7786/nmi.c mask = NMIMR_MAN_NMIM; mask 59 arch/sh/boards/mach-sdk7786/nmi.c mask = NMIMR_AUX_NMIM; mask 63 arch/sh/boards/mach-sdk7786/nmi.c mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM; mask 68 arch/sh/boards/mach-sdk7786/nmi.c source = mask = 0; mask 79 arch/sh/boards/mach-sdk7786/nmi.c fpga_write_reg(NMIMR_MASK ^ mask, NMIMR); mask 33 arch/sh/boards/mach-se/7206/irq.c unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq))); mask 38 arch/sh/boards/mach-se/7206/irq.c val &= mask; mask 33 arch/sh/boards/mach-se/7343/irq.c unsigned long mask; mask 38 arch/sh/boards/mach-se/7343/irq.c mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG); mask 40 arch/sh/boards/mach-se/7343/irq.c for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR) mask 84 arch/sh/boards/mach-se/7343/irq.c ct->regs.mask = PA_CPLD_IMSK_REG; mask 32 arch/sh/boards/mach-se/7722/irq.c unsigned long mask; mask 37 arch/sh/boards/mach-se/7722/irq.c mask = ioread16(se7722_irq_regs + IRQ01_STS_REG); mask 39 arch/sh/boards/mach-se/7722/irq.c for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR) mask 83 arch/sh/boards/mach-se/7722/irq.c ct->regs.mask = IRQ01_MASK_REG; mask 26 arch/sh/boards/mach-se/7724/irq.c unsigned short mask; mask 50 arch/sh/boards/mach-se/7724/irq.c set.mask = IRQ0_MASK; mask 56 arch/sh/boards/mach-se/7724/irq.c set.mask = IRQ1_MASK; mask 62 arch/sh/boards/mach-se/7724/irq.c set.mask = IRQ2_MASK; mask 99 arch/sh/boards/mach-se/7724/irq.c intv &= set.mask; mask 64 arch/sh/boards/mach-x3proto/gpio.c unsigned long mask; mask 69 arch/sh/boards/mach-x3proto/gpio.c mask = __raw_readw(KEYDETR); mask 70 arch/sh/boards/mach-x3proto/gpio.c for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS) mask 25 arch/sh/cchips/hd6446x/hd64461.c unsigned short mask = 1 << (irq - HD64461_IRQBASE); mask 28 arch/sh/cchips/hd6446x/hd64461.c nimr |= mask; mask 36 arch/sh/cchips/hd6446x/hd64461.c unsigned short mask = 1 << (irq - HD64461_IRQBASE); mask 39 arch/sh/cchips/hd6446x/hd64461.c nimr &= ~mask; mask 41 arch/sh/drivers/heartbeat.c new &= hd->mask; mask 45 arch/sh/drivers/heartbeat.c new |= ioread32(hd->base) & ~hd->mask; mask 49 arch/sh/drivers/heartbeat.c new |= ioread16(hd->base) & ~hd->mask; mask 53 arch/sh/drivers/heartbeat.c new |= ioread8(hd->base) & ~hd->mask; mask 114 arch/sh/drivers/heartbeat.c hd->mask = 0; mask 116 arch/sh/drivers/heartbeat.c hd->mask |= (1 << hd->bit_pos[i]); mask 67 arch/sh/drivers/pci/pci-sh7780.c unsigned int mask; mask 121 arch/sh/drivers/pci/pci-sh7780.c if (status & pci_arbiter_errors[i].mask) { mask 124 arch/sh/drivers/pci/pci-sh7780.c cmd |= pci_arbiter_errors[i].mask; mask 134 arch/sh/drivers/pci/pci-sh7780.c if (status & pci_interrupt_errors[i].mask) { mask 137 arch/sh/drivers/pci/pci-sh7780.c cmd |= pci_interrupt_errors[i].mask; mask 166 arch/sh/drivers/pci/pcie-sh7786.c static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) mask 171 arch/sh/drivers/pci/pcie-sh7786.c if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) mask 444 arch/sh/drivers/pci/pcie-sh7786.c u32 mask; mask 463 arch/sh/drivers/pci/pcie-sh7786.c mask = (roundup_pow_of_two(size) / SZ_256K) - 1; mask 464 arch/sh/drivers/pci/pcie-sh7786.c pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); mask 471 arch/sh/drivers/pci/pcie-sh7786.c mask = MASK_PARE; mask 473 arch/sh/drivers/pci/pcie-sh7786.c mask |= MASK_SPC; mask 475 arch/sh/drivers/pci/pcie-sh7786.c pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win)); mask 16 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 20 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 23 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old|mask) != old); mask 28 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 32 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 35 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old&~mask) != old); mask 40 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 44 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 47 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old^mask) != old); mask 52 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 56 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 59 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old|mask) != old); mask 61 arch/sh/include/asm/bitops-cas.h return !!(old & mask); mask 66 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 70 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 73 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old&~mask) != old); mask 75 arch/sh/include/asm/bitops-cas.h return !!(old & mask); mask 80 arch/sh/include/asm/bitops-cas.h unsigned mask, old; mask 84 arch/sh/include/asm/bitops-cas.h mask = 1U << (nr & 0x1f); mask 87 arch/sh/include/asm/bitops-cas.h while (__bo_cas(a, old, old^mask) != old); mask 89 arch/sh/include/asm/bitops-cas.h return !!(old & mask); mask 7 arch/sh/include/asm/bitops-grb.h int mask; mask 12 arch/sh/include/asm/bitops-grb.h mask = 1 << (nr & 0x1f); mask 25 arch/sh/include/asm/bitops-grb.h : "r" (mask) mask 31 arch/sh/include/asm/bitops-grb.h int mask; mask 36 arch/sh/include/asm/bitops-grb.h mask = ~(1 << (nr & 0x1f)); mask 48 arch/sh/include/asm/bitops-grb.h : "r" (mask) mask 54 arch/sh/include/asm/bitops-grb.h int mask; mask 59 arch/sh/include/asm/bitops-grb.h mask = 1 << (nr & 0x1f); mask 71 arch/sh/include/asm/bitops-grb.h : "r" (mask) mask 77 arch/sh/include/asm/bitops-grb.h int mask, retval; mask 82 arch/sh/include/asm/bitops-grb.h mask = 1 << (nr & 0x1f); mask 100 arch/sh/include/asm/bitops-grb.h : "r" (mask) mask 108 arch/sh/include/asm/bitops-grb.h int mask, retval,not_mask; mask 113 arch/sh/include/asm/bitops-grb.h mask = 1 << (nr & 0x1f); mask 115 arch/sh/include/asm/bitops-grb.h not_mask = ~mask; mask 133 arch/sh/include/asm/bitops-grb.h : "r" (mask), mask 142 arch/sh/include/asm/bitops-grb.h int mask, retval; mask 147 arch/sh/include/asm/bitops-grb.h mask = 1 << (nr & 0x1f); mask 165 arch/sh/include/asm/bitops-grb.h : "r" (mask) mask 7 arch/sh/include/asm/bitops-llsc.h int mask; mask 12 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 21 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (mask) mask 28 arch/sh/include/asm/bitops-llsc.h int mask; mask 33 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 42 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (~mask) mask 49 arch/sh/include/asm/bitops-llsc.h int mask; mask 54 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 63 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (mask) mask 70 arch/sh/include/asm/bitops-llsc.h int mask, retval; mask 75 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 86 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (mask) mask 95 arch/sh/include/asm/bitops-llsc.h int mask, retval; mask 100 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 112 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (mask), "r" (~mask) mask 121 arch/sh/include/asm/bitops-llsc.h int mask, retval; mask 126 arch/sh/include/asm/bitops-llsc.h mask = 1 << (nr & 0x1f); mask 138 arch/sh/include/asm/bitops-llsc.h : "r" (a), "r" (mask) mask 31 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 34 arch/sh/include/asm/bitops-op32.h *p |= mask; mask 49 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 52 arch/sh/include/asm/bitops-op32.h *p &= ~mask; mask 76 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 79 arch/sh/include/asm/bitops-op32.h *p ^= mask; mask 94 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 98 arch/sh/include/asm/bitops-op32.h *p = old | mask; mask 99 arch/sh/include/asm/bitops-op32.h return (old & mask) != 0; mask 113 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 117 arch/sh/include/asm/bitops-op32.h *p = old & ~mask; mask 118 arch/sh/include/asm/bitops-op32.h return (old & mask) != 0; mask 125 arch/sh/include/asm/bitops-op32.h unsigned long mask = BIT_MASK(nr); mask 129 arch/sh/include/asm/bitops-op32.h *p = old ^ mask; mask 130 arch/sh/include/asm/bitops-op32.h return (old & mask) != 0; mask 15 arch/sh/include/asm/heartbeat.h unsigned int mask; mask 40 arch/sh/include/asm/smp.h void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 18 arch/sh/include/asm/word-at-a-time.h static inline long count_masked_bytes(long mask) mask 21 arch/sh/include/asm/word-at-a-time.h long a = (0x0ff0001+mask) >> 23; mask 23 arch/sh/include/asm/word-at-a-time.h return a & mask; mask 29 arch/sh/include/asm/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 30 arch/sh/include/asm/word-at-a-time.h *bits = mask; mask 31 arch/sh/include/asm/word-at-a-time.h return mask; mask 46 arch/sh/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 48 arch/sh/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 50 arch/sh/include/asm/word-at-a-time.h return count_masked_bytes(mask); mask 19 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg) mask 20 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg) mask 21 arch/sh/include/mach-common/mach/magicpanelr2.h #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg) mask 22 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg) mask 23 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg) mask 24 arch/sh/include/mach-common/mach/magicpanelr2.h #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg) mask 41 arch/sh/include/mach-common/mach/secureedge5410.h #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ mask 43 arch/sh/include/mach-common/mach/secureedge5410.h ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) mask 44 arch/sh/kernel/cpu/sh4a/ubc.c static void sh4a_ubc_enable_all(unsigned long mask) mask 49 arch/sh/kernel/cpu/sh4a/ubc.c if (mask & (1 << i)) mask 80 arch/sh/kernel/cpu/sh4a/ubc.c static void sh4a_ubc_clear_triggered_mask(unsigned long mask) mask 82 arch/sh/kernel/cpu/sh4a/ubc.c __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); mask 232 arch/sh/kernel/irq.c struct cpumask *mask = irq_data_get_affinity_mask(data); mask 233 arch/sh/kernel/irq.c unsigned int newcpu = cpumask_any_and(mask, mask 239 arch/sh/kernel/irq.c cpumask_setall(mask); mask 241 arch/sh/kernel/irq.c irq_set_affinity(irq, mask); mask 220 arch/sh/kernel/signal_32.c unsigned long mask) mask 243 arch/sh/kernel/signal_32.c err |= __put_user(mask, &sc->oldmask); mask 323 arch/sh/kernel/signal_64.c unsigned long mask) mask 354 arch/sh/kernel/signal_64.c err |= __put_user(mask, &sc->oldmask); mask 271 arch/sh/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 275 arch/sh/kernel/smp.c for_each_cpu(cpu, mask) mask 285 arch/sh/kernel/smp.c void tick_broadcast(const struct cpumask *mask) mask 289 arch/sh/kernel/smp.c for_each_cpu(cpu, mask) mask 22 arch/sparc/include/asm/bitops_32.h unsigned long ___set_bit(unsigned long *addr, unsigned long mask); mask 23 arch/sparc/include/asm/bitops_32.h unsigned long ___clear_bit(unsigned long *addr, unsigned long mask); mask 24 arch/sparc/include/asm/bitops_32.h unsigned long ___change_bit(unsigned long *addr, unsigned long mask); mask 34 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 37 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 39 arch/sparc/include/asm/bitops_32.h return ___set_bit(ADDR, mask) != 0; mask 44 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 47 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 49 arch/sparc/include/asm/bitops_32.h (void) ___set_bit(ADDR, mask); mask 54 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 57 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 59 arch/sparc/include/asm/bitops_32.h return ___clear_bit(ADDR, mask) != 0; mask 64 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 67 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 69 arch/sparc/include/asm/bitops_32.h (void) ___clear_bit(ADDR, mask); mask 74 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 77 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 79 arch/sparc/include/asm/bitops_32.h return ___change_bit(ADDR, mask) != 0; mask 84 arch/sparc/include/asm/bitops_32.h unsigned long *ADDR, mask; mask 87 arch/sparc/include/asm/bitops_32.h mask = 1 << (nr & 31); mask 89 arch/sparc/include/asm/bitops_32.h (void) ___change_bit(ADDR, mask); mask 74 arch/sparc/include/asm/cmpxchg_64.h unsigned int mask = 0xffff << bit_shift; mask 83 arch/sparc/include/asm/cmpxchg_64.h new32 = (load32 & (~mask)) | val << bit_shift; mask 87 arch/sparc/include/asm/cmpxchg_64.h return (load32 & mask) >> bit_shift; mask 135 arch/sparc/include/asm/cmpxchg_64.h unsigned int mask = 0xff << bit_shift; mask 141 arch/sparc/include/asm/cmpxchg_64.h new32 = (load32 & ~mask) | (new << bit_shift); mask 142 arch/sparc/include/asm/cmpxchg_64.h old32 = (load32 & ~mask) | (old << bit_shift); mask 146 arch/sparc/include/asm/cmpxchg_64.h load = (load32 & mask) >> bit_shift; mask 68 arch/sparc/include/asm/fbio.h u32 mask; /* cursor mask bits */ mask 484 arch/sparc/include/asm/floppy_64.h unsigned char mask = 0x00; mask 492 arch/sparc/include/asm/floppy_64.h mask |= 1 << (status & 0x03); mask 495 arch/sparc/include/asm/floppy_64.h } while ((mask != 0x0f) && --timeout); mask 46 arch/sparc/include/asm/iommu-common.h unsigned long mask, mask 90 arch/sparc/include/asm/irq_64.h void arch_trigger_cpumask_backtrace(const struct cpumask *mask, mask 110 arch/sparc/include/asm/leon_amba.h u32 mask[16]; mask 93 arch/sparc/include/asm/mdesc.h void mdesc_fill_in_cpu_data(cpumask_t *mask); mask 94 arch/sparc/include/asm/mdesc.h void mdesc_populate_present_mask(cpumask_t *mask); mask 95 arch/sparc/include/asm/mdesc.h void mdesc_get_page_sizes(cpumask_t *mask, unsigned long *pgsz_mask); mask 104 arch/sparc/include/asm/obio.h int mask; mask 107 arch/sparc/include/asm/obio.h "=r" (mask) : mask 110 arch/sparc/include/asm/obio.h return mask; mask 113 arch/sparc/include/asm/obio.h static inline void bw_clear_intr_mask(int sbus_level, int mask) mask 116 arch/sparc/include/asm/obio.h "r" (mask), mask 180 arch/sparc/include/asm/obio.h unsigned int mask; mask 183 arch/sparc/include/asm/obio.h "=r" (mask) : mask 186 arch/sparc/include/asm/obio.h return mask; mask 189 arch/sparc/include/asm/obio.h static inline void cc_set_imsk(unsigned int mask) mask 192 arch/sparc/include/asm/obio.h "r" (mask), mask 199 arch/sparc/include/asm/obio.h unsigned int mask; mask 202 arch/sparc/include/asm/obio.h "=r" (mask) : mask 205 arch/sparc/include/asm/obio.h return mask; mask 208 arch/sparc/include/asm/obio.h static inline void cc_set_imsk_other(int cpuid, unsigned int mask) mask 211 arch/sparc/include/asm/obio.h "r" (mask), mask 282 arch/sparc/include/asm/pgtable_64.h unsigned long mask, tmp; mask 324 arch/sparc/include/asm/pgtable_64.h : "=r" (mask), "=r" (tmp) mask 335 arch/sparc/include/asm/pgtable_64.h return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); mask 385 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 395 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 398 arch/sparc/include/asm/pgtable_64.h return mask; mask 408 arch/sparc/include/asm/pgtable_64.h unsigned long mask = __pte_default_huge_mask(); mask 410 arch/sparc/include/asm/pgtable_64.h return (pte_val(pte) & mask) == mask; mask 491 arch/sparc/include/asm/pgtable_64.h unsigned long val = pte_val(pte), mask; mask 501 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 504 arch/sparc/include/asm/pgtable_64.h return __pte(val | mask); mask 533 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 543 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 546 arch/sparc/include/asm/pgtable_64.h mask |= _PAGE_R; mask 548 arch/sparc/include/asm/pgtable_64.h return __pte(pte_val(pte) & ~mask); mask 553 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 563 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 566 arch/sparc/include/asm/pgtable_64.h mask |= _PAGE_R; mask 568 arch/sparc/include/asm/pgtable_64.h return __pte(pte_val(pte) | mask); mask 591 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 601 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 604 arch/sparc/include/asm/pgtable_64.h return (pte_val(pte) & mask); mask 609 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 619 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 622 arch/sparc/include/asm/pgtable_64.h return (pte_val(pte) & mask); mask 627 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 637 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 640 arch/sparc/include/asm/pgtable_64.h return (pte_val(pte) & mask); mask 645 arch/sparc/include/asm/pgtable_64.h unsigned long mask; mask 653 arch/sparc/include/asm/pgtable_64.h : "=r" (mask) mask 656 arch/sparc/include/asm/pgtable_64.h return (pte_val(pte) & mask); mask 69 arch/sparc/include/asm/sbi.h static inline int acquire_sbi(int devid, int mask) mask 72 arch/sparc/include/asm/sbi.h "=r" (mask) : mask 73 arch/sparc/include/asm/sbi.h "0" (mask), mask 76 arch/sparc/include/asm/sbi.h return mask; mask 79 arch/sparc/include/asm/sbi.h static inline void release_sbi(int devid, int mask) mask 82 arch/sparc/include/asm/sbi.h "r" (mask), mask 60 arch/sparc/include/asm/smp_32.h void (*cross_call)(smpfunc_t func, cpumask_t mask, unsigned long arg1, mask 98 arch/sparc/include/asm/smp_32.h void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 41 arch/sparc/include/asm/smp_64.h void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 19 arch/sparc/include/asm/vvar.h u64 mask; mask 105 arch/sparc/include/uapi/asm/fbio.h char __user *mask; /* cursor mask bits */ mask 488 arch/sparc/kernel/ds.c cpumask_t *mask, u32 default_stat) mask 505 arch/sparc/kernel/ds.c for_each_cpu(cpu, mask) { mask 534 arch/sparc/kernel/ds.c u64 req_num, cpumask_t *mask) mask 540 arch/sparc/kernel/ds.c ncpus = cpumask_weight(mask); mask 547 arch/sparc/kernel/ds.c resp_len, ncpus, mask, mask 550 arch/sparc/kernel/ds.c mdesc_populate_present_mask(mask); mask 551 arch/sparc/kernel/ds.c mdesc_fill_in_cpu_data(mask); mask 553 arch/sparc/kernel/ds.c for_each_cpu(cpu, mask) { mask 593 arch/sparc/kernel/ds.c cpumask_t *mask) mask 599 arch/sparc/kernel/ds.c ncpus = cpumask_weight(mask); mask 606 arch/sparc/kernel/ds.c resp_len, ncpus, mask, mask 609 arch/sparc/kernel/ds.c for_each_cpu(cpu, mask) { mask 637 arch/sparc/kernel/ds.c cpumask_t mask; mask 654 arch/sparc/kernel/ds.c cpumask_clear(&mask); mask 660 arch/sparc/kernel/ds.c cpumask_set_cpu(cpu_list[i], &mask); mask 664 arch/sparc/kernel/ds.c err = dr_cpu_configure(dp, cp, req_num, &mask); mask 666 arch/sparc/kernel/ds.c err = dr_cpu_unconfigure(dp, cp, req_num, &mask); mask 101 arch/sparc/kernel/iommu-common.c unsigned long mask, mask 153 arch/sparc/kernel/iommu-common.c if (limit + shift > mask) { mask 154 arch/sparc/kernel/iommu-common.c limit = mask - shift + 1; mask 159 arch/sparc/kernel/iommu-common.c if ((start & mask) >= limit || pass > 0) { mask 165 arch/sparc/kernel/iommu-common.c start &= mask; mask 38 arch/sparc/kernel/irq.h u32 mask; mask 351 arch/sparc/kernel/irq_64.c cpumask_t mask; mask 354 arch/sparc/kernel/irq_64.c cpumask_copy(&mask, affinity); mask 355 arch/sparc/kernel/irq_64.c if (cpumask_equal(&mask, cpu_online_mask)) { mask 360 arch/sparc/kernel/irq_64.c cpumask_and(&tmp, cpu_online_mask, &mask); mask 396 arch/sparc/kernel/irq_64.c const struct cpumask *mask, bool force) mask 405 arch/sparc/kernel/irq_64.c cpuid = irq_choose_cpu(data->irq, mask); mask 473 arch/sparc/kernel/irq_64.c const struct cpumask *mask, bool force) mask 475 arch/sparc/kernel/irq_64.c unsigned long cpuid = irq_choose_cpu(data->irq, mask); mask 538 arch/sparc/kernel/irq_64.c const struct cpumask *mask, bool force) mask 545 arch/sparc/kernel/irq_64.c cpuid = irq_choose_cpu(data->irq, mask); mask 51 arch/sparc/kernel/kernel.h #define ali_sound_dma_hack(dev, mask) (0) mask 44 arch/sparc/kernel/leon_kernel.c #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu]) mask 72 arch/sparc/kernel/leon_kernel.c unsigned long mask, oldmask; mask 87 arch/sparc/kernel/leon_kernel.c mask = 1 << eirq; mask 89 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); mask 95 arch/sparc/kernel/leon_kernel.c unsigned long mask; mask 101 arch/sparc/kernel/leon_kernel.c mask = 0; mask 103 arch/sparc/kernel/leon_kernel.c mask = LEON_HARD_INT(irq); mask 105 arch/sparc/kernel/leon_kernel.c return mask; mask 111 arch/sparc/kernel/leon_kernel.c cpumask_t mask; mask 113 arch/sparc/kernel/leon_kernel.c cpumask_and(&mask, cpu_online_mask, affinity); mask 114 arch/sparc/kernel/leon_kernel.c if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) mask 117 arch/sparc/kernel/leon_kernel.c return cpumask_first(&mask); mask 126 arch/sparc/kernel/leon_kernel.c unsigned long mask, oldmask, flags; mask 129 arch/sparc/kernel/leon_kernel.c mask = (unsigned long)data->chip_data; mask 139 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IMASK(oldcpu), (oldmask & ~mask)); mask 141 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IMASK(newcpu), (oldmask | mask)); mask 149 arch/sparc/kernel/leon_kernel.c unsigned long mask, oldmask, flags; mask 152 arch/sparc/kernel/leon_kernel.c mask = (unsigned long)data->chip_data; mask 156 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask | mask)); mask 162 arch/sparc/kernel/leon_kernel.c unsigned long mask, oldmask, flags; mask 165 arch/sparc/kernel/leon_kernel.c mask = (unsigned long)data->chip_data; mask 169 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask & ~mask)); mask 189 arch/sparc/kernel/leon_kernel.c unsigned long mask = (unsigned long)data->chip_data; mask 191 arch/sparc/kernel/leon_kernel.c if (mask & LEON_DO_ACK_HW) mask 192 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(LEON_IACK, mask & ~LEON_DO_ACK_HW); mask 216 arch/sparc/kernel/leon_kernel.c unsigned long mask; mask 220 arch/sparc/kernel/leon_kernel.c mask = leon_get_irqmask(real_irq); mask 221 arch/sparc/kernel/leon_kernel.c if (mask == 0) mask 229 arch/sparc/kernel/leon_kernel.c mask |= LEON_DO_ACK_HW; mask 235 arch/sparc/kernel/leon_kernel.c irq_set_chip_data(irq, (void *)mask); mask 252 arch/sparc/kernel/leon_kernel.c unsigned long mask = (unsigned long)irq_get_chip_data(virq); mask 254 arch/sparc/kernel/leon_kernel.c mask &= ~LEON_DO_ACK_HW; mask 256 arch/sparc/kernel/leon_kernel.c mask |= LEON_DO_ACK_HW; mask 260 arch/sparc/kernel/leon_kernel.c irq_set_chip_data(virq, (void *)mask); mask 418 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[boot_cpu_id], 0); mask 494 arch/sparc/kernel/leon_kernel.c unsigned long mask, flags, *addr; mask 495 arch/sparc/kernel/leon_kernel.c mask = leon_get_irqmask(irq_nr); mask 498 arch/sparc/kernel/leon_kernel.c LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); mask 63 arch/sparc/kernel/leon_pci.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 75 arch/sparc/kernel/leon_pci.c if (!(mask & (1<<i))) mask 134 arch/sparc/kernel/leon_smp.c static void leon_smp_setbroadcast(unsigned int mask) mask 149 arch/sparc/kernel/leon_smp.c LEON_BYPASS_STORE_PA(&(leon3_irqctrl_regs->mpbroadcast), mask); mask 204 arch/sparc/kernel/leon_smp.c LEON_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[i], 0); mask 307 arch/sparc/kernel/leon_smp.c unsigned long mask; mask 308 arch/sparc/kernel/leon_smp.c mask = leon_get_irqmask(level); mask 309 arch/sparc/kernel/leon_smp.c LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask); mask 377 arch/sparc/kernel/leon_smp.c static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, mask 408 arch/sparc/kernel/leon_smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 409 arch/sparc/kernel/leon_smp.c cpumask_and(&mask, cpu_online_mask, &mask); mask 411 arch/sparc/kernel/leon_smp.c if (cpumask_test_cpu(i, &mask)) { mask 425 arch/sparc/kernel/leon_smp.c if (!cpumask_test_cpu(i, &mask)) mask 434 arch/sparc/kernel/leon_smp.c if (!cpumask_test_cpu(i, &mask)) mask 1057 arch/sparc/kernel/mdesc.c static void get_one_mondo_bits(const u64 *p, unsigned int *mask, mask 1072 arch/sparc/kernel/mdesc.c *mask = ((1U << val) * 64U) - 1U; mask 1076 arch/sparc/kernel/mdesc.c *mask = ((1U << def) * 64U) - 1U; mask 1106 arch/sparc/kernel/mdesc.c static void *mdesc_iterate_over_cpus(void *(*func)(struct mdesc_handle *, u64, int, void *), void *arg, cpumask_t *mask) mask 1123 arch/sparc/kernel/mdesc.c if (!cpumask_test_cpu(cpuid, mask)) mask 1146 arch/sparc/kernel/mdesc.c void mdesc_populate_present_mask(cpumask_t *mask) mask 1152 arch/sparc/kernel/mdesc.c mdesc_iterate_over_cpus(record_one_cpu, NULL, mask); mask 1173 arch/sparc/kernel/mdesc.c void __init mdesc_get_page_sizes(cpumask_t *mask, unsigned long *pgsz_mask) mask 1176 arch/sparc/kernel/mdesc.c mdesc_iterate_over_cpus(check_one_pgsz, pgsz_mask, mask); mask 1229 arch/sparc/kernel/mdesc.c void mdesc_fill_in_cpu_data(cpumask_t *mask) mask 1233 arch/sparc/kernel/mdesc.c mdesc_iterate_over_cpus(fill_in_one_cpu, NULL, mask); mask 726 arch/sparc/kernel/pci.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 738 arch/sparc/kernel/pci.c if (!(mask & (1<<i))) mask 1082 arch/sparc/kernel/pci.c u32 mask; mask 1088 arch/sparc/kernel/pci.c mask = prop->slot_mask; mask 1093 arch/sparc/kernel/pci.c node, mask); mask 1096 arch/sparc/kernel/pci.c while (mask) { mask 1100 arch/sparc/kernel/pci.c if (!(mask & this_bit)) { mask 1114 arch/sparc/kernel/pci.c mask &= ~this_bit; mask 76 arch/sparc/kernel/pci_sun4v.c static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) mask 78 arch/sparc/kernel/pci_sun4v.c return iommu->atu && mask > DMA_BIT_MASK(32); mask 82 arch/sparc/kernel/pci_sun4v.c static long iommu_batch_flush(struct iommu_batch *p, u64 mask) mask 100 arch/sparc/kernel/pci_sun4v.c if (!iommu_use_atu(pbm->iommu, mask)) { mask 144 arch/sparc/kernel/pci_sun4v.c static inline void iommu_batch_new_entry(unsigned long entry, u64 mask) mask 151 arch/sparc/kernel/pci_sun4v.c iommu_batch_flush(p, mask); mask 156 arch/sparc/kernel/pci_sun4v.c static inline long iommu_batch_add(u64 phys_page, u64 mask) mask 164 arch/sparc/kernel/pci_sun4v.c return iommu_batch_flush(p, mask); mask 170 arch/sparc/kernel/pci_sun4v.c static inline long iommu_batch_end(u64 mask) mask 176 arch/sparc/kernel/pci_sun4v.c return iommu_batch_flush(p, mask); mask 183 arch/sparc/kernel/pci_sun4v.c u64 mask; mask 212 arch/sparc/kernel/pci_sun4v.c mask = dev->coherent_dma_mask; mask 213 arch/sparc/kernel/pci_sun4v.c if (!iommu_use_atu(iommu, mask)) mask 236 arch/sparc/kernel/pci_sun4v.c long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask); mask 241 arch/sparc/kernel/pci_sun4v.c if (unlikely(iommu_batch_end(mask) < 0L)) mask 361 arch/sparc/kernel/pci_sun4v.c u64 mask; mask 378 arch/sparc/kernel/pci_sun4v.c mask = *dev->dma_mask; mask 379 arch/sparc/kernel/pci_sun4v.c if (!iommu_use_atu(iommu, mask)) mask 405 arch/sparc/kernel/pci_sun4v.c long err = iommu_batch_add(base_paddr, mask); mask 409 arch/sparc/kernel/pci_sun4v.c if (unlikely(iommu_batch_end(mask) < 0L)) mask 480 arch/sparc/kernel/pci_sun4v.c u64 mask; mask 514 arch/sparc/kernel/pci_sun4v.c mask = *dev->dma_mask; mask 515 arch/sparc/kernel/pci_sun4v.c if (!iommu_use_atu(iommu, mask)) mask 544 arch/sparc/kernel/pci_sun4v.c iommu_batch_new_entry(entry, mask); mask 553 arch/sparc/kernel/pci_sun4v.c err = iommu_batch_add(paddr, mask); mask 588 arch/sparc/kernel/pci_sun4v.c err = iommu_batch_end(mask); mask 644 arch/sparc/kernel/pcic.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 656 arch/sparc/kernel/pcic.c if (!(mask & (1<<i))) mask 773 arch/sparc/kernel/pcic.c unsigned long mask, flags; mask 775 arch/sparc/kernel/pcic.c mask = (unsigned long)data->chip_data; mask 777 arch/sparc/kernel/pcic.c writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); mask 783 arch/sparc/kernel/pcic.c unsigned long mask, flags; mask 785 arch/sparc/kernel/pcic.c mask = (unsigned long)data->chip_data; mask 787 arch/sparc/kernel/pcic.c writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); mask 809 arch/sparc/kernel/pcic.c unsigned long mask; mask 812 arch/sparc/kernel/pcic.c mask = get_irqmask(real_irq); mask 813 arch/sparc/kernel/pcic.c if (mask == 0) mask 822 arch/sparc/kernel/pcic.c irq_set_chip_data(irq, (void *)mask); mask 193 arch/sparc/kernel/perf_event.c u64 shift, mask, pic; mask 199 arch/sparc/kernel/perf_event.c mask = ((u64) 0xffffffff) << shift; mask 203 arch/sparc/kernel/perf_event.c pic &= ~mask; mask 829 arch/sparc/kernel/perf_event.c u64 enc, val, mask = mask_for_index(idx); mask 838 arch/sparc/kernel/perf_event.c val &= ~mask; mask 847 arch/sparc/kernel/perf_event.c u64 mask = mask_for_index(idx); mask 856 arch/sparc/kernel/perf_event.c val &= ~mask; mask 252 arch/sparc/kernel/process_64.c void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) mask 268 arch/sparc/kernel/process_64.c if (cpumask_test_cpu(this_cpu, mask) && !exclude_self) mask 273 arch/sparc/kernel/process_64.c for_each_cpu(cpu, mask) { mask 131 arch/sparc/kernel/prom_64.c unsigned long mask = 0xffffffffUL; mask 134 arch/sparc/kernel/prom_64.c mask = 0x7fffff; mask 139 arch/sparc/kernel/prom_64.c (unsigned int) (regs->phys_addr & mask)); mask 336 arch/sparc/kernel/prom_irqtrans.c u64 mask = 1UL << (ino & IMAP_INO); mask 340 arch/sparc/kernel/prom_irqtrans.c schizo_write(sync_reg, mask); mask 346 arch/sparc/kernel/prom_irqtrans.c if (!(val & mask)) mask 351 arch/sparc/kernel/prom_irqtrans.c val, mask); mask 364 arch/sparc/kernel/prom_irqtrans.c : "=&r" (mask), "=&r" (val) mask 365 arch/sparc/kernel/prom_irqtrans.c : "0" (mask), "1" (val), mask 63 arch/sparc/kernel/signal32.c compat_sigset_t mask; mask 245 arch/sparc/kernel/signal32.c err |= get_compat_sigset(&set, &sf->mask); mask 564 arch/sparc/kernel/signal32.c err |= put_compat_sigset(&sf->mask, oldset, sizeof(compat_sigset_t)); mask 52 arch/sparc/kernel/signal_32.c sigset_t mask; mask 181 arch/sparc/kernel/signal_32.c err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t)); mask 372 arch/sparc/kernel/signal_32.c err |= __copy_to_user(&sf->mask, &oldset->sig[0], sizeof(sigset_t)); mask 252 arch/sparc/kernel/signal_64.c sigset_t mask; mask 303 arch/sparc/kernel/signal_64.c err |= __copy_from_user(&set, &sf->mask, sizeof(sigset_t)); mask 407 arch/sparc/kernel/signal_64.c err |= copy_to_user(&sf->mask, sigmask_to_save(), sizeof(sigset_t)); mask 145 arch/sparc/kernel/smp_32.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 150 arch/sparc/kernel/smp_32.c for_each_cpu(cpu, mask) mask 789 arch/sparc/kernel/smp_64.c static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask) mask 822 arch/sparc/kernel/smp_64.c for_each_cpu(i, mask) { mask 838 arch/sparc/kernel/smp_64.c static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask) mask 842 arch/sparc/kernel/smp_64.c xcall_deliver(data0, data1, data2, mask); mask 861 arch/sparc/kernel/smp_64.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 863 arch/sparc/kernel/smp_64.c xcall_deliver((u64) &xcall_call_function, 0, 0, mask); mask 110 arch/sparc/kernel/sun4d_irq.c unsigned int idx, mask; mask 119 arch/sparc/kernel/sun4d_irq.c mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil); mask 120 arch/sparc/kernel/sun4d_irq.c mask &= (0xf << sbil); mask 124 arch/sparc/kernel/sun4d_irq.c for (idx = 0; mask != 0; idx++, slot <<= 1) { mask 128 arch/sparc/kernel/sun4d_irq.c if (!(mask & slot)) mask 131 arch/sparc/kernel/sun4d_irq.c mask &= ~slot; mask 493 arch/sparc/kernel/sun4d_irq.c unsigned int mask; mask 499 arch/sparc/kernel/sun4d_irq.c mask = acquire_sbi(devid, 0xffffffff); mask 500 arch/sparc/kernel/sun4d_irq.c if (mask) { mask 502 arch/sparc/kernel/sun4d_irq.c mask, board); mask 503 arch/sparc/kernel/sun4d_irq.c release_sbi(devid, mask); mask 284 arch/sparc/kernel/sun4d_smp.c static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, mask 318 arch/sparc/kernel/sun4d_smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 319 arch/sparc/kernel/sun4d_smp.c cpumask_and(&mask, cpu_online_mask, &mask); mask 321 arch/sparc/kernel/sun4d_smp.c if (cpumask_test_cpu(i, &mask)) { mask 334 arch/sparc/kernel/sun4d_smp.c if (!cpumask_test_cpu(i, &mask)) mask 342 arch/sparc/kernel/sun4d_smp.c if (!cpumask_test_cpu(i, &mask)) mask 109 arch/sparc/kernel/sun4m_irq.c long mask; mask 197 arch/sparc/kernel/sun4m_irq.c if (handler_data->mask) { mask 202 arch/sparc/kernel/sun4m_irq.c sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set); mask 204 arch/sparc/kernel/sun4m_irq.c sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set); mask 216 arch/sparc/kernel/sun4m_irq.c if (handler_data->mask) { mask 221 arch/sparc/kernel/sun4m_irq.c sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear); mask 223 arch/sparc/kernel/sun4m_irq.c sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear); mask 278 arch/sparc/kernel/sun4m_irq.c handler_data->mask = sun4m_imask[real_irq]; mask 173 arch/sparc/kernel/sun4m_smp.c static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, mask 194 arch/sparc/kernel/sun4m_smp.c cpumask_clear_cpu(smp_processor_id(), &mask); mask 195 arch/sparc/kernel/sun4m_smp.c cpumask_and(&mask, cpu_online_mask, &mask); mask 197 arch/sparc/kernel/sun4m_smp.c if (cpumask_test_cpu(i, &mask)) { mask 213 arch/sparc/kernel/sun4m_smp.c if (!cpumask_test_cpu(i, &mask)) mask 221 arch/sparc/kernel/sun4m_smp.c if (!cpumask_test_cpu(i, &mask)) mask 175 arch/sparc/kernel/time_32.c .mask = CLOCKSOURCE_MASK(64), mask 773 arch/sparc/kernel/time_64.c .mask = CLOCKSOURCE_MASK(64), mask 657 arch/sparc/kernel/traps_64.c unsigned long mask; mask 1152 arch/sparc/kernel/traps_64.c for (i = 0; cheetah_error_table[i].mask; i++) { mask 1153 arch/sparc/kernel/traps_64.c if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL) mask 1163 arch/sparc/kernel/traps_64.c for (i = 0; cheetah_error_table[i].mask; i++) { mask 1164 arch/sparc/kernel/traps_64.c if ((bit & cheetah_error_table[i].mask) != 0UL) mask 35 arch/sparc/kernel/vdso.c vdata->clock.mask = tk->tkr_mono.mask; mask 123 arch/sparc/lib/atomic32.c unsigned long ___set_bit(unsigned long *addr, unsigned long mask) mask 129 arch/sparc/lib/atomic32.c *addr = old | mask; mask 132 arch/sparc/lib/atomic32.c return old & mask; mask 136 arch/sparc/lib/atomic32.c unsigned long ___clear_bit(unsigned long *addr, unsigned long mask) mask 142 arch/sparc/lib/atomic32.c *addr = old & ~mask; mask 145 arch/sparc/lib/atomic32.c return old & mask; mask 149 arch/sparc/lib/atomic32.c unsigned long ___change_bit(unsigned long *addr, unsigned long mask) mask 155 arch/sparc/lib/atomic32.c *addr = old ^ mask; mask 158 arch/sparc/lib/atomic32.c return old & mask; mask 226 arch/sparc/mm/init_64.c unsigned long mask = this_cpu; mask 230 arch/sparc/mm/init_64.c mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); mask 241 arch/sparc/mm/init_64.c : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) mask 247 arch/sparc/mm/init_64.c unsigned long mask = (1UL << PG_dcache_dirty); mask 263 arch/sparc/mm/init_64.c : "r" (cpu), "r" (mask), "r" (&page->flags), mask 447 arch/sparc/mm/init_64.c unsigned long mask = 0x1ffc00000UL; mask 452 arch/sparc/mm/init_64.c pte_val(pte) &= ~mask; mask 453 arch/sparc/mm/init_64.c pte_val(pte) |= (address & mask); mask 527 arch/sparc/mm/init_64.c unsigned long paddr, mask = _PAGE_PADDR_4U; mask 530 arch/sparc/mm/init_64.c paddr = kaddr & mask; mask 537 arch/sparc/mm/init_64.c paddr = pte_val(*ptep) & mask; mask 929 arch/sparc/mm/init_64.c unsigned long mask; mask 941 arch/sparc/mm/init_64.c u64 mask; mask 984 arch/sparc/mm/init_64.c if ((start & p->mask) == p->match) { mask 1032 arch/sparc/mm/init_64.c if ((pa_start & m->mask) == m->match) { mask 1034 arch/sparc/mm/init_64.c m_mask = m->mask; mask 1049 arch/sparc/mm/init_64.c if ((pa_start & m->mask) == m->match) { mask 1051 arch/sparc/mm/init_64.c m_mask = m->mask; mask 1118 arch/sparc/mm/init_64.c node_masks[0].mask = 0; mask 1286 arch/sparc/mm/init_64.c m->mask = *val; mask 1290 arch/sparc/mm/init_64.c count - 1, m->node, m->latency, m->match, m->mask); mask 1343 arch/sparc/mm/init_64.c u64 grp, cpumask_t *mask) mask 1347 arch/sparc/mm/init_64.c cpumask_clear(mask); mask 1358 arch/sparc/mm/init_64.c cpumask_set_cpu(*id, mask); mask 1392 arch/sparc/mm/init_64.c if ((grp->mask == n->mask) && (grp->match == n->match)) mask 1446 arch/sparc/mm/init_64.c n->mask = candidate->mask; mask 1450 arch/sparc/mm/init_64.c index, n->mask, n->match, candidate->latency); mask 1458 arch/sparc/mm/init_64.c cpumask_t mask; mask 1461 arch/sparc/mm/init_64.c numa_parse_mdesc_group_cpus(md, grp, &mask); mask 1463 arch/sparc/mm/init_64.c for_each_cpu(cpu, &mask) mask 1465 arch/sparc/mm/init_64.c cpumask_copy(&numa_cpumask_lookup_table[index], &mask); mask 1469 arch/sparc/mm/init_64.c for_each_cpu(cpu, &mask) mask 1546 arch/sparc/mm/init_64.c node_masks[index].mask = ~((1UL << 36UL) - 1UL); mask 132 arch/sparc/vdso/vclock_gettime.c v = (cycles - vvar->clock.cycle_last) & vvar->clock.mask; mask 142 arch/sparc/vdso/vclock_gettime.c v = (cycles - vvar->clock.cycle_last) & vvar->clock.mask; mask 125 arch/um/drivers/hostaudio_kern.c __poll_t mask = 0; mask 131 arch/um/drivers/hostaudio_kern.c return mask; mask 47 arch/um/include/asm/thread_info.h unsigned long mask = THREAD_SIZE - 1; mask 51 arch/um/include/asm/thread_info.h ti = (struct thread_info *) (((unsigned long)p) & ~mask); mask 10 arch/um/include/shared/frame_kern.h struct pt_regs *regs, sigset_t *mask); mask 12 arch/um/include/shared/frame_kern.h struct pt_regs *regs, sigset_t *mask); mask 541 arch/um/kernel/irq.c unsigned long mask, old; mask 544 arch/um/kernel/irq.c mask = xchg(&pending_mask, *mask_out); mask 545 arch/um/kernel/irq.c if (mask != 0) { mask 557 arch/um/kernel/irq.c old |= mask; mask 558 arch/um/kernel/irq.c mask = xchg(&pending_mask, old); mask 559 arch/um/kernel/irq.c } while (mask != old); mask 577 arch/um/kernel/irq.c mask = xchg(&pending_mask, 0); mask 578 arch/um/kernel/irq.c *mask_out |= mask | nested; mask 585 arch/um/kernel/irq.c unsigned long mask; mask 596 arch/um/kernel/irq.c mask = xchg(&pending_mask, 0); mask 597 arch/um/kernel/irq.c return mask & ~1; mask 158 arch/um/kernel/time.c .mask = CLOCKSOURCE_MASK(64), mask 41 arch/unicore32/include/asm/hwdef-copro.h extern void adjust_cr(unsigned long mask, unsigned long set); mask 241 arch/unicore32/include/asm/pgtable.h const unsigned long mask = PTE_EXEC | PTE_WRITE | PTE_READ; mask 242 arch/unicore32/include/asm/pgtable.h pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); mask 42 arch/unicore32/kernel/irq.c unsigned int mask; mask 45 arch/unicore32/kernel/irq.c mask = 1 << d->irq; mask 47 arch/unicore32/kernel/irq.c mask = GPIO_MASK(d->irq); mask 50 arch/unicore32/kernel/irq.c if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) mask 56 arch/unicore32/kernel/irq.c GPIO_IRQ_rising_edge |= mask; mask 58 arch/unicore32/kernel/irq.c GPIO_IRQ_rising_edge &= ~mask; mask 60 arch/unicore32/kernel/irq.c GPIO_IRQ_falling_edge |= mask; mask 62 arch/unicore32/kernel/irq.c GPIO_IRQ_falling_edge &= ~mask; mask 113 arch/unicore32/kernel/irq.c unsigned int mask, irq; mask 115 arch/unicore32/kernel/irq.c mask = readl(GPIO_GEDR); mask 121 arch/unicore32/kernel/irq.c writel(mask, GPIO_GEDR); mask 125 arch/unicore32/kernel/irq.c if (mask & 1) mask 127 arch/unicore32/kernel/irq.c mask >>= 1; mask 129 arch/unicore32/kernel/irq.c } while (mask); mask 130 arch/unicore32/kernel/irq.c mask = readl(GPIO_GEDR); mask 131 arch/unicore32/kernel/irq.c } while (mask); mask 141 arch/unicore32/kernel/irq.c unsigned int mask = GPIO_MASK(d->irq); mask 143 arch/unicore32/kernel/irq.c writel(mask, GPIO_GEDR); mask 148 arch/unicore32/kernel/irq.c unsigned int mask = GPIO_MASK(d->irq); mask 150 arch/unicore32/kernel/irq.c GPIO_IRQ_mask &= ~mask; mask 152 arch/unicore32/kernel/irq.c writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); mask 153 arch/unicore32/kernel/irq.c writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); mask 158 arch/unicore32/kernel/irq.c unsigned int mask = GPIO_MASK(d->irq); mask 160 arch/unicore32/kernel/irq.c GPIO_IRQ_mask |= mask; mask 344 arch/unicore32/kernel/pci.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 354 arch/unicore32/kernel/pci.c if (!(mask & (1 << idx))) mask 71 arch/unicore32/kernel/time.c .mask = CLOCKSOURCE_MASK(32), mask 152 arch/unicore32/mm/fault.c unsigned int mask = VM_READ | VM_WRITE | VM_EXEC; mask 155 arch/unicore32/mm/fault.c mask = VM_WRITE; mask 157 arch/unicore32/mm/fault.c mask = VM_EXEC; mask 159 arch/unicore32/mm/fault.c return vma->vm_flags & mask ? false : true; mask 57 arch/unicore32/mm/mmu.c void adjust_cr(unsigned long mask, unsigned long set) mask 61 arch/unicore32/mm/mmu.c mask &= ~CR_A; mask 63 arch/unicore32/mm/mmu.c set &= mask; mask 67 arch/unicore32/mm/mmu.c cr_no_alignment = (cr_no_alignment & ~mask) | set; mask 68 arch/unicore32/mm/mmu.c cr_alignment = (cr_alignment & ~mask) | set; mask 70 arch/unicore32/mm/mmu.c set_cr((get_cr() & ~mask) | set); mask 47 arch/x86/boot/cpuflags.c int has_eflag(unsigned long mask) mask 62 arch/x86/boot/cpuflags.c : "ri" (mask)); mask 64 arch/x86/boot/cpuflags.c return !!((f0^f1) & mask); mask 18 arch/x86/boot/cpuflags.h int has_eflag(unsigned long mask); mask 2135 arch/x86/events/intel/core.c u64 ctrl_val, mask; mask 2137 arch/x86/events/intel/core.c mask = 0xfULL << (idx * 4); mask 2140 arch/x86/events/intel/core.c ctrl_val &= ~mask; mask 2197 arch/x86/events/intel/core.c u64 ctrl_val, mask, bits = 0; mask 2218 arch/x86/events/intel/core.c mask = 0xfULL << (idx * 4); mask 2222 arch/x86/events/intel/core.c mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4); mask 2226 arch/x86/events/intel/core.c ctrl_val &= ~mask; mask 4070 arch/x86/events/intel/core.c static bool check_msr(unsigned long msr, u64 mask) mask 4092 arch/x86/events/intel/core.c val_tmp = val_old ^ mask; mask 1838 arch/x86/events/intel/ds.c u64 mask; mask 1848 arch/x86/events/intel/ds.c mask = (1ULL << x86_pmu.max_pebs_events) - 1; mask 1851 arch/x86/events/intel/ds.c mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; mask 1865 arch/x86/events/intel/ds.c pebs_status &= mask; mask 1916 arch/x86/events/intel/ds.c for_each_set_bit(bit, (unsigned long *)&mask, size) { mask 1951 arch/x86/events/intel/ds.c u64 mask; mask 1961 arch/x86/events/intel/ds.c mask = ((1ULL << x86_pmu.max_pebs_events) - 1) | mask 1974 arch/x86/events/intel/ds.c pebs_status &= mask; mask 1980 arch/x86/events/intel/ds.c for_each_set_bit(bit, (unsigned long *)&mask, size) { mask 344 arch/x86/events/intel/lbr.c unsigned lbr_idx, mask; mask 366 arch/x86/events/intel/lbr.c mask = x86_pmu.lbr_nr - 1; mask 368 arch/x86/events/intel/lbr.c lbr_idx = (tos - i) & mask; mask 377 arch/x86/events/intel/lbr.c lbr_idx = (tos - i) & mask; mask 391 arch/x86/events/intel/lbr.c unsigned lbr_idx, mask; mask 400 arch/x86/events/intel/lbr.c mask = x86_pmu.lbr_nr - 1; mask 403 arch/x86/events/intel/lbr.c lbr_idx = (tos - i) & mask; mask 538 arch/x86/events/intel/lbr.c unsigned long mask = x86_pmu.lbr_nr - 1; mask 543 arch/x86/events/intel/lbr.c unsigned long lbr_idx = (tos - i) & mask; mask 575 arch/x86/events/intel/lbr.c unsigned long mask = x86_pmu.lbr_nr - 1; mask 589 arch/x86/events/intel/lbr.c unsigned long lbr_idx = (tos - i) & mask; mask 691 arch/x86/events/intel/lbr.c int mask = 0; mask 694 arch/x86/events/intel/lbr.c mask |= X86_BR_USER; mask 697 arch/x86/events/intel/lbr.c mask |= X86_BR_KERNEL; mask 702 arch/x86/events/intel/lbr.c mask |= X86_BR_ANY; mask 705 arch/x86/events/intel/lbr.c mask |= X86_BR_ANY_CALL; mask 708 arch/x86/events/intel/lbr.c mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; mask 711 arch/x86/events/intel/lbr.c mask |= X86_BR_IND_CALL; mask 714 arch/x86/events/intel/lbr.c mask |= X86_BR_ABORT; mask 717 arch/x86/events/intel/lbr.c mask |= X86_BR_IN_TX; mask 720 arch/x86/events/intel/lbr.c mask |= X86_BR_NO_TX; mask 723 arch/x86/events/intel/lbr.c mask |= X86_BR_JCC; mask 728 arch/x86/events/intel/lbr.c if (mask & ~(X86_BR_USER | X86_BR_KERNEL)) mask 730 arch/x86/events/intel/lbr.c mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET | mask 735 arch/x86/events/intel/lbr.c mask |= X86_BR_IND_JMP; mask 738 arch/x86/events/intel/lbr.c mask |= X86_BR_CALL | X86_BR_ZERO_CALL; mask 741 arch/x86/events/intel/lbr.c mask |= X86_BR_TYPE_SAVE; mask 747 arch/x86/events/intel/lbr.c event->hw.branch_reg.reg = mask; mask 760 arch/x86/events/intel/lbr.c u64 mask = 0, v; mask 772 arch/x86/events/intel/lbr.c mask |= v; mask 785 arch/x86/events/intel/lbr.c reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK); mask 45 arch/x86/events/intel/pt.c .reg = _r, .mask = _m } mask 51 arch/x86/events/intel/pt.c u32 mask; mask 75 arch/x86/events/intel/pt.c unsigned int shift = __ffs(cd->mask); mask 77 arch/x86/events/intel/pt.c return (c & cd->mask) >> shift; mask 198 arch/x86/events/intel/uncore_nhmex.c DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63"); mask 558 arch/x86/events/intel/uncore_nhmex.c u64 mask; mask 583 arch/x86/events/intel/uncore_nhmex.c mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK; mask 585 arch/x86/events/intel/uncore_nhmex.c mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK; mask 592 arch/x86/events/intel/uncore_nhmex.c mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx); mask 594 arch/x86/events/intel/uncore_nhmex.c mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx); mask 597 arch/x86/events/intel/uncore_nhmex.c if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) { mask 600 arch/x86/events/intel/uncore_nhmex.c mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK | mask 603 arch/x86/events/intel/uncore_nhmex.c mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK | mask 605 arch/x86/events/intel/uncore_nhmex.c er->config &= ~mask; mask 606 arch/x86/events/intel/uncore_nhmex.c er->config |= (config & mask); mask 1014 arch/x86/events/intel/uncore_nhmex.c u64 mask = 0xff << ((idx - 2) * 8); mask 1016 arch/x86/events/intel/uncore_nhmex.c !((er->config ^ config1) & mask)) { mask 1018 arch/x86/events/intel/uncore_nhmex.c er->config &= ~mask; mask 1019 arch/x86/events/intel/uncore_nhmex.c er->config |= config1 & mask; mask 865 arch/x86/events/intel/uncore_snbep.c u64 mask; mask 877 arch/x86/events/intel/uncore_snbep.c mask = cbox_filter_mask(0x1 << i); mask 879 arch/x86/events/intel/uncore_snbep.c !((reg1->config ^ er->config) & mask)) { mask 881 arch/x86/events/intel/uncore_snbep.c er->config &= ~mask; mask 882 arch/x86/events/intel/uncore_snbep.c er->config |= reg1->config & mask; mask 906 arch/x86/events/intel/uncore_snbep.c u64 mask = 0; mask 909 arch/x86/events/intel/uncore_snbep.c mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID; mask 911 arch/x86/events/intel/uncore_snbep.c mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID; mask 913 arch/x86/events/intel/uncore_snbep.c mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE; mask 915 arch/x86/events/intel/uncore_snbep.c mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC; mask 917 arch/x86/events/intel/uncore_snbep.c return mask; mask 996 arch/x86/events/intel/uncore_snbep.c u64 mask, config1 = reg1->config; mask 1003 arch/x86/events/intel/uncore_snbep.c mask = 0xffULL << (idx * 8); mask 1006 arch/x86/events/intel/uncore_snbep.c !((config1 ^ er->config) & mask)) { mask 1008 arch/x86/events/intel/uncore_snbep.c er->config &= ~mask; mask 1009 arch/x86/events/intel/uncore_snbep.c er->config |= config1 & mask; mask 1584 arch/x86/events/intel/uncore_snbep.c u64 mask = 0; mask 1587 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_TID; mask 1589 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK; mask 1591 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE; mask 1593 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NID; mask 1595 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC; mask 1596 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_NC; mask 1597 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_C6; mask 1598 arch/x86/events/intel/uncore_snbep.c mask |= IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC; mask 1601 arch/x86/events/intel/uncore_snbep.c return mask; mask 2020 arch/x86/events/intel/uncore_snbep.c u64 mask = 0; mask 2023 arch/x86/events/intel/uncore_snbep.c mask |= KNL_CHA_MSR_PMON_BOX_FILTER_TID; mask 2025 arch/x86/events/intel/uncore_snbep.c mask |= KNL_CHA_MSR_PMON_BOX_FILTER_STATE; mask 2027 arch/x86/events/intel/uncore_snbep.c mask |= KNL_CHA_MSR_PMON_BOX_FILTER_OP; mask 2028 arch/x86/events/intel/uncore_snbep.c return mask; mask 2569 arch/x86/events/intel/uncore_snbep.c u64 mask = 0; mask 2571 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID; mask 2573 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK; mask 2575 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE; mask 2577 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID; mask 2579 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC; mask 2580 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC; mask 2581 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6; mask 2582 arch/x86/events/intel/uncore_snbep.c mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC; mask 2584 arch/x86/events/intel/uncore_snbep.c return mask; mask 3458 arch/x86/events/intel/uncore_snbep.c u64 mask = 0; mask 3461 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_TID; mask 3463 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK; mask 3465 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE; mask 3467 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM; mask 3468 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC; mask 3469 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC; mask 3470 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM; mask 3471 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM; mask 3472 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0; mask 3473 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1; mask 3474 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC; mask 3475 arch/x86/events/intel/uncore_snbep.c mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC; mask 3477 arch/x86/events/intel/uncore_snbep.c return mask; mask 100 arch/x86/hyperv/hv_apic.c static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector) mask 122 arch/x86/hyperv/hv_apic.c if (!cpumask_equal(mask, cpu_present_mask)) { mask 124 arch/x86/hyperv/hv_apic.c nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask); mask 139 arch/x86/hyperv/hv_apic.c static bool __send_ipi_mask(const struct cpumask *mask, int vector) mask 145 arch/x86/hyperv/hv_apic.c trace_hyperv_send_ipi_mask(mask, vector); mask 147 arch/x86/hyperv/hv_apic.c if (cpumask_empty(mask)) mask 166 arch/x86/hyperv/hv_apic.c if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64) mask 172 arch/x86/hyperv/hv_apic.c for_each_cpu(cur_cpu, mask) { mask 192 arch/x86/hyperv/hv_apic.c return __send_ipi_mask_ex(mask, vector); mask 197 arch/x86/hyperv/hv_apic.c struct cpumask mask = CPU_MASK_NONE; mask 199 arch/x86/hyperv/hv_apic.c cpumask_set_cpu(cpu, &mask); mask 200 arch/x86/hyperv/hv_apic.c return __send_ipi_mask(&mask, vector); mask 209 arch/x86/hyperv/hv_apic.c static void hv_send_ipi_mask(const struct cpumask *mask, int vector) mask 211 arch/x86/hyperv/hv_apic.c if (!__send_ipi_mask(mask, vector)) mask 212 arch/x86/hyperv/hv_apic.c orig_apic.send_IPI_mask(mask, vector); mask 215 arch/x86/hyperv/hv_apic.c static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) mask 221 arch/x86/hyperv/hv_apic.c cpumask_copy(&new_mask, mask); mask 225 arch/x86/hyperv/hv_apic.c orig_apic.send_IPI_mask_allbutself(mask, vector); mask 182 arch/x86/ia32/ia32_signal.c struct pt_regs *regs, unsigned int mask) mask 211 arch/x86/ia32/ia32_signal.c put_user_ex(mask, &sc->oldmask); mask 32 arch/x86/include/asm/apb_timer.h extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu); mask 174 arch/x86/include/asm/apic.h extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); mask 302 arch/x86/include/asm/apic.h void (*send_IPI_mask)(const struct cpumask *mask, int vector); mask 334 arch/x86/include/asm/apicdef.h mask : 1, mask 346 arch/x86/include/asm/apicdef.h mask : 1, mask 357 arch/x86/include/asm/apicdef.h mask : 1, mask 370 arch/x86/include/asm/apicdef.h mask : 1, mask 383 arch/x86/include/asm/apicdef.h mask : 1, mask 393 arch/x86/include/asm/apicdef.h mask : 1, mask 39 arch/x86/include/asm/barrier.h unsigned long mask; mask 42 arch/x86/include/asm/barrier.h :"=r" (mask) mask 45 arch/x86/include/asm/barrier.h return mask; mask 117 arch/x86/include/asm/debugreg.h extern void set_dr_addr_mask(unsigned long mask, int dr); mask 119 arch/x86/include/asm/debugreg.h static inline void set_dr_addr_mask(unsigned long mask, int dr) { } mask 378 arch/x86/include/asm/elf.h unsigned long mask; mask 276 arch/x86/include/asm/fpu/internal.h u64 mask = -1; mask 277 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 278 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 298 arch/x86/include/asm/fpu/internal.h u64 mask = -1; mask 299 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 300 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 322 arch/x86/include/asm/fpu/internal.h u64 mask = -1; mask 323 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 324 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 338 arch/x86/include/asm/fpu/internal.h static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) mask 340 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 341 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 378 arch/x86/include/asm/fpu/internal.h static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) mask 381 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 382 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 396 arch/x86/include/asm/fpu/internal.h static inline int copy_kernel_to_xregs_err(struct xregs_state *xstate, u64 mask) mask 398 arch/x86/include/asm/fpu/internal.h u32 lmask = mask; mask 399 arch/x86/include/asm/fpu/internal.h u32 hmask = mask >> 32; mask 445 arch/x86/include/asm/fpu/internal.h static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask) mask 448 arch/x86/include/asm/fpu/internal.h copy_kernel_to_xregs(&fpstate->xsave, mask); mask 16 arch/x86/include/asm/hw_breakpoint.h unsigned long mask; mask 70 arch/x86/include/asm/hw_irq.h const struct cpumask *mask; /* CPU mask for vector allocation */ mask 60 arch/x86/include/asm/i8259.h void (*mask)(unsigned int irq); mask 43 arch/x86/include/asm/intel_pmc_ipc.h int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); mask 84 arch/x86/include/asm/intel_pmc_ipc.h static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) mask 47 arch/x86/include/asm/intel_scu_ipc.h int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask); mask 78 arch/x86/include/asm/io_apic.h mask : 1, /* 0: enabled, 1: disabled */ mask 93 arch/x86/include/asm/io_apic.h mask : 1, mask 96 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask); mask 215 arch/x86/include/asm/iosf_mbi.h int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) mask 46 arch/x86/include/asm/irq.h void arch_trigger_cpumask_backtrace(const struct cpumask *mask, mask 18 arch/x86/include/asm/irqdomain.h const struct cpumask *mask); mask 488 arch/x86/include/asm/kvm_host.h u64 mask; mask 1079 arch/x86/include/asm/kvm_host.h void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); mask 1162 arch/x86/include/asm/kvm_host.h gfn_t offset, unsigned long mask); mask 1278 arch/x86/include/asm/kvm_host.h gfn_t gfn_offset, unsigned long mask); mask 1301 arch/x86/include/asm/kvm_host.h bool mask); mask 1572 arch/x86/include/asm/kvm_host.h int kvm_set_shared_msr(unsigned index, u64 val, u64 mask); mask 94 arch/x86/include/asm/mpspec.h unsigned long mask[PHYSID_ARRAY_SIZE]; mask 99 arch/x86/include/asm/mpspec.h #define physid_set(physid, map) set_bit(physid, (map).mask) mask 100 arch/x86/include/asm/mpspec.h #define physid_clear(physid, map) clear_bit(physid, (map).mask) mask 101 arch/x86/include/asm/mpspec.h #define physid_isset(physid, map) test_bit(physid, (map).mask) mask 103 arch/x86/include/asm/mpspec.h test_and_set_bit(physid, (map).mask) mask 106 arch/x86/include/asm/mpspec.h bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) mask 109 arch/x86/include/asm/mpspec.h bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC) mask 112 arch/x86/include/asm/mpspec.h bitmap_zero((map).mask, MAX_LOCAL_APIC) mask 115 arch/x86/include/asm/mpspec.h bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC) mask 118 arch/x86/include/asm/mpspec.h bitmap_empty((map).mask, MAX_LOCAL_APIC) mask 121 arch/x86/include/asm/mpspec.h bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC) mask 124 arch/x86/include/asm/mpspec.h bitmap_weight((map).mask, MAX_LOCAL_APIC) mask 127 arch/x86/include/asm/mpspec.h bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC) mask 130 arch/x86/include/asm/mpspec.h bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC) mask 134 arch/x86/include/asm/mpspec.h return map->mask[0]; mask 140 arch/x86/include/asm/mpspec.h map->mask[0] = physids; mask 343 arch/x86/include/asm/msr.h void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); mask 344 arch/x86/include/asm/msr.h void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); mask 297 arch/x86/include/asm/paravirt.h static inline void set_iopl_mask(unsigned mask) mask 299 arch/x86/include/asm/paravirt.h PVOP_VCALL1(cpu.set_iopl_mask, mask); mask 811 arch/x86/include/asm/paravirt.h #define COND_PUSH(set, mask, reg) \ mask 812 arch/x86/include/asm/paravirt.h .if ((~(set)) & mask); push %reg; .endif mask 813 arch/x86/include/asm/paravirt.h #define COND_POP(set, mask, reg) \ mask 814 arch/x86/include/asm/paravirt.h .if ((~(set)) & mask); pop %reg; .endif mask 143 arch/x86/include/asm/paravirt_types.h void (*set_iopl_mask)(unsigned mask); mask 803 arch/x86/include/asm/perf_event_p4.h #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask)) mask 78 arch/x86/include/asm/pgtable-2level.h unsigned long mask, unsigned int leftshift) mask 80 arch/x86/include/asm/pgtable-2level.h return ((value >> rightshift) & mask) << leftshift; mask 105 arch/x86/include/asm/pgtable-2level.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask) mask 27 arch/x86/include/asm/pgtable-invert.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask) mask 35 arch/x86/include/asm/pgtable-invert.h val = (val & ~mask) | (~val & mask); mask 602 arch/x86/include/asm/pgtable.h static inline u64 flip_protnone_guard(u64 oldval, u64 val, u64 mask); mask 521 arch/x86/include/asm/processor.h static inline void native_set_iopl_mask(unsigned mask) mask 533 arch/x86/include/asm/processor.h : "i" (~X86_EFLAGS_IOPL), "r" (mask)); mask 18 arch/x86/include/asm/sighandling.h struct pt_regs *regs, unsigned long mask); mask 60 arch/x86/include/asm/smp.h void (*send_call_func_ipi)(const struct cpumask *mask); mask 125 arch/x86/include/asm/smp.h static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 127 arch/x86/include/asm/smp.h smp_ops.send_call_func_ipi(mask); mask 147 arch/x86/include/asm/smp.h void native_send_call_func_ipi(const struct cpumask *mask); mask 293 arch/x86/include/asm/tlbflush.h static inline void cr4_set_bits_irqsoff(unsigned long mask) mask 298 arch/x86/include/asm/tlbflush.h if ((cr4 | mask) != cr4) mask 299 arch/x86/include/asm/tlbflush.h __cr4_set(cr4 | mask); mask 303 arch/x86/include/asm/tlbflush.h static inline void cr4_clear_bits_irqsoff(unsigned long mask) mask 308 arch/x86/include/asm/tlbflush.h if ((cr4 & ~mask) != cr4) mask 309 arch/x86/include/asm/tlbflush.h __cr4_set(cr4 & ~mask); mask 313 arch/x86/include/asm/tlbflush.h static inline void cr4_set_bits(unsigned long mask) mask 318 arch/x86/include/asm/tlbflush.h cr4_set_bits_irqsoff(mask); mask 323 arch/x86/include/asm/tlbflush.h static inline void cr4_clear_bits(unsigned long mask) mask 328 arch/x86/include/asm/tlbflush.h cr4_clear_bits_irqsoff(mask); mask 332 arch/x86/include/asm/tlbflush.h static inline void cr4_toggle_bits_irqsoff(unsigned long mask) mask 337 arch/x86/include/asm/tlbflush.h __cr4_set(cr4 ^ mask); mask 363 arch/x86/include/asm/tlbflush.h static inline void cr4_set_bits_and_update_boot(unsigned long mask) mask 365 arch/x86/include/asm/tlbflush.h mmu_cr4_features |= mask; mask 368 arch/x86/include/asm/tlbflush.h cr4_set_bits(mask); mask 612 arch/x86/include/asm/tlbflush.h #define flush_tlb_others(mask, info) \ mask 613 arch/x86/include/asm/tlbflush.h native_flush_tlb_others(mask, info) mask 685 arch/x86/include/asm/uaccess.h int mask; mask 23 arch/x86/include/asm/uv/uv_irq.h mask : 1, mask 287 arch/x86/include/asm/vdso/gettimeofday.h u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) mask 28 arch/x86/include/asm/word-at-a-time.h static inline long count_masked_bytes(unsigned long mask) mask 30 arch/x86/include/asm/word-at-a-time.h return mask*0x0001020304050608ul >> 56; mask 36 arch/x86/include/asm/word-at-a-time.h static inline long count_masked_bytes(long mask) mask 39 arch/x86/include/asm/word-at-a-time.h long a = (0x0ff0001+mask) >> 23; mask 41 arch/x86/include/asm/word-at-a-time.h return a & mask; mask 49 arch/x86/include/asm/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 50 arch/x86/include/asm/word-at-a-time.h *bits = mask; mask 51 arch/x86/include/asm/word-at-a-time.h return mask; mask 66 arch/x86/include/asm/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 68 arch/x86/include/asm/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 70 arch/x86/include/asm/word-at-a-time.h return count_masked_bytes(mask); mask 65 arch/x86/include/asm/xen/hypervisor.h extern void xen_set_iopl_mask(unsigned mask); mask 100 arch/x86/include/uapi/asm/kvm.h __u8 mask:1; mask 570 arch/x86/kernel/acpi/boot.c unsigned int mask = 1 << irq; mask 589 arch/x86/kernel/acpi/boot.c new &= ~mask; mask 592 arch/x86/kernel/acpi/boot.c new |= mask; mask 23 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, mask 26 arch/x86/kernel/acpi/cppc_msr.c *val &= mask; mask 39 arch/x86/kernel/acpi/cppc_msr.c u64 mask = GENMASK_ULL(reg->bit_offset + reg->bit_width - 1, mask 43 arch/x86/kernel/acpi/cppc_msr.c val &= mask; mask 44 arch/x86/kernel/acpi/cppc_msr.c rd_val &= ~mask; mask 382 arch/x86/kernel/amd_nb.c unsigned int mask; mask 387 arch/x86/kernel/amd_nb.c pci_read_config_dword(link, 0x1d4, &mask); mask 389 arch/x86/kernel/amd_nb.c return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf; mask 392 arch/x86/kernel/amd_nb.c int amd_set_subcaches(int cpu, unsigned long mask) mask 399 arch/x86/kernel/amd_nb.c if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf) mask 410 arch/x86/kernel/amd_nb.c if (mask != 0xf) { mask 416 arch/x86/kernel/amd_nb.c mask <<= 4 * cuid; mask 417 arch/x86/kernel/amd_nb.c mask |= (0xf ^ (1 << cuid)) << 26; mask 419 arch/x86/kernel/amd_nb.c pci_write_config_dword(nb->link, 0x1d4, mask); mask 429 arch/x86/kernel/apic/apic.c int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) mask 434 arch/x86/kernel/apic/apic.c new = (mask << 16) | (msg_type << 8) | vector; mask 519 arch/x86/kernel/apic/apic.c static void lapic_timer_broadcast(const struct cpumask *mask) mask 522 arch/x86/kernel/apic/apic.c apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); mask 2358 arch/x86/kernel/apic/apic.c u32 mask; mask 2363 arch/x86/kernel/apic/apic.c mask = (1U << (fls(smp_num_siblings) - 1)) - 1; mask 2364 arch/x86/kernel/apic/apic.c return !(apicid & mask); mask 51 arch/x86/kernel/apic/apic_flat_64.c static void _flat_send_IPI_mask(unsigned long mask, int vector) mask 56 arch/x86/kernel/apic/apic_flat_64.c __default_send_IPI_dest_field(mask, vector, apic->dest_logical); mask 62 arch/x86/kernel/apic/apic_flat_64.c unsigned long mask = cpumask_bits(cpumask)[0]; mask 64 arch/x86/kernel/apic/apic_flat_64.c _flat_send_IPI_mask(mask, vector); mask 70 arch/x86/kernel/apic/apic_flat_64.c unsigned long mask = cpumask_bits(cpumask)[0]; mask 74 arch/x86/kernel/apic/apic_flat_64.c __clear_bit(cpu, &mask); mask 76 arch/x86/kernel/apic/apic_flat_64.c _flat_send_IPI_mask(mask, vector); mask 119 arch/x86/kernel/apic/apic_numachip.c static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) mask 123 arch/x86/kernel/apic/apic_numachip.c for_each_cpu(cpu, mask) mask 127 arch/x86/kernel/apic/apic_numachip.c static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, mask 133 arch/x86/kernel/apic/apic_numachip.c for_each_cpu(cpu, mask) { mask 31 arch/x86/kernel/apic/hw_nmi.c static void nmi_raise_cpu_backtrace(cpumask_t *mask) mask 33 arch/x86/kernel/apic/hw_nmi.c apic->send_IPI_mask(mask, NMI_VECTOR); mask 36 arch/x86/kernel/apic/hw_nmi.c void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) mask 38 arch/x86/kernel/apic/hw_nmi.c nmi_trigger_cpumask_backtrace(mask, exclude_self, mask 361 arch/x86/kernel/apic/io_apic.c union entry_union eu = { .entry.mask = IOAPIC_MASKED }; mask 522 arch/x86/kernel/apic/io_apic.c entry1.mask = IOAPIC_MASKED; mask 558 arch/x86/kernel/apic/io_apic.c if (entry.mask == IOAPIC_UNMASKED) { mask 559 arch/x86/kernel/apic/io_apic.c entry.mask = IOAPIC_MASKED; mask 675 arch/x86/kernel/apic/io_apic.c if (entry.mask == IOAPIC_UNMASKED) { mask 676 arch/x86/kernel/apic/io_apic.c entry.mask = IOAPIC_MASKED; mask 1246 arch/x86/kernel/apic/io_apic.c entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ", mask 1384 arch/x86/kernel/apic/io_apic.c if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { mask 1428 arch/x86/kernel/apic/io_apic.c entry.mask = IOAPIC_UNMASKED; mask 1692 arch/x86/kernel/apic/io_apic.c legacy_pic->mask(irq); mask 1885 arch/x86/kernel/apic/io_apic.c const struct cpumask *mask, bool force) mask 1891 arch/x86/kernel/apic/io_apic.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 2061 arch/x86/kernel/apic/io_apic.c entry1.mask = IOAPIC_UNMASKED; mask 2144 arch/x86/kernel/apic/io_apic.c legacy_pic->mask(0); mask 2232 arch/x86/kernel/apic/io_apic.c legacy_pic->mask(0); mask 2249 arch/x86/kernel/apic/io_apic.c legacy_pic->mask(0); mask 2969 arch/x86/kernel/apic/io_apic.c entry->mask = IOAPIC_MASKED; mask 2971 arch/x86/kernel/apic/io_apic.c entry->mask = IOAPIC_UNMASKED; mask 3021 arch/x86/kernel/apic/io_apic.c legacy_pic->mask(virq); mask 78 arch/x86/kernel/apic/ipi.c void native_send_call_func_ipi(const struct cpumask *mask) mask 83 arch/x86/kernel/apic/ipi.c if (!cpumask_or_equal(mask, cpumask_of(cpu), cpu_online_mask)) mask 86 arch/x86/kernel/apic/ipi.c if (cpumask_test_cpu(cpu, mask)) mask 94 arch/x86/kernel/apic/ipi.c apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); mask 99 arch/x86/kernel/apic/ipi.c static inline int __prepare_ICR2(unsigned int mask) mask 101 arch/x86/kernel/apic/ipi.c return SET_APIC_DEST_FIELD(mask); mask 145 arch/x86/kernel/apic/ipi.c void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest) mask 160 arch/x86/kernel/apic/ipi.c cfg = __prepare_ICR2(mask); mask 184 arch/x86/kernel/apic/ipi.c void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector) mask 195 arch/x86/kernel/apic/ipi.c for_each_cpu(query_cpu, mask) { mask 202 arch/x86/kernel/apic/ipi.c void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, mask 212 arch/x86/kernel/apic/ipi.c for_each_cpu(query_cpu, mask) { mask 246 arch/x86/kernel/apic/ipi.c void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, mask 259 arch/x86/kernel/apic/ipi.c for_each_cpu(query_cpu, mask) mask 266 arch/x86/kernel/apic/ipi.c void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, mask 276 arch/x86/kernel/apic/ipi.c for_each_cpu(query_cpu, mask) { mask 291 arch/x86/kernel/apic/ipi.c unsigned long mask = cpumask_bits(cpumask)[0]; mask 294 arch/x86/kernel/apic/ipi.c if (!mask) mask 298 arch/x86/kernel/apic/ipi.c WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]); mask 299 arch/x86/kernel/apic/ipi.c __default_send_IPI_dest_field(mask, vector, apic->dest_logical); mask 54 arch/x86/kernel/apic/local.h void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest); mask 58 arch/x86/kernel/apic/local.h void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector); mask 59 arch/x86/kernel/apic/local.h void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, int vector); mask 65 arch/x86/kernel/apic/local.h void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector); mask 66 arch/x86/kernel/apic/local.h void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector); mask 67 arch/x86/kernel/apic/local.h void default_send_IPI_mask_logical(const struct cpumask *mask, int vector); mask 62 arch/x86/kernel/apic/msi.c msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) mask 74 arch/x86/kernel/apic/msi.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 64 arch/x86/kernel/apic/vector.c const struct cpumask *mask) mask 67 arch/x86/kernel/apic/vector.c info->mask = mask; mask 298 arch/x86/kernel/apic/vector.c if (info->mask) mask 299 arch/x86/kernel/apic/vector.c return assign_irq_vector(irqd, info->mask); mask 15 arch/x86/kernel/apic/x2apic_cluster.c struct cpumask mask; mask 37 arch/x86/kernel/apic/x2apic_cluster.c __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) mask 48 arch/x86/kernel/apic/x2apic_cluster.c cpumask_copy(tmpmsk, mask); mask 58 arch/x86/kernel/apic/x2apic_cluster.c for_each_cpu_and(clustercpu, tmpmsk, &cmsk->mask) mask 66 arch/x86/kernel/apic/x2apic_cluster.c cpumask_andnot(tmpmsk, tmpmsk, &cmsk->mask); mask 72 arch/x86/kernel/apic/x2apic_cluster.c static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) mask 74 arch/x86/kernel/apic/x2apic_cluster.c __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); mask 78 arch/x86/kernel/apic/x2apic_cluster.c x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) mask 80 arch/x86/kernel/apic/x2apic_cluster.c __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); mask 121 arch/x86/kernel/apic/x2apic_cluster.c cpumask_set_cpu(smp_processor_id(), &cmsk->mask); mask 160 arch/x86/kernel/apic/x2apic_cluster.c cpumask_clear_cpu(dead_cpu, &cmsk->mask); mask 45 arch/x86/kernel/apic/x2apic_phys.c __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) mask 56 arch/x86/kernel/apic/x2apic_phys.c for_each_cpu(query_cpu, mask) { mask 65 arch/x86/kernel/apic/x2apic_phys.c static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) mask 67 arch/x86/kernel/apic/x2apic_phys.c __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); mask 71 arch/x86/kernel/apic/x2apic_phys.c x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) mask 73 arch/x86/kernel/apic/x2apic_phys.c __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); mask 552 arch/x86/kernel/apic/x2apic_uv_x.c static void uv_send_IPI_mask(const struct cpumask *mask, int vector) mask 556 arch/x86/kernel/apic/x2apic_uv_x.c for_each_cpu(cpu, mask) mask 560 arch/x86/kernel/apic/x2apic_uv_x.c static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) mask 565 arch/x86/kernel/apic/x2apic_uv_x.c for_each_cpu(cpu, mask) { mask 791 arch/x86/kernel/apic/x2apic_uv_x.c unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; mask 806 arch/x86/kernel/apic/x2apic_uv_x.c base = (gru.v & mask) >> shift; mask 535 arch/x86/kernel/cpu/amd.c va_align.mask = (upperbit - 1) & PAGE_MASK; mask 539 arch/x86/kernel/cpu/amd.c va_align.bits = get_random_int() & va_align.mask; mask 1013 arch/x86/kernel/cpu/amd.c u16 mask = 0xfff; mask 1023 arch/x86/kernel/cpu/amd.c tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; mask 1024 arch/x86/kernel/cpu/amd.c tlb_lli_4k[ENTRIES] = ebx & mask; mask 1032 arch/x86/kernel/cpu/amd.c mask = 0xff; mask 1036 arch/x86/kernel/cpu/amd.c if (!((eax >> 16) & mask)) mask 1039 arch/x86/kernel/cpu/amd.c tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; mask 1045 arch/x86/kernel/cpu/amd.c if (!(eax & mask)) { mask 1054 arch/x86/kernel/cpu/amd.c tlb_lli_2m[ENTRIES] = eax & mask; mask 1153 arch/x86/kernel/cpu/amd.c void set_dr_addr_mask(unsigned long mask, int dr) mask 1160 arch/x86/kernel/cpu/amd.c wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); mask 1165 arch/x86/kernel/cpu/amd.c wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); mask 963 arch/x86/kernel/cpu/bugs.c u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; mask 966 arch/x86/kernel/cpu/bugs.c mask |= SPEC_CTRL_STIBP; mask 968 arch/x86/kernel/cpu/bugs.c if (mask == x86_spec_ctrl_base) mask 972 arch/x86/kernel/cpu/bugs.c mask & SPEC_CTRL_STIBP ? "always-on" : "off"); mask 973 arch/x86/kernel/cpu/bugs.c x86_spec_ctrl_base = mask; mask 433 arch/x86/kernel/cpu/common.c unsigned long mask; mask 435 arch/x86/kernel/cpu/common.c mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP); mask 436 arch/x86/kernel/cpu/common.c cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask; mask 359 arch/x86/kernel/cpu/hygon.c u16 mask = 0xfff; mask 366 arch/x86/kernel/cpu/hygon.c tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; mask 367 arch/x86/kernel/cpu/hygon.c tlb_lli_4k[ENTRIES] = ebx & mask; mask 370 arch/x86/kernel/cpu/hygon.c if (!((eax >> 16) & mask)) mask 373 arch/x86/kernel/cpu/hygon.c tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; mask 379 arch/x86/kernel/cpu/hygon.c if (!(eax & mask)) { mask 383 arch/x86/kernel/cpu/hygon.c tlb_lli_2m[ENTRIES] = eax & mask; mask 464 arch/x86/kernel/cpu/intel.c movsl_mask.mask = 7; mask 467 arch/x86/kernel/cpu/intel.c movsl_mask.mask = 7; mask 34 arch/x86/kernel/cpu/mce/severity.c u64 mask; mask 53 arch/x86/kernel/cpu/mce/severity.c #define BITCLR(x) .mask = x, .result = 0 mask 54 arch/x86/kernel/cpu/mce/severity.c #define BITSET(x) .mask = x, .result = x mask 56 arch/x86/kernel/cpu/mce/severity.c #define MASK(x, y) .mask = x, .result = y mask 311 arch/x86/kernel/cpu/mce/severity.c if ((m->status & s->mask) != s->result) mask 179 arch/x86/kernel/cpu/mtrr/cleanup.c u64 base, mask; mask 186 arch/x86/kernel/cpu/mtrr/cleanup.c mask = (1ULL << address_bits) - 1; mask 187 arch/x86/kernel/cpu/mtrr/cleanup.c mask &= ~((((u64)sizek) << 10) - 1); mask 192 arch/x86/kernel/cpu/mtrr/cleanup.c mask |= 0x800; mask 197 arch/x86/kernel/cpu/mtrr/cleanup.c mask_lo = mask & ((1ULL<<32) - 1); mask 198 arch/x86/kernel/cpu/mtrr/cleanup.c mask_hi = mask >> 32; mask 68 arch/x86/kernel/cpu/mtrr/generic.c static u64 get_mtrr_size(u64 mask) mask 72 arch/x86/kernel/cpu/mtrr/generic.c mask >>= PAGE_SHIFT; mask 73 arch/x86/kernel/cpu/mtrr/generic.c mask |= size_or_mask; mask 74 arch/x86/kernel/cpu/mtrr/generic.c size = -mask; mask 164 arch/x86/kernel/cpu/mtrr/generic.c u64 base, mask; mask 182 arch/x86/kernel/cpu/mtrr/generic.c mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + mask 185 arch/x86/kernel/cpu/mtrr/generic.c start_state = ((start & mask) == (base & mask)); mask 186 arch/x86/kernel/cpu/mtrr/generic.c end_state = ((end & mask) == (base & mask)); mask 212 arch/x86/kernel/cpu/mtrr/generic.c *partial_end = base + get_mtrr_size(mask); mask 226 arch/x86/kernel/cpu/mtrr/generic.c if ((start & mask) != (base & mask)) mask 504 arch/x86/kernel/cpu/mtrr/generic.c unsigned long mask = smp_changes_mask; mask 506 arch/x86/kernel/cpu/mtrr/generic.c if (!mask) mask 508 arch/x86/kernel/cpu/mtrr/generic.c if (mask & MTRR_CHANGE_MASK_FIXED) mask 510 arch/x86/kernel/cpu/mtrr/generic.c if (mask & MTRR_CHANGE_MASK_VARIABLE) mask 512 arch/x86/kernel/cpu/mtrr/generic.c if (mask & MTRR_CHANGE_MASK_DEFTYPE) mask 584 arch/x86/kernel/cpu/mtrr/generic.c u64 tmp, mask; mask 606 arch/x86/kernel/cpu/mtrr/generic.c mask = size_or_mask | tmp; mask 613 arch/x86/kernel/cpu/mtrr/generic.c if (tmp != mask) { mask 616 arch/x86/kernel/cpu/mtrr/generic.c mask = tmp; mask 624 arch/x86/kernel/cpu/mtrr/generic.c *size = -mask; mask 797 arch/x86/kernel/cpu/mtrr/generic.c unsigned long mask, count; mask 804 arch/x86/kernel/cpu/mtrr/generic.c mask = set_mtrr_state(); mask 813 arch/x86/kernel/cpu/mtrr/generic.c for (count = 0; count < sizeof(mask) * 8; ++count) { mask 814 arch/x86/kernel/cpu/mtrr/generic.c if (mask & 0x01) mask 816 arch/x86/kernel/cpu/mtrr/generic.c mask >>= 1; mask 556 arch/x86/kernel/cpu/resctrl/internal.h umode_t mask); mask 265 arch/x86/kernel/cpu/resctrl/rdtgroup.c struct cpumask *mask; mask 277 arch/x86/kernel/cpu/resctrl/rdtgroup.c mask = &rdtgrp->plr->d->cpu_mask; mask 280 arch/x86/kernel/cpu/resctrl/rdtgroup.c cpumask_pr_args(mask)); mask 1568 arch/x86/kernel/cpu/resctrl/rdtgroup.c umode_t mask) mask 1580 arch/x86/kernel/cpu/resctrl/rdtgroup.c iattr.ia_mode = rft->mode & mask; mask 2183 arch/x86/kernel/cpu/resctrl/rdtgroup.c struct cpumask *mask) mask 2204 arch/x86/kernel/cpu/resctrl/rdtgroup.c if (mask && t->on_cpu) mask 2205 arch/x86/kernel/cpu/resctrl/rdtgroup.c cpumask_set_cpu(task_cpu(t), mask); mask 98 arch/x86/kernel/fpu/init.c unsigned int mask = 0; mask 106 arch/x86/kernel/fpu/init.c mask = fxregs.mxcsr_mask; mask 113 arch/x86/kernel/fpu/init.c if (mask == 0) mask 114 arch/x86/kernel/fpu/init.c mask = 0x0000ffbf; mask 116 arch/x86/kernel/fpu/init.c mxcsr_feature_mask &= mask; mask 1159 arch/x86/kernel/fpu/xstate.c u64 mask = ((u64)1 << i); mask 1161 arch/x86/kernel/fpu/xstate.c if (hdr.xfeatures & mask) { mask 1213 arch/x86/kernel/fpu/xstate.c u64 mask = ((u64)1 << i); mask 1215 arch/x86/kernel/fpu/xstate.c if (hdr.xfeatures & mask) { mask 751 arch/x86/kernel/hpet.c .mask = HPET_MASK, mask 119 arch/x86/kernel/hw_breakpoint.c if (info->mask) mask 120 arch/x86/kernel/hw_breakpoint.c set_dr_addr_mask(info->mask, i); mask 156 arch/x86/kernel/hw_breakpoint.c if (info->mask) mask 235 arch/x86/kernel/hw_breakpoint.c hw->mask = 0; mask 304 arch/x86/kernel/hw_breakpoint.c hw->mask = attr->bp_len - 1; mask 329 arch/x86/kernel/hw_breakpoint.c if (hw->mask) mask 330 arch/x86/kernel/hw_breakpoint.c align = hw->mask; mask 60 arch/x86/kernel/i8259.c unsigned int mask = 1 << irq; mask 64 arch/x86/kernel/i8259.c cached_irq_mask |= mask; mask 79 arch/x86/kernel/i8259.c unsigned int mask = ~(1 << irq); mask 83 arch/x86/kernel/i8259.c cached_irq_mask &= mask; mask 98 arch/x86/kernel/i8259.c unsigned int mask = 1<<irq; mask 104 arch/x86/kernel/i8259.c ret = inb(PIC_MASTER_CMD) & mask; mask 106 arch/x86/kernel/i8259.c ret = inb(PIC_SLAVE_CMD) & (mask >> 8); mask 400 arch/x86/kernel/i8259.c .mask = legacy_pic_uint_noop, mask 413 arch/x86/kernel/i8259.c .mask = mask_8259A_irq, mask 434 arch/x86/kernel/kvm.c static void __send_ipi_mask(const struct cpumask *mask, int vector) mask 446 arch/x86/kernel/kvm.c if (cpumask_empty(mask)) mask 460 arch/x86/kernel/kvm.c for_each_cpu(cpu, mask) { mask 488 arch/x86/kernel/kvm.c static void kvm_send_ipi_mask(const struct cpumask *mask, int vector) mask 490 arch/x86/kernel/kvm.c __send_ipi_mask(mask, vector); mask 493 arch/x86/kernel/kvm.c static void kvm_send_ipi_mask_allbutself(const struct cpumask *mask, int vector) mask 499 arch/x86/kernel/kvm.c cpumask_copy(&new_mask, mask); mask 515 arch/x86/kernel/kvm.c static void kvm_smp_send_call_func_ipi(const struct cpumask *mask) mask 519 arch/x86/kernel/kvm.c native_send_call_func_ipi(mask); mask 522 arch/x86/kernel/kvm.c for_each_cpu(cpu, mask) { mask 166 arch/x86/kernel/kvmclock.c .mask = CLOCKSOURCE_MASK(64), mask 65 arch/x86/kernel/nmi_selftest.c static void __init test_nmi_ipi(struct cpumask *mask) mask 78 arch/x86/kernel/nmi_selftest.c apic->send_IPI_mask(mask, NMI_VECTOR); mask 82 arch/x86/kernel/nmi_selftest.c while (!cpumask_empty(mask) && --timeout) mask 910 arch/x86/kernel/pci-calgary_64.c u64 mask; mask 929 arch/x86/kernel/pci-calgary_64.c mask = ~(0xFUL << phb_shift); mask 930 arch/x86/kernel/pci-calgary_64.c val64 &= mask; mask 90 arch/x86/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 92 arch/x86/kernel/perf_regs.c if (!mask || (mask & (REG_NOSUPPORT | PERF_REG_X86_RESERVED))) mask 116 arch/x86/kernel/perf_regs.c int perf_reg_validate(u64 mask) mask 118 arch/x86/kernel/perf_regs.c if (!mask || (mask & (REG_NOSUPPORT | PERF_REG_X86_RESERVED))) mask 256 arch/x86/kernel/setup.c size_t mask = align - 1; mask 260 arch/x86/kernel/setup.c BUG_ON(align & mask); mask 262 arch/x86/kernel/setup.c _brk_end = (_brk_end + mask) & ~mask; mask 160 arch/x86/kernel/signal.c struct pt_regs *regs, unsigned long mask) mask 211 arch/x86/kernel/signal.c put_user_ex(mask, &sc->oldmask); mask 39 arch/x86/kernel/sys_x86_64.c return va_align.mask; mask 130 arch/x86/kernel/time.c if (cs->mask != CLOCKSOURCE_MASK(64)) { mask 132 arch/x86/kernel/time.c cs->name, cs->mask); mask 1118 arch/x86/kernel/tsc.c .mask = CLOCKSOURCE_MASK(64), mask 1137 arch/x86/kernel/tsc.c .mask = CLOCKSOURCE_MASK(64), mask 1526 arch/x86/kernel/tsc.c const struct cpumask *mask = topology_core_cpumask(cpu); mask 1528 arch/x86/kernel/tsc.c if (!constant_tsc || !mask) mask 1531 arch/x86/kernel/tsc.c sibling = cpumask_any_but(mask, cpu); mask 57 arch/x86/kernel/tsc_msr.c u32 mask; mask 68 arch/x86/kernel/tsc_msr.c .mask = 0x07, mask 74 arch/x86/kernel/tsc_msr.c .mask = 0x07, mask 89 arch/x86/kernel/tsc_msr.c .mask = 0x07, mask 109 arch/x86/kernel/tsc_msr.c .mask = 0x0f, mask 120 arch/x86/kernel/tsc_msr.c .mask = 0x07, mask 133 arch/x86/kernel/tsc_msr.c .mask = 0x0f, mask 140 arch/x86/kernel/tsc_msr.c .mask = 0x0f, mask 184 arch/x86/kernel/tsc_msr.c index = lo & freq_desc->mask; mask 142 arch/x86/kernel/tsc_sync.c struct cpumask *mask; mask 167 arch/x86/kernel/tsc_sync.c mask = topology_core_cpumask(cpu); mask 168 arch/x86/kernel/tsc_sync.c refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids; mask 90 arch/x86/kernel/vm86_32.c #define set_flags(X, new, mask) \ mask 91 arch/x86/kernel/vm86_32.c ((X) = ((X) & ~(mask)) | ((new) & (mask))) mask 656 arch/x86/kvm/cpuid.c u64 mask = ((u64)1 << idx); mask 670 arch/x86/kvm/cpuid.c if (entry[i].eax == 0 || !(supported & mask)) mask 515 arch/x86/kvm/emulate.c static void assign_masked(ulong *dest, ulong src, ulong mask) mask 517 arch/x86/kvm/emulate.c *dest = (*dest & ~mask) | (src & mask); mask 576 arch/x86/kvm/emulate.c static void masked_increment(ulong *reg, ulong mask, int inc) mask 578 arch/x86/kvm/emulate.c assign_masked(reg, *reg + inc, mask); mask 1422 arch/x86/kvm/emulate.c long sv = 0, mask; mask 1425 arch/x86/kvm/emulate.c mask = ~((long)ctxt->dst.bytes * 8 - 1); mask 1428 arch/x86/kvm/emulate.c sv = (s16)ctxt->src.val & (s16)mask; mask 1430 arch/x86/kvm/emulate.c sv = (s32)ctxt->src.val & (s32)mask; mask 1432 arch/x86/kvm/emulate.c sv = (s64)ctxt->src.val & (s64)mask; mask 2157 arch/x86/kvm/emulate.c unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | mask 2194 arch/x86/kvm/emulate.c ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); mask 2978 arch/x86/kvm/emulate.c unsigned mask = (1 << len) - 1; mask 3006 arch/x86/kvm/emulate.c if ((perm >> bit_idx) & mask) mask 630 arch/x86/kvm/i8254.c static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask) mask 634 arch/x86/kvm/i8254.c if (!mask) mask 91 arch/x86/kvm/i8259.c int mask, ret = 1; mask 92 arch/x86/kvm/i8259.c mask = 1 << irq; mask 93 arch/x86/kvm/i8259.c if (s->elcr & mask) /* level triggered */ mask 95 arch/x86/kvm/i8259.c ret = !(s->irr & mask); mask 96 arch/x86/kvm/i8259.c s->irr |= mask; mask 97 arch/x86/kvm/i8259.c s->last_irr |= mask; mask 99 arch/x86/kvm/i8259.c s->irr &= ~mask; mask 100 arch/x86/kvm/i8259.c s->last_irr &= ~mask; mask 104 arch/x86/kvm/i8259.c if ((s->last_irr & mask) == 0) { mask 105 arch/x86/kvm/i8259.c ret = !(s->irr & mask); mask 106 arch/x86/kvm/i8259.c s->irr |= mask; mask 108 arch/x86/kvm/i8259.c s->last_irr |= mask; mask 110 arch/x86/kvm/i8259.c s->last_irr &= ~mask; mask 112 arch/x86/kvm/i8259.c return (s->imr & mask) ? -1 : ret; mask 119 arch/x86/kvm/i8259.c static inline int get_priority(struct kvm_kpic_state *s, int mask) mask 122 arch/x86/kvm/i8259.c if (mask == 0) mask 125 arch/x86/kvm/i8259.c while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) mask 135 arch/x86/kvm/i8259.c int mask, cur_priority, priority; mask 137 arch/x86/kvm/i8259.c mask = s->irr & ~s->imr; mask 138 arch/x86/kvm/i8259.c priority = get_priority(s, mask); mask 146 arch/x86/kvm/i8259.c mask = s->isr; mask 148 arch/x86/kvm/i8259.c mask &= ~(1 << 2); mask 149 arch/x86/kvm/i8259.c cur_priority = get_priority(s, mask); mask 177 arch/x86/kvm/ioapic.c u32 mask = 1 << irq; mask 185 arch/x86/kvm/ioapic.c ioapic->irr &= ~mask; mask 208 arch/x86/kvm/ioapic.c ioapic->irr |= mask; mask 210 arch/x86/kvm/ioapic.c ioapic->irr_delivered &= ~mask; mask 298 arch/x86/kvm/ioapic.c mask_before = e->fields.mask; mask 321 arch/x86/kvm/ioapic.c mask_after = e->fields.mask; mask 338 arch/x86/kvm/ioapic.c if (entry->fields.mask || mask 458 arch/x86/kvm/ioapic.c if (!ent->fields.mask && (ioapic->irr & (1 << i))) { mask 593 arch/x86/kvm/ioapic.c ioapic->redirtbl[i].fields.mask = 1; mask 71 arch/x86/kvm/ioapic.h u8 mask:1; mask 252 arch/x86/kvm/irq_comm.c bool mask) mask 262 arch/x86/kvm/irq_comm.c kimn->func(kimn, mask); mask 89 arch/x86/kvm/kvm_cache_regs.h static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask) mask 91 arch/x86/kvm/kvm_cache_regs.h ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS; mask 94 arch/x86/kvm/kvm_cache_regs.h return vcpu->arch.cr0 & mask; mask 102 arch/x86/kvm/kvm_cache_regs.h static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask) mask 104 arch/x86/kvm/kvm_cache_regs.h ulong tmask = mask & KVM_POSSIBLE_CR4_GUEST_BITS; mask 107 arch/x86/kvm/kvm_cache_regs.h return vcpu->arch.cr4 & mask; mask 131 arch/x86/kvm/lapic.c u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { mask 142 arch/x86/kvm/lapic.c *mask = dest_id & (0xffff >> (16 - cluster_size)); mask 144 arch/x86/kvm/lapic.c *mask = 0; mask 151 arch/x86/kvm/lapic.c *mask = dest_id & 0xff; mask 155 arch/x86/kvm/lapic.c *mask = dest_id & 0xf; mask 195 arch/x86/kvm/lapic.c u16 mask; mask 232 arch/x86/kvm/lapic.c if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) mask 235 arch/x86/kvm/lapic.c if (mask) mask 236 arch/x86/kvm/lapic.c cluster[ffs(mask) - 1] = apic; mask 1889 arch/x86/kvm/lapic.c u32 mask = 0x3ff; mask 1891 arch/x86/kvm/lapic.c mask |= APIC_SPIV_DIRECTED_EOI; mask 1892 arch/x86/kvm/lapic.c apic_set_spiv(apic, val & mask); mask 437 arch/x86/kvm/mmu.c u64 mask; mask 442 arch/x86/kvm/mmu.c mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK; mask 443 arch/x86/kvm/mmu.c mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK; mask 444 arch/x86/kvm/mmu.c return mask; mask 460 arch/x86/kvm/mmu.c u64 mask = generation_mmio_spte_mask(gen); mask 464 arch/x86/kvm/mmu.c mask |= shadow_mmio_value | access; mask 465 arch/x86/kvm/mmu.c mask |= gpa | shadow_nonpresent_or_rsvd_mask; mask 466 arch/x86/kvm/mmu.c mask |= (gpa & shadow_nonpresent_or_rsvd_mask) mask 470 arch/x86/kvm/mmu.c mmu_spte_set(sptep, mask); mask 1753 arch/x86/kvm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 1757 arch/x86/kvm/mmu.c while (mask) { mask 1758 arch/x86/kvm/mmu.c rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), mask 1763 arch/x86/kvm/mmu.c mask &= mask - 1; mask 1779 arch/x86/kvm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 1783 arch/x86/kvm/mmu.c while (mask) { mask 1784 arch/x86/kvm/mmu.c rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), mask 1789 arch/x86/kvm/mmu.c mask &= mask - 1; mask 1806 arch/x86/kvm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 1810 arch/x86/kvm/mmu.c mask); mask 1812 arch/x86/kvm/mmu.c kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); mask 3409 arch/x86/kvm/mmu.c unsigned long mask; mask 3420 arch/x86/kvm/mmu.c mask = KVM_PAGES_PER_HPAGE(level) - 1; mask 3421 arch/x86/kvm/mmu.c VM_BUG_ON((gfn & mask) != (pfn & mask)); mask 3422 arch/x86/kvm/mmu.c if (pfn & mask) { mask 3424 arch/x86/kvm/mmu.c pfn &= ~mask; mask 6248 arch/x86/kvm/mmu.c u64 mask; mask 6258 arch/x86/kvm/mmu.c mask = BIT_ULL(51) | PT_PRESENT_MASK; mask 6260 arch/x86/kvm/mmu.c mask = 0; mask 6262 arch/x86/kvm/mmu.c kvm_mmu_set_mmio_spte_mask(mask, mask, ACC_WRITE_MASK | ACC_USER_MASK); mask 57 arch/x86/kvm/mtrr.c u64 mask; mask 78 arch/x86/kvm/mtrr.c mask = (~0ULL) << cpuid_maxphyaddr(vcpu); mask 83 arch/x86/kvm/mtrr.c mask |= 0xf00; mask 86 arch/x86/kvm/mtrr.c mask |= 0x7ff; mask 87 arch/x86/kvm/mtrr.c if (data & mask) { mask 298 arch/x86/kvm/mtrr.c u64 mask; mask 302 arch/x86/kvm/mtrr.c mask = range->mask & PAGE_MASK; mask 307 arch/x86/kvm/mtrr.c *end = (*start | ~mask) + 1; mask 341 arch/x86/kvm/mtrr.c return (range->mask & (1 << 11)) != 0; mask 365 arch/x86/kvm/mtrr.c cur->mask = data | (-1LL << cpuid_maxphyaddr(vcpu)); mask 431 arch/x86/kvm/mtrr.c *pdata = vcpu->arch.mtrr_state.var_ranges[index].mask; mask 107 arch/x86/kvm/paging_tmpl.h unsigned mask; mask 115 arch/x86/kvm/paging_tmpl.h mask = (unsigned)~ACC_WRITE_MASK; mask 117 arch/x86/kvm/paging_tmpl.h mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & mask 119 arch/x86/kvm/paging_tmpl.h *access &= mask; mask 560 arch/x86/kvm/paging_tmpl.h u64 mask; mask 564 arch/x86/kvm/paging_tmpl.h mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1; mask 565 arch/x86/kvm/paging_tmpl.h base_gpa = pte_gpa & ~mask; mask 737 arch/x86/kvm/paging_tmpl.h gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1); mask 747 arch/x86/kvm/paging_tmpl.h self_changed |= !(gfn & mask); mask 318 arch/x86/kvm/pmu.c u64 mask = fast_mode ? ~0u : ~0ull; mask 326 arch/x86/kvm/pmu.c pmc = kvm_x86_ops->pmu_ops->msr_idx_to_pmc(vcpu, idx, &mask); mask 330 arch/x86/kvm/pmu.c *data = pmc_read_counter(pmc) & mask; mask 31 arch/x86/kvm/pmu.h u64 *mask); mask 187 arch/x86/kvm/pmu_amd.c static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *mask) mask 766 arch/x86/kvm/svm.c static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) mask 770 arch/x86/kvm/svm.c if (mask == 0) mask 1309 arch/x86/kvm/svm.c u64 msr, mask; mask 1336 arch/x86/kvm/svm.c mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0; mask 1338 arch/x86/kvm/svm.c kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK); mask 3153 arch/x86/kvm/svm.c u16 val, mask; mask 3166 arch/x86/kvm/svm.c mask = (0xf >> (4 - size)) << start_bit; mask 3172 arch/x86/kvm/svm.c return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; mask 3178 arch/x86/kvm/svm.c int write, mask; mask 3186 arch/x86/kvm/svm.c mask = 1 << ((2 * (msr & 0xf)) + write); mask 3197 arch/x86/kvm/svm.c return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST; mask 1048 arch/x86/kvm/vmx/nested.c static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask) mask 1050 arch/x86/kvm/vmx/nested.c superset &= mask; mask 1051 arch/x86/kvm/vmx/nested.c subset &= mask; mask 214 arch/x86/kvm/vmx/ops.h static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask) mask 219 arch/x86/kvm/vmx/ops.h return evmcs_write32(field, evmcs_read32(field) & ~mask); mask 221 arch/x86/kvm/vmx/ops.h __vmcs_writel(field, __vmcs_readl(field) & ~mask); mask 224 arch/x86/kvm/vmx/ops.h static __always_inline void vmcs_set_bits(unsigned long field, u32 mask) mask 229 arch/x86/kvm/vmx/ops.h return evmcs_write32(field, evmcs_read32(field) | mask); mask 231 arch/x86/kvm/vmx/ops.h __vmcs_writel(field, __vmcs_readl(field) | mask); mask 130 arch/x86/kvm/vmx/pmu_intel.c unsigned idx, u64 *mask) mask 147 arch/x86/kvm/vmx/pmu_intel.c *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP]; mask 704 arch/x86/kvm/vmx/vmx.c u32 mask = 1 << (seg * SEG_FIELD_NR + field); mask 710 arch/x86/kvm/vmx/vmx.c ret = vmx->segment_cache.bitmask & mask; mask 711 arch/x86/kvm/vmx/vmx.c vmx->segment_cache.bitmask |= mask; mask 986 arch/x86/kvm/vmx/vmx.c vmx->guest_msrs[efer_offset].mask = ~ignore_bits; mask 1130 arch/x86/kvm/vmx/vmx.c vmx->guest_msrs[i].mask); mask 1450 arch/x86/kvm/vmx/vmx.c void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) mask 1457 arch/x86/kvm/vmx/vmx.c if (mask & KVM_X86_SHADOW_INT_MOV_SS) mask 1459 arch/x86/kvm/vmx/vmx.c else if (mask & KVM_X86_SHADOW_INT_STI) mask 2151 arch/x86/kvm/vmx/vmx.c msr->mask); mask 4221 arch/x86/kvm/vmx/vmx.c vmx->guest_msrs[j].mask = -1ull; mask 6922 arch/x86/kvm/vmx/vmx.c u32 mask = mask 6931 arch/x86/kvm/vmx/vmx.c secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); mask 7313 arch/x86/kvm/vmx/vmx.c gfn_t offset, unsigned long mask) mask 7315 arch/x86/kvm/vmx/vmx.c kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); mask 35 arch/x86/kvm/vmx/vmx.h u64 mask; mask 320 arch/x86/kvm/vmx/vmx.h void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask); mask 299 arch/x86/kvm/x86.c int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) mask 305 arch/x86/kvm/x86.c value = (value & mask) | (smsr->values[slot].host & ~mask); mask 399 arch/x86/kvm/x86.c unsigned int mask; mask 404 arch/x86/kvm/x86.c mask = 1 << vector; mask 407 arch/x86/kvm/x86.c if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR))) mask 410 arch/x86/kvm/x86.c if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) mask 1487 arch/x86/kvm/x86.c void kvm_enable_efer_bits(u64 mask) mask 1489 arch/x86/kvm/x86.c efer_reserved_bits &= ~mask; mask 1625 arch/x86/kvm/x86.c u64 mask; mask 1649 arch/x86/kvm/x86.c vdata->clock.mask = tk->tkr_mono.mask; mask 2095 arch/x86/kvm/x86.c gtod->clock.mask; mask 2105 arch/x86/kvm/x86.c gtod->clock.mask; mask 6326 arch/x86/kvm/x86.c static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) mask 6336 arch/x86/kvm/x86.c if (int_shadow & mask) mask 6337 arch/x86/kvm/x86.c mask = 0; mask 6338 arch/x86/kvm/x86.c if (unlikely(int_shadow || mask)) { mask 6339 arch/x86/kvm/x86.c kvm_x86_ops->set_interrupt_shadow(vcpu, mask); mask 6340 arch/x86/kvm/x86.c if (!mask) mask 99 arch/x86/lib/msr-smp.c static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, mask 113 arch/x86/lib/msr-smp.c if (cpumask_test_cpu(this_cpu, mask)) mask 116 arch/x86/lib/msr-smp.c smp_call_function_many(mask, msr_func, &rv, 1); mask 127 arch/x86/lib/msr-smp.c void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) mask 129 arch/x86/lib/msr-smp.c __rwmsr_on_cpus(mask, msr_no, msrs, __rdmsr_on_cpu); mask 141 arch/x86/lib/msr-smp.c void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) mask 143 arch/x86/lib/msr-smp.c __rwmsr_on_cpus(mask, msr_no, msrs, __wrmsr_on_cpu); mask 24 arch/x86/lib/usercopy_32.c if (n >= 64 && ((a1 ^ a2) & movsl_mask.mask)) mask 818 arch/x86/mm/numa.c struct cpumask *mask; mask 824 arch/x86/mm/numa.c mask = node_to_cpumask_map[node]; mask 825 arch/x86/mm/numa.c if (!mask) { mask 832 arch/x86/mm/numa.c cpumask_set_cpu(cpu, mask); mask 834 arch/x86/mm/numa.c cpumask_clear_cpu(cpu, mask); mask 838 arch/x86/mm/numa.c cpu, node, cpumask_pr_args(mask)); mask 1761 arch/x86/mm/pageattr.c pgprot_t mask, int array) mask 1763 arch/x86/mm/pageattr.c return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, mask 1768 arch/x86/mm/pageattr.c pgprot_t mask, int array) mask 1770 arch/x86/mm/pageattr.c return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, mask 1775 arch/x86/mm/pageattr.c pgprot_t mask) mask 1777 arch/x86/mm/pageattr.c return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, mask 1782 arch/x86/mm/pageattr.c pgprot_t mask) mask 1784 arch/x86/mm/pageattr.c return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, mask 354 arch/x86/oprofile/op_model_p4.c #define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9)) mask 26 arch/x86/pci/ce4100.c u32 mask; mask 68 arch/x86/pci/ce4100.c reg->sim_reg.value = (value & reg->sim_reg.mask) | mask 69 arch/x86/pci/ce4100.c (reg->sim_reg.value & ~reg->sim_reg.mask); mask 82 arch/x86/pci/ce4100.c if (*value != reg->sim_reg.mask) mask 89 arch/x86/pci/ce4100.c reg->sim_reg.mask = 0; mask 168 arch/x86/pci/ce4100.c uint32_t mask; mask 171 arch/x86/pci/ce4100.c mask = 0xFFFFFFFF >> ((4 - len) * 8); mask 172 arch/x86/pci/ce4100.c *value &= mask; mask 705 arch/x86/pci/common.c int pcibios_enable_device(struct pci_dev *dev, int mask) mask 709 arch/x86/pci/common.c if ((err = pci_enable_resources(dev, mask)) < 0) mask 111 arch/x86/pci/fixup.c int mask = 0x1f; /* clear bits 5, 6, 7 by default */ mask 124 arch/x86/pci/fixup.c mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 mask 129 arch/x86/pci/fixup.c if (v & ~mask) { mask 131 arch/x86/pci/fixup.c d->device, d->revision, where, v, mask, v & mask); mask 132 arch/x86/pci/fixup.c v &= mask; mask 155 arch/x86/pci/irq.c unsigned char mask = 1 << (irq & 7); mask 166 arch/x86/pci/irq.c if (!(val & mask)) { mask 168 arch/x86/pci/irq.c outb(val | mask, port); mask 887 arch/x86/pci/irq.c u32 mask; mask 914 arch/x86/pci/irq.c mask = info->irq[pin - 1].bitmap; mask 920 arch/x86/pci/irq.c 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); mask 921 arch/x86/pci/irq.c mask &= pcibios_irq_mask; mask 936 arch/x86/pci/irq.c mask = 0x400; mask 946 arch/x86/pci/irq.c if (newirq && !((1 << newirq) & mask)) { mask 951 arch/x86/pci/irq.c "%#x; try pci=usepirqmask\n", newirq, mask); mask 955 arch/x86/pci/irq.c if (!(mask & (1 << i))) mask 969 arch/x86/pci/irq.c ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { mask 982 arch/x86/pci/irq.c if (newirq && mask == (1 << newirq)) { mask 1008 arch/x86/pci/irq.c ((1 << dev2->irq) & mask))) { mask 147 arch/x86/pci/mmconfig-shared.c u32 pciexbar, mask = 0, len = 0; mask 158 arch/x86/pci/mmconfig-shared.c mask = 0xf0000000U; mask 162 arch/x86/pci/mmconfig-shared.c mask = 0xf8000000U; mask 166 arch/x86/pci/mmconfig-shared.c mask = 0xfc000000U; mask 176 arch/x86/pci/mmconfig-shared.c if ((pciexbar & mask) & 0x0fffffffU) mask 180 arch/x86/pci/mmconfig-shared.c if ((pciexbar & mask) >= 0xf0000000U) mask 183 arch/x86/pci/mmconfig-shared.c if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) mask 189 arch/x86/pci/pcbios.c u16 number = 0, mask = 0; mask 200 arch/x86/pci/pcbios.c mask = 0xff; mask 204 arch/x86/pci/pcbios.c mask = 0xffff; mask 225 arch/x86/pci/pcbios.c if (mask) mask 226 arch/x86/pci/pcbios.c *value &= mask; mask 143 arch/x86/platform/intel/iosf_mbi.c int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) mask 169 arch/x86/platform/intel/iosf_mbi.c value &= ~mask; mask 170 arch/x86/platform/intel/iosf_mbi.c mdr &= mask; mask 95 arch/x86/platform/scx200/scx200_32.c u32 scx200_gpio_configure(unsigned index, u32 mask, u32 bits) mask 104 arch/x86/platform/scx200/scx200_32.c new_config = (config & mask) | bits; mask 425 arch/x86/platform/uv/tlb_uv.c cpumask_t *mask = bcp->uvhub_master->cpumask; mask 430 arch/x86/platform/uv/tlb_uv.c cpumask_clear(mask); mask 440 arch/x86/platform/uv/tlb_uv.c cpumask_set_cpu(cpu, mask); mask 444 arch/x86/platform/uv/tlb_uv.c smp_call_function_many(mask, do_reset, (void *)&reset_args, 1); mask 2198 arch/x86/platform/uv/tlb_uv.c cpumask_var_t *mask; mask 2219 arch/x86/platform/uv/tlb_uv.c mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); mask 2220 arch/x86/platform/uv/tlb_uv.c zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); mask 42 arch/x86/platform/uv/uv_irq.c entry->mask = 0; mask 51 arch/x86/platform/uv/uv_irq.c uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask, mask 58 arch/x86/platform/uv/uv_irq.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 144 arch/x86/platform/uv/uv_irq.c entry->mask = 1; mask 270 arch/x86/platform/uv/uv_nmi.c static void uv_init_hubless_pch_io(int offset, int mask, int data) mask 275 arch/x86/platform/uv/uv_nmi.c if (mask) { /* OR in new data */ mask 276 arch/x86/platform/uv/uv_nmi.c int writed = (readd & ~mask) | data; mask 279 arch/x86/platform/uv/uv_nmi.c addr, readd, ~mask, data, writed); mask 303 arch/x86/platform/uv/uv_nmi.c unsigned int mask; mask 308 arch/x86/platform/uv/uv_nmi.c .mask = 0x1, mask 315 arch/x86/platform/uv/uv_nmi.c .mask = 0x0, mask 320 arch/x86/platform/uv/uv_nmi.c .mask = 0x0, mask 325 arch/x86/platform/uv/uv_nmi.c .mask = 0x0, mask 330 arch/x86/platform/uv/uv_nmi.c .mask = 0x0, mask 337 arch/x86/platform/uv/uv_nmi.c .mask = 0x1, mask 342 arch/x86/platform/uv/uv_nmi.c .mask = 0x1, mask 347 arch/x86/platform/uv/uv_nmi.c .mask = 0x1, mask 352 arch/x86/platform/uv/uv_nmi.c .mask = 0x1, mask 359 arch/x86/platform/uv/uv_nmi.c .mask = 0xffffffff, mask 399 arch/x86/platform/uv/uv_nmi.c .mask = 0x3c00, mask 417 arch/x86/platform/uv/uv_nmi.c init_nmi[i].mask, mask 28 arch/x86/platform/uv/uv_time.c .mask = (u64)UVH_RTC_REAL_TIME_CLOCK_MASK, mask 382 arch/x86/platform/uv/uv_time.c clock_event_device_uv.max_delta_ns = clocksource_uv.mask * mask 384 arch/x86/platform/uv/uv_time.c clock_event_device_uv.max_delta_ticks = clocksource_uv.mask; mask 145 arch/x86/um/ptrace_32.c unsigned long mask = ~0UL; mask 155 arch/x86/um/ptrace_32.c mask = 0xffff; mask 172 arch/x86/um/ptrace_32.c return mask & child->thread.regs.regs.gp[reg_offsets[regno]]; mask 139 arch/x86/um/ptrace_64.c unsigned long mask = ~0UL; mask 142 arch/x86/um/ptrace_64.c mask = 0xffffffff; mask 173 arch/x86/um/ptrace_64.c mask = 0xffff; mask 178 arch/x86/um/ptrace_64.c return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]]; mask 238 arch/x86/um/signal.c unsigned long mask) mask 283 arch/x86/um/signal.c sc.oldmask = mask; mask 361 arch/x86/um/signal.c struct pt_regs *regs, sigset_t *mask) mask 379 arch/x86/um/signal.c err |= copy_sc_to_user(&frame->sc, &frame->fpstate, regs, mask->sig[0]); mask 381 arch/x86/um/signal.c err |= __copy_to_user(&frame->extramask, &mask->sig[1], mask 407 arch/x86/um/signal.c struct pt_regs *regs, sigset_t *mask) mask 427 arch/x86/um/signal.c err |= copy_ucontext_to_user(&frame->uc, &frame->fpstate, mask, mask 840 arch/x86/xen/enlighten_pv.c void xen_set_iopl_mask(unsigned mask) mask 845 arch/x86/xen/enlighten_pv.c set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3; mask 1013 arch/x86/xen/mmu_pv.c cpumask_var_t mask; mask 1019 arch/x86/xen/mmu_pv.c if (!alloc_cpumask_var(&mask, GFP_ATOMIC)) { mask 1035 arch/x86/xen/mmu_pv.c cpumask_clear(mask); mask 1038 arch/x86/xen/mmu_pv.c cpumask_set_cpu(cpu, mask); mask 1041 arch/x86/xen/mmu_pv.c smp_call_function_many(mask, drop_mm_ref_this_cpu, mm, 1); mask 1042 arch/x86/xen/mmu_pv.c free_cpumask_var(mask); mask 1353 arch/x86/xen/mmu_pv.c DECLARE_BITMAP(mask, NR_CPUS); mask 1357 arch/x86/xen/mmu_pv.c sizeof(args->mask[0]) * BITS_TO_LONGS(num_possible_cpus()); mask 1366 arch/x86/xen/mmu_pv.c args->op.arg2.vcpumask = to_cpumask(args->mask); mask 1369 arch/x86/xen/mmu_pv.c cpumask_and(to_cpumask(args->mask), cpus, cpu_online_mask); mask 1370 arch/x86/xen/mmu_pv.c cpumask_clear_cpu(smp_processor_id(), to_cpumask(args->mask)); mask 931 arch/x86/xen/setup.c u32 *mask = vdso_image_32.data + mask 933 arch/x86/xen/setup.c *mask |= 1 << VDSO_NOTE_NONEGSEG_BIT; mask 156 arch/x86/xen/smp.c static void __xen_send_IPI_mask(const struct cpumask *mask, mask 161 arch/x86/xen/smp.c for_each_cpu_and(cpu, mask, cpu_online_mask) mask 165 arch/x86/xen/smp.c void xen_smp_send_call_function_ipi(const struct cpumask *mask) mask 169 arch/x86/xen/smp.c __xen_send_IPI_mask(mask, XEN_CALL_FUNCTION_VECTOR); mask 172 arch/x86/xen/smp.c for_each_cpu(cpu, mask) { mask 218 arch/x86/xen/smp.c void xen_send_IPI_mask(const struct cpumask *mask, mask 224 arch/x86/xen/smp.c __xen_send_IPI_mask(mask, xen_vector); mask 243 arch/x86/xen/smp.c void xen_send_IPI_mask_allbutself(const struct cpumask *mask, mask 253 arch/x86/xen/smp.c for_each_cpu_and(cpu, mask, cpu_online_mask) { mask 5 arch/x86/xen/smp.h extern void xen_send_IPI_mask(const struct cpumask *mask, mask 7 arch/x86/xen/smp.h extern void xen_send_IPI_mask_allbutself(const struct cpumask *mask, mask 21 arch/x86/xen/smp.h void xen_smp_send_call_function_ipi(const struct cpumask *mask); mask 152 arch/x86/xen/time.c .mask = ~0, mask 104 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 115 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 122 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 133 arch/xtensa/include/asm/bitops.h : "a" (~mask), "a" (p) mask 140 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 151 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 159 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 170 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 173 arch/xtensa/include/asm/bitops.h return value & mask; mask 180 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 191 arch/xtensa/include/asm/bitops.h : "a" (~mask), "a" (p) mask 194 arch/xtensa/include/asm/bitops.h return value & mask; mask 201 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 212 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 215 arch/xtensa/include/asm/bitops.h return value & mask; mask 223 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 234 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 241 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 252 arch/xtensa/include/asm/bitops.h : "a" (~mask), "a" (p) mask 259 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 270 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 278 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 289 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 292 arch/xtensa/include/asm/bitops.h return tmp & mask; mask 299 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 310 arch/xtensa/include/asm/bitops.h : "a" (~mask), "a" (p) mask 313 arch/xtensa/include/asm/bitops.h return tmp & mask; mask 320 arch/xtensa/include/asm/bitops.h unsigned long mask = 1UL << (bit & 31); mask 331 arch/xtensa/include/asm/bitops.h : "a" (mask), "a" (p) mask 334 arch/xtensa/include/asm/bitops.h return tmp & mask; mask 23 arch/xtensa/include/asm/smp.h void arch_send_call_function_ipi_mask(const struct cpumask *mask); mask 92 arch/xtensa/kernel/irq.c u32 mask = 1 << hw; mask 94 arch/xtensa/kernel/irq.c if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) { mask 98 arch/xtensa/kernel/irq.c } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) { mask 102 arch/xtensa/kernel/irq.c } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) { mask 106 arch/xtensa/kernel/irq.c } else if (mask & XCHAL_INTTYPE_MASK_TIMER) { mask 111 arch/xtensa/kernel/irq.c } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) { mask 127 arch/xtensa/kernel/irq.c unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE | mask 131 arch/xtensa/kernel/irq.c for (i = 0; mask; ++i, mask >>= 1) { mask 132 arch/xtensa/kernel/irq.c if ((mask & 1) && ext_irq-- == 0) mask 140 arch/xtensa/kernel/irq.c unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE | mask 143 arch/xtensa/kernel/irq.c return hweight32(mask); mask 175 arch/xtensa/kernel/irq.c struct cpumask *mask; mask 181 arch/xtensa/kernel/irq.c mask = irq_data_get_affinity_mask(data); mask 182 arch/xtensa/kernel/irq.c if (!cpumask_test_cpu(cpu, mask)) mask 185 arch/xtensa/kernel/irq.c newcpu = cpumask_any_and(mask, cpu_online_mask); mask 191 arch/xtensa/kernel/irq.c cpumask_setall(mask); mask 193 arch/xtensa/kernel/irq.c irq_set_affinity(i, mask); mask 41 arch/xtensa/kernel/perf_event.c #define XTENSA_PMU_MASK(select, mask) \ mask 43 arch/xtensa/kernel/perf_event.c ((mask) << XTENSA_PMU_PMCTRL_MASK_SHIFT) | \ mask 372 arch/xtensa/kernel/smp.c unsigned long mask = 0; mask 375 arch/xtensa/kernel/smp.c mask |= 1 << index; mask 377 arch/xtensa/kernel/smp.c set_er(mask, MIPISET(msg_id)); mask 380 arch/xtensa/kernel/smp.c void arch_send_call_function_ipi_mask(const struct cpumask *mask) mask 382 arch/xtensa/kernel/smp.c send_ipi_message(mask, IPI_CALL_FUNC); mask 51 arch/xtensa/kernel/time.c .mask = CLOCKSOURCE_MASK(32), mask 706 block/bio.c unsigned long mask = queue_segment_boundary(q); mask 710 block/bio.c if ((addr1 | mask) != (addr2 | mask)) mask 163 block/blk-merge.c unsigned long mask = queue_segment_boundary(q); mask 166 block/blk-merge.c if (mask == BLK_SEG_BOUNDARY_MASK) mask 169 block/blk-merge.c return min_t(unsigned long, mask - (mask & offset) + 1, mask 29 block/blk-mq-pci.c const struct cpumask *mask; mask 33 block/blk-mq-pci.c mask = pci_irq_get_affinity(pdev, queue + offset); mask 34 block/blk-mq-pci.c if (!mask) mask 37 block/blk-mq-pci.c for_each_cpu(cpu, mask) mask 27 block/blk-mq-rdma.c const struct cpumask *mask; mask 31 block/blk-mq-rdma.c mask = ib_get_vector_affinity(dev, first_vec + queue); mask 32 block/blk-mq-rdma.c if (!mask) mask 35 block/blk-mq-rdma.c for_each_cpu(cpu, mask) mask 27 block/blk-mq-virtio.c const struct cpumask *mask; mask 34 block/blk-mq-virtio.c mask = vdev->config->get_vq_affinity(vdev, first_vec + queue); mask 35 block/blk-mq-virtio.c if (!mask) mask 38 block/blk-mq-virtio.c for_each_cpu(cpu, mask) mask 683 block/blk-settings.c void blk_queue_update_dma_pad(struct request_queue *q, unsigned int mask) mask 685 block/blk-settings.c if (mask > q->dma_pad_mask) mask 686 block/blk-settings.c q->dma_pad_mask = mask; mask 732 block/blk-settings.c void blk_queue_segment_boundary(struct request_queue *q, unsigned long mask) mask 734 block/blk-settings.c if (mask < PAGE_SIZE - 1) { mask 735 block/blk-settings.c mask = PAGE_SIZE - 1; mask 737 block/blk-settings.c __func__, mask); mask 740 block/blk-settings.c q->limits.seg_boundary_mask = mask; mask 749 block/blk-settings.c void blk_queue_virt_boundary(struct request_queue *q, unsigned long mask) mask 751 block/blk-settings.c q->limits.virt_boundary_mask = mask; mask 759 block/blk-settings.c if (mask) mask 774 block/blk-settings.c void blk_queue_dma_alignment(struct request_queue *q, int mask) mask 776 block/blk-settings.c q->dma_alignment = mask; mask 794 block/blk-settings.c void blk_queue_update_dma_alignment(struct request_queue *q, int mask) mask 796 block/blk-settings.c BUG_ON(mask > PAGE_SIZE); mask 798 block/blk-settings.c if (mask > q->dma_alignment) mask 799 block/blk-settings.c q->dma_alignment = mask; mask 78 block/blk.h unsigned long mask = queue_segment_boundary(q); mask 86 block/blk.h if ((addr1 | mask) != ((addr2 + vec2->bv_len - 1) | mask)) mask 1762 block/genhd.c void disk_flush_events(struct gendisk *disk, unsigned int mask) mask 1770 block/genhd.c ev->clearing |= mask; mask 1788 block/genhd.c unsigned int disk_clear_events(struct gendisk *disk, unsigned int mask) mask 1793 block/genhd.c unsigned int clearing = mask; mask 1797 block/genhd.c if ((mask & DISK_EVENT_MEDIA_CHANGE) && mask 1824 block/genhd.c pending = ev->pending & mask; mask 1825 block/genhd.c ev->pending &= ~mask; mask 1827 block/genhd.c WARN_ON_ONCE(clearing & mask); mask 335 crypto/ablkcipher.c u32 mask) mask 341 crypto/ablkcipher.c u32 mask) mask 106 crypto/acompress.c u32 mask) mask 108 crypto/acompress.c return crypto_alloc_tfm(alg_name, &crypto_acomp_type, type, mask); mask 518 crypto/adiantum.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 545 crypto/adiantum.c algt->mask)); mask 232 crypto/aead.c struct rtattr **tb, u32 type, u32 mask) mask 247 crypto/aead.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 261 crypto/aead.c mask |= crypto_requires_sync(algt->type, algt->mask); mask 264 crypto/aead.c err = crypto_grab_aead(spawn, name, type, mask); mask 372 crypto/aead.c u32 type, u32 mask) mask 375 crypto/aead.c return crypto_grab_spawn(&spawn->base, name, type, mask); mask 379 crypto/aead.c struct crypto_aead *crypto_alloc_aead(const char *alg_name, u32 type, u32 mask) mask 381 crypto/aead.c return crypto_alloc_tfm(alg_name, &crypto_aead_type, type, mask); mask 1061 crypto/af_alg.c __poll_t mask; mask 1064 crypto/af_alg.c mask = 0; mask 1067 crypto/af_alg.c mask |= EPOLLIN | EPOLLRDNORM; mask 1070 crypto/af_alg.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 1072 crypto/af_alg.c return mask; mask 225 crypto/ahash.c unsigned long mask) mask 227 crypto/ahash.c return len + (mask & ~(crypto_tfm_ctx_alignment() - 1)); mask 560 crypto/ahash.c u32 mask) mask 562 crypto/ahash.c return crypto_alloc_tfm(alg_name, &crypto_ahash_type, type, mask); mask 566 crypto/ahash.c int crypto_has_ahash(const char *alg_name, u32 type, u32 mask) mask 568 crypto/ahash.c return crypto_type_has_alg(alg_name, &crypto_ahash_type, type, mask); mask 665 crypto/ahash.c struct hash_alg_common *ahash_attr_alg(struct rtattr *rta, u32 type, u32 mask) mask 669 crypto/ahash.c alg = crypto_attr_alg2(rta, &crypto_ahash_type, type, mask); mask 94 crypto/akcipher.c u32 type, u32 mask) mask 97 crypto/akcipher.c return crypto_grab_spawn(&spawn->base, name, type, mask); mask 102 crypto/akcipher.c u32 mask) mask 104 crypto/akcipher.c return crypto_alloc_tfm(alg_name, &crypto_akcipher_type, type, mask); mask 141 crypto/algapi.c if ((spawn->alg->cra_flags ^ new_type) & spawn->mask) mask 320 crypto/algapi.c if ((q->cra_flags ^ alg->cra_flags) & larval->mask) mask 633 crypto/algapi.c struct crypto_instance *inst, u32 mask) mask 641 crypto/algapi.c spawn->mask = mask; mask 673 crypto/algapi.c u32 type, u32 mask) mask 678 crypto/algapi.c alg = crypto_find_alg(name, spawn->frontend, type, mask); mask 682 crypto/algapi.c err = crypto_init_spawn(spawn, alg, spawn->inst, mask); mask 713 crypto/algapi.c u32 mask) mask 723 crypto/algapi.c if (unlikely((alg->cra_flags ^ type) & mask)) mask 726 crypto/algapi.c tfm = __crypto_alloc_tfm(alg, type, mask); mask 797 crypto/algapi.c if ((algt->type ^ type) & algt->mask) mask 824 crypto/algapi.c u32 type, u32 mask) mask 832 crypto/algapi.c return crypto_find_alg(name, frontend, type, mask); mask 1038 crypto/algapi.c u32 type, u32 mask) mask 1041 crypto/algapi.c struct crypto_alg *alg = crypto_find_alg(name, frontend, type, mask); mask 178 crypto/algboss.c param->type.data.mask = larval->mask & ~CRYPTO_ALG_TESTED; mask 182 crypto/algboss.c param->omask = larval->mask; mask 473 crypto/algif_aead.c static void *aead_bind(const char *name, u32 type, u32 mask) mask 483 crypto/algif_aead.c aead = crypto_alloc_aead(name, type, mask); mask 401 crypto/algif_hash.c static void *hash_bind(const char *name, u32 type, u32 mask) mask 403 crypto/algif_hash.c return crypto_alloc_ahash(name, type, mask); mask 116 crypto/algif_rng.c static void *rng_bind(const char *name, u32 type, u32 mask) mask 118 crypto/algif_rng.c return crypto_alloc_rng(name, type, mask); mask 304 crypto/algif_skcipher.c static void *skcipher_bind(const char *name, u32 type, u32 mask) mask 306 crypto/algif_skcipher.c return crypto_alloc_skcipher(name, type, mask); mask 56 crypto/api.c u32 mask) mask 67 crypto/api.c if ((q->cra_flags ^ type) & mask) mask 72 crypto/api.c ((struct crypto_larval *)q)->mask != mask) mask 105 crypto/api.c struct crypto_larval *crypto_larval_alloc(const char *name, u32 type, u32 mask) mask 113 crypto/api.c larval->mask = mask; mask 126 crypto/api.c u32 mask) mask 131 crypto/api.c larval = crypto_larval_alloc(name, type, mask); mask 138 crypto/api.c alg = __crypto_alg_lookup(name, type, mask); mask 194 crypto/api.c u32 mask) mask 199 crypto/api.c if (!((type | mask) & CRYPTO_ALG_TESTED)) mask 203 crypto/api.c alg = __crypto_alg_lookup(name, type | test, mask | test); mask 205 crypto/api.c alg = __crypto_alg_lookup(name, type, mask); mask 218 crypto/api.c u32 mask) mask 226 crypto/api.c mask &= ~(CRYPTO_ALG_LARVAL | CRYPTO_ALG_DEAD); mask 228 crypto/api.c alg = crypto_alg_lookup(name, type, mask); mask 229 crypto/api.c if (!alg && !(mask & CRYPTO_NOLOAD)) { mask 232 crypto/api.c if (!((type ^ CRYPTO_ALG_NEED_FALLBACK) & mask & mask 236 crypto/api.c alg = crypto_alg_lookup(name, type, mask); mask 242 crypto/api.c alg = crypto_larval_add(name, type, mask); mask 261 crypto/api.c struct crypto_alg *crypto_alg_mod_lookup(const char *name, u32 type, u32 mask) mask 274 crypto/api.c if (!((type | mask) & CRYPTO_ALG_INTERNAL)) mask 275 crypto/api.c mask |= CRYPTO_ALG_INTERNAL; mask 277 crypto/api.c larval = crypto_larval_lookup(name, type, mask); mask 294 crypto/api.c static int crypto_init_ops(struct crypto_tfm *tfm, u32 type, u32 mask) mask 299 crypto/api.c return type_obj->init(tfm, type, mask); mask 324 crypto/api.c static unsigned int crypto_ctxsize(struct crypto_alg *alg, u32 type, u32 mask) mask 331 crypto/api.c return len + type_obj->ctxsize(alg, type, mask); mask 357 crypto/api.c u32 mask) mask 363 crypto/api.c tfm_size = sizeof(*tfm) + crypto_ctxsize(alg, type, mask); mask 370 crypto/api.c err = crypto_init_ops(tfm, type, mask); mask 414 crypto/api.c struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask) mask 422 crypto/api.c alg = crypto_alg_mod_lookup(alg_name, type, mask); mask 428 crypto/api.c tfm = __crypto_alloc_tfm(alg, type, mask); mask 491 crypto/api.c u32 type, u32 mask) mask 495 crypto/api.c mask &= frontend->maskclear; mask 497 crypto/api.c mask |= frontend->maskset; mask 500 crypto/api.c return crypto_alg_mod_lookup(alg_name, type, mask); mask 525 crypto/api.c const struct crypto_type *frontend, u32 type, u32 mask) mask 533 crypto/api.c alg = crypto_find_alg(alg_name, frontend, type, mask); mask 584 crypto/api.c int crypto_has_alg(const char *name, u32 type, u32 mask) mask 587 crypto/api.c struct crypto_alg *alg = crypto_alg_mod_lookup(name, type, mask); mask 398 crypto/authenc.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 403 crypto/authenc.c crypto_requires_sync(algt->type, algt->mask)); mask 429 crypto/authenc.c algt->mask)); mask 416 crypto/authencesn.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 421 crypto/authencesn.c crypto_requires_sync(algt->type, algt->mask)); mask 447 crypto/authencesn.c algt->mask)); mask 440 crypto/blkcipher.c u32 mask) mask 445 crypto/blkcipher.c if ((mask & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_MASK && mask 487 crypto/blkcipher.c static int crypto_init_blkcipher_ops(struct crypto_tfm *tfm, u32 type, u32 mask) mask 494 crypto/blkcipher.c if ((mask & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_MASK) mask 471 crypto/ccm.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 501 crypto/ccm.c algt->mask)); mask 758 crypto/ccm.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 772 crypto/ccm.c crypto_requires_sync(algt->type, algt->mask)); mask 581 crypto/chacha20poly1305.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 595 crypto/chacha20poly1305.c algt->mask)); mask 619 crypto/chacha20poly1305.c algt->mask)); mask 195 crypto/cryptd.c u32 *mask) mask 204 crypto/cryptd.c *mask |= algt->mask & CRYPTO_ALG_INTERNAL; mask 405 crypto/cryptd.c u32 mask; mask 409 crypto/cryptd.c mask = CRYPTO_ALG_ASYNC; mask 411 crypto/cryptd.c cryptd_check_internal(tb, &type, &mask); mask 425 crypto/cryptd.c err = crypto_grab_skcipher(&ctx->spawn, name, type, mask); mask 677 crypto/cryptd.c u32 mask = 0; mask 680 crypto/cryptd.c cryptd_check_internal(tb, &type, &mask); mask 682 crypto/cryptd.c salg = shash_attr_alg(tb[1], type, mask); mask 861 crypto/cryptd.c u32 mask = CRYPTO_ALG_ASYNC; mask 864 crypto/cryptd.c cryptd_check_internal(tb, &type, &mask); mask 878 crypto/cryptd.c err = crypto_grab_aead(&ctx->aead_spawn, name, type, mask); mask 921 crypto/cryptd.c switch (algt->type & algt->mask & CRYPTO_ALG_TYPE_MASK) { mask 962 crypto/cryptd.c u32 type, u32 mask) mask 972 crypto/cryptd.c tfm = crypto_alloc_skcipher(cryptd_alg_name, type, mask); mask 1014 crypto/cryptd.c u32 type, u32 mask) mask 1023 crypto/cryptd.c tfm = crypto_alloc_ahash(cryptd_alg_name, type, mask); mask 1071 crypto/cryptd.c u32 type, u32 mask) mask 1080 crypto/cryptd.c tfm = crypto_alloc_aead(cryptd_alg_name, type, mask); mask 270 crypto/ctr.c u32 mask; mask 278 crypto/ctr.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 289 crypto/ctr.c mask = crypto_requires_sync(algt->type, algt->mask) | mask 290 crypto/ctr.c crypto_requires_off(algt->type, algt->mask, mask 296 crypto/ctr.c err = crypto_grab_skcipher(spawn, cipher_name, 0, mask); mask 341 crypto/cts.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 357 crypto/cts.c algt->mask)); mask 486 crypto/essiv.c type = algt->type & algt->mask; mask 503 crypto/essiv.c algt->mask)); mask 525 crypto/essiv.c algt->mask)); mask 599 crypto/gcm.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 606 crypto/gcm.c algt->mask)); mask 631 crypto/gcm.c algt->mask)); mask 880 crypto/gcm.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 894 crypto/gcm.c crypto_requires_sync(algt->type, algt->mask)); mask 1117 crypto/gcm.c if ((algt->type ^ CRYPTO_ALG_TYPE_AEAD) & algt->mask) mask 1132 crypto/gcm.c crypto_requires_sync(algt->type, algt->mask)); mask 31 crypto/internal.h u32 mask; mask 59 crypto/internal.h struct crypto_alg *crypto_alg_mod_lookup(const char *name, u32 type, u32 mask); mask 64 crypto/internal.h struct crypto_larval *crypto_larval_alloc(const char *name, u32 type, u32 mask); mask 72 crypto/internal.h u32 mask); mask 77 crypto/internal.h u32 type, u32 mask); mask 79 crypto/internal.h const struct crypto_type *frontend, u32 type, u32 mask); mask 86 crypto/internal.h u32 type, u32 mask); mask 131 crypto/jitterentropy.c unsigned int mask = (1<<bits) - 1; mask 145 crypto/jitterentropy.c shuffle ^= time & mask; mask 84 crypto/kpp.c struct crypto_kpp *crypto_alloc_kpp(const char *alg_name, u32 type, u32 mask) mask 86 crypto/kpp.c return crypto_alloc_tfm(alg_name, &crypto_kpp_type, type, mask); mask 312 crypto/lrw.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 328 crypto/lrw.c algt->mask)); mask 337 crypto/lrw.c algt->mask)); mask 230 crypto/pcrypt.c u32 type, u32 mask) mask 316 crypto/pcrypt.c switch (algt->type & algt->mask & CRYPTO_ALG_TYPE_MASK) { mask 318 crypto/pcrypt.c return pcrypt_create_aead(tmpl, tb, algt->type, algt->mask); mask 32 crypto/poly1305_generic.c static inline u32 and(u32 v, u32 mask) mask 34 crypto/poly1305_generic.c return v & mask; mask 220 crypto/poly1305_generic.c u32 mask; mask 243 crypto/poly1305_generic.c mask = (g4 >> ((sizeof(u32) * 8) - 1)) - 1; mask 244 crypto/poly1305_generic.c g0 &= mask; mask 245 crypto/poly1305_generic.c g1 &= mask; mask 246 crypto/poly1305_generic.c g2 &= mask; mask 247 crypto/poly1305_generic.c g3 &= mask; mask 248 crypto/poly1305_generic.c g4 &= mask; mask 249 crypto/poly1305_generic.c mask = ~mask; mask 250 crypto/poly1305_generic.c h0 = (h0 & mask) | g0; mask 251 crypto/poly1305_generic.c h1 = (h1 & mask) | g1; mask 252 crypto/poly1305_generic.c h2 = (h2 & mask) | g2; mask 253 crypto/poly1305_generic.c h3 = (h3 & mask) | g3; mask 254 crypto/poly1305_generic.c h4 = (h4 & mask) | g4; mask 114 crypto/rng.c struct crypto_rng *crypto_alloc_rng(const char *alg_name, u32 type, u32 mask) mask 116 crypto/rng.c return crypto_alloc_tfm(alg_name, &crypto_rng_type, type, mask); mask 613 crypto/rsa-pkcs1pad.c if ((algt->type ^ CRYPTO_ALG_TYPE_AKCIPHER) & algt->mask) mask 641 crypto/rsa-pkcs1pad.c crypto_requires_sync(algt->type, algt->mask)); mask 448 crypto/shash.c u32 mask) mask 450 crypto/shash.c return crypto_alloc_tfm(alg_name, &crypto_shash_type, type, mask); mask 569 crypto/shash.c struct shash_alg *shash_attr_alg(struct rtattr *rta, u32 type, u32 mask) mask 573 crypto/shash.c alg = crypto_attr_alg2(rta, &crypto_shash_type, type, mask); mask 982 crypto/skcipher.c const char *name, u32 type, u32 mask) mask 985 crypto/skcipher.c return crypto_grab_spawn(&spawn->base, name, type, mask); mask 990 crypto/skcipher.c u32 type, u32 mask) mask 992 crypto/skcipher.c return crypto_alloc_tfm(alg_name, &crypto_skcipher_type2, type, mask); mask 997 crypto/skcipher.c const char *alg_name, u32 type, u32 mask) mask 1002 crypto/skcipher.c mask |= CRYPTO_ALG_ASYNC; mask 1004 crypto/skcipher.c tfm = crypto_alloc_tfm(alg_name, &crypto_skcipher_type2, type, mask); mask 1020 crypto/skcipher.c int crypto_has_skcipher2(const char *alg_name, u32 type, u32 mask) mask 1023 crypto/skcipher.c type, mask); mask 1177 crypto/skcipher.c u32 mask; mask 1184 crypto/skcipher.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 1187 crypto/skcipher.c mask = CRYPTO_ALG_TYPE_MASK | mask 1188 crypto/skcipher.c crypto_requires_off(algt->type, algt->mask, mask 1191 crypto/skcipher.c cipher_alg = crypto_get_attr_alg(tb, CRYPTO_ALG_TYPE_CIPHER, mask); mask 63 crypto/tcrypt.c static u32 mask; mask 1055 crypto/tcrypt.c struct hash_speed *speed, unsigned mask) mask 1064 crypto/tcrypt.c tfm = crypto_alloc_ahash(algo, 0, mask); mask 1660 crypto/tcrypt.c static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) mask 1669 crypto/tcrypt.c mask ?: CRYPTO_ALG_TYPE_MASK)) mask 3035 crypto/tcrypt.c err = do_test(alg, type, mask, mode, num_mb); mask 3072 crypto/tcrypt.c module_param(mask, uint, 0); mask 62 crypto/testmgr.c int alg_test(const char *driver, const char *alg, u32 type, u32 mask) mask 128 crypto/testmgr.c u32 type, u32 mask); mask 1675 crypto/testmgr.c static int alloc_shash(const char *driver, u32 type, u32 mask, mask 1682 crypto/testmgr.c tfm = crypto_alloc_shash(driver, type, mask); mask 1710 crypto/testmgr.c u32 type, u32 mask, mask 1728 crypto/testmgr.c atfm = crypto_alloc_ahash(driver, type, mask); mask 1747 crypto/testmgr.c err = alloc_shash(driver, type, mask, &stfm, &desc); mask 1795 crypto/testmgr.c u32 type, u32 mask) mask 1825 crypto/testmgr.c err = __alg_test_hash(template, nr_unkeyed, driver, type, mask, mask 1831 crypto/testmgr.c err = __alg_test_hash(template, nr_keyed, driver, type, mask, mask 2298 crypto/testmgr.c u32 type, u32 mask) mask 2311 crypto/testmgr.c tfm = crypto_alloc_aead(driver, type, mask); mask 2857 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 2870 crypto/testmgr.c tfm = crypto_alloc_skcipher(driver, type, mask); mask 3248 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 3254 crypto/testmgr.c tfm = crypto_alloc_cipher(driver, type, mask); mask 3270 crypto/testmgr.c u32 type, u32 mask) mask 3278 crypto/testmgr.c acomp = crypto_alloc_acomp(driver, type, mask); mask 3290 crypto/testmgr.c comp = crypto_alloc_comp(driver, type, mask); mask 3308 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 3314 crypto/testmgr.c err = alg_test_hash(desc, driver, type, mask); mask 3318 crypto/testmgr.c tfm = crypto_alloc_shash(driver, type, mask); mask 3360 crypto/testmgr.c u32 type, u32 mask) mask 3365 crypto/testmgr.c rng = crypto_alloc_rng(driver, type, mask); mask 3381 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 3392 crypto/testmgr.c drng = crypto_alloc_rng(driver, type, mask); mask 3449 crypto/testmgr.c u32 type, u32 mask) mask 3461 crypto/testmgr.c err = drbg_cavs_test(&template[i], pr, driver, type, mask); mask 3632 crypto/testmgr.c u32 type, u32 mask) mask 3637 crypto/testmgr.c tfm = crypto_alloc_kpp(driver, type, mask); mask 3852 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 3857 crypto/testmgr.c tfm = crypto_alloc_akcipher(driver, type, mask); mask 3872 crypto/testmgr.c const char *driver, u32 type, u32 mask) mask 5206 crypto/testmgr.c int alg_test(const char *driver, const char *alg, u32 type, u32 mask) mask 5233 crypto/testmgr.c rc = alg_test_cipher(alg_test_descs + i, driver, type, mask); mask 5249 crypto/testmgr.c type, mask); mask 5252 crypto/testmgr.c type, mask); mask 344 crypto/xts.c u32 mask; mask 351 crypto/xts.c if ((algt->type ^ CRYPTO_ALG_TYPE_SKCIPHER) & algt->mask) mask 366 crypto/xts.c mask = crypto_requires_off(algt->type, algt->mask, mask 370 crypto/xts.c err = crypto_grab_skcipher(&ctx->spawn, cipher_name, 0, mask); mask 377 crypto/xts.c err = crypto_grab_skcipher(&ctx->spawn, ctx->name, 0, mask); mask 43 drivers/acpi/acpi_lpit.c u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset + mask 47 drivers/acpi/acpi_lpit.c *counter &= mask; mask 135 drivers/acpi/acpica/acinterp.h u64 mask, mask 319 drivers/acpi/acpica/acmacros.h #define ACPI_REGISTER_PREPARE_BITS(val, pos, mask) \ mask 320 drivers/acpi/acpica/acmacros.h ((val << pos) & mask) mask 322 drivers/acpi/acpica/acmacros.h #define ACPI_REGISTER_INSERT_VALUE(reg, pos, mask, val) \ mask 323 drivers/acpi/acpica/acmacros.h reg = (reg & (~(mask))) | ACPI_REGISTER_PREPARE_BITS(val, pos, mask) mask 325 drivers/acpi/acpica/acmacros.h #define ACPI_INSERT_BITS(target, mask, source) \ mask 326 drivers/acpi/acpica/acmacros.h target = ((target & (~(mask))) | (source & mask)) mask 330 drivers/acpi/acpica/acmacros.h #define ACPI_GET_BITS(source_ptr, position, mask) \ mask 331 drivers/acpi/acpica/acmacros.h ((*(source_ptr) >> (position)) & (mask)) mask 333 drivers/acpi/acpica/acmacros.h #define ACPI_SET_BITS(target_ptr, position, mask, value) \ mask 334 drivers/acpi/acpica/acmacros.h (*(target_ptr) |= (((value) & (mask)) << (position))) mask 246 drivers/acpi/acpica/acresrc.h u8 acpi_rs_decode_bitmask(u16 mask, u8 * list); mask 545 drivers/acpi/acpica/exfldio.c u64 mask, mask 552 drivers/acpi/acpica/exfldio.c ACPI_FUNCTION_TRACE_U32(ex_write_with_update_rule, mask); mask 560 drivers/acpi/acpica/exfldio.c if (mask != ACPI_UINT64_MAX) { mask 571 drivers/acpi/acpica/exfldio.c if ((~mask << (ACPI_MUL_8(sizeof(mask)) - mask 587 drivers/acpi/acpica/exfldio.c merged_value |= (current_value & ~mask); mask 595 drivers/acpi/acpica/exfldio.c merged_value |= ~mask; mask 602 drivers/acpi/acpica/exfldio.c merged_value &= mask; mask 618 drivers/acpi/acpica/exfldio.c ACPI_FORMAT_UINT64(mask), mask 811 drivers/acpi/acpica/exfldio.c u64 mask; mask 869 drivers/acpi/acpica/exfldio.c mask = width_mask & mask 897 drivers/acpi/acpica/exfldio.c merged_datum &= mask; mask 899 drivers/acpi/acpica/exfldio.c acpi_ex_write_with_update_rule(obj_desc, mask, merged_datum, mask 927 drivers/acpi/acpica/exfldio.c mask = width_mask; mask 950 drivers/acpi/acpica/exfldio.c mask &= ACPI_MASK_BITS_ABOVE(buffer_tail_bits); mask 955 drivers/acpi/acpica/exfldio.c merged_datum &= mask; mask 957 drivers/acpi/acpica/exfldio.c acpi_ex_write_with_update_rule(obj_desc, mask, merged_datum, mask 28 drivers/acpi/acpica/rsutils.c u8 acpi_rs_decode_bitmask(u16 mask, u8 * list) mask 37 drivers/acpi/acpica/rsutils.c for (i = 0, bit_count = 0; mask; i++) { mask 38 drivers/acpi/acpica/rsutils.c if (mask & 0x0001) { mask 43 drivers/acpi/acpica/rsutils.c mask >>= 1; mask 65 drivers/acpi/acpica/rsutils.c u16 mask; mask 71 drivers/acpi/acpica/rsutils.c for (i = 0, mask = 0; i < count; i++) { mask 72 drivers/acpi/acpica/rsutils.c mask |= (0x1 << list[i]); mask 75 drivers/acpi/acpica/rsutils.c return (mask); mask 65 drivers/acpi/apei/apei-base.c *val &= entry->mask; mask 103 drivers/acpi/apei/apei-base.c val &= entry->mask; mask 110 drivers/acpi/apei/apei-base.c valr &= ~(entry->mask << entry->register_region.bit_offset); mask 1060 drivers/acpi/arm64/iort.c u64 mask, dmaaddr = 0, size = 0, offset = 0; mask 1095 drivers/acpi/arm64/iort.c mask = msb == 64 ? U64_MAX : (1ULL << msb) - 1; mask 1100 drivers/acpi/arm64/iort.c dev->bus_dma_mask = mask; mask 1101 drivers/acpi/arm64/iort.c dev->coherent_dma_mask = mask; mask 1102 drivers/acpi/arm64/iort.c *dev->dma_mask = mask; mask 917 drivers/acpi/nfit/core.c u32 mask; mask 919 drivers/acpi/nfit/core.c mask = (1 << (pcap->highest_capability + 1)) - 1; mask 920 drivers/acpi/nfit/core.c acpi_desc->platform_cap = pcap->capabilities & mask; mask 1377 drivers/acpi/nfit/core.c const unsigned long mask = 1 << ND_CMD_ARS_CAP | 1 << ND_CMD_ARS_START mask 1380 drivers/acpi/nfit/core.c return (nd_desc->cmd_mask & mask) == mask; mask 356 drivers/acpi/pci_root.c acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req) mask 362 drivers/acpi/pci_root.c if (!mask) mask 365 drivers/acpi/pci_root.c ctrl = *mask & OSC_PCI_CONTROL_MASKS; mask 375 drivers/acpi/pci_root.c *mask = ctrl | root->osc_control_set; mask 381 drivers/acpi/pci_root.c while (*mask) { mask 382 drivers/acpi/pci_root.c status = acpi_pci_query_osc(root, root->osc_support_set, mask); mask 385 drivers/acpi/pci_root.c if (ctrl == *mask) mask 388 drivers/acpi/pci_root.c ctrl & ~(*mask)); mask 389 drivers/acpi/pci_root.c ctrl = *mask; mask 402 drivers/acpi/pci_root.c status = acpi_pci_run_osc(handle, capbuf, mask); mask 404 drivers/acpi/pci_root.c root->osc_control_set = *mask; mask 334 drivers/acpi/pmic/intel_pmic.c u32 value, u32 mask) mask 351 drivers/acpi/pmic/intel_pmic.c value, mask); mask 355 drivers/acpi/pmic/intel_pmic.c reg_address, mask, value); mask 358 drivers/acpi/pmic/intel_pmic.c __func__, i2c_address, reg_address, value, mask); mask 364 drivers/acpi/pmic/intel_pmic.c __func__, i2c_address, reg_address, value, mask); mask 19 drivers/acpi/pmic/intel_pmic.h u32 reg_address, u32 value, u32 mask); mask 288 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 val, mask = bit; mask 295 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); mask 353 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 mask = BIT(bit); mask 359 drivers/acpi/pmic/intel_pmic_bxtwc.c *value = (val & mask) >> bit; mask 367 drivers/acpi/pmic/intel_pmic_bxtwc.c u8 mask = BIT(bit), val = enable << bit; mask 369 drivers/acpi/pmic/intel_pmic_bxtwc.c return regmap_update_bits(regmap, reg, mask, val); mask 237 drivers/acpi/pmic/intel_pmic_chtwc.c u32 value, u32 mask) mask 249 drivers/acpi/pmic/intel_pmic_chtwc.c return regmap_update_bits(regmap, address, mask, value); mask 668 drivers/acpi/utils.c u64 mask = 0; mask 680 drivers/acpi/utils.c mask = obj->integer.value; mask 683 drivers/acpi/utils.c mask |= (((u64)obj->buffer.pointer[i]) << (i * 8)); mask 690 drivers/acpi/utils.c if ((mask & 0x1) && (mask & funcs) == funcs) mask 49 drivers/amba/bus.c while (table->mask) { mask 50 drivers/amba/bus.c if (((dev->periphid & table->mask) == table->id) && mask 726 drivers/amba/bus.c unsigned int mask; mask 735 drivers/amba/bus.c r = (pcdev->periphid & d->mask) == d->id; mask 765 drivers/amba/bus.c unsigned int mask) mask 773 drivers/amba/bus.c data.mask = mask; mask 142 drivers/android/binder.c #define binder_debug(mask, x...) \ mask 144 drivers/android/binder.c if (binder_debug_mask & mask) \ mask 44 drivers/android/binder_alloc.c #define binder_alloc_debug(mask, x...) \ mask 46 drivers/android/binder_alloc.c if (binder_alloc_debug_mask & mask) \ mask 81 drivers/ata/ahci_sunxi.c static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift) mask 83 drivers/ata/ahci_sunxi.c return (readl(reg) >> shift) & mask; mask 141 drivers/ata/ata_piix.c const u32 mask; mask 339 drivers/ata/ata_piix.c .mask = 0x7, mask 355 drivers/ata/ata_piix.c .mask = 0x3, mask 367 drivers/ata/ata_piix.c .mask = 0x3, mask 384 drivers/ata/ata_piix.c .mask = 0x3, mask 396 drivers/ata/ata_piix.c .mask = 0x3, mask 408 drivers/ata/ata_piix.c .mask = 0x3, mask 420 drivers/ata/ata_piix.c .mask = 0x3, mask 510 drivers/ata/ata_piix.c u8 mask; mask 523 drivers/ata/ata_piix.c mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; mask 524 drivers/ata/ata_piix.c if ((hpriv->saved_iocfg & mask) == 0) mask 1366 drivers/ata/ata_piix.c map = map_db->map[map_value & map_db->mask]; mask 3040 drivers/ata/libata-core.c u32 sstatus, spd, mask; mask 3055 drivers/ata/libata-core.c mask = link->sata_spd_limit; mask 3056 drivers/ata/libata-core.c if (mask <= 1) mask 3060 drivers/ata/libata-core.c bit = fls(mask) - 1; mask 3061 drivers/ata/libata-core.c mask &= ~(1 << bit); mask 3073 drivers/ata/libata-core.c mask &= (1 << (spd - 1)) - 1; mask 3078 drivers/ata/libata-core.c if (!mask) mask 3082 drivers/ata/libata-core.c if (mask & ((1 << spd_limit) - 1)) mask 3083 drivers/ata/libata-core.c mask &= (1 << spd_limit) - 1; mask 3085 drivers/ata/libata-core.c bit = ffs(mask) - 1; mask 3086 drivers/ata/libata-core.c mask = 1 << bit; mask 3090 drivers/ata/libata-core.c link->sata_spd_limit = mask; mask 3093 drivers/ata/libata-core.c sata_spd_string(fls(mask))); mask 6814 drivers/ata/libata-core.c tmp &= bits->mask; mask 7175 drivers/ata/libata-core.c u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val, mask 7189 drivers/ata/libata-core.c while ((tmp & mask) == val && time_before(jiffies, deadline)) { mask 2230 drivers/ata/libata-sff.c unsigned int mask = 0; mask 2274 drivers/ata/libata-sff.c mask |= 1 << i; mask 2277 drivers/ata/libata-sff.c if (!mask) { mask 2362 drivers/ata/libata-sff.c u8 tmp8, mask = 0; mask 2374 drivers/ata/libata-sff.c mask |= (1 << 0); mask 2376 drivers/ata/libata-sff.c mask |= (1 << 2); mask 2377 drivers/ata/libata-sff.c if ((tmp8 & mask) != mask) mask 26 drivers/ata/pata_acpi.c unsigned long mask[2]; mask 58 drivers/ata/pata_acpi.c if ((acpi->mask[0] | acpi->mask[1]) & (0xF8 << ATA_SHIFT_UDMA)) mask 100 drivers/ata/pata_acpi.c static unsigned long pacpi_mode_filter(struct ata_device *adev, unsigned long mask) mask 103 drivers/ata/pata_acpi.c return mask & acpi->mask[adev->devno]; mask 203 drivers/ata/pata_acpi.c acpi->mask[0] = pacpi_discover_modes(ap, &ap->link.device[0]); mask 204 drivers/ata/pata_acpi.c acpi->mask[1] = pacpi_discover_modes(ap, &ap->link.device[1]); mask 118 drivers/ata/pata_ali.c static unsigned long ali_20_filter(struct ata_device *adev, unsigned long mask) mask 123 drivers/ata/pata_ali.c mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); mask 126 drivers/ata/pata_ali.c return mask &= ~ATA_MASK_UDMA; mask 127 drivers/ata/pata_ali.c return mask; mask 211 drivers/ata/pata_arasan_cf.c dma_cap_mask_t mask; mask 254 drivers/ata/pata_arasan_cf.c cf_interrupt_enable(struct arasan_cf_dev *acdev, u32 mask, bool enable) mask 259 drivers/ata/pata_arasan_cf.c writel(mask, acdev->vbase + IRQ_STS); mask 260 drivers/ata/pata_arasan_cf.c writel(val | mask, acdev->vbase + IRQ_EN); mask 262 drivers/ata/pata_arasan_cf.c writel(val & ~mask, acdev->vbase + IRQ_EN); mask 860 drivers/ata/pata_arasan_cf.c dma_cap_set(DMA_MEMCPY, acdev->mask); mask 409 drivers/ata/pata_atp867x.c unsigned int mask = 0; mask 456 drivers/ata/pata_atp867x.c mask |= 1 << i; mask 459 drivers/ata/pata_atp867x.c if (!mask) { mask 651 drivers/ata/pata_ep93xx.c dma_cap_mask_t mask; mask 654 drivers/ata/pata_ep93xx.c dma_cap_zero(mask); mask 655 drivers/ata/pata_ep93xx.c dma_cap_set(DMA_SLAVE, mask); mask 665 drivers/ata/pata_ep93xx.c drv_data->dma_rx_channel = dma_request_channel(mask, mask 673 drivers/ata/pata_ep93xx.c drv_data->dma_tx_channel = dma_request_channel(mask, mask 199 drivers/ata/pata_hpt366.c static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) mask 203 drivers/ata/pata_hpt366.c mask &= ~ATA_MASK_UDMA; mask 205 drivers/ata/pata_hpt366.c mask &= ~(0xF8 << ATA_SHIFT_UDMA); mask 207 drivers/ata/pata_hpt366.c mask &= ~(0xF0 << ATA_SHIFT_UDMA); mask 209 drivers/ata/pata_hpt366.c mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); mask 211 drivers/ata/pata_hpt366.c return mask; mask 234 drivers/ata/pata_hpt366.c u32 mask, reg, t; mask 238 drivers/ata/pata_hpt366.c mask = 0xc1f8ffff; mask 240 drivers/ata/pata_hpt366.c mask = 0x303800ff; mask 242 drivers/ata/pata_hpt366.c mask = 0x30070000; mask 252 drivers/ata/pata_hpt366.c reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000; mask 282 drivers/ata/pata_hpt37x.c static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) mask 286 drivers/ata/pata_hpt37x.c mask &= ~ATA_MASK_UDMA; mask 288 drivers/ata/pata_hpt37x.c mask &= ~(0xE0 << ATA_SHIFT_UDMA); mask 290 drivers/ata/pata_hpt37x.c return mask; mask 300 drivers/ata/pata_hpt37x.c static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) mask 304 drivers/ata/pata_hpt37x.c mask &= ~(0xE0 << ATA_SHIFT_UDMA); mask 306 drivers/ata/pata_hpt37x.c return mask; mask 317 drivers/ata/pata_hpt37x.c static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) mask 320 drivers/ata/pata_hpt37x.c mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); mask 322 drivers/ata/pata_hpt37x.c return mask; mask 413 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; mask 427 drivers/ata/pata_hpt37x.c mask = 0xcfc3ffff; mask 429 drivers/ata/pata_hpt37x.c mask = 0x31c001ff; mask 431 drivers/ata/pata_hpt37x.c mask = 0x303c0000; mask 436 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); mask 507 drivers/ata/pata_hpt37x.c u32 reg, timing, mask; mask 520 drivers/ata/pata_hpt37x.c mask = 0xcfc3ffff; mask 522 drivers/ata/pata_hpt37x.c mask = 0x31c001ff; mask 524 drivers/ata/pata_hpt37x.c mask = 0x303c0000; mask 529 drivers/ata/pata_hpt37x.c reg = (reg & ~mask) | (timing & mask); mask 125 drivers/ata/pata_hpt3x2n.c static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) mask 128 drivers/ata/pata_hpt3x2n.c mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); mask 130 drivers/ata/pata_hpt3x2n.c return mask; mask 187 drivers/ata/pata_hpt3x2n.c u32 reg, timing, mask; mask 200 drivers/ata/pata_hpt3x2n.c mask = 0xcfc3ffff; mask 202 drivers/ata/pata_hpt3x2n.c mask = 0x31c001ff; mask 204 drivers/ata/pata_hpt3x2n.c mask = 0x303c0000; mask 209 drivers/ata/pata_hpt3x2n.c reg = (reg & ~mask) | (timing & mask); mask 860 drivers/ata/pata_legacy.c int mask = 1 << probe->slot; mask 875 drivers/ata/pata_legacy.c if (reg & mask) mask 910 drivers/ata/pata_legacy.c if (ht6560a & mask) mask 912 drivers/ata/pata_legacy.c if (ht6560b & mask) mask 914 drivers/ata/pata_legacy.c if (opti82c611a & mask) mask 916 drivers/ata/pata_legacy.c if (opti82c46x & mask) mask 918 drivers/ata/pata_legacy.c if (autospeed & mask) mask 937 drivers/ata/pata_legacy.c u32 mask = (1 << probe->slot); mask 945 drivers/ata/pata_legacy.c u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; mask 1016 drivers/ata/pata_macio.c unsigned int mask = 1U << (priv->timings[i].mode & 0x0f); mask 1019 drivers/ata/pata_macio.c pinfo->pio_mask |= (mask >> 8); mask 1022 drivers/ata/pata_macio.c pinfo->mwdma_mask |= mask; mask 1025 drivers/ata/pata_macio.c pinfo->udma_mask |= mask; mask 67 drivers/ata/pata_pdc2027x.c static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); mask 261 drivers/ata/pata_pdc2027x.c static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) mask 267 drivers/ata/pata_pdc2027x.c return mask; mask 274 drivers/ata/pata_pdc2027x.c mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); mask 276 drivers/ata/pata_pdc2027x.c return mask; mask 43 drivers/ata/pata_rdc.c u8 mask; mask 46 drivers/ata/pata_rdc.c mask = 0x30 << (2 * ap->port_no); mask 47 drivers/ata/pata_rdc.c if ((hpriv->saved_iocfg & mask) == 0) mask 153 drivers/ata/pata_serverworks.c static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) mask 156 drivers/ata/pata_serverworks.c mask &= ~ATA_MASK_UDMA; mask 157 drivers/ata/pata_serverworks.c return mask; mask 169 drivers/ata/pata_serverworks.c static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) mask 177 drivers/ata/pata_serverworks.c return mask; mask 184 drivers/ata/pata_serverworks.c mask &= ~(0xE0 << ATA_SHIFT_UDMA); mask 186 drivers/ata/pata_serverworks.c return mask; mask 199 drivers/ata/pata_sis.c u8 mask = 0x11; mask 201 drivers/ata/pata_sis.c mask <<= (2 * ap->port_no); mask 202 drivers/ata/pata_sis.c mask <<= adev->devno; mask 206 drivers/ata/pata_sis.c fifoctrl &= ~mask; mask 210 drivers/ata/pata_sis.c fifoctrl |= mask; mask 528 drivers/ata/pata_sis.c static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask) mask 538 drivers/ata/pata_sis.c mask &= ~(0xC0 << ATA_SHIFT_UDMA); mask 539 drivers/ata/pata_sis.c return mask; mask 234 drivers/ata/pata_sl82c105.c u32 val, mask = ap->port_no ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; mask 238 drivers/ata/pata_sl82c105.c return val & mask; mask 355 drivers/ata/pata_via.c static unsigned long via_mode_filter(struct ata_device *dev, unsigned long mask) mask 366 drivers/ata/pata_via.c mask &= ~ ATA_MASK_UDMA; mask 373 drivers/ata/pata_via.c mask &= ATA_MASK_PIO; mask 376 drivers/ata/pata_via.c return mask; mask 218 drivers/ata/sata_dwc_460ex.c dma_cap_mask_t mask; mask 222 drivers/ata/sata_dwc_460ex.c dma_cap_zero(mask); mask 223 drivers/ata/sata_dwc_460ex.c dma_cap_set(DMA_SLAVE, mask); mask 226 drivers/ata/sata_dwc_460ex.c hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp); mask 787 drivers/ata/sata_dwc_460ex.c u32 mask = 0x0; mask 803 drivers/ata/sata_dwc_460ex.c mask = (~(qcmd_tag_to_mask(tag))); mask 804 drivers/ata/sata_dwc_460ex.c hsdev->sactive_queued = hsdev->sactive_queued & mask; mask 805 drivers/ata/sata_dwc_460ex.c hsdev->sactive_issued = hsdev->sactive_issued & mask; mask 1019 drivers/ata/sata_mv.c static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) mask 1029 drivers/ata/sata_mv.c if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) mask 1030 drivers/ata/sata_mv.c mask &= ~DONE_IRQ_0_3; mask 1031 drivers/ata/sata_mv.c if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) mask 1032 drivers/ata/sata_mv.c mask &= ~DONE_IRQ_4_7; mask 1033 drivers/ata/sata_mv.c writelfl(mask, hpriv->main_irq_mask_addr); mask 3131 drivers/ata/sata_mv.c const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); mask 3147 drivers/ata/sata_mv.c tmp &= ~mask; mask 1562 drivers/ata/sata_nv.c u8 mask; mask 1564 drivers/ata/sata_nv.c mask = ioread8(scr_addr + NV_INT_ENABLE); mask 1565 drivers/ata/sata_nv.c mask &= ~(NV_INT_ALL << shift); mask 1566 drivers/ata/sata_nv.c iowrite8(mask, scr_addr + NV_INT_ENABLE); mask 1573 drivers/ata/sata_nv.c u8 mask; mask 1577 drivers/ata/sata_nv.c mask = ioread8(scr_addr + NV_INT_ENABLE); mask 1578 drivers/ata/sata_nv.c mask |= (NV_INT_MASK << shift); mask 1579 drivers/ata/sata_nv.c iowrite8(mask, scr_addr + NV_INT_ENABLE); mask 1586 drivers/ata/sata_nv.c u8 mask; mask 1588 drivers/ata/sata_nv.c mask = readb(mmio_base + NV_INT_ENABLE_CK804); mask 1589 drivers/ata/sata_nv.c mask &= ~(NV_INT_ALL << shift); mask 1590 drivers/ata/sata_nv.c writeb(mask, mmio_base + NV_INT_ENABLE_CK804); mask 1597 drivers/ata/sata_nv.c u8 mask; mask 1601 drivers/ata/sata_nv.c mask = readb(mmio_base + NV_INT_ENABLE_CK804); mask 1602 drivers/ata/sata_nv.c mask |= (NV_INT_MASK << shift); mask 1603 drivers/ata/sata_nv.c writeb(mask, mmio_base + NV_INT_ENABLE_CK804); mask 1610 drivers/ata/sata_nv.c u32 mask; mask 1614 drivers/ata/sata_nv.c mask = readl(mmio_base + NV_INT_ENABLE_MCP55); mask 1615 drivers/ata/sata_nv.c mask &= ~(NV_INT_ALL_MCP55 << shift); mask 1616 drivers/ata/sata_nv.c writel(mask, mmio_base + NV_INT_ENABLE_MCP55); mask 1623 drivers/ata/sata_nv.c u32 mask; mask 1627 drivers/ata/sata_nv.c mask = readl(mmio_base + NV_INT_ENABLE_MCP55); mask 1628 drivers/ata/sata_nv.c mask |= (NV_INT_MASK_MCP55 << shift); mask 1629 drivers/ata/sata_nv.c writel(mask, mmio_base + NV_INT_ENABLE_MCP55); mask 672 drivers/ata/sata_promise.c const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; mask 673 drivers/ata/sata_promise.c return (flags & mask) == mask; mask 921 drivers/ata/sata_promise.c u32 mask = 0; mask 951 drivers/ata/sata_promise.c mask = readl(host_mmio + PDC_INT_SEQMASK); mask 953 drivers/ata/sata_promise.c if (mask == 0xffffffff && hotplug_status == 0) { mask 958 drivers/ata/sata_promise.c mask &= 0xffff; /* only 16 SEQIDs possible */ mask 959 drivers/ata/sata_promise.c if (mask == 0 && hotplug_status == 0) { mask 964 drivers/ata/sata_promise.c writel(mask, host_mmio + PDC_INT_SEQMASK); mask 986 drivers/ata/sata_promise.c tmp = mask & (1 << (i + 1)); mask 777 drivers/ata/sata_sx4.c u32 mask = 0; mask 793 drivers/ata/sata_sx4.c mask = readl(mmio_base + PDC_20621_SEQMASK); mask 794 drivers/ata/sata_sx4.c VPRINTK("mask == 0x%x\n", mask); mask 796 drivers/ata/sata_sx4.c if (mask == 0xffffffff) { mask 800 drivers/ata/sata_sx4.c mask &= 0xffff; /* only 16 tags possible */ mask 801 drivers/ata/sata_sx4.c if (!mask) { mask 816 drivers/ata/sata_sx4.c tmp = mask & (1 << i); mask 830 drivers/ata/sata_sx4.c VPRINTK("mask == 0x%x\n", mask); mask 129 drivers/ata/sata_vsc.c u8 mask; mask 133 drivers/ata/sata_vsc.c mask = readb(mask_addr); mask 135 drivers/ata/sata_vsc.c mask |= 0x80; mask 137 drivers/ata/sata_vsc.c mask &= 0x7F; mask 138 drivers/ata/sata_vsc.c writeb(mask, mask_addr); mask 1755 drivers/atm/fore200e.c opcode.mask = 0; mask 1780 drivers/atm/fore200e.c fore200e_set_oc3(struct fore200e* fore200e, u32 reg, u32 value, u32 mask) mask 1787 drivers/atm/fore200e.c DPRINTK(2, "set OC-3 reg = 0x%02x, value = 0x%02x, mask = 0x%02x\n", reg, value, mask); mask 1794 drivers/atm/fore200e.c opcode.mask = mask; mask 334 drivers/atm/fore200e.h u32 mask : 8 /* register mask that specifies which mask 94 drivers/atm/he.h #define NEXT_ENTRY(base, tail, mask) \ mask 95 drivers/atm/he.h (((unsigned long)base)|(((unsigned long)(tail+1))&mask)) mask 43 drivers/atm/suni.c #define REG_CHANGE(mask,shift,value,reg) \ mask 44 drivers/atm/suni.c PUT((GET(reg) & ~(mask)) | ((value) << (shift)),reg) mask 143 drivers/auxdisplay/panel.c __u64 mask; mask 1238 drivers/auxdisplay/panel.c if (((phys_prev & input->mask) == input->value) && mask 1239 drivers/auxdisplay/panel.c ((phys_curr & input->mask) > input->value)) { mask 1245 drivers/auxdisplay/panel.c if ((phys_curr & input->mask) == input->value) { mask 1295 drivers/auxdisplay/panel.c if (((phys_prev & input->mask) == input->value) && mask 1296 drivers/auxdisplay/panel.c ((phys_curr & input->mask) > input->value)) { mask 1302 drivers/auxdisplay/panel.c if ((phys_curr & input->mask) == input->value) { mask 1357 drivers/auxdisplay/panel.c if ((phys_curr & input->mask) != input->value) mask 1366 drivers/auxdisplay/panel.c if ((phys_prev & input->mask) == input->value) mask 1372 drivers/auxdisplay/panel.c if ((phys_curr & input->mask) != input->value) { mask 1429 drivers/auxdisplay/panel.c static u8 input_name2mask(const char *name, __u64 *mask, __u64 *value, mask 1470 drivers/auxdisplay/panel.c *mask = m; mask 1493 drivers/auxdisplay/panel.c if (!input_name2mask(name, &key->mask, &key->value, &scan_mask_i, mask 1532 drivers/auxdisplay/panel.c if (!input_name2mask(name, &callback->mask, &callback->value, mask 386 drivers/base/cacheinfo.c const struct cpumask *mask = &this_leaf->shared_cpu_map; mask 388 drivers/base/cacheinfo.c return cpumap_print_to_pagebuf(list, buf, mask); mask 485 drivers/base/cacheinfo.c const struct cpumask *mask = &this_leaf->shared_cpu_map; mask 494 drivers/base/cacheinfo.c if ((attr == &dev_attr_shared_cpu_map.attr) && !cpumask_empty(mask)) mask 496 drivers/base/cacheinfo.c if ((attr == &dev_attr_shared_cpu_list.attr) && !cpumask_empty(mask)) mask 33 drivers/base/node.c cpumask_var_t mask; mask 39 drivers/base/node.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 42 drivers/base/node.c cpumask_and(mask, cpumask_of_node(node_dev->dev.id), cpu_online_mask); mask 43 drivers/base/node.c n = cpumap_print_to_pagebuf(list, buf, mask); mask 44 drivers/base/node.c free_cpumask_var(mask); mask 52 drivers/base/power/qos.c enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, s32 mask) mask 67 drivers/base/power/qos.c val = pqf->effective_flags & mask; mask 69 drivers/base/power/qos.c return (val == mask) ? PM_QOS_FLAGS_ALL : PM_QOS_FLAGS_SOME; mask 79 drivers/base/power/qos.c enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, s32 mask) mask 85 drivers/base/power/qos.c ret = __dev_pm_qos_flags(dev, mask); mask 794 drivers/base/power/qos.c int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set) mask 809 drivers/base/power/qos.c value |= mask; mask 811 drivers/base/power/qos.c value &= ~mask; mask 106 drivers/base/regmap/internal.h unsigned int mask, unsigned int val); mask 209 drivers/base/regmap/internal.h unsigned int mask; mask 63 drivers/base/regmap/regmap-irq.c unsigned int reg, unsigned int mask, mask 67 drivers/base/regmap/regmap-irq.c return regmap_write_bits(d->map, reg, mask, val); mask 69 drivers/base/regmap/regmap-irq.c return regmap_update_bits(d->map, reg, mask, val); mask 217 drivers/base/regmap/regmap-irq.c unsigned int mask, type; mask 233 drivers/base/regmap/regmap-irq.c mask = d->type_buf[irq_data->reg_offset / map->reg_stride]; mask 235 drivers/base/regmap/regmap-irq.c mask = irq_data->mask; mask 240 drivers/base/regmap/regmap-irq.c d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask; mask 249 drivers/base/regmap/regmap-irq.c d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; mask 308 drivers/base/regmap/regmap-irq.c &= ~irq_data->mask; mask 313 drivers/base/regmap/regmap-irq.c |= irq_data->mask; mask 505 drivers/base/regmap/regmap-irq.c map->reg_stride] & chip->irqs[i].mask) { mask 671 drivers/base/regmap/regmap-irq.c |= chip->irqs[i].mask; mask 834 drivers/base/regmap/regmap-irq.c if (!d->chip->irqs[hwirq].mask) mask 968 drivers/base/regmap/regmap-irq.c if (!data->chip->irqs[irq].mask) mask 45 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, mask 1211 drivers/base/regmap/regmap.c rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb); mask 1463 drivers/base/regmap/regmap.c unsigned long mask) mask 1468 drivers/base/regmap/regmap.c if (!mask || !map->work_buf) mask 1474 drivers/base/regmap/regmap.c buf[i] |= (mask >> (8 * i)) & 0xff; mask 2007 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, mask 2010 drivers/base/regmap/regmap.c mask = (mask << field->shift) & field->mask; mask 2013 drivers/base/regmap/regmap.c mask, val << field->shift, mask 2034 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, mask 2040 drivers/base/regmap/regmap.c mask = (mask << field->shift) & field->mask; mask 2044 drivers/base/regmap/regmap.c mask, val << field->shift, mask 2747 drivers/base/regmap/regmap.c reg_val &= field->mask; mask 2780 drivers/base/regmap/regmap.c reg_val &= field->mask; mask 2866 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, mask 2876 drivers/base/regmap/regmap.c ret = map->reg_update_bits(map->bus_context, reg, mask, val); mask 2884 drivers/base/regmap/regmap.c tmp = orig & ~mask; mask 2885 drivers/base/regmap/regmap.c tmp |= val & mask; mask 2920 drivers/base/regmap/regmap.c unsigned int mask, unsigned int val, mask 2929 drivers/base/regmap/regmap.c ret = _regmap_update_bits(map, reg, mask, val, change, force); mask 24 drivers/base/topology.c #define define_siblings_show_map(name, mask) \ mask 28 drivers/base/topology.c return cpumap_print_to_pagebuf(false, buf, topology_##mask(dev->id));\ mask 31 drivers/base/topology.c #define define_siblings_show_list(name, mask) \ mask 36 drivers/base/topology.c return cpumap_print_to_pagebuf(true, buf, topology_##mask(dev->id));\ mask 39 drivers/base/topology.c #define define_siblings_show_func(name, mask) \ mask 40 drivers/base/topology.c define_siblings_show_map(name, mask); \ mask 41 drivers/base/topology.c define_siblings_show_list(name, mask) mask 24 drivers/bcma/bcma_private.h bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, mask 12 drivers/bcma/core.c static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask, mask 20 drivers/bcma/core.c if ((val & mask) == value) mask 19 drivers/bcma/driver_chipcommon.c u32 mask, u32 value) mask 21 drivers/bcma/driver_chipcommon.c value &= mask; mask 22 drivers/bcma/driver_chipcommon.c value |= bcma_cc_read32(cc, offset) & ~mask; mask 264 drivers/bcma/driver_chipcommon.c void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 266 drivers/bcma/driver_chipcommon.c bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); mask 269 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) mask 271 drivers/bcma/driver_chipcommon.c return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; mask 274 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) mask 276 drivers/bcma/driver_chipcommon.c return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; mask 279 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 285 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); mask 292 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 298 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); mask 309 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 315 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); mask 322 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 328 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); mask 334 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 340 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); mask 346 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 355 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); mask 361 drivers/bcma/driver_chipcommon.c u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) mask 370 drivers/bcma/driver_chipcommon.c res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); mask 14 drivers/bcma/driver_chipcommon_b.c static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask, mask 22 drivers/bcma/driver_chipcommon_b.c if ((val & mask) == value) mask 32 drivers/bcma/driver_chipcommon_pmu.c void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, mask 37 drivers/bcma/driver_chipcommon_pmu.c bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set); mask 42 drivers/bcma/driver_chipcommon_pmu.c u32 offset, u32 mask, u32 set) mask 46 drivers/bcma/driver_chipcommon_pmu.c bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set); mask 50 drivers/bcma/driver_chipcommon_pmu.c void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, mask 55 drivers/bcma/driver_chipcommon_pmu.c bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set); mask 84 drivers/bcma/driver_chipcommon_pmu.c u32 pll0, mask; mask 127 drivers/bcma/driver_chipcommon_pmu.c mask = (u32)~(BCMA_RES_4314_HT_AVAIL | mask 130 drivers/bcma/driver_chipcommon_pmu.c bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask); mask 131 drivers/bcma/driver_chipcommon_pmu.c bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask); mask 107 drivers/bcma/driver_gpio.c u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ); mask 109 drivers/bcma/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; mask 99 drivers/bcma/main.c bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, mask 107 drivers/bcma/main.c if ((val & mask) == value) mask 204 drivers/bcma/sprom.c static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift) mask 210 drivers/bcma/sprom.c gain = (v & mask) >> shift; mask 242 drivers/block/amiflop.c #define SELECT(mask) (ciab.prb &= ~mask) mask 243 drivers/block/amiflop.c #define DESELECT(mask) (ciab.prb |= mask) mask 486 drivers/block/drbd/drbd_bitmap.c unsigned long mask; mask 494 drivers/block/drbd/drbd_bitmap.c mask = (1UL << (tmp & BITS_PER_LONG_MASK)) -1; mask 497 drivers/block/drbd/drbd_bitmap.c mask = cpu_to_lel(mask); mask 501 drivers/block/drbd/drbd_bitmap.c if (mask) { mask 506 drivers/block/drbd/drbd_bitmap.c cleared = hweight_long(*bm & ~mask); mask 507 drivers/block/drbd/drbd_bitmap.c *bm &= mask; mask 523 drivers/block/drbd/drbd_bitmap.c unsigned long mask; mask 530 drivers/block/drbd/drbd_bitmap.c mask = (1UL << (tmp & BITS_PER_LONG_MASK)) -1; mask 533 drivers/block/drbd/drbd_bitmap.c mask = cpu_to_lel(mask); mask 537 drivers/block/drbd/drbd_bitmap.c if (mask) { mask 542 drivers/block/drbd/drbd_bitmap.c *bm |= ~mask; mask 560 drivers/block/drbd/drbd_bitmap.c unsigned long mask = (1UL << (b->bm_bits & BITS_PER_LONG_MASK)) -1; mask 574 drivers/block/drbd/drbd_bitmap.c p_addr[last_word] &= cpu_to_lel(mask); mask 1034 drivers/block/drbd/drbd_main.c int drbd_send_state_req(struct drbd_peer_device *peer_device, union drbd_state mask, union drbd_state val) mask 1043 drivers/block/drbd/drbd_main.c p->mask = cpu_to_be32(mask.i); mask 1048 drivers/block/drbd/drbd_main.c int conn_send_state_req(struct drbd_connection *connection, union drbd_state mask, union drbd_state val) mask 1059 drivers/block/drbd/drbd_main.c p->mask = cpu_to_be32(mask.i); mask 474 drivers/block/drbd/drbd_nl.c union drbd_state mask = { }; mask 525 drivers/block/drbd/drbd_nl.c mask.pdsk = D_MASK; mask 530 drivers/block/drbd/drbd_nl.c mask.pdsk = D_MASK; mask 537 drivers/block/drbd/drbd_nl.c mask.pdsk = D_MASK; mask 548 drivers/block/drbd/drbd_nl.c mask.disk = D_MASK; mask 557 drivers/block/drbd/drbd_nl.c mask.pdsk = D_MASK; mask 580 drivers/block/drbd/drbd_nl.c _conn_request_state(connection, mask, val, CS_VERBOSE); mask 625 drivers/block/drbd/drbd_nl.c union drbd_state mask, val; mask 640 drivers/block/drbd/drbd_nl.c mask.i = 0; mask.role = R_MASK; mask 644 drivers/block/drbd/drbd_nl.c rv = _drbd_request_state_holding_state_mutex(device, mask, val, CS_WAIT_COMPLETE); mask 648 drivers/block/drbd/drbd_nl.c if (rv == SS_CW_FAILED_BY_PEER && mask.pdsk != 0) { mask 650 drivers/block/drbd/drbd_nl.c mask.pdsk = 0; mask 657 drivers/block/drbd/drbd_nl.c mask.disk = D_MASK; mask 664 drivers/block/drbd/drbd_nl.c device->state.disk == D_CONSISTENT && mask.pdsk == 0) { mask 669 drivers/block/drbd/drbd_nl.c mask.disk = D_MASK; mask 676 drivers/block/drbd/drbd_nl.c if (rv == SS_PRIMARY_NOP && mask.pdsk == 0) { mask 679 drivers/block/drbd/drbd_nl.c mask.pdsk = D_MASK; mask 700 drivers/block/drbd/drbd_nl.c rv = _drbd_request_state(device, mask, val, mask 3061 drivers/block/drbd/drbd_nl.c union drbd_state mask, union drbd_state val) mask 3073 drivers/block/drbd/drbd_nl.c retcode = drbd_request_state(adm_ctx.device, mask, val); mask 371 drivers/block/drbd/drbd_protocol.h u32 mask; mask 4388 drivers/block/drbd/drbd_receiver.c union drbd_state mask, val; mask 4396 drivers/block/drbd/drbd_receiver.c mask.i = be32_to_cpu(p->mask); mask 4405 drivers/block/drbd/drbd_receiver.c mask = convert_state(mask); mask 4408 drivers/block/drbd/drbd_receiver.c rv = drbd_change_state(device, CS_VERBOSE, mask, val); mask 4419 drivers/block/drbd/drbd_receiver.c union drbd_state mask, val; mask 4422 drivers/block/drbd/drbd_receiver.c mask.i = be32_to_cpu(p->mask); mask 4431 drivers/block/drbd/drbd_receiver.c mask = convert_state(mask); mask 4434 drivers/block/drbd/drbd_receiver.c rv = conn_request_state(connection, mask, val, CS_VERBOSE | CS_LOCAL_ONLY | CS_IGN_OUTD_FAIL); mask 481 drivers/block/drbd/drbd_state.c apply_mask_val(union drbd_state os, union drbd_state mask, union drbd_state val) mask 484 drivers/block/drbd/drbd_state.c ns.i = (os.i & ~mask.i) | val.i; mask 490 drivers/block/drbd/drbd_state.c union drbd_state mask, union drbd_state val) mask 497 drivers/block/drbd/drbd_state.c ns = apply_mask_val(drbd_read_state(device), mask, val); mask 511 drivers/block/drbd/drbd_state.c union drbd_state mask, union drbd_state val) mask 513 drivers/block/drbd/drbd_state.c drbd_change_state(device, CS_HARD, mask, val); mask 517 drivers/block/drbd/drbd_state.c _req_st_cond(struct drbd_device *device, union drbd_state mask, mask 532 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); mask 563 drivers/block/drbd/drbd_state.c drbd_req_state(struct drbd_device *device, union drbd_state mask, mask 581 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); mask 600 drivers/block/drbd/drbd_state.c if (drbd_send_state_req(first_peer_device(device), mask, val)) { mask 608 drivers/block/drbd/drbd_state.c (rv = _req_st_cond(device, mask, val))); mask 616 drivers/block/drbd/drbd_state.c ns = apply_mask_val(drbd_read_state(device), mask, val); mask 649 drivers/block/drbd/drbd_state.c _drbd_request_state(struct drbd_device *device, union drbd_state mask, mask 655 drivers/block/drbd/drbd_state.c (rv = drbd_req_state(device, mask, val, f)) != SS_IN_TRANSIENT_STATE); mask 700 drivers/block/drbd/drbd_state.c _drbd_request_state_holding_state_mutex(struct drbd_device *device, union drbd_state mask, mask 708 drivers/block/drbd/drbd_state.c (rv = drbd_req_state(device, mask, val, f)) != SS_IN_TRANSIENT_STATE, mask 2151 drivers/block/drbd/drbd_state.c conn_is_valid_transition(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 2163 drivers/block/drbd/drbd_state.c ns = sanitize_state(device, os, apply_mask_val(os, mask, val), NULL); mask 2194 drivers/block/drbd/drbd_state.c conn_set_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 2209 drivers/block/drbd/drbd_state.c if (mask.conn == C_MASK) { mask 2224 drivers/block/drbd/drbd_state.c ns = apply_mask_val(os, mask, val); mask 2266 drivers/block/drbd/drbd_state.c _conn_rq_cond(struct drbd_connection *connection, union drbd_state mask, union drbd_state val) mask 2276 drivers/block/drbd/drbd_state.c err = conn_is_valid_transition(connection, mask, val, 0); mask 2284 drivers/block/drbd/drbd_state.c _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 2294 drivers/block/drbd/drbd_state.c if (mask.conn) { mask 2300 drivers/block/drbd/drbd_state.c rv = conn_is_valid_transition(connection, mask, val, flags); mask 2315 drivers/block/drbd/drbd_state.c if (conn_send_state_req(connection, mask, val)) { mask 2331 drivers/block/drbd/drbd_state.c (rv = _conn_rq_cond(connection, mask, val)), mask 2341 drivers/block/drbd/drbd_state.c conn_set_state(connection, mask, val, &ns_min, &ns_max, flags); mask 2371 drivers/block/drbd/drbd_state.c drbd_err(connection, " mask = 0x%x val = 0x%x\n", mask.i, val.i); mask 2378 drivers/block/drbd/drbd_state.c conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 2384 drivers/block/drbd/drbd_state.c rv = _conn_request_state(connection, mask, val, flags); mask 38 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \ mask 41 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \ mask 42 drivers/block/drbd/drbd_state.h mask.T2 = T2##_MASK; mask; }), \ mask 46 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \ mask 47 drivers/block/drbd/drbd_state.h mask.T2 = T2##_MASK; mask.T3 = T3##_MASK; mask; }), \ mask 117 drivers/block/drbd/drbd_state.h union drbd_state mask, mask 137 drivers/block/drbd/drbd_state.h _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 141 drivers/block/drbd/drbd_state.h conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val, mask 158 drivers/block/drbd/drbd_state.h union drbd_state mask, mask 161 drivers/block/drbd/drbd_state.h return _drbd_request_state(device, mask, val, CS_VERBOSE + CS_ORDERED); mask 236 drivers/block/floppy.c static int set_dor(int fdc, char mask, char data); mask 795 drivers/block/floppy.c static int set_dor(int fdc, char mask, char data) mask 806 drivers/block/floppy.c newdor = (olddor & mask) | data; mask 913 drivers/block/floppy.c unsigned char mask = ~(0x10 << UNIT(nr)); mask 918 drivers/block/floppy.c set_dor(FDC(nr), mask, 0); mask 1867 drivers/block/floppy.c int mask; mask 1870 drivers/block/floppy.c mask = 0xfc; mask 1882 drivers/block/floppy.c mask &= ~(0x10 << UNIT(current_drive)); mask 1886 drivers/block/floppy.c set_dor(fdc, mask, data); mask 340 drivers/block/paride/pcd.c cd->info.mask = 0; mask 694 drivers/block/paride/pcd.c cd->info.mask |= CDC_CD_R; mask 696 drivers/block/paride/pcd.c cd->info.mask |= CDC_CD_RW; mask 698 drivers/block/paride/pcd.c cd->info.mask |= CDC_PLAY_AUDIO; mask 700 drivers/block/paride/pcd.c cd->info.mask |= CDC_LOCK; mask 702 drivers/block/paride/pcd.c cd->info.mask |= CDC_OPEN_TRAY; mask 704 drivers/block/paride/pcd.c cd->info.mask |= CDC_CLOSE_TRAY; mask 272 drivers/block/rsxx/core.c static void __enable_intr(unsigned int *mask, unsigned int intr) mask 274 drivers/block/rsxx/core.c *mask |= intr; mask 277 drivers/block/rsxx/core.c static void __disable_intr(unsigned int *mask, unsigned int intr) mask 279 drivers/block/rsxx/core.c *mask &= ~intr; mask 1313 drivers/block/skd_main.c u8 mask; mask 1370 drivers/block/skd_main.c if (sns->mask & 0x10) mask 1374 drivers/block/skd_main.c if (sns->mask & 0x08) mask 1378 drivers/block/skd_main.c if (sns->mask & 0x04) mask 1382 drivers/block/skd_main.c if (sns->mask & 0x02) mask 1386 drivers/block/skd_main.c if (sns->mask & 0x01) mask 1055 drivers/block/sx8.c u32 mask; mask 1069 drivers/block/sx8.c mask = readl(mmio + CARM_INT_STAT); mask 1071 drivers/block/sx8.c if (mask == 0 || mask == 0xffffffff) { mask 1072 drivers/block/sx8.c VPRINTK("no work, mask == 0x%x\n", mask); mask 1076 drivers/block/sx8.c if (mask & INT_ACK_MASK) mask 1077 drivers/block/sx8.c writel(mask, mmio + CARM_INT_STAT); mask 1080 drivers/block/sx8.c VPRINTK("not initialized yet, mask = 0x%x\n", mask); mask 1084 drivers/block/sx8.c if (mask & CARM_HAVE_RESP) { mask 301 drivers/bluetooth/btintel.c u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; mask 306 drivers/bluetooth/btintel.c mask[1] |= 0x62; mask 308 drivers/bluetooth/btintel.c skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT); mask 435 drivers/bluetooth/btmrvl_sdio.c u8 mask) mask 439 drivers/bluetooth/btmrvl_sdio.c sdio_writeb(card->func, mask, card->reg->host_int_mask, &ret); mask 449 drivers/bluetooth/btmrvl_sdio.c u8 mask) mask 458 drivers/bluetooth/btmrvl_sdio.c host_int_mask &= ~mask; mask 180 drivers/bus/brcmstb_gisb.c u32 mask = gdev->valid_mask & masters; mask 182 drivers/bus/brcmstb_gisb.c if (hweight_long(mask) != 1) mask 185 drivers/bus/brcmstb_gisb.c return gdev->master_names[ffs(mask) - 1]; mask 56 drivers/bus/da8xx-mstpri.c int mask; mask 63 drivers/bus/da8xx-mstpri.c .mask = 0x0000000f, mask 68 drivers/bus/da8xx-mstpri.c .mask = 0x000000f0, mask 73 drivers/bus/da8xx-mstpri.c .mask = 0x000f0000, mask 78 drivers/bus/da8xx-mstpri.c .mask = 0x00f00000, mask 83 drivers/bus/da8xx-mstpri.c .mask = 0x0000000f, mask 88 drivers/bus/da8xx-mstpri.c .mask = 0x000000f0, mask 93 drivers/bus/da8xx-mstpri.c .mask = 0x00000f00, mask 98 drivers/bus/da8xx-mstpri.c .mask = 0x0000f000, mask 103 drivers/bus/da8xx-mstpri.c .mask = 0x000f0000, mask 108 drivers/bus/da8xx-mstpri.c .mask = 0x0f000000, mask 113 drivers/bus/da8xx-mstpri.c .mask = 0xf0000000, mask 118 drivers/bus/da8xx-mstpri.c .mask = 0x0000000f, mask 123 drivers/bus/da8xx-mstpri.c .mask = 0x00000f00, mask 128 drivers/bus/da8xx-mstpri.c .mask = 0x0000f000, mask 133 drivers/bus/da8xx-mstpri.c .mask = 0x00f00000, mask 138 drivers/bus/da8xx-mstpri.c .mask = 0x0f000000, mask 143 drivers/bus/da8xx-mstpri.c .mask = 0xf0000000, mask 239 drivers/bus/da8xx-mstpri.c reg &= ~prio_descr->mask; mask 163 drivers/bus/fsl-mc/dprc.c u32 mask) mask 172 drivers/bus/fsl-mc/dprc.c cmd_params->mask = cpu_to_le32(mask); mask 132 drivers/bus/fsl-mc/fsl-mc-private.h __le32 mask; mask 292 drivers/bus/fsl-mc/fsl-mc-private.h u32 mask); mask 2053 drivers/bus/ti-sysc.c u32 mask; mask 2058 drivers/bus/ti-sysc.c .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, mask 2060 drivers/bus/ti-sysc.c .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, mask 2062 drivers/bus/ti-sysc.c .mask = SYSC_QUIRK_NO_IDLE, }, mask 2078 drivers/bus/ti-sysc.c ddata->cfg.quirks |= sysc_dts_quirks[i].mask; mask 41 drivers/bus/uniphier-system-bus.c u64 end, mask; mask 80 drivers/bus/uniphier-system-bus.c mask = paddr ^ (end - 1); mask 81 drivers/bus/uniphier-system-bus.c mask = roundup_pow_of_two(mask); mask 83 drivers/bus/uniphier-system-bus.c paddr = round_down(paddr, mask); mask 84 drivers/bus/uniphier-system-bus.c end = round_up(end, mask); mask 137 drivers/bus/uniphier-system-bus.c u32 base, end, mask, val; mask 163 drivers/bus/uniphier-system-bus.c mask = base ^ (end - 1); mask 166 drivers/bus/uniphier-system-bus.c val |= (~mask >> 16) & 0xfffe; mask 333 drivers/cdrom/cdrom.c #define CDROM_CAN(type) (cdi->ops->capability & ~cdi->mask & (type)) mask 912 drivers/cdrom/cdrom.c cdi->mask &= ~CDC_MRW; mask 914 drivers/cdrom/cdrom.c cdi->mask |= CDC_MRW; mask 917 drivers/cdrom/cdrom.c cdi->mask &= ~CDC_MRW_W; mask 919 drivers/cdrom/cdrom.c cdi->mask |= CDC_MRW_W; mask 922 drivers/cdrom/cdrom.c cdi->mask &= ~CDC_RAM; mask 924 drivers/cdrom/cdrom.c cdi->mask |= CDC_RAM; mask 1509 drivers/cdrom/cdrom.c unsigned int mask = (1 << (queue & 1)); mask 1510 drivers/cdrom/cdrom.c int ret = !!(cdi->mc_flags & mask); mask 1531 drivers/cdrom/cdrom.c cdi->mc_flags &= ~mask; /* clear bit */ mask 2517 drivers/cdrom/cdrom.c return (cdi->ops->capability & ~cdi->mask); mask 3112 drivers/cdrom/cdrom.c char mask[sizeof(buffer)]; mask 3164 drivers/cdrom/cdrom.c cgc->buffer = mask; mask 3169 drivers/cdrom/cdrom.c buffer[offset + 9] = volctrl.channel0 & mask[offset + 9]; mask 3170 drivers/cdrom/cdrom.c buffer[offset + 11] = volctrl.channel1 & mask[offset + 11]; mask 3171 drivers/cdrom/cdrom.c buffer[offset + 13] = volctrl.channel2 & mask[offset + 13]; mask 3172 drivers/cdrom/cdrom.c buffer[offset + 15] = volctrl.channel3 & mask[offset + 15]; mask 709 drivers/cdrom/gdrom.c gd.cd_info->mask = CDC_CLOSE_TRAY|CDC_OPEN_TRAY|CDC_LOCK| mask 54 drivers/char/agp/agp.h unsigned long mask; mask 361 drivers/char/agp/amd-k7-agp.c {.mask = 1, .type = 0} mask 41 drivers/char/agp/ati-agp.c { .mask = 1, .type = 0} mask 65 drivers/char/agp/efficeon-agp.c {.mask = 0x00000001, .type = 0} mask 1323 drivers/char/agp/generic.c return addr | bridge->driver->masks[0].mask; mask 53 drivers/char/agp/hp-agp.c {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0} mask 99 drivers/char/agp/i460-agp.c .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT, mask 552 drivers/char/agp/i460-agp.c return bridge->driver->masks[0].mask mask 411 drivers/char/agp/intel-agp.c {.mask = 0x00000017, .type = 0} mask 1364 drivers/char/agp/intel-gtt.c int i, mask; mask 1410 drivers/char/agp/intel-gtt.c mask = intel_private.driver->dma_mask_size; mask 1411 drivers/char/agp/intel-gtt.c if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) mask 1413 drivers/char/agp/intel-gtt.c "set gfx device dma mask %d-bit failed!\n", mask); mask 1416 drivers/char/agp/intel-gtt.c DMA_BIT_MASK(mask)); mask 305 drivers/char/agp/nvidia-agp.c { .mask = 1, .type = 0} mask 54 drivers/char/agp/parisc-agp.c .mask = SBA_PDIR_VALID_BIT, mask 387 drivers/char/agp/sworks-agp.c {.mask = 1, .type = 0} mask 125 drivers/char/ds1620.c unsigned int value = 0, mask = 1; mask 135 drivers/char/ds1620.c value |= mask; mask 137 drivers/char/ds1620.c mask <<= 1; mask 234 drivers/char/dtlk.c __poll_t mask = 0; mask 248 drivers/char/dtlk.c mask = EPOLLIN | EPOLLRDNORM; mask 252 drivers/char/dtlk.c mask |= EPOLLOUT | EPOLLWRNORM; mask 260 drivers/char/dtlk.c return mask; mask 79 drivers/char/hpet.c .mask = CLOCKSOURCE_MASK(64), mask 82 drivers/char/hw_random/nomadik-rng.c .mask = 0x000fffff, /* top bits are rev and cfg: accept all */ mask 340 drivers/char/ipmi/bt-bmc.c __poll_t mask = 0; mask 348 drivers/char/ipmi/bt-bmc.c mask |= EPOLLIN; mask 351 drivers/char/ipmi/bt-bmc.c mask |= EPOLLOUT; mask 353 drivers/char/ipmi/bt-bmc.c return mask; mask 160 drivers/char/ipmi/ipmb_dev_int.c unsigned int mask = POLLOUT; mask 166 drivers/char/ipmi/ipmb_dev_int.c mask |= POLLIN; mask 169 drivers/char/ipmi/ipmb_dev_int.c return mask; mask 60 drivers/char/ipmi/ipmi_devintf.c __poll_t mask = 0; mask 68 drivers/char/ipmi/ipmi_devintf.c mask |= (EPOLLIN | EPOLLRDNORM); mask 72 drivers/char/ipmi/ipmi_devintf.c return mask; mask 849 drivers/char/ipmi/ipmi_watchdog.c __poll_t mask = 0; mask 855 drivers/char/ipmi/ipmi_watchdog.c mask |= (EPOLLIN | EPOLLRDNORM); mask 858 drivers/char/ipmi/ipmi_watchdog.c return mask; mask 68 drivers/char/ipmi/kcs_bmc.c static void update_status_bits(struct kcs_bmc *kcs_bmc, u8 mask, u8 val) mask 72 drivers/char/ipmi/kcs_bmc.c tmp &= ~mask; mask 73 drivers/char/ipmi/kcs_bmc.c tmp |= val & mask; mask 261 drivers/char/ipmi/kcs_bmc.c __poll_t mask = 0; mask 267 drivers/char/ipmi/kcs_bmc.c mask |= EPOLLIN; mask 270 drivers/char/ipmi/kcs_bmc.c return mask; mask 125 drivers/char/pc8736x_gpio.c static inline u32 pc8736x_gpio_configure_fn(unsigned index, u32 mask, u32 bits, mask 139 drivers/char/pc8736x_gpio.c new_config = (config & mask) | bits; mask 147 drivers/char/pc8736x_gpio.c static u32 pc8736x_gpio_configure(unsigned index, u32 mask, u32 bits) mask 149 drivers/char/pc8736x_gpio.c return pc8736x_gpio_configure_fn(index, mask, bits, mask 421 drivers/char/pcmcia/cm4040_cs.c __poll_t mask = 0; mask 426 drivers/char/pcmcia/cm4040_cs.c mask |= EPOLLIN | EPOLLRDNORM; mask 428 drivers/char/pcmcia/cm4040_cs.c mask |= EPOLLOUT | EPOLLWRNORM; mask 430 drivers/char/pcmcia/cm4040_cs.c DEBUGP(2, dev, "<- cm4040_poll(%u)\n", mask); mask 432 drivers/char/pcmcia/cm4040_cs.c return mask; mask 327 drivers/char/pcmcia/synclink_cs.c #define set_reg_bits(info, reg, mask) \ mask 329 drivers/char/pcmcia/synclink_cs.c (unsigned char) (read_reg(info, (reg)) | (mask))) mask 330 drivers/char/pcmcia/synclink_cs.c #define clear_reg_bits(info, reg, mask) \ mask 332 drivers/char/pcmcia/synclink_cs.c (unsigned char) (read_reg(info, (reg)) & ~(mask))) mask 336 drivers/char/pcmcia/synclink_cs.c static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) mask 339 drivers/char/pcmcia/synclink_cs.c info->imra_value |= mask; mask 342 drivers/char/pcmcia/synclink_cs.c info->imrb_value |= mask; mask 346 drivers/char/pcmcia/synclink_cs.c static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask) mask 349 drivers/char/pcmcia/synclink_cs.c info->imra_value &= ~mask; mask 352 drivers/char/pcmcia/synclink_cs.c info->imrb_value &= ~mask; mask 357 drivers/char/pcmcia/synclink_cs.c #define port_irq_disable(info, mask) \ mask 358 drivers/char/pcmcia/synclink_cs.c { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); } mask 360 drivers/char/pcmcia/synclink_cs.c #define port_irq_enable(info, mask) \ mask 361 drivers/char/pcmcia/synclink_cs.c { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); } mask 430 drivers/char/pcmcia/synclink_cs.c static int wait_events(MGSLPC_INFO *info, int __user *mask); mask 1960 drivers/char/pcmcia/synclink_cs.c int mask; mask 1964 drivers/char/pcmcia/synclink_cs.c COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); mask 1969 drivers/char/pcmcia/synclink_cs.c printk("wait_events(%s,%d)\n", info->device_name, mask); mask 1976 drivers/char/pcmcia/synclink_cs.c events = mask & mask 1991 drivers/char/pcmcia/synclink_cs.c (mask & MgslEvent_ExitHuntMode)) mask 2029 drivers/char/pcmcia/synclink_cs.c events = mask & mask 2050 drivers/char/pcmcia/synclink_cs.c if (mask & MgslEvent_ExitHuntMode) { mask 518 drivers/char/ppdev.c unsigned char mask; mask 568 drivers/char/ppdev.c if (copy_from_user(&mask, argp, mask 569 drivers/char/ppdev.c sizeof(mask))) mask 574 drivers/char/ppdev.c parport_frob_control(port, mask, reg); mask 779 drivers/char/ppdev.c __poll_t mask = 0; mask 783 drivers/char/ppdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 785 drivers/char/ppdev.c return mask; mask 2049 drivers/char/random.c __poll_t mask; mask 2053 drivers/char/random.c mask = 0; mask 2055 drivers/char/random.c mask |= EPOLLIN | EPOLLRDNORM; mask 2057 drivers/char/random.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2058 drivers/char/random.c return mask; mask 77 drivers/char/sonypi.c static unsigned long mask = 0xffffffff; mask 78 drivers/char/sonypi.c module_param(mask, ulong, 0644); mask 79 drivers/char/sonypi.c MODULE_PARM_DESC(mask, mask 380 drivers/char/sonypi.c unsigned long mask; mask 838 drivers/char/sonypi.c if (!(mask & sonypi_eventtypes[i].mask)) mask 1276 drivers/char/sonypi.c mask, mask 145 drivers/char/tlclk.c #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port) mask 215 drivers/char/tpm/st33zp24/st33zp24.c static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask, mask 221 drivers/char/tpm/st33zp24/st33zp24.c if ((status & mask) == mask) mask 239 drivers/char/tpm/st33zp24/st33zp24.c static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout, mask 252 drivers/char/tpm/st33zp24/st33zp24.c if ((status & mask) == mask) mask 274 drivers/char/tpm/st33zp24/st33zp24.c condition = wait_for_tpm_stat_cond(chip, mask, mask 289 drivers/char/tpm/st33zp24/st33zp24.c if ((status & mask) == mask) mask 236 drivers/char/tpm/tpm-dev-common.c __poll_t mask = 0; mask 247 drivers/char/tpm/tpm-dev-common.c mask = EPOLLIN | EPOLLRDNORM; mask 249 drivers/char/tpm/tpm-dev-common.c mask = EPOLLOUT | EPOLLWRNORM; mask 252 drivers/char/tpm/tpm-dev-common.c return mask; mask 111 drivers/char/tpm/tpm_crb.c static bool crb_wait_for_reg_32(u32 __iomem *reg, u32 mask, u32 value, mask 121 drivers/char/tpm/tpm_crb.c if ((ioread32(reg) & mask) == value) mask 127 drivers/char/tpm/tpm_crb.c return ((ioread32(reg) & mask) == value); mask 245 drivers/char/tpm/tpm_crb.c u32 mask = CRB_LOC_STATE_LOC_ASSIGNED | mask 253 drivers/char/tpm/tpm_crb.c if (!crb_wait_for_reg_32(&priv->regs_h->loc_state, mask, value, mask 413 drivers/char/tpm/tpm_i2c_infineon.c static int wait_for_stat(struct tpm_chip *chip, u8 mask, unsigned long timeout, mask 420 drivers/char/tpm/tpm_i2c_infineon.c if ((*status != 0xFF) && (*status & mask) == mask) mask 428 drivers/char/tpm/tpm_i2c_infineon.c if ((*status & mask) == mask) mask 164 drivers/char/tpm/tpm_i2c_nuvoton.c static bool i2c_nuvoton_check_status(struct tpm_chip *chip, u8 mask, u8 value) mask 167 drivers/char/tpm/tpm_i2c_nuvoton.c return (status != TPM_STS_ERR_VAL) && ((status & mask) == value); mask 170 drivers/char/tpm/tpm_i2c_nuvoton.c static int i2c_nuvoton_wait_for_stat(struct tpm_chip *chip, u8 mask, u8 value, mask 191 drivers/char/tpm/tpm_i2c_nuvoton.c status_valid = i2c_nuvoton_check_status(chip, mask, value); mask 207 drivers/char/tpm/tpm_i2c_nuvoton.c status_valid = i2c_nuvoton_check_status(chip, mask, mask 213 drivers/char/tpm/tpm_i2c_nuvoton.c dev_err(&chip->dev, "%s(%02x, %02x) -> timeout\n", __func__, mask, mask 70 drivers/char/tpm/tpm_nsc.c static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) mask 77 drivers/char/tpm/tpm_nsc.c if ((*data & mask) == val) mask 85 drivers/char/tpm/tpm_nsc.c if ((*data & mask) == val) mask 32 drivers/char/tpm/tpm_tis_core.c static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask, mask 38 drivers/char/tpm/tpm_tis_core.c if ((status & mask) == mask) mask 47 drivers/char/tpm/tpm_tis_core.c static int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask, mask 58 drivers/char/tpm/tpm_tis_core.c if ((status & mask) == mask) mask 69 drivers/char/tpm/tpm_tis_core.c wait_for_tpm_stat_cond(chip, mask, check_cancel, mask 86 drivers/char/tpm/tpm_tis_core.c if ((status & mask) == mask) mask 40 drivers/char/tpm/xen-tpmfront.c static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask, mask 46 drivers/char/tpm/xen-tpmfront.c if ((status & mask) == mask) mask 55 drivers/char/tpm/xen-tpmfront.c static int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask, mask 66 drivers/char/tpm/xen-tpmfront.c if ((status & mask) == mask) mask 77 drivers/char/tpm/xen-tpmfront.c wait_for_tpm_stat_cond(chip, mask, check_cancel, mask 93 drivers/char/tpm/xen-tpmfront.c if ((status & mask) == mask) mask 1739 drivers/char/xillybus/xillybus_core.c __poll_t mask = 0; mask 1758 drivers/char/xillybus/xillybus_core.c mask |= EPOLLIN | EPOLLRDNORM; mask 1766 drivers/char/xillybus/xillybus_core.c mask |= EPOLLIN | EPOLLRDNORM; mask 1781 drivers/char/xillybus/xillybus_core.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1786 drivers/char/xillybus/xillybus_core.c mask |= EPOLLERR; mask 1788 drivers/char/xillybus/xillybus_core.c return mask; mask 69 drivers/clk/at91/clk-master.c mckr &= layout->mask; mask 147 drivers/clk/at91/clk-master.c .mask = 0x31F, mask 153 drivers/clk/at91/clk-master.c .mask = 0x373, mask 62 drivers/clk/at91/clk-pll.c u32 mask = PLL_STATUS_MASK(id); mask 75 drivers/clk/at91/clk-pll.c if ((status & mask) && mask 107 drivers/clk/at91/clk-pll.c unsigned int mask = pll->layout->pllr_mask; mask 109 drivers/clk/at91/clk-pll.c regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); mask 105 drivers/clk/at91/clk-programmable.c unsigned int mask = layout->css_mask; mask 109 drivers/clk/at91/clk-programmable.c mask |= AT91_PMC_CSSMCK_MCK; mask 118 drivers/clk/at91/clk-programmable.c regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), mask, pckr); mask 213 drivers/clk/at91/pmc.c static bool pmc_ready(unsigned int mask) mask 219 drivers/clk/at91/pmc.c return ((status & mask) == mask) ? 1 : 0; mask 227 drivers/clk/at91/pmc.c u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; mask 256 drivers/clk/at91/pmc.c mask |= AT91_PMC_LOCKU; mask 258 drivers/clk/at91/pmc.c while (!pmc_ready(mask)) mask 38 drivers/clk/at91/pmc.h u32 mask; mask 19 drivers/clk/at91/sam9x60.c .mask = 0x373, mask 50 drivers/clk/bcm/clk-kona.c u32 mask = bitfield_mask(shift, width); mask 52 drivers/clk/bcm/clk-kona.c return (reg_val & ~mask) | (val << shift); mask 219 drivers/clk/bcm/clk-kona.c u32 mask; mask 252 drivers/clk/bcm/clk-kona.c mask = (u32)1 << go_bit; mask 254 drivers/clk/bcm/clk-kona.c mask |= 1 << control->atl_bit; mask 256 drivers/clk/bcm/clk-kona.c mask |= 1 << control->ac_bit; mask 257 drivers/clk/bcm/clk-kona.c __ccu_write(ccu, offset, mask); mask 313 drivers/clk/bcm/clk-kona.c u32 mask; mask 335 drivers/clk/bcm/clk-kona.c mask = (u32)1 << policy->bit; mask 340 drivers/clk/bcm/clk-kona.c reg_val |= mask; mask 399 drivers/clk/bcm/clk-kona.c u32 mask; mask 410 drivers/clk/bcm/clk-kona.c mask = (u32)1 << gate->hw_sw_sel_bit; mask 412 drivers/clk/bcm/clk-kona.c reg_val |= mask; mask 414 drivers/clk/bcm/clk-kona.c reg_val &= ~mask; mask 424 drivers/clk/bcm/clk-kona.c mask = (u32)1 << gate->en_bit; mask 427 drivers/clk/bcm/clk-kona.c reg_val |= mask; mask 429 drivers/clk/bcm/clk-kona.c reg_val &= ~mask; mask 531 drivers/clk/bcm/clk-kona.c u32 mask; mask 537 drivers/clk/bcm/clk-kona.c mask = (u32)1 << hyst->en_bit; mask 538 drivers/clk/bcm/clk-kona.c mask |= (u32)1 << hyst->val_bit; mask 541 drivers/clk/bcm/clk-kona.c reg_val |= mask; mask 80 drivers/clk/clk-asm9260.c u8 mask; mask 293 drivers/clk/clk-asm9260.c 0, mc->mask, 0, mc->table, &asm9260_clk_lock); mask 212 drivers/clk/clk-axi-clkgen.c unsigned int reg, unsigned int val, unsigned int mask) mask 221 drivers/clk/clk-axi-clkgen.c if (mask != 0xffff) { mask 223 drivers/clk/clk-axi-clkgen.c reg_val &= ~mask; mask 226 drivers/clk/clk-axi-clkgen.c reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); mask 19 drivers/clk/clk-bd718x7.c u8 mask; mask 28 drivers/clk/clk-bd718x7.c return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status); mask 57 drivers/clk/clk-bd718x7.c return enabled & c->mask; mask 94 drivers/clk/clk-bd718x7.c c->mask = BD718XX_OUT32K_EN; mask 98 drivers/clk/clk-bd718x7.c c->mask = BD70528_CLK_OUT_EN_MASK; mask 133 drivers/clk/clk-cdce706.c unsigned mask, unsigned val) mask 135 drivers/clk/clk-cdce706.c int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); mask 102 drivers/clk/clk-cs2000-cp.c static int cs2000_bset(struct cs2000_priv *priv, u8 addr, u8 mask, u8 val) mask 110 drivers/clk/clk-cs2000-cp.c data &= ~mask; mask 111 drivers/clk/clk-cs2000-cp.c data |= (val & mask); mask 47 drivers/clk/clk-divider.c unsigned int maxdiv = 0, mask = clk_div_mask(width); mask 51 drivers/clk/clk-divider.c if (clkt->div > maxdiv && clkt->val <= mask) mask 92 drivers/clk/clk-max9485.c u8 mask, u8 value) mask 96 drivers/clk/clk-max9485.c drvdata->reg_value &= ~mask; mask 101 drivers/clk/clk-max9485.c mask, value, drvdata->reg_value); mask 94 drivers/clk/clk-milbeaut.c u8 mask; mask 286 drivers/clk/clk-milbeaut.c val &= mux->mask; mask 297 drivers/clk/clk-milbeaut.c u32 write_en = BIT(fls(mux->mask) - 1); mask 305 drivers/clk/clk-milbeaut.c reg &= ~(mux->mask << mux->shift); mask 328 drivers/clk/clk-milbeaut.c u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, mask 348 drivers/clk/clk-milbeaut.c mux->mask = mask; mask 553 drivers/clk/clk-milbeaut.c factors->mask, factors->mux_flags, mask 93 drivers/clk/clk-mux.c val &= mux->mask; mask 111 drivers/clk/clk-mux.c reg = mux->mask << (mux->shift + 16); mask 114 drivers/clk/clk-mux.c reg &= ~(mux->mask << mux->shift); mask 151 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u32 mask, mask 161 drivers/clk/clk-mux.c width = fls(mask) - ffs(mask) + 1; mask 185 drivers/clk/clk-mux.c mux->mask = mask; mask 205 drivers/clk/clk-mux.c void __iomem *reg, u8 shift, u32 mask, mask 211 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, mask 225 drivers/clk/clk-mux.c u32 mask = BIT(width) - 1; mask 228 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, mask 239 drivers/clk/clk-mux.c u32 mask = BIT(width) - 1; mask 242 drivers/clk/clk-mux.c flags, reg, shift, mask, clk_mux_flags, mask 471 drivers/clk/clk-nomadik.c u32 mask = BIT(i & 0x1f); mask 475 drivers/clk/clk-nomadik.c (pcksrb & mask) ? "on " : "off", mask 476 drivers/clk/clk-nomadik.c (pcksr & mask) ? "on " : "off", mask 477 drivers/clk/clk-nomadik.c (pckreq & mask) ? "on " : "off"); mask 148 drivers/clk/clk-npcm7xx.c u8 mask; mask 609 drivers/clk/clk-npcm7xx.c mux_data->shift, mux_data->mask, 0, mask 28 drivers/clk/clk-s2mps11.c u32 mask; mask 43 drivers/clk/clk-s2mps11.c s2mps11->mask, s2mps11->mask); mask 51 drivers/clk/clk-s2mps11.c s2mps11->mask, ~s2mps11->mask); mask 65 drivers/clk/clk-s2mps11.c return val & s2mps11->mask; mask 168 drivers/clk/clk-s2mps11.c s2mps11_clks[i].mask = 1 << i; mask 434 drivers/clk/clk-si5341.c u8 mask = BIT(index); mask 438 drivers/clk/clk-si5341.c SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0); mask 441 drivers/clk/clk-si5341.c SI5341_SYNTH_N_PDNB, mask, 0); mask 444 drivers/clk/clk-si5341.c SI5341_SYNTH_N_CLK_DIS, mask, mask); mask 452 drivers/clk/clk-si5341.c u8 mask = BIT(index); mask 456 drivers/clk/clk-si5341.c SI5341_SYNTH_N_PDNB, mask, mask); mask 462 drivers/clk/clk-si5341.c SI5341_SYNTH_N_CLK_DIS, mask, 0); mask 468 drivers/clk/clk-si5341.c SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask); mask 117 drivers/clk/clk-si5351.c u8 reg, u8 mask, u8 val) mask 119 drivers/clk/clk-si5351.c return regmap_update_bits(drvdata->regmap, reg, mask, val); mask 368 drivers/clk/clk-si5351.c u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; mask 380 drivers/clk/clk-si5351.c si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask, mask 381 drivers/clk/clk-si5351.c (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask); mask 389 drivers/clk/clk-si5351.c u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; mask 394 drivers/clk/clk-si5351.c return (val & mask) ? 1 : 0; mask 840 drivers/clk/clk-si5351.c u8 mask; mask 847 drivers/clk/clk-si5351.c mask = SI5351_CLK_DRIVE_STRENGTH_2MA; mask 850 drivers/clk/clk-si5351.c mask = SI5351_CLK_DRIVE_STRENGTH_4MA; mask 853 drivers/clk/clk-si5351.c mask = SI5351_CLK_DRIVE_STRENGTH_6MA; mask 856 drivers/clk/clk-si5351.c mask = SI5351_CLK_DRIVE_STRENGTH_8MA; mask 863 drivers/clk/clk-si5351.c SI5351_CLK_DRIVE_STRENGTH_MASK, mask); mask 874 drivers/clk/clk-si5351.c u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift; mask 897 drivers/clk/clk-si5351.c si5351_set_bits(drvdata, reg, mask, val << shift); mask 1085 drivers/clk/clk-stm32f4.c mux->mask = 3; mask 1161 drivers/clk/clk-stm32f4.c u8 mask; mask 1628 drivers/clk/clk-stm32f4.c int offset_mux, u8 shift, u8 mask, mask 1662 drivers/clk/clk-stm32f4.c mux->mask = mask; mask 1877 drivers/clk/clk-stm32f4.c aux_clk->mask, aux_clk->offset_gate, mask 306 drivers/clk/clk-stm32h7.c mux->mask = (1 << width) - 1; mask 749 drivers/clk/clk-stm32h7.c u32 val, mask; mask 753 drivers/clk/clk-stm32h7.c mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift; mask 754 drivers/clk/clk-stm32h7.c m = (val & mask) >> fd->mshift; mask 757 drivers/clk/clk-stm32h7.c mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift; mask 758 drivers/clk/clk-stm32h7.c n = ((val & mask) >> fd->nshift) + 1; mask 309 drivers/clk/clk-stm32mp1.c u32 mask; mask 487 drivers/clk/clk-stm32mp1.c mmux->mux.mask = (1 << cfg->mux->width) - 1; mask 502 drivers/clk/clk-stm32mp1.c mux->mask = (1 << cfg->mux->width) - 1; mask 550 drivers/clk/clk-stm32mp1.c mgate->mask = BIT(cfg->mgate->nbr_clk++); mask 670 drivers/clk/clk-stm32mp1.c clk_mgate->mgate->flag |= clk_mgate->mask; mask 682 drivers/clk/clk-stm32mp1.c clk_mgate->mgate->flag &= ~clk_mgate->mask; mask 218 drivers/clk/clk-versaclock5.c const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; mask 222 drivers/clk/clk-versaclock5.c src &= mask; mask 239 drivers/clk/clk-versaclock5.c const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; mask 262 drivers/clk/clk-versaclock5.c return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src); mask 298 drivers/clk/clk-versaclock5.c u32 mask; mask 301 drivers/clk/clk-versaclock5.c mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; mask 303 drivers/clk/clk-versaclock5.c mask = 0; mask 307 drivers/clk/clk-versaclock5.c mask); mask 569 drivers/clk/clk-versaclock5.c const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | mask 580 drivers/clk/clk-versaclock5.c if ((src & mask) == 0) { mask 584 drivers/clk/clk-versaclock5.c mask | VC5_OUT_DIV_CONTROL_RESET, src); mask 610 drivers/clk/clk-versaclock5.c const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | mask 620 drivers/clk/clk-versaclock5.c src &= mask; mask 640 drivers/clk/clk-versaclock5.c const u8 mask = VC5_OUT_DIV_CONTROL_RESET | mask 654 drivers/clk/clk-versaclock5.c mask, src); mask 225 drivers/clk/clk-xgene.c u32 mask; mask 259 drivers/clk/clk-xgene.c scale = (val & fd->mask) >> fd->shift; mask 322 drivers/clk/clk-xgene.c val &= ~fd->mask; mask 362 drivers/clk/clk-xgene.c fd->mask = (BIT(width) - 1) << shift; mask 36 drivers/clk/davinci/da8xx-cfgchip.c u32 mask; mask 46 drivers/clk/davinci/da8xx-cfgchip.c return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); mask 53 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); mask 63 drivers/clk/davinci/da8xx-cfgchip.c return !!(val & clk->mask); mask 119 drivers/clk/davinci/da8xx-cfgchip.c gate->mask = info->bit; mask 207 drivers/clk/davinci/da8xx-cfgchip.c u32 mask; mask 216 drivers/clk/davinci/da8xx-cfgchip.c unsigned int val = index ? clk->mask : 0; mask 218 drivers/clk/davinci/da8xx-cfgchip.c return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); mask 228 drivers/clk/davinci/da8xx-cfgchip.c return (val & clk->mask) ? 1 : 0; mask 259 drivers/clk/davinci/da8xx-cfgchip.c mux->mask = info->bit; mask 376 drivers/clk/davinci/da8xx-cfgchip.c unsigned int mask, val; mask 387 drivers/clk/davinci/da8xx-cfgchip.c mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; mask 390 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); mask 422 drivers/clk/davinci/da8xx-cfgchip.c unsigned int mask, val; mask 425 drivers/clk/davinci/da8xx-cfgchip.c mask = CFGCHIP2_REFFREQ_MASK; mask 458 drivers/clk/davinci/da8xx-cfgchip.c regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); mask 590 drivers/clk/davinci/pll.c mux->mask = info->ocsrc_mask; mask 22 drivers/clk/hisilicon/clk-hisi-phase.c u32 mask; mask 48 drivers/clk/hisilicon/clk-hisi-phase.c regval = (regval & phase->mask) >> phase->shift; mask 79 drivers/clk/hisilicon/clk-hisi-phase.c val &= ~phase->mask; mask 112 drivers/clk/hisilicon/clk-hisi-phase.c phase->mask = (BIT(clks->width) - 1) << clks->shift; mask 158 drivers/clk/hisilicon/clk.c u32 mask = BIT(clks[i].width) - 1; mask 164 drivers/clk/hisilicon/clk.c mask, clks[i].mux_flags, mask 37 drivers/clk/hisilicon/clkdivider-hi6220.c u32 mask; mask 84 drivers/clk/hisilicon/clkdivider-hi6220.c data |= dclk->mask; mask 141 drivers/clk/hisilicon/clkdivider-hi6220.c div->mask = mask_bit ? BIT(mask_bit) : 0; mask 26 drivers/clk/imgtec/clk-boston.c static u32 ext_field(u32 val, u32 mask) mask 28 drivers/clk/imgtec/clk-boston.c return (val & mask) >> (ffs(mask) - 1); mask 172 drivers/clk/imx/clk-busy.c busy->mux.mask = BIT(width) - 1; mask 43 drivers/clk/imx/clk-composite-7ulp.c mux->mask = PCG_PCS_MASK; mask 144 drivers/clk/imx/clk-composite-8m.c mux->mask = PCG_PCS_MASK; mask 51 drivers/clk/imx/clk-fixup-mux.c val &= ~(mux->mask << mux->shift); mask 90 drivers/clk/imx/clk-fixup-mux.c fixup_mux->mux.mask = BIT(width) - 1; mask 321 drivers/clk/ingenic/cgu.c u32 reg, mask; mask 345 drivers/clk/ingenic/cgu.c mask = GENMASK(clk_info->mux.bits - 1, 0); mask 346 drivers/clk/ingenic/cgu.c mask <<= clk_info->mux.shift; mask 352 drivers/clk/ingenic/cgu.c reg &= ~mask; mask 466 drivers/clk/ingenic/cgu.c u32 reg, mask; mask 487 drivers/clk/ingenic/cgu.c mask = GENMASK(clk_info->div.bits - 1, 0); mask 488 drivers/clk/ingenic/cgu.c reg &= ~(mask << clk_info->div.shift); mask 252 drivers/clk/keystone/pll.c u32 shift, mask; mask 276 drivers/clk/keystone/pll.c if (of_property_read_u32(node, "bit-mask", &mask)) { mask 283 drivers/clk/keystone/pll.c mask, 0, NULL); mask 300 drivers/clk/keystone/pll.c u32 shift, mask; mask 323 drivers/clk/keystone/pll.c if (of_property_read_u32(node, "bit-mask", &mask)) { mask 329 drivers/clk/keystone/pll.c ARRAY_SIZE(parents) , 0, reg, shift, mask, mask 27 drivers/clk/mediatek/clk-cpumux.c val &= mux->mask; mask 35 drivers/clk/mediatek/clk-cpumux.c u32 mask, val; mask 38 drivers/clk/mediatek/clk-cpumux.c mask = mux->mask << mux->shift; mask 40 drivers/clk/mediatek/clk-cpumux.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); mask 68 drivers/clk/mediatek/clk-cpumux.c cpumux->mask = BIT(mux->mux_width) - 1; mask 14 drivers/clk/mediatek/clk-cpumux.h u32 mask; mask 169 drivers/clk/mediatek/clk-mtk.c mux->mask = BIT(mc->mux_width) - 1; mask 23 drivers/clk/mediatek/clk-mux.c u32 mask = BIT(mux->data->gate_shift); mask 26 drivers/clk/mediatek/clk-mux.c mask, ~mask); mask 32 drivers/clk/mediatek/clk-mux.c u32 mask = BIT(mux->data->gate_shift); mask 34 drivers/clk/mediatek/clk-mux.c regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask); mask 66 drivers/clk/mediatek/clk-mux.c u32 mask = GENMASK(mux->data->mux_width - 1, 0); mask 70 drivers/clk/mediatek/clk-mux.c val = (val >> mux->data->mux_shift) & mask; mask 78 drivers/clk/mediatek/clk-mux.c u32 mask = GENMASK(mux->data->mux_width - 1, 0); mask 86 drivers/clk/mediatek/clk-mux.c regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask 100 drivers/clk/mediatek/clk-mux.c u32 mask = GENMASK(mux->data->mux_width - 1, 0); mask 110 drivers/clk/mediatek/clk-mux.c val = (orig & ~(mask << mux->data->mux_shift)) mask 115 drivers/clk/mediatek/clk-mux.c mask << mux->data->mux_shift); mask 141 drivers/clk/meson/axg-aoclk.c .mask = 0x1, mask 176 drivers/clk/meson/axg-aoclk.c .mask = 0x1, mask 195 drivers/clk/meson/axg-aoclk.c .mask = 0x1, mask 214 drivers/clk/meson/axg-aoclk.c .mask = 0x3, mask 46 drivers/clk/meson/axg-audio.c .mask = (_mask), \ mask 796 drivers/clk/meson/axg.c .mask = 0x1, mask 813 drivers/clk/meson/axg.c .mask = 0x1, mask 870 drivers/clk/meson/axg.c .mask = 0x7, mask 933 drivers/clk/meson/axg.c .mask = 0x7, mask 983 drivers/clk/meson/axg.c .mask = 0x7, mask 1048 drivers/clk/meson/axg.c .mask = 0xf, mask 149 drivers/clk/meson/clk-regmap.c val &= mux->mask; mask 160 drivers/clk/meson/clk-regmap.c mux->mask << mux->shift, mask 100 drivers/clk/meson/clk-regmap.h u32 mask; mask 160 drivers/clk/meson/g12a-aoclk.c .mask = 0x1, mask 251 drivers/clk/meson/g12a-aoclk.c .mask = 0x1, mask 286 drivers/clk/meson/g12a-aoclk.c .mask = 0x1, mask 305 drivers/clk/meson/g12a-aoclk.c .mask = 0x1, mask 324 drivers/clk/meson/g12a-aoclk.c .mask = 0x3, mask 344 drivers/clk/meson/g12a.c .mask = 0x3, mask 365 drivers/clk/meson/g12a.c .mask = 0x3, mask 411 drivers/clk/meson/g12a.c .mask = 0x1, mask 448 drivers/clk/meson/g12a.c .mask = 0x1, mask 468 drivers/clk/meson/g12a.c .mask = 0x1, mask 488 drivers/clk/meson/g12a.c .mask = 0x1, mask 508 drivers/clk/meson/g12a.c .mask = 0x1, mask 528 drivers/clk/meson/g12a.c .mask = 0x3, mask 574 drivers/clk/meson/g12a.c .mask = 0x1, mask 594 drivers/clk/meson/g12a.c .mask = 0x3, mask 632 drivers/clk/meson/g12a.c .mask = 0x1, mask 652 drivers/clk/meson/g12a.c .mask = 0x1, mask 672 drivers/clk/meson/g12a.c .mask = 0x1, mask 694 drivers/clk/meson/g12a.c .mask = 0x3, mask 714 drivers/clk/meson/g12a.c .mask = 0x3, mask 751 drivers/clk/meson/g12a.c .mask = 0x1, mask 786 drivers/clk/meson/g12a.c .mask = 0x1, mask 804 drivers/clk/meson/g12a.c .mask = 0x1, mask 822 drivers/clk/meson/g12a.c .mask = 0x1, mask 840 drivers/clk/meson/g12a.c .mask = 0x1, mask 858 drivers/clk/meson/g12a.c .mask = 0x1, mask 876 drivers/clk/meson/g12a.c .mask = 0x1, mask 894 drivers/clk/meson/g12a.c .mask = 0x1, mask 1424 drivers/clk/meson/g12a.c .mask = 7, mask 1467 drivers/clk/meson/g12a.c .mask = 7, mask 1510 drivers/clk/meson/g12a.c .mask = 7, mask 1553 drivers/clk/meson/g12a.c .mask = 7, mask 2160 drivers/clk/meson/g12a.c .mask = 0x1, mask 2417 drivers/clk/meson/g12a.c .mask = 0x7, mask 2480 drivers/clk/meson/g12a.c .mask = 0x7, mask 2529 drivers/clk/meson/g12a.c .mask = 0x7, mask 2578 drivers/clk/meson/g12a.c .mask = 0x7, mask 2655 drivers/clk/meson/g12a.c .mask = 0x1, mask 2703 drivers/clk/meson/g12a.c .mask = 0x7, mask 2747 drivers/clk/meson/g12a.c .mask = 0x7, mask 2791 drivers/clk/meson/g12a.c .mask = 1, mask 2825 drivers/clk/meson/g12a.c .mask = 0x7, mask 2875 drivers/clk/meson/g12a.c .mask = 0x7, mask 2925 drivers/clk/meson/g12a.c .mask = 0x7, mask 2988 drivers/clk/meson/g12a.c .mask = 0x3, mask 3036 drivers/clk/meson/g12a.c .mask = 0x3, mask 3084 drivers/clk/meson/g12a.c .mask = 1, mask 3131 drivers/clk/meson/g12a.c .mask = 0x7, mask 3146 drivers/clk/meson/g12a.c .mask = 0x7, mask 3509 drivers/clk/meson/g12a.c .mask = 0xf, mask 3525 drivers/clk/meson/g12a.c .mask = 0xf, mask 3541 drivers/clk/meson/g12a.c .mask = 0xf, mask 3572 drivers/clk/meson/g12a.c .mask = 0xf, mask 3661 drivers/clk/meson/g12a.c .mask = 0x3, mask 3721 drivers/clk/meson/g12a.c .mask = 0x7, mask 3769 drivers/clk/meson/g12a.c .mask = 0x7, mask 3822 drivers/clk/meson/g12a.c .mask = 1, mask 125 drivers/clk/meson/gxbb-aoclk.c .mask = 0x1, mask 158 drivers/clk/meson/gxbb-aoclk.c .mask = 0x7, mask 180 drivers/clk/meson/gxbb-aoclk.c .mask = 0x1, mask 199 drivers/clk/meson/gxbb-aoclk.c .mask = 0x1, mask 857 drivers/clk/meson/gxbb.c .mask = 0x7, mask 910 drivers/clk/meson/gxbb.c .mask = 0x3, mask 977 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1030 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1088 drivers/clk/meson/gxbb.c .mask = 1, mask 1103 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1157 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1211 drivers/clk/meson/gxbb.c .mask = 0x1, mask 1245 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1308 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1358 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1408 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1466 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1514 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1562 drivers/clk/meson/gxbb.c .mask = 1, mask 1593 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1645 drivers/clk/meson/gxbb.c .mask = 0x3, mask 1697 drivers/clk/meson/gxbb.c .mask = 1, mask 1779 drivers/clk/meson/gxbb.c .mask = 0x1, mask 1824 drivers/clk/meson/gxbb.c .mask = 0x7, mask 1844 drivers/clk/meson/gxbb.c .mask = 0x7, mask 2212 drivers/clk/meson/gxbb.c .mask = 0xf, mask 2228 drivers/clk/meson/gxbb.c .mask = 0xf, mask 2244 drivers/clk/meson/gxbb.c .mask = 0xf, mask 2275 drivers/clk/meson/gxbb.c .mask = 0xf, mask 2370 drivers/clk/meson/gxbb.c .mask = 0x3, mask 2424 drivers/clk/meson/gxbb.c .mask = 0x3, mask 2474 drivers/clk/meson/gxbb.c .mask = 0x3, mask 2540 drivers/clk/meson/gxbb.c .mask = 0xf, mask 572 drivers/clk/meson/meson8b.c .mask = 0x7, mask 628 drivers/clk/meson/meson8b.c .mask = 0x1, mask 707 drivers/clk/meson/meson8b.c .mask = 0x3, mask 733 drivers/clk/meson/meson8b.c .mask = 0x1, mask 753 drivers/clk/meson/meson8b.c .mask = 0x7, mask 902 drivers/clk/meson/meson8b.c .mask = 0x7, mask 942 drivers/clk/meson/meson8b.c .mask = 0x7, mask 982 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1022 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1061 drivers/clk/meson/meson8b.c .mask = 0x1, mask 1134 drivers/clk/meson/meson8b.c .mask = 0x3, mask 1180 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1347 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1522 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1553 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1584 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1615 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1654 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1685 drivers/clk/meson/meson8b.c .mask = 0xf, mask 1716 drivers/clk/meson/meson8b.c .mask = 0x3, mask 1788 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1843 drivers/clk/meson/meson8b.c .mask = 0x7, mask 1898 drivers/clk/meson/meson8b.c .mask = 1, mask 1992 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2007 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2063 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2078 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2134 drivers/clk/meson/meson8b.c .mask = 1, mask 2161 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2245 drivers/clk/meson/meson8b.c .mask = 0x1, mask 2264 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2314 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2364 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2414 drivers/clk/meson/meson8b.c .mask = 0x1, mask 2442 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2501 drivers/clk/meson/meson8b.c .mask = 0x3, mask 2551 drivers/clk/meson/meson8b.c .mask = 0x1, mask 38 drivers/clk/mmp/clk-gate.c tmp &= ~gate->mask; mask 64 drivers/clk/mmp/clk-gate.c tmp &= ~gate->mask; mask 86 drivers/clk/mmp/clk-gate.c return (tmp & gate->mask) == gate->val_enable; mask 97 drivers/clk/mmp/clk-gate.c void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable, mask 117 drivers/clk/mmp/clk-gate.c gate->mask = mask; mask 108 drivers/clk/mmp/clk.c clks[i].mask, mask 113 drivers/clk/mmp/clk.h u32 mask; mask 123 drivers/clk/mmp/clk.h void __iomem *reg, u32 mask, u32 val_enable, mask 186 drivers/clk/mmp/clk.h u32 mask; mask 141 drivers/clk/mvebu/armada-37xx-periph.c .mask = 3, \ mask 456 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, mask 462 drivers/clk/mvebu/armada-37xx-periph.c mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset; mask 463 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, val); mask 561 drivers/clk/mvebu/armada-37xx-periph.c unsigned int reg, mask, val, mask 577 drivers/clk/mvebu/armada-37xx-periph.c mask = ARMADA_37XX_NB_CPU_LOAD_MASK; mask 581 drivers/clk/mvebu/armada-37xx-periph.c regmap_update_bits(base, reg, mask, load_level); mask 29 drivers/clk/mvebu/clk-corediv.c unsigned int mask; mask 70 drivers/clk/mvebu/clk-corediv.c { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ mask 74 drivers/clk/mvebu/clk-corediv.c { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */ mask 134 drivers/clk/mvebu/clk-corediv.c div = (reg >> desc->offset) & desc->mask; mask 168 drivers/clk/mvebu/clk-corediv.c reg &= ~(desc->mask << desc->offset); mask 169 drivers/clk/mvebu/clk-corediv.c reg |= (div & desc->mask) << desc->offset; mask 37 drivers/clk/mvebu/dove-divider.c static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load) mask 44 drivers/clk/mvebu/dove-divider.c v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val; mask 134 drivers/clk/mvebu/dove-divider.c u32 mask, load, div; mask 145 drivers/clk/mvebu/dove-divider.c mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start; mask 149 drivers/clk/mvebu/dove-divider.c dove_load_divider(dc->base, div, mask, load); mask 181 drivers/clk/nxp/clk-lpc18xx-cgu.c .mask = 0x1f, \ mask 211 drivers/clk/nxp/clk-lpc18xx-cgu.c .mask = 0x1f, \ mask 278 drivers/clk/nxp/clk-lpc18xx-cgu.c .mask = 0x1f, \ mask 344 drivers/clk/nxp/clk-lpc32xx.c u32 mask; mask 887 drivers/clk/nxp/clk-lpc32xx.c u32 mask = BIT(clk->bit_idx); mask 888 drivers/clk/nxp/clk-lpc32xx.c u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask); mask 890 drivers/clk/nxp/clk-lpc32xx.c return regmap_update_bits(clk_regmap, clk->reg, mask, val); mask 896 drivers/clk/nxp/clk-lpc32xx.c u32 mask = BIT(clk->bit_idx); mask 897 drivers/clk/nxp/clk-lpc32xx.c u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0); mask 899 drivers/clk/nxp/clk-lpc32xx.c regmap_update_bits(clk_regmap, clk->reg, mask, val); mask 1006 drivers/clk/nxp/clk-lpc32xx.c val &= mux->mask; mask 1031 drivers/clk/nxp/clk-lpc32xx.c mux->mask << mux->shift, index << mux->shift); mask 1120 drivers/clk/nxp/clk-lpc32xx.c .mask = (_mask), \ mask 159 drivers/clk/qcom/clk-alpha-pll.c static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, mask 175 drivers/clk/qcom/clk-alpha-pll.c if (inverse && !(val & mask)) mask 177 drivers/clk/qcom/clk-alpha-pll.c else if ((val & mask) == mask) mask 211 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; mask 234 drivers/clk/qcom/clk-alpha-pll.c mask = config->main_output_mask; mask 235 drivers/clk/qcom/clk-alpha-pll.c mask |= config->aux_output_mask; mask 236 drivers/clk/qcom/clk-alpha-pll.c mask |= config->aux2_output_mask; mask 237 drivers/clk/qcom/clk-alpha-pll.c mask |= config->early_output_mask; mask 238 drivers/clk/qcom/clk-alpha-pll.c mask |= config->pre_div_mask; mask 239 drivers/clk/qcom/clk-alpha-pll.c mask |= config->post_div_mask; mask 240 drivers/clk/qcom/clk-alpha-pll.c mask |= config->vco_mask; mask 242 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); mask 304 drivers/clk/qcom/clk-alpha-pll.c static int pll_is_enabled(struct clk_hw *hw, u32 mask) mask 314 drivers/clk/qcom/clk-alpha-pll.c return !!(val & mask); mask 331 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; mask 333 drivers/clk/qcom/clk-alpha-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; mask 347 drivers/clk/qcom/clk-alpha-pll.c if ((val & mask) == mask) mask 383 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; mask 395 drivers/clk/qcom/clk-alpha-pll.c mask = PLL_OUTCTRL; mask 396 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); mask 402 drivers/clk/qcom/clk-alpha-pll.c mask = PLL_RESET_N | PLL_BYPASSNL; mask 403 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0); mask 1015 drivers/clk/qcom/clk-alpha-pll.c u32 val, mask; mask 1028 drivers/clk/qcom/clk-alpha-pll.c mask = config->post_div_mask; mask 1030 drivers/clk/qcom/clk-alpha-pll.c regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); mask 50 drivers/clk/qcom/clk-branch.c u32 mask; mask 52 drivers/clk/qcom/clk-branch.c mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT; mask 53 drivers/clk/qcom/clk-branch.c mask |= BRANCH_CLK_OFF; mask 58 drivers/clk/qcom/clk-branch.c val &= mask; mask 28 drivers/clk/qcom/clk-krait.c regval &= ~(mux->mask << mux->shift); mask 29 drivers/clk/qcom/clk-krait.c regval |= (sel & mux->mask) << mux->shift; mask 31 drivers/clk/qcom/clk-krait.c regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); mask 32 drivers/clk/qcom/clk-krait.c regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); mask 65 drivers/clk/qcom/clk-krait.c sel &= mux->mask; mask 92 drivers/clk/qcom/clk-krait.c u32 mask = BIT(d->width) - 1; mask 95 drivers/clk/qcom/clk-krait.c mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift; mask 99 drivers/clk/qcom/clk-krait.c val &= ~mask; mask 110 drivers/clk/qcom/clk-krait.c u32 mask = BIT(d->width) - 1; mask 115 drivers/clk/qcom/clk-krait.c div &= mask; mask 11 drivers/clk/qcom/clk-krait.h u32 mask; mask 28 drivers/clk/qcom/clk-pll.c u32 mask, val; mask 30 drivers/clk/qcom/clk-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; mask 36 drivers/clk/qcom/clk-pll.c if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA) mask 68 drivers/clk/qcom/clk-pll.c u32 mask; mask 75 drivers/clk/qcom/clk-pll.c mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; mask 76 drivers/clk/qcom/clk-pll.c regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); mask 222 drivers/clk/qcom/clk-pll.c u32 mask; mask 235 drivers/clk/qcom/clk-pll.c mask = config->vco_mask; mask 236 drivers/clk/qcom/clk-pll.c mask |= config->pre_div_mask; mask 237 drivers/clk/qcom/clk-pll.c mask |= config->post_div_mask; mask 238 drivers/clk/qcom/clk-pll.c mask |= config->mn_ena_mask; mask 239 drivers/clk/qcom/clk-pll.c mask |= config->main_output_mask; mask 240 drivers/clk/qcom/clk-pll.c mask |= config->aux_output_mask; mask 242 drivers/clk/qcom/clk-pll.c regmap_update_bits(regmap, pll->config_reg, mask, val); mask 27 drivers/clk/qcom/clk-rcg.c u32 mask; mask 29 drivers/clk/qcom/clk-rcg.c mask = SRC_SEL_MASK; mask 30 drivers/clk/qcom/clk-rcg.c mask <<= s->src_sel_shift; mask 31 drivers/clk/qcom/clk-rcg.c ns &= ~mask; mask 122 drivers/clk/qcom/clk-rcg.c u32 mask; mask 124 drivers/clk/qcom/clk-rcg.c mask = BIT(p->pre_div_width) - 1; mask 125 drivers/clk/qcom/clk-rcg.c mask <<= p->pre_div_shift; mask 126 drivers/clk/qcom/clk-rcg.c ns &= ~mask; mask 134 drivers/clk/qcom/clk-rcg.c u32 mask, mask_w; mask 137 drivers/clk/qcom/clk-rcg.c mask = (mask_w << mn->m_val_shift) | mask_w; mask 138 drivers/clk/qcom/clk-rcg.c md &= ~mask; mask 165 drivers/clk/qcom/clk-rcg.c u32 mask; mask 167 drivers/clk/qcom/clk-rcg.c mask = BIT(mn->width) - 1; mask 168 drivers/clk/qcom/clk-rcg.c mask <<= mn->n_val_shift; mask 169 drivers/clk/qcom/clk-rcg.c ns &= ~mask; mask 184 drivers/clk/qcom/clk-rcg.c u32 mask; mask 186 drivers/clk/qcom/clk-rcg.c mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift; mask 187 drivers/clk/qcom/clk-rcg.c mask |= BIT(mn->mnctr_en_bit); mask 188 drivers/clk/qcom/clk-rcg.c val &= ~mask; mask 478 drivers/clk/qcom/clk-rcg.c u32 mask = 0; mask 487 drivers/clk/qcom/clk-rcg.c mask = BIT(mn->mnctr_reset_bit); mask 488 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask); mask 511 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0); mask 168 drivers/clk/qcom/clk-rcg2.c u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; mask 173 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; mask 175 drivers/clk/qcom/clk-rcg2.c m &= mask; mask 178 drivers/clk/qcom/clk-rcg2.c n &= mask; mask 184 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; mask 186 drivers/clk/qcom/clk-rcg2.c hid_div &= mask; mask 266 drivers/clk/qcom/clk-rcg2.c u32 cfg, mask; mask 274 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; mask 276 drivers/clk/qcom/clk-rcg2.c RCG_M_OFFSET(rcg), mask, f->m); mask 281 drivers/clk/qcom/clk-rcg2.c RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); mask 286 drivers/clk/qcom/clk-rcg2.c RCG_D_OFFSET(rcg), mask, ~f->n); mask 291 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; mask 292 drivers/clk/qcom/clk-rcg2.c mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK; mask 298 drivers/clk/qcom/clk-rcg2.c mask, cfg); mask 417 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 437 drivers/clk/qcom/clk-rcg2.c f.pre_div &= mask; mask 462 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 486 drivers/clk/qcom/clk-rcg2.c hid_div &= mask; mask 515 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 525 drivers/clk/qcom/clk-rcg2.c div = min_t(u32, div, mask); mask 538 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 541 drivers/clk/qcom/clk-rcg2.c div = min_t(u32, div, mask); mask 571 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 582 drivers/clk/qcom/clk-rcg2.c div = min_t(u32, div, mask); mask 596 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 600 drivers/clk/qcom/clk-rcg2.c div = min_t(u32, div, mask); mask 675 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; mask 700 drivers/clk/qcom/clk-rcg2.c f.pre_div &= mask; mask 958 drivers/clk/qcom/clk-rcg2.c u32 val, mask, cfg, mode, src; mask 963 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; mask 965 drivers/clk/qcom/clk-rcg2.c if (cfg & mask) mask 966 drivers/clk/qcom/clk-rcg2.c f->pre_div = cfg & mask; mask 983 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; mask 986 drivers/clk/qcom/clk-rcg2.c val &= mask; mask 992 drivers/clk/qcom/clk-rcg2.c val &= mask; mask 1039 drivers/clk/qcom/clk-rcg2.c u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; mask 1059 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; mask 1061 drivers/clk/qcom/clk-rcg2.c if (cfg & mask) mask 1062 drivers/clk/qcom/clk-rcg2.c pre_div = cfg & mask; mask 1067 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; mask 1070 drivers/clk/qcom/clk-rcg2.c m &= mask; mask 1075 drivers/clk/qcom/clk-rcg2.c n &= mask; mask 26 drivers/clk/qcom/clk-regmap-mux-div.c u32 val, mask; mask 30 drivers/clk/qcom/clk-regmap-mux-div.c mask = ((BIT(md->hid_width) - 1) << md->hid_shift) | mask 34 drivers/clk/qcom/clk-regmap-mux-div.c mask, val); mask 22 drivers/clk/qcom/clk-regmap-mux.c unsigned int mask = GENMASK(mux->width - 1, 0); mask 28 drivers/clk/qcom/clk-regmap-mux.c val &= mask; mask 40 drivers/clk/qcom/clk-regmap-mux.c unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); mask 49 drivers/clk/qcom/clk-regmap-mux.c return regmap_update_bits(clkr->regmap, mux->reg, mask, val); mask 92 drivers/clk/qcom/common.c u32 mask; mask 100 drivers/clk/qcom/common.c mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; mask 101 drivers/clk/qcom/common.c mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; mask 102 drivers/clk/qcom/common.c regmap_update_bits(map, reg, mask, val); mask 1278 drivers/clk/qcom/gcc-ipq4019.c u32 mask; mask 1285 drivers/clk/qcom/gcc-ipq4019.c mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; mask 1287 drivers/clk/qcom/gcc-ipq4019.c pll->cdiv.reg, mask, mask 170 drivers/clk/qcom/gdsc.c u32 mask = RETAIN_MEM | RETAIN_PERIPH; mask 173 drivers/clk/qcom/gdsc.c regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask); mask 179 drivers/clk/qcom/gdsc.c u32 mask = RETAIN_MEM | RETAIN_PERIPH; mask 182 drivers/clk/qcom/gdsc.c regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0); mask 301 drivers/clk/qcom/gdsc.c u32 mask, val; mask 309 drivers/clk/qcom/gdsc.c mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK | mask 312 drivers/clk/qcom/gdsc.c ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val); mask 207 drivers/clk/qcom/gpucc-sdm845.c unsigned int value, mask; mask 219 drivers/clk/qcom/gpucc-sdm845.c mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; mask 220 drivers/clk/qcom/gpucc-sdm845.c mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; mask 222 drivers/clk/qcom/gpucc-sdm845.c regmap_update_bits(regmap, 0x1098, mask, value); mask 136 drivers/clk/qcom/krait-cc.c mux->mask = 0x3; mask 187 drivers/clk/qcom/krait-cc.c mux->mask = 0x3; mask 27 drivers/clk/qcom/reset.c u32 mask; mask 31 drivers/clk/qcom/reset.c mask = BIT(map->bit); mask 33 drivers/clk/qcom/reset.c return regmap_update_bits(rst->regmap, map->reg, mask, mask); mask 41 drivers/clk/qcom/reset.c u32 mask; mask 45 drivers/clk/qcom/reset.c mask = BIT(map->bit); mask 47 drivers/clk/qcom/reset.c return regmap_update_bits(rst->regmap, map->reg, mask, 0); mask 155 drivers/clk/renesas/clk-div6.c u32 mask; mask 160 drivers/clk/renesas/clk-div6.c mask = ~((BIT(clock->src_width) - 1) << clock->src_shift); mask 163 drivers/clk/renesas/clk-div6.c writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift), mask 97 drivers/clk/renesas/rcar-gen3-cpg.c unsigned long mask; mask 110 drivers/clk/renesas/rcar-gen3-cpg.c val = readl(zclk->reg) & zclk->mask; mask 111 drivers/clk/renesas/rcar-gen3-cpg.c mult = 32 - (val >> __ffs(zclk->mask)); mask 145 drivers/clk/renesas/rcar-gen3-cpg.c cpg_reg_modify(zclk->reg, zclk->mask, mask 146 drivers/clk/renesas/rcar-gen3-cpg.c ((32 - mult) << __ffs(zclk->mask)) & zclk->mask); mask 202 drivers/clk/renesas/rcar-gen3-cpg.c zclk->mask = GENMASK(offset + 4, offset); mask 141 drivers/clk/renesas/renesas-cpg-mssr.c u32 mask; mask 441 drivers/clk/renesas/renesas-cpg-mssr.c priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32); mask 802 drivers/clk/renesas/renesas-cpg-mssr.c if (priv->smstpcr_saved[reg].mask) mask 817 drivers/clk/renesas/renesas-cpg-mssr.c u32 mask, oldval, newval; mask 828 drivers/clk/renesas/renesas-cpg-mssr.c mask = priv->smstpcr_saved[reg].mask; mask 829 drivers/clk/renesas/renesas-cpg-mssr.c if (!mask) mask 836 drivers/clk/renesas/renesas-cpg-mssr.c newval = oldval & ~mask; mask 837 drivers/clk/renesas/renesas-cpg-mssr.c newval |= priv->smstpcr_saved[reg].val & mask; mask 851 drivers/clk/renesas/renesas-cpg-mssr.c mask &= ~priv->smstpcr_saved[reg].val; mask 852 drivers/clk/renesas/renesas-cpg-mssr.c if (!mask) mask 857 drivers/clk/renesas/renesas-cpg-mssr.c if (!(oldval & mask)) mask 864 drivers/clk/renesas/renesas-cpg-mssr.c priv->base + SMSTPCR(reg), oldval & mask); mask 184 drivers/clk/rockchip/clk-half-divider.c mux->mask = BIT(mux_width) - 1; mask 24 drivers/clk/rockchip/clk-muxgrf.c unsigned int mask = GENMASK(mux->width - 1, 0); mask 30 drivers/clk/rockchip/clk-muxgrf.c val &= mask; mask 38 drivers/clk/rockchip/clk-muxgrf.c unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); mask 45 drivers/clk/rockchip/clk-muxgrf.c return regmap_write(mux->regmap, mux->reg, val | (mask << 16)); mask 47 drivers/clk/rockchip/clk-muxgrf.c return regmap_update_bits(mux->regmap, mux->reg, mask, val); mask 865 drivers/clk/rockchip/clk-pll.c pll_mux->mask = PLL_RK3328_MODE_MASK; mask 867 drivers/clk/rockchip/clk-pll.c pll_mux->mask = PLL_MODE_MASK; mask 61 drivers/clk/rockchip/clk.c mux->mask = BIT(mux_width) - 1; mask 281 drivers/clk/rockchip/clk.c frac_mux->mask = BIT(child->mux_width) - 1; mask 25 drivers/clk/rockchip/clk.h #define HIWORD_UPDATE(val, mask, shift) \ mask 26 drivers/clk/rockchip/clk.h ((val) << (shift) | (mask) << ((shift) + 16)) mask 69 drivers/clk/samsung/clk-cpu.c static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) mask 74 drivers/clk/samsung/clk-cpu.c if (!(readl(div_reg) & mask)) mask 78 drivers/clk/samsung/clk-cpu.c if (!(readl(div_reg) & mask)) mask 138 drivers/clk/samsung/clk-cpu.c unsigned long mask) mask 143 drivers/clk/samsung/clk-cpu.c div0 = (div0 & ~mask) | (div & mask); mask 145 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask); mask 266 drivers/clk/samsung/clk-cpu.c unsigned long mask) mask 271 drivers/clk/samsung/clk-cpu.c div0 = (div0 & ~mask) | (div & mask); mask 273 drivers/clk/samsung/clk-cpu.c wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask); mask 97 drivers/clk/samsung/clk-exynos-clkout.c clkout->mux.mask = mux_mask; mask 26 drivers/clk/samsung/clk-exynos5-subcmu.c writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); mask 27 drivers/clk/samsung/clk-exynos5-subcmu.c rd->save &= rd->mask; mask 36 drivers/clk/samsung/clk-exynos5-subcmu.c writel((readl(base + rd->offset) & ~rd->mask) | rd->save, mask 9 drivers/clk/samsung/clk-exynos5-subcmu.h u32 mask; mask 53 drivers/clk/samsung/clk-s3c2410-dclk.c u32 mask; mask 67 drivers/clk/samsung/clk-s3c2410-dclk.c val &= clkout->mask; mask 79 drivers/clk/samsung/clk-s3c2410-dclk.c s3c2410_modify_misccr((clkout->mask << clkout->shift), mask 93 drivers/clk/samsung/clk-s3c2410-dclk.c u8 shift, u32 mask) mask 111 drivers/clk/samsung/clk-s3c2410-dclk.c clkout->mask = mask; mask 47 drivers/clk/socfpga/clk-gate-s10.c u32 mask; mask 51 drivers/clk/socfpga/clk-gate-s10.c mask = (0x1 << socfpgaclk->bypass_shift); mask 52 drivers/clk/socfpga/clk-gate-s10.c parent = ((readl(socfpgaclk->bypass_reg) & mask) >> mask 51 drivers/clk/socfpga/clk-periph-s10.c u32 clk_src, mask; mask 55 drivers/clk/socfpga/clk-periph-s10.c mask = (0x1 << socfpgaclk->bypass_shift); mask 56 drivers/clk/socfpga/clk-periph-s10.c parent = ((readl(socfpgaclk->bypass_reg) & mask) >> mask 71 drivers/clk/sprd/pll.c u32 shift, mask, index, refin_id = 3; mask 77 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_REFIN); mask 78 drivers/clk/sprd/pll.c refin_id = (sprd_pll_read(pll, index) & mask) >> shift; mask 101 drivers/clk/sprd/pll.c u32 i, mask, regs_num = pll->regs_num; mask 130 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_KINT); mask 135 drivers/clk/sprd/pll.c ((mask >> __ffs(mask)) + 1)) * mask 143 drivers/clk/sprd/pll.c #define SPRD_PLL_WRITE_CHECK(pll, i, mask, val) \ mask 144 drivers/clk/sprd/pll.c (((sprd_pll_read(pll, i) & mask) == val) ? 0 : (-EFAULT)) mask 152 drivers/clk/sprd/pll.c u32 mask, shift, width, ibias_val, index; mask 163 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_PREDIV); mask 166 drivers/clk/sprd/pll.c if (width && (sprd_pll_read(pll, index) & mask)) mask 169 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_POSTDIV); mask 172 drivers/clk/sprd/pll.c cfg[index].msk = mask; mask 175 drivers/clk/sprd/pll.c cfg[index].val |= mask; mask 180 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_DIV_S); mask 182 drivers/clk/sprd/pll.c cfg[index].val |= mask; mask 183 drivers/clk/sprd/pll.c cfg[index].msk |= mask; mask 185 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_SDM_EN); mask 187 drivers/clk/sprd/pll.c cfg[index].val |= mask; mask 188 drivers/clk/sprd/pll.c cfg[index].msk |= mask; mask 191 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_NINT); mask 194 drivers/clk/sprd/pll.c cfg[index].val |= (nint << shift) & mask; mask 195 drivers/clk/sprd/pll.c cfg[index].msk |= mask; mask 197 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_KINT); mask 202 drivers/clk/sprd/pll.c tmp = do_div(tmp, 10000) * ((mask >> shift) + 1); mask 204 drivers/clk/sprd/pll.c cfg[index].val |= (kint << shift) & mask; mask 205 drivers/clk/sprd/pll.c cfg[index].msk |= mask; mask 209 drivers/clk/sprd/pll.c mask = pmask(pll, PLL_IBIAS); mask 212 drivers/clk/sprd/pll.c cfg[index].val |= ibias_val << shift & mask; mask 213 drivers/clk/sprd/pll.c cfg[index].msk |= mask; mask 224 drivers/clk/st/clk-flexgen.c fgxbar->mux.mask = BIT(6) - 1; mask 195 drivers/clk/st/clkgen-pll.c !!((reg >> field->shift) & field->mask), 0, 10000); mask 669 drivers/clk/st/clkgen-pll.c div->width = fls(pll_data->odf[odf].mask); mask 17 drivers/clk/st/clkgen.h unsigned int mask; mask 24 drivers/clk/st/clkgen.h return (readl(base + field->offset) >> field->shift) & field->mask; mask 32 drivers/clk/st/clkgen.h ~(field->mask << field->shift)) | (val << field->shift), mask 40 drivers/clk/st/clkgen.h .mask = _mask, \ mask 51 drivers/clk/sunxi/clk-a10-mod1.c mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1; mask 86 drivers/clk/sunxi/clk-a20-gmac.c mux->mask = SUN7I_A20_GMAC_MASK; mask 75 drivers/clk/sunxi/clk-factors.c factors->mux->mask; mask 240 drivers/clk/sunxi/clk-factors.c mux->mask = data->muxmask; mask 135 drivers/clk/sunxi/clk-sun4i-display.c mux->mask = (1 << data->width_mux) - 1; mask 19 drivers/clk/sunxi/clk-sun6i-apb0-gates.c DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE); mask 23 drivers/clk/sunxi/clk-sun6i-apb0-gates.c .mask = {0x7F}, mask 27 drivers/clk/sunxi/clk-sun6i-apb0-gates.c .mask = {0x5D}, mask 73 drivers/clk/sunxi/clk-sun6i-apb0-gates.c ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE); mask 79 drivers/clk/sunxi/clk-sun6i-apb0-gates.c for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) { mask 73 drivers/clk/sunxi/clk-sun8i-mbus.c mux->mask = SUN8I_MBUS_MUX_MASK; mask 214 drivers/clk/sunxi/clk-sun9i-cpus.c mux->mask = SUN9I_CPUS_MUX_MASK >> SUN9I_CPUS_MUX_SHIFT; mask 863 drivers/clk/sunxi/clk-sunxi.c DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); mask 20 drivers/clk/tegra/clk-periph-fixed.c u32 mask = 1 << (fixed->num % 32), value; mask 23 drivers/clk/tegra/clk-periph-fixed.c if (value & mask) { mask 25 drivers/clk/tegra/clk-periph-fixed.c if ((value & mask) == 0) mask 35 drivers/clk/tegra/clk-periph-fixed.c u32 mask = 1 << (fixed->num % 32); mask 37 drivers/clk/tegra/clk-periph-fixed.c writel(mask, fixed->base + fixed->regs->enb_set_reg); mask 45 drivers/clk/tegra/clk-periph-fixed.c u32 mask = 1 << (fixed->num % 32); mask 47 drivers/clk/tegra/clk-periph-fixed.c writel(mask, fixed->base + fixed->regs->enb_clr_reg); mask 245 drivers/clk/tegra/clk-pll.c #define divm_mask(p) mask(p->params->div_nmp->divm_width) mask 246 drivers/clk/tegra/clk-pll.c #define divn_mask(p) mask(p->params->div_nmp->divn_width) mask 248 drivers/clk/tegra/clk-pll.c mask(p->params->div_nmp->divp_width)) mask 663 drivers/clk/tegra/clk-tegra210.c u8 misc_num, u32 default_val, u32 mask) mask 667 drivers/clk/tegra/clk-tegra210.c boot_val &= mask; mask 668 drivers/clk/tegra/clk-tegra210.c default_val &= mask; mask 672 drivers/clk/tegra/clk-tegra210.c pr_warn(" (comparison mask = 0x%x)\n", mask); mask 756 drivers/clk/tegra/clk-tegra210.c u32 mask; mask 774 drivers/clk/tegra/clk-tegra210.c mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; mask 776 drivers/clk/tegra/clk-tegra210.c ~mask & PLLA_MISC0_WRITE_MASK); mask 784 drivers/clk/tegra/clk-tegra210.c val &= ~mask; mask 785 drivers/clk/tegra/clk-tegra210.c val |= PLLA_MISC0_DEFAULT_VALUE & mask; mask 809 drivers/clk/tegra/clk-tegra210.c u32 mask = 0xffff; mask 826 drivers/clk/tegra/clk-tegra210.c mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | mask 829 drivers/clk/tegra/clk-tegra210.c ~mask & PLLD_MISC0_WRITE_MASK); mask 835 drivers/clk/tegra/clk-tegra210.c mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; mask 837 drivers/clk/tegra/clk-tegra210.c val &= ~mask; mask 838 drivers/clk/tegra/clk-tegra210.c val |= PLLD_MISC0_DEFAULT_VALUE & mask; mask 981 drivers/clk/tegra/clk-tegra210.c u32 mask; mask 1002 drivers/clk/tegra/clk-tegra210.c mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; mask 1004 drivers/clk/tegra/clk-tegra210.c ~mask & PLLRE_MISC0_WRITE_MASK); mask 1012 drivers/clk/tegra/clk-tegra210.c val &= ~mask; mask 1013 drivers/clk/tegra/clk-tegra210.c val |= PLLRE_MISC0_DEFAULT_VALUE & mask; mask 1160 drivers/clk/tegra/clk-tegra210.c u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); mask 1171 drivers/clk/tegra/clk-tegra210.c mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; mask 1173 drivers/clk/tegra/clk-tegra210.c ~mask & PLLMB_MISC1_WRITE_MASK); mask 1179 drivers/clk/tegra/clk-tegra210.c val &= ~mask; mask 1180 drivers/clk/tegra/clk-tegra210.c val |= PLLMB_MISC1_DEFAULT_VALUE & mask; mask 1201 drivers/clk/tegra/clk-tegra210.c u32 val, mask; mask 1205 drivers/clk/tegra/clk-tegra210.c mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; mask 1207 drivers/clk/tegra/clk-tegra210.c mask |= PLLP_MISC0_IDDQ; mask 1209 drivers/clk/tegra/clk-tegra210.c ~mask & PLLP_MISC0_WRITE_MASK); mask 1213 drivers/clk/tegra/clk-tegra210.c mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; mask 1215 drivers/clk/tegra/clk-tegra210.c ~mask & PLLP_MISC1_WRITE_MASK); mask 1220 drivers/clk/tegra/clk-tegra210.c u32 mask; mask 1237 drivers/clk/tegra/clk-tegra210.c mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; mask 1238 drivers/clk/tegra/clk-tegra210.c val &= ~mask; mask 1239 drivers/clk/tegra/clk-tegra210.c val |= PLLP_MISC0_DEFAULT_VALUE & mask; mask 1252 drivers/clk/tegra/clk-tegra210.c mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; mask 1253 drivers/clk/tegra/clk-tegra210.c val &= mask; mask 1254 drivers/clk/tegra/clk-tegra210.c val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; mask 1268 drivers/clk/tegra/clk-tegra210.c u32 val, mask; mask 1272 drivers/clk/tegra/clk-tegra210.c mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); mask 1274 drivers/clk/tegra/clk-tegra210.c ~mask & PLLU_MISC0_WRITE_MASK); mask 1277 drivers/clk/tegra/clk-tegra210.c mask = PLLU_MISC1_LOCK_OVERRIDE; mask 1279 drivers/clk/tegra/clk-tegra210.c ~mask & PLLU_MISC1_WRITE_MASK); mask 1322 drivers/clk/tegra/clk-tegra210.c #define divm_mask(p) mask(p->params->div_nmp->divm_width) mask 1323 drivers/clk/tegra/clk-tegra210.c #define divn_mask(p) mask(p->params->div_nmp->divn_width) mask 1325 drivers/clk/tegra/clk-tegra210.c mask(p->params->div_nmp->divp_width)) mask 1337 drivers/clk/tegra/clk-tegra210.c u32 reg, u32 mask) mask 1345 drivers/clk/tegra/clk-tegra210.c if ((val & mask) == mask) { mask 589 drivers/clk/tegra/clk.h .mask = _mux_mask, \ mask 60 drivers/clk/ti/clk.c static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr) mask 65 drivers/clk/ti/clk.c v &= ~mask; mask 70 drivers/clk/ti/clk.c static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) mask 75 drivers/clk/ti/clk.c _clk_rmw(val, mask, reg->ptr); mask 77 drivers/clk/ti/clk.c regmap_update_bits(io->regmap, reg->offset, mask, val); mask 79 drivers/clk/ti/clk.c _clk_rmw(val, mask, io->mem + reg->offset); mask 346 drivers/clk/ti/clkctrl.c mux->mask = num_parents; mask 348 drivers/clk/ti/clkctrl.c mux->mask--; mask 350 drivers/clk/ti/clkctrl.c mux->mask = (1 << fls(mux->mask)) - 1; mask 60 drivers/clk/ti/clkt_dflt.c u32 mask, u8 idlest, const char *name) mask 64 drivers/clk/ti/clkt_dflt.c ena = (idlest) ? 0 : mask; mask 68 drivers/clk/ti/clkt_dflt.c if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) mask 183 drivers/clk/ti/clkt_dpll.c u8 mask, val; mask 185 drivers/clk/ti/clkt_dpll.c mask = ti_clk_get_features()->dpll_bypass_vals; mask 192 drivers/clk/ti/clkt_dpll.c while (mask) { mask 193 drivers/clk/ti/clkt_dpll.c val = __ffs(mask); mask 194 drivers/clk/ti/clkt_dpll.c mask ^= (1 << val); mask 36 drivers/clk/ti/clock.h u32 mask; mask 40 drivers/clk/ti/dpll44xx.c u32 mask; mask 45 drivers/clk/ti/dpll44xx.c mask = clk->flags & CLOCK_CLKOUTX2 ? mask 51 drivers/clk/ti/dpll44xx.c v &= ~mask; mask 58 drivers/clk/ti/dpll44xx.c u32 mask; mask 63 drivers/clk/ti/dpll44xx.c mask = clk->flags & CLOCK_CLKOUTX2 ? mask 69 drivers/clk/ti/dpll44xx.c v |= mask; mask 43 drivers/clk/ti/mux.c val &= mux->mask; mask 82 drivers/clk/ti/mux.c val = mux->mask << (mux->shift + 16); mask 85 drivers/clk/ti/mux.c val &= ~(mux->mask << mux->shift); mask 132 drivers/clk/ti/mux.c struct clk_omap_reg *reg, u8 shift, u32 mask, mask 153 drivers/clk/ti/mux.c mux->mask = mask; mask 180 drivers/clk/ti/mux.c u32 mask = 0; mask 210 drivers/clk/ti/mux.c mask = num_parents; mask 212 drivers/clk/ti/mux.c mask--; mask 214 drivers/clk/ti/mux.c mask = (1 << fls(mask)) - 1; mask 217 drivers/clk/ti/mux.c flags, ®, shift, mask, latch, clk_mux_flags, mask 251 drivers/clk/ti/mux.c mux->mask = num_parents - 1; mask 252 drivers/clk/ti/mux.c mux->mask = (1 << fls(mux->mask)) - 1; mask 283 drivers/clk/ti/mux.c mux->mask = num_parents - 1; mask 284 drivers/clk/ti/mux.c mux->mask = (1 << fls(mux->mask)) - 1; mask 22 drivers/clk/uniphier/clk-uniphier-cpugear.c unsigned int mask; mask 36 drivers/clk/uniphier/clk-uniphier-cpugear.c gear->mask, index); mask 65 drivers/clk/uniphier/clk-uniphier-cpugear.c val &= gear->mask; mask 97 drivers/clk/uniphier/clk-uniphier-cpugear.c gear->mask = data->mask; mask 29 drivers/clk/uniphier/clk-uniphier.h unsigned int mask; mask 79 drivers/clk/uniphier/clk-uniphier.h .mask = (_mask) \ mask 165 drivers/clk/versatile/clk-icst.c u32 mask; mask 172 drivers/clk/versatile/clk-icst.c mask = INTEGRATOR_AP_CM_BITS; mask 182 drivers/clk/versatile/clk-icst.c mask = INTEGRATOR_AP_SYS_BITS; mask 192 drivers/clk/versatile/clk-icst.c mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */ mask 200 drivers/clk/versatile/clk-icst.c mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */ mask 209 drivers/clk/versatile/clk-icst.c mask = VERSATILE_AUX_OSC_BITS; mask 220 drivers/clk/versatile/clk-icst.c ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val); mask 92 drivers/clk/x86/clk-pmc-atom.c static void plt_clk_reg_update(struct clk_plt *clk, u32 mask, u32 val) mask 100 drivers/clk/x86/clk-pmc-atom.c tmp = (tmp & ~mask) | (val & mask); mask 102 drivers/clk/zte/clk.h .mask = BIT(_width) - 1, \ mask 69 drivers/clocksource/acpi_pm.c .mask = (u64)ACPI_PM_MASK, mask 99 drivers/clocksource/arc_timer.c .mask = CLOCKSOURCE_MASK(64), mask 157 drivers/clocksource/arc_timer.c .mask = CLOCKSOURCE_MASK(64), mask 210 drivers/clocksource/arc_timer.c .mask = CLOCKSOURCE_MASK(32), mask 192 drivers/clocksource/arm_arch_timer.c .mask = CLOCKSOURCE_MASK(56), mask 198 drivers/clocksource/arm_arch_timer.c .mask = CLOCKSOURCE_MASK(56), mask 1177 drivers/clocksource/arm_arch_timer.c unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM; mask 1180 drivers/clocksource/arm_arch_timer.c if ((arch_timers_present & mask) == mask) mask 214 drivers/clocksource/arm_global_timer.c .mask = CLOCKSOURCE_MASK(64), mask 48 drivers/clocksource/clksrc-dbx500-prcmu.c .mask = CLOCKSOURCE_MASK(32), mask 396 drivers/clocksource/dw_apb_timer.c dw_cs->cs.mask = CLOCKSOURCE_MASK(32); mask 219 drivers/clocksource/em_sti.c cs->mask = CLOCKSOURCE_MASK(48); mask 89 drivers/clocksource/exynos_mct.c u32 mask; mask 98 drivers/clocksource/exynos_mct.c mask = 1 << 3; /* L_TCON write status */ mask 101 drivers/clocksource/exynos_mct.c mask = 1 << 1; /* L_ICNTB write status */ mask 104 drivers/clocksource/exynos_mct.c mask = 1 << 0; /* L_TCNTB write status */ mask 113 drivers/clocksource/exynos_mct.c mask = 1 << 16; /* G_TCON write status */ mask 117 drivers/clocksource/exynos_mct.c mask = 1 << 0; /* G_COMP0_L write status */ mask 121 drivers/clocksource/exynos_mct.c mask = 1 << 1; /* G_COMP0_U write status */ mask 125 drivers/clocksource/exynos_mct.c mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ mask 129 drivers/clocksource/exynos_mct.c mask = 1 << 0; /* G_CNT_L write status */ mask 133 drivers/clocksource/exynos_mct.c mask = 1 << 1; /* G_CNT_U write status */ mask 142 drivers/clocksource/exynos_mct.c if (readl_relaxed(reg_base + stat_addr) & mask) { mask 143 drivers/clocksource/exynos_mct.c writel_relaxed(mask, reg_base + stat_addr); mask 211 drivers/clocksource/exynos_mct.c .mask = CLOCKSOURCE_MASK(32), mask 355 drivers/clocksource/exynos_mct.c unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; mask 359 drivers/clocksource/exynos_mct.c if (tmp & mask) { mask 360 drivers/clocksource/exynos_mct.c tmp &= ~mask; mask 122 drivers/clocksource/h8300_timer16.c .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8), mask 115 drivers/clocksource/h8300_tpu.c .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8), mask 244 drivers/clocksource/hyperv_timer.c .mask = CLOCKSOURCE_MASK(64), mask 270 drivers/clocksource/hyperv_timer.c .mask = CLOCKSOURCE_MASK(64), mask 101 drivers/clocksource/i8253.c .mask = CLOCKSOURCE_MASK(32), mask 205 drivers/clocksource/ingenic-timer.c cs->mask = CLOCKSOURCE_MASK(16); mask 174 drivers/clocksource/mips-gic-timer.c gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); mask 27 drivers/clocksource/mmio.c return ~(u64)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask; mask 37 drivers/clocksource/mmio.c return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask; mask 66 drivers/clocksource/mmio.c cs->clksrc.mask = CLOCKSOURCE_MASK(bits); mask 189 drivers/clocksource/mxs_timer.c .mask = CLOCKSOURCE_MASK(16), mask 24 drivers/clocksource/numachip.c .mask = CLOCKSOURCE_MASK(64), mask 227 drivers/clocksource/samsung_pwm_timer.c u32 mask = (1 << pwm.event_id); mask 228 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); mask 250 drivers/clocksource/samsung_pwm_timer.c u32 mask = (1 << pwm.event_id); mask 251 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); mask 288 drivers/clocksource/samsung_pwm_timer.c u32 mask = (1 << pwm.event_id); mask 289 drivers/clocksource/samsung_pwm_timer.c writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT); mask 356 drivers/clocksource/samsung_pwm_timer.c samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); mask 379 drivers/clocksource/samsung_pwm_timer.c u8 mask; mask 382 drivers/clocksource/samsung_pwm_timer.c mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1); mask 383 drivers/clocksource/samsung_pwm_timer.c channel = fls(mask) - 1; mask 390 drivers/clocksource/samsung_pwm_timer.c mask &= ~(1 << channel); mask 391 drivers/clocksource/samsung_pwm_timer.c channel = fls(mask) - 1; mask 52 drivers/clocksource/scx200_hrt.c .mask = CLOCKSOURCE_MASK(32), mask 683 drivers/clocksource/sh_cmt.c cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8); mask 961 drivers/clocksource/sh_cmt.c unsigned int mask; mask 1023 drivers/clocksource/sh_cmt.c for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { mask 1024 drivers/clocksource/sh_cmt.c unsigned int hwidx = ffs(mask) - 1; mask 1033 drivers/clocksource/sh_cmt.c mask &= ~(1 << hwidx); mask 320 drivers/clocksource/sh_tmu.c cs->mask = CLOCKSOURCE_MASK(32); mask 155 drivers/clocksource/timer-atlas7.c .mask = CLOCKSOURCE_MASK(64), mask 221 drivers/clocksource/timer-atmel-pit.c data->clksrc.mask = CLOCKSOURCE_MASK(bits); mask 91 drivers/clocksource/timer-atmel-st.c .mask = CLOCKSOURCE_MASK(20), mask 113 drivers/clocksource/timer-atmel-tcb.c .mask = CLOCKSOURCE_MASK(32), mask 351 drivers/clocksource/timer-cadence-ttc.c ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); mask 307 drivers/clocksource/timer-davinci.c davinci_clocksource.dev.mask = mask 74 drivers/clocksource/timer-keystone.c static int keystone_timer_config(u64 period, int mask) mask 83 drivers/clocksource/timer-keystone.c tcr |= mask; mask 113 drivers/clocksource/timer-mp-csky.c .mask = CLOCKSOURCE_MASK(32), mask 145 drivers/clocksource/timer-pistachio.c .mask = CLOCKSOURCE_MASK(32), mask 161 drivers/clocksource/timer-prima2.c .mask = CLOCKSOURCE_MASK(64), mask 92 drivers/clocksource/timer-qcom.c .mask = CLOCKSOURCE_MASK(32), mask 174 drivers/clocksource/timer-rda.c .mask = CLOCKSOURCE_MASK(64), mask 52 drivers/clocksource/timer-riscv.c .mask = CLOCKSOURCE_MASK(64), mask 166 drivers/clocksource/timer-sprd.c TIMER_VALUE_SHDW_LO) & cs->mask; mask 189 drivers/clocksource/timer-sprd.c .mask = CLOCKSOURCE_MASK(32), mask 229 drivers/clocksource/timer-sun5i.c cs->clksrc.mask = CLOCKSOURCE_MASK(32); mask 208 drivers/clocksource/timer-tegra.c .mask = CLOCKSOURCE_MASK(32), mask 69 drivers/clocksource/timer-ti-32k.c .mask = CLOCKSOURCE_MASK(32), mask 683 drivers/clocksource/timer-ti-dm.c static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) mask 685 drivers/clocksource/timer-ti-dm.c u32 l = mask; mask 693 drivers/clocksource/timer-ti-dm.c l = readl_relaxed(timer->irq_ena) & ~mask; mask 696 drivers/clocksource/timer-ti-dm.c l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; mask 700 drivers/clocksource/timer-ti-dm.c timer->context.tier &= ~mask; mask 701 drivers/clocksource/timer-ti-dm.c timer->context.twer &= ~mask; mask 57 drivers/clocksource/timer-vt8500.c .mask = CLOCKSOURCE_MASK(32), mask 96 drivers/counter/104-quad-8.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) mask 105 drivers/counter/104-quad-8.c switch (mask) { mask 145 drivers/counter/104-quad-8.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 152 drivers/counter/104-quad-8.c switch (mask) { mask 18 drivers/counter/ftm-quaddec.c #define FTM_FIELD_UPDATE(ftm, offset, mask, val) \ mask 22 drivers/counter/ftm-quaddec.c flags &= ~mask; \ mask 23 drivers/counter/ftm-quaddec.c flags |= FIELD_PREP(mask, val); \ mask 96 drivers/counter/stm32-lptimer-cnt.c u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE | mask 107 drivers/counter/stm32-lptimer-cnt.c return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val); mask 112 drivers/counter/stm32-lptimer-cnt.c int val, int val2, long mask) mask 117 drivers/counter/stm32-lptimer-cnt.c switch (mask) { mask 141 drivers/counter/stm32-lptimer-cnt.c int *val, int *val2, long mask) mask 147 drivers/counter/stm32-lptimer-cnt.c switch (mask) { mask 302 drivers/cpufreq/acpi-cpufreq.c static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) mask 311 drivers/cpufreq/acpi-cpufreq.c err = smp_call_function_any(mask, do_drv_read, &cmd, 1); mask 325 drivers/cpufreq/acpi-cpufreq.c const struct cpumask *mask, u32 val) mask 336 drivers/cpufreq/acpi-cpufreq.c if (cpumask_test_cpu(this_cpu, mask)) mask 339 drivers/cpufreq/acpi-cpufreq.c smp_call_function_many(mask, do_drv_write, &cmd, 1); mask 343 drivers/cpufreq/acpi-cpufreq.c static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) mask 347 drivers/cpufreq/acpi-cpufreq.c if (unlikely(cpumask_empty(mask))) mask 350 drivers/cpufreq/acpi-cpufreq.c val = drv_read(data, mask); mask 390 drivers/cpufreq/acpi-cpufreq.c const struct cpumask *mask, unsigned int freq) mask 397 drivers/cpufreq/acpi-cpufreq.c cur_freq = extract_freq(policy, get_cur_val(mask, data)); mask 410 drivers/cpufreq/acpi-cpufreq.c const struct cpumask *mask; mask 436 drivers/cpufreq/acpi-cpufreq.c mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? mask 439 drivers/cpufreq/acpi-cpufreq.c drv_write(data, mask, perf->states[next_perf_state].control); mask 442 drivers/cpufreq/acpi-cpufreq.c if (!check_freqs(policy, mask, mask 129 drivers/cpufreq/armada-37xx-cpufreq.c unsigned int reg, mask, val, offset = 0; mask 142 drivers/cpufreq/armada-37xx-cpufreq.c mask = (ARMADA_37XX_NB_CLK_SEL_MASK mask 150 drivers/cpufreq/armada-37xx-cpufreq.c mask |= (ARMADA_37XX_NB_TBG_DIV_MASK mask 155 drivers/cpufreq/armada-37xx-cpufreq.c mask |= (ARMADA_37XX_NB_VDD_SEL_MASK mask 159 drivers/cpufreq/armada-37xx-cpufreq.c mask <<= offset; mask 161 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); mask 296 drivers/cpufreq/armada-37xx-cpufreq.c mask = ARMADA_37XX_NB_DFS_EN; mask 298 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, 0); mask 304 drivers/cpufreq/armada-37xx-cpufreq.c mask = ARMADA_37XX_NB_CPU_LOAD_MASK; mask 308 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, val); mask 312 drivers/cpufreq/armada-37xx-cpufreq.c mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN | mask 316 drivers/cpufreq/armada-37xx-cpufreq.c regmap_update_bits(base, reg, mask, mask); mask 824 drivers/cpufreq/cpufreq.c ssize_t cpufreq_show_cpus(const struct cpumask *mask, char *buf) mask 829 drivers/cpufreq/cpufreq.c for_each_cpu(cpu, mask) { mask 69 drivers/cpufreq/intel_pstate.c int mask, ret; mask 72 drivers/cpufreq/intel_pstate.c mask = (1 << FRAC_BITS) - 1; mask 73 drivers/cpufreq/intel_pstate.c if (x & mask) mask 134 drivers/cpufreq/powernv-cpufreq.c cpumask_t mask; mask 906 drivers/cpufreq/powernv-cpufreq.c cpumask_t mask; mask 909 drivers/cpufreq/powernv-cpufreq.c cpumask_and(&mask, &chip->mask, cpu_online_mask); mask 910 drivers/cpufreq/powernv-cpufreq.c smp_call_function_any(&mask, mask 917 drivers/cpufreq/powernv-cpufreq.c for_each_cpu(cpu, &mask) { mask 924 drivers/cpufreq/powernv-cpufreq.c cpumask_andnot(&mask, &mask, policy.cpus); mask 1070 drivers/cpufreq/powernv-cpufreq.c cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i])); mask 1072 drivers/cpufreq/powernv-cpufreq.c for_each_cpu(cpu, &chips[i].mask) mask 114 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK; mask 129 drivers/cpufreq/pxa3xx-cpufreq.c while ((ACSR & mask) != (accr & mask)) mask 135 drivers/cpufreq/pxa3xx-cpufreq.c uint32_t mask; mask 138 drivers/cpufreq/pxa3xx-cpufreq.c mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK | mask 141 drivers/cpufreq/pxa3xx-cpufreq.c accr &= ~mask; mask 147 drivers/cpufreq/pxa3xx-cpufreq.c while ((ACSR & mask) != (accr & mask)) mask 41 drivers/cpuidle/cpuidle-powernv.c u64 mask; mask 148 drivers/cpuidle/cpuidle-powernv.c stop_psscr_table[index].mask); mask 247 drivers/cpuidle/cpuidle-powernv.c stop_psscr_table[index].mask = psscr_mask; mask 2390 drivers/crypto/atmel-aes.c dma_cap_mask_t mask; mask 2392 drivers/crypto/atmel-aes.c dma_cap_zero(mask); mask 2393 drivers/crypto/atmel-aes.c dma_cap_set(DMA_SLAVE, mask); mask 2397 drivers/crypto/atmel-aes.c dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, mask 2403 drivers/crypto/atmel-aes.c dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter, mask 720 drivers/crypto/atmel-tdes.c dma_cap_mask_t mask; mask 722 drivers/crypto/atmel-tdes.c dma_cap_zero(mask); mask 723 drivers/crypto/atmel-tdes.c dma_cap_set(DMA_SLAVE, mask); mask 726 drivers/crypto/atmel-tdes.c dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask, mask 742 drivers/crypto/atmel-tdes.c dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask, mask 864 drivers/crypto/cavium/zip/zip_regs.h u64 mask : 1; mask 870 drivers/crypto/cavium/zip/zip_regs.h u64 mask : 1; mask 23 drivers/crypto/ccp/ccp-dmaengine.c u64 mask = _mask + 1; \ mask 24 drivers/crypto/ccp/ccp-dmaengine.c (mask == 0) ? 64 : fls64(mask); \ mask 1950 drivers/crypto/ccp/ccp-ops.c struct ccp_dm_workarea mask; mask 1966 drivers/crypto/ccp/ccp-ops.c if (!pt->mask) mask 1980 drivers/crypto/ccp/ccp-ops.c ret = ccp_init_dm_workarea(&mask, cmd_q, mask 1987 drivers/crypto/ccp/ccp-ops.c ret = ccp_set_dm_area(&mask, 0, pt->mask, 0, pt->mask_len); mask 1990 drivers/crypto/ccp/ccp-ops.c ret = ccp_copy_to_sb(cmd_q, &mask, op.jobid, op.sb_key, mask 2073 drivers/crypto/ccp/ccp-ops.c ccp_dm_free(&mask); mask 2083 drivers/crypto/ccp/ccp-ops.c struct ccp_dm_workarea mask; mask 2096 drivers/crypto/ccp/ccp-ops.c if (!pt->mask) mask 2110 drivers/crypto/ccp/ccp-ops.c mask.length = pt->mask_len; mask 2111 drivers/crypto/ccp/ccp-ops.c mask.dma.address = pt->mask; mask 2112 drivers/crypto/ccp/ccp-ops.c mask.dma.length = pt->mask_len; mask 2114 drivers/crypto/ccp/ccp-ops.c ret = ccp_copy_to_sb(cmd_q, &mask, op.jobid, op.sb_key, mask 581 drivers/crypto/ccree/cc_request_mgr.c u32 mask; mask 603 drivers/crypto/ccree/cc_request_mgr.c mask = cc_cpp_int_mask(cc_req->cpp.alg, mask 605 drivers/crypto/ccree/cc_request_mgr.c rc = (drvdata->irq & mask ? -EPERM : 0); mask 606 drivers/crypto/ccree/cc_request_mgr.c dev_dbg(dev, "Got mask: %x irq: %x rc: %d\n", mask, mask 25 drivers/crypto/chelsio/chtls/chtls_hw.c u64 mask, u64 val, u8 cookie, int no_reply) mask 34 drivers/crypto/chelsio/chtls/chtls_hw.c req->mask = cpu_to_be64(mask); mask 42 drivers/crypto/chelsio/chtls/chtls_hw.c u64 mask, u64 val, u8 cookie, int no_reply) mask 53 drivers/crypto/chelsio/chtls/chtls_hw.c __set_tcb_field_direct(csk, req, word, mask, val, cookie, no_reply); mask 61 drivers/crypto/chelsio/chtls/chtls_hw.c static int chtls_set_tcb_field(struct sock *sk, u16 word, u64 mask, u64 val) mask 80 drivers/crypto/chelsio/chtls/chtls_hw.c __set_tcb_field(sk, skb, word, mask, val, 0, 1); mask 1049 drivers/crypto/hifn_795x.c unsigned dlen, unsigned slen, u16 mask, u8 snum) mask 1055 drivers/crypto/hifn_795x.c base_cmd->masks = __cpu_to_le16(mask); mask 1118 drivers/crypto/hifn_795x.c u16 mask; mask 1123 drivers/crypto/hifn_795x.c mask = 0; mask 1126 drivers/crypto/hifn_795x.c mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE; mask 1129 drivers/crypto/hifn_795x.c mask = HIFN_BASE_CMD_CRYPT; mask 1132 drivers/crypto/hifn_795x.c mask = HIFN_BASE_CMD_MAC; mask 1139 drivers/crypto/hifn_795x.c nbytes, mask, dev->snum); mask 1243 drivers/crypto/inside-secure/safexcel.c u32 val, mask = 0; mask 1250 drivers/crypto/inside-secure/safexcel.c mask = EIP197_N_PES_MASK; mask 1253 drivers/crypto/inside-secure/safexcel.c mask = EIP97_N_PES_MASK; mask 1255 drivers/crypto/inside-secure/safexcel.c priv->config.pes = (val >> EIP197_N_PES_OFFSET) & mask; mask 1260 drivers/crypto/inside-secure/safexcel.c mask = BIT(val) - 1; mask 1263 drivers/crypto/inside-secure/safexcel.c priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask; mask 1266 drivers/crypto/inside-secure/safexcel.c priv->config.rd_offset = (priv->config.rd_size + mask) & ~mask; mask 1312 drivers/crypto/inside-secure/safexcel.c u32 peid, version, mask, val, hiaopt; mask 1328 drivers/crypto/inside-secure/safexcel.c mask = 0; /* do not swap */ mask 1333 drivers/crypto/inside-secure/safexcel.c mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; mask 1345 drivers/crypto/inside-secure/safexcel.c mask = EIP197_MST_CTRL_BYTE_SWAP_BITS; mask 1361 drivers/crypto/inside-secure/safexcel.c if (mask) { mask 1363 drivers/crypto/inside-secure/safexcel.c val = val ^ (mask >> 24); /* toggle byte swap bits */ mask 118 drivers/crypto/marvell/cesa.c u32 status, mask; mask 124 drivers/crypto/marvell/cesa.c mask = mv_cesa_get_int_mask(engine); mask 127 drivers/crypto/marvell/cesa.c if (!(status & mask)) mask 138 drivers/crypto/marvell/cesa.c res = mv_cesa_int_process(engine, status & mask); mask 650 drivers/crypto/marvell/cesa.h u32 cfg, u32 mask) mask 652 drivers/crypto/marvell/cesa.h op->desc.config &= cpu_to_le32(~mask); mask 120 drivers/crypto/mediatek/mtk-platform.c static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask) mask 123 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL); mask 124 drivers/crypto/mediatek/mtk-platform.c writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL); mask 80 drivers/crypto/omap-aes.c u32 value, u32 mask) mask 85 drivers/crypto/omap-aes.c val &= ~mask; mask 173 drivers/crypto/omap-aes.c u32 mask, val; mask 182 drivers/crypto/omap-aes.c mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | mask 185 drivers/crypto/omap-aes.c omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); mask 201 drivers/crypto/omap-aes.c u32 mask; mask 203 drivers/crypto/omap-aes.c mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | mask 206 drivers/crypto/omap-aes.c omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); mask 205 drivers/crypto/omap-des.c u32 value, u32 mask) mask 210 drivers/crypto/omap-des.c val &= ~mask; mask 250 drivers/crypto/omap-des.c u32 val = 0, mask = 0; mask 274 drivers/crypto/omap-des.c mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES; mask 276 drivers/crypto/omap-des.c omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask); mask 283 drivers/crypto/omap-des.c u32 mask, val; mask 294 drivers/crypto/omap-des.c mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | mask 297 drivers/crypto/omap-des.c omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask); mask 302 drivers/crypto/omap-des.c u32 mask; mask 304 drivers/crypto/omap-des.c mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | mask 307 drivers/crypto/omap-des.c omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask); mask 259 drivers/crypto/omap-sham.c u32 value, u32 mask) mask 264 drivers/crypto/omap-sham.c val &= ~mask; mask 387 drivers/crypto/omap-sham.c u32 val = length << 5, mask; mask 406 drivers/crypto/omap-sham.c mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | mask 409 drivers/crypto/omap-sham.c omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); mask 456 drivers/crypto/omap-sham.c u32 val, mask; mask 491 drivers/crypto/omap-sham.c mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | mask 496 drivers/crypto/omap-sham.c omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask); mask 2087 drivers/crypto/omap-sham.c dma_cap_mask_t mask; mask 2125 drivers/crypto/omap-sham.c dma_cap_zero(mask); mask 2126 drivers/crypto/omap-sham.c dma_cap_set(DMA_SLAVE, mask); mask 52 drivers/crypto/qat/qat_common/icp_qat_fw.h #define QAT_FIELD_SET(flags, val, bitpos, mask) \ mask 53 drivers/crypto/qat/qat_common/icp_qat_fw.h { (flags) = (((flags) & (~((mask) << (bitpos)))) | \ mask 54 drivers/crypto/qat/qat_common/icp_qat_fw.h (((val) & (mask)) << (bitpos))) ; } mask 56 drivers/crypto/qat/qat_common/icp_qat_fw.h #define QAT_FIELD_GET(flags, bitpos, mask) \ mask 57 drivers/crypto/qat/qat_common/icp_qat_fw.h (((flags) >> (bitpos)) & (mask)) mask 1189 drivers/crypto/qat/qat_common/qat_hal.c unsigned short mask; mask 1198 drivers/crypto/qat/qat_common/qat_hal.c mask = 0x1f; mask 1201 drivers/crypto/qat/qat_common/qat_hal.c mask = 0x0f; mask 1203 drivers/crypto/qat/qat_common/qat_hal.c if (reg_num & ~mask) mask 207 drivers/crypto/ux500/cryp/cryp.h dma_cap_mask_t mask; mask 491 drivers/crypto/ux500/cryp/cryp_core.c dma_cap_zero(device_data->dma.mask); mask 492 drivers/crypto/ux500/cryp/cryp_core.c dma_cap_set(DMA_SLAVE, device_data->dma.mask); mask 496 drivers/crypto/ux500/cryp/cryp_core.c dma_request_channel(device_data->dma.mask, mask 502 drivers/crypto/ux500/cryp/cryp_core.c dma_request_channel(device_data->dma.mask, mask 23 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_SET_BITS(reg_name, mask) \ mask 24 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) mask 26 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_WRITE_BIT(reg_name, val, mask) \ mask 27 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\ mask 28 drivers/crypto/ux500/cryp/cryp_p.h ((val) & (mask))), reg_name) mask 33 drivers/crypto/ux500/cryp/cryp_p.h #define CRYP_PUT_BITS(reg, val, shift, mask) \ mask 34 drivers/crypto/ux500/cryp/cryp_p.h writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \ mask 35 drivers/crypto/ux500/cryp/cryp_p.h (((u32)val << shift) & (mask))), reg) mask 98 drivers/crypto/ux500/hash/hash_alg.h #define HASH_SET_BITS(reg_name, mask) \ mask 99 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed((readl_relaxed(reg_name) | mask), reg_name) mask 101 drivers/crypto/ux500/hash/hash_alg.h #define HASH_CLEAR_BITS(reg_name, mask) \ mask 102 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name) mask 104 drivers/crypto/ux500/hash/hash_alg.h #define HASH_PUT_BITS(reg, val, shift, mask) \ mask 105 drivers/crypto/ux500/hash/hash_alg.h writel_relaxed(((readl(reg) & ~(mask)) | \ mask 106 drivers/crypto/ux500/hash/hash_alg.h (((u32)val << shift) & (mask))), reg) mask 310 drivers/crypto/ux500/hash/hash_alg.h dma_cap_mask_t mask; mask 117 drivers/crypto/ux500/hash/hash_core.c dma_cap_zero(device_data->dma.mask); mask 118 drivers/crypto/ux500/hash/hash_core.c dma_cap_set(DMA_SLAVE, device_data->dma.mask); mask 122 drivers/crypto/ux500/hash/hash_core.c dma_request_channel(device_data->dma.mask, mask 22 drivers/dax/device.c unsigned long mask; mask 35 drivers/dax/device.c mask = dax_region->align - 1; mask 36 drivers/dax/device.c if (vma->vm_start & mask || vma->vm_end & mask) { mask 40 drivers/dax/device.c mask); mask 2295 drivers/dma/amba-pl08x.c u32 mask = 0, err, tc, i; mask 2350 drivers/dma/amba-pl08x.c mask |= BIT(i); mask 2354 drivers/dma/amba-pl08x.c return mask ? IRQ_HANDLED : IRQ_NONE; mask 3036 drivers/dma/amba-pl08x.c .mask = 0xffffffff, mask 3042 drivers/dma/amba-pl08x.c .mask = 0x000fffff, mask 3048 drivers/dma/amba-pl08x.c .mask = 0x000fffff, mask 3054 drivers/dma/amba-pl08x.c .mask = 0x00ffffff, mask 3060 drivers/dma/amba-pl08x.c .mask = 0x000fffff, mask 249 drivers/dma/at_hdmac.c dma_writel(atdma, CHER, atchan->mask); mask 642 drivers/dma/at_hdmac.c AT_DMA_RES(i) | atchan->mask); mask 1439 drivers/dma/at_hdmac.c dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); mask 1442 drivers/dma/at_hdmac.c while (dma_readl(atdma, CHSR) & atchan->mask) mask 1662 drivers/dma/at_hdmac.c dma_cap_mask_t mask; mask 1671 drivers/dma/at_hdmac.c dma_cap_zero(mask); mask 1672 drivers/dma/at_hdmac.c dma_cap_set(DMA_SLAVE, mask); mask 1704 drivers/dma/at_hdmac.c chan = dma_request_channel(mask, at_dma_filter, atslave); mask 1899 drivers/dma/at_hdmac.c atchan->mask = 1 << i; mask 2107 drivers/dma/at_hdmac.c dma_writel(atdma, CHER, atchan->mask); mask 252 drivers/dma/at_hdmac_regs.h u8 mask; mask 422 drivers/dma/at_hdmac_regs.h return !!(dma_readl(atdma, CHSR) & atchan->mask); mask 186 drivers/dma/at_xdmac.c u32 mask; /* Channel Mask */ mask 318 drivers/dma/at_xdmac.c return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; mask 403 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); mask 405 drivers/dma/at_xdmac.c "%s: enable channel (0x%08x)\n", __func__, atchan->mask); mask 407 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); mask 1399 drivers/dma/at_xdmac.c u32 cur_nda, check_nda, cur_ubc, mask, value; mask 1438 drivers/dma/at_xdmac.c mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; mask 1440 drivers/dma/at_xdmac.c if ((desc->lld.mbr_cfg & mask) == value) { mask 1441 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); mask 1498 drivers/dma/at_xdmac.c if ((desc->lld.mbr_cfg & mask) == value) { mask 1499 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); mask 1602 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); mask 1603 drivers/dma/at_xdmac.c while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) mask 1714 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); mask 1765 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); mask 1788 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); mask 1805 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); mask 1806 drivers/dma/at_xdmac.c while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) mask 1951 drivers/dma/at_xdmac.c at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); mask 2074 drivers/dma/at_xdmac.c atchan->mask = 1 << i; mask 171 drivers/dma/bcm-sba-raid.c static inline u64 __pure sba_cmd_enc(u64 cmd, u32 val, u32 shift, u32 mask) mask 173 drivers/dma/bcm-sba-raid.c cmd &= ~((u64)mask << shift); mask 174 drivers/dma/bcm-sba-raid.c cmd |= ((u64)(val & mask) << shift); mask 799 drivers/dma/dma-jz4780.c dma_cap_mask_t mask = jzdma->dma_device.cap_mask; mask 829 drivers/dma/dma-jz4780.c return __dma_request_channel(&mask, jz4780_dma_filter_fn, &data, mask 167 drivers/dma/dmaengine.c #define dma_device_satisfies_mask(device, mask) \ mask 168 drivers/dma/dmaengine.c __dma_device_satisfies_mask((device), &(mask)) mask 499 drivers/dma/dmaengine.c static struct dma_chan *private_candidate(const dma_cap_mask_t *mask, mask 505 drivers/dma/dmaengine.c if (mask && !__dma_device_satisfies_mask(dev, mask)) { mask 537 drivers/dma/dmaengine.c const dma_cap_mask_t *mask, mask 540 drivers/dma/dmaengine.c struct dma_chan *chan = private_candidate(mask, device, fn, fn_param); mask 610 drivers/dma/dmaengine.c dma_cap_mask_t mask; mask 613 drivers/dma/dmaengine.c dma_cap_zero(mask); mask 614 drivers/dma/dmaengine.c dma_cap_set(DMA_SLAVE, mask); mask 619 drivers/dma/dmaengine.c chan = find_candidate(device, &mask, NULL, NULL); mask 636 drivers/dma/dmaengine.c struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, mask 650 drivers/dma/dmaengine.c chan = find_candidate(device, mask, fn, fn_param); mask 716 drivers/dma/dmaengine.c dma_cap_mask_t mask; mask 722 drivers/dma/dmaengine.c dma_cap_zero(mask); mask 723 drivers/dma/dmaengine.c dma_cap_set(DMA_SLAVE, mask); mask 725 drivers/dma/dmaengine.c chan = find_candidate(d, &mask, d->filter.fn, map->param); mask 759 drivers/dma/dmaengine.c struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask) mask 763 drivers/dma/dmaengine.c if (!mask) mask 766 drivers/dma/dmaengine.c chan = __dma_request_channel(mask, NULL, NULL, NULL); mask 1048 drivers/dma/dmatest.c dma_cap_mask_t mask; mask 1050 drivers/dma/dmatest.c dma_cap_zero(mask); mask 1051 drivers/dma/dmatest.c dma_cap_set(type, mask); mask 1056 drivers/dma/dmatest.c chan = dma_request_channel(mask, filter, params); mask 538 drivers/dma/dw-edma/dw-edma-core.c u32 mask; mask 543 drivers/dma/dw-edma/dw-edma-core.c mask = dw_irq->wr_mask; mask 547 drivers/dma/dw-edma/dw-edma-core.c mask = dw_irq->rd_mask; mask 553 drivers/dma/dw-edma/dw-edma-core.c val &= mask; mask 563 drivers/dma/dw-edma/dw-edma-core.c val &= mask; mask 761 drivers/dma/dw-edma/dw-edma-core.c static inline void dw_edma_add_irq_mask(u32 *mask, u32 alloc, u16 cnt) mask 763 drivers/dma/dw-edma/dw-edma-core.c while (*mask * alloc < cnt) mask 764 drivers/dma/dw-edma/dw-edma-core.c (*mask)++; mask 127 drivers/dma/dw/core.c channel_set_bit(dw, MASK.XFER, dwc->mask); mask 128 drivers/dma/dw/core.c channel_set_bit(dw, MASK.ERROR, dwc->mask); mask 148 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); mask 149 drivers/dma/dw/core.c while (dma_readl(dw, CH_EN) & dwc->mask) mask 172 drivers/dma/dw/core.c channel_set_bit(dw, CH_EN, dwc->mask); mask 186 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { mask 221 drivers/dma/dw/core.c channel_set_bit(dw, CH_EN, dwc->mask); mask 274 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { mask 317 drivers/dma/dw/core.c if (status_xfer & dwc->mask) { mask 319 drivers/dma/dw/core.c dma_writel(dw, CLEAR.XFER, dwc->mask); mask 448 drivers/dma/dw/core.c dma_writel(dw, CLEAR.ERROR, dwc->mask); mask 987 drivers/dma/dw/core.c if (dma_readl(dw, CH_EN) & dwc->mask) { mask 1011 drivers/dma/dw/core.c dw->in_use |= dwc->mask; mask 1028 drivers/dma/dw/core.c BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); mask 1038 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.XFER, dwc->mask); mask 1039 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.BLOCK, dwc->mask); mask 1040 drivers/dma/dw/core.c channel_clear_bit(dw, MASK.ERROR, dwc->mask); mask 1045 drivers/dma/dw/core.c dw->in_use &= ~dwc->mask; mask 1156 drivers/dma/dw/core.c dwc->mask = 1 << i; mask 1161 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); mask 1257 drivers/dma/dw/core.c channel_clear_bit(dw, CH_EN, dwc->mask); mask 267 drivers/dma/dw/regs.h u8 mask; mask 356 drivers/dma/dw/regs.h #define channel_set_bit(dw, reg, mask) \ mask 357 drivers/dma/dw/regs.h dma_writel(dw, reg, ((mask) << 8) | (mask)) mask 358 drivers/dma/dw/regs.h #define channel_clear_bit(dw, reg, mask) \ mask 359 drivers/dma/dw/regs.h dma_writel(dw, reg, ((mask) << 8) | 0) mask 1003 drivers/dma/fsldma.c u32 gsr, mask; mask 1008 drivers/dma/fsldma.c mask = 0xff000000; mask 1016 drivers/dma/fsldma.c if (gsr & mask) { mask 1022 drivers/dma/fsldma.c gsr &= ~mask; mask 1023 drivers/dma/fsldma.c mask >>= 8; mask 71 drivers/dma/idma64.c channel_set_bit(idma64, MASK(XFER), idma64c->mask); mask 72 drivers/dma/idma64.c channel_set_bit(idma64, MASK(ERROR), idma64c->mask); mask 86 drivers/dma/idma64.c channel_clear_bit(idma64, CH_EN, idma64c->mask); mask 102 drivers/dma/idma64.c channel_set_bit(idma64, CH_EN, idma64c->mask); mask 146 drivers/dma/idma64.c dma_writel(idma64, CLEAR(ERROR), idma64c->mask); mask 149 drivers/dma/idma64.c dma_writel(idma64, CLEAR(XFER), idma64c->mask); mask 566 drivers/dma/idma64.c idma64c->mask = BIT(i); mask 134 drivers/dma/idma64.h unsigned int mask; mask 146 drivers/dma/idma64.h #define channel_set_bit(idma64, reg, mask) \ mask 147 drivers/dma/idma64.h dma_writel(idma64, reg, ((mask) << 8) | (mask)) mask 148 drivers/dma/idma64.h #define channel_clear_bit(idma64, reg, mask) \ mask 149 drivers/dma/idma64.h dma_writel(idma64, reg, ((mask) << 8) | 0) mask 1957 drivers/dma/imx-sdma.c dma_cap_mask_t mask = sdma->dma_device.cap_mask; mask 1975 drivers/dma/imx-sdma.c return __dma_request_channel(&mask, sdma_filter_fn, &data, mask 115 drivers/dma/ipu/ipu_idmac.c uint32_t ic_conf, mask; mask 119 drivers/dma/ipu/ipu_idmac.c mask = IC_CONF_PRPENC_EN; mask 122 drivers/dma/ipu/ipu_idmac.c mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN; mask 127 drivers/dma/ipu/ipu_idmac.c ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask; mask 134 drivers/dma/ipu/ipu_idmac.c uint32_t ic_conf, mask; mask 138 drivers/dma/ipu/ipu_idmac.c mask = IC_CONF_PRPENC_EN; mask 141 drivers/dma/ipu/ipu_idmac.c mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN; mask 146 drivers/dma/ipu/ipu_idmac.c ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask; mask 577 drivers/dma/ipu/ipu_idmac.c uint32_t mask; mask 582 drivers/dma/ipu/ipu_idmac.c mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN; mask 586 drivers/dma/ipu/ipu_idmac.c mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN; mask 589 drivers/dma/ipu/ipu_idmac.c mask = 0; mask 593 drivers/dma/ipu/ipu_idmac.c return mask; mask 180 drivers/dma/mediatek/mtk-cqdma.c u32 mask, u32 set) mask 185 drivers/dma/mediatek/mtk-cqdma.c val &= ~mask; mask 280 drivers/dma/mediatek/mtk-hsdma.c u32 mask, u32 set) mask 285 drivers/dma/mediatek/mtk-hsdma.c val &= ~mask; mask 605 drivers/dma/mmp_tdma.c dma_cap_mask_t mask = tdev->device.cap_mask; mask 616 drivers/dma/mmp_tdma.c return __dma_request_channel(&mask, mmp_tdma_filter_fn, ¶m, mask 748 drivers/dma/mxs-dma.c dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask; mask 759 drivers/dma/mxs-dma.c return __dma_request_channel(&mask, mxs_dma_filter_fn, ¶m, mask 3252 drivers/dma/pl330.c .mask = 0x000fffff, mask 1847 drivers/dma/ppc4xx/adma.c u8 xor_arg_no, u32 mask) mask 1851 drivers/dma/ppc4xx/adma.c xcb->ops[xor_arg_no].h |= mask; mask 3934 drivers/dma/ppc4xx/adma.c u32 mask, enable; mask 3957 drivers/dma/ppc4xx/adma.c mask = ioread32(&adev->i2o_reg->iopim) & enable; mask 3958 drivers/dma/ppc4xx/adma.c iowrite32(mask, &adev->i2o_reg->iopim); mask 3977 drivers/dma/ppc4xx/adma.c u32 mask, disable; mask 3981 drivers/dma/ppc4xx/adma.c mask = ioread32be(&adev->xor_reg->ier); mask 3982 drivers/dma/ppc4xx/adma.c mask &= ~(XOR_IE_CBCIE_BIT | XOR_IE_ICBIE_BIT | mask 3984 drivers/dma/ppc4xx/adma.c iowrite32be(mask, &adev->xor_reg->ier); mask 3990 drivers/dma/ppc4xx/adma.c mask = ioread32(&adev->i2o_reg->iopim) | disable; mask 3991 drivers/dma/ppc4xx/adma.c iowrite32(mask, &adev->i2o_reg->iopim); mask 1545 drivers/dma/sh/rcar-dmac.c u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE; mask 1569 drivers/dma/sh/rcar-dmac.c mask |= RCAR_DMACHCR_DE; mask 1570 drivers/dma/sh/rcar-dmac.c rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask); mask 1571 drivers/dma/sh/rcar-dmac.c if (mask & RCAR_DMACHCR_DE) mask 1673 drivers/dma/sh/rcar-dmac.c dma_cap_mask_t mask; mask 1679 drivers/dma/sh/rcar-dmac.c dma_cap_zero(mask); mask 1680 drivers/dma/sh/rcar-dmac.c dma_cap_set(DMA_SLAVE, mask); mask 1682 drivers/dma/sh/rcar-dmac.c chan = __dma_request_channel(&mask, rcar_dmac_chan_filter, dma_spec, mask 23 drivers/dma/sh/shdma-of.c dma_cap_mask_t mask; mask 29 drivers/dma/sh/shdma-of.c dma_cap_zero(mask); mask 31 drivers/dma/sh/shdma-of.c dma_cap_set(DMA_SLAVE, mask); mask 33 drivers/dma/sh/shdma-of.c chan = dma_request_channel(mask, shdma_chan_filter, mask 600 drivers/dma/sh/usb-dmac.c u32 mask = 0; mask 608 drivers/dma/sh/usb-dmac.c mask |= USB_DMACHCR_DE | USB_DMACHCR_TE | USB_DMACHCR_SP; mask 615 drivers/dma/sh/usb-dmac.c mask |= USB_DMACHCR_NULL; mask 619 drivers/dma/sh/usb-dmac.c if (mask) mask 620 drivers/dma/sh/usb-dmac.c usb_dmac_chan_write(chan, USB_DMACHCR, chcr & ~mask); mask 650 drivers/dma/sh/usb-dmac.c dma_cap_mask_t mask; mask 656 drivers/dma/sh/usb-dmac.c dma_cap_zero(mask); mask 657 drivers/dma/sh/usb-dmac.c dma_cap_set(DMA_SLAVE, mask); mask 659 drivers/dma/sh/usb-dmac.c chan = __dma_request_channel(&mask, usb_dmac_chan_filter, dma_spec, mask 239 drivers/dma/sprd-dma.c u32 mask, u32 val) mask 244 drivers/dma/sprd-dma.c tmp = (orig & ~mask) | val; mask 249 drivers/dma/sprd-dma.c u32 mask, u32 val) mask 254 drivers/dma/sprd-dma.c tmp = (orig & ~mask) | val; mask 37 drivers/dma/stm32-mdma.c #define STM32_MDMA_SET(n, mask) (((n) << STM32_MDMA_SHIFT(mask)) & \ mask 38 drivers/dma/stm32-mdma.c (mask)) mask 39 drivers/dma/stm32-mdma.c #define STM32_MDMA_GET(n, mask) (((n) & (mask)) >> \ mask 40 drivers/dma/stm32-mdma.c STM32_MDMA_SHIFT(mask)) mask 322 drivers/dma/stm32-mdma.c u32 mask) mask 326 drivers/dma/stm32-mdma.c writel_relaxed(readl_relaxed(addr) | mask, addr); mask 330 drivers/dma/stm32-mdma.c u32 mask) mask 334 drivers/dma/stm32-mdma.c writel_relaxed(readl_relaxed(addr) & ~mask, addr); mask 481 drivers/dma/stm32-mdma.c u32 mask; mask 486 drivers/dma/stm32-mdma.c mask = src_addr & 0xF0000000; mask 488 drivers/dma/stm32-mdma.c if (mask == dmadev->ahb_addr_masks[i]) { mask 70 drivers/dma/tegra210-adma.c #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift) mask 317 drivers/dma/ti/cppi41.c u32 mask; mask 319 drivers/dma/ti/cppi41.c mask = 1 << QMGR_PENDING_BIT_Q(first_completion_queue); mask 321 drivers/dma/ti/cppi41.c mask--; mask 323 drivers/dma/ti/cppi41.c val &= ~mask; mask 611 drivers/dma/ti/omap-dma.c unsigned mask, csr; mask 615 drivers/dma/ti/omap-dma.c mask = BIT(channel); mask 616 drivers/dma/ti/omap-dma.c status &= ~mask; mask 626 drivers/dma/ti/omap-dma.c omap_dma_glbl_write(od, IRQSTATUS_L1, mask); mask 247 drivers/edac/altera_edac.c static int a10_unmask_irq(struct platform_device *pdev, u32 mask) mask 268 drivers/edac/altera_edac.c iowrite32(mask, sm_base); mask 392 drivers/edac/amd64_edac.c u64 *base, u64 *mask) mask 416 drivers/edac/amd64_edac.c *mask = ~0ULL; mask 418 drivers/edac/amd64_edac.c *mask &= ~((GENMASK_ULL(15, 5) << 6) | mask 421 drivers/edac/amd64_edac.c *mask |= (csmask & GENMASK_ULL(15, 5)) << 6; mask 422 drivers/edac/amd64_edac.c *mask |= (csmask & GENMASK_ULL(30, 19)) << 8; mask 440 drivers/edac/amd64_edac.c *mask = ~0ULL; mask 442 drivers/edac/amd64_edac.c *mask &= ~(mask_bits << addr_shift); mask 444 drivers/edac/amd64_edac.c *mask |= (csmask & mask_bits) << addr_shift; mask 467 drivers/edac/amd64_edac.c u64 base, mask; mask 475 drivers/edac/amd64_edac.c get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); mask 477 drivers/edac/amd64_edac.c mask = ~mask; mask 479 drivers/edac/amd64_edac.c if ((input_addr & mask) == (base & mask)) { mask 960 drivers/edac/amd64_edac.c u32 *mask, *mask_sec; mask 987 drivers/edac/amd64_edac.c mask = &pvt->csels[umc].csmasks[cs]; mask 993 drivers/edac/amd64_edac.c if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) mask 995 drivers/edac/amd64_edac.c umc, cs, *mask, mask_reg); mask 3024 drivers/edac/amd64_edac.c static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid) mask 3030 drivers/edac/amd64_edac.c cpumask_set_cpu(cpu, mask); mask 3036 drivers/edac/amd64_edac.c cpumask_var_t mask; mask 3040 drivers/edac/amd64_edac.c if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { mask 3045 drivers/edac/amd64_edac.c get_cpus_on_this_dct_cpumask(mask, nid); mask 3047 drivers/edac/amd64_edac.c rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); mask 3049 drivers/edac/amd64_edac.c for_each_cpu(cpu, mask) { mask 3063 drivers/edac/amd64_edac.c free_cpumask_var(mask); mask 3109 drivers/edac/amd64_edac.c u32 value, mask = 0x3; /* UECC/CECC enable */ mask 3118 drivers/edac/amd64_edac.c s->old_nbctl = value & mask; mask 3121 drivers/edac/amd64_edac.c value |= mask; mask 3160 drivers/edac/amd64_edac.c u32 value, mask = 0x3; /* UECC/CECC enable */ mask 3166 drivers/edac/amd64_edac.c value &= ~mask; mask 585 drivers/edac/cpc925_edac.c static u32 mask = 0; mask 588 drivers/edac/cpc925_edac.c if (mask != 0) mask 589 drivers/edac/cpc925_edac.c return mask; mask 591 drivers/edac/cpc925_edac.c mask = APIMASK_ADI0 | APIMASK_ADI1; mask 600 drivers/edac/cpc925_edac.c mask &= ~APIMASK_ADI(*reg); mask 603 drivers/edac/cpc925_edac.c if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) { mask 611 drivers/edac/cpc925_edac.c return mask; mask 100 drivers/edac/edac_pci.h u8 mask) mask 102 drivers/edac/edac_pci.h if (mask != 0xff) { mask 106 drivers/edac/edac_pci.h value &= mask; mask 107 drivers/edac/edac_pci.h buf &= ~mask; mask 116 drivers/edac/edac_pci.h u16 value, u16 mask) mask 118 drivers/edac/edac_pci.h if (mask != 0xffff) { mask 122 drivers/edac/edac_pci.h value &= mask; mask 123 drivers/edac/edac_pci.h buf &= ~mask; mask 140 drivers/edac/edac_pci.h u32 value, u32 mask) mask 142 drivers/edac/edac_pci.h if (mask != 0xffffffff) { mask 146 drivers/edac/edac_pci.h value &= mask; mask 147 drivers/edac/edac_pci.h buf &= ~mask; mask 263 drivers/edac/i5400_edac.c static inline int to_nf_mask(unsigned int mask) mask 265 drivers/edac/i5400_edac.c return (mask & EMASK_M29) | (mask >> 3); mask 268 drivers/edac/i5400_edac.c static inline int from_nf_ferr(unsigned int mask) mask 270 drivers/edac/i5400_edac.c return (mask & EMASK_M29) | /* Bit 28 */ mask 271 drivers/edac/i5400_edac.c (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ mask 918 drivers/edac/i7core_edac.c u64 mask = 0; mask 938 drivers/edac/i7core_edac.c mask |= 1LL << 41; mask 941 drivers/edac/i7core_edac.c mask |= (pvt->inject.dimm & 0x3LL) << 35; mask 943 drivers/edac/i7core_edac.c mask |= (pvt->inject.dimm & 0x1LL) << 36; mask 948 drivers/edac/i7core_edac.c mask |= 1LL << 40; mask 951 drivers/edac/i7core_edac.c mask |= (pvt->inject.rank & 0x1LL) << 34; mask 953 drivers/edac/i7core_edac.c mask |= (pvt->inject.rank & 0x3LL) << 34; mask 958 drivers/edac/i7core_edac.c mask |= 1LL << 39; mask 960 drivers/edac/i7core_edac.c mask |= (pvt->inject.bank & 0x15LL) << 30; mask 964 drivers/edac/i7core_edac.c mask |= 1LL << 38; mask 966 drivers/edac/i7core_edac.c mask |= (pvt->inject.page & 0xffff) << 14; mask 970 drivers/edac/i7core_edac.c mask |= 1LL << 37; mask 972 drivers/edac/i7core_edac.c mask |= (pvt->inject.col & 0x3fff); mask 990 drivers/edac/i7core_edac.c MC_CHANNEL_ADDR_MATCH, mask); mask 992 drivers/edac/i7core_edac.c MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); mask 1009 drivers/edac/i7core_edac.c mask, pvt->inject.eccmask, injectmask); mask 10 drivers/edac/mce_amd.h #define XEC(x, mask) (((x) >> 16) & mask) mask 347 drivers/edac/pnd2_edac.c static void mk_region_mask(char *name, struct region *rp, u64 base, u64 mask) mask 349 drivers/edac/pnd2_edac.c if (mask == 0) { mask 353 drivers/edac/pnd2_edac.c if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) { mask 357 drivers/edac/pnd2_edac.c if (base & ~mask) { mask 362 drivers/edac/pnd2_edac.c rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0); mask 377 drivers/edac/pnd2_edac.c int mask = 0; mask 380 drivers/edac/pnd2_edac.c mask |= p->sym_slice0_channel_enabled; mask 383 drivers/edac/pnd2_edac.c mask |= p->sym_slice1_channel_enabled << 2; mask 386 drivers/edac/pnd2_edac.c mask &= 0x5; mask 388 drivers/edac/pnd2_edac.c return mask; mask 397 drivers/edac/pnd2_edac.c int mask = 0; mask 400 drivers/edac/pnd2_edac.c mask = intlv[as2way->asym_2way_intlv_mode]; mask 402 drivers/edac/pnd2_edac.c mask |= (1 << as0->slice0_asym_channel_select); mask 404 drivers/edac/pnd2_edac.c mask |= (4 << as1->slice1_asym_channel_select); mask 406 drivers/edac/pnd2_edac.c mask &= 0xc; mask 408 drivers/edac/pnd2_edac.c mask &= 0x3; mask 410 drivers/edac/pnd2_edac.c mask &= 0x5; mask 412 drivers/edac/pnd2_edac.c return mask; mask 618 drivers/edac/pnd2_edac.c u64 mask; mask 623 drivers/edac/pnd2_edac.c mask = (1ull << bitidx) - 1; mask 624 drivers/edac/pnd2_edac.c *addr = ((*addr >> 1) & ~mask) | (*addr & mask); mask 628 drivers/edac/pnd2_edac.c static int hash_by_mask(u64 addr, u64 mask) mask 630 drivers/edac/pnd2_edac.c u64 result = addr & mask; mask 46 drivers/edac/thunderx_edac.c u64 mask; mask 56 drivers/edac/thunderx_edac.c while (descr->type && descr->mask && descr->descr) { mask 57 drivers/edac/thunderx_edac.c if (reg & descr->mask) { mask 126 drivers/edac/thunderx_edac.c .mask = LMC_INT_SEC_ERR, mask 131 drivers/edac/thunderx_edac.c .mask = LMC_INT_DDR_ERR, mask 136 drivers/edac/thunderx_edac.c .mask = LMC_INT_DED_ERR, mask 141 drivers/edac/thunderx_edac.c .mask = LMC_INT_NXM_WR_MASK, mask 853 drivers/edac/thunderx_edac.c .mask = OCX_COM_IO_BADID, mask 858 drivers/edac/thunderx_edac.c .mask = OCX_COM_MEM_BADID, mask 863 drivers/edac/thunderx_edac.c .mask = OCX_COM_COPR_BADID, mask 868 drivers/edac/thunderx_edac.c .mask = OCX_COM_WIN_REQ_BADID, mask 873 drivers/edac/thunderx_edac.c .mask = OCX_COM_WIN_REQ_TOUT, mask 902 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_REPLAY_SBE, mask 907 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_TXFIFO_SBE, mask 912 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_RXFIFO_SBE, mask 917 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_BLK_ERR, mask 922 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_ALIGN_FAIL, mask 927 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_BAD_WORD, mask 932 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_REPLAY_DBE, mask 937 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_TXFIFO_DBE, mask 942 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_RXFIFO_DBE, mask 947 drivers/edac/thunderx_edac.c .mask = OCX_COM_LINK_STOP, mask 997 drivers/edac/thunderx_edac.c .mask = OCX_LANE_SERDES_LOCK_LOSS, mask 1002 drivers/edac/thunderx_edac.c .mask = OCX_LANE_BDRY_SYNC_LOSS, mask 1007 drivers/edac/thunderx_edac.c .mask = OCX_LANE_CRC32_ERR, mask 1012 drivers/edac/thunderx_edac.c .mask = OCX_LANE_UKWN_CNTL_WORD, mask 1017 drivers/edac/thunderx_edac.c .mask = OCX_LANE_SCRM_SYNC_LOSS, mask 1022 drivers/edac/thunderx_edac.c .mask = OCX_LANE_DSKEW_FIFO_OVFL, mask 1027 drivers/edac/thunderx_edac.c .mask = OCX_LANE_BAD_64B67B, mask 1551 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_SBFSBE, mask 1556 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_FBFSBE, mask 1561 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_L2DDBE, mask 1566 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_SBFDBE, mask 1571 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_FBFDBE, mask 1576 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_TAGDBE, mask 1581 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_RTGDBE, mask 1586 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_WRDISOCI, mask 1591 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_RDDISOCI, mask 1596 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_WRDISLMC, mask 1601 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_RDDISLMC, mask 1606 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_LFBTO, mask 1611 drivers/edac/thunderx_edac.c .mask = L2C_TAD_INT_GSYNCTO, mask 1662 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_RSDSBE, mask 1667 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_MIBSBE, mask 1672 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_RSDDBE, mask 1677 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_MIBDBE, mask 1682 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_IORDDISOCI, mask 1687 drivers/edac/thunderx_edac.c .mask = L2C_CBC_INT_IOWRDISOCI, mask 1715 drivers/edac/thunderx_edac.c .mask = L2C_MCI_INT_VBFSBE, mask 1720 drivers/edac/thunderx_edac.c .mask = L2C_MCI_INT_VBFDBE, mask 146 drivers/extcon/extcon-arizona.c unsigned int mask = 0, val = 0; mask 153 drivers/extcon/extcon-arizona.c mask = 0; mask 157 drivers/extcon/extcon-arizona.c mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | mask 176 drivers/extcon/extcon-arizona.c mask = ARIZONA_RMV_SHRT_HP1L; mask 198 drivers/extcon/extcon-arizona.c if (mask) { mask 200 drivers/extcon/extcon-arizona.c mask, val); mask 206 drivers/extcon/extcon-arizona.c mask, val); mask 1088 drivers/extcon/extcon-arizona.c unsigned int val, present, mask; mask 1100 drivers/extcon/extcon-arizona.c mask = ARIZONA_MICD_CLAMP_STS; mask 1103 drivers/extcon/extcon-arizona.c mask = ARIZONA_JD1_STS; mask 1119 drivers/extcon/extcon-arizona.c val &= mask; mask 1231 drivers/extcon/extcon-arizona.c unsigned int mask; mask 1236 drivers/extcon/extcon-arizona.c mask = 0x3f00; mask 1239 drivers/extcon/extcon-arizona.c mask = 0x3f; mask 1243 drivers/extcon/extcon-arizona.c regmap_update_bits(arizona->regmap, reg, mask, level); mask 203 drivers/extcon/extcon-fsa9480.c u16 mask, bool attached) mask 205 drivers/extcon/extcon-fsa9480.c while (mask) { mask 206 drivers/extcon/extcon-fsa9480.c int dev = fls64(mask) - 1; mask 216 drivers/extcon/extcon-fsa9480.c mask &= ~BIT_ULL(dev); mask 317 drivers/extcon/extcon-intel-cht-wc.c int ret, mask, val; mask 327 drivers/extcon/extcon-intel-cht-wc.c mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF; mask 328 drivers/extcon/extcon-intel-cht-wc.c val = enable ? mask : 0; mask 329 drivers/extcon/extcon-intel-cht-wc.c ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val); mask 340 drivers/extcon/extcon-intel-cht-wc.c unsigned long mask = ~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_USBID_MASK); mask 416 drivers/extcon/extcon-intel-cht-wc.c ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask); mask 68 drivers/extcon/extcon-intel-mrfld.c unsigned int mask) mask 70 drivers/extcon/extcon-intel-mrfld.c return regmap_update_bits(data->regmap, reg, mask, 0x00); mask 74 drivers/extcon/extcon-intel-mrfld.c unsigned int mask) mask 76 drivers/extcon/extcon-intel-mrfld.c return regmap_update_bits(data->regmap, reg, mask, 0xff); mask 81 drivers/extcon/extcon-intel-mrfld.c unsigned int mask = BCOVE_CHGRCTRL0_SWCONTROL; mask 86 drivers/extcon/extcon-intel-mrfld.c ret = mrfld_extcon_set(data, BCOVE_CHGRCTRL0, mask); mask 88 drivers/extcon/extcon-intel-mrfld.c ret = mrfld_extcon_clear(data, BCOVE_CHGRCTRL0, mask); mask 167 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADC, }, mask 168 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADCERROR, }, mask 169 drivers/extcon/extcon-max77843.c { .reg_offset = 0, .mask = MAX77843_MUIC_ADC1K, }, mask 172 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_CHGTYP, }, mask 173 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_CHGDETRUN, }, mask 174 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_DCDTMR, }, mask 175 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_DXOVP, }, mask 176 drivers/extcon/extcon-max77843.c { .reg_offset = 1, .mask = MAX77843_MUIC_VBVOLT, }, mask 179 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_VBADC, }, mask 180 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_VDNMON, }, mask 181 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_DNRES, }, mask 182 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MPNACK, }, mask 183 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXBUFOW, }, mask 184 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXTRF, }, mask 185 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXPERR, }, mask 186 drivers/extcon/extcon-max77843.c { .reg_offset = 2, .mask = MAX77843_MUIC_MRXRDY, }, mask 33 drivers/extcon/extcon-rt8973a.c u8 mask; mask 74 drivers/extcon/extcon-rt8973a.c .mask = RT8973A_REG_CONTROL1_ADC_EN_MASK mask 172 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_ATTACH_MASK, }, mask 173 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_DETACH_MASK, }, mask 174 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_CHGDET_MASK, }, mask 175 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_DCD_T_MASK, }, mask 176 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_OVP_MASK, }, mask 177 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_CONNECT_MASK, }, mask 178 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_ADC_CHG_MASK, }, mask 179 drivers/extcon/extcon-rt8973a.c { .reg_offset = 0, .mask = RT8973A_INT1_OTP_MASK, }, mask 182 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_UVLOT_MASK,}, mask 183 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_POR_MASK, }, mask 184 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OTP_FET_MASK, }, mask 185 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OVP_FET_MASK, }, mask 186 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OCP_LATCH_MASK, }, mask 187 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OCP_MASK, }, mask 188 drivers/extcon/extcon-rt8973a.c { .reg_offset = 1, .mask = RT8973A_INT2_OVP_OCP_MASK, }, mask 525 drivers/extcon/extcon-rt8973a.c u8 mask = info->reg_data[i].mask; mask 533 drivers/extcon/extcon-rt8973a.c regmap_update_bits(info->regmap, reg, mask, val); mask 173 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_ATTACH_MASK, }, mask 174 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_DETACH_MASK, }, mask 175 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_KP_MASK, }, mask 176 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKP_MASK, }, mask 177 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_LKR_MASK, }, mask 178 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_EVENT_MASK, }, mask 179 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OCP_EVENT_MASK, }, mask 180 drivers/extcon/extcon-sm5502.c { .reg_offset = 0, .mask = SM5502_IRQ_INT1_OVP_OCP_DIS_MASK, }, mask 183 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_VBUS_DET_MASK,}, mask 184 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_REV_ACCE_MASK, }, mask 185 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_ADC_CHG_MASK, }, mask 186 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_MASK, }, mask 187 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK, }, mask 188 drivers/extcon/extcon-sm5502.c { .reg_offset = 1, .mask = SM5502_IRQ_INT2_MHL_MASK, }, mask 1777 drivers/firewire/core-cdev.c __poll_t mask = 0; mask 1782 drivers/firewire/core-cdev.c mask |= EPOLLHUP | EPOLLERR; mask 1784 drivers/firewire/core-cdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 1786 drivers/firewire/core-cdev.c return mask; mask 304 drivers/firewire/core-iso.c u32 mask; mask 307 drivers/firewire/core-iso.c mask = channel < 32 ? 1 << channel : 1 << (channel - 32); mask 311 drivers/firewire/core-iso.c manage_channel(card, irm_id, generation, mask, offset, false); mask 226 drivers/firewire/nosy.c reg_set_bits(struct pcilynx *lynx, int offset, u32 mask) mask 228 drivers/firewire/nosy.c reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); mask 2939 drivers/firewire/ohci.c u32 *uninitialized_var(mask), uninitialized_var(regs); mask 2946 drivers/firewire/ohci.c mask = &ohci->it_context_mask; mask 2948 drivers/firewire/ohci.c index = ffs(*mask) - 1; mask 2950 drivers/firewire/ohci.c *mask &= ~(1 << index); mask 2958 drivers/firewire/ohci.c mask = &ohci->ir_context_mask; mask 2960 drivers/firewire/ohci.c index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; mask 2963 drivers/firewire/ohci.c *mask &= ~(1 << index); mask 2970 drivers/firewire/ohci.c mask = &ohci->ir_context_mask; mask 2972 drivers/firewire/ohci.c index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; mask 2975 drivers/firewire/ohci.c *mask &= ~(1 << index); mask 3023 drivers/firewire/ohci.c *mask |= 1 << index; mask 119 drivers/firmware/arm_scmi/perf.c u64 mask; mask 301 drivers/firmware/arm_scmi/perf.c if (db->mask) \ mask 302 drivers/firmware/arm_scmi/perf.c val = ioread##w(db->addr) & db->mask; \ mask 324 drivers/firmware/arm_scmi/perf.c if (db->mask) mask 325 drivers/firmware/arm_scmi/perf.c val = ioread64_hi_lo(db->addr) & db->mask; mask 555 drivers/firmware/arm_scmi/perf.c db->mask = le32_to_cpu(resp->db_preserve_lmask); mask 556 drivers/firmware/arm_scmi/perf.c db->mask |= (u64)le32_to_cpu(resp->db_preserve_hmask) << 32; mask 92 drivers/firmware/efi/libstub/arm64-stub.c u32 mask = (MIN_KIMG_ALIGN - 1) & ~(EFI_KIMG_ALIGN - 1); mask 94 drivers/firmware/efi/libstub/arm64-stub.c (phys_seed >> 32) & mask : TEXT_OFFSET; mask 13 drivers/firmware/efi/libstub/gop.c static void find_bits(unsigned long mask, u8 *pos, u8 *size) mask 20 drivers/firmware/efi/libstub/gop.c if (mask) { mask 21 drivers/firmware/efi/libstub/gop.c while (!(mask & 0x1)) { mask 22 drivers/firmware/efi/libstub/gop.c mask = mask >> 1; mask 26 drivers/firmware/efi/libstub/gop.c while (mask & 0x1) { mask 27 drivers/firmware/efi/libstub/gop.c mask = mask >> 1; mask 35 drivers/firmware/imx/imx-scu-irq.c u32 mask; mask 97 drivers/firmware/imx/imx-scu-irq.c int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) mask 113 drivers/firmware/imx/imx-scu-irq.c msg.mask = mask; mask 119 drivers/firmware/imx/imx-scu-irq.c group, mask, ret); mask 99 drivers/firmware/psci/psci.c const u32 mask = psci_has_ext_power_state() ? mask 103 drivers/firmware/psci/psci.c return state & mask; mask 268 drivers/fpga/altera-cvp.c u32 mask, words = len / sizeof(u32); mask 277 drivers/fpga/altera-cvp.c mask = BIT(remainder * 8) - 1; mask 278 drivers/fpga/altera-cvp.c if (mask) mask 279 drivers/fpga/altera-cvp.c conf->write_data(conf, *data & mask); mask 488 drivers/fpga/altera-cvp.c u32 mask, val; mask 509 drivers/fpga/altera-cvp.c mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE; mask 510 drivers/fpga/altera-cvp.c ret = altera_cvp_wait_status(conf, mask, mask, mask 53 drivers/fpga/altera-fpga2sdram.c int mask; mask 63 drivers/fpga/altera-fpga2sdram.c return (value & priv->mask) == priv->mask; mask 70 drivers/fpga/altera-fpga2sdram.c priv->mask, enable ? priv->mask : 0); mask 122 drivers/fpga/altera-fpga2sdram.c regmap_read(sysmgr, SYSMGR_ISWGRP_HANDOFF3, &priv->mask); mask 135 drivers/fpga/altera-fpga2sdram.c dev_info(dev, "driver initialized with handoff %08x\n", priv->mask); mask 30 drivers/fpga/dfl-afu-error.c static void __afu_port_err_mask(struct device *dev, bool mask) mask 36 drivers/fpga/dfl-afu-error.c writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK); mask 39 drivers/fpga/dfl-afu-error.c static void afu_port_err_mask(struct device *dev, bool mask) mask 44 drivers/fpga/dfl-afu-error.c __afu_port_err_mask(dev, mask); mask 314 drivers/fpga/dfl-fme-error.c static void fme_err_mask(struct device *dev, bool mask) mask 325 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK); mask 327 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK); mask 329 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK); mask 330 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK); mask 331 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK); mask 332 drivers/fpga/dfl-fme-error.c writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK); mask 278 drivers/fpga/socfpga-a10.c u32 msel, stat, mask; mask 297 drivers/fpga/socfpga-a10.c mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN | mask 299 drivers/fpga/socfpga-a10.c if ((stat & mask) != mask) mask 463 drivers/fsi/fsi-scom.c u64 prev_data, mask, data; mask 471 drivers/fsi/fsi-scom.c if (acc.mask) { mask 477 drivers/fsi/fsi-scom.c mask = acc.mask; mask 479 drivers/fsi/fsi-scom.c prev_data = mask = -1ull; mask 481 drivers/fsi/fsi-scom.c data = (prev_data & ~mask) | (acc.data & mask); mask 190 drivers/gnss/core.c __poll_t mask = 0; mask 195 drivers/gnss/core.c mask |= EPOLLIN | EPOLLRDNORM; mask 197 drivers/gnss/core.c mask |= EPOLLHUP; mask 199 drivers/gnss/core.c return mask; mask 60 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); mask 62 drivers/gpio/gpio-104-dio-48e.c return !!(dio48egpio->io_state[port] & mask); mask 110 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); mask 137 drivers/gpio/gpio-104-dio-48e.c dio48egpio->out_state[io_port] |= mask; mask 139 drivers/gpio/gpio-104-dio-48e.c dio48egpio->out_state[io_port] &= ~mask; mask 158 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); mask 166 drivers/gpio/gpio-104-dio-48e.c if (!(dio48egpio->io_state[port] & mask)) { mask 175 drivers/gpio/gpio-104-dio-48e.c return !!(port_state & mask); mask 178 drivers/gpio/gpio-104-dio-48e.c static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, mask 207 drivers/gpio/gpio-104-dio-48e.c word_mask = mask[word_index] & (port_mask << word_offset); mask 227 drivers/gpio/gpio-104-dio-48e.c const unsigned mask = BIT(offset % 8); mask 234 drivers/gpio/gpio-104-dio-48e.c dio48egpio->out_state[port] |= mask; mask 236 drivers/gpio/gpio-104-dio-48e.c dio48egpio->out_state[port] &= ~mask; mask 244 drivers/gpio/gpio-104-dio-48e.c unsigned long *mask, unsigned long *bits) mask 257 drivers/gpio/gpio-104-dio-48e.c if (!mask[BIT_WORD(i)]) { mask 264 drivers/gpio/gpio-104-dio-48e.c bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)]; mask 269 drivers/gpio/gpio-104-dio-48e.c dio48egpio->out_state[port] &= ~mask[BIT_WORD(i)]; mask 276 drivers/gpio/gpio-104-dio-48e.c mask[BIT_WORD(i)] >>= gpio_reg_size; mask 70 drivers/gpio/gpio-104-idi-48.c unsigned mask; mask 75 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); mask 77 drivers/gpio/gpio-104-idi-48.c return !!(inb(idi48gpio->base + base_offset) & mask); mask 84 drivers/gpio/gpio-104-idi-48.c static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, mask 113 drivers/gpio/gpio-104-idi-48.c word_mask = mask[word_index] & (port_mask << word_offset); mask 139 drivers/gpio/gpio-104-idi-48.c unsigned mask; mask 145 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); mask 148 drivers/gpio/gpio-104-idi-48.c idi48gpio->irq_mask[boundary] &= ~mask; mask 171 drivers/gpio/gpio-104-idi-48.c unsigned mask; mask 178 drivers/gpio/gpio-104-idi-48.c mask = BIT(offset - i); mask 182 drivers/gpio/gpio-104-idi-48.c idi48gpio->irq_mask[boundary] |= mask; mask 74 drivers/gpio/gpio-104-idio-16.c const unsigned mask = BIT(offset-16); mask 80 drivers/gpio/gpio-104-idio-16.c return !!(inb(idio16gpio->base + 1) & mask); mask 82 drivers/gpio/gpio-104-idio-16.c return !!(inb(idio16gpio->base + 5) & (mask>>8)); mask 86 drivers/gpio/gpio-104-idio-16.c unsigned long *mask, unsigned long *bits) mask 91 drivers/gpio/gpio-104-idio-16.c if (*mask & GENMASK(23, 16)) mask 93 drivers/gpio/gpio-104-idio-16.c if (*mask & GENMASK(31, 24)) mask 102 drivers/gpio/gpio-104-idio-16.c const unsigned mask = BIT(offset); mask 111 drivers/gpio/gpio-104-idio-16.c idio16gpio->out_state |= mask; mask 113 drivers/gpio/gpio-104-idio-16.c idio16gpio->out_state &= ~mask; mask 124 drivers/gpio/gpio-104-idio-16.c unsigned long *mask, unsigned long *bits) mask 131 drivers/gpio/gpio-104-idio-16.c idio16gpio->out_state &= ~*mask; mask 132 drivers/gpio/gpio-104-idio-16.c idio16gpio->out_state |= *mask & *bits; mask 134 drivers/gpio/gpio-104-idio-16.c if (*mask & 0xFF) mask 136 drivers/gpio/gpio-104-idio-16.c if ((*mask >> 8) & 0xFF) mask 150 drivers/gpio/gpio-104-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); mask 153 drivers/gpio/gpio-104-idio-16.c idio16gpio->irq_mask &= ~mask; mask 168 drivers/gpio/gpio-104-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); mask 172 drivers/gpio/gpio-104-idio-16.c idio16gpio->irq_mask |= mask; mask 71 drivers/gpio/gpio-74x164.c static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 81 drivers/gpio/gpio-74x164.c idx = i / sizeof(*mask); mask 82 drivers/gpio/gpio-74x164.c shift = i % sizeof(*mask) * BITS_PER_BYTE; mask 83 drivers/gpio/gpio-74x164.c bankmask = mask[idx] >> shift; mask 104 drivers/gpio/gpio-amd-fch.c u32 mask; mask 108 drivers/gpio/gpio-amd-fch.c mask = readl_relaxed(ptr); mask 110 drivers/gpio/gpio-amd-fch.c mask |= AMD_FCH_GPIO_FLAG_WRITE; mask 112 drivers/gpio/gpio-amd-fch.c mask &= ~AMD_FCH_GPIO_FLAG_WRITE; mask 113 drivers/gpio/gpio-amd-fch.c writel_relaxed(mask, ptr); mask 828 drivers/gpio/gpio-aspeed.c const u32 mask = GPIO_BIT(offset); mask 837 drivers/gpio/gpio-aspeed.c iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); mask 841 drivers/gpio/gpio-aspeed.c iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); mask 55 drivers/gpio/gpio-ath79.c struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) mask 60 drivers/gpio/gpio-ath79.c new_val = (old_val & ~mask) | (bits & mask); mask 71 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); mask 75 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); mask 82 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); mask 86 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); mask 93 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); mask 97 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); mask 98 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); mask 105 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); mask 109 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); mask 110 drivers/gpio/gpio-ath79.c ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); mask 118 drivers/gpio/gpio-ath79.c u32 mask = BIT(irqd_to_hwirq(data)); mask 125 drivers/gpio/gpio-ath79.c polarity |= mask; mask 131 drivers/gpio/gpio-ath79.c polarity |= mask; mask 134 drivers/gpio/gpio-ath79.c type |= mask; mask 144 drivers/gpio/gpio-ath79.c ctrl->both_edges |= mask; mask 147 drivers/gpio/gpio-ath79.c ctrl->both_edges &= ~mask; mask 155 drivers/gpio/gpio-ath79.c ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); mask 158 drivers/gpio/gpio-ath79.c ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); mask 160 drivers/gpio/gpio-ath79.c ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); mask 164 drivers/gpio/gpio-ath79.c ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); mask 113 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); mask 120 drivers/gpio/gpio-brcmstb.c imask |= mask; mask 122 drivers/gpio/gpio-brcmstb.c imask &= ~mask; mask 161 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); mask 163 drivers/gpio/gpio-brcmstb.c gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); mask 171 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); mask 179 drivers/gpio/gpio-brcmstb.c level = mask; mask 184 drivers/gpio/gpio-brcmstb.c level = mask; mask 185 drivers/gpio/gpio-brcmstb.c edge_config = mask; mask 195 drivers/gpio/gpio-brcmstb.c edge_config = mask; mask 201 drivers/gpio/gpio-brcmstb.c edge_insensitive = mask; mask 210 drivers/gpio/gpio-brcmstb.c GIO_EC(bank->id)) & ~mask; mask 212 drivers/gpio/gpio-brcmstb.c GIO_EI(bank->id)) & ~mask; mask 214 drivers/gpio/gpio-brcmstb.c GIO_LEVEL(bank->id)) & ~mask; mask 247 drivers/gpio/gpio-brcmstb.c u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); mask 254 drivers/gpio/gpio-brcmstb.c bank->wake_active |= mask; mask 256 drivers/gpio/gpio-brcmstb.c bank->wake_active &= ~mask; mask 90 drivers/gpio/gpio-cadence.c u32 mask = BIT(d->hwirq); mask 95 drivers/gpio/gpio-cadence.c int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask; mask 96 drivers/gpio/gpio-cadence.c int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask; mask 105 drivers/gpio/gpio-cadence.c int_type |= mask; mask 106 drivers/gpio/gpio-cadence.c int_value |= mask; mask 108 drivers/gpio/gpio-cadence.c int_type |= mask; mask 117 drivers/gpio/gpio-crystalcove.c int mask = BIT(gpio % 8); mask 120 drivers/gpio/gpio-crystalcove.c regmap_update_bits(cg->regmap, mirqs0, mask, mask); mask 122 drivers/gpio/gpio-crystalcove.c regmap_update_bits(cg->regmap, mirqs0, mask, 0); mask 38 drivers/gpio/gpio-cs5535.c static ulong mask = GPIO_DEFAULT_MASK; mask 39 drivers/gpio/gpio-cs5535.c module_param_named(mask, mask, ulong, 0444); mask 40 drivers/gpio/gpio-cs5535.c MODULE_PARM_DESC(mask, "GPIO channel mask."); mask 211 drivers/gpio/gpio-cs5535.c if ((mask & (1 << offset)) == 0) { mask 308 drivers/gpio/gpio-cs5535.c ulong mask_orig = mask; mask 337 drivers/gpio/gpio-cs5535.c mask &= 0x1F7FFFFF; mask 341 drivers/gpio/gpio-cs5535.c mask &= ~(1 << 28); mask 343 drivers/gpio/gpio-cs5535.c if (mask_orig != mask) mask 345 drivers/gpio/gpio-cs5535.c mask_orig, mask); mask 94 drivers/gpio/gpio-davinci.c u32 mask = __gpio_mask(offset); mask 100 drivers/gpio/gpio-davinci.c temp &= ~mask; mask 101 drivers/gpio/gpio-davinci.c writel_relaxed(mask, value ? &g->set_data : &g->clr_data); mask 103 drivers/gpio/gpio-davinci.c temp |= mask; mask 301 drivers/gpio/gpio-davinci.c uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); mask 303 drivers/gpio/gpio-davinci.c writel_relaxed(mask, &g->clr_falling); mask 304 drivers/gpio/gpio-davinci.c writel_relaxed(mask, &g->clr_rising); mask 310 drivers/gpio/gpio-davinci.c uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); mask 318 drivers/gpio/gpio-davinci.c writel_relaxed(mask, &g->set_falling); mask 320 drivers/gpio/gpio-davinci.c writel_relaxed(mask, &g->set_rising); mask 342 drivers/gpio/gpio-davinci.c u32 mask = 0xffff; mask 354 drivers/gpio/gpio-davinci.c mask <<= 16; mask 364 drivers/gpio/gpio-davinci.c status = readl_relaxed(&g->intstat) & mask; mask 415 drivers/gpio/gpio-davinci.c u32 mask, i; mask 426 drivers/gpio/gpio-davinci.c mask = __gpio_mask(i); mask 431 drivers/gpio/gpio-davinci.c writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) mask 433 drivers/gpio/gpio-davinci.c writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) mask 347 drivers/gpio/gpio-dwapb.c unsigned long mask = BIT(offset); mask 353 drivers/gpio/gpio-dwapb.c dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); mask 355 drivers/gpio/gpio-dwapb.c dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); mask 435 drivers/gpio/gpio-dwapb.c ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); mask 90 drivers/gpio/gpio-ftgpio010.c u32 mask = BIT(irqd_to_hwirq(d)); mask 100 drivers/gpio/gpio-ftgpio010.c reg_type &= ~mask; mask 101 drivers/gpio/gpio-ftgpio010.c reg_both |= mask; mask 105 drivers/gpio/gpio-ftgpio010.c reg_type &= ~mask; mask 106 drivers/gpio/gpio-ftgpio010.c reg_both &= ~mask; mask 107 drivers/gpio/gpio-ftgpio010.c reg_level &= ~mask; mask 111 drivers/gpio/gpio-ftgpio010.c reg_type &= ~mask; mask 112 drivers/gpio/gpio-ftgpio010.c reg_both &= ~mask; mask 113 drivers/gpio/gpio-ftgpio010.c reg_level |= mask; mask 117 drivers/gpio/gpio-ftgpio010.c reg_type |= mask; mask 118 drivers/gpio/gpio-ftgpio010.c reg_level &= ~mask; mask 122 drivers/gpio/gpio-ftgpio010.c reg_type |= mask; mask 123 drivers/gpio/gpio-ftgpio010.c reg_level |= mask; mask 53 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); mask 55 drivers/gpio/gpio-gpio-mm.c return !!(gpiommgpio->io_state[port] & mask); mask 102 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); mask 129 drivers/gpio/gpio-gpio-mm.c gpiommgpio->out_state[io_port] |= mask; mask 131 drivers/gpio/gpio-gpio-mm.c gpiommgpio->out_state[io_port] &= ~mask; mask 147 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); mask 155 drivers/gpio/gpio-gpio-mm.c if (!(gpiommgpio->io_state[port] & mask)) { mask 164 drivers/gpio/gpio-gpio-mm.c return !!(port_state & mask); mask 167 drivers/gpio/gpio-gpio-mm.c static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, mask 196 drivers/gpio/gpio-gpio-mm.c word_mask = mask[word_index] & (port_mask << word_offset); mask 217 drivers/gpio/gpio-gpio-mm.c const unsigned int mask = BIT(offset % 8); mask 224 drivers/gpio/gpio-gpio-mm.c gpiommgpio->out_state[port] |= mask; mask 226 drivers/gpio/gpio-gpio-mm.c gpiommgpio->out_state[port] &= ~mask; mask 234 drivers/gpio/gpio-gpio-mm.c unsigned long *mask, unsigned long *bits) mask 247 drivers/gpio/gpio-gpio-mm.c if (!mask[BIT_WORD(i)]) { mask 254 drivers/gpio/gpio-gpio-mm.c bitmask = mask[BIT_WORD(i)] & bits[BIT_WORD(i)]; mask 259 drivers/gpio/gpio-gpio-mm.c gpiommgpio->out_state[port] &= ~mask[BIT_WORD(i)]; mask 266 drivers/gpio/gpio-gpio-mm.c mask[BIT_WORD(i)] >>= gpio_reg_size; mask 121 drivers/gpio/gpio-grgpio.c u32 mask = BIT(d->hwirq); mask 133 drivers/gpio/gpio-grgpio.c pol = mask; mask 138 drivers/gpio/gpio-grgpio.c edge = mask; mask 141 drivers/gpio/gpio-grgpio.c pol = mask; mask 142 drivers/gpio/gpio-grgpio.c edge = mask; mask 150 drivers/gpio/gpio-grgpio.c ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask; mask 151 drivers/gpio/gpio-grgpio.c iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask; mask 122 drivers/gpio/gpio-hlwd.c u32 mask; mask 125 drivers/gpio/gpio-hlwd.c mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask 126 drivers/gpio/gpio-hlwd.c mask &= ~BIT(data->hwirq); mask 127 drivers/gpio/gpio-hlwd.c iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); mask 136 drivers/gpio/gpio-hlwd.c u32 mask; mask 139 drivers/gpio/gpio-hlwd.c mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask 140 drivers/gpio/gpio-hlwd.c mask |= BIT(data->hwirq); mask 141 drivers/gpio/gpio-hlwd.c iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); mask 276 drivers/gpio/gpio-intel-mid.c u32 base, gpio, mask; mask 285 drivers/gpio/gpio-intel-mid.c mask = BIT(gpio); mask 287 drivers/gpio/gpio-intel-mid.c writel(mask, gedr); mask 136 drivers/gpio/gpio-it87.c static inline void superio_set_mask(int mask, int reg) mask 139 drivers/gpio/gpio-it87.c u8 new_val = curr_val | mask; mask 145 drivers/gpio/gpio-it87.c static inline void superio_clear_mask(int mask, int reg) mask 148 drivers/gpio/gpio-it87.c u8 new_val = curr_val & ~mask; mask 156 drivers/gpio/gpio-it87.c u8 mask, group; mask 160 drivers/gpio/gpio-it87.c mask = 1 << (gpio_num % 8); mask 173 drivers/gpio/gpio-it87.c superio_set_mask(mask, group + it87_gpio->simple_base); mask 178 drivers/gpio/gpio-it87.c superio_clear_mask(mask, group + it87_gpio->output_base); mask 190 drivers/gpio/gpio-it87.c u8 mask; mask 193 drivers/gpio/gpio-it87.c mask = 1 << (gpio_num % 8); mask 196 drivers/gpio/gpio-it87.c return !!(inb(reg) & mask); mask 201 drivers/gpio/gpio-it87.c u8 mask, group; mask 205 drivers/gpio/gpio-it87.c mask = 1 << (gpio_num % 8); mask 215 drivers/gpio/gpio-it87.c superio_clear_mask(mask, group + it87_gpio->output_base); mask 227 drivers/gpio/gpio-it87.c u8 mask, curr_vals; mask 231 drivers/gpio/gpio-it87.c mask = 1 << (gpio_num % 8); mask 236 drivers/gpio/gpio-it87.c outb(curr_vals | mask, reg); mask 238 drivers/gpio/gpio-it87.c outb(curr_vals & ~mask, reg); mask 244 drivers/gpio/gpio-it87.c u8 mask, group; mask 248 drivers/gpio/gpio-it87.c mask = 1 << (gpio_num % 8); mask 258 drivers/gpio/gpio-it87.c superio_set_mask(mask, group + it87_gpio->output_base); mask 71 drivers/gpio/gpio-lp3943.c return lp3943_update_bits(lp3943, mux[offset].reg, mux[offset].mask, mask 121 drivers/gpio/gpio-lp3943.c read = (read & mux[offset].mask) >> mux[offset].shift; mask 114 drivers/gpio/gpio-max3191x.c static void max3191x_set_multiple(struct gpio_chip *gpio, unsigned long *mask, mask 231 drivers/gpio/gpio-max3191x.c static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask, mask 242 drivers/gpio/gpio-max3191x.c while ((bit = find_next_bit(mask, gpio->ngpio, bit)) != gpio->ngpio) { mask 254 drivers/gpio/gpio-max3191x.c bits[index] &= ~(mask[index] & (0xff << shift)); mask 255 drivers/gpio/gpio-max3191x.c bits[index] |= mask[index] & (in << shift); /* copy bits */ mask 207 drivers/gpio/gpio-max732x.c static void max732x_gpio_set_mask(struct gpio_chip *gc, unsigned off, int mask, mask 217 drivers/gpio/gpio-max732x.c reg_out = (reg_out & ~mask) | (val & mask); mask 235 drivers/gpio/gpio-max732x.c uint8_t mask = 1u << (off & 0x7); mask 237 drivers/gpio/gpio-max732x.c max732x_gpio_set_mask(gc, base, mask, val << (off & 0x7)); mask 241 drivers/gpio/gpio-max732x.c unsigned long *mask, unsigned long *bits) mask 243 drivers/gpio/gpio-max732x.c unsigned mask_lo = mask[0] & 0xff; mask 244 drivers/gpio/gpio-max732x.c unsigned mask_hi = (mask[0] >> 8) & 0xff; mask 255 drivers/gpio/gpio-max732x.c unsigned int mask = 1u << off; mask 257 drivers/gpio/gpio-max732x.c if ((mask & chip->dir_input) == 0) { mask 267 drivers/gpio/gpio-max732x.c if ((mask & chip->dir_output)) mask 277 drivers/gpio/gpio-max732x.c unsigned int mask = 1u << off; mask 279 drivers/gpio/gpio-max732x.c if ((mask & chip->dir_output) == 0) { mask 397 drivers/gpio/gpio-max732x.c uint16_t mask = 1 << off; mask 399 drivers/gpio/gpio-max732x.c if (!(mask & chip->dir_input)) { mask 412 drivers/gpio/gpio-max732x.c chip->irq_trig_fall |= mask; mask 414 drivers/gpio/gpio-max732x.c chip->irq_trig_fall &= ~mask; mask 417 drivers/gpio/gpio-max732x.c chip->irq_trig_raise |= mask; mask 419 drivers/gpio/gpio-max732x.c chip->irq_trig_raise &= ~mask; mask 562 drivers/gpio/gpio-max732x.c unsigned int mask = 1 << port; mask 566 drivers/gpio/gpio-max732x.c chip->dir_output |= mask; mask 569 drivers/gpio/gpio-max732x.c chip->dir_input |= mask; mask 572 drivers/gpio/gpio-max732x.c chip->dir_output |= mask; mask 573 drivers/gpio/gpio-max732x.c chip->dir_input |= mask; mask 580 drivers/gpio/gpio-max732x.c chip->mask_group_a |= mask; mask 26 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE0, mask 37 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE1, mask 48 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE2, mask 59 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE3, mask 70 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE4, mask 81 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE5, mask 92 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE6, mask 103 drivers/gpio/gpio-max77620.c .mask = MAX77620_IRQ_LVL2_GPIO_EDGE7, mask 55 drivers/gpio/gpio-max77650.c int mask, regval; mask 57 drivers/gpio/gpio-max77650.c mask = MAX77650_GPIO_DIR_MASK | MAX77650_GPIO_OUTVAL_MASK; mask 62 drivers/gpio/gpio-max77650.c MAX77650_REG_CNFG_GPIO, mask, regval); mask 147 drivers/gpio/gpio-mmio.c static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 154 drivers/gpio/gpio-mmio.c *bits &= ~*mask; mask 156 drivers/gpio/gpio-mmio.c set_mask = *mask & gc->bgpio_dir; mask 157 drivers/gpio/gpio-mmio.c get_mask = *mask & ~gc->bgpio_dir; mask 175 drivers/gpio/gpio-mmio.c static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, mask 179 drivers/gpio/gpio-mmio.c *bits &= ~*mask; mask 180 drivers/gpio/gpio-mmio.c *bits |= gc->read_reg(gc->reg_dat) & *mask; mask 187 drivers/gpio/gpio-mmio.c static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, mask 195 drivers/gpio/gpio-mmio.c *bits &= ~*mask; mask 199 drivers/gpio/gpio-mmio.c while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio) mask 222 drivers/gpio/gpio-mmio.c unsigned long mask = bgpio_line2mask(gc, gpio); mask 228 drivers/gpio/gpio-mmio.c gc->bgpio_data |= mask; mask 230 drivers/gpio/gpio-mmio.c gc->bgpio_data &= ~mask; mask 240 drivers/gpio/gpio-mmio.c unsigned long mask = bgpio_line2mask(gc, gpio); mask 243 drivers/gpio/gpio-mmio.c gc->write_reg(gc->reg_set, mask); mask 245 drivers/gpio/gpio-mmio.c gc->write_reg(gc->reg_clr, mask); mask 250 drivers/gpio/gpio-mmio.c unsigned long mask = bgpio_line2mask(gc, gpio); mask 256 drivers/gpio/gpio-mmio.c gc->bgpio_data |= mask; mask 258 drivers/gpio/gpio-mmio.c gc->bgpio_data &= ~mask; mask 266 drivers/gpio/gpio-mmio.c unsigned long *mask, unsigned long *bits, mask 276 drivers/gpio/gpio-mmio.c if (*mask == 0) mask 278 drivers/gpio/gpio-mmio.c if (__test_and_clear_bit(i, mask)) { mask 288 drivers/gpio/gpio-mmio.c unsigned long *mask, mask 297 drivers/gpio/gpio-mmio.c bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); mask 307 drivers/gpio/gpio-mmio.c static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 310 drivers/gpio/gpio-mmio.c bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); mask 313 drivers/gpio/gpio-mmio.c static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, mask 316 drivers/gpio/gpio-mmio.c bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); mask 320 drivers/gpio/gpio-mmio.c unsigned long *mask, mask 325 drivers/gpio/gpio-mmio.c bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); mask 106 drivers/gpio/gpio-mockup.c unsigned long *mask, unsigned long *bits) mask 112 drivers/gpio/gpio-mockup.c for_each_set_bit(bit, mask, gc->ngpio) { mask 138 drivers/gpio/gpio-mockup.c unsigned long *mask, unsigned long *bits) mask 144 drivers/gpio/gpio-mockup.c for_each_set_bit(bit, mask, gc->ngpio) mask 135 drivers/gpio/gpio-mpc8xxx.c unsigned int mask; mask 137 drivers/gpio/gpio-mpc8xxx.c mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) mask 139 drivers/gpio/gpio-mpc8xxx.c if (mask) mask 141 drivers/gpio/gpio-mpc8xxx.c 32 - ffs(mask))); mask 106 drivers/gpio/gpio-msic.c unsigned mask; mask 109 drivers/gpio/gpio-msic.c mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK; mask 115 drivers/gpio/gpio-msic.c return intel_msic_reg_update(reg, value, mask); mask 156 drivers/gpio/gpio-mt7621.c u32 mask = BIT(pin); mask 160 drivers/gpio/gpio-mt7621.c rg->hlevel | rg->llevel) & mask) mask 166 drivers/gpio/gpio-mt7621.c rg->rising &= ~mask; mask 167 drivers/gpio/gpio-mt7621.c rg->falling &= ~mask; mask 168 drivers/gpio/gpio-mt7621.c rg->hlevel &= ~mask; mask 169 drivers/gpio/gpio-mt7621.c rg->llevel &= ~mask; mask 173 drivers/gpio/gpio-mt7621.c rg->rising |= mask; mask 174 drivers/gpio/gpio-mt7621.c rg->falling |= mask; mask 177 drivers/gpio/gpio-mt7621.c rg->rising |= mask; mask 180 drivers/gpio/gpio-mt7621.c rg->falling |= mask; mask 183 drivers/gpio/gpio-mt7621.c rg->hlevel |= mask; mask 186 drivers/gpio/gpio-mt7621.c rg->llevel |= mask; mask 404 drivers/gpio/gpio-mvebu.c u32 mask = d->mask; mask 407 drivers/gpio/gpio-mvebu.c mvebu_gpio_write_edge_cause(mvchip, ~mask); mask 416 drivers/gpio/gpio-mvebu.c u32 mask = d->mask; mask 419 drivers/gpio/gpio-mvebu.c ct->mask_cache_priv &= ~mask; mask 429 drivers/gpio/gpio-mvebu.c u32 mask = d->mask; mask 432 drivers/gpio/gpio-mvebu.c ct->mask_cache_priv |= mask; mask 442 drivers/gpio/gpio-mvebu.c u32 mask = d->mask; mask 445 drivers/gpio/gpio-mvebu.c ct->mask_cache_priv &= ~mask; mask 455 drivers/gpio/gpio-mvebu.c u32 mask = d->mask; mask 458 drivers/gpio/gpio-mvebu.c ct->mask_cache_priv |= mask; mask 364 drivers/gpio/gpio-mxc.c ct->regs.mask = GPIO_IMR; mask 247 drivers/gpio/gpio-mxs.c u32 mask = 1 << offset; mask 251 drivers/gpio/gpio-mxs.c return !(dir & mask); mask 53 drivers/gpio/gpio-octeon.c u64 mask = 1ull << offset; mask 55 drivers/gpio/gpio-octeon.c cvmx_write_csr(reg, mask); mask 92 drivers/gpio/gpio-omap.c static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) mask 97 drivers/gpio/gpio-omap.c val |= mask; mask 99 drivers/gpio/gpio-omap.c val &= ~mask; mask 494 drivers/gpio/gpio-omap.c u32 mask = (BIT(bank->width)) - 1; mask 500 drivers/gpio/gpio-omap.c l &= mask; mask 850 drivers/gpio/gpio-omap.c static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, mask 859 drivers/gpio/gpio-omap.c m = direction & *mask; mask 863 drivers/gpio/gpio-omap.c m = ~direction & *mask; mask 916 drivers/gpio/gpio-omap.c static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, mask 925 drivers/gpio/gpio-omap.c l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); mask 1103 drivers/gpio/gpio-omap.c u32 mask, nowake; mask 1111 drivers/gpio/gpio-omap.c mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; mask 1112 drivers/gpio/gpio-omap.c mask &= ~bank->context.risingdetect; mask 1113 drivers/gpio/gpio-omap.c bank->saved_datain |= mask; mask 1116 drivers/gpio/gpio-omap.c mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; mask 1117 drivers/gpio/gpio-omap.c mask &= ~bank->context.fallingdetect; mask 1118 drivers/gpio/gpio-omap.c bank->saved_datain &= ~mask; mask 456 drivers/gpio/gpio-pca953x.c unsigned long *mask, unsigned long *bits) mask 470 drivers/gpio/gpio-pca953x.c bank_mask = mask[bank / sizeof(*mask)] >> mask 471 drivers/gpio/gpio-pca953x.c ((bank % sizeof(*mask)) * 8); mask 644 drivers/gpio/gpio-pca953x.c u8 mask = BIT(d->hwirq % BANK_SZ); mask 653 drivers/gpio/gpio-pca953x.c chip->irq_trig_fall[bank_nb] |= mask; mask 655 drivers/gpio/gpio-pca953x.c chip->irq_trig_fall[bank_nb] &= ~mask; mask 658 drivers/gpio/gpio-pca953x.c chip->irq_trig_raise[bank_nb] |= mask; mask 660 drivers/gpio/gpio-pca953x.c chip->irq_trig_raise[bank_nb] &= ~mask; mask 669 drivers/gpio/gpio-pca953x.c u8 mask = BIT(d->hwirq % BANK_SZ); mask 671 drivers/gpio/gpio-pca953x.c chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask; mask 672 drivers/gpio/gpio-pca953x.c chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask; mask 85 drivers/gpio/gpio-pci-idio-16.c unsigned long mask = BIT(offset); mask 88 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->out0_7) & mask); mask 91 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->out8_15) & (mask >> 8)); mask 94 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->in0_7) & (mask >> 16)); mask 96 drivers/gpio/gpio-pci-idio-16.c return !!(ioread8(&idio16gpio->reg->in8_15) & (mask >> 24)); mask 100 drivers/gpio/gpio-pci-idio-16.c unsigned long *mask, unsigned long *bits) mask 131 drivers/gpio/gpio-pci-idio-16.c word_mask = mask[word_index] & (port_mask << word_offset); mask 151 drivers/gpio/gpio-pci-idio-16.c unsigned int mask = BIT(offset); mask 160 drivers/gpio/gpio-pci-idio-16.c mask >>= 8; mask 168 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(base) | mask; mask 170 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(base) & ~mask; mask 178 drivers/gpio/gpio-pci-idio-16.c unsigned long *mask, unsigned long *bits) mask 187 drivers/gpio/gpio-pci-idio-16.c if (*mask & 0xFF) { mask 188 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(&idio16gpio->reg->out0_7) & ~*mask; mask 189 drivers/gpio/gpio-pci-idio-16.c out_state |= *mask & *bits; mask 194 drivers/gpio/gpio-pci-idio-16.c *mask >>= 8; mask 197 drivers/gpio/gpio-pci-idio-16.c if (*mask & 0xFF) { mask 199 drivers/gpio/gpio-pci-idio-16.c out_state = ioread8(&idio16gpio->reg->out8_15) & ~*mask; mask 200 drivers/gpio/gpio-pci-idio-16.c out_state |= *mask & *bits; mask 215 drivers/gpio/gpio-pci-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); mask 218 drivers/gpio/gpio-pci-idio-16.c idio16gpio->irq_mask &= ~mask; mask 233 drivers/gpio/gpio-pci-idio-16.c const unsigned long mask = BIT(irqd_to_hwirq(data)); mask 237 drivers/gpio/gpio-pci-idio-16.c idio16gpio->irq_mask |= mask; mask 198 drivers/gpio/gpio-pcie-idio-24.c unsigned long *mask, unsigned long *bits) mask 231 drivers/gpio/gpio-pcie-idio-24.c word_mask = mask[word_index] & (port_mask << word_offset); mask 258 drivers/gpio/gpio-pcie-idio-24.c const unsigned int mask = BIT(offset % 8); mask 284 drivers/gpio/gpio-pcie-idio-24.c out_state = ioread8(base) | mask; mask 286 drivers/gpio/gpio-pcie-idio-24.c out_state = ioread8(base) & ~mask; mask 294 drivers/gpio/gpio-pcie-idio-24.c unsigned long *mask, unsigned long *bits) mask 312 drivers/gpio/gpio-pcie-idio-24.c const unsigned long ttl_mask = (mask[ttl_i] >> word_offset) & port_mask; mask 321 drivers/gpio/gpio-pcie-idio-24.c gpio_mask = (*mask >> bits_offset) & port_mask; mask 96 drivers/gpio/gpio-pisosr.c unsigned long *mask, unsigned long *bits) mask 233 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); mask 237 drivers/gpio/gpio-pl061.c gpioie = readb(pl061->base + GPIOIE) & ~mask; mask 246 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); mask 250 drivers/gpio/gpio-pl061.c gpioie = readb(pl061->base + GPIOIE) | mask; mask 267 drivers/gpio/gpio-pl061.c u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); mask 270 drivers/gpio/gpio-pl061.c writeb(mask, pl061->base + GPIOIC); mask 409 drivers/gpio/gpio-pl061.c .mask = 0x000fffff, mask 263 drivers/gpio/gpio-pxa.c uint32_t value, mask = GPIO_bit(offset); mask 277 drivers/gpio/gpio-pxa.c value |= mask; mask 279 drivers/gpio/gpio-pxa.c value &= ~mask; mask 290 drivers/gpio/gpio-pxa.c uint32_t tmp, mask = GPIO_bit(offset); mask 294 drivers/gpio/gpio-pxa.c writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); mask 306 drivers/gpio/gpio-pxa.c tmp &= ~mask; mask 308 drivers/gpio/gpio-pxa.c tmp |= mask; mask 404 drivers/gpio/gpio-pxa.c unsigned long gpdr, mask = GPIO_bit(gpio); mask 422 drivers/gpio/gpio-pxa.c writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); mask 424 drivers/gpio/gpio-pxa.c writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); mask 427 drivers/gpio/gpio-pxa.c c->irq_edge_rise |= mask; mask 429 drivers/gpio/gpio-pxa.c c->irq_edge_rise &= ~mask; mask 432 drivers/gpio/gpio-pxa.c c->irq_edge_fall |= mask; mask 434 drivers/gpio/gpio-pxa.c c->irq_edge_fall &= ~mask; mask 313 drivers/gpio/gpio-rcar.c static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, mask 320 drivers/gpio/gpio-rcar.c bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); mask 560 drivers/gpio/gpio-rcar.c u32 mask; mask 566 drivers/gpio/gpio-rcar.c mask = BIT(offset); mask 568 drivers/gpio/gpio-rcar.c if (!(p->bank_info.iointsel & mask)) { mask 569 drivers/gpio/gpio-rcar.c if (p->bank_info.inoutsel & mask) mask 572 drivers/gpio/gpio-rcar.c !!(p->bank_info.outdt & mask)); mask 581 drivers/gpio/gpio-rcar.c !(p->bank_info.posneg & mask), mask 582 drivers/gpio/gpio-rcar.c !(p->bank_info.edglevel & mask), mask 583 drivers/gpio/gpio-rcar.c !!(p->bank_info.bothedge & mask)); mask 585 drivers/gpio/gpio-rcar.c if (p->bank_info.intmsk & mask) mask 586 drivers/gpio/gpio-rcar.c gpio_rcar_write(p, MSKCLR, mask); mask 55 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); mask 60 drivers/gpio/gpio-reg.c val |= mask; mask 62 drivers/gpio/gpio-reg.c val &= ~mask; mask 71 drivers/gpio/gpio-reg.c u32 val, mask = BIT(offset); mask 73 drivers/gpio/gpio-reg.c if (r->direction & mask) { mask 83 drivers/gpio/gpio-reg.c return !!(val & mask); mask 86 drivers/gpio/gpio-reg.c static void gpio_reg_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 93 drivers/gpio/gpio-reg.c r->out = (r->out & ~*mask) | (*bits & *mask); mask 125 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); mask 128 drivers/gpio/gpio-sa1100.c if ((sgc->irqrising | sgc->irqfalling) & mask) mask 134 drivers/gpio/gpio-sa1100.c sgc->irqrising |= mask; mask 136 drivers/gpio/gpio-sa1100.c sgc->irqrising &= ~mask; mask 138 drivers/gpio/gpio-sa1100.c sgc->irqfalling |= mask; mask 140 drivers/gpio/gpio-sa1100.c sgc->irqfalling &= ~mask; mask 160 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); mask 162 drivers/gpio/gpio-sa1100.c sgc->irqmask &= ~mask; mask 170 drivers/gpio/gpio-sa1100.c unsigned int mask = BIT(d->hwirq); mask 172 drivers/gpio/gpio-sa1100.c sgc->irqmask |= mask; mask 229 drivers/gpio/gpio-sa1100.c unsigned int irq, mask; mask 232 drivers/gpio/gpio-sa1100.c mask = readl_relaxed(gedr); mask 238 drivers/gpio/gpio-sa1100.c writel_relaxed(mask, gedr); mask 242 drivers/gpio/gpio-sa1100.c if (mask & 1) mask 244 drivers/gpio/gpio-sa1100.c mask >>= 1; mask 246 drivers/gpio/gpio-sa1100.c } while (mask); mask 248 drivers/gpio/gpio-sa1100.c mask = readl_relaxed(gedr); mask 249 drivers/gpio/gpio-sa1100.c } while (mask); mask 63 drivers/gpio/gpio-sama5d2-piobu.c unsigned int mask = BIT(PIOBU_DET_OFFSET + pin); mask 65 drivers/gpio/gpio-sama5d2-piobu.c ret = regmap_update_bits(piobu->regmap, PIOBU_BMPR, mask, 0); mask 69 drivers/gpio/gpio-sama5d2-piobu.c ret = regmap_update_bits(piobu->regmap, PIOBU_NMPR, mask, 0); mask 73 drivers/gpio/gpio-sama5d2-piobu.c return regmap_update_bits(piobu->regmap, PIOBU_WKPR, mask, 0); mask 80 drivers/gpio/gpio-sama5d2-piobu.c unsigned int mask, unsigned int value) mask 88 drivers/gpio/gpio-sama5d2-piobu.c return regmap_update_bits(piobu->regmap, reg, mask, value); mask 96 drivers/gpio/gpio-sama5d2-piobu.c unsigned int mask) mask 108 drivers/gpio/gpio-sama5d2-piobu.c return val & mask; mask 172 drivers/gpio/gpio-siox.c u8 mask = 1 << (19 - offset); mask 177 drivers/gpio/gpio-siox.c ddata->setdata[0] |= mask; mask 179 drivers/gpio/gpio-siox.c ddata->setdata[0] &= ~mask; mask 162 drivers/gpio/gpio-sodaville.c ct->regs.mask = GPIO_INT; mask 46 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 53 drivers/gpio/gpio-stmpe.c return !!(ret & mask); mask 62 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 69 drivers/gpio/gpio-stmpe.c stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); mask 71 drivers/gpio/gpio-stmpe.c stmpe_reg_write(stmpe, reg, mask); mask 80 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 87 drivers/gpio/gpio-stmpe.c return !(ret & mask); mask 96 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 100 drivers/gpio/gpio-stmpe.c return stmpe_set_bits(stmpe, reg, mask, mask); mask 109 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 111 drivers/gpio/gpio-stmpe.c return stmpe_set_bits(stmpe, reg, mask, 0); mask 143 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); mask 154 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_RE][regoffset] |= mask; mask 156 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; mask 159 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_FE][regoffset] |= mask; mask 161 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; mask 231 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); mask 233 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; mask 242 drivers/gpio/gpio-stmpe.c int mask = BIT(offset % 8); mask 244 drivers/gpio/gpio-stmpe.c stmpe_gpio->regs[REG_IE][regoffset] |= mask; mask 257 drivers/gpio/gpio-stmpe.c u8 mask = BIT(offset % 8); mask 264 drivers/gpio/gpio-stmpe.c dir = !!(ret & mask); mask 307 drivers/gpio/gpio-stmpe.c edge_det = !!(ret & mask); mask 316 drivers/gpio/gpio-stmpe.c rise = !!(ret & mask); mask 320 drivers/gpio/gpio-stmpe.c fall = !!(ret & mask); mask 334 drivers/gpio/gpio-stmpe.c irqen = !!(ret & mask); mask 60 drivers/gpio/gpio-tb10x.c u32 mask, u32 val) mask 68 drivers/gpio/gpio-tb10x.c r = (r & ~mask) | (val & mask); mask 208 drivers/gpio/gpio-tb10x.c gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN; mask 42 drivers/gpio/gpio-tc3589x.c u8 mask = BIT(offset % 8); mask 49 drivers/gpio/gpio-tc3589x.c return !!(ret & mask); mask 160 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); mask 163 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; mask 167 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; mask 170 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IS][regoffset] |= mask; mask 172 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; mask 175 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; mask 177 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; mask 225 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); mask 227 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; mask 236 drivers/gpio/gpio-tc3589x.c int mask = BIT(offset % 8); mask 238 drivers/gpio/gpio-tc3589x.c tc3589x_gpio->regs[REG_IE][regoffset] |= mask; mask 497 drivers/gpio/gpio-tegra.c u32 port, bit, mask; mask 501 drivers/gpio/gpio-tegra.c mask = BIT(bit); mask 504 drivers/gpio/gpio-tegra.c bank->wake_enb[port] |= mask; mask 506 drivers/gpio/gpio-tegra.c bank->wake_enb[port] &= ~mask; mask 271 drivers/gpio/gpio-thunderx.c unsigned long *mask, mask 279 drivers/gpio/gpio-thunderx.c set_bits = bits[bank] & mask[bank]; mask 280 drivers/gpio/gpio-thunderx.c clear_bits = ~bits[bank] & mask[bank]; mask 60 drivers/gpio/gpio-tpic2810.c static void tpic2810_set_mask_bits(struct gpio_chip *chip, u8 mask, u8 bits) mask 68 drivers/gpio/gpio-tpic2810.c buffer = gpio->buffer & ~mask; mask 69 drivers/gpio/gpio-tpic2810.c buffer |= (mask & bits); mask 84 drivers/gpio/gpio-tpic2810.c static void tpic2810_set_multiple(struct gpio_chip *chip, unsigned long *mask, mask 87 drivers/gpio/gpio-tpic2810.c tpic2810_set_mask_bits(chip, *mask, *bits); mask 56 drivers/gpio/gpio-tps6586x.c uint8_t val, mask; mask 61 drivers/gpio/gpio-tps6586x.c mask = 0x3 << (offset * 2); mask 64 drivers/gpio/gpio-tps6586x.c val, mask); mask 113 drivers/gpio/gpio-tqmx86.c u8 gpiic, mask; mask 115 drivers/gpio/gpio-tqmx86.c mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); mask 119 drivers/gpio/gpio-tqmx86.c gpiic &= ~mask; mask 130 drivers/gpio/gpio-tqmx86.c u8 gpiic, mask; mask 132 drivers/gpio/gpio-tqmx86.c mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS); mask 136 drivers/gpio/gpio-tqmx86.c gpiic &= ~mask; mask 184 drivers/gpio/gpio-ts5500.c static inline void ts5500_set_mask(u8 mask, u8 addr) mask 187 drivers/gpio/gpio-ts5500.c val |= mask; mask 191 drivers/gpio/gpio-ts5500.c static inline void ts5500_clear_mask(u8 mask, u8 addr) mask 194 drivers/gpio/gpio-ts5500.c val &= ~mask; mask 123 drivers/gpio/gpio-twl4030.c u8 mask = LEDEN_LEDAON | LEDEN_LEDAPWM; mask 126 drivers/gpio/gpio-twl4030.c mask <<= 1; mask 129 drivers/gpio/gpio-twl4030.c cached_leden &= ~mask; mask 131 drivers/gpio/gpio-twl4030.c cached_leden |= mask; mask 56 drivers/gpio/gpio-uniphier.c unsigned int *bank, u32 *mask) mask 59 drivers/gpio/gpio-uniphier.c *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); mask 63 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) mask 70 drivers/gpio/gpio-uniphier.c tmp &= ~mask; mask 71 drivers/gpio/gpio-uniphier.c tmp |= mask & val; mask 77 drivers/gpio/gpio-uniphier.c unsigned int reg, u32 mask, u32 val) mask 81 drivers/gpio/gpio-uniphier.c if (!mask) mask 85 drivers/gpio/gpio-uniphier.c mask, val); mask 93 drivers/gpio/gpio-uniphier.c u32 mask; mask 95 drivers/gpio/gpio-uniphier.c uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); mask 97 drivers/gpio/gpio-uniphier.c uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); mask 105 drivers/gpio/gpio-uniphier.c u32 mask; mask 107 drivers/gpio/gpio-uniphier.c uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); mask 110 drivers/gpio/gpio-uniphier.c return !!(readl(priv->regs + reg_offset) & mask); mask 148 drivers/gpio/gpio-uniphier.c unsigned long *mask, unsigned long *bits) mask 156 drivers/gpio/gpio-uniphier.c bank_mask = (mask[BIT_WORD(i)] >> shift) & mask 187 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); mask 189 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); mask 197 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); mask 199 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); mask 207 drivers/gpio/gpio-uniphier.c u32 mask = BIT(data->hwirq); mask 211 drivers/gpio/gpio-uniphier.c val = mask; mask 215 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); mask 217 drivers/gpio/gpio-uniphier.c uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); mask 87 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); mask 91 drivers/gpio/gpio-vf610.c mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); mask 92 drivers/gpio/gpio-vf610.c if (mask) mask 102 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); mask 105 drivers/gpio/gpio-vf610.c vf610_gpio_writel(mask, port->gpio_base + offset); mask 111 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); mask 116 drivers/gpio/gpio-vf610.c val &= ~mask; mask 127 drivers/gpio/gpio-vf610.c unsigned long mask = BIT(gpio); mask 130 drivers/gpio/gpio-vf610.c vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR); mask 59 drivers/gpio/gpio-viperboard.c u16 mask; mask 262 drivers/gpio/gpio-viperboard.c gbmsg->mask = cpu_to_be16(0x0001 << offset); mask 325 drivers/gpio/gpio-viperboard.c gbmsg->mask = cpu_to_be16(0x0001 << offset); mask 228 drivers/gpio/gpio-vr41xx.c u16 mask; mask 231 drivers/gpio/gpio-vr41xx.c mask = 1 << pin; mask 233 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTTYPL, mask); mask 235 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTHTSELL, mask); mask 237 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTHTSELL, mask); mask 241 drivers/gpio/gpio-vr41xx.c giu_set(GIUFEDGEINHL, mask); mask 242 drivers/gpio/gpio-vr41xx.c giu_clear(GIUREDGEINHL, mask); mask 245 drivers/gpio/gpio-vr41xx.c giu_clear(GIUFEDGEINHL, mask); mask 246 drivers/gpio/gpio-vr41xx.c giu_set(GIUREDGEINHL, mask); mask 249 drivers/gpio/gpio-vr41xx.c giu_set(GIUFEDGEINHL, mask); mask 250 drivers/gpio/gpio-vr41xx.c giu_set(GIUREDGEINHL, mask); mask 258 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTTYPL, mask); mask 259 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTHTSELL, mask); mask 264 drivers/gpio/gpio-vr41xx.c giu_write(GIUINTSTATL, mask); mask 266 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - GIUINT_HIGH_OFFSET); mask 268 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTTYPH, mask); mask 270 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTHTSELH, mask); mask 272 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTHTSELH, mask); mask 276 drivers/gpio/gpio-vr41xx.c giu_set(GIUFEDGEINHH, mask); mask 277 drivers/gpio/gpio-vr41xx.c giu_clear(GIUREDGEINHH, mask); mask 280 drivers/gpio/gpio-vr41xx.c giu_clear(GIUFEDGEINHH, mask); mask 281 drivers/gpio/gpio-vr41xx.c giu_set(GIUREDGEINHH, mask); mask 284 drivers/gpio/gpio-vr41xx.c giu_set(GIUFEDGEINHH, mask); mask 285 drivers/gpio/gpio-vr41xx.c giu_set(GIUREDGEINHH, mask); mask 293 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTTYPH, mask); mask 294 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTHTSELH, mask); mask 299 drivers/gpio/gpio-vr41xx.c giu_write(GIUINTSTATH, mask); mask 306 drivers/gpio/gpio-vr41xx.c u16 mask; mask 309 drivers/gpio/gpio-vr41xx.c mask = 1 << pin; mask 311 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTALSELL, mask); mask 313 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTALSELL, mask); mask 314 drivers/gpio/gpio-vr41xx.c giu_write(GIUINTSTATL, mask); mask 316 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - GIUINT_HIGH_OFFSET); mask 318 drivers/gpio/gpio-vr41xx.c giu_set(GIUINTALSELH, mask); mask 320 drivers/gpio/gpio-vr41xx.c giu_clear(GIUINTALSELH, mask); mask 321 drivers/gpio/gpio-vr41xx.c giu_write(GIUINTSTATH, mask); mask 328 drivers/gpio/gpio-vr41xx.c u16 offset, mask, reg; mask 336 drivers/gpio/gpio-vr41xx.c mask = 1 << pin; mask 339 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 16); mask 343 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 32); mask 348 drivers/gpio/gpio-vr41xx.c mask = PIOEN0; mask 352 drivers/gpio/gpio-vr41xx.c mask = PIOEN1; mask 364 drivers/gpio/gpio-vr41xx.c reg |= mask; mask 366 drivers/gpio/gpio-vr41xx.c reg &= ~mask; mask 376 drivers/gpio/gpio-vr41xx.c u16 reg, mask; mask 383 drivers/gpio/gpio-vr41xx.c mask = 1 << pin; mask 386 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 16); mask 389 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 32); mask 392 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 48); mask 395 drivers/gpio/gpio-vr41xx.c if (reg & mask) mask 404 drivers/gpio/gpio-vr41xx.c u16 offset, mask, reg; mask 412 drivers/gpio/gpio-vr41xx.c mask = 1 << pin; mask 415 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 16); mask 418 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 32); mask 421 drivers/gpio/gpio-vr41xx.c mask = 1 << (pin - 48); mask 428 drivers/gpio/gpio-vr41xx.c reg |= mask; mask 430 drivers/gpio/gpio-vr41xx.c reg &= ~mask; mask 117 drivers/gpio/gpio-wcove.c unsigned int reg, mask; mask 121 drivers/gpio/gpio-wcove.c mask = BIT(gpio % GROUP0_NR_IRQS); mask 124 drivers/gpio/gpio-wcove.c mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS); mask 128 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, mask); mask 130 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, 0); mask 324 drivers/gpio/gpio-wcove.c unsigned int pending, virq, gpio, mask, offset; mask 342 drivers/gpio/gpio-wcove.c mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) : mask 347 drivers/gpio/gpio-wcove.c mask, mask); mask 57 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 59 drivers/gpio/gpio-ws16c48.c return !!(ws16c48gpio->io_state[port] & mask); mask 66 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 71 drivers/gpio/gpio-ws16c48.c ws16c48gpio->io_state[port] |= mask; mask 72 drivers/gpio/gpio-ws16c48.c ws16c48gpio->out_state[port] &= ~mask; mask 85 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 90 drivers/gpio/gpio-ws16c48.c ws16c48gpio->io_state[port] &= ~mask; mask 92 drivers/gpio/gpio-ws16c48.c ws16c48gpio->out_state[port] |= mask; mask 94 drivers/gpio/gpio-ws16c48.c ws16c48gpio->out_state[port] &= ~mask; mask 106 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 113 drivers/gpio/gpio-ws16c48.c if (!(ws16c48gpio->io_state[port] & mask)) { mask 122 drivers/gpio/gpio-ws16c48.c return !!(port_state & mask); mask 126 drivers/gpio/gpio-ws16c48.c unsigned long *mask, unsigned long *bits) mask 154 drivers/gpio/gpio-ws16c48.c word_mask = mask[word_index] & (port_mask << word_offset); mask 174 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 180 drivers/gpio/gpio-ws16c48.c if (ws16c48gpio->io_state[port] & mask) { mask 186 drivers/gpio/gpio-ws16c48.c ws16c48gpio->out_state[port] |= mask; mask 188 drivers/gpio/gpio-ws16c48.c ws16c48gpio->out_state[port] &= ~mask; mask 195 drivers/gpio/gpio-ws16c48.c unsigned long *mask, unsigned long *bits) mask 208 drivers/gpio/gpio-ws16c48.c if (!mask[BIT_WORD(i)]) { mask 216 drivers/gpio/gpio-ws16c48.c iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port]; mask 229 drivers/gpio/gpio-ws16c48.c mask[BIT_WORD(i)] >>= gpio_reg_size; mask 240 drivers/gpio/gpio-ws16c48.c const unsigned mask = BIT(offset % 8); mask 253 drivers/gpio/gpio-ws16c48.c outb(port_state & ~mask, ws16c48gpio->base + 8 + port); mask 254 drivers/gpio/gpio-ws16c48.c outb(port_state | mask, ws16c48gpio->base + 8 + port); mask 265 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); mask 275 drivers/gpio/gpio-ws16c48.c ws16c48gpio->irq_mask &= ~mask; mask 289 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); mask 299 drivers/gpio/gpio-ws16c48.c ws16c48gpio->irq_mask |= mask; mask 313 drivers/gpio/gpio-ws16c48.c const unsigned long mask = BIT(offset); mask 327 drivers/gpio/gpio-ws16c48.c ws16c48gpio->flow_mask |= mask; mask 330 drivers/gpio/gpio-ws16c48.c ws16c48gpio->flow_mask &= ~mask; mask 136 drivers/gpio/gpio-xilinx.c static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 148 drivers/gpio/gpio-xilinx.c if (*mask == 0) mask 159 drivers/gpio/gpio-xilinx.c if (__test_and_clear_bit(i, mask)) { mask 116 drivers/gpio/gpio-xtensa.c u32 mask = BIT(offset); mask 121 drivers/gpio/gpio-xtensa.c :: "a" (val), "a" (mask)); mask 181 drivers/gpio/gpio-zx.c u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); mask 185 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; mask 187 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; mask 196 drivers/gpio/gpio-zx.c u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); mask 200 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; mask 202 drivers/gpio/gpio-zx.c gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; mask 558 drivers/gpio/gpiolib-acpi.c const enum gpiod_flags mask = mask 581 drivers/gpio/gpiolib-acpi.c *flags = (*flags & ~mask) | (update & mask); mask 3279 drivers/gpio/gpiolib.c unsigned long *mask, unsigned long *bits) mask 3282 drivers/gpio/gpiolib.c return chip->get_multiple(chip, mask, bits); mask 3286 drivers/gpio/gpiolib.c for_each_set_bit(i, mask, chip->ngpio) { mask 3337 drivers/gpio/gpiolib.c unsigned long *mask, *bits; mask 3341 drivers/gpio/gpiolib.c mask = fastpath; mask 3343 drivers/gpio/gpiolib.c mask = kmalloc_array(2 * BITS_TO_LONGS(chip->ngpio), mask 3344 drivers/gpio/gpiolib.c sizeof(*mask), mask 3346 drivers/gpio/gpiolib.c if (!mask) mask 3350 drivers/gpio/gpiolib.c bits = mask + BITS_TO_LONGS(chip->ngpio); mask 3351 drivers/gpio/gpiolib.c bitmap_zero(mask, chip->ngpio); mask 3362 drivers/gpio/gpiolib.c __set_bit(hwgpio, mask); mask 3371 drivers/gpio/gpiolib.c ret = gpio_chip_get_multiple(chip, mask, bits); mask 3373 drivers/gpio/gpiolib.c if (mask != fastpath) mask 3374 drivers/gpio/gpiolib.c kfree(mask); mask 3394 drivers/gpio/gpiolib.c if (mask != fastpath) mask 3395 drivers/gpio/gpiolib.c kfree(mask); mask 3570 drivers/gpio/gpiolib.c unsigned long *mask, unsigned long *bits) mask 3573 drivers/gpio/gpiolib.c chip->set_multiple(chip, mask, bits); mask 3578 drivers/gpio/gpiolib.c for_each_set_bit(i, mask, chip->ngpio) mask 3620 drivers/gpio/gpiolib.c unsigned long *mask, *bits; mask 3624 drivers/gpio/gpiolib.c mask = fastpath; mask 3626 drivers/gpio/gpiolib.c mask = kmalloc_array(2 * BITS_TO_LONGS(chip->ngpio), mask 3627 drivers/gpio/gpiolib.c sizeof(*mask), mask 3629 drivers/gpio/gpiolib.c if (!mask) mask 3633 drivers/gpio/gpiolib.c bits = mask + BITS_TO_LONGS(chip->ngpio); mask 3634 drivers/gpio/gpiolib.c bitmap_zero(mask, chip->ngpio); mask 3663 drivers/gpio/gpiolib.c __set_bit(hwgpio, mask); mask 3679 drivers/gpio/gpiolib.c gpio_chip_set_multiple(chip, mask, bits); mask 3681 drivers/gpio/gpiolib.c if (mask != fastpath) mask 3682 drivers/gpio/gpiolib.c kfree(mask); mask 1089 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_P(reg, val, mask) \ mask 1092 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ &= (mask); \ mask 1093 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ |= ((val) & ~(mask)); \ mask 1098 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define WREG32_PLL_P(reg, val, mask) \ mask 1101 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ &= (mask); \ mask 1102 drivers/gpu/drm/amd/amdgpu/amdgpu.h tmp_ |= ((val) & ~(mask)); \ mask 132 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c static void amdgpu_atif_parse_notification(struct amdgpu_atif_notifications *n, u32 mask) mask 134 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED; mask 135 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED; mask 136 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED; mask 137 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED; mask 138 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED; mask 139 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c n->gpu_package_power_limit = mask & ATIF_GPU_PACKAGE_POWER_LIMIT_REQUEST_SUPPORTED; mask 152 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mask) mask 154 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED; mask 155 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED; mask 156 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED; mask 158 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c mask & ATIF_QUERY_BACKLIGHT_TRANSFER_CHARACTERISTICS_SUPPORTED; mask 159 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->ready_to_undock = mask & ATIF_READY_TO_UNDOCK_NOTIFICATION_SUPPORTED; mask 160 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->external_gpu_information = mask & ATIF_GET_EXTERNAL_GPU_INFORMATION_SUPPORTED; mask 545 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mask) mask 547 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED; mask 548 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; mask 549 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; mask 550 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; mask 78 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t mask:24; mask 687 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; mask 186 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c gpio.mask = (1 << pin->ucGpioPinBitShift); mask 211 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c switch(gpio->mask) { mask 155 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mask) mask 157 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; mask 158 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; mask 159 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; mask 160 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; mask 161 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED; mask 162 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED; mask 163 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED; mask 164 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c f->disp_detection_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED; mask 144 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh) mask 149 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c memset(mask, 0, sizeof(*mask) * max_se * max_sh); mask 165 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c mask[se * max_sh + sh] |= 1u << cu; mask 352 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, mask 482 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h u32 mask; mask 858 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) mask 868 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c *mask = 0; mask 880 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c *mask |= 1 << level; mask 896 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 901 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 906 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask); mask 908 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); mask 943 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 948 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 953 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask); mask 955 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); mask 986 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 988 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 993 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask); mask 995 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask); mask 1026 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 1028 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 1033 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask); mask 1035 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask); mask 1066 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 1068 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 1073 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask); mask 1075 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask); mask 1106 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t mask = 0; mask 1108 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_read_mask(buf, count, &mask); mask 1113 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask); mask 1115 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); mask 110 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c uint32_t reg_val, uint32_t mask, bool check_changed) mask 122 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c if ((val & mask) == reg_val) mask 268 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h uint32_t field_val, uint32_t mask, bool check_changed); mask 393 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t ref, uint32_t mask) mask 396 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); mask 165 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t val, uint32_t mask); mask 168 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t ref, uint32_t mask); mask 1561 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c uint32_t mask = 0xffffffff << shift; mask 1564 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c mask &= 0xffffffff >> (bytes - len) * 8; mask 1571 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c if (!write || mask != 0xffffffff) mask 1574 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c value &= ~mask; mask 1575 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c value |= (*(uint32_t *)buf << shift) & mask; mask 1580 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c value = (value & mask) >> shift; mask 59 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ mask 60 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ mask 69 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h #define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ mask 72 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ mask 142 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t ref, uint32_t mask) mask 153 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c ref, mask); mask 298 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h uint32_t ref, uint32_t mask); mask 387 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c unsigned mask, shift, idx; mask 393 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c mask = amdgpu_vm_entries_mask(adev, cursor->level); mask 397 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c idx = (cursor->pfn >> shift) & mask; mask 1396 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c unsigned shift, parent_shift, mask; mask 1444 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c mask = amdgpu_vm_entries_mask(adev, cursor.level); mask 1445 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c pe_start = ((cursor.pfn >> shift) & mask) * 8; mask 1446 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c entry_end = (uint64_t)(mask + 1) << shift; mask 766 drivers/gpu/drm/amd/amdgpu/atom.c uint32_t dst, mask, src, saved; mask 770 drivers/gpu/drm/amd/amdgpu/atom.c mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); mask 771 drivers/gpu/drm/amd/amdgpu/atom.c SDEBUG(" mask: 0x%08x", mask); mask 774 drivers/gpu/drm/amd/amdgpu/atom.c dst &= mask; mask 3251 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c uint32_t disp_int, mask; mask 3261 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c mask = interrupt_status_offsets[hpd].hpd; mask 3263 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (disp_int & mask) { mask 3378 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c uint32_t disp_int, mask; mask 3388 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c mask = interrupt_status_offsets[hpd].hpd; mask 3390 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (disp_int & mask) { mask 3045 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t disp_int, mask, tmp; mask 3055 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c mask = interrupt_status_offsets[hpd].hpd; mask 3057 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (disp_int & mask) { mask 3137 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c uint32_t disp_int, mask, tmp; mask 3147 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c mask = interrupt_status_offsets[hpd].hpd; mask 3149 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (disp_int & mask) { mask 413 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t addr1, uint32_t ref, uint32_t mask, mask 429 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, mask); mask 1524 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 data, mask; mask 1532 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / mask 1535 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return (~data) & mask; mask 4830 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t val, uint32_t mask) mask 4832 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); mask 4837 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t ref, uint32_t mask) mask 4847 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ref, mask, 0x20); mask 4850 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ref, mask); mask 5438 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; mask 5449 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mask = 1; mask 5460 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (bitmap & mask) { mask 5462 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ao_bitmap |= mask; mask 5465 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c mask <<= 1; mask 1328 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 data, mask; mask 1335 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ mask 1338 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return ~data & mask; mask 1533 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 data, mask; mask 1538 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); mask 1539 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; mask 1546 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 data, mask; mask 1556 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask = 1; mask 1558 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask <<= k; mask 1559 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if (active_cu & mask) { mask 1560 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c data &= ~mask; mask 2261 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 mask; mask 2276 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; mask 2278 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) mask 3576 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; mask 3593 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask = 1; mask 3604 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c if (bitmap & mask) { mask 3606 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ao_bitmap |= mask; mask 3609 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask <<= 1; mask 1623 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 data, mask; mask 1631 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / mask 1634 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c return (~data) & mask; mask 3367 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 mask; mask 3383 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | mask 3388 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) mask 3434 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 tmp, i, mask; mask 3439 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK | mask 3442 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) mask 3824 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 data, mask; mask 3832 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); mask 3834 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c return (~data) & mask; mask 5109 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; mask 5126 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask = 1; mask 5137 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (bitmap & mask) { mask 5139 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ao_bitmap |= mask; mask 5142 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mask <<= 1; mask 3479 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 data, mask; mask 3486 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / mask 3489 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c return (~data) & mask; mask 3870 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 mask; mask 3894 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | mask 3899 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) mask 7118 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 data, mask; mask 7123 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); mask 7125 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; mask 7131 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; mask 7148 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mask = 1; mask 7159 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (bitmap & mask) { mask 7161 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ao_bitmap |= mask; mask 7164 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mask <<= 1; mask 819 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t addr1, uint32_t ref, uint32_t mask, mask 835 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, mask); mask 1494 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t mask, cu_bitmap, counter; mask 1506 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask = 1; mask 1512 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (cu_info->bitmap[i][j] & mask) { mask 1516 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c cu_bitmap |= mask; mask 1521 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask <<= 1; mask 2402 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 data, mask; mask 2410 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / mask 2413 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return (~data) & mask; mask 2549 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 mask; mask 2573 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | mask 2578 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) mask 5445 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t val, uint32_t mask) mask 5447 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); mask 5452 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t ref, uint32_t mask) mask 5461 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ref, mask, 0x20); mask 5464 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ref, mask); mask 6437 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 data, mask; mask 6445 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); mask 6447 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return (~data) & mask; mask 6454 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; mask 6474 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask = 1; mask 6497 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (bitmap & mask) { mask 6499 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ao_bitmap |= mask; mask 6502 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c mask <<= 1; mask 422 drivers/gpu/drm/amd/amdgpu/kv_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 436 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data &= ~config_regs->mask; mask 437 drivers/gpu/drm/amd/amdgpu/kv_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 1499 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 mask; mask 1508 drivers/gpu/drm/amd/amdgpu/kv_dpm.c mask = 1 << pi->uvd_boot_level; mask 1510 drivers/gpu/drm/amd/amdgpu/kv_dpm.c mask = 0x1f; mask 1523 drivers/gpu/drm/amd/amdgpu/kv_dpm.c mask); mask 72 drivers/gpu/drm/amd/amdgpu/kv_dpm.h u32 mask; mask 126 drivers/gpu/drm/amd/amdgpu/kv_smc.c u32 data, original_data, addr, extra_shift, t_byte, count, mask; mask 145 drivers/gpu/drm/amd/amdgpu/kv_smc.c mask = 0; mask 149 drivers/gpu/drm/amd/amdgpu/kv_smc.c mask = (mask << 8) | 0xff; mask 154 drivers/gpu/drm/amd/amdgpu/kv_smc.c mask <<= 8; mask 157 drivers/gpu/drm/amd/amdgpu/kv_smc.c mask = (mask << 8) | 0xff; mask 162 drivers/gpu/drm/amd/amdgpu/kv_smc.c data |= original_data & mask; mask 100 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask, uint32_t data) mask 103 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_rd_mod_wt->mask_value = mask; mask 112 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h uint32_t mask, uint32_t wait) mask 115 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h direct_poll->mask_value = mask; mask 120 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ mask 123 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h (mask), (data)); \ mask 136 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \ mask 139 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h (mask), (wait)); \ mask 321 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); mask 329 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c while (reg & mask) { mask 368 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); mask 373 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c if (!(reg & mask)) mask 390 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); mask 394 drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c while (!(reg & mask)) { mask 717 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t ref, uint32_t mask, mask 734 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c amdgpu_ring_write(ring, mask); /* mask */ mask 1639 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t val, uint32_t mask) mask 1641 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); mask 1182 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t val, uint32_t mask) mask 1190 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_write(ring, mask); /* mask */ mask 1197 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t ref, uint32_t mask) mask 1202 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); mask 1301 drivers/gpu/drm/amd/amdgpu/si.c u32 link_width_cntl, mask; mask 1308 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X0; mask 1311 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X1; mask 1314 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X2; mask 1317 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X4; mask 1320 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X8; mask 1323 drivers/gpu/drm/amd/amdgpu/si.c mask = LC_LINK_WIDTH_X16; mask 1332 drivers/gpu/drm/amd/amdgpu/si.c link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; mask 2858 drivers/gpu/drm/amd/amdgpu/si_dpm.c data &= ~config_regs->mask; mask 2859 drivers/gpu/drm/amd/amdgpu/si_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 855 drivers/gpu/drm/amd/amdgpu/si_dpm.h u32 mask; mask 50 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \ mask 56 drivers/gpu/drm/amd/amdgpu/soc15_common.h while ((tmp_ & (mask)) != (expected_value)) { \ mask 66 drivers/gpu/drm/amd/amdgpu/soc15_common.h inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ mask 1352 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t val, uint32_t mask) mask 1364 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, mask); mask 1374 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t data0, data1, mask; mask 1381 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c mask = 0xffffffff; mask 1382 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); mask 1405 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c uint32_t mask) mask 1409 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c amdgpu_ring_write(ring, mask); mask 578 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c u32 mask = 0; mask 580 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK; mask 581 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK; mask 583 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c return !(RREG32(mmSRBM_STATUS2) & mask); mask 670 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c u32 mask = 0; mask 672 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK; mask 673 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK; mask 675 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c return !(RREG32(mmSRBM_STATUS2) & mask); mask 981 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c uint32_t val, uint32_t mask) mask 985 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c amdgpu_ring_write(ring, mask); mask 1541 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) mask 1553 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, mask); mask 1563 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data0, data1, mask; mask 1570 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c mask = 0xffffffff; mask 1571 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); mask 1692 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) mask 1696 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, mask); mask 1936 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t mask) mask 1961 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c amdgpu_ring_write(ring, mask); mask 1968 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t data0, data1, mask; mask 1975 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c mask = 0xffffffff; mask 1976 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); mask 2031 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c uint32_t reg, reg_offset, val, mask, i; mask 2067 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c mask = 0x1; mask 2082 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->ring[ptr++] = mask; mask 1600 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) mask 1611 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, mask); mask 1622 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data0, data1, mask; mask 1629 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c mask = 0xffffffff; mask 1630 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); mask 1766 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) mask 1770 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, mask); mask 1988 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t val, uint32_t mask) mask 2011 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c amdgpu_ring_write(ring, mask); mask 2018 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c uint32_t data0, data1, mask; mask 2025 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c mask = 0xffffffff; mask 2026 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); mask 35 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); mask 47 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); mask 59 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h uint32_t val, uint32_t mask); mask 244 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c cntl->bitfields.mask = mask 248 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; mask 262 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask); mask 315 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c cntl.bitfields.mask); mask 412 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c cntl.bitfields.mask); mask 198 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h uint32_t mask:24; mask 276 drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h unsigned int mask; mask 860 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c uint32_t mask = get_support_mask_for_device_id(id); mask 862 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c return (le16_to_cpu(bp->object_info_tbl.v1_1->usDeviceSupport) & mask) != 0; mask 1815 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->mask = (uint32_t) (1 << mask 1817 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->mask_y = info->mask + 2; mask 1818 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->mask_en = info->mask + 1; mask 1819 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c info->mask_mask = info->mask - 1; mask 548 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->mask = (uint32_t) (1 << mask 550 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->mask_y = info->mask + 2; mask 551 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->mask_en = info->mask + 1; mask 552 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c info->mask_mask = info->mask - 1; mask 1001 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c uint32_t mask = get_support_mask_for_device_id(id); mask 1004 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c mask) != 0; mask 157 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mask = 1 << i; mask 159 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c if (mantissa & mask) mask 160 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c value |= mask; mask 166 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c uint32_t mask = 1 << j; mask 168 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c if (exponenta & mask) mask 169 drivers/gpu/drm/amd/display/dc/calcs/custom_float.c value |= mask << i; mask 1319 drivers/gpu/drm/amd/display/dc/core/dc.c if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) { mask 1326 drivers/gpu/drm/amd/display/dc/core/dc.c pin_info.mask); mask 122 drivers/gpu/drm/amd/display/dc/core/dc_link.c pin_info.mask); mask 37 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t mask; mask 48 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t mask, mask 51 drivers/gpu/drm/amd/display/dc/dc_helper.c ASSERT(mask != 0); mask 53 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift)); mask 54 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value_mask->mask = field_value_mask->mask | mask; mask 62 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t shift, mask, field_value; mask 71 drivers/gpu/drm/amd/display/dc/dc_helper.c mask = va_arg(ap, uint32_t); mask 75 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value, mask, shift); mask 98 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; mask 120 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; mask 144 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift, uint32_t mask, uint32_t *field_value) mask 147 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value = get_reg_field_value_ex(reg_val, mask, shift); mask 294 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value, mask 315 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value = get_reg_field_value_ex(reg_val, mask, shift); mask 362 drivers/gpu/drm/amd/display/dc/dc_helper.c uint32_t shift, mask, field_value; mask 373 drivers/gpu/drm/amd/display/dc/dc_helper.c mask = va_arg(ap, uint32_t); mask 376 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); mask 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h unsigned int mask); mask 54 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h void dcn10_clear_status_bits(struct dc *dc, unsigned int mask); mask 520 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c void dcn10_clear_status_bits(struct dc *dc, unsigned int mask) mask 531 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if (mask == 0x0) mask 532 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c mask = 0xFFFFFFFF; mask 534 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if (mask & DC_HW_STATE_MASK_HUBP_UNDERFLOW) mask 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if (mask & DC_HW_STATE_MASK_OTPC_UNDERFLOW) mask 541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c void dcn10_get_hw_state(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask) mask 562 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if (mask == 0x0) mask 563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c mask = 0xFFFF; // Default, capture all, invariant only mask 565 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_HUBBUB) && remaining_buf_size > 0) { mask 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_HUBP) && remaining_buf_size > 0) { mask 572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c chars_printed = dcn10_get_hubp_states(dc, pBuf, remaining_buf_size, mask & DC_HW_STATE_INVAR_ONLY); mask 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_RQ) && remaining_buf_size > 0) { mask 583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_DLG) && remaining_buf_size > 0) { mask 589 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_TTU) && remaining_buf_size > 0) { mask 595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_CM) && remaining_buf_size > 0) { mask 601 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_MPCC) && remaining_buf_size > 0) { mask 607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_OTG) && remaining_buf_size > 0) { mask 613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c if ((mask & DC_HW_STATE_MASK_CLOCKS) && remaining_buf_size > 0) { mask 105 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t mask, mask 108 drivers/gpu/drm/amd/display/dc/dm_services.h return (mask & reg_value) >> shift; mask 120 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t mask, mask 123 drivers/gpu/drm/amd/display/dc/dm_services.h ASSERT(mask != 0); mask 124 drivers/gpu/drm/amd/display/dc/dm_services.h return (reg_value & ~mask) | (mask & (value << shift)); mask 150 drivers/gpu/drm/amd/display/dc/dm_services.h uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value, mask 41 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c uint32_t mask, mask 49 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c switch (mask) { mask 79 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c switch (mask) { mask 106 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c switch (mask) { mask 121 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c switch (mask) { mask 190 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; mask 222 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; mask 257 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 260 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 263 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 266 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 269 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 272 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 275 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 286 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 289 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 292 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 295 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 298 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 301 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 312 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK; mask 316 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK; mask 329 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK; mask 333 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = mask 338 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK; mask 342 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK; mask 360 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask_y = info->mask; mask 361 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask_en = info->mask; mask 362 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_translate_dce110.c info->mask_mask = info->mask; mask 63 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c uint32_t mask, mask 71 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c switch (mask) { mask 101 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c switch (mask) { mask 128 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c switch (mask) { mask 143 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c switch (mask) { mask 212 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; mask 244 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; mask 279 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 282 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 285 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 288 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 291 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 294 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 297 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 308 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 311 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 314 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 317 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 320 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 323 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 334 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK; mask 338 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK; mask 351 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK; mask 355 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = mask 360 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK; mask 364 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK; mask 382 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask_y = info->mask; mask 383 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask_en = info->mask; mask 384 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c info->mask_mask = info->mask; mask 48 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t mask = 1; mask 51 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c if (vector == mask) mask 55 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c mask <<= 1; mask 56 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c } while (mask); mask 65 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c uint32_t mask, mask 73 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c switch (mask) { mask 103 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c switch (mask) { mask 130 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c switch (mask) { mask 145 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c switch (mask) { mask 166 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c *en = index_from_vector(mask); mask 219 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; mask 251 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; mask 286 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 289 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 292 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 295 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 298 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 301 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 304 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 315 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 318 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 321 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 324 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 327 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 330 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 341 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK; mask 345 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK; mask 358 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK; mask 362 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = mask 367 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK; mask 371 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK; mask 380 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask = (1 << en); mask 381 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c result = (info->mask <= GPIO_GPIO_PAD_MAX); mask 394 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask_y = info->mask; mask 395 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask_en = info->mask; mask 396 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_translate_dce80.c info->mask_mask = info->mask; mask 63 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c uint32_t mask, mask 71 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c switch (mask) { mask 101 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c switch (mask) { mask 128 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c switch (mask) { mask 143 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c switch (mask) { mask 212 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; mask 244 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; mask 279 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 282 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 285 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 288 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 291 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 294 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 297 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 308 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 311 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 314 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 317 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 320 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 323 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 334 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK; mask 338 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK; mask 351 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK; mask 355 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = mask 360 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK; mask 364 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask = DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK; mask 382 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask_y = info->mask; mask 383 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask_en = info->mask; mask 384 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c info->mask_mask = info->mask; mask 68 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c uint32_t mask, mask 76 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c switch (mask) { mask 106 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c switch (mask) { mask 133 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c switch (mask) { mask 199 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK; mask 229 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK; mask 262 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 265 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 268 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 271 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 274 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 277 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 280 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 291 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 294 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 297 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 300 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 303 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 306 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 353 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask_y = info->mask; mask 354 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask_en = info->mask; mask 355 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c info->mask_mask = info->mask; mask 67 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c uint32_t mask, mask 75 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c switch (mask) { mask 109 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c switch (mask) { mask 136 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c switch (mask) { mask 204 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK; mask 231 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK; mask 261 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; mask 264 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; mask 267 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; mask 270 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; mask 273 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; mask 276 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; mask 279 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; mask 290 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 293 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; mask 296 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; mask 299 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; mask 302 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; mask 305 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; mask 310 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; mask 356 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask_y = info->mask; mask 357 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask_en = info->mask; mask 358 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c info->mask_mask = info->mask; mask 131 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask) mask 136 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) { mask 147 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask) mask 153 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) { mask 189 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c pin.mask = 0xFFFFFFFF; mask 473 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c uint32_t mask, mask 480 drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) mask 45 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_GET(MASK_reg, MASK, &gpio->store.mask); mask 54 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c REG_UPDATE(MASK_reg, MASK, gpio->store.mask); mask 191 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c pin->store.mask = 0; mask 36 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t mask; mask 98 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h uint32_t mask; mask 32 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.h uint32_t mask, mask 86 drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h uint32_t mask, mask 263 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*get_hw_state)(struct dc *dc, char *pBuf, unsigned int bufSize, unsigned int mask); mask 264 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h void (*clear_status_bits)(struct dc *dc, unsigned int mask); mask 392 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift, uint32_t mask, uint32_t *field_value); mask 52 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask); mask 57 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask); mask 74 drivers/gpu/drm/amd/display/include/gpio_service_interface.h uint32_t mask, mask 82 drivers/gpu/drm/amd/display/include/gpio_types.h uint32_t mask; mask 246 drivers/gpu/drm/amd/include/kgd_pp_interface.h int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); mask 714 drivers/gpu/drm/amd/powerplay/amd_powerplay.c enum pp_clock_type type, uint32_t mask) mask 733 drivers/gpu/drm/amd/powerplay/amd_powerplay.c ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); mask 608 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask) mask 618 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c feature_id = smu_feature_get_index(smu, mask); mask 631 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask, mask 639 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c feature_id = smu_feature_get_index(smu, mask); mask 663 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask) mask 669 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c feature_id = smu_feature_get_index(smu, mask); mask 683 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c enum smu_feature_mask mask, mask 690 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c feature_id = smu_feature_get_index(smu, mask); mask 752 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c enum smu_clk_type type, uint32_t mask) mask 761 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 762 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 27 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value) mask 36 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c } while (value != (data & mask) && (timeout != 0)); mask 44 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask, mask 57 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c data = (data & (~mask)) | (value << shift); mask 61 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c ret = baco_wait_register(hwmgr, reg, mask, value); mask 95 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask, mask 42 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h uint32_t mask; mask 1298 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint16_t end_index, uint32_t mask, uint32_t *efuse) mask 1313 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c *efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask; mask 312 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint16_t end_index, uint32_t mask, uint32_t *efuse); mask 831 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 838 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c low = mask ? (ffs(mask) - 1) : 0; mask 839 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c high = mask ? (fls(mask) - 1) : 0; mask 110 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c enum pp_clock_type type, uint32_t mask); mask 4400 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 4404 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (mask == 0) mask 4412 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); mask 4418 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); mask 4422 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; mask 48 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h uint32_t mask; mask 906 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 926 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data &= ~config_regs->mask; mask 927 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 1494 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 1500 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c mask); mask 1503 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c mask); mask 91 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c u32 mask = 0; mask 96 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c mask = 0xFF << shift; mask 98 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c mask = 0xFFFF << shift; mask 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c original_data &= ~mask; mask 110 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t mask) mask 122 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c if ((cur_value & mask) == (value & mask)) mask 143 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t mask) mask 151 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value); mask 156 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t value, uint32_t mask) mask 167 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c if ((cur_value & mask) != (value & mask)) mask 182 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t mask) mask 189 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c value, mask); mask 374 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int32_t mask = 0; mask 378 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c mask = mask << 1; mask 380 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c mask |= 0x1; mask 382 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c mask &= 0xFFFFFFFE; mask 385 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c return mask; mask 523 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask) mask 527 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c while (0 == (mask & (1 << level))) mask 64 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); mask 68 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); mask 91 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); mask 100 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t value, uint32_t mask); mask 106 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t mask); mask 163 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \ mask 164 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask) mask 167 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ mask 168 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) mask 174 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \ mask 176 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h mm##port##_INDEX, index, value, mask) mask 178 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ mask 179 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) mask 188 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h port, index, value, mask) \ mask 190 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h mm##port##_INDEX_11, index, value, mask) mask 192 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \ mask 193 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) mask 202 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h port, index, value, mask) \ mask 204 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h mm##port##_INDEX_11, index, value, mask) mask 206 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \ mask 207 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask) mask 215 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h index, value, mask) \ mask 217 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h index, value, mask) mask 219 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \ mask 221 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h mm##reg, value, mask) mask 957 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t mask = 0; mask 968 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c mask |= (uint32_t)(i << (8 * j)); mask 976 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c pp_table->LedPin0 = (uint8_t)(mask & 0xff); mask 977 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); mask 978 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); mask 4079 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 4085 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; mask 4086 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; mask 4098 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; mask 4099 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; mask 4112 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; mask 4113 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; mask 809 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; mask 810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 815 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; mask 816 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 821 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; mask 822 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 841 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data &= ~config_regs->mask; mask 842 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 47 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t mask; mask 55 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h uint32_t mask; mask 52 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c enum pp_clock_type type, uint32_t mask); mask 1881 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 1889 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 1890 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 1909 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 1910 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 1930 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 1931 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 1958 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c hard_min_level = mask ? (ffs(mask) - 1) : 0; mask 2507 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c enum pp_clock_type type, uint32_t mask) mask 2515 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 2516 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 2542 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 2543 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 2570 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 2571 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 2598 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 2599 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 2626 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c hard_min_level = mask ? (ffs(mask) - 1) : 0; mask 2648 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 2649 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 409 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); mask 614 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_feature_get_enabled_mask(smu, mask, num) \ mask 615 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0) mask 783 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_feature_mask mask); mask 785 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_feature_mask mask, bool enable); mask 787 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_feature_mask mask); mask 789 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h enum smu_feature_mask mask, bool enable); mask 314 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); mask 748 drivers/gpu/drm/amd/powerplay/navi10_ppt.c enum smu_clk_type clk_type, uint32_t mask) mask 754 drivers/gpu/drm/amd/powerplay/navi10_ppt.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 755 drivers/gpu/drm/amd/powerplay/navi10_ppt.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 322 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1; mask 328 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mask, &efuse)) { mask 1898 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c u32 mask = 0; mask 1909 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mask |= (i << (8 * j)); mask 1916 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c if (mask) mask 1919 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c mask); mask 1501 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1; mask 1506 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c mask, &efuse); mask 1272 drivers/gpu/drm/amd/powerplay/vega20_ppt.c enum smu_clk_type clk_type, uint32_t mask) mask 1287 drivers/gpu/drm/amd/powerplay/vega20_ppt.c soft_min_level = mask ? (ffs(mask) - 1) : 0; mask 1288 drivers/gpu/drm/amd/powerplay/vega20_ppt.c soft_max_level = mask ? (fls(mask) - 1) : 0; mask 13 drivers/gpu/drm/arm/display/include/malidp_utils.h #define has_bit(nr, mask) (BIT(nr) & (mask)) mask 14 drivers/gpu/drm/arm/display/include/malidp_utils.h #define has_bits(bits, mask) (((bits) & (mask)) == (bits)) mask 16 drivers/gpu/drm/arm/display/include/malidp_utils.h #define dp_for_each_set_bit(bit, mask) \ mask 17 drivers/gpu/drm/arm/display/include/malidp_utils.h for_each_set_bit((bit), ((unsigned long *)&(mask)), sizeof(mask) * 8) mask 384 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c u32 ctrl = L_EN | LW_OFM, mask = L_EN | LW_OFM | LW_TBU_EN; mask 394 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c malidp_write32_mask(reg, BLK_CONTROL, mask, ctrl); mask 51 drivers/gpu/drm/arm/hdlcd_crtc.c unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); mask 53 drivers/gpu/drm/arm/hdlcd_crtc.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); mask 61 drivers/gpu/drm/arm/hdlcd_crtc.c unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); mask 63 drivers/gpu/drm/arm/hdlcd_crtc.c hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); mask 801 drivers/gpu/drm/arm/malidp_hw.c u32 mask = MALIDP550_SE_CTL_VCSEL(MALIDP550_SE_CTL_SEL_MASK) | mask 806 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, mask, MALIDP550_SE_CONTROL); mask 1166 drivers/gpu/drm/arm/malidp_hw.c u32 status, mask, dc_status; mask 1200 drivers/gpu/drm/arm/malidp_hw.c mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ); mask 1202 drivers/gpu/drm/arm/malidp_hw.c status &= (mask | de->err_mask); mask 1284 drivers/gpu/drm/arm/malidp_hw.c u32 status, mask; mask 1303 drivers/gpu/drm/arm/malidp_hw.c mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ); mask 1304 drivers/gpu/drm/arm/malidp_hw.c status &= mask; mask 270 drivers/gpu/drm/arm/malidp_hw.h u32 mask, u32 reg) mask 274 drivers/gpu/drm/arm/malidp_hw.h data |= mask; mask 279 drivers/gpu/drm/arm/malidp_hw.h u32 mask, u32 reg) mask 283 drivers/gpu/drm/arm/malidp_hw.h data &= ~mask; mask 88 drivers/gpu/drm/armada/armada_crtc.c val = regs->mask; mask 228 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) mask 230 drivers/gpu/drm/armada/armada_crtc.c if (dcrtc->irq_ena & mask) { mask 231 drivers/gpu/drm/armada/armada_crtc.c dcrtc->irq_ena &= ~mask; mask 236 drivers/gpu/drm/armada/armada_crtc.c static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) mask 238 drivers/gpu/drm/armada/armada_crtc.c if ((dcrtc->irq_ena & mask) != mask) { mask 239 drivers/gpu/drm/armada/armada_crtc.c dcrtc->irq_ena |= mask; mask 241 drivers/gpu/drm/armada/armada_crtc.c if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) mask 14 drivers/gpu/drm/armada/armada_crtc.h uint32_t mask; mask 22 drivers/gpu/drm/armada/armada_crtc.h __reg[_i].mask = ~(_m); \ mask 55 drivers/gpu/drm/armada/armada_debugfs.c unsigned long reg, mask, val; mask 71 drivers/gpu/drm/armada/armada_debugfs.c if (sscanf(buf, "%lx %lx %lx", ®, &mask, &val) != 3) mask 78 drivers/gpu/drm/armada/armada_debugfs.c v &= ~mask; mask 79 drivers/gpu/drm/armada/armada_debugfs.c v |= val & mask; mask 22 drivers/gpu/drm/armada/armada_drm.h armada_updatel(uint32_t val, uint32_t mask, void __iomem *ptr) mask 27 drivers/gpu/drm/armada/armada_drm.h v = (v & ~mask) | val; mask 183 drivers/gpu/drm/ast/ast_drv.h uint8_t mask, uint8_t val); mask 187 drivers/gpu/drm/ast/ast_drv.h uint32_t base, uint8_t index, uint8_t mask); mask 42 drivers/gpu/drm/ast/ast_main.c uint8_t mask, uint8_t val) mask 46 drivers/gpu/drm/ast/ast_main.c tmp = (ast_io_read8(ast, base + 1) & mask) | val; mask 60 drivers/gpu/drm/ast/ast_main.c uint32_t base, uint8_t index, uint8_t mask) mask 64 drivers/gpu/drm/ast/ast_main.c ret = ast_io_read8(ast, base + 1) & mask; mask 620 drivers/gpu/drm/ast/ast_post.c u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0; mask 633 drivers/gpu/drm/ast/ast_post.c mask = 0x00010001; mask 635 drivers/gpu/drm/ast/ast_post.c if (data & mask) { mask 643 drivers/gpu/drm/ast/ast_post.c mask <<= 1; mask 74 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL; mask 107 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c mask |= ATMEL_HLCDC_CLKSEL; mask 136 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg); mask 92 drivers/gpu/drm/bridge/analogix-anx78xx.c static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask) mask 94 drivers/gpu/drm/bridge/analogix-anx78xx.c return regmap_update_bits(map, reg, mask, mask); mask 97 drivers/gpu/drm/bridge/analogix-anx78xx.c static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask) mask 99 drivers/gpu/drm/bridge/analogix-anx78xx.c return regmap_update_bits(map, reg, mask, 0); mask 234 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 mask = DP_PLL_PD; mask 239 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = RK_PLL_PD; mask 244 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 246 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 256 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c u32 mask; mask 264 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = RK_AUX_PD; mask 266 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = AUX_PD; mask 270 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 272 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 276 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = CH0_PD; mask 280 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 282 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 286 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = CH1_PD; mask 290 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 292 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 296 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = CH2_PD; mask 300 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 302 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 306 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = CH3_PD; mask 310 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 312 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 322 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = DP_INC_BG; mask 324 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c mask = DP_PHY_PD; mask 328 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg |= mask; mask 330 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c reg &= ~mask; mask 208 drivers/gpu/drm/bridge/sii902x.c static int sii902x_update_bits_unlocked(struct i2c_client *i2c, u8 reg, u8 mask, mask 217 drivers/gpu/drm/bridge/sii902x.c status &= ~mask; mask 218 drivers/gpu/drm/bridge/sii902x.c status |= val & mask; mask 212 drivers/gpu/drm/bridge/sii9234.c int value, int mask) mask 236 drivers/gpu/drm/bridge/sii9234.c value = (value & mask) | (ret & ~mask); mask 285 drivers/gpu/drm/bridge/sii9234.c #define mhl_tx_writebm(sii9234, offset, value, mask) \ mask 286 drivers/gpu/drm/bridge/sii9234.c sii9234_writebm(sii9234, I2C_MHL, offset, value, mask) mask 291 drivers/gpu/drm/bridge/sii9234.c #define cbus_writebm(sii9234, offset, value, mask) \ mask 292 drivers/gpu/drm/bridge/sii9234.c sii9234_writebm(sii9234, I2C_CBUS, offset, value, mask) mask 297 drivers/gpu/drm/bridge/sii9234.c #define hdmi_writebm(sii9234, offset, value, mask) \ mask 298 drivers/gpu/drm/bridge/sii9234.c sii9234_writebm(sii9234, I2C_HDMI, offset, value, mask) mask 303 drivers/gpu/drm/bridge/sii9234.c #define tpi_writebm(sii9234, offset, value, mask) \ mask 304 drivers/gpu/drm/bridge/sii9234.c sii9234_writebm(sii9234, I2C_TPI, offset, value, mask) mask 255 drivers/gpu/drm/bridge/sil-sii8620.c static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) mask 257 drivers/gpu/drm/bridge/sil-sii8620.c val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); mask 429 drivers/gpu/drm/bridge/sil-sii8620.c static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) mask 431 drivers/gpu/drm/bridge/sil-sii8620.c sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); mask 219 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) mask 221 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); mask 225 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c u8 shift, u8 mask) mask 227 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_modb(hdmi, data << shift, mask, reg); mask 375 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c u32 val, mask; mask 387 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; mask 389 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c val, (val & mask) == mask, mask 347 drivers/gpu/drm/drm_client_modeset.c const u64 mask = BIT_ULL(connector_count) - 1; mask 407 drivers/gpu/drm/drm_client_modeset.c if ((conn_configured & mask) != mask) { mask 512 drivers/gpu/drm/drm_client_modeset.c unsigned long conn_configured, conn_seq, mask; mask 534 drivers/gpu/drm/drm_client_modeset.c mask = GENMASK(count - 1, 0); mask 648 drivers/gpu/drm/drm_client_modeset.c if ((conn_configured & mask) != mask && conn_configured != conn_seq) mask 103 drivers/gpu/drm/drm_dp_cec.c u8 mask[2]; mask 108 drivers/gpu/drm/drm_dp_cec.c mask[0] = la_mask & 0xff; mask 109 drivers/gpu/drm/drm_dp_cec.c mask[1] = la_mask >> 8; mask 110 drivers/gpu/drm/drm_dp_cec.c err = drm_dp_dpcd_write(aux, DP_CEC_LOGICAL_ADDRESS_MASK, mask, 2); mask 3540 drivers/gpu/drm/drm_edid.c u16 mask; mask 3603 drivers/gpu/drm/drm_edid.c mask = (db[10 + offset] << 8) | db[11 + offset]; mask 3605 drivers/gpu/drm/drm_edid.c mask = 0xffff; mask 3608 drivers/gpu/drm/drm_edid.c if (mask & (1 << i)) mask 942 drivers/gpu/drm/drm_fb_helper.c u32 mask = (1 << info->var.transp.length) - 1; mask 944 drivers/gpu/drm/drm_fb_helper.c mask <<= info->var.transp.offset; mask 945 drivers/gpu/drm/drm_fb_helper.c value |= mask; mask 572 drivers/gpu/drm/drm_file.c __poll_t mask = 0; mask 577 drivers/gpu/drm/drm_file.c mask |= EPOLLIN | EPOLLRDNORM; mask 579 drivers/gpu/drm/drm_file.c return mask; mask 149 drivers/gpu/drm/drm_hashtab.c unsigned long mask = (1UL << bits) - 1; mask 158 drivers/gpu/drm/drm_hashtab.c unshifted_key = (unshifted_key + 1) & mask; mask 1801 drivers/gpu/drm/etnaviv/etnaviv_gpu.c u32 idle, mask; mask 1808 drivers/gpu/drm/etnaviv/etnaviv_gpu.c mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE; mask 1809 drivers/gpu/drm/etnaviv/etnaviv_gpu.c idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; mask 1810 drivers/gpu/drm/etnaviv/etnaviv_gpu.c if (idle != mask) mask 95 drivers/gpu/drm/exynos/exynos5433_drm_decon.c static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, mask 98 drivers/gpu/drm/exynos/exynos5433_drm_decon.c val = (val & mask) | (readl(ctx->addr + reg) & ~mask); mask 266 drivers/gpu/drm/exynos/exynos5433_drm_decon.c u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf); mask 286 drivers/gpu/drm/exynos/exynos5433_drm_decon.c decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); mask 1266 drivers/gpu/drm/exynos/exynos_drm_dsi.c u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | mask 1269 drivers/gpu/drm/exynos/exynos_drm_dsi.c exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); mask 237 drivers/gpu/drm/exynos/exynos_drm_fimd.c static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, mask 240 drivers/gpu/drm/exynos/exynos_drm_fimd.c val = (val & mask) | (readl(ctx->regs + reg) & ~mask); mask 573 drivers/gpu/drm/exynos/exynos_drm_fimd.c u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); mask 593 drivers/gpu/drm/exynos/exynos_drm_fimd.c fimd_set_bits(ctx, BLENDEQx(win), mask, val); mask 612 drivers/gpu/drm/exynos/exynos_drm_gsc.c u32 mask = 0x00000001 << buf_id; mask 618 drivers/gpu/drm/exynos/exynos_drm_gsc.c cfg &= ~mask; mask 911 drivers/gpu/drm/exynos/exynos_drm_gsc.c u32 mask = 0x00000001; mask 916 drivers/gpu/drm/exynos/exynos_drm_gsc.c if (cfg & (mask << i)) mask 929 drivers/gpu/drm/exynos/exynos_drm_gsc.c u32 mask = 0x00000001 << buf_id; mask 935 drivers/gpu/drm/exynos/exynos_drm_gsc.c cfg &= ~mask; mask 704 drivers/gpu/drm/exynos/exynos_hdmi.c u32 reg_id, u32 value, u32 mask) mask 710 drivers/gpu/drm/exynos/exynos_hdmi.c value = (value & mask) | (old & ~mask); mask 194 drivers/gpu/drm/exynos/exynos_mixer.c u32 val, u32 mask) mask 198 drivers/gpu/drm/exynos/exynos_mixer.c val = (val & mask) | (old & ~mask); mask 214 drivers/gpu/drm/exynos/exynos_mixer.c u32 reg_id, u32 val, u32 mask) mask 218 drivers/gpu/drm/exynos/exynos_mixer.c val = (val & mask) | (old & ~mask); mask 63 drivers/gpu/drm/exynos/regs-rotator.h #define ROT_ALIGN(x, align, mask) (((x) + (1 << ((align) - 1))) & (mask)) mask 65 drivers/gpu/drm/exynos/regs-rotator.h #define ROT_MIN(min, mask) (((min) + ~(mask)) & (mask)) mask 67 drivers/gpu/drm/exynos/regs-rotator.h #define ROT_MAX(max, mask) ((max) & (mask)) mask 31 drivers/gpu/drm/gma500/gtt.c uint32_t mask = PSB_PTE_VALID; mask 38 drivers/gpu/drm/gma500/gtt.c mask |= PSB_PTE_CACHED; mask 40 drivers/gpu/drm/gma500/gtt.c mask |= PSB_PTE_RO; mask 42 drivers/gpu/drm/gma500/gtt.c mask |= PSB_PTE_WO; mask 44 drivers/gpu/drm/gma500/gtt.c return (pfn << PAGE_SHIFT) | mask; mask 83 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c u32 mask) mask 90 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if ((mask & REG_READ(gen_fifo_stat_reg)) == mask) mask 114 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c static int handle_dsi_error(struct mdfld_dsi_pkg_sender *sender, u32 mask) mask 119 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c dev_dbg(sender->dev->dev, "Handling error 0x%08x\n", mask); mask 121 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c switch (mask) { mask 173 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(intr_stat_reg, mask); mask 178 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c REG_WRITE(intr_stat_reg, mask); mask 188 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if (mask & REG_READ(intr_stat_reg)) mask 190 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c "Cannot clean interrupt 0x%08x\n", mask); mask 198 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c u32 mask; mask 206 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c mask = (0x00000001UL) << i; mask 207 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c if (intr_stat & mask) { mask 209 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c err = handle_dsi_error(sender, mask); mask 153 drivers/gpu/drm/gma500/mmu.c uint32_t mask = PSB_PTE_VALID; mask 156 drivers/gpu/drm/gma500/mmu.c mask |= PSB_PTE_CACHED; mask 158 drivers/gpu/drm/gma500/mmu.c mask |= PSB_PTE_RO; mask 160 drivers/gpu/drm/gma500/mmu.c mask |= PSB_PTE_WO; mask 162 drivers/gpu/drm/gma500/mmu.c return (pfn << PAGE_SHIFT) | mask; mask 685 drivers/gpu/drm/gma500/psb_drv.h psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); mask 688 drivers/gpu/drm/gma500/psb_drv.h psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); mask 1885 drivers/gpu/drm/gma500/psb_intel_sdvo.c uint16_t mask = 0; mask 1893 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_LVDS1; mask 1895 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_LVDS0; mask 1897 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_TMDS1; mask 1899 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_TMDS0; mask 1901 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_RGB1; mask 1903 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask |= SDVO_OUTPUT_RGB0; mask 1908 drivers/gpu/drm/gma500/psb_intel_sdvo.c mask &= sdvo->caps.output_flags; mask 1909 drivers/gpu/drm/gma500/psb_intel_sdvo.c num_bits = hweight16(mask); mask 73 drivers/gpu/drm/gma500/psb_irq.c psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) mask 75 drivers/gpu/drm/gma500/psb_irq.c if ((dev_priv->pipestat[pipe] & mask) != mask) { mask 77 drivers/gpu/drm/gma500/psb_irq.c dev_priv->pipestat[pipe] |= mask; mask 81 drivers/gpu/drm/gma500/psb_irq.c writeVal |= (mask | (mask >> 16)); mask 90 drivers/gpu/drm/gma500/psb_irq.c psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) mask 92 drivers/gpu/drm/gma500/psb_irq.c if ((dev_priv->pipestat[pipe] & mask) != 0) { mask 94 drivers/gpu/drm/gma500/psb_irq.c dev_priv->pipestat[pipe] &= ~mask; mask 97 drivers/gpu/drm/gma500/psb_irq.c writeVal &= ~mask; mask 89 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h u32 mask, u32 val) mask 94 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h tmp = orig & ~(mask << bit_start); mask 95 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h tmp |= (val & mask) << bit_start; mask 216 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h u32 mask, u32 val) mask 221 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h tmp = orig & ~(mask << bit_start); mask 222 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h tmp |= (val & mask) << bit_start; mask 151 drivers/gpu/drm/i2c/ch7006_priv.h state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \ mask 94 drivers/gpu/drm/i915/display/intel_combo_phy.c enum phy phy, i915_reg_t reg, u32 mask, mask 99 drivers/gpu/drm/i915/display/intel_combo_phy.c if ((val & mask) != expected_val) { mask 103 drivers/gpu/drm/i915/display/intel_combo_phy.c reg.reg, val, mask, expected_val); mask 6410 drivers/gpu/drm/i915/display/intel_display.c u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; mask 6413 drivers/gpu/drm/i915/display/intel_display.c val |= mask; mask 6415 drivers/gpu/drm/i915/display/intel_display.c val &= ~mask; mask 6794 drivers/gpu/drm/i915/display/intel_display.c u64 mask; mask 6800 drivers/gpu/drm/i915/display/intel_display.c mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe)); mask 6801 drivers/gpu/drm/i915/display/intel_display.c mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder)); mask 6804 drivers/gpu/drm/i915/display/intel_display.c mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); mask 6810 drivers/gpu/drm/i915/display/intel_display.c mask |= BIT_ULL(intel_encoder->power_domain); mask 6814 drivers/gpu/drm/i915/display/intel_display.c mask |= BIT_ULL(POWER_DOMAIN_AUDIO); mask 6817 drivers/gpu/drm/i915/display/intel_display.c mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE); mask 6819 drivers/gpu/drm/i915/display/intel_display.c return mask; mask 12664 drivers/gpu/drm/i915/display/intel_display.c #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ mask 12665 drivers/gpu/drm/i915/display/intel_display.c if ((current_config->name ^ pipe_config->name) & (mask)) { \ mask 12668 drivers/gpu/drm/i915/display/intel_display.c (mask), \ mask 12669 drivers/gpu/drm/i915/display/intel_display.c current_config->name & (mask), \ mask 12670 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name & (mask)); \ mask 619 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | mask 635 drivers/gpu/drm/i915/display/intel_display_power.c return (val & mask) == mask; mask 714 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask; mask 716 drivers/gpu/drm/i915/display/intel_display_power.c mask = DC_STATE_EN_UPTO_DC5; mask 718 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; mask 720 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_DC9; mask 722 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_UPTO_DC6; mask 724 drivers/gpu/drm/i915/display/intel_display_power.c return mask; mask 764 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask; mask 770 drivers/gpu/drm/i915/display/intel_display_power.c mask = gen9_dc_mask(dev_priv); mask 772 drivers/gpu/drm/i915/display/intel_display_power.c val & mask, state); mask 775 drivers/gpu/drm/i915/display/intel_display_power.c if ((val & mask) != dev_priv->csr.dc_state) mask 777 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state, val & mask); mask 779 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~mask; mask 784 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->csr.dc_state = val & mask; mask 899 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); mask 903 drivers/gpu/drm/i915/display/intel_display_power.c if (bios_req & mask) { mask 906 drivers/gpu/drm/i915/display/intel_display_power.c if (!(drv_req & mask)) mask 907 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, drv_req | mask); mask 908 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->bios, bios_req & ~mask); mask 1060 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask; mask 1064 drivers/gpu/drm/i915/display/intel_display_power.c mask = PUNIT_PWRGT_MASK(pw_idx); mask 1071 drivers/gpu/drm/i915/display/intel_display_power.c ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) mask 1077 drivers/gpu/drm/i915/display/intel_display_power.c ctrl &= ~mask; mask 1109 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask; mask 1113 drivers/gpu/drm/i915/display/intel_display_power.c mask = PUNIT_PWRGT_MASK(pw_idx); mask 1118 drivers/gpu/drm/i915/display/intel_display_power.c state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; mask 1132 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; mask 1486 drivers/gpu/drm/i915/display/intel_display_power.c enum dpio_channel ch, bool override, unsigned int mask) mask 1515 drivers/gpu/drm/i915/display/intel_display_power.c if (!override || mask == 0xf) { mask 1528 drivers/gpu/drm/i915/display/intel_display_power.c } else if (mask != 0x0) { mask 1579 drivers/gpu/drm/i915/display/intel_display_power.c bool override, unsigned int mask) mask 1589 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); mask 1599 drivers/gpu/drm/i915/display/intel_display_power.c phy, ch, mask, dev_priv->chv_phy_control); mask 1603 drivers/gpu/drm/i915/display/intel_display_power.c assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); mask 1719 drivers/gpu/drm/i915/display/intel_display_power.c const char *prefix, u64 mask) mask 1726 drivers/gpu/drm/i915/display/intel_display_power.c DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask)); mask 1727 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_domain(domain, mask) mask 1958 drivers/gpu/drm/i915/display/intel_display_power.c release_async_put_domains(struct i915_power_domains *power_domains, u64 mask) mask 1975 drivers/gpu/drm/i915/display/intel_display_power.c for_each_power_domain(domain, mask) { mask 3930 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask; mask 3941 drivers/gpu/drm/i915/display/intel_display_power.c mask = DC_STATE_EN_DC9; mask 3944 drivers/gpu/drm/i915/display/intel_display_power.c mask = 0; mask 3947 drivers/gpu/drm/i915/display/intel_display_power.c mask = DC_STATE_EN_DC9; mask 3950 drivers/gpu/drm/i915/display/intel_display_power.c mask = 0; mask 3970 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_UPTO_DC6; mask 3972 drivers/gpu/drm/i915/display/intel_display_power.c mask |= DC_STATE_EN_UPTO_DC5; mask 3974 drivers/gpu/drm/i915/display/intel_display_power.c DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); mask 3976 drivers/gpu/drm/i915/display/intel_display_power.c return mask; mask 4208 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask, val; mask 4210 drivers/gpu/drm/i915/display/intel_display_power.c mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | mask 4216 drivers/gpu/drm/i915/display/intel_display_power.c val &= ~mask; mask 4766 drivers/gpu/drm/i915/display/intel_display_power.c unsigned int mask; mask 4768 drivers/gpu/drm/i915/display/intel_display_power.c mask = status & DPLL_PORTB_READY_MASK; mask 4769 drivers/gpu/drm/i915/display/intel_display_power.c if (mask == 0xf) mask 4770 drivers/gpu/drm/i915/display/intel_display_power.c mask = 0x0; mask 4776 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); mask 4778 drivers/gpu/drm/i915/display/intel_display_power.c mask = (status & DPLL_PORTC_READY_MASK) >> 4; mask 4779 drivers/gpu/drm/i915/display/intel_display_power.c if (mask == 0xf) mask 4780 drivers/gpu/drm/i915/display/intel_display_power.c mask = 0x0; mask 4786 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); mask 4797 drivers/gpu/drm/i915/display/intel_display_power.c unsigned int mask; mask 4799 drivers/gpu/drm/i915/display/intel_display_power.c mask = status & DPLL_PORTD_READY_MASK; mask 4801 drivers/gpu/drm/i915/display/intel_display_power.c if (mask == 0xf) mask 4802 drivers/gpu/drm/i915/display/intel_display_power.c mask = 0x0; mask 4808 drivers/gpu/drm/i915/display/intel_display_power.c PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); mask 232 drivers/gpu/drm/i915/display/intel_display_power.h #define for_each_power_domain(domain, mask) \ mask 234 drivers/gpu/drm/i915/display/intel_display_power.h for_each_if(BIT_ULL(domain) & (mask)) mask 327 drivers/gpu/drm/i915/display/intel_display_power.h bool override, unsigned int mask); mask 2451 drivers/gpu/drm/i915/display/intel_dp.c u32 mask, mask 2465 drivers/gpu/drm/i915/display/intel_dp.c mask, value, mask 2470 drivers/gpu/drm/i915/display/intel_dp.c mask, value, 5000)) mask 3980 drivers/gpu/drm/i915/display/intel_dp.c u32 signal_levels, mask = 0; mask 3987 drivers/gpu/drm/i915/display/intel_dp.c mask = DDI_BUF_EMP_MASK; mask 3994 drivers/gpu/drm/i915/display/intel_dp.c mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; mask 3997 drivers/gpu/drm/i915/display/intel_dp.c mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; mask 4000 drivers/gpu/drm/i915/display/intel_dp.c mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; mask 4003 drivers/gpu/drm/i915/display/intel_dp.c if (mask) mask 4012 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; mask 492 drivers/gpu/drm/i915/display/intel_dpio_phy.c i915_reg_t reg, u32 mask, u32 expected, mask 500 drivers/gpu/drm/i915/display/intel_dpio_phy.c if ((val & mask) == expected) mask 509 drivers/gpu/drm/i915/display/intel_dpio_phy.c phy, &vaf, reg.reg, val, (val & ~mask) | expected, mask 510 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask); mask 521 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 mask; mask 526 drivers/gpu/drm/i915/display/intel_dpio_phy.c #define _CHK(reg, mask, exp, fmt, ...) \ mask 527 drivers/gpu/drm/i915/display/intel_dpio_phy.c __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ mask 544 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; mask 545 drivers/gpu/drm/i915/display/intel_dpio_phy.c ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, mask 559 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | mask 561 drivers/gpu/drm/i915/display/intel_dpio_phy.c ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, mask 564 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask = GRC_DIS | GRC_RDY_OVRD; mask 565 drivers/gpu/drm/i915/display/intel_dpio_phy.c ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, mask 624 drivers/gpu/drm/i915/display/intel_dpio_phy.c u8 mask; mask 628 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask = 0; mask 633 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask |= BIT(lane); mask 636 drivers/gpu/drm/i915/display/intel_dpio_phy.c return mask; mask 395 drivers/gpu/drm/i915/display/intel_dsi_vbt.c u32 value, mask, reg_address; mask 403 drivers/gpu/drm/i915/display/intel_dsi_vbt.c mask = get_unaligned_le32(data + 11); mask 407 drivers/gpu/drm/i915/display/intel_dsi_vbt.c value, mask); mask 559 drivers/gpu/drm/i915/display/intel_hdmi.c u32 mask; mask 561 drivers/gpu/drm/i915/display/intel_hdmi.c mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | mask 566 drivers/gpu/drm/i915/display/intel_hdmi.c mask |= VIDEO_DIP_ENABLE_DRM_GLK; mask 568 drivers/gpu/drm/i915/display/intel_hdmi.c return val & mask; mask 627 drivers/gpu/drm/i915/display/intel_panel.c u32 tmp, mask; mask 640 drivers/gpu/drm/i915/display/intel_panel.c mask = BACKLIGHT_DUTY_CYCLE_MASK; mask 643 drivers/gpu/drm/i915/display/intel_panel.c mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; mask 646 drivers/gpu/drm/i915/display/intel_panel.c tmp = I915_READ(BLC_PWM_CTL) & ~mask; mask 110 drivers/gpu/drm/i915/display/intel_psr.c u32 debug_mask, mask; mask 120 drivers/gpu/drm/i915/display/intel_psr.c mask = 0; mask 124 drivers/gpu/drm/i915/display/intel_psr.c mask |= EDP_PSR_ERROR(shift); mask 130 drivers/gpu/drm/i915/display/intel_psr.c mask |= debug_mask; mask 132 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR_IMR, ~mask); mask 177 drivers/gpu/drm/i915/display/intel_psr.c u32 mask = 0; mask 201 drivers/gpu/drm/i915/display/intel_psr.c mask |= EDP_PSR_ERROR(shift); mask 225 drivers/gpu/drm/i915/display/intel_psr.c if (mask) { mask 226 drivers/gpu/drm/i915/display/intel_psr.c mask |= I915_READ(EDP_PSR_IMR); mask 227 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR_IMR, mask); mask 690 drivers/gpu/drm/i915/display/intel_psr.c u32 mask; mask 715 drivers/gpu/drm/i915/display/intel_psr.c mask = EDP_PSR_DEBUG_MASK_MEMUP | mask 721 drivers/gpu/drm/i915/display/intel_psr.c mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; mask 723 drivers/gpu/drm/i915/display/intel_psr.c I915_WRITE(EDP_PSR_DEBUG, mask); mask 975 drivers/gpu/drm/i915/display/intel_psr.c u32 mask; mask 983 drivers/gpu/drm/i915/display/intel_psr.c mask = EDP_PSR2_STATUS_STATE_MASK; mask 986 drivers/gpu/drm/i915/display/intel_psr.c mask = EDP_PSR_STATUS_STATE_MASK; mask 991 drivers/gpu/drm/i915/display/intel_psr.c err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); mask 1679 drivers/gpu/drm/i915/display/intel_sdvo.c u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT; mask 1681 drivers/gpu/drm/i915/display/intel_sdvo.c if ((val & mask) == mask) mask 2475 drivers/gpu/drm/i915/display/intel_sdvo.c u16 mask = 0; mask 2484 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_LVDS1; mask 2487 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_LVDS0; mask 2490 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_TMDS1; mask 2493 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_TMDS0; mask 2496 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_RGB1; mask 2499 drivers/gpu/drm/i915/display/intel_sdvo.c mask |= SDVO_OUTPUT_RGB0; mask 2504 drivers/gpu/drm/i915/display/intel_sdvo.c mask &= sdvo->caps.output_flags; mask 2505 drivers/gpu/drm/i915/display/intel_sdvo.c num_bits = hweight16(mask); mask 155 drivers/gpu/drm/i915/display/intel_tc.c u32 mask = 0; mask 164 drivers/gpu/drm/i915/display/intel_tc.c return mask; mask 168 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_TBT_ALT); mask 170 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_DP_ALT); mask 173 drivers/gpu/drm/i915/display/intel_tc.c mask |= BIT(TC_PORT_LEGACY); mask 176 drivers/gpu/drm/i915/display/intel_tc.c if (!WARN_ON(hweight32(mask) > 1)) mask 177 drivers/gpu/drm/i915/display/intel_tc.c tc_port_fixup_legacy_flag(dig_port, mask); mask 179 drivers/gpu/drm/i915/display/intel_tc.c return mask; mask 82 drivers/gpu/drm/i915/display/vlv_dsi.c u32 mask; mask 84 drivers/gpu/drm/i915/display/vlv_dsi.c mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | mask 88 drivers/gpu/drm/i915/display/vlv_dsi.c mask, 100)) mask 218 drivers/gpu/drm/i915/display/vlv_dsi.c u32 mask; mask 235 drivers/gpu/drm/i915/display/vlv_dsi.c mask = SPL_PKT_SENT_INTERRUPT; mask 236 drivers/gpu/drm/i915/display/vlv_dsi.c if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) mask 201 drivers/gpu/drm/i915/display/vlv_dsi_pll.c u32 mask; mask 203 drivers/gpu/drm/i915/display/vlv_dsi_pll.c mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; mask 205 drivers/gpu/drm/i915/display/vlv_dsi_pll.c enabled = (val & mask) == mask; mask 897 drivers/gpu/drm/i915/gem/i915_gem_context.c ce->engine->mask)) { mask 902 drivers/gpu/drm/i915/gem/i915_gem_context.c if (!(ce->engine->mask & engines)) mask 464 drivers/gpu/drm/i915/gem/i915_gem_shmem.c gfp_t mask; mask 486 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; mask 489 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mask &= ~__GFP_HIGHMEM; mask 490 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mask |= __GFP_DMA32; mask 494 drivers/gpu/drm/i915/gem/i915_gem_shmem.c mapping_set_gfp_mask(mapping, mask); mask 347 drivers/gpu/drm/i915/gt/intel_engine.h void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask); mask 251 drivers/gpu/drm/i915/gt/intel_engine_cs.c void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask) mask 261 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_WRITE(engine, RING_HWSTAM, mask); mask 263 drivers/gpu/drm/i915/gt/intel_engine_cs.c ENGINE_WRITE16(engine, RING_HWSTAM, mask); mask 293 drivers/gpu/drm/i915/gt/intel_engine_cs.c BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); mask 296 drivers/gpu/drm/i915/gt/intel_engine_cs.c engine->mask = BIT(id); mask 357 drivers/gpu/drm/i915/gt/intel_engine_cs.c RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) || mask 402 drivers/gpu/drm/i915/gt/intel_engine_cs.c unsigned int mask = 0; mask 408 drivers/gpu/drm/i915/gt/intel_engine_cs.c GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); mask 421 drivers/gpu/drm/i915/gt/intel_engine_cs.c mask |= BIT(i); mask 429 drivers/gpu/drm/i915/gt/intel_engine_cs.c if (WARN_ON(mask != engine_mask)) mask 430 drivers/gpu/drm/i915/gt/intel_engine_cs.c device_info->engine_mask = mask; mask 432 drivers/gpu/drm/i915/gt/intel_engine_cs.c RUNTIME_INFO(i915)->num_engines = hweight32(mask); mask 299 drivers/gpu/drm/i915/gt/intel_engine_types.h intel_engine_mask_t mask; mask 401 drivers/gpu/drm/i915/gt/intel_gt_irq.c void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask) mask 403 drivers/gpu/drm/i915/gt/intel_gt_irq.c gen5_gt_update_irq(gt, mask, mask); mask 407 drivers/gpu/drm/i915/gt/intel_gt_irq.c void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask) mask 409 drivers/gpu/drm/i915/gt/intel_gt_irq.c gen5_gt_update_irq(gt, mask, 0); mask 34 drivers/gpu/drm/i915/gt/intel_gt_irq.h void gen5_gt_disable_irq(struct intel_gt *gt, u32 mask); mask 35 drivers/gpu/drm/i915/gt/intel_gt_irq.h void gen5_gt_enable_irq(struct intel_gt *gt, u32 mask); mask 17 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c u32 mask = gt->pm_imr; mask 22 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c mask <<= 16; /* pm is in upper half */ mask 29 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, mask); mask 52 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask) mask 54 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c gen6_gt_pm_update_irq(gt, mask, mask); mask 57 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask) mask 59 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c gen6_gt_pm_update_irq(gt, mask, 0); mask 78 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c u32 mask = gt->pm_ier; mask 83 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c mask <<= 16; /* pm is in upper half */ mask 90 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c intel_uncore_write(uncore, reg, mask); mask 14 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h void gen6_gt_pm_unmask_irq(struct intel_gt *gt, u32 mask); mask 15 drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask); mask 122 drivers/gpu/drm/i915/gt/intel_hangcheck.c intel_gt_handle_error(engine->gt, engine->mask, 0, mask 293 drivers/gpu/drm/i915/gt/intel_hangcheck.c hung |= engine->mask; mask 295 drivers/gpu/drm/i915/gt/intel_hangcheck.c stuck |= engine->mask; mask 299 drivers/gpu/drm/i915/gt/intel_hangcheck.c wedged |= engine->mask; mask 890 drivers/gpu/drm/i915/gt/intel_lrc.c if (!(rq->execution_mask & engine->mask)) /* We peeked too soon! */ mask 1213 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(!(rq->execution_mask & engine->mask)); mask 3528 drivers/gpu/drm/i915/gt/intel_lrc.c intel_engine_mask_t mask; mask 3535 drivers/gpu/drm/i915/gt/intel_lrc.c mask = rq->execution_mask; mask 3536 drivers/gpu/drm/i915/gt/intel_lrc.c if (unlikely(!mask)) { mask 3539 drivers/gpu/drm/i915/gt/intel_lrc.c mask = ve->siblings[0]->mask; mask 3545 drivers/gpu/drm/i915/gt/intel_lrc.c mask, ve->base.execlists.queue_priority_hint); mask 3547 drivers/gpu/drm/i915/gt/intel_lrc.c return mask; mask 3554 drivers/gpu/drm/i915/gt/intel_lrc.c intel_engine_mask_t mask; mask 3558 drivers/gpu/drm/i915/gt/intel_lrc.c mask = virtual_submission_mask(ve); mask 3560 drivers/gpu/drm/i915/gt/intel_lrc.c if (unlikely(!mask)) mask 3570 drivers/gpu/drm/i915/gt/intel_lrc.c if (unlikely(!(mask & sibling->mask))) { mask 3691 drivers/gpu/drm/i915/gt/intel_lrc.c allowed = ~to_request(signal)->engine->mask; mask 3773 drivers/gpu/drm/i915/gt/intel_lrc.c GEM_BUG_ON(!is_power_of_2(sibling->mask)); mask 3774 drivers/gpu/drm/i915/gt/intel_lrc.c if (sibling->mask & ve->base.mask) { mask 3798 drivers/gpu/drm/i915/gt/intel_lrc.c ve->base.mask |= sibling->mask; mask 3895 drivers/gpu/drm/i915/gt/intel_lrc.c bond->sibling_mask |= sibling->mask; mask 3906 drivers/gpu/drm/i915/gt/intel_lrc.c bond[ve->num_bonds].sibling_mask = sibling->mask; mask 448 drivers/gpu/drm/i915/gt/intel_reset.c u32 request, mask, ack; mask 458 drivers/gpu/drm/i915/gt/intel_reset.c mask = RESET_CTL_CAT_ERROR; mask 464 drivers/gpu/drm/i915/gt/intel_reset.c mask = RESET_CTL_READY_TO_RESET; mask 471 drivers/gpu/drm/i915/gt/intel_reset.c ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, mask 657 drivers/gpu/drm/i915/gt/intel_reset.c awake |= engine->mask; mask 686 drivers/gpu/drm/i915/gt/intel_reset.c __intel_engine_reset(engine, stalled_mask & engine->mask); mask 708 drivers/gpu/drm/i915/gt/intel_reset.c if (awake & engine->mask) mask 1013 drivers/gpu/drm/i915/gt/intel_reset.c return __intel_gt_reset(engine->gt, engine->mask); mask 1173 drivers/gpu/drm/i915/gt/intel_reset.c engine_mask &= ~engine->mask; mask 489 drivers/gpu/drm/i915/gt/intel_ringbuffer.c static void set_hwstam(struct intel_engine_cs *engine, u32 mask) mask 497 drivers/gpu/drm/i915/gt/intel_ringbuffer.c mask &= ~BIT(0); mask 499 drivers/gpu/drm/i915/gt/intel_ringbuffer.c mask &= ~I915_USER_INTERRUPT; mask 502 drivers/gpu/drm/i915/gt/intel_ringbuffer.c intel_engine_set_hwsp_writemask(engine, mask); mask 1777 drivers/gpu/drm/i915/gt/intel_ringbuffer.c if (ppgtt->pd_dirty_engines & engine->mask) { mask 1778 drivers/gpu/drm/i915/gt/intel_ringbuffer.c unwind_mm = engine->mask; mask 113 drivers/gpu/drm/i915/gt/intel_sseu.c u32 mask, val = slices; mask 116 drivers/gpu/drm/i915/gt/intel_sseu.c mask = GEN11_RPCS_S_CNT_MASK; mask 119 drivers/gpu/drm/i915/gt/intel_sseu.c mask = GEN8_RPCS_S_CNT_MASK; mask 123 drivers/gpu/drm/i915/gt/intel_sseu.c GEM_BUG_ON(val & ~mask); mask 124 drivers/gpu/drm/i915/gt/intel_sseu.c val &= mask; mask 117 drivers/gpu/drm/i915/gt/intel_workarounds.c if ((wa->mask & ~wa_->mask) == 0) { mask 120 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->mask, wa_->val); mask 122 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->val &= ~wa->mask; mask 127 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->mask |= wa->mask; mask 149 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, mask 154 drivers/gpu/drm/i915/gt/intel_workarounds.c .mask = mask, mask 156 drivers/gpu/drm/i915/gt/intel_workarounds.c .read = mask, mask 180 drivers/gpu/drm/i915/gt/intel_workarounds.c #define WA_SET_BIT_MASKED(addr, mask) \ mask 181 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask)) mask 183 drivers/gpu/drm/i915/gt/intel_workarounds.c #define WA_CLR_BIT_MASKED(addr, mask) \ mask 184 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask)) mask 186 drivers/gpu/drm/i915/gt/intel_workarounds.c #define WA_SET_FIELD_MASKED(addr, mask, value) \ mask 187 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value))) mask 957 drivers/gpu/drm/i915/gt/intel_workarounds.c wa->val, wa->mask); mask 982 drivers/gpu/drm/i915/gt/intel_workarounds.c intel_uncore_rmw_fw(uncore, wa->reg, wa->mask, wa->val); mask 16 drivers/gpu/drm/i915/gt/intel_workarounds_types.h u32 mask; mask 253 drivers/gpu/drm/i915/gt/mock_engine.c engine->base.mask = BIT(id); mask 1037 drivers/gpu/drm/i915/gt/selftest_hangcheck.c static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask) mask 1041 drivers/gpu/drm/i915/gt/selftest_hangcheck.c intel_gt_reset(gt, mask, NULL); mask 1302 drivers/gpu/drm/i915/gt/selftest_hangcheck.c fake_hangcheck(gt, rq->engine->mask); mask 1589 drivers/gpu/drm/i915/gt/selftest_hangcheck.c intel_gt_handle_error(gt, engine->mask, 0, NULL); mask 1892 drivers/gpu/drm/i915/gt/selftest_lrc.c request[n]->execution_mask = siblings[nsibling - n - 1]->mask; mask 375 drivers/gpu/drm/i915/gt/selftest_timeline.c unsigned int mask = BIT(order) - 1; mask 387 drivers/gpu/drm/i915/gt/selftest_timeline.c u64 id = (u64)(count & mask) << order; mask 230 drivers/gpu/drm/i915/gt/selftest_workarounds.c intel_gt_reset(engine->gt, engine->mask, "live_workarounds"); mask 183 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) mask 186 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->msg_enabled_mask |= mask; mask 190 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) mask 193 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->msg_enabled_mask &= ~mask; mask 20 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.mask = HUC_LOAD_SUCCESSFUL; mask 24 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.mask = HUC_FW_VERIFIED; mask 151 drivers/gpu/drm/i915/gt/uc/intel_huc.c huc->status.mask, mask 191 drivers/gpu/drm/i915/gt/uc/intel_huc.c return (status & huc->status.mask) == huc->status.value; mask 22 drivers/gpu/drm/i915/gt/uc/intel_huc.h u32 mask; mask 357 drivers/gpu/drm/i915/gt/uc/intel_uc.c u32 mask; mask 375 drivers/gpu/drm/i915/gt/uc/intel_uc.c mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED; mask 376 drivers/gpu/drm/i915/gt/uc/intel_uc.c err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask, mask 381 drivers/gpu/drm/i915/gt/uc/intel_uc.c mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent; mask 383 drivers/gpu/drm/i915/gt/uc/intel_uc.c base | huc_agent, mask, mask 72 drivers/gpu/drm/i915/gvt/cfg_space.c u8 mask, new, old; mask 76 drivers/gpu/drm/i915/gvt/cfg_space.c mask = pci_cfg_space_rw_bmp[off + i]; mask 78 drivers/gpu/drm/i915/gvt/cfg_space.c new = src[i] & mask; mask 86 drivers/gpu/drm/i915/gvt/cfg_space.c new = (~new & old) & mask; mask 88 drivers/gpu/drm/i915/gvt/cfg_space.c cfg_base[off + i] = (old & ~mask) | new; mask 90 drivers/gpu/drm/i915/gvt/execlist.h u32 mask :16; mask 3478 drivers/gpu/drm/i915/gvt/handlers.c u32 mask, old_vreg; mask 3482 drivers/gpu/drm/i915/gvt/handlers.c mask = vgpu_vreg(vgpu, offset) >> 16; mask 3483 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | mask 3484 drivers/gpu/drm/i915/gvt/handlers.c (vgpu_vreg(vgpu, offset) & mask); mask 3575 drivers/gpu/drm/i915/gvt/handlers.c u32 mask = vgpu_vreg(vgpu, offset) >> 16; mask 3577 drivers/gpu/drm/i915/gvt/handlers.c vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) mask 3578 drivers/gpu/drm/i915/gvt/handlers.c | (vgpu_vreg(vgpu, offset) & mask); mask 222 drivers/gpu/drm/i915/gvt/mmio_context.c (mmio->mask << 16); mask 495 drivers/gpu/drm/i915/gvt/mmio_context.c if (mmio->mask) mask 497 drivers/gpu/drm/i915/gvt/mmio_context.c ~(mmio->mask << 16); mask 514 drivers/gpu/drm/i915/gvt/mmio_context.c if (mmio->mask) mask 516 drivers/gpu/drm/i915/gvt/mmio_context.c (mmio->mask << 16); mask 522 drivers/gpu/drm/i915/gvt/mmio_context.c if (mmio->mask) mask 523 drivers/gpu/drm/i915/gvt/mmio_context.c new_v = mmio->value | (mmio->mask << 16); mask 42 drivers/gpu/drm/i915/gvt/mmio_context.h u32 mask; mask 589 drivers/gpu/drm/i915/i915_active.c intel_engine_mask_t tmp, mask = engine->mask; mask 601 drivers/gpu/drm/i915/i915_active.c for_each_engine_masked(engine, i915, mask, tmp) { mask 120 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 132 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 146 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 164 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 220 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), mask 222 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC }, mask 225 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 229 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC }, mask 232 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 255 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 262 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 268 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_REPORT_PERF_COUNT_GGTT, mask 274 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 282 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, mask 291 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), mask 296 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | mask 313 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), mask 333 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 340 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_NOTIFY, mask 345 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_USE_GTT, mask 352 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_STORE_INDEX, mask 360 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 377 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 384 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_NOTIFY, mask 389 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_USE_GTT, mask 396 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_STORE_INDEX, mask 404 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 414 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_GLOBAL_GTT, mask 421 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_NOTIFY, mask 426 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_USE_GTT, mask 433 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_FLUSH_DW_STORE_INDEX, mask 477 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), mask 480 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC } ), mask 483 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC } ), mask 485 drivers/gpu/drm/i915/i915_cmd_parser.c .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), mask 496 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = MI_BB_START_OPERAND_MASK, mask 567 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 652 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, mask 655 drivers/gpu/drm/i915/i915_cmd_parser.c .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | mask 803 drivers/gpu/drm/i915/i915_cmd_parser.c u32 curr = desc->cmd.value & desc->cmd.mask; mask 1056 drivers/gpu/drm/i915/i915_cmd_parser.c if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) mask 1077 drivers/gpu/drm/i915/i915_cmd_parser.c u32 mask; mask 1079 drivers/gpu/drm/i915/i915_cmd_parser.c if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) mask 1086 drivers/gpu/drm/i915/i915_cmd_parser.c mask = engine->get_cmd_length_mask(cmd_header); mask 1087 drivers/gpu/drm/i915/i915_cmd_parser.c if (!mask) mask 1091 drivers/gpu/drm/i915/i915_cmd_parser.c default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; mask 1092 drivers/gpu/drm/i915/i915_cmd_parser.c default_desc->length.mask = mask; mask 1229 drivers/gpu/drm/i915/i915_cmd_parser.c const u32 reg_addr = cmd[offset] & desc->reg.mask; mask 1243 drivers/gpu/drm/i915/i915_cmd_parser.c if (reg->mask) { mask 1258 drivers/gpu/drm/i915/i915_cmd_parser.c (cmd[offset + 1] & reg->mask) != reg->value)) { mask 1273 drivers/gpu/drm/i915/i915_cmd_parser.c if (desc->bits[i].mask == 0) mask 1293 drivers/gpu/drm/i915/i915_cmd_parser.c desc->bits[i].mask; mask 1298 drivers/gpu/drm/i915/i915_cmd_parser.c desc->bits[i].mask, mask 1471 drivers/gpu/drm/i915/i915_cmd_parser.c length = ((*cmd & desc->length.mask) + LENGTH_BIAS); mask 1323 drivers/gpu/drm/i915/i915_debugfs.c u32 mask; mask 1326 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; mask 1328 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; mask 1330 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; mask 1332 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; mask 1334 drivers/gpu/drm/i915/i915_debugfs.c mask = I915_READ(FBC_STATUS) & (FBC_STAT_COMPRESSING | mask 1337 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Compressing: %s\n", yesno(mask)); mask 2893 drivers/gpu/drm/i915/i915_debugfs.c wa->val, wa->mask); mask 2417 drivers/gpu/drm/i915/i915_drv.c u32 mask, u32 val) mask 2431 drivers/gpu/drm/i915/i915_drv.c intel_uncore_read_notrace(&i915->uncore, reg)) & mask) mask 2468 drivers/gpu/drm/i915/i915_drv.c u32 mask; mask 2479 drivers/gpu/drm/i915/i915_drv.c mask = VLV_GTLC_ALLOWWAKEACK; mask 2480 drivers/gpu/drm/i915/i915_drv.c val = allow ? mask : 0; mask 2482 drivers/gpu/drm/i915/i915_drv.c err = vlv_wait_for_pw_status(dev_priv, mask, val); mask 2492 drivers/gpu/drm/i915/i915_drv.c u32 mask; mask 2495 drivers/gpu/drm/i915/i915_drv.c mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; mask 2496 drivers/gpu/drm/i915/i915_drv.c val = wait_for_on ? mask : 0; mask 2505 drivers/gpu/drm/i915/i915_drv.c if (vlv_wait_for_pw_status(dev_priv, mask, val)) mask 2521 drivers/gpu/drm/i915/i915_drv.c u32 mask; mask 2530 drivers/gpu/drm/i915/i915_drv.c mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; mask 2531 drivers/gpu/drm/i915/i915_drv.c WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); mask 1918 drivers/gpu/drm/i915/i915_drv.h const u32 mask = info->platform_mask[pi]; mask 1925 drivers/gpu/drm/i915/i915_drv.h return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); mask 882 drivers/gpu/drm/i915/i915_gem_gtt.c const u64 mask = ~0ull << gen8_pd_shift(lvl + 1); mask 885 drivers/gpu/drm/i915/i915_gem_gtt.c end += ~mask >> gen8_pd_shift(1); mask 888 drivers/gpu/drm/i915/i915_gem_gtt.c if ((start ^ end) & mask) mask 896 drivers/gpu/drm/i915/i915_gem_gtt.c const u64 mask = ~0ull << gen8_pd_shift(lvl + 1); mask 899 drivers/gpu/drm/i915/i915_gem_gtt.c return (start ^ end) & mask && (start & ~mask) == 0; mask 471 drivers/gpu/drm/i915/i915_gem_gtt.h const u32 mask = NUM_PTE(pde_shift) - 1; mask 473 drivers/gpu/drm/i915/i915_gem_gtt.h return (address >> PAGE_SHIFT) & mask; mask 482 drivers/gpu/drm/i915/i915_gem_gtt.h const u64 mask = ~((1ULL << pde_shift) - 1); mask 490 drivers/gpu/drm/i915/i915_gem_gtt.h if ((addr & mask) != (end & mask)) mask 265 drivers/gpu/drm/i915/i915_irq.c u32 mask, mask 271 drivers/gpu/drm/i915/i915_irq.c WARN_ON(bits & ~mask); mask 274 drivers/gpu/drm/i915/i915_irq.c val &= ~mask; mask 292 drivers/gpu/drm/i915/i915_irq.c u32 mask, mask 296 drivers/gpu/drm/i915/i915_irq.c i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); mask 383 drivers/gpu/drm/i915/i915_irq.c u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask) mask 385 drivers/gpu/drm/i915/i915_irq.c return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz; mask 2119 drivers/gpu/drm/i915/i915_irq.c u32 mask = PORTA_HOTPLUG_STATUS_MASK | mask 2123 drivers/gpu/drm/i915/i915_irq.c dig_hotplug_reg &= ~mask; mask 2616 drivers/gpu/drm/i915/i915_irq.c u32 mask; mask 2624 drivers/gpu/drm/i915/i915_irq.c mask = GEN8_AUX_CHANNEL_A; mask 2626 drivers/gpu/drm/i915/i915_irq.c mask |= GEN9_AUX_CHANNEL_B | mask 2631 drivers/gpu/drm/i915/i915_irq.c mask |= CNL_AUX_CHANNEL_F; mask 2634 drivers/gpu/drm/i915/i915_irq.c mask |= ICL_AUX_CHANNEL_E; mask 2636 drivers/gpu/drm/i915/i915_irq.c return mask; mask 3643 drivers/gpu/drm/i915/i915_irq.c u32 mask; mask 3649 drivers/gpu/drm/i915/i915_irq.c mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; mask 3651 drivers/gpu/drm/i915/i915_irq.c mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; mask 3653 drivers/gpu/drm/i915/i915_irq.c mask = SDE_GMBUS_CPT; mask 3656 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(SDEIMR, ~mask); mask 3844 drivers/gpu/drm/i915/i915_irq.c u32 mask = SDE_GMBUS_ICP; mask 3851 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(SDEIMR, ~mask); mask 47 drivers/gpu/drm/i915/i915_irq.h u32 mask, mask 90 drivers/gpu/drm/i915/i915_irq.h void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); mask 91 drivers/gpu/drm/i915/i915_irq.h void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask); mask 97 drivers/gpu/drm/i915/i915_irq.h u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask); mask 662 drivers/gpu/drm/i915/i915_perf.c u32 mask = (OA_BUFFER_SIZE - 1); mask 711 drivers/gpu/drm/i915/i915_perf.c head = (head + report_size) & mask) { mask 950 drivers/gpu/drm/i915/i915_perf.c u32 mask = (OA_BUFFER_SIZE - 1); mask 996 drivers/gpu/drm/i915/i915_perf.c head = (head + report_size) & mask) { mask 262 drivers/gpu/drm/i915/i915_reg.h #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) mask 263 drivers/gpu/drm/i915/i915_reg.h #define _MASKED_FIELD(mask, value) ({ \ mask 264 drivers/gpu/drm/i915/i915_reg.h if (__builtin_constant_p(mask)) \ mask 265 drivers/gpu/drm/i915/i915_reg.h BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ mask 268 drivers/gpu/drm/i915/i915_reg.h if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ mask 269 drivers/gpu/drm/i915/i915_reg.h BUILD_BUG_ON_MSG((value) & ~(mask), \ mask 271 drivers/gpu/drm/i915/i915_reg.h __MASKED_FIELD(mask, value); }) mask 3305 drivers/gpu/drm/i915/i915_reg.h #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) mask 844 drivers/gpu/drm/i915/i915_request.c if (already_busywaiting(to) & from->engine->mask) mask 884 drivers/gpu/drm/i915/i915_request.c to->sched.semaphores |= from->engine->mask; mask 1154 drivers/gpu/drm/i915/i915_request.c if (is_power_of_2(prev->engine->mask | rq->engine->mask)) mask 61 drivers/gpu/drm/i915/i915_sysfs.c unsigned int mask; mask 63 drivers/gpu/drm/i915/i915_sysfs.c mask = 0; mask 65 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(0); mask 67 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(1); mask 69 drivers/gpu/drm/i915/i915_sysfs.c mask |= BIT(2); mask 71 drivers/gpu/drm/i915/i915_sysfs.c return snprintf(buf, PAGE_SIZE, "%x\n", mask); mask 230 drivers/gpu/drm/i915/i915_utils.h #define __mask_next_bit(mask) ({ \ mask 231 drivers/gpu/drm/i915/i915_utils.h int __idx = ffs(mask) - 1; \ mask 232 drivers/gpu/drm/i915/i915_utils.h mask &= ~BIT(__idx); \ mask 271 drivers/gpu/drm/i915/intel_csr.c u32 val, mask; mask 273 drivers/gpu/drm/i915/intel_csr.c mask = DC_STATE_DEBUG_MASK_MEMORY_UP; mask 276 drivers/gpu/drm/i915/intel_csr.c mask |= DC_STATE_DEBUG_MASK_CORES; mask 280 drivers/gpu/drm/i915/intel_csr.c if ((val & mask) != mask) { mask 281 drivers/gpu/drm/i915/intel_csr.c val |= mask; mask 817 drivers/gpu/drm/i915/intel_device_info.c u32 mask = 0; mask 825 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_ULT); mask 828 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_ULX); mask 831 drivers/gpu/drm/i915/intel_device_info.c mask |= BIT(INTEL_SUBPLATFORM_ULT); mask 835 drivers/gpu/drm/i915/intel_device_info.c mask = BIT(INTEL_SUBPLATFORM_PORTF); mask 838 drivers/gpu/drm/i915/intel_device_info.c GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS); mask 840 drivers/gpu/drm/i915/intel_device_info.c RUNTIME_INFO(i915)->platform_mask[pi] |= mask; mask 6704 drivers/gpu/drm/i915/intel_pm.c u32 mask = 0; mask 6708 drivers/gpu/drm/i915/intel_pm.c mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; mask 6710 drivers/gpu/drm/i915/intel_pm.c mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; mask 6712 drivers/gpu/drm/i915/intel_pm.c mask &= dev_priv->pm_rps_events; mask 6714 drivers/gpu/drm/i915/intel_pm.c return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); mask 107 drivers/gpu/drm/i915/intel_uncore.c GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); mask 108 drivers/gpu/drm/i915/intel_uncore.c d->uncore->fw_domains_timer |= d->mask; mask 385 drivers/gpu/drm/i915/intel_uncore.c uncore->fw_domains_timer &= ~domain->mask; mask 389 drivers/gpu/drm/i915/intel_uncore.c uncore->funcs.force_wake_put(uncore, domain->mask); mask 428 drivers/gpu/drm/i915/intel_uncore.c active_domains |= domain->mask; mask 594 drivers/gpu/drm/i915/intel_uncore.c fw_domains &= ~domain->mask; mask 793 drivers/gpu/drm/i915/intel_uncore.c if (uncore->fw_domains_timer & domain->mask) mask 1394 drivers/gpu/drm/i915/intel_uncore.c d->mask = BIT(domain_id); mask 1898 drivers/gpu/drm/i915/intel_uncore.c u32 mask, mask 1905 drivers/gpu/drm/i915/intel_uncore.c #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) mask 1946 drivers/gpu/drm/i915/intel_uncore.c u32 mask, mask 1963 drivers/gpu/drm/i915/intel_uncore.c reg, mask, value, mask 1972 drivers/gpu/drm/i915/intel_uncore.c (reg_value & mask) == value, mask 139 drivers/gpu/drm/i915/intel_uncore.h enum forcewake_domains mask; mask 225 drivers/gpu/drm/i915/intel_uncore.h u32 mask, mask 233 drivers/gpu/drm/i915/intel_uncore.h u32 mask, mask 237 drivers/gpu/drm/i915/intel_uncore.h return __intel_wait_for_register(uncore, reg, mask, value, 2, mask 243 drivers/gpu/drm/i915/intel_uncore.h u32 mask, mask 251 drivers/gpu/drm/i915/intel_uncore.h u32 mask, mask 255 drivers/gpu/drm/i915/intel_uncore.h return __intel_wait_for_register_fw(uncore, reg, mask, value, mask 402 drivers/gpu/drm/i915/intel_uncore.h u32 mask, u32 expected_val) mask 409 drivers/gpu/drm/i915/intel_uncore.h return (reg_val & mask) != expected_val ? -EINVAL : 0; mask 83 drivers/gpu/drm/imx/imx-ldb.c int mask; mask 235 drivers/gpu/drm/imx/imx-ldb.c regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, mask 330 drivers/gpu/drm/imx/imx-ldb.c mux &= lvds_mux->mask; mask 523 drivers/gpu/drm/imx/imx-ldb.c .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, mask 527 drivers/gpu/drm/imx/imx-ldb.c .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, mask 185 drivers/gpu/drm/imx/imx-tve.c unsigned int mask; mask 206 drivers/gpu/drm/imx/imx-tve.c mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; mask 208 drivers/gpu/drm/imx/imx-tve.c mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; mask 210 drivers/gpu/drm/imx/imx-tve.c mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; mask 212 drivers/gpu/drm/imx/imx-tve.c ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); mask 18 drivers/gpu/drm/lima/lima_bcast.c int i, mask = bcast_read(LIMA_BCAST_BROADCAST_MASK) & 0xffff0000; mask 23 drivers/gpu/drm/lima/lima_bcast.c mask |= 1 << (pp->id - lima_ip_pp0); mask 26 drivers/gpu/drm/lima/lima_bcast.c bcast_write(LIMA_BCAST_BROADCAST_MASK, mask); mask 31 drivers/gpu/drm/lima/lima_bcast.c int i, mask = 0; mask 35 drivers/gpu/drm/lima/lima_bcast.c mask |= 1 << (i - lima_ip_pp0); mask 38 drivers/gpu/drm/lima/lima_bcast.c bcast_write(LIMA_BCAST_BROADCAST_MASK, mask << 16); mask 39 drivers/gpu/drm/lima/lima_bcast.c bcast_write(LIMA_BCAST_INTERRUPT_MASK, mask); mask 19 drivers/gpu/drm/lima/lima_dlbu.c int i, mask = 0; mask 24 drivers/gpu/drm/lima/lima_dlbu.c mask |= 1 << (pp->id - lima_ip_pp0); mask 27 drivers/gpu/drm/lima/lima_dlbu.c dlbu_write(LIMA_DLBU_PP_ENABLE_MASK, mask); mask 82 drivers/gpu/drm/mediatek/mtk_cec.c unsigned int val, unsigned int mask) mask 84 drivers/gpu/drm/mediatek/mtk_cec.c u32 tmp = readl(cec->regs + offset) & ~mask; mask 86 drivers/gpu/drm/mediatek/mtk_cec.c tmp |= val & mask; mask 89 drivers/gpu/drm/mediatek/mtk_disp_rdma.c unsigned int mask, unsigned int val) mask 93 drivers/gpu/drm/mediatek/mtk_disp_rdma.c tmp = (tmp & ~mask) | (val & mask); mask 116 drivers/gpu/drm/mediatek/mtk_dpi.c static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) mask 118 drivers/gpu/drm/mediatek/mtk_dpi.c u32 tmp = readl(dpi->regs + offset) & ~mask; mask 120 drivers/gpu/drm/mediatek/mtk_dpi.c tmp |= (val & mask); mask 196 drivers/gpu/drm/mediatek/mtk_dsi.c static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) mask 200 drivers/gpu/drm/mediatek/mtk_dsi.c writel((temp & ~mask) | (data & mask), dsi->regs + offset); mask 213 drivers/gpu/drm/mediatek/mtk_hdmi.c static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) mask 219 drivers/gpu/drm/mediatek/mtk_hdmi.c tmp = (tmp & ~mask) | (val & mask); mask 503 drivers/gpu/drm/mediatek/mtk_hdmi.c const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; mask 514 drivers/gpu/drm/mediatek/mtk_hdmi.c mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); mask 81 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int mask, unsigned int shift, mask 87 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c tmp &= ~mask; mask 88 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c tmp |= (val << shift) & mask; mask 93 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c unsigned int offset, unsigned int mask, mask 96 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c return (readl(ddc->regs + offset) & mask) >> shift; mask 41 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c u32 val, u32 mask) mask 47 drivers/gpu/drm/mediatek/mtk_hdmi_phy.c tmp = (tmp & ~mask) | (val & mask); mask 50 drivers/gpu/drm/mediatek/mtk_hdmi_phy.h u32 val, u32 mask); mask 157 drivers/gpu/drm/mediatek/mtk_mipi_tx.c u32 mask, u32 data) mask 161 drivers/gpu/drm/mediatek/mtk_mipi_tx.c writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset); mask 216 drivers/gpu/drm/meson/meson_dw_hdmi.c unsigned int mask, mask 221 drivers/gpu/drm/meson/meson_dw_hdmi.c data &= ~mask; mask 280 drivers/gpu/drm/meson/meson_dw_hdmi.c unsigned int mask, mask 285 drivers/gpu/drm/meson/meson_dw_hdmi.c data &= ~mask; mask 14 drivers/gpu/drm/meson/meson_registers.h #define writel_bits_relaxed(mask, val, addr) \ mask 15 drivers/gpu/drm/meson/meson_registers.h writel_relaxed((readl_relaxed(addr) & ~(mask)) | ((val) & (mask)), addr) mask 43 drivers/gpu/drm/mgag200/mgag200_i2c.c static void mga_i2c_set_gpio(struct mga_device *mdev, int mask, int val) mask 48 drivers/gpu/drm/mgag200/mgag200_i2c.c tmp = (RREG8(DAC_DATA) & mask) | val; mask 53 drivers/gpu/drm/mgag200/mgag200_i2c.c static inline void mga_i2c_set(struct mga_device *mdev, int mask, int state) mask 58 drivers/gpu/drm/mgag200/mgag200_i2c.c state = mask; mask 59 drivers/gpu/drm/mgag200/mgag200_i2c.c mga_i2c_set_gpio(mdev, ~mask, state); mask 131 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t reg, uint32_t mask, uint32_t value) mask 135 drivers/gpu/drm/msm/adreno/a5xx_gpu.h if ((gpu_read(gpu, reg) & mask) == value) mask 92 drivers/gpu/drm/msm/adreno/a6xx_gmu.h static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) mask 96 drivers/gpu/drm/msm/adreno/a6xx_gmu.h val &= ~mask; mask 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c u32 mask, u8 en) mask 208 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c opmode |= mask; mask 210 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c opmode &= ~mask; mask 216 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c u32 mask, u8 en) mask 226 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c opmode |= mask; mask 228 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c opmode &= ~mask; mask 159 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift; mask 172 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c mask = 0x7 << reg_shift; mask 174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~mask; mask 175 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= (remap_level << reg_shift) & mask; mask 177 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val_lvl &= ~mask; mask 178 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val_lvl |= (remap_level << reg_shift) & mask; mask 1052 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c u32 mask; mask 1057 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mask = pstate->hwpipe->flush_mask; mask 1060 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mask |= pstate->r_hwpipe->flush_mask; mask 1062 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c return mask; mask 66 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable) mask 72 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->vblank_mask |= mask; mask 74 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->vblank_mask &= ~mask; mask 65 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable); mask 762 drivers/gpu/drm/msm/dsi/dsi_host.c static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) mask 771 drivers/gpu/drm/msm/dsi/dsi_host.c intr |= mask; mask 773 drivers/gpu/drm/msm/dsi/dsi_host.c intr &= ~mask; mask 134 drivers/gpu/drm/msm/msm_atomic.c unsigned i, mask = 0; mask 137 drivers/gpu/drm/msm/msm_atomic.c mask |= drm_crtc_mask(crtc); mask 139 drivers/gpu/drm/msm/msm_atomic.c return mask; mask 224 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) mask 228 drivers/gpu/drm/msm/msm_gpu.h val &= ~mask; mask 165 drivers/gpu/drm/mxsfb/mxsfb_crtc.c static int clear_poll_bit(void __iomem *addr, u32 mask) mask 169 drivers/gpu/drm/mxsfb/mxsfb_crtc.c writel(mask, addr + MXS_CLR_ADDR); mask 170 drivers/gpu/drm/mxsfb/mxsfb_crtc.c return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT); mask 392 drivers/gpu/drm/nouveau/dispnv04/hw.h int mask; mask 401 drivers/gpu/drm/nouveau/dispnv04/hw.h mask = 128 / bpp - 1; mask 403 drivers/gpu/drm/nouveau/dispnv04/hw.h mask = 512 / bpp - 1; mask 405 drivers/gpu/drm/nouveau/dispnv04/hw.h return (width + mask) & ~mask; mask 20 drivers/gpu/drm/nouveau/dispnv50/atom.h u32 mask; mask 139 drivers/gpu/drm/nouveau/dispnv50/atom.h u16 mask; mask 243 drivers/gpu/drm/nouveau/dispnv50/atom.h u8 mask; mask 72 drivers/gpu/drm/nouveau/dispnv50/disp.c u8 mask; mask 1853 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->clr.mask, asyh->set.mask); mask 1860 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->clr.mask) { mask 1872 drivers/gpu/drm/nouveau/dispnv50/disp.c asyw->clr.mask, asyw->set.mask); mask 1873 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!asyw->clr.mask) mask 1888 drivers/gpu/drm/nouveau/dispnv50/disp.c outp->clr.mask, outp->set.mask); mask 1890 drivers/gpu/drm/nouveau/dispnv50/disp.c if (outp->clr.mask) { mask 1919 drivers/gpu/drm/nouveau/dispnv50/disp.c outp->set.mask, outp->clr.mask); mask 1921 drivers/gpu/drm/nouveau/dispnv50/disp.c if (outp->set.mask) { mask 1936 drivers/gpu/drm/nouveau/dispnv50/disp.c asyh->set.mask, asyh->clr.mask); mask 1938 drivers/gpu/drm/nouveau/dispnv50/disp.c if (asyh->set.mask) { mask 1959 drivers/gpu/drm/nouveau/dispnv50/disp.c asyw->set.mask, asyw->clr.mask); mask 1960 drivers/gpu/drm/nouveau/dispnv50/disp.c if ( !asyw->set.mask && mask 1961 drivers/gpu/drm/nouveau/dispnv50/disp.c (!asyw->clr.mask || atom->flush_disable)) mask 38 drivers/gpu/drm/nouveau/dispnv50/head.c .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), mask 226 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->wndw.olut != asyh->wndw.mask) mask 323 drivers/gpu/drm/nouveau/dispnv50/head.c asyc->set.mask = ~0; mask 324 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.mask = ~0; mask 398 drivers/gpu/drm/nouveau/dispnv50/head.c if (asyh->clr.mask || asyh->set.mask) mask 437 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->clr.mask = 0; mask 438 drivers/gpu/drm/nouveau/dispnv50/head.c asyh->set.mask = 0; mask 118 drivers/gpu/drm/nouveau/dispnv50/wndw.c .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), mask 155 drivers/gpu/drm/nouveau/dispnv50/wndw.c if (asyw->set.point = false, asyw->set.mask) mask 437 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyh->wndw.mask |= BIT(wndw->id); mask 441 drivers/gpu/drm/nouveau/dispnv50/wndw.c harm->wndw.mask &= ~BIT(wndw->id); mask 551 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->clr.mask = 0; mask 552 drivers/gpu/drm/nouveau/dispnv50/wndw.c asyw->set.mask = 0; mask 43 drivers/gpu/drm/nouveau/include/nvif/event.h __u8 mask; mask 51 drivers/gpu/drm/nouveau/include/nvif/event.h __u8 mask; mask 36 drivers/gpu/drm/nouveau/include/nvif/if0002.h __u32 mask; mask 48 drivers/gpu/drm/nouveau/include/nvif/mmu.h nvif_mmu_type(struct nvif_mmu *mmu, u8 mask) mask 52 drivers/gpu/drm/nouveau/include/nvif/mmu.h if ((mmu->type[i].type & mask) == mask) mask 16 drivers/gpu/drm/nouveau/include/nvkm/core/enum.h u32 mask; mask 106 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val) mask 110 drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h return nvkm_mask(device, falcon->addr + addr, mask, val); mask 39 drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR); mask 63 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h u16 dcb_outp_match(struct nvkm_bios *, u16 type, u16 mask, u8 *, u8 *, mask 17 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h u16 mask; mask 25 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/disp.h u16 nvbios_outp_match(struct nvkm_bios *, u16 type, u16 mask, mask 10 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h u16 mask; mask 19 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dp.h u16 nvbios_dpout_match(struct nvkm_bios *, u16 type, u16 mask, mask 14 drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h u8 mask; mask 19 drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h u8 mask; mask 16 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 mask; mask 21 drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h u8 mask; mask 39 drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value); mask 52 drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h void nvkm_memx_wait(struct nvkm_memx *, u32 addr, u32 mask, u32 data, u32 nsec); mask 69 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h #define nvkm_wait_nsec(d,n,addr,mask,data) \ mask 71 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h if ((nvkm_rd32(d, (addr)) & (mask)) == (data)) \ mask 74 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h #define nvkm_wait_usec(d,u,addr,mask,data) \ mask 75 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h nvkm_wait_nsec((d), (u) * 1000, (addr), (mask), (data)) mask 76 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h #define nvkm_wait_msec(d,m,addr,mask,data) \ mask 77 drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h nvkm_wait_usec((d), (m) * 1000, (addr), (mask), (data)) mask 1421 drivers/gpu/drm/nouveau/nouveau_bios.c uint32_t mask; mask 1425 drivers/gpu/drm/nouveau/nouveau_bios.c mask = ~0xd; mask 1439 drivers/gpu/drm/nouveau/nouveau_bios.c mask = ~0x7; mask 1447 drivers/gpu/drm/nouveau/nouveau_bios.c if (conf & mask) { mask 241 drivers/gpu/drm/nouveau/nouveau_connector.c asyc->set.mask = 0; mask 1148 drivers/gpu/drm/nouveau/nouveau_connector.c bool plugged = (rep->mask != NVIF_NOTIFY_CONN_V0_UNPLUG); mask 1150 drivers/gpu/drm/nouveau/nouveau_connector.c if (rep->mask & NVIF_NOTIFY_CONN_V0_IRQ) { mask 1441 drivers/gpu/drm/nouveau/nouveau_connector.c .mask = NVIF_NOTIFY_CONN_V0_ANY, mask 98 drivers/gpu/drm/nouveau/nouveau_connector.h u8 mask; mask 100 drivers/gpu/drm/nouveau/nv50_fbcon.c uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); mask 114 drivers/gpu/drm/nouveau/nv50_fbcon.c OUT_RING(chan, palette[image->bg_color] | mask); mask 115 drivers/gpu/drm/nouveau/nv50_fbcon.c OUT_RING(chan, palette[image->fg_color] | mask); mask 100 drivers/gpu/drm/nouveau/nvc0_fbcon.c uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); mask 114 drivers/gpu/drm/nouveau/nvc0_fbcon.c OUT_RING (chan, palette[image->bg_color] | mask); mask 115 drivers/gpu/drm/nouveau/nvc0_fbcon.c OUT_RING (chan, palette[image->fg_color] | mask); mask 46 drivers/gpu/drm/nouveau/nvkm/core/enum.c if (value & bf->mask) { mask 115 drivers/gpu/drm/nouveau/nvkm/core/mm.c u32 mask = align - 1; mask 137 drivers/gpu/drm/nouveau/nvkm/core/mm.c s = (s + mask) & ~mask; mask 138 drivers/gpu/drm/nouveau/nvkm/core/mm.c e &= ~mask; mask 190 drivers/gpu/drm/nouveau/nvkm/core/mm.c u32 mask = align - 1; mask 213 drivers/gpu/drm/nouveau/nvkm/core/mm.c s = (s + mask) & ~mask; mask 219 drivers/gpu/drm/nouveau/nvkm/core/mm.c s = (e - a) & ~mask; mask 64 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 mask = nvkm_rd32(device, 0x104904 + base); mask 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c u32 intr = nvkm_rd32(device, 0x104908 + base) & mask; mask 65 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 mask = nvkm_rd32(device, 0x10440c + base); mask 66 drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; mask 351 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c u64 mask = (1ULL << NVKM_ENGINE_DMAOBJ) | mask 358 drivers/gpu/drm/nouveau/nvkm/engine/device/user.c for (; i = __ffs64(mask), mask && !sclass; mask &= ~(1ULL << i)) { mask 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c notify->types = req->v0.mask; mask 55 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c const u32 mask = 0x00000001 << chan->chid.user; mask 57 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c nvkm_mask(device, 0x610090, mask, 0x00000000); mask 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c nvkm_mask(device, 0x6100a0, mask, 0x00000000); mask 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/changf119.c nvkm_mask(device, 0x6100a0, mask, mask); mask 171 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c const u32 mask = 0x00010001 << chan->chid.user; mask 173 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_mask(device, 0x610028, mask, data); mask 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c CONN_DBG(conn, "HPD: %d", line->mask); mask 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c rep.mask = NVIF_NOTIFY_CONN_V0_UNPLUG; mask 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c rep.mask = NVIF_NOTIFY_CONN_V0_PLUG; mask 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep)); mask 110 drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c .mask = NVKM_GPIO_TOGGLED, mask 158 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c const u32 mask = 0x00000001; mask 159 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c const u32 data = en ? mask : 0; mask 160 drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c nvkm_mask(device, 0x611dac, mask, data); mask 43 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c const u32 mask = 0x00010000 << chan->head; mask 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c const u32 data = en ? mask : 0; mask 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgv100.c nvkm_mask(device, 0x611dac, mask, data); mask 544 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c OUTP_DBG(&dp->outp, "HPD: %d", line->mask); mask 545 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (line->mask & NVKM_I2C_IRQ) { mask 548 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c rep.mask |= NVIF_NOTIFY_CONN_V0_IRQ; mask 553 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (line->mask & NVKM_I2C_UNPLUG) mask 554 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG; mask 555 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (line->mask & NVKM_I2C_PLUG) mask 556 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG; mask 558 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c nvkm_event_send(&disp->hpd, rep.mask, conn->index, &rep, sizeof(rep)); mask 662 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG | mask 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 mask[4]; mask 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); mask 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c HEAD_DBG(head, "%08x", mask[head->id]); mask 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(mask[head->id] & 0x00001000)) mask 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(mask[head->id] & 0x00001000)) mask 66 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(mask[head->id] & 0x00010000)) mask 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(mask[head->id] & 0x00001000)) mask 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (!(mask[head->id] & 0x00001000)) mask 166 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c u32 mask = 0x01000000 << head->id; mask 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c if (mask & intr) { mask 48 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c u32 mask[4]; mask 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); mask 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c HEAD_DBG(head, "%08x", mask[head->id]); mask 60 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(mask[head->id] & 0x00001000)) mask 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(mask[head->id] & 0x00001000)) mask 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(mask[head->id] & 0x00010000)) mask 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(mask[head->id] & 0x00001000)) mask 85 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if (!(mask[head->id] & 0x00001000)) mask 175 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long mask; mask 184 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if ((mask = (stat & 0x00ff0000) >> 16)) { mask 185 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(head, &mask, disp->wndw.nr) { mask 269 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c unsigned long mask; mask 272 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c if ((mask = (stat & 0x000000ff))) { mask 273 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c for_each_set_bit(head, &mask, 8) { mask 387 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | mask 392 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ mask 396 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ mask 46 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c u32 mask = 0x80000001; mask 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c mask |= 0x00000002; mask 53 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf119.c nvkm_mask(device, 0x10ec10 + ior->id * 0x030, mask, data); mask 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c u32 mask = 0x80000001; mask 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c mask |= 0x00000002; mask 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data); mask 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wndw.nr = func->wndw.cnt(&disp->base, &disp->wndw.mask); mask 93 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->wndw.nr, disp->wndw.mask); mask 96 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->head.nr = func->head.cnt(&disp->base, &disp->head.mask); mask 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->head.nr, disp->head.mask); mask 99 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->head.mask, disp->head.nr) { mask 106 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->dac.nr = func->dac.cnt(&disp->base, &disp->dac.mask); mask 108 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->dac.nr, disp->dac.mask); mask 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->dac.mask, disp->dac.nr) { mask 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr = func->pior.cnt(&disp->base, &disp->pior.mask); mask 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr, disp->pior.mask); mask 120 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->pior.mask, disp->pior.nr) { mask 127 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr = func->sor.cnt(&disp->base, &disp->sor.mask); mask 129 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->sor.nr, disp->sor.mask); mask 130 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->sor.mask, disp->sor.nr) { mask 21 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h unsigned long mask; mask 26 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h unsigned long mask; mask 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h unsigned long mask; mask 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h int (*cnt)(struct nvkm_disp *, unsigned long *mask); mask 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c u16 type, mask = 0; mask 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c mask = args->v1.hashm; mask 68 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c hidx = ffs((mask >> 8) & 0x0f) - 1; mask 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c if (mask) { mask 78 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c (temp->info.hashm & mask) == mask) { mask 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c u32 mask = 0, i; mask 92 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c mask |= 1 << sor->func->dp.lanes[i]; mask 94 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask); mask 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c const u32 mask = 0x8000000d; mask 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c nvkm_mask(device, 0x616618 + hoff, mask, data); mask 32 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c const u32 mask = 0x8000000d; mask 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c nvkm_mask(device, 0x61c1e0 + soff, mask, data); mask 49 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c const u32 mask = 0x8000000d; mask 50 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c nvkm_mask(device, 0x616560 + hoff, mask, data); mask 109 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | mask 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ mask 118 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ mask 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c const u32 mask = 0x00000001 << chan->head; mask 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c const u32 data = en ? mask : 0; mask 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c nvkm_mask(device, 0x611da8, mask, data); mask 65 drivers/gpu/drm/nouveau/nvkm/engine/disp/wimmgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) mask 134 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c const u32 mask = 0x00000001 << chan->head; mask 135 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c const u32 data = en ? mask : 0; mask 136 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c nvkm_mask(device, 0x611da4, mask, data); mask 167 drivers/gpu/drm/nouveau/nvkm/engine/disp/wndwgv100.c if (!(disp->wndw.mask & BIT(args->v0.index))) mask 366 drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c bitmap_clear(fifo->mask, 0, fifo->nr); mask 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c u64 mask = chan->engines; mask 211 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c for (; c = 0, i = __ffs64(mask), mask; mask &= ~(1ULL << i)) { mask 322 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c __clear_bit(chan->chid, fifo->mask); mask 406 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c chan->chid = find_first_zero_bit(fifo->mask, NVKM_FIFO_CHID_NR); mask 412 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c __set_bit(chan->chid, fifo->mask); mask 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 mask = fifo->base.nr - 1; mask 91 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask; mask 115 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask); mask 132 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 mask = 1 << chan->base.chid; mask 135 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); mask 152 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u64 mask, todo; mask 155 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mask = fifo->recover.mask; mask 156 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c fifo->recover.mask = 0ULL; mask 159 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) mask 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) { mask 192 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c fifo->recover.mask |= 1ULL << engine->subdev.index; mask 490 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x0025a4); mask 491 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c while (mask) { mask 492 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 unit = __ffs(mask); mask 494 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mask &= ~(1 << unit); mask 504 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x002140); mask 505 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 stat = nvkm_rd32(device, 0x002100) & mask; mask 535 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x00259c); mask 536 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c while (mask) { mask 537 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 unit = __ffs(mask); mask 540 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mask &= ~(1 << unit); mask 546 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 mask = nvkm_rd32(device, 0x0025a0); mask 547 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c while (mask) { mask 548 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c u32 unit = __ffs(mask); mask 551 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c mask &= ~(1 << unit); mask 17 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h u64 mask; mask 688 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000)); mask 689 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask; mask 737 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000)); mask 738 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask; mask 757 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x002a00); mask 758 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c while (mask) { mask 759 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c int runl = __ffs(mask); mask 762 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mask &= ~(1 << runl); mask 778 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x002140); mask 779 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 stat = nvkm_rd32(device, 0x002100) & mask; mask 824 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x00259c); mask 825 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c while (mask) { mask 826 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 unit = __ffs(mask); mask 829 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mask &= ~(1 << unit); mask 835 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 mask = nvkm_rd32(device, 0x0025a0); mask 836 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c while (mask) { mask 837 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c u32 unit = __ffs(mask); mask 841 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c mask &= ~(1 << unit); mask 42 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c const u32 mask = ce ? 0x00020000 : 0x00010000; mask 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c const u32 data = valid ? mask : 0x00000000; mask 55 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_mo32(chan->base.inst, 0x0ac, mask, data); mask 113 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c const u32 mask = 0x0000000f << (subc * 4); mask 119 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_wr32(device, 0x003280, (engine &= ~mask)); mask 126 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c if (!(engine & mask) && sw) mask 245 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); mask 246 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; mask 344 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c set_bit(nr - 1, fifo->base.mask); /* inactive channel */ mask 123 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c set_bit(0, fifo->base.mask); /* PIO channel */ mask 124 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c set_bit(127, fifo->base.mask); /* inactive channel */ mask 86 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c const u32 mask = (1 << fifo->pbdma_nr) - 1; mask 88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask); mask 181 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 mask = 0x00000010, data = on ? mask : 0x00000000; mask 182 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_mask(device, 0x40988c, mask, data); mask 184 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_mask(device, 0x41a88c, mask, data); mask 186 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_mask(device, 0x408a14, mask, data); mask 100 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c u8 mask = 0x00; mask 106 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c mask |= (1 << i); mask 110 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_snprintbf(msg, sizeof(msg), units, mask); mask 1335 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mask = 0x00010000 << tpc; mask 1336 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (stat & mask) { mask 1338 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); mask 1339 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c stat &= ~mask; mask 1444 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mask = 0x00000001 << gpc; mask 1445 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (stat & mask) { mask 1447 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x400118, mask); mask 1448 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c stat &= ~mask; mask 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c u32 mask = 0, data, gpc; mask 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c mask |= data << (gpc * 4); mask 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c nvkm_wr32(device, 0x4181d0, mask); mask 445 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_set_ctx1(struct nvkm_device *device, u32 inst, u32 mask, u32 value) mask 451 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c tmp &= ~mask; mask 460 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_set_ctx_val(struct nvkm_device *device, u32 inst, u32 mask, u32 value) mask 470 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c tmp &= ~mask; mask 1215 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c u32 mask = 0xffffffff; mask 1218 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; mask 1221 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask)) mask 136 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c u32 mask, value; mask 151 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask = value = 0x00000000; mask 153 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask = value = 0x80000000; mask 154 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask |= (src->mask << src->shift); mask 158 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_mask(device, src->addr, mask, value); mask 161 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src->addr, mask, value); mask 175 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c u32 mask; mask 190 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask = 0x00000000; mask 192 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask = 0x80000000; mask 193 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask |= (src->mask << src->shift); mask 196 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_mask(device, src->addr, mask, 0); mask 198 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src->addr, mask); mask 574 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c args->v0.mask = src->mask; mask 739 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c src->mask = smux->mask; mask 766 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c nvkm_perfdom_new(struct nvkm_pm *pm, const char *name, u32 mask, mask 775 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c for (i = 0; i == 0 || mask; i++) { mask 777 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (i && !(mask & (1 << i))) mask 787 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c if (mask) { mask 816 drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c mask &= ~(1 << i); mask 193 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c u32 mask; mask 210 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask = (1 << nvkm_rd32(device, 0x022430)) - 1; mask 211 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022504); mask 212 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022584); mask 214 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c ret = nvkm_perfdom_new(pm, "gpc", mask, 0x180000, mask 220 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask = (1 << nvkm_rd32(device, 0x022438)) - 1; mask 221 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x022548); mask 222 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c mask &= ~nvkm_rd32(device, 0x0225c8); mask 224 drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.c ret = nvkm_perfdom_new(pm, "part", mask, 0x1a0000, mask 25 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h u32 mask; mask 41 drivers/gpu/drm/nouveau/nvkm/engine/pm/priv.h u32 mask; mask 132 drivers/gpu/drm/nouveau/nvkm/falcon/base.c nvkm_falcon_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) mask 134 drivers/gpu/drm/nouveau/nvkm/falcon/base.c return falcon->func->clear_interrupt(falcon, mask); mask 305 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) mask 311 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c nvkm_falcon_mask(falcon, 0x004, mask, mask); mask 313 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0); mask 122 drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c u32 mask = (1ULL << M0209E.bits) - 1; mask 127 drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.c info->data[i] = info->data[i] & mask; mask 197 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c dcb_outp_match(struct nvkm_bios *bios, u16 type, u16 mask, mask 203 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c if ((dcb_outp_hashm(outp) & mask) == mask) mask 102 drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c info->mask = nvbios_rd32(bios, data + 0x02); mask 104 drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c info->mask |= 0x00c0; mask 116 drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c nvbios_outp_match(struct nvkm_bios *bios, u16 type, u16 mask, mask 122 drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.c if ((info->mask & mask) == mask) mask 99 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c info->mask = nvbios_rd16(bios, data + 0x02); mask 102 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c info->mask |= 0x00c0; /* match any link */ mask 138 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c nvbios_dpout_match(struct nvkm_bios *bios, u16 type, u16 mask, mask 145 drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c if ((info->mask & mask) == mask) mask 201 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) mask 207 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c nvkm_wr32(device, reg, (tmp & ~mask) | val); mask 502 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3); mask 505 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c cond, port, index, mask, value); mask 506 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c return (init_rdvgai(init, port, index) & mask) == value; mask 519 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3); mask 524 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; mask 626 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 4); mask 634 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift); mask 637 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c conf = (init_rdvgai(init, port, index) & mask) >> shift; mask 689 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 4); mask 698 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift, iofc); mask 701 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c conf = (init_rdvgai(init, port, index) & mask) >> shift; mask 748 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 10); mask 753 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", mask 757 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c data = init_rdvgai(init, port, index) & mask; mask 890 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 5); mask 892 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); mask 895 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, mask, 0); mask 907 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 5); mask 909 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); mask 912 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, 0, mask); mask 925 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 9); mask 930 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); mask 941 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, creg, ~mask, data | iaddr); mask 955 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 4); mask 963 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c reg, port, index, mask, shift); mask 966 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c conf = (init_rdvgai(init, port, index) & mask) >> shift; mask 1014 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 1); mask 1018 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); mask 1024 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wri2cr(init, index, addr, reg, (val & mask) | data); mask 1098 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 3); mask 1103 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c tmds, addr, mask, data); mask 1110 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); mask 1180 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 2); mask 1184 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); mask 1187 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c val = init_rdvgai(init, 0x03d4, addr) & mask; mask 1394 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 4); mask 1399 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index, addr, reg, mask, data); mask 1404 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if ((value & mask) != data) mask 1627 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd16(bios, init->offset + 3); mask 1631 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); mask 1654 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c value = init_rdport(init, port) & mask; mask 1693 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 1); mask 1697 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); mask 1700 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if ((init_rd32(init, 0x100000) & mask) != value) mask 1713 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 5); mask 1716 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); mask 1719 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_mask(init, reg, ~mask, data); mask 1766 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 1); mask 1769 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); mask 1772 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if ((init_rd32(init, 0x101000) & mask) != value) mask 1858 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 4); mask 1863 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c port, index, mask, data); mask 1866 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c value = init_rdvgai(init, port, index) & mask; mask 2089 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u32 mask = nvbios_rd32(bios, init->offset + 5); mask 2093 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); mask 2097 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c data = (data & mask) | ((data + add) & ~mask); mask 2116 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 0); mask 2118 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); mask 2119 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c mask = init_rdauxr(init, addr) & mask; mask 2120 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c init_wrauxr(init, addr, mask | data); mask 2159 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c u8 mask = nvbios_rd08(bios, init->offset + 5); mask 2165 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index, addr, reglo, reghi, mask, data); mask 2179 drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c if (ret == 2 && ((o[0] & mask) == data)) mask 17 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h u32 mask; mask 22 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_stride(u32 addr, u32 stride, u32 mask) mask 29 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h .mask = mask, mask 42 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h .mask = 0x3, mask 55 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h .mask = 0x1, mask 97 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h u32 mask, off = 0; mask 102 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { mask 103 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h if (mask & 1) mask 117 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) mask 120 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h if (temp != ((temp & ~mask) | data) || reg->force) mask 121 drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h hwsq_wr32(ram, reg, (temp & ~mask) | data); mask 452 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 mask; mask 467 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c if (!(stage[i].mask & (1 << j))) mask 37 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); mask 51 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c nvkm_mask(device, NV04_PFB_CFG0, 0, mask); mask 60 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.c nvkm_mask(device, NV04_PFB_CFG0, mask, 0); mask 18 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h u32 mask; mask 23 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_stride(u32 addr, u32 stride, u32 mask) mask 29 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h .mask = mask, mask 41 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h .mask = 0x3, mask 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h .mask = 0x1, mask 93 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h unsigned int mask, off = 0; mask 98 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { mask 99 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h if (mask & 1) mask 112 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) mask 115 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h if (temp != ((temp & ~mask) | data) || reg->force) { mask 116 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_wr32(ram, reg, (temp & ~mask) | data); mask 123 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) mask 125 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h nvkm_memx_wait(ram->memx, addr, mask, data, nsec); mask 113 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c u32 mask = nvkm_rd32(device, 0x022554); mask 120 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c if (mask & (1 << i)) mask 141 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) mask 146 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f910, mask, data); mask 147 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f914, mask, data); mask 236 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 mask = _mask | _copy; mask 243 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 next = (prev & ~mask) | data; mask 258 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 mask, data; mask 304 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x800f07e0; mask 327 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x03000000; mask 329 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00002000; mask 331 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00004000; mask 333 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000003; mask 335 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x34000000; mask 337 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x40000000; mask 339 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f824, mask, data); mask 420 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x00070000; mask 432 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f824, mask, data); mask 473 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = mask = 0x00000000; mask 477 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x01000000; mask 479 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f200, mask, data); mask 481 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = mask = 0x00000000; mask 484 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000300; mask 489 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x70000000; mask 491 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f604, mask, data); mask 493 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = mask = 0x00000000; mask 496 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x70000000; mask 501 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000100; mask 503 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f614, mask, data); mask 505 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = mask = 0x00000000; mask 508 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x70000000; mask 513 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000100; mask 515 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f610, mask, data); mask 517 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x33f00000; mask 529 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000020; mask 532 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000004; mask 535 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x40000020; mask 539 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f808, mask, data); mask 543 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c data = mask = 0x00000000; mask 546 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000003; mask 551 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000004; mask 554 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { mask 709 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 mask, data; mask 749 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x00010000; mask 753 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x800807e0; mask 771 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x03000000; mask 773 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00002000; mask 775 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00004000; mask 777 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000003; mask 779 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x14000000; mask 780 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f824, mask, data); mask 833 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x00010000; mask 845 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f824, mask, data); mask 867 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask = 0x33f00000; mask 879 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000020; mask 882 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x08000004; mask 886 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x44000020; mask 890 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c ram_mask(fuc, 0x10f808, mask, data); mask 1160 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u32 mask, data; mask 1171 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { mask 1173 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x001ff000; mask 1177 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x000001ff; mask 1179 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f468, mask, data); mask 1181 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { mask 1183 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000001; mask 1185 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f420, mask, data); mask 1187 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { mask 1189 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000001; mask 1191 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f430, mask, data); mask 1193 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { mask 1195 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x0000001f; mask 1197 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f400, mask, data); mask 1199 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { mask 1201 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000200; mask 1203 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f410, mask, data); mask 1205 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0d) { mask 1207 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00ff0000; mask 1211 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x0000ff00; mask 1213 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f440, mask, data); mask 1215 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if (mask = 0, data = 0, ram->diff.rammap_11_0e) { mask 1217 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x0000ff00; mask 1221 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000080; mask 1225 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c mask |= 0x00000020; mask 1227 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c nvkm_mask(device, 0x10f444, mask, data); mask 1259 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c u16 mask; mask 1327 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c train->mask |= 1 << M0205E.type; mask 1338 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c if ((train->mask & 0x03d3) != 0x03d3) { mask 133 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c notify->types = req->mask; mask 157 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c .mask = (NVKM_GPIO_HI * !!(hi & (1 << i))) | mask 160 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c nvkm_event_send(&gpio->event, rep.mask, i, &rep, sizeof(rep)); mask 168 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c u32 mask = (1ULL << gpio->func->lines) - 1; mask 170 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c gpio->func->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0); mask 171 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c gpio->func->intr_stat(gpio, &mask, &mask); mask 41 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c g94_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) mask 47 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c inte0 = (inte0 & ~(mask << 16)) | (data << 16); mask 49 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); mask 50 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c mask >>= 16; mask 53 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c inte1 = (inte1 & ~(mask << 16)) | (data << 16); mask 55 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.c inte1 = (inte1 & ~mask) | data; mask 41 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c gk104_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) mask 47 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c inte0 = (inte0 & ~(mask << 16)) | (data << 16); mask 49 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); mask 50 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c mask >>= 16; mask 53 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c inte1 = (inte1 & ~(mask << 16)) | (data << 16); mask 55 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.c inte1 = (inte1 & ~mask) | data; mask 55 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c u32 reg, mask, data; mask 60 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c mask = 0x00000011; mask 66 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c mask = 0x00000003; mask 72 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c mask = 0x00000003; mask 78 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c nvkm_mask(device, reg, mask << line, data << line); mask 94 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c nv10_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) mask 99 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c inte = (inte & ~(mask << 16)) | (data << 16); mask 101 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.c inte = (inte & ~mask) | data; mask 107 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data) mask 112 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c inte = (inte & ~(mask << 16)) | (data << 16); mask 114 drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c inte = (inte & ~mask) | data; mask 114 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c notify->types = req->mask; mask 143 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c u32 mask = 0; mask 144 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if (hi & aux->intr) mask |= NVKM_I2C_PLUG; mask 145 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if (lo & aux->intr) mask |= NVKM_I2C_UNPLUG; mask 146 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if (rq & aux->intr) mask |= NVKM_I2C_IRQ; mask 147 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if (tx & aux->intr) mask |= NVKM_I2C_DONE; mask 148 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if (mask) { mask 150 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c .mask = mask, mask 152 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c nvkm_event_send(&i2c->event, rep.mask, aux->id, mask 165 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c u32 mask; mask 175 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c if ((mask = (1 << i2c->func->aux) - 1), i2c->func->aux_stat) { mask 176 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c i2c->func->aux_mask(i2c, NVKM_I2C_ANY, mask, 0); mask 177 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c i2c->func->aux_stat(i2c, &mask, &mask, &mask, &mask); mask 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c g94_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) mask 48 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.c if (mask & (1 << i)) { mask 43 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c gk104_aux_mask(struct nvkm_i2c *i2c, u32 type, u32 mask, u32 data) mask 48 drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.c if (mask & (1 << i)) { mask 114 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 mask; mask 116 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c mask = nvkm_rd32(device, 0x00017c); mask 117 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c while (mask) { mask 118 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c u32 s, c = __ffs(mask); mask 121 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c mask &= ~(1 << c); mask 212 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c const u32 mask = nvkm_rd32(device, 0x022554); mask 217 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c if (!(mask & (1 << i))) mask 93 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 mask; mask 95 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c mask = nvkm_rd32(device, 0x00017c); mask 96 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c while (mask) { mask 97 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c u32 s, c = __ffs(mask); mask 100 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c mask &= ~(1 << c); mask 109 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c const u32 mask = nvkm_rd32(device, 0x021c14); mask 114 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c if (!(mask & (1 << i))) mask 30 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c u32 mask; mask 32 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c mask = nvkm_rd32(device, 0x0001c0); mask 33 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c while (mask) { mask 34 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c u32 s, c = __ffs(mask); mask 37 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c mask &= ~(1 << c); mask 43 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c u32 mask = nvkm_top_intr_mask(device, devidx); mask 44 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c for (map = mc->func->intr; !mask && map->stat; map++) { mask 46 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c mask = map->stat; mask 48 drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c mc->func->intr_mask(mc, mask, en ? mask : 0); mask 89 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c gf100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat) mask 92 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c nvkm_mask(device, 0x000640, mask, stat); mask 93 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c nvkm_mask(device, 0x000644, mask, stat); mask 31 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c u32 mask; mask 38 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c u32 mask = mc->intr ? mc->mask : 0, i; mask 40 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c nvkm_wr32(device, 0x000180 + (i * 0x04), ~mask); mask 41 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c nvkm_wr32(device, 0x000160 + (i * 0x04), mask); mask 68 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr) mask 73 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c mc->mask = (mc->mask & ~mask) | intr; mask 120 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c mc->mask = 0x7fffffff; mask 57 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c gt215_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 stat) mask 59 drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.c nvkm_mask(mc->subdev.device, 0x000640, mask, stat); mask 26 drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h void (*intr_mask)(struct nvkm_mc *, u32 mask, u32 stat); mask 37 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c u16 mask; mask 55 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c if (ptp->free == ptp->mask) { mask 91 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c ptp->mask = (1 << slot) - 1; mask 92 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c ptp->free = ptp->mask; mask 33 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c u64 data[2], mask; mask 41 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c mask = BIT_ULL(0); mask 46 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c if (mask & BIT_ULL(i)) { mask 56 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c nvkm_wo32(inst, 0x298, lower_32_bits(mask)); mask 57 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.c nvkm_wo32(inst, 0x29c, upper_32_bits(mask)); mask 50 drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 value) mask 53 drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c pci->func->wr32(pci, addr, (data & ~mask) | value); mask 108 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c u32 addr, u32 mask, u32 data, u32 nsec) mask 111 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c addr, mask, data, nsec); mask 112 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec }); mask 110 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c u32 mask = enable ? 0x80000000 : 0x00000000; mask 111 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c if (line == 2) nvkm_mask(device, 0x0010f0, 0x80000000, mask); mask 112 drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c else if (line == 9) nvkm_mask(device, 0x0015f4, 0x80000000, mask); mask 356 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask); mask 3186 drivers/gpu/drm/omapdrm/dss/dispc.c u32 mask, val; mask 3188 drivers/gpu/drm/omapdrm/dss/dispc.c mask = (1 << 0) | (1 << 3) | (1 << 6); mask 3191 drivers/gpu/drm/omapdrm/dss/dispc.c mask <<= 16 + shifts[channel]; mask 3195 drivers/gpu/drm/omapdrm/dss/dispc.c mask, val); mask 3759 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) mask 3761 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); mask 3764 drivers/gpu/drm/omapdrm/dss/dispc.c static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) mask 3769 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); mask 3771 drivers/gpu/drm/omapdrm/dss/dispc.c dispc_write_reg(dispc, DISPC_IRQENABLE, mask); mask 204 drivers/gpu/drm/omapdrm/dss/dsi.c typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); mask 242 drivers/gpu/drm/omapdrm/dss/dsi.c u32 mask; mask 483 drivers/gpu/drm/omapdrm/dss/dsi.c static void dsi_completion_handler(void *data, u32 mask) mask 748 drivers/gpu/drm/omapdrm/dss/dsi.c if (isr_data->isr && isr_data->mask & irqstatus) mask 852 drivers/gpu/drm/omapdrm/dss/dsi.c u32 mask; mask 856 drivers/gpu/drm/omapdrm/dss/dsi.c mask = default_mask; mask 864 drivers/gpu/drm/omapdrm/dss/dsi.c mask |= isr_data->mask; mask 869 drivers/gpu/drm/omapdrm/dss/dsi.c dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); mask 870 drivers/gpu/drm/omapdrm/dss/dsi.c dsi_write_reg(dsi, enable_reg, mask); mask 880 drivers/gpu/drm/omapdrm/dss/dsi.c u32 mask = DSI_IRQ_ERROR_MASK; mask 882 drivers/gpu/drm/omapdrm/dss/dsi.c mask |= DSI_IRQ_TE_TRIGGER; mask 885 drivers/gpu/drm/omapdrm/dss/dsi.c ARRAY_SIZE(dsi->isr_tables.isr_table), mask, mask 924 drivers/gpu/drm/omapdrm/dss/dsi.c static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, mask 939 drivers/gpu/drm/omapdrm/dss/dsi.c isr_data->mask == mask) { mask 953 drivers/gpu/drm/omapdrm/dss/dsi.c isr_data->mask = mask; mask 958 drivers/gpu/drm/omapdrm/dss/dsi.c static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, mask 967 drivers/gpu/drm/omapdrm/dss/dsi.c isr_data->mask != mask) mask 972 drivers/gpu/drm/omapdrm/dss/dsi.c isr_data->mask = 0; mask 981 drivers/gpu/drm/omapdrm/dss/dsi.c void *arg, u32 mask) mask 988 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, mask 1000 drivers/gpu/drm/omapdrm/dss/dsi.c void *arg, u32 mask) mask 1007 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, mask 1019 drivers/gpu/drm/omapdrm/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1026 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, mask 1039 drivers/gpu/drm/omapdrm/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1046 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, mask 1059 drivers/gpu/drm/omapdrm/dss/dsi.c void *arg, u32 mask) mask 1066 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, mask 1078 drivers/gpu/drm/omapdrm/dss/dsi.c void *arg, u32 mask) mask 1085 drivers/gpu/drm/omapdrm/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, mask 1920 drivers/gpu/drm/omapdrm/dss/dsi.c unsigned int mask = 0; mask 1925 drivers/gpu/drm/omapdrm/dss/dsi.c mask |= 1 << i; mask 1928 drivers/gpu/drm/omapdrm/dss/dsi.c return mask; mask 2224 drivers/gpu/drm/omapdrm/dss/dsi.c static void dsi_packet_sent_handler_vp(void *data, u32 mask) mask 2274 drivers/gpu/drm/omapdrm/dss/dsi.c static void dsi_packet_sent_handler_l4(void *data, u32 mask) mask 3040 drivers/gpu/drm/omapdrm/dss/dsi.c unsigned int mask; mask 3085 drivers/gpu/drm/omapdrm/dss/dsi.c mask = 0; mask 3090 drivers/gpu/drm/omapdrm/dss/dsi.c mask |= 1 << i; mask 3094 drivers/gpu/drm/omapdrm/dss/dsi.c REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5); mask 300 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); mask 301 drivers/gpu/drm/omapdrm/dss/hdmi.h void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); mask 56 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) mask 58 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); mask 61 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) mask 63 drivers/gpu/drm/omapdrm/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); mask 493 drivers/gpu/drm/omapdrm/dss/omapdss.h typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); mask 494 drivers/gpu/drm/omapdrm/dss/omapdss.h int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); mask 495 drivers/gpu/drm/omapdrm/dss/omapdss.h int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); mask 561 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask); mask 562 drivers/gpu/drm/omapdrm/dss/omapdss.h void (*write_irqenable)(struct dispc_device *dispc, u32 mask); mask 189 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dma_cap_mask_t mask; mask 198 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dma_cap_zero(mask); mask 199 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dma_cap_set(DMA_MEMCPY, mask); mask 201 drivers/gpu/drm/omapdrm/omap_dmm_tiler.c dmm->wa_dma_chan = dma_request_channel(mask, NULL, NULL); mask 164 drivers/gpu/drm/omapdrm/omap_irq.c u32 mask; mask 172 drivers/gpu/drm/omapdrm/omap_irq.c const u32 mask = DISPC_IRQ_GFX_FIFO_UNDERFLOW mask 179 drivers/gpu/drm/omapdrm/omap_irq.c irqstatus &= priv->irq_mask & mask; mask 191 drivers/gpu/drm/omapdrm/omap_irq.c if (sources[i].mask & irqstatus) mask 28 drivers/gpu/drm/omapdrm/tcm-sita.c static unsigned long mask[8]; mask 127 drivers/gpu/drm/omapdrm/tcm-sita.c bitmap_clear(mask, 0, slot_stride); mask 128 drivers/gpu/drm/omapdrm/tcm-sita.c bitmap_set(mask, (*pos % BITS_PER_LONG), w); mask 136 drivers/gpu/drm/omapdrm/tcm-sita.c if (bitmap_intersects(&map[index], mask, mask 459 drivers/gpu/drm/panfrost/panfrost_job.c u32 mask = MK_JS_MASK(j); mask 461 drivers/gpu/drm/panfrost/panfrost_job.c if (!(status & mask)) mask 464 drivers/gpu/drm/panfrost/panfrost_job.c job_write(pfdev, JOB_INT_CLEAR, mask); mask 496 drivers/gpu/drm/panfrost/panfrost_job.c status &= ~mask; mask 584 drivers/gpu/drm/panfrost/panfrost_mmu.c u32 mask = BIT(i) | BIT(i + 16); mask 591 drivers/gpu/drm/panfrost/panfrost_mmu.c if (!(status & mask)) mask 605 drivers/gpu/drm/panfrost/panfrost_mmu.c if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) mask 626 drivers/gpu/drm/panfrost/panfrost_mmu.c mmu_write(pfdev, MMU_INT_CLEAR, mask); mask 628 drivers/gpu/drm/panfrost/panfrost_mmu.c status &= ~mask; mask 432 drivers/gpu/drm/pl111/pl111_drv.c .mask = 0x000fffff, mask 437 drivers/gpu/drm/pl111/pl111_drv.c .mask = 0x00fffffe, mask 442 drivers/gpu/drm/pl111/pl111_drv.c .mask = 0x000fffff, mask 521 drivers/gpu/drm/qxl/qxl_dev.h struct qxl_q_mask mask; mask 530 drivers/gpu/drm/qxl/qxl_dev.h struct qxl_q_mask mask; mask 538 drivers/gpu/drm/qxl/qxl_dev.h struct qxl_q_mask mask; mask 567 drivers/gpu/drm/qxl/qxl_dev.h struct qxl_q_mask mask; mask 598 drivers/gpu/drm/qxl/qxl_dev.h struct qxl_q_mask mask; mask 673 drivers/gpu/drm/qxl/qxl_dev.h QXLPHYSICAL mask; /* May be NULL */ mask 229 drivers/gpu/drm/qxl/qxl_draw.c drawable->u.copy.mask.flags = 0; mask 230 drivers/gpu/drm/qxl/qxl_draw.c drawable->u.copy.mask.pos.x = 0; mask 231 drivers/gpu/drm/qxl/qxl_draw.c drawable->u.copy.mask.pos.y = 0; mask 232 drivers/gpu/drm/qxl/qxl_draw.c drawable->u.copy.mask.bitmap = 0; mask 105 drivers/gpu/drm/r128/r128_ioc32.c u32 mask; mask 122 drivers/gpu/drm/r128/r128_ioc32.c depth.mask = compat_ptr(depth32.mask); mask 128 drivers/gpu/drm/r128/r128_ioc32.c u32 mask; mask 140 drivers/gpu/drm/r128/r128_ioc32.c stipple.mask = compat_ptr(stipple32.mask); mask 896 drivers/gpu/drm/r128/r128_state.c u8 *mask; mask 916 drivers/gpu/drm/r128/r128_state.c if (depth->mask) { mask 917 drivers/gpu/drm/r128/r128_state.c mask = memdup_user(depth->mask, mask_size); mask 918 drivers/gpu/drm/r128/r128_state.c if (IS_ERR(mask)) { mask 920 drivers/gpu/drm/r128/r128_state.c return PTR_ERR(mask); mask 924 drivers/gpu/drm/r128/r128_state.c if (mask[i]) { mask 946 drivers/gpu/drm/r128/r128_state.c kfree(mask); mask 981 drivers/gpu/drm/r128/r128_state.c u8 *mask; mask 1008 drivers/gpu/drm/r128/r128_state.c if (depth->mask) { mask 1010 drivers/gpu/drm/r128/r128_state.c mask = memdup_user(depth->mask, mask_size); mask 1011 drivers/gpu/drm/r128/r128_state.c if (IS_ERR(mask)) { mask 1015 drivers/gpu/drm/r128/r128_state.c return PTR_ERR(mask); mask 1019 drivers/gpu/drm/r128/r128_state.c if (mask[i]) { mask 1041 drivers/gpu/drm/r128/r128_state.c kfree(mask); mask 1495 drivers/gpu/drm/r128/r128_state.c u32 mask[32]; mask 1501 drivers/gpu/drm/r128/r128_state.c if (copy_from_user(&mask, stipple->mask, 32 * sizeof(u32))) mask 1506 drivers/gpu/drm/r128/r128_state.c r128_cce_dispatch_stipple(dev, mask); mask 751 drivers/gpu/drm/radeon/atom.c uint32_t dst, mask, src, saved; mask 755 drivers/gpu/drm/radeon/atom.c mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); mask 756 drivers/gpu/drm/radeon/atom.c SDEBUG(" mask: 0x%08x", mask); mask 759 drivers/gpu/drm/radeon/atom.c dst &= mask; mask 580 drivers/gpu/drm/radeon/ci_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 594 drivers/gpu/drm/radeon/ci_dpm.c data &= ~config_regs->mask; mask 595 drivers/gpu/drm/radeon/ci_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 170 drivers/gpu/drm/radeon/ci_dpm.h u32 mask; mask 3065 drivers/gpu/drm/radeon/cik.c u32 i, mask = 0; mask 3068 drivers/gpu/drm/radeon/cik.c mask <<= 1; mask 3069 drivers/gpu/drm/radeon/cik.c mask |= 1; mask 3071 drivers/gpu/drm/radeon/cik.c return mask; mask 3089 drivers/gpu/drm/radeon/cik.c u32 data, mask; mask 3100 drivers/gpu/drm/radeon/cik.c mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se); mask 3102 drivers/gpu/drm/radeon/cik.c return data & mask; mask 3120 drivers/gpu/drm/radeon/cik.c u32 data, mask; mask 3136 drivers/gpu/drm/radeon/cik.c mask = 1; mask 3138 drivers/gpu/drm/radeon/cik.c if (!(disabled_rbs & mask)) mask 3139 drivers/gpu/drm/radeon/cik.c enabled_rbs |= mask; mask 3140 drivers/gpu/drm/radeon/cik.c mask <<= 1; mask 5799 drivers/gpu/drm/radeon/cik.c u32 mask; mask 5813 drivers/gpu/drm/radeon/cik.c mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY; mask 5815 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) mask 5856 drivers/gpu/drm/radeon/cik.c u32 tmp, i, mask; mask 5861 drivers/gpu/drm/radeon/cik.c mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS; mask 5863 drivers/gpu/drm/radeon/cik.c if ((RREG32(RLC_GPM_STAT) & mask) == mask) mask 6541 drivers/gpu/drm/radeon/cik.c u32 mask = 0, tmp, tmp1; mask 6555 drivers/gpu/drm/radeon/cik.c mask <<= 1; mask 6556 drivers/gpu/drm/radeon/cik.c mask |= 1; mask 6559 drivers/gpu/drm/radeon/cik.c return (~tmp) & mask; mask 6565 drivers/gpu/drm/radeon/cik.c u32 mask, counter, cu_bitmap; mask 6570 drivers/gpu/drm/radeon/cik.c mask = 1; mask 6574 drivers/gpu/drm/radeon/cik.c if (cik_get_cu_active_bitmap(rdev, i, j) & mask) { mask 6576 drivers/gpu/drm/radeon/cik.c cu_bitmap |= mask; mask 6579 drivers/gpu/drm/radeon/cik.c mask <<= 1; mask 230 drivers/gpu/drm/radeon/cik_reg.h uint32_t mask:24; mask 778 drivers/gpu/drm/radeon/cik_sdma.c u32 mask; mask 781 drivers/gpu/drm/radeon/cik_sdma.c mask = RADEON_RESET_DMA; mask 783 drivers/gpu/drm/radeon/cik_sdma.c mask = RADEON_RESET_DMA1; mask 785 drivers/gpu/drm/radeon/cik_sdma.c if (!(reset_mask & mask)) { mask 4372 drivers/gpu/drm/radeon/evergreen.c u32 mask = RLC_ENABLE; mask 4375 drivers/gpu/drm/radeon/evergreen.c mask |= GFX_POWER_GATING_ENABLE | GFX_POWER_GATING_SRC; mask 4378 drivers/gpu/drm/radeon/evergreen.c WREG32(RLC_CNTL, mask); mask 4706 drivers/gpu/drm/radeon/evergreen.c u32 mask; mask 4753 drivers/gpu/drm/radeon/evergreen.c mask = LB_D1_VBLANK_INTERRUPT; mask 4767 drivers/gpu/drm/radeon/evergreen.c mask = LB_D1_VLINE_INTERRUPT; mask 4775 drivers/gpu/drm/radeon/evergreen.c if (!(disp_int[crtc_idx] & mask)) { mask 4780 drivers/gpu/drm/radeon/evergreen.c disp_int[crtc_idx] &= ~mask; mask 4797 drivers/gpu/drm/radeon/evergreen.c mask = DC_HPD1_INTERRUPT; mask 4803 drivers/gpu/drm/radeon/evergreen.c mask = DC_HPD1_RX_INTERRUPT; mask 4813 drivers/gpu/drm/radeon/evergreen.c if (!(disp_int[hpd_idx] & mask)) mask 4816 drivers/gpu/drm/radeon/evergreen.c disp_int[hpd_idx] &= ~mask; mask 296 drivers/gpu/drm/radeon/kv_dpm.c cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 310 drivers/gpu/drm/radeon/kv_dpm.c data &= ~config_regs->mask; mask 311 drivers/gpu/drm/radeon/kv_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 1431 drivers/gpu/drm/radeon/kv_dpm.c u32 mask; mask 1440 drivers/gpu/drm/radeon/kv_dpm.c mask = 1 << pi->uvd_boot_level; mask 1442 drivers/gpu/drm/radeon/kv_dpm.c mask = 0x1f; mask 1455 drivers/gpu/drm/radeon/kv_dpm.c mask); mask 46 drivers/gpu/drm/radeon/kv_dpm.h u32 mask; mask 122 drivers/gpu/drm/radeon/kv_smc.c u32 data, original_data, addr, extra_shift, t_byte, count, mask; mask 141 drivers/gpu/drm/radeon/kv_smc.c mask = 0; mask 145 drivers/gpu/drm/radeon/kv_smc.c mask = (mask << 8) | 0xff; mask 150 drivers/gpu/drm/radeon/kv_smc.c mask <<= 8; mask 153 drivers/gpu/drm/radeon/kv_smc.c mask = (mask << 8) | 0xff; mask 158 drivers/gpu/drm/radeon/kv_smc.c data |= original_data & mask; mask 290 drivers/gpu/drm/radeon/ni_dma.c u32 mask; mask 293 drivers/gpu/drm/radeon/ni_dma.c mask = RADEON_RESET_DMA; mask 295 drivers/gpu/drm/radeon/ni_dma.c mask = RADEON_RESET_DMA1; mask 297 drivers/gpu/drm/radeon/ni_dma.c if (!(reset_mask & mask)) { mask 362 drivers/gpu/drm/radeon/r100.c tmp |= voltage->gpio.mask; mask 364 drivers/gpu/drm/radeon/r100.c tmp &= ~(voltage->gpio.mask); mask 371 drivers/gpu/drm/radeon/r100.c tmp &= ~voltage->gpio.mask; mask 373 drivers/gpu/drm/radeon/r100.c tmp |= voltage->gpio.mask; mask 504 drivers/gpu/drm/radeon/r300.c uint32_t link_width_cntl, mask; mask 516 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X0; mask 519 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X1; mask 522 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X2; mask 525 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X4; mask 528 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X8; mask 531 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X12; mask 535 drivers/gpu/drm/radeon/r300.c mask = RADEON_PCIE_LC_LINK_WIDTH_X16; mask 542 drivers/gpu/drm/radeon/r300.c (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) mask 549 drivers/gpu/drm/radeon/r300.c link_width_cntl |= mask; mask 1943 drivers/gpu/drm/radeon/r600.c u32 data = 0, mask = 1 << (max_rb_num - 1); mask 1968 drivers/gpu/drm/radeon/r600.c if (!(mask & disabled_rb_mask)) { mask 1979 drivers/gpu/drm/radeon/r600.c mask >>= 1; mask 4403 drivers/gpu/drm/radeon/r600.c u32 link_width_cntl, mask; mask 4419 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X0; mask 4422 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X1; mask 4425 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X2; mask 4428 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X4; mask 4431 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X8; mask 4435 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X12; mask 4438 drivers/gpu/drm/radeon/r600.c mask = RADEON_PCIE_LC_LINK_WIDTH_X16; mask 4447 drivers/gpu/drm/radeon/r600.c link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; mask 522 drivers/gpu/drm/radeon/r600_dpm.c u64 mask) mask 524 drivers/gpu/drm/radeon/r600_dpm.c WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff); mask 525 drivers/gpu/drm/radeon/r600_dpm.c WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask)); mask 532 drivers/gpu/drm/radeon/r600_dpm.c u32 tmp, mask; mask 537 drivers/gpu/drm/radeon/r600_dpm.c mask = 7 << (3 * ix); mask 539 drivers/gpu/drm/radeon/r600_dpm.c tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask); mask 544 drivers/gpu/drm/radeon/r600_dpm.c u64 mask) mask 549 drivers/gpu/drm/radeon/r600_dpm.c gpio &= ~mask; mask 553 drivers/gpu/drm/radeon/r600_dpm.c gpio &= ~mask; mask 557 drivers/gpu/drm/radeon/r600_dpm.c gpio &= ~mask; mask 192 drivers/gpu/drm/radeon/r600_dpm.h u64 mask); mask 196 drivers/gpu/drm/radeon/r600_dpm.h u64 mask); mask 2542 drivers/gpu/drm/radeon/radeon.h #define WREG32_P(reg, val, mask) \ mask 2545 drivers/gpu/drm/radeon/radeon.h tmp_ &= (mask); \ mask 2546 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ mask 2551 drivers/gpu/drm/radeon/radeon.h #define WREG32_PLL_P(reg, val, mask) \ mask 2554 drivers/gpu/drm/radeon/radeon.h tmp_ &= (mask); \ mask 2555 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ mask 2558 drivers/gpu/drm/radeon/radeon.h #define WREG32_SMC_P(reg, val, mask) \ mask 2561 drivers/gpu/drm/radeon/radeon.h tmp_ &= (mask); \ mask 2562 drivers/gpu/drm/radeon/radeon.h tmp_ |= ((val) & ~(mask)); \ mask 2956 drivers/gpu/drm/radeon/radeon.h u32 reg, u32 mask, mask 162 drivers/gpu/drm/radeon/radeon_acpi.c static void radeon_atif_parse_notification(struct radeon_atif_notifications *n, u32 mask) mask 164 drivers/gpu/drm/radeon/radeon_acpi.c n->display_switch = mask & ATIF_DISPLAY_SWITCH_REQUEST_SUPPORTED; mask 165 drivers/gpu/drm/radeon/radeon_acpi.c n->expansion_mode_change = mask & ATIF_EXPANSION_MODE_CHANGE_REQUEST_SUPPORTED; mask 166 drivers/gpu/drm/radeon/radeon_acpi.c n->thermal_state = mask & ATIF_THERMAL_STATE_CHANGE_REQUEST_SUPPORTED; mask 167 drivers/gpu/drm/radeon/radeon_acpi.c n->forced_power_state = mask & ATIF_FORCED_POWER_STATE_CHANGE_REQUEST_SUPPORTED; mask 168 drivers/gpu/drm/radeon/radeon_acpi.c n->system_power_state = mask & ATIF_SYSTEM_POWER_SOURCE_CHANGE_REQUEST_SUPPORTED; mask 169 drivers/gpu/drm/radeon/radeon_acpi.c n->display_conf_change = mask & ATIF_DISPLAY_CONF_CHANGE_REQUEST_SUPPORTED; mask 170 drivers/gpu/drm/radeon/radeon_acpi.c n->px_gfx_switch = mask & ATIF_PX_GFX_SWITCH_REQUEST_SUPPORTED; mask 171 drivers/gpu/drm/radeon/radeon_acpi.c n->brightness_change = mask & ATIF_PANEL_BRIGHTNESS_CHANGE_REQUEST_SUPPORTED; mask 172 drivers/gpu/drm/radeon/radeon_acpi.c n->dgpu_display_event = mask & ATIF_DGPU_DISPLAY_EVENT_SUPPORTED; mask 185 drivers/gpu/drm/radeon/radeon_acpi.c static void radeon_atif_parse_functions(struct radeon_atif_functions *f, u32 mask) mask 187 drivers/gpu/drm/radeon/radeon_acpi.c f->system_params = mask & ATIF_GET_SYSTEM_PARAMETERS_SUPPORTED; mask 188 drivers/gpu/drm/radeon/radeon_acpi.c f->sbios_requests = mask & ATIF_GET_SYSTEM_BIOS_REQUESTS_SUPPORTED; mask 189 drivers/gpu/drm/radeon/radeon_acpi.c f->select_active_disp = mask & ATIF_SELECT_ACTIVE_DISPLAYS_SUPPORTED; mask 190 drivers/gpu/drm/radeon/radeon_acpi.c f->lid_state = mask & ATIF_GET_LID_STATE_SUPPORTED; mask 191 drivers/gpu/drm/radeon/radeon_acpi.c f->get_tv_standard = mask & ATIF_GET_TV_STANDARD_FROM_CMOS_SUPPORTED; mask 192 drivers/gpu/drm/radeon/radeon_acpi.c f->set_tv_standard = mask & ATIF_SET_TV_STANDARD_IN_CMOS_SUPPORTED; mask 193 drivers/gpu/drm/radeon/radeon_acpi.c f->get_panel_expansion_mode = mask & ATIF_GET_PANEL_EXPANSION_MODE_FROM_CMOS_SUPPORTED; mask 194 drivers/gpu/drm/radeon/radeon_acpi.c f->set_panel_expansion_mode = mask & ATIF_SET_PANEL_EXPANSION_MODE_IN_CMOS_SUPPORTED; mask 195 drivers/gpu/drm/radeon/radeon_acpi.c f->temperature_change = mask & ATIF_TEMPERATURE_CHANGE_NOTIFICATION_SUPPORTED; mask 196 drivers/gpu/drm/radeon/radeon_acpi.c f->graphics_device_types = mask & ATIF_GET_GRAPHICS_DEVICE_TYPES_SUPPORTED; mask 487 drivers/gpu/drm/radeon/radeon_acpi.c static void radeon_atcs_parse_functions(struct radeon_atcs_functions *f, u32 mask) mask 489 drivers/gpu/drm/radeon/radeon_acpi.c f->get_ext_state = mask & ATCS_GET_EXTERNAL_STATE_SUPPORTED; mask 490 drivers/gpu/drm/radeon/radeon_acpi.c f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; mask 491 drivers/gpu/drm/radeon/radeon_acpi.c f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; mask 492 drivers/gpu/drm/radeon/radeon_acpi.c f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; mask 229 drivers/gpu/drm/radeon/radeon_atombios.c gpio.mask = (1 << pin->ucGpioPinBitShift); mask 258 drivers/gpu/drm/radeon/radeon_atombios.c switch(gpio->mask) { mask 137 drivers/gpu/drm/radeon/radeon_atpx_handler.c static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mask) mask 139 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; mask 140 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; mask 141 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; mask 142 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; mask 143 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED; mask 144 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED; mask 145 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED; mask 146 drivers/gpu/drm/radeon/radeon_atpx_handler.c f->disp_detetion_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED; mask 2762 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); mask 2770 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); mask 569 drivers/gpu/drm/radeon/radeon_irq_kms.c u32 reg, u32 mask, mask 575 drivers/gpu/drm/radeon/radeon_irq_kms.c if (!!(tmp & mask) == enable) mask 580 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp |= mask); mask 583 drivers/gpu/drm/radeon/radeon_irq_kms.c WREG32(reg, tmp & ~mask); mask 303 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint32_t mask; mask 306 drivers/gpu/drm/radeon/radeon_legacy_crtc.c mask = (RADEON_CRTC2_DISP_DIS | mask 311 drivers/gpu/drm/radeon/radeon_legacy_crtc.c mask = (RADEON_CRTC_DISPLAY_DIS | mask 331 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); mask 335 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); mask 347 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); mask 351 drivers/gpu/drm/radeon/radeon_legacy_crtc.c WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); mask 502 drivers/gpu/drm/radeon/radeon_mode.h u32 mask; mask 1037 drivers/gpu/drm/radeon/radeon_uvd.c uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; mask 1038 drivers/gpu/drm/radeon/radeon_uvd.c if ((RREG32(cg_upll_func_cntl) & mask) == mask) mask 820 drivers/gpu/drm/radeon/radeon_vm.c uint64_t mask = RADEON_VM_PTE_COUNT - 1; mask 838 drivers/gpu/drm/radeon/radeon_vm.c if ((addr & ~mask) == (end & ~mask)) mask 841 drivers/gpu/drm/radeon/radeon_vm.c nptes = RADEON_VM_PTE_COUNT - (addr & mask); mask 844 drivers/gpu/drm/radeon/radeon_vm.c pte += (addr & mask) * 8; mask 234 drivers/gpu/drm/radeon/rs600.c tmp |= voltage->gpio.mask; mask 236 drivers/gpu/drm/radeon/rs600.c tmp &= ~(voltage->gpio.mask); mask 243 drivers/gpu/drm/radeon/rs600.c tmp &= ~voltage->gpio.mask; mask 245 drivers/gpu/drm/radeon/rs600.c tmp |= voltage->gpio.mask; mask 704 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 mask, set_pins; mask 709 drivers/gpu/drm/radeon/rv6xx_dpm.c &set_pins, &mask); mask 2969 drivers/gpu/drm/radeon/si.c u32 i, mask = 0; mask 2972 drivers/gpu/drm/radeon/si.c mask <<= 1; mask 2973 drivers/gpu/drm/radeon/si.c mask |= 1; mask 2975 drivers/gpu/drm/radeon/si.c return mask; mask 2980 drivers/gpu/drm/radeon/si.c u32 data, mask; mask 2991 drivers/gpu/drm/radeon/si.c mask = si_create_bitmask(cu_per_sh); mask 2993 drivers/gpu/drm/radeon/si.c return ~data & mask; mask 3001 drivers/gpu/drm/radeon/si.c u32 data, mask, active_cu; mask 3009 drivers/gpu/drm/radeon/si.c mask = 1; mask 3011 drivers/gpu/drm/radeon/si.c mask <<= k; mask 3012 drivers/gpu/drm/radeon/si.c if (active_cu & mask) { mask 3013 drivers/gpu/drm/radeon/si.c data &= ~mask; mask 3027 drivers/gpu/drm/radeon/si.c u32 data, mask; mask 3038 drivers/gpu/drm/radeon/si.c mask = si_create_bitmask(max_rb_num_per_se / sh_per_se); mask 3040 drivers/gpu/drm/radeon/si.c return data & mask; mask 3048 drivers/gpu/drm/radeon/si.c u32 data, mask; mask 3061 drivers/gpu/drm/radeon/si.c mask = 1; mask 3063 drivers/gpu/drm/radeon/si.c if (!(disabled_rbs & mask)) mask 3064 drivers/gpu/drm/radeon/si.c enabled_rbs |= mask; mask 3065 drivers/gpu/drm/radeon/si.c mask <<= 1; mask 5149 drivers/gpu/drm/radeon/si.c u32 mask; mask 5162 drivers/gpu/drm/radeon/si.c mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; mask 5164 drivers/gpu/drm/radeon/si.c if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) mask 5301 drivers/gpu/drm/radeon/si.c u32 mask = 0, tmp, tmp1; mask 5315 drivers/gpu/drm/radeon/si.c mask <<= 1; mask 5316 drivers/gpu/drm/radeon/si.c mask |= 1; mask 5319 drivers/gpu/drm/radeon/si.c return (~tmp) & mask; mask 5325 drivers/gpu/drm/radeon/si.c u32 mask, counter, cu_bitmap; mask 5330 drivers/gpu/drm/radeon/si.c mask = 1; mask 5334 drivers/gpu/drm/radeon/si.c if (si_get_cu_active_bitmap(rdev, i, j) & mask) { mask 5336 drivers/gpu/drm/radeon/si.c cu_bitmap |= mask; mask 5339 drivers/gpu/drm/radeon/si.c mask <<= 1; mask 6249 drivers/gpu/drm/radeon/si.c u32 mask; mask 6296 drivers/gpu/drm/radeon/si.c mask = LB_D1_VBLANK_INTERRUPT; mask 6310 drivers/gpu/drm/radeon/si.c mask = LB_D1_VLINE_INTERRUPT; mask 6318 drivers/gpu/drm/radeon/si.c if (!(disp_int[crtc_idx] & mask)) { mask 6323 drivers/gpu/drm/radeon/si.c disp_int[crtc_idx] &= ~mask; mask 6340 drivers/gpu/drm/radeon/si.c mask = DC_HPD1_INTERRUPT; mask 6346 drivers/gpu/drm/radeon/si.c mask = DC_HPD1_RX_INTERRUPT; mask 6356 drivers/gpu/drm/radeon/si.c if (!(disp_int[hpd_idx] & mask)) mask 6359 drivers/gpu/drm/radeon/si.c disp_int[hpd_idx] &= ~mask; mask 7467 drivers/gpu/drm/radeon/si.c uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; mask 7468 drivers/gpu/drm/radeon/si.c if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) mask 44 drivers/gpu/drm/radeon/si_dma.c u32 mask; mask 47 drivers/gpu/drm/radeon/si_dma.c mask = RADEON_RESET_DMA; mask 49 drivers/gpu/drm/radeon/si_dma.c mask = RADEON_RESET_DMA1; mask 51 drivers/gpu/drm/radeon/si_dma.c if (!(reset_mask & mask)) { mask 2759 drivers/gpu/drm/radeon/si_dpm.c data &= ~config_regs->mask; mask 2760 drivers/gpu/drm/radeon/si_dpm.c data |= ((config_regs->value << config_regs->shift) & config_regs->mask); mask 39 drivers/gpu/drm/radeon/si_dpm.h u32 mask; mask 169 drivers/gpu/drm/radeon/sumo_smc.c u32 mask = 0xFFF; mask 202 drivers/gpu/drm/radeon/sumo_smc.c sclk_dpm_tdp_limit &= ~(mask << shift); mask 71 drivers/gpu/drm/rcar-du/rcar_du_plane.c unsigned int mask; mask 76 drivers/gpu/drm/rcar-du/rcar_du_plane.c mask = 1 << state->hwindex; mask 78 drivers/gpu/drm/rcar-du/rcar_du_plane.c mask |= 1 << ((state->hwindex + 1) % 8); mask 80 drivers/gpu/drm/rcar-du/rcar_du_plane.c return mask; mask 38 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) mask 119 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422; mask 121 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c if ((di->color_formats & mask)) { mask 123 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c di->color_formats &= ~mask; mask 167 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) mask 308 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask) mask 310 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); mask 314 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c u32 mask, u32 val) mask 316 drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); mask 52 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) mask 242 drivers/gpu/drm/rockchip/inno_hdmi.c u32 mask, u32 disable, u32 enable) mask 244 drivers/gpu/drm/rockchip/inno_hdmi.c if (mask) mask 245 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable); mask 262 drivers/gpu/drm/rockchip/inno_hdmi.c if (mask) mask 263 drivers/gpu/drm/rockchip/inno_hdmi.c hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable); mask 157 drivers/gpu/drm/rockchip/rk3066_hdmi.c u32 mask, u32 disable, u32 enable) mask 159 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (mask) mask 160 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable); mask 177 drivers/gpu/drm/rockchip/rk3066_hdmi.c if (mask) mask 178 drivers/gpu/drm/rockchip/rk3066_hdmi.c hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable); mask 52 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (win_yuv2yuv && win_yuv2yuv->name.mask) \ mask 58 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \ mask 62 drivers/gpu/drm/rockchip/rockchip_drm_vop.c #define VOP_INTR_SET_MASK(vop, name, mask, v) \ mask 63 drivers/gpu/drm/rockchip/rockchip_drm_vop.c vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) mask 70 drivers/gpu/drm/rockchip/rockchip_drm_vop.c int i, reg = 0, mask = 0; \ mask 74 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mask |= 1 << i; \ mask 77 drivers/gpu/drm/rockchip/rockchip_drm_vop.c VOP_INTR_SET_MASK(vop, name, mask, reg); \ mask 86 drivers/gpu/drm/rockchip/rockchip_drm_vop.c (!!(win->phy->name.mask)) mask 185 drivers/gpu/drm/rockchip/rockchip_drm_vop.c return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; mask 192 drivers/gpu/drm/rockchip/rockchip_drm_vop.c int offset, mask, shift; mask 194 drivers/gpu/drm/rockchip/rockchip_drm_vop.c if (!reg || !reg->mask) { mask 200 drivers/gpu/drm/rockchip/rockchip_drm_vop.c mask = reg->mask & _mask; mask 204 drivers/gpu/drm/rockchip/rockchip_drm_vop.c v = ((v << shift) & 0xffff) | (mask << (shift + 16)); mask 208 drivers/gpu/drm/rockchip/rockchip_drm_vop.c v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); mask 30 drivers/gpu/drm/rockchip/rockchip_drm_vop.h uint32_t mask; mask 23 drivers/gpu/drm/rockchip/rockchip_vop_reg.c .mask = _mask, \ mask 49 drivers/gpu/drm/savage/savage_bci.c uint32_t mask = dev_priv->status_used_mask; mask 63 drivers/gpu/drm/savage/savage_bci.c if ((status & mask) < threshold) mask 126 drivers/gpu/drm/savage/savage_state.c #define SAVE_STATE_MASK(reg,where,mask) do { \ mask 130 drivers/gpu/drm/savage/savage_state.c dev_priv->state.where = (tmp & (mask)) | \ mask 131 drivers/gpu/drm/savage/savage_state.c (dev_priv->state.where & ~(mask)); \ mask 825 drivers/gpu/drm/savage/savage_state.c if (data->clear1.mask != 0xffffffff) { mask 829 drivers/gpu/drm/savage/savage_state.c DMA_WRITE(data->clear1.mask); mask 863 drivers/gpu/drm/savage/savage_state.c if (data->clear1.mask != 0xffffffff) { mask 297 drivers/gpu/drm/shmobile/shmob_drm_regs.h u32 mask, u32 until) mask 301 drivers/gpu/drm/shmobile/shmob_drm_regs.h while ((lcdc_read(sdev, reg) & mask) != until) { mask 241 drivers/gpu/drm/sti/sti_mixer.c u32 mask, val; mask 270 drivers/gpu/drm/sti/sti_mixer.c mask = GAM_DEPTH_MASK_ID << (3 * i); mask 271 drivers/gpu/drm/sti/sti_mixer.c if ((val & mask) == plane_id << (3 * i)) mask 275 drivers/gpu/drm/sti/sti_mixer.c mask |= GAM_DEPTH_MASK_ID << (3 * depth); mask 281 drivers/gpu/drm/sti/sti_mixer.c plane_id, mask); mask 283 drivers/gpu/drm/sti/sti_mixer.c val &= ~mask; mask 339 drivers/gpu/drm/sti/sti_mixer.c u32 mask, val; mask 344 drivers/gpu/drm/sti/sti_mixer.c mask = sti_mixer_get_plane_mask(plane); mask 345 drivers/gpu/drm/sti/sti_mixer.c if (!mask) { mask 351 drivers/gpu/drm/sti/sti_mixer.c val &= ~mask; mask 352 drivers/gpu/drm/sti/sti_mixer.c val |= status ? mask : 0; mask 454 drivers/gpu/drm/sti/sti_tvout.c int r, g, b, tmp, mask; mask 467 drivers/gpu/drm/sti/sti_tvout.c mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_R_SHIFT; mask 468 drivers/gpu/drm/sti/sti_tvout.c r = (val & mask) >> TVO_VIP_REORDER_R_SHIFT; mask 469 drivers/gpu/drm/sti/sti_tvout.c mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_G_SHIFT; mask 470 drivers/gpu/drm/sti/sti_tvout.c g = (val & mask) >> TVO_VIP_REORDER_G_SHIFT; mask 471 drivers/gpu/drm/sti/sti_tvout.c mask = TVO_VIP_REORDER_MASK << TVO_VIP_REORDER_B_SHIFT; mask 472 drivers/gpu/drm/sti/sti_tvout.c b = (val & mask) >> TVO_VIP_REORDER_B_SHIFT; mask 478 drivers/gpu/drm/sti/sti_tvout.c mask = TVO_VIP_CLIP_MASK << TVO_VIP_CLIP_SHIFT; mask 479 drivers/gpu/drm/sti/sti_tvout.c tmp = (val & mask) >> TVO_VIP_CLIP_SHIFT; mask 482 drivers/gpu/drm/sti/sti_tvout.c mask = TVO_VIP_RND_MASK << TVO_VIP_RND_SHIFT; mask 483 drivers/gpu/drm/sti/sti_tvout.c tmp = (val & mask) >> TVO_VIP_RND_SHIFT; mask 97 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) mask 99 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); mask 102 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) mask 104 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); mask 108 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c u32 mask, u32 val) mask 110 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); mask 252 drivers/gpu/drm/stm/ltdc.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) mask 254 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) | mask); mask 257 drivers/gpu/drm/stm/ltdc.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) mask 259 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, reg_read(base, reg) & ~mask); mask 262 drivers/gpu/drm/stm/ltdc.c static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, mask 265 drivers/gpu/drm/stm/ltdc.c reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); mask 32 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK | mask 51 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c reg & mask, len * byte_time_ns, mask 201 drivers/gpu/drm/sun4i/sun4i_tcon.c u32 mask, val = 0; mask 205 drivers/gpu/drm/sun4i/sun4i_tcon.c mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) | mask 210 drivers/gpu/drm/sun4i/sun4i_tcon.c val = mask; mask 212 drivers/gpu/drm/sun4i/sun4i_tcon.c regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); mask 215 drivers/gpu/drm/sun4i/sun8i_csc.c u32 val, mask; mask 217 drivers/gpu/drm/sun4i/sun8i_csc.c mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); mask 220 drivers/gpu/drm/sun4i/sun8i_csc.c val = mask; mask 225 drivers/gpu/drm/sun4i/sun8i_csc.c mask, val); mask 98 drivers/gpu/drm/sun4i/sun8i_vi_layer.c int mask, remainder; mask 100 drivers/gpu/drm/sun4i/sun8i_vi_layer.c mask = format->hsub - 1; mask 101 drivers/gpu/drm/sun4i/sun8i_vi_layer.c remainder = (state->src.x1 >> 16) & mask; mask 102 drivers/gpu/drm/sun4i/sun8i_vi_layer.c src_w = (src_w + remainder) & ~mask; mask 107 drivers/gpu/drm/sun4i/sun8i_vi_layer.c int mask, remainder; mask 109 drivers/gpu/drm/sun4i/sun8i_vi_layer.c mask = format->vsub - 1; mask 110 drivers/gpu/drm/sun4i/sun8i_vi_layer.c remainder = (state->src.y1 >> 16) & mask; mask 111 drivers/gpu/drm/sun4i/sun8i_vi_layer.c src_h = (src_h + remainder) & ~mask; mask 169 drivers/gpu/drm/tegra/hub.c u32 mask, value; mask 171 drivers/gpu/drm/tegra/hub.c mask = COMMON_UPDATE | WIN_A_UPDATE << plane->base.index; mask 172 drivers/gpu/drm/tegra/hub.c tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); mask 178 drivers/gpu/drm/tegra/hub.c if ((value & mask) == 0) mask 189 drivers/gpu/drm/tegra/hub.c u32 mask, value; mask 191 drivers/gpu/drm/tegra/hub.c mask = COMMON_ACTREQ | WIN_A_ACT_REQ << plane->base.index; mask 192 drivers/gpu/drm/tegra/hub.c tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); mask 198 drivers/gpu/drm/tegra/hub.c if ((value & mask) == 0) mask 223 drivers/gpu/drm/tegra/output.c unsigned int mask = 0; mask 229 drivers/gpu/drm/tegra/output.c mask |= drm_crtc_mask(crtc); mask 232 drivers/gpu/drm/tegra/output.c if (mask == 0) { mask 234 drivers/gpu/drm/tegra/output.c mask = 0x3; mask 237 drivers/gpu/drm/tegra/output.c output->encoder.possible_crtcs = mask; mask 141 drivers/gpu/drm/tilcdc/tilcdc_regs.h u32 val, u32 mask) mask 143 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask)); mask 146 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask) mask 148 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask); mask 151 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask) mask 153 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask); mask 168 drivers/gpu/drm/tilcdc/tilcdc_regs.h static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask) mask 170 drivers/gpu/drm/tilcdc/tilcdc_regs.h tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask); mask 200 drivers/gpu/drm/tiny/repaper.c const u8 *data, u8 fixed_value, const u8 *mask, mask 211 drivers/gpu/drm/tiny/repaper.c if (mask) { mask 212 drivers/gpu/drm/tiny/repaper.c pixel_mask = (mask[b] ^ pixels) & 0xaa; mask 246 drivers/gpu/drm/tiny/repaper.c const u8 *data, u8 fixed_value, const u8 *mask, mask 256 drivers/gpu/drm/tiny/repaper.c if (mask) { mask 257 drivers/gpu/drm/tiny/repaper.c pixel_mask = (mask[b - 1] ^ pixels) & 0x55; mask 296 drivers/gpu/drm/tiny/repaper.c const u8 *data, u8 fixed_value, const u8 *mask, mask 306 drivers/gpu/drm/tiny/repaper.c if (mask) { mask 307 drivers/gpu/drm/tiny/repaper.c pixel_mask = repaper_interleave_bits(mask[b - 1]); mask 340 drivers/gpu/drm/tiny/repaper.c const u8 *data, u8 fixed_value, const u8 *mask, mask 353 drivers/gpu/drm/tiny/repaper.c repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage); mask 364 drivers/gpu/drm/tiny/repaper.c repaper_even_pixels(epd, &p, data, fixed_value, mask, stage); mask 378 drivers/gpu/drm/tiny/repaper.c repaper_all_pixels(epd, &p, data, fixed_value, mask, stage); mask 433 drivers/gpu/drm/tiny/repaper.c const u8 *mask, enum repaper_stage stage) mask 437 drivers/gpu/drm/tiny/repaper.c if (!mask) { mask 447 drivers/gpu/drm/tiny/repaper.c repaper_one_line(epd, line, &image[n], 0, &mask[n], mask 465 drivers/gpu/drm/tiny/repaper.c const u8 *mask, enum repaper_stage stage) mask 471 drivers/gpu/drm/tiny/repaper.c repaper_frame_data(epd, image, mask, stage); mask 33 drivers/gpu/drm/vc4/vc4_perfmon.c u32 mask; mask 41 drivers/gpu/drm/vc4/vc4_perfmon.c mask = GENMASK(perfmon->ncounters - 1, 0); mask 42 drivers/gpu/drm/vc4/vc4_perfmon.c V3D_WRITE(V3D_PCTRC, mask); mask 43 drivers/gpu/drm/vc4/vc4_perfmon.c V3D_WRITE(V3D_PCTRE, V3D_PCTRE_EN | mask); mask 142 drivers/gpu/drm/via/via_drv.h u32 reg, u32 mask, u32 val) mask 147 drivers/gpu/drm/via/via_drv.h tmp = (tmp & ~mask) | (val & mask); mask 25 drivers/gpu/drm/zte/zx_drm_drv.h static inline void zx_writel_mask(void __iomem *reg, u32 mask, u32 val) mask 30 drivers/gpu/drm/zte/zx_drm_drv.h tmp = (tmp & ~mask) | (val & mask); mask 65 drivers/gpu/drm/zte/zx_hdmi.c u8 mask, u8 val) mask 70 drivers/gpu/drm/zte/zx_hdmi.c tmp = (tmp & ~mask) | (val & mask); mask 25 drivers/gpu/drm/zte/zx_tvenc.c u32 mask; mask 194 drivers/gpu/drm/zte/zx_tvenc.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, mask 195 drivers/gpu/drm/zte/zx_tvenc.c pwrctrl->mask); mask 212 drivers/gpu/drm/zte/zx_tvenc.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0); mask 324 drivers/gpu/drm/zte/zx_tvenc.c pwrctrl->mask = out_args.args[1]; mask 25 drivers/gpu/drm/zte/zx_vga.c u32 mask; mask 53 drivers/gpu/drm/zte/zx_vga.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, mask 54 drivers/gpu/drm/zte/zx_vga.c pwrctrl->mask); mask 67 drivers/gpu/drm/zte/zx_vga.c regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0); mask 213 drivers/gpu/drm/zte/zx_vga.c pwrctrl->mask = out_args.args[1]; mask 386 drivers/gpu/drm/zte/zx_vou.c u32 mask = bits->sec_vactive_mask; mask 389 drivers/gpu/drm/zte/zx_vou.c val &= ~mask; mask 390 drivers/gpu/drm/zte/zx_vou.c val |= ((vm.vactive / 2 - 1) << shift) & mask; mask 278 drivers/gpu/host1x/dev.c u64 mask = dma_get_mask(host->dev); mask 307 drivers/gpu/host1x/dev.c start = geometry->aperture_start & mask; mask 308 drivers/gpu/host1x/dev.c end = geometry->aperture_end & mask; mask 44 drivers/gpu/host1x/hw/debug_hw.c unsigned int mask, subop, num, opcode; mask 50 drivers/gpu/host1x/hw/debug_hw.c mask = val & 0x3f; mask 51 drivers/gpu/host1x/hw/debug_hw.c if (mask) { mask 54 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, mask); mask 55 drivers/gpu/host1x/hw/debug_hw.c return hweight8(mask); mask 80 drivers/gpu/host1x/hw/debug_hw.c mask = val & 0xffff; mask 82 drivers/gpu/host1x/hw/debug_hw.c val >> 16 & 0xfff, mask); mask 83 drivers/gpu/host1x/hw/debug_hw.c if (!mask) mask 86 drivers/gpu/host1x/hw/debug_hw.c return hweight16(mask); mask 79 drivers/gpu/host1x/hw/host1x01_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 81 drivers/gpu/host1x/hw/host1x01_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 94 drivers/gpu/host1x/hw/host1x01_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 96 drivers/gpu/host1x/hw/host1x01_hardware.h return (3 << 28) | (offset << 16) | mask; mask 78 drivers/gpu/host1x/hw/host1x02_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 80 drivers/gpu/host1x/hw/host1x02_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 93 drivers/gpu/host1x/hw/host1x02_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 95 drivers/gpu/host1x/hw/host1x02_hardware.h return (3 << 28) | (offset << 16) | mask; mask 78 drivers/gpu/host1x/hw/host1x04_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 80 drivers/gpu/host1x/hw/host1x04_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 93 drivers/gpu/host1x/hw/host1x04_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 95 drivers/gpu/host1x/hw/host1x04_hardware.h return (3 << 28) | (offset << 16) | mask; mask 78 drivers/gpu/host1x/hw/host1x05_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 80 drivers/gpu/host1x/hw/host1x05_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 93 drivers/gpu/host1x/hw/host1x05_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 95 drivers/gpu/host1x/hw/host1x05_hardware.h return (3 << 28) | (offset << 16) | mask; mask 79 drivers/gpu/host1x/hw/host1x06_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 81 drivers/gpu/host1x/hw/host1x06_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 94 drivers/gpu/host1x/hw/host1x06_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 96 drivers/gpu/host1x/hw/host1x06_hardware.h return (3 << 28) | (offset << 16) | mask; mask 79 drivers/gpu/host1x/hw/host1x07_hardware.h unsigned class_id, unsigned offset, unsigned mask) mask 81 drivers/gpu/host1x/hw/host1x07_hardware.h return (0 << 28) | (offset << 16) | (class_id << 6) | mask; mask 94 drivers/gpu/host1x/hw/host1x07_hardware.h static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) mask 96 drivers/gpu/host1x/hw/host1x07_hardware.h return (3 << 28) | (offset << 16) | mask; mask 266 drivers/gpu/host1x/job.c u32 mask; mask 304 drivers/gpu/host1x/job.c u32 mask = fw->mask; mask 308 drivers/gpu/host1x/job.c while (mask) { mask 312 drivers/gpu/host1x/job.c if (mask & 1) { mask 320 drivers/gpu/host1x/job.c mask >>= 1; mask 386 drivers/gpu/host1x/job.c fw->mask = 0; mask 395 drivers/gpu/host1x/job.c fw->mask = word & 0x3f; mask 420 drivers/gpu/host1x/job.c fw->mask = word & 0xffff; mask 435 drivers/gpu/ipu-v3/ipu-common.c int ipu_module_enable(struct ipu_soc *ipu, u32 mask) mask 444 drivers/gpu/ipu-v3/ipu-common.c if (mask & IPU_CONF_DI0_EN) mask 446 drivers/gpu/ipu-v3/ipu-common.c if (mask & IPU_CONF_DI1_EN) mask 452 drivers/gpu/ipu-v3/ipu-common.c val |= mask; mask 461 drivers/gpu/ipu-v3/ipu-common.c int ipu_module_disable(struct ipu_soc *ipu, u32 mask) mask 469 drivers/gpu/ipu-v3/ipu-common.c val &= ~mask; mask 474 drivers/gpu/ipu-v3/ipu-common.c if (mask & IPU_CONF_DI0_EN) mask 476 drivers/gpu/ipu-v3/ipu-common.c if (mask & IPU_CONF_DI1_EN) mask 698 drivers/gpu/ipu-v3/ipu-common.c u32 val, mask; mask 700 drivers/gpu/ipu-v3/ipu-common.c mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE : mask 707 drivers/gpu/ipu-v3/ipu-common.c val |= mask; mask 709 drivers/gpu/ipu-v3/ipu-common.c val &= ~mask; mask 749 drivers/gpu/ipu-v3/ipu-common.c u32 mask; mask 809 drivers/gpu/ipu-v3/ipu-common.c if (link->src.mask) { mask 811 drivers/gpu/ipu-v3/ipu-common.c src_reg &= ~link->src.mask; mask 816 drivers/gpu/ipu-v3/ipu-common.c if (link->sink.mask) { mask 818 drivers/gpu/ipu-v3/ipu-common.c sink_reg &= ~link->sink.mask; mask 843 drivers/gpu/ipu-v3/ipu-common.c if (link->src.mask) { mask 845 drivers/gpu/ipu-v3/ipu-common.c src_reg &= ~link->src.mask; mask 849 drivers/gpu/ipu-v3/ipu-common.c if (link->sink.mask) { mask 851 drivers/gpu/ipu-v3/ipu-common.c sink_reg &= ~link->sink.mask; mask 1307 drivers/gpu/ipu-v3/ipu-common.c ct->regs.mask = IPU_INT_CTRL(i / 32); mask 108 drivers/gpu/ipu-v3/ipu-cpmem.c u32 mask = (1 << size) - 1; mask 114 drivers/gpu/ipu-v3/ipu-cpmem.c val &= ~(mask << ofs); mask 120 drivers/gpu/ipu-v3/ipu-cpmem.c val &= ~(mask >> (ofs ? (32 - ofs) : 0)); mask 134 drivers/gpu/ipu-v3/ipu-cpmem.c u32 mask = (1 << size) - 1; mask 139 drivers/gpu/ipu-v3/ipu-cpmem.c val = (readl(&base->word[word].data[i]) >> ofs) & mask; mask 145 drivers/gpu/ipu-v3/ipu-cpmem.c tmp &= mask >> (ofs ? (32 - ofs) : 0); mask 279 drivers/gpu/ipu-v3/ipu-dc.c int byte_num, int offset, int mask) mask 286 drivers/gpu/ipu-v3/ipu-dc.c reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); mask 1920 drivers/gpu/ipu-v3/ipu-image-convert.c unsigned int mask = ~((1 << align) - 1); mask 1923 drivers/gpu/ipu-v3/ipu-image-convert.c x = clamp(x, (min + ~mask) & mask, max & mask); mask 1927 drivers/gpu/ipu-v3/ipu-image-convert.c x = (x + (1 << (align - 1))) & mask; mask 215 drivers/gpu/ipu-v3/ipu-prv.h int ipu_module_enable(struct ipu_soc *ipu, u32 mask); mask 216 drivers/gpu/ipu-v3/ipu-prv.h int ipu_module_disable(struct ipu_soc *ipu, u32 mask); mask 1348 drivers/hid/hid-core.c u32 mask = n < 32 ? (1U << n) - 1 : ~0U; mask 1359 drivers/hid/hid-core.c return value & mask; mask 93 drivers/hid/hid-cp2112.c u8 mask; /* What fields to program */ mask 901 drivers/hid/hid-cp2112.c cfg.mask = 0x01; mask 911 drivers/hid/hid-cp2112.c cfg.mask = 0x02; mask 921 drivers/hid/hid-cp2112.c cfg.mask = 0x04; mask 928 drivers/hid/hid-cp2112.c cfg.mask = 0x08; mask 936 drivers/hid/hid-cp2112.c cfg.mask = 0x10; mask 113 drivers/hid/hid-lg4ff.c const u16 mask; mask 1198 drivers/hid/hid-lg4ff.c const u16 mask = lg4ff_main_checklist[i]->mask; mask 1203 drivers/hid/hid-lg4ff.c (bcdDevice & mask) == result) { mask 510 drivers/hid/hid-logitech-hidpp.c u8 register_address, u8 byte, u8 mask, u8 value) mask 526 drivers/hid/hid-logitech-hidpp.c params[byte] &= ~mask; mask 527 drivers/hid/hid-logitech-hidpp.c params[byte] |= value & mask; mask 697 drivers/hid/hid-sensor-custom.c __poll_t mask = 0; mask 705 drivers/hid/hid-sensor-custom.c mask = EPOLLIN | EPOLLRDNORM; mask 707 drivers/hid/hid-sensor-custom.c return mask; mask 252 drivers/hid/hidraw.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; /* hidraw is always writable */ mask 256 drivers/hid/hidraw.c mask |= EPOLLIN | EPOLLRDNORM; mask 258 drivers/hid/hidraw.c mask |= EPOLLERR | EPOLLHUP; mask 259 drivers/hid/hidraw.c return mask; mask 769 drivers/hid/uhid.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; /* uhid is always writable */ mask 774 drivers/hid/uhid.c mask |= EPOLLIN | EPOLLRDNORM; mask 776 drivers/hid/uhid.c return mask; mask 38 drivers/hid/wacom_wac.c int button_count, int mask); mask 42 drivers/hid/wacom_wac.c static void wacom_update_led(struct wacom *wacom, int button_count, int mask, mask 3896 drivers/hid/wacom_wac.c static void wacom_24hd_update_leds(struct wacom *wacom, int mask, int group) mask 3908 drivers/hid/wacom_wac.c mask >>= 8; mask 3917 drivers/hid/wacom_wac.c if (!updated && mask & BIT(i)) { mask 3927 drivers/hid/wacom_wac.c int mask, int group) mask 3944 drivers/hid/wacom_wac.c return mask & (1 << group_button); mask 3947 drivers/hid/wacom_wac.c static void wacom_update_led(struct wacom *wacom, int button_count, int mask, mask 3955 drivers/hid/wacom_wac.c return wacom_24hd_update_leds(wacom, mask, group); mask 3957 drivers/hid/wacom_wac.c pressed = wacom_is_led_toggled(wacom, button_count, mask, group); mask 3990 drivers/hid/wacom_wac.c int button_count, int mask) mask 3996 drivers/hid/wacom_wac.c wacom_update_led(wacom, button_count, mask, i); mask 4002 drivers/hid/wacom_wac.c input_report_key(input_dev, key, mask & (1 << i)); mask 960 drivers/hwmon/abituguru.c unsigned long mask; mask 962 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &mask); mask 970 drivers/hwmon/abituguru.c if (mask) mask 993 drivers/hwmon/abituguru.c unsigned long mask; mask 995 drivers/hwmon/abituguru.c ret = kstrtoul(buf, 10, &mask); mask 1003 drivers/hwmon/abituguru.c if (mask) mask 232 drivers/hwmon/adc128d818.c int mask = 1 << to_sensor_dev_attr(attr)->index; mask 243 drivers/hwmon/adc128d818.c data->alarms &= ~mask; mask 245 drivers/hwmon/adc128d818.c return sprintf(buf, "%u\n", !!(alarms & mask)); mask 1166 drivers/hwmon/adm1026.c unsigned long mask; mask 1176 drivers/hwmon/adm1026.c mask = data->alarm_mask mask 1179 drivers/hwmon/adm1026.c mask & 0xff); mask 1180 drivers/hwmon/adm1026.c mask >>= 8; mask 1182 drivers/hwmon/adm1026.c mask & 0xff); mask 1183 drivers/hwmon/adm1026.c mask >>= 8; mask 1185 drivers/hwmon/adm1026.c mask & 0xff); mask 1186 drivers/hwmon/adm1026.c mask >>= 8; mask 1188 drivers/hwmon/adm1026.c mask & 0xff); mask 1241 drivers/hwmon/adm1026.c long mask; mask 1251 drivers/hwmon/adm1026.c mask = data->gpio_mask; mask 1252 drivers/hwmon/adm1026.c adm1026_write_value(client, ADM1026_REG_GPIO_MASK_0_7, mask & 0xff); mask 1253 drivers/hwmon/adm1026.c mask >>= 8; mask 1254 drivers/hwmon/adm1026.c adm1026_write_value(client, ADM1026_REG_GPIO_MASK_8_15, mask & 0xff); mask 1255 drivers/hwmon/adm1026.c mask = ((mask >> 1) & 0x80) | (data->alarm_mask >> 24 & 0x7f); mask 1256 drivers/hwmon/adm1026.c adm1026_write_value(client, ADM1026_REG_MASK1, mask & 0xff); mask 997 drivers/hwmon/adm1031.c unsigned int mask; mask 1001 drivers/hwmon/adm1031.c mask = (ADM1031_CONF2_PWM1_ENABLE | ADM1031_CONF2_TACH1_ENABLE); mask 1003 drivers/hwmon/adm1031.c mask |= (ADM1031_CONF2_PWM2_ENABLE | mask 1008 drivers/hwmon/adm1031.c if ((read_val | mask) != read_val) mask 1009 drivers/hwmon/adm1031.c adm1031_write_value(client, ADM1031_REG_CONF2, read_val | mask); mask 1018 drivers/hwmon/adm1031.c mask = ADM1031_UPDATE_RATE_MASK; mask 1020 drivers/hwmon/adm1031.c i = (read_val & mask) >> ADM1031_UPDATE_RATE_SHIFT; mask 981 drivers/hwmon/adt7462.c int mask = attr->index & ADT7462_ALARM_FLAG_MASK; mask 983 drivers/hwmon/adt7462.c if (data->alarms[reg] & mask) mask 535 drivers/hwmon/adt7470.c long mask; mask 537 drivers/hwmon/adt7470.c if (kstrtoul(buf, 0, &mask)) mask 540 drivers/hwmon/adt7470.c if (mask & ~0xffff) mask 544 drivers/hwmon/adt7470.c data->alarms_mask = mask; mask 545 drivers/hwmon/adt7470.c adt7470_write_word_data(data->client, ADT7470_REG_ALARM1_MASK, mask); mask 824 drivers/hwmon/adt7475.c u8 mask = BIT(5 + sattr->index); mask 826 drivers/hwmon/adt7475.c return sprintf(buf, "%d\n", !!(data->enh_acoustics[0] & mask)); mask 837 drivers/hwmon/adt7475.c u8 mask = BIT(5 + sattr->index); mask 844 drivers/hwmon/adt7475.c data->enh_acoustics[0] &= ~mask; mask 846 drivers/hwmon/adt7475.c data->enh_acoustics[0] |= mask; mask 109 drivers/hwmon/asc7621.c u8 mask[3]; mask 200 drivers/hwmon/asc7621.c shift[0]) & param->mask[0]); mask 214 drivers/hwmon/asc7621.c reqval = clamp_val(reqval, 0, param->mask[0]); mask 216 drivers/hwmon/asc7621.c reqval = (reqval & param->mask[0]) << param->shift[0]; mask 220 drivers/hwmon/asc7621.c reqval |= (currval & ~(param->mask[0] << param->shift[0])); mask 457 drivers/hwmon/asc7621.c ((data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]); mask 488 drivers/hwmon/asc7621.c newval = (newval & param->mask[0]) << param->shift[0]; mask 490 drivers/hwmon/asc7621.c newval |= (currval & ~(param->mask[0] << param->shift[0])); mask 508 drivers/hwmon/asc7621.c config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; mask 509 drivers/hwmon/asc7621.c altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; mask 543 drivers/hwmon/asc7621.c config = (config & param->mask[0]) << param->shift[0]; mask 544 drivers/hwmon/asc7621.c altbit = (altbit & param->mask[1]) << param->shift[1]; mask 548 drivers/hwmon/asc7621.c newval = config | (currval & ~(param->mask[0] << param->shift[0])); mask 549 drivers/hwmon/asc7621.c newval = altbit | (newval & ~(param->mask[1] << param->shift[1])); mask 563 drivers/hwmon/asc7621.c config = (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; mask 564 drivers/hwmon/asc7621.c altbit = (data->reg[param->msb[1]] >> param->shift[1]) & param->mask[1]; mask 565 drivers/hwmon/asc7621.c minoff = (data->reg[param->msb[2]] >> param->shift[2]) & param->mask[2]; mask 621 drivers/hwmon/asc7621.c config = (config & param->mask[0]) << param->shift[0]; mask 622 drivers/hwmon/asc7621.c altbit = (altbit & param->mask[1]) << param->shift[1]; mask 624 drivers/hwmon/asc7621.c newval = config | (currval & ~(param->mask[0] << param->shift[0])); mask 625 drivers/hwmon/asc7621.c newval = altbit | (newval & ~(param->mask[1] << param->shift[1])); mask 629 drivers/hwmon/asc7621.c minoff = (minoff & param->mask[2]) << param->shift[2]; mask 632 drivers/hwmon/asc7621.c minoff | (currval & ~(param->mask[2] << param->shift[2])); mask 650 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; mask 678 drivers/hwmon/asc7621.c newval = (newval & param->mask[0]) << param->shift[0]; mask 682 drivers/hwmon/asc7621.c newval |= (currval & ~(param->mask[0] << param->shift[0])); mask 698 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; mask 727 drivers/hwmon/asc7621.c newval = (newval & param->mask[0]) << param->shift[0]; mask 731 drivers/hwmon/asc7621.c newval |= (currval & ~(param->mask[0] << param->shift[0])); mask 747 drivers/hwmon/asc7621.c (data->reg[param->msb[0]] >> param->shift[0]) & param->mask[0]; mask 775 drivers/hwmon/asc7621.c newval = (newval & param->mask[0]) << param->shift[0]; mask 779 drivers/hwmon/asc7621.c newval |= (currval & ~(param->mask[0] << param->shift[0])); mask 801 drivers/hwmon/asc7621.c .priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \ mask 806 drivers/hwmon/asc7621.c .priority = pri, .msb[0] = rm, .lsb[0] = rl, .mask[0] = m, \ mask 815 drivers/hwmon/asc7621.c .priority = pri, .msb = rm, .lsb = rl, .mask = m, .shift = s,} mask 202 drivers/hwmon/coretemp.c u8 mask; mask 259 drivers/hwmon/coretemp.c (tm->mask == ANY || c->x86_stepping == tm->mask)) mask 164 drivers/hwmon/fam15h_power.c cpumask_var_t mask; mask 167 drivers/hwmon/fam15h_power.c ret = zalloc_cpumask_var(&mask, GFP_KERNEL); mask 192 drivers/hwmon/fam15h_power.c cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask); mask 195 drivers/hwmon/fam15h_power.c on_each_cpu_mask(mask, do_read_registers_on_cu, data, true); mask 198 drivers/hwmon/fam15h_power.c free_cpumask_var(mask); mask 299 drivers/hwmon/gl518sm.c #define set_bits(type, suffix, value, reg, mask, shift) \ mask 315 drivers/hwmon/gl518sm.c regvalue = (regvalue & ~mask) | (data->value << shift); \ mask 286 drivers/hwmon/ina209.c u32 mask = attr->index; mask 296 drivers/hwmon/ina209.c if (mask & (1 << i)) mask 354 drivers/hwmon/ina209.c const unsigned int mask = attr->index; mask 366 drivers/hwmon/ina209.c return snprintf(buf, PAGE_SIZE, "%u\n", !!(status & mask)); mask 393 drivers/hwmon/ina3221.c u16 config, mask = INA3221_CONFIG_CHx_EN(channel); mask 394 drivers/hwmon/ina3221.c u16 config_old = ina->reg_config & mask; mask 398 drivers/hwmon/ina3221.c config = enable ? mask : 0; mask 414 drivers/hwmon/ina3221.c tmp = (ina->reg_config & ~mask) | (config & mask); mask 2869 drivers/hwmon/it87.c u8 mask, fan_main_ctrl; mask 2871 drivers/hwmon/it87.c mask = 0x70 & ~(sio_data->skip_fan << 4); mask 2873 drivers/hwmon/it87.c if ((fan_main_ctrl & mask) == 0) { mask 2875 drivers/hwmon/it87.c fan_main_ctrl |= mask; mask 1873 drivers/hwmon/lm93.c int mask; mask 1877 drivers/hwmon/lm93.c mask = mapping & 0x01; mask 1878 drivers/hwmon/lm93.c mask |= (mapping & 0x04) >> 1; mask 1879 drivers/hwmon/lm93.c mask |= (mapping & 0x10) >> 2; mask 1880 drivers/hwmon/lm93.c mask |= (mapping & 0x40) >> 3; mask 1884 drivers/hwmon/lm93.c data->sfc2 &= ~mask; mask 223 drivers/hwmon/lm95234.c u32 mask = to_sensor_dev_attr(attr)->index; mask 229 drivers/hwmon/lm95234.c return sprintf(buf, "%u", !!(data->status & mask)); mask 236 drivers/hwmon/lm95234.c u8 mask = to_sensor_dev_attr(attr)->index; mask 242 drivers/hwmon/lm95234.c return sprintf(buf, data->sensor_type & mask ? "1\n" : "2\n"); mask 250 drivers/hwmon/lm95234.c u8 mask = to_sensor_dev_attr(attr)->index; mask 265 drivers/hwmon/lm95234.c data->sensor_type |= mask; mask 267 drivers/hwmon/lm95234.c data->sensor_type &= ~mask; mask 171 drivers/hwmon/ltc4215.c const u32 mask = attr->index; mask 173 drivers/hwmon/ltc4215.c return snprintf(buf, PAGE_SIZE, "%u\n", !!(reg & mask)); mask 56 drivers/hwmon/mlxreg-fan.c #define MLXREG_FAN_GET_FAULT(val, mask) ((val) == (mask)) mask 74 drivers/hwmon/mlxreg-fan.c u32 mask; mask 139 drivers/hwmon/mlxreg-fan.c *val = MLXREG_FAN_GET_FAULT(regval, tacho->mask); mask 417 drivers/hwmon/mlxreg-fan.c fan->tacho[tacho_num].mask = data->mask; mask 434 drivers/hwmon/mlxreg-fan.c if (!data->mask && !data->bit && !data->capability) { mask 444 drivers/hwmon/mlxreg-fan.c if (data->mask) mask 445 drivers/hwmon/mlxreg-fan.c fan->samples = data->mask; mask 3767 drivers/hwmon/nct6775.c int *available, int *mask) mask 3779 drivers/hwmon/nct6775.c if (!src || (*mask & BIT(src))) mask 3787 drivers/hwmon/nct6775.c *mask |= BIT(src); mask 3798 drivers/hwmon/nct6775.c int src, mask, available; mask 4334 drivers/hwmon/nct6775.c mask = 0; mask 4341 drivers/hwmon/nct6775.c if (!src || (mask & BIT(src))) mask 4344 drivers/hwmon/nct6775.c mask |= BIT(src); mask 4351 drivers/hwmon/nct6775.c add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask); mask 4352 drivers/hwmon/nct6775.c add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask); mask 4354 drivers/hwmon/nct6775.c mask = 0; mask 4361 drivers/hwmon/nct6775.c if (!src || (mask & BIT(src))) mask 4371 drivers/hwmon/nct6775.c mask |= BIT(src); mask 4438 drivers/hwmon/nct6775.c if (mask & BIT(src)) mask 4440 drivers/hwmon/nct6775.c mask |= BIT(src); mask 4476 drivers/hwmon/nct6775.c if (mask & BIT(i + 1)) mask 880 drivers/hwmon/nct7904.c u32 mask; mask 905 drivers/hwmon/nct7904.c mask = 0; mask 908 drivers/hwmon/nct7904.c mask = (ret >> 8) | ((ret & 0xff) << 8); mask 911 drivers/hwmon/nct7904.c mask |= (ret << 16); mask 912 drivers/hwmon/nct7904.c data->vsen_mask = mask; mask 71 drivers/hwmon/nsa320-hwmon.c u32 mask; mask 83 drivers/hwmon/nsa320-hwmon.c for (mask = BIT(31); mask; mask >>= 1) { mask 89 drivers/hwmon/nsa320-hwmon.c mcu_data |= mask; mask 177 drivers/hwmon/pmbus/adm1275.c u16 mask; mask 186 drivers/hwmon/pmbus/adm1275.c mask = is_power ? ADM1278_PWR_AVG_MASK : ADM1278_VI_AVG_MASK; mask 190 drivers/hwmon/pmbus/adm1275.c mask = ADM1275_VI_AVG_MASK; mask 196 drivers/hwmon/pmbus/adm1275.c return (ret & mask) >> shift; mask 204 drivers/hwmon/pmbus/adm1275.c u16 mask; mask 208 drivers/hwmon/pmbus/adm1275.c mask = is_power ? ADM1278_PWR_AVG_MASK : ADM1278_VI_AVG_MASK; mask 212 drivers/hwmon/pmbus/adm1275.c mask = ADM1275_VI_AVG_MASK; mask 218 drivers/hwmon/pmbus/adm1275.c word = (ret & ~mask) | ((word << shift) & mask); mask 122 drivers/hwmon/pmbus/ltc2978.c u8 mask; mask 131 drivers/hwmon/pmbus/ltc2978.c mask = LTC_NOT_BUSY; mask 133 drivers/hwmon/pmbus/ltc2978.c mask |= LTC_NOT_PENDING; mask 145 drivers/hwmon/pmbus/ltc2978.c if ((status & mask) == mask) mask 454 drivers/hwmon/pmbus/pmbus.h u8 mask, u8 value); mask 468 drivers/hwmon/pmbus/pmbus.h u8 config, u8 mask, u16 command); mask 265 drivers/hwmon/pmbus/pmbus_core.c u8 config, u8 mask, u16 command) mask 276 drivers/hwmon/pmbus/pmbus_core.c to = (from & ~mask) | (config & mask); mask 366 drivers/hwmon/pmbus/pmbus_core.c u8 mask, u8 value) mask 375 drivers/hwmon/pmbus/pmbus_core.c tmp = (rv & ~mask) | (value & mask); mask 905 drivers/hwmon/pmbus/pmbus_core.c u16 mask = index & 0xffff; mask 913 drivers/hwmon/pmbus/pmbus_core.c regval = status & mask; mask 1048 drivers/hwmon/pmbus/pmbus_core.c u16 reg, u16 mask) mask 1064 drivers/hwmon/pmbus/pmbus_core.c (reg << 16) | mask); mask 194 drivers/hwmon/tmp108.c u32 regval, mask; mask 200 drivers/hwmon/tmp108.c mask = TMP108_CONVRATE_16HZ; mask 202 drivers/hwmon/tmp108.c mask = TMP108_CONVRATE_4HZ; mask 204 drivers/hwmon/tmp108.c mask = TMP108_CONVRATE_1HZ; mask 206 drivers/hwmon/tmp108.c mask = TMP108_CONVRATE_0P25HZ; mask 210 drivers/hwmon/tmp108.c mask); mask 237 drivers/hwmon/tmp108.c mask = TMP108_HYSTERESIS_0C; mask 239 drivers/hwmon/tmp108.c mask = TMP108_HYSTERESIS_1C; mask 241 drivers/hwmon/tmp108.c mask = TMP108_HYSTERESIS_2C; mask 243 drivers/hwmon/tmp108.c mask = TMP108_HYSTERESIS_4C; mask 245 drivers/hwmon/tmp108.c TMP108_CONF_HYSTERESIS_MASK, mask); mask 314 drivers/hwmon/tmp401.c int mask = to_sensor_dev_attr_2(devattr)->index; mask 320 drivers/hwmon/tmp401.c return sprintf(buf, "%d\n", !!(data->status[nr] & mask)); mask 1775 drivers/hwmon/w83627ehf.c u16 reg, mask; mask 1780 drivers/hwmon/w83627ehf.c mask = to_sensor_dev_attr_2(attr)->nr; mask 1784 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask); mask 1785 drivers/hwmon/w83627ehf.c w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask); mask 2093 drivers/hwmon/w83627ehf.c int mask = 0; mask 2111 drivers/hwmon/w83627ehf.c if (src && !(mask & (1 << src))) { mask 2113 drivers/hwmon/w83627ehf.c mask |= 1 << src; mask 1139 drivers/hwmon/w83627hf.c static const u8 mask[]={0xF8, 0x8F}; mask 1154 drivers/hwmon/w83627hf.c W83627HF_REG_PWM_FREQ) & mask[nr])); mask 629 drivers/hwmon/w83793.c u8 mask = (index < 4) ? 0x03 : 0x01; mask 634 drivers/hwmon/w83793.c tmp = (data->temp_mode[index] >> shift) & mask; mask 654 drivers/hwmon/w83793.c u8 mask = (index < 4) ? 0x03 : 0x01; mask 678 drivers/hwmon/w83793.c data->temp_mode[index] &= ~(mask << shift); mask 119 drivers/hwmon/xgene-hwmon.c static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask) mask 124 drivers/hwmon/xgene-hwmon.c ret = val & mask; mask 125 drivers/hwmon/xgene-hwmon.c val &= ~mask; mask 573 drivers/hwtracing/coresight/coresight-catu.c .mask = 0x000fffff, mask 414 drivers/hwtracing/coresight/coresight-cpu-debug.c cpumask_t mask; mask 420 drivers/hwtracing/coresight/coresight-cpu-debug.c cpumask_clear(&mask); mask 431 drivers/hwtracing/coresight/coresight-cpu-debug.c cpumask_set_cpu(cpu, &mask); mask 441 drivers/hwtracing/coresight/coresight-cpu-debug.c for_each_cpu(cpu, &mask) { mask 497 drivers/hwtracing/coresight/coresight-etb10.c u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1); mask 500 drivers/hwtracing/coresight/coresight-etb10.c to_read = handle->size & mask; mask 833 drivers/hwtracing/coresight/coresight-etb10.c .mask = 0x000fffff, mask 126 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_t *mask = &event_data->mask; mask 129 drivers/hwtracing/coresight/coresight-etm-perf.c if (WARN_ON(cpumask_empty(mask))) mask 135 drivers/hwtracing/coresight/coresight-etm-perf.c cpu = cpumask_first(mask); mask 143 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_t *mask; mask 147 drivers/hwtracing/coresight/coresight-etm-perf.c mask = &event_data->mask; mask 152 drivers/hwtracing/coresight/coresight-etm-perf.c for_each_cpu(cpu, mask) { mask 167 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_t *mask; mask 176 drivers/hwtracing/coresight/coresight-etm-perf.c mask = &event_data->mask; mask 178 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_set_cpu(cpu, mask); mask 180 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_copy(mask, cpu_present_mask); mask 212 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_t *mask; mask 232 drivers/hwtracing/coresight/coresight-etm-perf.c mask = &event_data->mask; mask 241 drivers/hwtracing/coresight/coresight-etm-perf.c for_each_cpu(cpu, mask) { mask 252 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_clear_cpu(cpu, mask); mask 263 drivers/hwtracing/coresight/coresight-etm-perf.c cpumask_clear_cpu(cpu, mask); mask 271 drivers/hwtracing/coresight/coresight-etm-perf.c cpu = cpumask_first(mask); mask 55 drivers/hwtracing/coresight/coresight-etm-perf.h cpumask_t mask; mask 1719 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val1, val2, mask; mask 1791 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask = config->ctxid_mask0; mask 1794 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c maskbyte = mask & ETMv4_EVENT_MASK; mask 1807 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask = config->ctxid_mask1; mask 1809 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask >>= 0x8; mask 1908 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c unsigned long val1, val2, mask; mask 1974 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask = config->vmid_mask0; mask 1977 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c maskbyte = mask & ETMv4_EVENT_MASK; mask 1990 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask = config->vmid_mask1; mask 1992 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c mask >>= 0x8; mask 354 drivers/hwtracing/coresight/coresight-funnel.c .mask = 0x000fffff, mask 359 drivers/hwtracing/coresight/coresight-funnel.c .mask = 0x000fffff, mask 173 drivers/hwtracing/coresight/coresight-priv.h .mask = 0x000fffff, \ mask 180 drivers/hwtracing/coresight/coresight-priv.h .mask = 0x000fffff, \ mask 191 drivers/hwtracing/coresight/coresight-priv.h .mask = 0x000fffff, \ mask 352 drivers/hwtracing/coresight/coresight-replicator.c .mask = 0x000fffff, mask 357 drivers/hwtracing/coresight/coresight-replicator.c .mask = 0x000fffff, mask 494 drivers/hwtracing/coresight/coresight-tmc-etf.c u32 mask = tmc_get_memwidth_mask(drvdata); mask 500 drivers/hwtracing/coresight/coresight-tmc-etf.c to_read = handle->size & mask; mask 1520 drivers/hwtracing/coresight/coresight-tmc-etr.c u32 mask = tmc_get_memwidth_mask(drvdata); mask 1526 drivers/hwtracing/coresight/coresight-tmc-etr.c size = handle->size & mask; mask 75 drivers/hwtracing/coresight/coresight-tmc.c u32 mask = 0; mask 91 drivers/hwtracing/coresight/coresight-tmc.c mask = GENMASK(31, 4); mask 94 drivers/hwtracing/coresight/coresight-tmc.c mask = GENMASK(31, 5); mask 98 drivers/hwtracing/coresight/coresight-tmc.c return mask; mask 205 drivers/hwtracing/coresight/coresight-tpiu.c .mask = 0x000fffff, mask 209 drivers/hwtracing/coresight/coresight-tpiu.c .mask = 0x0007ffff, mask 214 drivers/hwtracing/coresight/coresight-tpiu.c .mask = 0x000fffff, mask 229 drivers/hwtracing/intel_th/gth.c .mask = (_mask), \ mask 238 drivers/hwtracing/intel_th/gth.c unsigned int mask; mask 255 drivers/hwtracing/intel_th/gth.c unsigned int mask = output_parms[parm].mask; mask 256 drivers/hwtracing/intel_th/gth.c unsigned int shift = __ffs(mask); mask 258 drivers/hwtracing/intel_th/gth.c config &= ~mask; mask 259 drivers/hwtracing/intel_th/gth.c config |= (val << shift) & mask; mask 267 drivers/hwtracing/intel_th/gth.c unsigned int mask = output_parms[parm].mask; mask 268 drivers/hwtracing/intel_th/gth.c unsigned int shift = __ffs(mask); mask 270 drivers/hwtracing/intel_th/gth.c config &= mask; mask 1734 drivers/hwtracing/intel_th/msu.c u32 mask = msc->index ? MSUSTS_MSC1BLAST : MSUSTS_MSC0BLAST; mask 1740 drivers/hwtracing/intel_th/msu.c msusts &= mask; mask 94 drivers/i2c/busses/i2c-altera.c altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable) mask 103 drivers/i2c/busses/i2c-altera.c idev->isr_mask = int_en | mask; mask 105 drivers/i2c/busses/i2c-altera.c idev->isr_mask = int_en & ~mask; mask 112 drivers/i2c/busses/i2c-altera.c static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask) mask 116 drivers/i2c/busses/i2c-altera.c writel(int_en | mask, idev->base + ALTR_I2C_ISR); mask 152 drivers/i2c/busses/i2c-axxia.c static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) mask 157 drivers/i2c/busses/i2c-axxia.c writel(int_en & ~mask, idev->base + MST_INT_ENABLE); mask 160 drivers/i2c/busses/i2c-axxia.c static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) mask 165 drivers/i2c/busses/i2c-axxia.c writel(int_en | mask, idev->base + MST_INT_ENABLE); mask 416 drivers/i2c/busses/i2c-axxia.c int mask = idev->last ? ~0 : ~MST_STATUS_TSS; mask 418 drivers/i2c/busses/i2c-axxia.c i2c_int_disable(idev, mask); mask 15 drivers/i2c/busses/i2c-efm32.c #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) mask 227 drivers/i2c/busses/i2c-ibm_iic.c static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask) mask 230 drivers/i2c/busses/i2c-ibm_iic.c while ((in_8(&iic->directcntl) & mask) != mask){ mask 242 drivers/i2c/busses/i2c-ibm_iic.c u8 mask, v, sda; mask 270 drivers/i2c/busses/i2c-ibm_iic.c for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){ mask 273 drivers/i2c/busses/i2c-ibm_iic.c sda = (v & mask) ? DIRCNTL_SDAC : 0; mask 154 drivers/i2c/busses/i2c-iop3xx.c typedef int (* compare_func)(unsigned test, unsigned mask); mask 191 drivers/i2c/busses/i2c-iop3xx.c all_bits_clear(unsigned test, unsigned mask) mask 193 drivers/i2c/busses/i2c-iop3xx.c return (test & mask) == 0; mask 197 drivers/i2c/busses/i2c-iop3xx.c any_bits_set(unsigned test, unsigned mask) mask 199 drivers/i2c/busses/i2c-iop3xx.c return (test & mask) != 0; mask 102 drivers/i2c/busses/i2c-meson.c static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask, mask 108 drivers/i2c/busses/i2c-meson.c data &= ~mask; mask 109 drivers/i2c/busses/i2c-meson.c data |= val & mask; mask 92 drivers/i2c/busses/i2c-nomadik.c #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask)) mask 98 drivers/i2c/busses/i2c-nomadik.c #define IRQ_MASK(mask) (mask & 0x1fffffff) mask 197 drivers/i2c/busses/i2c-nomadik.c static inline void i2c_set_bit(void __iomem *reg, u32 mask) mask 199 drivers/i2c/busses/i2c-nomadik.c writel(readl(reg) | mask, reg); mask 202 drivers/i2c/busses/i2c-nomadik.c static inline void i2c_clr_bit(void __iomem *reg, u32 mask) mask 204 drivers/i2c/busses/i2c-nomadik.c writel(readl(reg) & ~mask, reg); mask 252 drivers/i2c/busses/i2c-nomadik.c u32 mask = IRQ_MASK(0); mask 253 drivers/i2c/busses/i2c-nomadik.c writel(mask, dev->virtbase + I2C_IMSCR); mask 262 drivers/i2c/busses/i2c-nomadik.c u32 mask; mask 263 drivers/i2c/busses/i2c-nomadik.c mask = IRQ_MASK(I2C_CLEAR_ALL_INTS); mask 264 drivers/i2c/busses/i2c-nomadik.c writel(mask, dev->virtbase + I2C_ICR); mask 1088 drivers/i2c/busses/i2c-nomadik.c .mask = 0x00ffffff, mask 1093 drivers/i2c/busses/i2c-nomadik.c .mask = 0x00ffffff, mask 281 drivers/i2c/busses/i2c-ocores.c int reg, u8 mask, u8 val, mask 290 drivers/i2c/busses/i2c-ocores.c if ((status & mask) == val) mask 309 drivers/i2c/busses/i2c-ocores.c u8 mask; mask 314 drivers/i2c/busses/i2c-ocores.c mask = OCI2C_STAT_BUSY; mask 317 drivers/i2c/busses/i2c-ocores.c mask = OCI2C_STAT_TIP; mask 329 drivers/i2c/busses/i2c-ocores.c err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); mask 333 drivers/i2c/busses/i2c-ocores.c __func__, mask); mask 647 drivers/i2c/busses/i2c-omap.c u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); mask 653 drivers/i2c/busses/i2c-omap.c } while (!(stat & mask) && count < 5); mask 1057 drivers/i2c/busses/i2c-omap.c u16 mask; mask 1061 drivers/i2c/busses/i2c-omap.c mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); mask 1063 drivers/i2c/busses/i2c-omap.c if (stat & mask) mask 229 drivers/i2c/busses/i2c-pxa.c u32 mask; mask 233 drivers/i2c/busses/i2c-pxa.c #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } mask 240 drivers/i2c/busses/i2c-pxa.c const char *str = val & bits->mask ? bits->set : bits->unset; mask 197 drivers/i2c/busses/i2c-st.c static inline void st_i2c_set_bits(void __iomem *reg, u32 mask) mask 199 drivers/i2c/busses/i2c-st.c writel_relaxed(readl_relaxed(reg) | mask, reg); mask 202 drivers/i2c/busses/i2c-st.c static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask) mask 204 drivers/i2c/busses/i2c-st.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); mask 134 drivers/i2c/busses/i2c-stm32f4.c static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask) mask 136 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(readl_relaxed(reg) | mask, reg); mask 139 drivers/i2c/busses/i2c-stm32f4.c static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask) mask 141 drivers/i2c/busses/i2c-stm32f4.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); mask 438 drivers/i2c/busses/i2c-stm32f4.c u32 mask; mask 461 drivers/i2c/busses/i2c-stm32f4.c mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; mask 462 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_clr_bits(reg, mask); mask 685 drivers/i2c/busses/i2c-stm32f4.c u32 mask; mask 697 drivers/i2c/busses/i2c-stm32f4.c mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN; mask 698 drivers/i2c/busses/i2c-stm32f4.c stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask); mask 361 drivers/i2c/busses/i2c-stm32f7.c static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) mask 363 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(readl_relaxed(reg) | mask, reg); mask 366 drivers/i2c/busses/i2c-stm32f7.c static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) mask 368 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); mask 371 drivers/i2c/busses/i2c-stm32f7.c static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) mask 373 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); mask 624 drivers/i2c/busses/i2c-stm32f7.c u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; mask 626 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); mask 1173 drivers/i2c/busses/i2c-stm32f7.c u32 mask; mask 1184 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR2_RELOAD; mask 1185 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); mask 1186 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | mask 1188 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); mask 1191 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | mask 1193 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); mask 1202 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR2_RELOAD; mask 1203 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); mask 1210 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | mask 1213 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); mask 1220 drivers/i2c/busses/i2c-stm32f7.c u32 isr, addcode, dir, mask; mask 1236 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_ICR_ADDRCF; mask 1237 drivers/i2c/busses/i2c-stm32f7.c writel_relaxed(mask, base + STM32F7_I2C_ICR); mask 1312 drivers/i2c/busses/i2c-stm32f7.c u32 cr2, status, mask; mask 1343 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR2_NACK; mask 1344 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); mask 1364 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_ISR_TXE; mask 1365 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); mask 1389 drivers/i2c/busses/i2c-stm32f7.c u32 status, mask; mask 1419 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_XFER_IRQ_MASK; mask 1421 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_ALL_IRQ_MASK; mask 1422 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_disable_irq(i2c_dev, mask); mask 1438 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR2_STOP; mask 1439 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); mask 1532 drivers/i2c/busses/i2c-stm32f7.c u32 mask; mask 1535 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_XFER_IRQ_MASK; mask 1537 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_ALL_IRQ_MASK; mask 1538 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_disable_irq(i2c_dev, mask); mask 1679 drivers/i2c/busses/i2c-stm32f7.c u32 oar1, oar2, mask; mask 1735 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | mask 1737 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); mask 1751 drivers/i2c/busses/i2c-stm32f7.c u32 mask; mask 1765 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_OAR1_OA1EN; mask 1766 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); mask 1768 drivers/i2c/busses/i2c-stm32f7.c mask = STM32F7_I2C_OAR2_OA2EN; mask 1769 drivers/i2c/busses/i2c-stm32f7.c stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); mask 1788 drivers/i2c/busses/i2c-stm32f7.c u32 reg, mask; mask 1800 drivers/i2c/busses/i2c-stm32f7.c ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask); mask 1804 drivers/i2c/busses/i2c-stm32f7.c return regmap_update_bits(i2c_dev->regmap, reg, mask, mask); mask 334 drivers/i2c/busses/i2c-tegra.c static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) mask 338 drivers/i2c/busses/i2c-tegra.c int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; mask 342 drivers/i2c/busses/i2c-tegra.c static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) mask 346 drivers/i2c/busses/i2c-tegra.c int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; mask 459 drivers/i2c/busses/i2c-tegra.c u32 mask, val; mask 462 drivers/i2c/busses/i2c-tegra.c mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | mask 466 drivers/i2c/busses/i2c-tegra.c mask = I2C_FIFO_CONTROL_TX_FLUSH | mask 472 drivers/i2c/busses/i2c-tegra.c val |= mask; mask 475 drivers/i2c/busses/i2c-tegra.c while (i2c_readl(i2c_dev, offset) & mask) { mask 136 drivers/i2c/busses/i2c-uniphier-f.c u32 mask) mask 138 drivers/i2c/busses/i2c-uniphier-f.c writel(mask, priv->membase + UNIPHIER_FI2C_IC); mask 127 drivers/i2c/busses/i2c-xgene-slimpro.c static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask) mask 132 drivers/i2c/busses/i2c-xgene-slimpro.c ret = val & mask; mask 133 drivers/i2c/busses/i2c-xgene-slimpro.c val &= ~mask; mask 224 drivers/i2c/busses/i2c-xiic.c static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) mask 227 drivers/i2c/busses/i2c-xiic.c xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); mask 230 drivers/i2c/busses/i2c-xiic.c static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) mask 233 drivers/i2c/busses/i2c-xiic.c xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); mask 236 drivers/i2c/busses/i2c-xiic.c static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) mask 239 drivers/i2c/busses/i2c-xiic.c xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); mask 242 drivers/i2c/busses/i2c-xiic.c static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) mask 244 drivers/i2c/busses/i2c-xiic.c xiic_irq_clr(i2c, mask); mask 245 drivers/i2c/busses/i2c-xiic.c xiic_irq_en(i2c, mask); mask 115 drivers/i2c/busses/i2c-xlp9xx.c static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) mask 119 drivers/i2c/busses/i2c-xlp9xx.c inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask; mask 123 drivers/i2c/busses/i2c-xlp9xx.c static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask) mask 127 drivers/i2c/busses/i2c-xlp9xx.c inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask; mask 167 drivers/ide/aec62xx.c u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01; mask 171 drivers/ide/aec62xx.c return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; mask 295 drivers/ide/cmd64x.c u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01; mask 301 drivers/ide/cmd64x.c return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; mask 86 drivers/ide/cs5530.c u8 mask = hwif->ultra_mask; mask 97 drivers/ide/cs5530.c mask = 0; mask 100 drivers/ide/cs5530.c return mask; mask 557 drivers/ide/hpt366.c u8 mask = hwif->ultra_mask; mask 563 drivers/ide/hpt366.c mask = ATA_UDMA3; mask 567 drivers/ide/hpt366.c mask = ATA_UDMA2; mask 572 drivers/ide/hpt366.c mask = ATA_UDMA4; mask 584 drivers/ide/hpt366.c mask &= ~0x0e; mask 587 drivers/ide/hpt366.c return mask; mask 590 drivers/ide/hpt366.c return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask; mask 658 drivers/ide/hpt366.c static void hpt3xx_maskproc(ide_drive_t *drive, int mask) mask 671 drivers/ide/hpt366.c if (((scr1 & 0x10) >> 4) != mask) { mask 672 drivers/ide/hpt366.c if (mask) mask 678 drivers/ide/hpt366.c } else if (mask) mask 779 drivers/ide/hpt366.c u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; mask 783 drivers/ide/hpt366.c if (bwsr & mask) mask 168 drivers/ide/icside.c static void icside_maskproc(ide_drive_t *drive, int mask) mask 179 drivers/ide/icside.c if (state->enabled && !mask) { mask 1305 drivers/ide/ide-cd.c devinfo->mask |= CDC_SELECT_SPEED; mask 1322 drivers/ide/ide-cd.c cdi->mask = (CDC_CD_R | CDC_CD_RW | CDC_DVD | CDC_DVD_R | mask 1327 drivers/ide/ide-cd.c cdi->mask &= ~(CDC_MO_DRIVE | CDC_RAM); mask 1335 drivers/ide/ide-cd.c cdi->mask &= ~CDC_PLAY_AUDIO; mask 1356 drivers/ide/ide-cd.c cdi->mask &= ~CDC_CD_R; mask 1358 drivers/ide/ide-cd.c cdi->mask &= ~(CDC_CD_RW | CDC_RAM); mask 1360 drivers/ide/ide-cd.c cdi->mask &= ~CDC_DVD; mask 1362 drivers/ide/ide-cd.c cdi->mask &= ~(CDC_DVD_RAM | CDC_RAM); mask 1364 drivers/ide/ide-cd.c cdi->mask &= ~CDC_DVD_R; mask 1366 drivers/ide/ide-cd.c cdi->mask &= ~CDC_PLAY_AUDIO; mask 1372 drivers/ide/ide-cd.c cdi->mask |= CDC_CLOSE_TRAY; mask 1375 drivers/ide/ide-cd.c cdi->mask &= ~CDC_SELECT_DISC; mask 1381 drivers/ide/ide-cd.c cdi->mask &= ~CDC_SELECT_DISC; mask 1392 drivers/ide/ide-cd.c printk(KERN_CONT " %s", (cdi->mask & CDC_DVD) ? "CD-ROM" : "DVD-ROM"); mask 1394 drivers/ide/ide-cd.c if ((cdi->mask & CDC_DVD_R) == 0 || (cdi->mask & CDC_DVD_RAM) == 0) mask 1396 drivers/ide/ide-cd.c (cdi->mask & CDC_DVD_R) ? "" : "-R", mask 1397 drivers/ide/ide-cd.c (cdi->mask & CDC_DVD_RAM) ? "" : "/RAM"); mask 1399 drivers/ide/ide-cd.c if ((cdi->mask & CDC_CD_R) == 0 || (cdi->mask & CDC_CD_RW) == 0) mask 1401 drivers/ide/ide-cd.c (cdi->mask & CDC_CD_R) ? "" : "-R", mask 1402 drivers/ide/ide-cd.c (cdi->mask & CDC_CD_RW) ? "" : "/RW"); mask 1404 drivers/ide/ide-cd.c if ((cdi->mask & CDC_SELECT_DISC) == 0) mask 124 drivers/ide/ide-cd_ioctl.c if (ejectflag && (cdi->mask & CDC_CLOSE_TRAY)) mask 226 drivers/ide/ide-cd_ioctl.c if ((cdi->mask & (CDC_CD_R | CDC_CD_RW | CDC_DVD_R)) != mask 242 drivers/ide/ide-dma.c unsigned int mask = 0; mask 248 drivers/ide/ide-dma.c mask = id[ATA_ID_UDMA_MODES]; mask 250 drivers/ide/ide-dma.c mask &= port_ops->udma_filter(drive); mask 252 drivers/ide/ide-dma.c mask &= hwif->ultra_mask; mask 258 drivers/ide/ide-dma.c if ((mask & 0x78) && (eighty_ninty_three(drive) == 0)) mask 259 drivers/ide/ide-dma.c mask &= 0x07; mask 263 drivers/ide/ide-dma.c mask = id[ATA_ID_MWDMA_MODES]; mask 269 drivers/ide/ide-dma.c mask |= ((2 << mode) - 1) << 3; mask 273 drivers/ide/ide-dma.c mask &= port_ops->mdma_filter(drive); mask 275 drivers/ide/ide-dma.c mask &= hwif->mwdma_mask; mask 278 drivers/ide/ide-dma.c mask = id[ATA_ID_SWDMA_MODES]; mask 279 drivers/ide/ide-dma.c if (!(mask & ATA_SWDMA2) && (id[ATA_ID_OLD_DMA_MODES] >> 8)) { mask 287 drivers/ide/ide-dma.c mask = (2 << mode) - 1; mask 289 drivers/ide/ide-dma.c mask &= hwif->swdma_mask; mask 296 drivers/ide/ide-dma.c return mask; mask 314 drivers/ide/ide-dma.c unsigned int mask; mask 326 drivers/ide/ide-dma.c mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode); mask 327 drivers/ide/ide-dma.c x = fls(mask) - 1; mask 31 drivers/ide/ide-iops.c void SELECT_MASK(ide_drive_t *drive, int mask) mask 36 drivers/ide/ide-iops.c port_ops->maskproc(drive, mask); mask 110 drivers/ide/pdc202xx_old.c u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); mask 114 drivers/ide/pdc202xx_old.c return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; mask 275 drivers/ide/piix.c u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30; mask 289 drivers/ide/piix.c return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; mask 109 drivers/ide/sc1200.c u8 mask = hwif->ultra_mask; mask 120 drivers/ide/sc1200.c mask = 0; mask 123 drivers/ide/sc1200.c return mask; mask 75 drivers/ide/serverworks.c u8 btr = 0, mode, mask; mask 86 drivers/ide/serverworks.c case 3: mask = 0x3f; break; mask 87 drivers/ide/serverworks.c case 2: mask = 0x1f; break; mask 88 drivers/ide/serverworks.c case 1: mask = 0x07; break; mask 89 drivers/ide/serverworks.c default: mask = 0x00; break; mask 92 drivers/ide/serverworks.c return mask; mask 470 drivers/ide/setup-pci.c (tmp & e->mask) != e->val)) { mask 200 drivers/ide/siimage.c u8 scsc, mask = 0; mask 208 drivers/ide/siimage.c mask = ATA_UDMA6; mask 211 drivers/ide/siimage.c mask = ATA_UDMA6; mask 214 drivers/ide/siimage.c mask = ATA_UDMA5; mask 220 drivers/ide/siimage.c return mask; mask 546 drivers/ide/sis5513.c u8 mask = hwif->channel ? 0x20 : 0x10; mask 548 drivers/ide/sis5513.c ata66 = (reg48h & mask) ? 0 : 1; mask 117 drivers/ide/sl82c105.c u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; mask 121 drivers/ide/sl82c105.c return (val & mask) ? 1 : 0; mask 152 drivers/ide/sl82c105.c u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA; mask 161 drivers/ide/sl82c105.c if (val & mask) mask 122 drivers/ide/slc90e66.c u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02; mask 127 drivers/ide/slc90e66.c return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; mask 110 drivers/ide/tx4939ide.c u32 mask, val; mask 122 drivers/ide/tx4939ide.c mask = is_slave ? 0x07f00000 : 0x000007f0; mask 124 drivers/ide/tx4939ide.c hwif->select_data = (hwif->select_data & ~mask) | val; mask 130 drivers/ide/tx4939ide.c u32 mask, val; mask 139 drivers/ide/tx4939ide.c mask = 0x00f00000; mask 142 drivers/ide/tx4939ide.c mask = 0x000000f0; mask 145 drivers/ide/tx4939ide.c hwif->select_data = (hwif->select_data & ~mask) | val; mask 103 drivers/iio/accel/adis16201.c long mask) mask 111 drivers/iio/accel/adis16201.c switch (mask) { mask 184 drivers/iio/accel/adis16201.c long mask) mask 189 drivers/iio/accel/adis16201.c if (mask != IIO_CHAN_INFO_CALIBBIAS) mask 111 drivers/iio/accel/adis16209.c long mask) mask 116 drivers/iio/accel/adis16209.c if (mask != IIO_CHAN_INFO_CALIBBIAS) mask 135 drivers/iio/accel/adis16209.c long mask) mask 143 drivers/iio/accel/adis16209.c switch (mask) { mask 87 drivers/iio/accel/adxl345_core.c int *val, int *val2, long mask) mask 95 drivers/iio/accel/adxl345_core.c switch (mask) { mask 151 drivers/iio/accel/adxl345_core.c int val, int val2, long mask) mask 156 drivers/iio/accel/adxl345_core.c switch (mask) { mask 179 drivers/iio/accel/adxl345_core.c long mask) mask 181 drivers/iio/accel/adxl345_core.c switch (mask) { mask 795 drivers/iio/accel/adxl372.c unsigned int mask; mask 806 drivers/iio/accel/adxl372.c mask = *indio_dev->active_scan_mask; mask 809 drivers/iio/accel/adxl372.c if (mask == adxl372_axis_lookup_table[i].bits) mask 867 drivers/iio/accel/adxl372.c unsigned long int mask = 0; mask 870 drivers/iio/accel/adxl372.c mask = ADXL372_INT1_MAP_FIFO_FULL_MSK; mask 872 drivers/iio/accel/adxl372.c return adxl372_set_interrupts(st, mask, 0); mask 164 drivers/iio/accel/bma180.c static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val) mask 167 drivers/iio/accel/bma180.c u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1)); mask 464 drivers/iio/accel/bma180.c long mask) mask 469 drivers/iio/accel/bma180.c switch (mask) { mask 508 drivers/iio/accel/bma180.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 513 drivers/iio/accel/bma180.c switch (mask) { mask 123 drivers/iio/accel/bma220_spi.c int *val, int *val2, long mask) mask 129 drivers/iio/accel/bma220_spi.c switch (mask) { mask 151 drivers/iio/accel/bma220_spi.c int val, int val2, long mask) mask 158 drivers/iio/accel/bma220_spi.c switch (mask) { mask 574 drivers/iio/accel/bmc150-accel-core.c int *val, int *val2, long mask) mask 579 drivers/iio/accel/bmc150-accel-core.c switch (mask) { mask 635 drivers/iio/accel/bmc150-accel-core.c int val, int val2, long mask) mask 640 drivers/iio/accel/bmc150-accel-core.c switch (mask) { mask 72 drivers/iio/accel/cros_ec_accel_legacy.c int *val, int *val2, long mask) mask 81 drivers/iio/accel/cros_ec_accel_legacy.c switch (mask) { mask 102 drivers/iio/accel/cros_ec_accel_legacy.c mask); mask 112 drivers/iio/accel/cros_ec_accel_legacy.c int val, int val2, long mask) mask 118 drivers/iio/accel/cros_ec_accel_legacy.c if (mask == IIO_CHAN_INFO_CALIBBIAS) mask 63 drivers/iio/accel/da280.c int *val, int *val2, long mask) mask 68 drivers/iio/accel/da280.c switch (mask) { mask 101 drivers/iio/accel/da311.c u8 mask, u8 data) mask 113 drivers/iio/accel/da311.c if (mask != 0xff) { mask 120 drivers/iio/accel/da311.c tmp_data &= ~mask; mask 121 drivers/iio/accel/da311.c tmp_data |= data & mask; mask 141 drivers/iio/accel/da311.c u8 mask; mask 167 drivers/iio/accel/da311.c init_data[i].mask, mask 186 drivers/iio/accel/da311.c int *val, int *val2, long mask) mask 191 drivers/iio/accel/da311.c switch (mask) { mask 68 drivers/iio/accel/dmard06.c int *val, int *val2, long mask) mask 73 drivers/iio/accel/dmard06.c switch (mask) { mask 51 drivers/iio/accel/dmard09.c int *val, int *val2, long mask) mask 58 drivers/iio/accel/dmard09.c switch (mask) { mask 140 drivers/iio/accel/dmard10.c int *val, int *val2, long mask) mask 146 drivers/iio/accel/dmard10.c switch (mask) { mask 133 drivers/iio/accel/hid-sensor-accel-3d.c long mask) mask 145 drivers/iio/accel/hid-sensor-accel-3d.c switch (mask) { mask 196 drivers/iio/accel/hid-sensor-accel-3d.c long mask) mask 201 drivers/iio/accel/hid-sensor-accel-3d.c switch (mask) { mask 748 drivers/iio/accel/kxcjk-1013.c int *val2, long mask) mask 753 drivers/iio/accel/kxcjk-1013.c switch (mask) { mask 798 drivers/iio/accel/kxcjk-1013.c int val2, long mask) mask 803 drivers/iio/accel/kxcjk-1013.c switch (mask) { mask 139 drivers/iio/accel/kxsd9.c long mask) mask 146 drivers/iio/accel/kxsd9.c if (mask == IIO_CHAN_INFO_SCALE) { mask 161 drivers/iio/accel/kxsd9.c int *val, int *val2, long mask) mask 171 drivers/iio/accel/kxsd9.c switch (mask) { mask 84 drivers/iio/accel/mc3230.c int *val, int *val2, long mask) mask 89 drivers/iio/accel/mc3230.c switch (mask) { mask 108 drivers/iio/accel/mma7455_core.c int *val, int *val2, long mask) mask 115 drivers/iio/accel/mma7455_core.c switch (mask) { mask 157 drivers/iio/accel/mma7455_core.c int val, int val2, long mask) mask 162 drivers/iio/accel/mma7455_core.c switch (mask) { mask 142 drivers/iio/accel/mma7660.c int *val, int *val2, long mask) mask 147 drivers/iio/accel/mma7660.c switch (mask) { mask 484 drivers/iio/accel/mma8452.c int *val, int *val2, long mask) mask 490 drivers/iio/accel/mma8452.c switch (mask) { mask 704 drivers/iio/accel/mma8452.c int val, int val2, long mask) mask 713 drivers/iio/accel/mma8452.c switch (mask) { mask 108 drivers/iio/accel/mma9551.c int *val, int *val2, long mask) mask 113 drivers/iio/accel/mma9551.c switch (mask) { mask 50 drivers/iio/accel/mma9551_core.c #define MMA9551_RSC_OFFSET(mask) (3 - (ffs(mask) - 1) / 8) mask 51 drivers/iio/accel/mma9551_core.c #define MMA9551_RSC_VAL(mask) (mask >> (((ffs(mask) - 1) / 8) * 8)) mask 493 drivers/iio/accel/mma9551_core.c u16 reg, u8 mask, u8 val) mask 502 drivers/iio/accel/mma9551_core.c tmp = orig & ~mask; mask 503 drivers/iio/accel/mma9551_core.c tmp |= val & mask; mask 60 drivers/iio/accel/mma9551_core.h u16 reg, u8 mask, u8 val); mask 194 drivers/iio/accel/mma9553.c static u8 mma9553_get_bits(u16 val, u16 mask) mask 196 drivers/iio/accel/mma9553.c return (val & mask) >> (ffs(mask) - 1); mask 199 drivers/iio/accel/mma9553.c static u16 mma9553_set_bits(u16 current_val, u16 val, u16 mask) mask 201 drivers/iio/accel/mma9553.c return (current_val & ~mask) | (val << (ffs(mask) - 1)); mask 264 drivers/iio/accel/mma9553.c u16 *p_reg_val, u16 val, u16 mask) mask 270 drivers/iio/accel/mma9553.c if (val == mma9553_get_bits(reg_val, mask)) mask 273 drivers/iio/accel/mma9553.c reg_val = mma9553_set_bits(reg_val, val, mask); mask 464 drivers/iio/accel/mma9553.c int *val, int *val2, long mask) mask 471 drivers/iio/accel/mma9553.c switch (mask) { mask 607 drivers/iio/accel/mma9553.c int val, int val2, long mask) mask 612 drivers/iio/accel/mma9553.c switch (mask) { mask 207 drivers/iio/accel/mxc4005.c int *val, int *val2, long mask) mask 212 drivers/iio/accel/mxc4005.c switch (mask) { mask 243 drivers/iio/accel/mxc4005.c int val, int val2, long mask) mask 247 drivers/iio/accel/mxc4005.c switch (mask) { mask 51 drivers/iio/accel/mxc6255.c int *val, int *val2, long mask) mask 57 drivers/iio/accel/mxc6255.c switch (mask) { mask 713 drivers/iio/accel/sca3000.c long mask) mask 719 drivers/iio/accel/sca3000.c switch (mask) { mask 778 drivers/iio/accel/sca3000.c int val, int val2, long mask) mask 783 drivers/iio/accel/sca3000.c switch (mask) { mask 29 drivers/iio/accel/ssp_accel_sensor.c int *val2, long mask) mask 34 drivers/iio/accel/ssp_accel_sensor.c switch (mask) { mask 48 drivers/iio/accel/ssp_accel_sensor.c int val2, long mask) mask 53 drivers/iio/accel/ssp_accel_sensor.c switch (mask) { mask 110 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 124 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 129 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 133 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 159 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 164 drivers/iio/accel/st_accel_core.c .mask = 0x10, mask 170 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 192 drivers/iio/accel/st_accel_core.c .mask = 0x18, mask 202 drivers/iio/accel/st_accel_core.c .mask = 0xe0, mask 208 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 212 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 233 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 238 drivers/iio/accel/st_accel_core.c .mask = 0x02, mask 244 drivers/iio/accel/st_accel_core.c .mask = 0x10, mask 252 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 271 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 287 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 292 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 296 drivers/iio/accel/st_accel_core.c .mask = 0x38, mask 327 drivers/iio/accel/st_accel_core.c .mask = 0x08, mask 332 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 338 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 361 drivers/iio/accel/st_accel_core.c .mask = 0x30, /* DF1 and DF0 */ mask 371 drivers/iio/accel/st_accel_core.c .mask = 0xc0, mask 377 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 381 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 397 drivers/iio/accel/st_accel_core.c .mask = 0x40, mask 405 drivers/iio/accel/st_accel_core.c .mask = 0x01, mask 410 drivers/iio/accel/st_accel_core.c .mask = 0x04, mask 414 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 433 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 441 drivers/iio/accel/st_accel_core.c .mask = 0x40, mask 447 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 451 drivers/iio/accel/st_accel_core.c .mask = 0x20, mask 472 drivers/iio/accel/st_accel_core.c .mask = 0x04, mask 478 drivers/iio/accel/st_accel_core.c .mask = 0x20, mask 486 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 505 drivers/iio/accel/st_accel_core.c .mask = 0x18, mask 515 drivers/iio/accel/st_accel_core.c .mask = 0x20, mask 521 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 525 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 546 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 551 drivers/iio/accel/st_accel_core.c .mask = 0x02, mask 555 drivers/iio/accel/st_accel_core.c .mask = 0x10, mask 575 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 585 drivers/iio/accel/st_accel_core.c .mask = 0xc0, mask 591 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 610 drivers/iio/accel/st_accel_core.c .mask = 0x04, mask 614 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 633 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 647 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 652 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 656 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 683 drivers/iio/accel/st_accel_core.c .mask = 0x10, mask 689 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 708 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 720 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 725 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 751 drivers/iio/accel/st_accel_core.c .mask = 0x08, mask 756 drivers/iio/accel/st_accel_core.c .mask = 0x01, mask 762 drivers/iio/accel/st_accel_core.c .mask = 0x01, mask 770 drivers/iio/accel/st_accel_core.c .mask = 0x01, mask 795 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 809 drivers/iio/accel/st_accel_core.c .mask = 0x01, mask 814 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 820 drivers/iio/accel/st_accel_core.c .mask = 0x80, mask 826 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 841 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 856 drivers/iio/accel/st_accel_core.c .mask = 0xf0, mask 861 drivers/iio/accel/st_accel_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 865 drivers/iio/accel/st_accel_core.c .mask = 0x30, mask 892 drivers/iio/accel/st_accel_core.c .mask = 0x10, mask 898 drivers/iio/accel/st_accel_core.c .mask = 0x07, mask 912 drivers/iio/accel/st_accel_core.c int *val2, long mask) mask 917 drivers/iio/accel/st_accel_core.c switch (mask) { mask 940 drivers/iio/accel/st_accel_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 944 drivers/iio/accel/st_accel_core.c switch (mask) { mask 333 drivers/iio/accel/stk8312.c int *val, int *val2, long mask) mask 338 drivers/iio/accel/stk8312.c switch (mask) { mask 377 drivers/iio/accel/stk8312.c int val, int val2, long mask) mask 384 drivers/iio/accel/stk8312.c switch (mask) { mask 210 drivers/iio/accel/stk8ba50.c int *val, int *val2, long mask) mask 215 drivers/iio/accel/stk8ba50.c switch (mask) { mask 251 drivers/iio/accel/stk8ba50.c int val, int val2, long mask) mask 258 drivers/iio/accel/stk8ba50.c switch (mask) { mask 181 drivers/iio/adc/ad7124.c unsigned long mask, mask 192 drivers/iio/adc/ad7124.c readval &= ~mask; mask 278 drivers/iio/adc/ad7291.c unsigned int mask; mask 289 drivers/iio/adc/ad7291.c mask = BIT(15 - chan->channel); mask 293 drivers/iio/adc/ad7291.c if ((!state) && (chip->c_mask & mask)) mask 294 drivers/iio/adc/ad7291.c chip->c_mask &= ~mask; mask 295 drivers/iio/adc/ad7291.c else if (state && (!(chip->c_mask & mask))) mask 296 drivers/iio/adc/ad7291.c chip->c_mask |= mask; mask 324 drivers/iio/adc/ad7291.c long mask) mask 330 drivers/iio/adc/ad7291.c switch (mask) { mask 257 drivers/iio/adc/ad7606.c long mask) mask 262 drivers/iio/adc/ad7606.c switch (mask) { mask 147 drivers/iio/adc/ad7606.h unsigned long mask, mask 161 drivers/iio/adc/ad7606_spi.c unsigned long mask, mask 170 drivers/iio/adc/ad7606_spi.c readval &= ~mask; mask 264 drivers/iio/adc/ad7791.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 273 drivers/iio/adc/ad7791.c switch (mask) { mask 468 drivers/iio/adc/ad7793.c long mask) mask 478 drivers/iio/adc/ad7793.c switch (mask) { mask 527 drivers/iio/adc/ad7793.c long mask) mask 61 drivers/iio/adc/ad7949.c u16 mask) mask 75 drivers/iio/adc/ad7949.c ad7949_adc->cfg = (val & mask) | (ad7949_adc->cfg & ~mask); mask 94 drivers/iio/adc/ad7949.c int mask = GENMASK(ad7949_adc->resolution, 0); mask 135 drivers/iio/adc/ad7949.c *val = ad7949_adc->buffer & mask; mask 161 drivers/iio/adc/ad7949.c int *val, int *val2, long mask) mask 169 drivers/iio/adc/ad7949.c switch (mask) { mask 92 drivers/iio/adc/aspeed_adc.c int *val, int *val2, long mask) mask 98 drivers/iio/adc/aspeed_adc.c switch (mask) { mask 120 drivers/iio/adc/aspeed_adc.c int val, int val2, long mask) mask 126 drivers/iio/adc/aspeed_adc.c switch (mask) { mask 1388 drivers/iio/adc/at91-sama5d2_adc.c int *val, int *val2, long mask) mask 1392 drivers/iio/adc/at91-sama5d2_adc.c switch (mask) { mask 1417 drivers/iio/adc/at91-sama5d2_adc.c int val, int val2, long mask) mask 1421 drivers/iio/adc/at91-sama5d2_adc.c switch (mask) { mask 688 drivers/iio/adc/at91_adc.c int *val, int *val2, long mask) mask 693 drivers/iio/adc/at91_adc.c switch (mask) { mask 468 drivers/iio/adc/axp20x_adc.c int *val2, long mask) mask 470 drivers/iio/adc/axp20x_adc.c switch (mask) { mask 487 drivers/iio/adc/axp20x_adc.c int *val2, long mask) mask 489 drivers/iio/adc/axp20x_adc.c switch (mask) { mask 507 drivers/iio/adc/axp20x_adc.c int *val2, long mask) mask 509 drivers/iio/adc/axp20x_adc.c switch (mask) { mask 527 drivers/iio/adc/axp20x_adc.c long mask) mask 536 drivers/iio/adc/axp20x_adc.c if (mask != IIO_CHAN_INFO_OFFSET) mask 159 drivers/iio/adc/axp288_adc.c int *val, int *val2, long mask) mask 165 drivers/iio/adc/axp288_adc.c switch (mask) { mask 230 drivers/iio/adc/bcm_iproc_adc.c u32 mask; mask 256 drivers/iio/adc/bcm_iproc_adc.c mask = IPROC_ADC_CHANNEL_ROUNDS_MASK | IPROC_ADC_CHANNEL_MODE_MASK | mask 260 drivers/iio/adc/bcm_iproc_adc.c mask, val); mask 456 drivers/iio/adc/bcm_iproc_adc.c long mask) mask 461 drivers/iio/adc/bcm_iproc_adc.c switch (mask) { mask 204 drivers/iio/adc/berlin2-adc.c int *val2, long mask) mask 208 drivers/iio/adc/berlin2-adc.c switch (mask) { mask 216 drivers/iio/adc/cc10001_adc.c int *val, int *val2, long mask) mask 221 drivers/iio/adc/cc10001_adc.c switch (mask) { mask 865 drivers/iio/adc/cpcap-adc.c int *val, int *val2, long mask) mask 875 drivers/iio/adc/cpcap-adc.c switch (mask) { mask 224 drivers/iio/adc/da9150-gpadc.c int *val, int *val2, long mask) mask 232 drivers/iio/adc/da9150-gpadc.c switch (mask) { mask 332 drivers/iio/adc/dln2-adc.c long mask) mask 338 drivers/iio/adc/dln2-adc.c switch (mask) { mask 380 drivers/iio/adc/dln2-adc.c long mask) mask 386 drivers/iio/adc/dln2-adc.c switch (mask) { mask 189 drivers/iio/adc/envelope-detector.c int *val, int *val2, long mask) mask 194 drivers/iio/adc/envelope-detector.c switch (mask) { mask 80 drivers/iio/adc/ep93xx_adc.c int *shift, long mask) mask 86 drivers/iio/adc/ep93xx_adc.c switch (mask) { mask 148 drivers/iio/adc/exynos_adc.c u32 mask; mask 265 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 277 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 289 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 316 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 337 drivers/iio/adc/exynos_adc.c .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ mask 357 drivers/iio/adc/exynos_adc.c .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ mask 366 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 425 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 437 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 469 drivers/iio/adc/exynos_adc.c .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ mask 528 drivers/iio/adc/exynos_adc.c long mask) mask 534 drivers/iio/adc/exynos_adc.c if (mask != IIO_CHAN_INFO_RAW) mask 601 drivers/iio/adc/exynos_adc.c u32 mask = info->data->mask; mask 609 drivers/iio/adc/exynos_adc.c info->value = readl(ADC_V1_DATX(info->regs)) & mask; mask 133 drivers/iio/adc/fsl-imx25-gcq.c int *val2, long mask) mask 138 drivers/iio/adc/fsl-imx25-gcq.c switch (mask) { mask 106 drivers/iio/adc/hi8435.c int *val, int *val2, long mask) mask 112 drivers/iio/adc/hi8435.c switch (mask) { mask 284 drivers/iio/adc/hx711.c int *val, int *val2, long mask) mask 288 drivers/iio/adc/hx711.c switch (mask) { mask 317 drivers/iio/adc/hx711.c long mask) mask 323 drivers/iio/adc/hx711.c switch (mask) { mask 363 drivers/iio/adc/hx711.c long mask) mask 286 drivers/iio/adc/imx7d_adc.c long mask) mask 293 drivers/iio/adc/imx7d_adc.c switch (mask) { mask 174 drivers/iio/adc/ina2xx-adc.c int *val, int *val2, long mask) mask 180 drivers/iio/adc/ina2xx-adc.c switch (mask) { mask 447 drivers/iio/adc/ina2xx-adc.c long mask) mask 449 drivers/iio/adc/ina2xx-adc.c switch (mask) { mask 471 drivers/iio/adc/ina2xx-adc.c int val, int val2, long mask) mask 488 drivers/iio/adc/ina2xx-adc.c switch (mask) { mask 62 drivers/iio/adc/ingenic-adc.c uint32_t mask, mask 70 drivers/iio/adc/ingenic-adc.c cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask; mask 96 drivers/iio/adc/lp8788_adc.c int *val, int *val2, long mask) mask 104 drivers/iio/adc/lp8788_adc.c switch (mask) { mask 90 drivers/iio/adc/lpc18xx_adc.c int *val, int *val2, long mask) mask 94 drivers/iio/adc/lpc18xx_adc.c switch (mask) { mask 59 drivers/iio/adc/lpc32xx_adc.c long mask) mask 64 drivers/iio/adc/lpc32xx_adc.c switch (mask) { mask 58 drivers/iio/adc/ltc2485.c int *val, int *val2, long mask) mask 63 drivers/iio/adc/ltc2485.c if (mask == IIO_CHAN_INFO_RAW) { mask 70 drivers/iio/adc/ltc2485.c } else if (mask == IIO_CHAN_INFO_SCALE) { mask 100 drivers/iio/adc/ltc2497.c int *val, int *val2, long mask) mask 105 drivers/iio/adc/ltc2497.c switch (mask) { mask 267 drivers/iio/adc/max1027.c int *val, int *val2, long mask) mask 274 drivers/iio/adc/max1027.c switch (mask) { mask 128 drivers/iio/adc/max1118.c int *val, int *val2, long mask) mask 132 drivers/iio/adc/max1118.c switch (mask) { mask 299 drivers/iio/adc/max1363.c *max1363_match_mode(const unsigned long *mask, mask 303 drivers/iio/adc/max1363.c if (mask) mask 305 drivers/iio/adc/max1363.c if (bitmap_subset(mask, mask 791 drivers/iio/adc/max1363.c unsigned long mask, loc; mask 797 drivers/iio/adc/max1363.c mask = rx; mask 798 drivers/iio/adc/max1363.c for_each_set_bit(loc, &mask, 8) mask 303 drivers/iio/adc/max9611.c int *val, int *val2, long mask) mask 311 drivers/iio/adc/max9611.c switch (mask) { mask 195 drivers/iio/adc/mcp320x.c int *val2, long mask) mask 205 drivers/iio/adc/mcp320x.c switch (mask) { mask 157 drivers/iio/adc/mcp3422.c int *val2, long mask) mask 165 drivers/iio/adc/mcp3422.c switch (mask) { mask 191 drivers/iio/adc/mcp3422.c int val2, long mask) mask 200 drivers/iio/adc/mcp3422.c switch (mask) { mask 254 drivers/iio/adc/mcp3422.c struct iio_chan_spec const *chan, long mask) mask 256 drivers/iio/adc/mcp3422.c switch (mask) { mask 84 drivers/iio/adc/mcp3911.c static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, mask 94 drivers/iio/adc/mcp3911.c val &= mask; mask 95 drivers/iio/adc/mcp3911.c val |= tmp & ~mask; mask 101 drivers/iio/adc/mcp3911.c int *val2, long mask) mask 107 drivers/iio/adc/mcp3911.c switch (mask) { mask 153 drivers/iio/adc/mcp3911.c int val2, long mask) mask 159 drivers/iio/adc/mcp3911.c switch (mask) { mask 587 drivers/iio/adc/meson_saradc.c int *val, int *val2, long mask) mask 592 drivers/iio/adc/meson_saradc.c switch (mask) { mask 538 drivers/iio/adc/mxs-lradc-adc.c const unsigned long *mask) mask 542 drivers/iio/adc/mxs-lradc-adc.c const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS); mask 559 drivers/iio/adc/mxs-lradc-adc.c if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS)) mask 291 drivers/iio/adc/nau7802.c int *val, int *val2, long mask) mask 296 drivers/iio/adc/nau7802.c switch (mask) { mask 361 drivers/iio/adc/nau7802.c int val, int val2, long mask) mask 366 drivers/iio/adc/nau7802.c switch (mask) { mask 398 drivers/iio/adc/nau7802.c long mask) mask 135 drivers/iio/adc/npcm_adc.c int *val2, long mask) mask 141 drivers/iio/adc/npcm_adc.c switch (mask) { mask 194 drivers/iio/adc/palmas_gpadc.c bool mask) mask 198 drivers/iio/adc/palmas_gpadc.c if (!mask) mask 216 drivers/iio/adc/palmas_gpadc.c unsigned int mask, val; mask 230 drivers/iio/adc/palmas_gpadc.c mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK | mask 239 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_CTRL1, mask, val); mask 246 drivers/iio/adc/palmas_gpadc.c mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK | mask 250 drivers/iio/adc/palmas_gpadc.c PALMAS_GPADC_SW_SELECT, mask, val); mask 383 drivers/iio/adc/palmas_gpadc.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) mask 394 drivers/iio/adc/palmas_gpadc.c switch (mask) { mask 408 drivers/iio/adc/palmas_gpadc.c if (mask == IIO_CHAN_INFO_PROCESSED) mask 649 drivers/iio/adc/qcom-pm8xxx-xoadc.c int *val, int *val2, long mask) mask 656 drivers/iio/adc/qcom-pm8xxx-xoadc.c switch (mask) { mask 382 drivers/iio/adc/qcom-spmi-adc5.c long mask) mask 391 drivers/iio/adc/qcom-spmi-adc5.c switch (mask) { mask 312 drivers/iio/adc/qcom-spmi-iadc.c int *val, int *val2, long mask) mask 319 drivers/iio/adc/qcom-spmi-iadc.c switch (mask) { mask 446 drivers/iio/adc/qcom-spmi-vadc.c long mask) mask 453 drivers/iio/adc/qcom-spmi-vadc.c switch (mask) { mask 181 drivers/iio/adc/rcar-gyroadc.c int *val, int *val2, long mask) mask 198 drivers/iio/adc/rcar-gyroadc.c switch (mask) { mask 56 drivers/iio/adc/rockchip_saradc.c int *val, int *val2, long mask) mask 61 drivers/iio/adc/rockchip_saradc.c switch (mask) { mask 328 drivers/iio/adc/sc27xx_adc.c int *val, int *val2, long mask) mask 334 drivers/iio/adc/sc27xx_adc.c switch (mask) { mask 369 drivers/iio/adc/sc27xx_adc.c int val, int val2, long mask) mask 373 drivers/iio/adc/sc27xx_adc.c switch (mask) { mask 388 drivers/iio/adc/sc27xx_adc.c #define SC27XX_ADC_CHANNEL(index, mask) { \ mask 391 drivers/iio/adc/sc27xx_adc.c .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \ mask 142 drivers/iio/adc/spear_adc.c long mask) mask 147 drivers/iio/adc/spear_adc.c switch (mask) { mask 182 drivers/iio/adc/spear_adc.c long mask) mask 187 drivers/iio/adc/spear_adc.c if (mask != IIO_CHAN_INFO_SAMP_FREQ) mask 112 drivers/iio/adc/stm32-adc.c int mask; mask 496 drivers/iio/adc/stm32-adc.c adc->cfg->regs->ier_eoc.mask); mask 506 drivers/iio/adc/stm32-adc.c adc->cfg->regs->ier_eoc.mask); mask 515 drivers/iio/adc/stm32-adc.c val = (val & ~res->mask) | (adc->res << res->shift); mask 978 drivers/iio/adc/stm32-adc.c val &= ~sqr[i].mask; mask 988 drivers/iio/adc/stm32-adc.c val &= ~sqr[0].mask; mask 1052 drivers/iio/adc/stm32-adc.c val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); mask 1130 drivers/iio/adc/stm32-adc.c val &= ~regs->sqr[1].mask; mask 1135 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); mask 1138 drivers/iio/adc/stm32-adc.c stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); mask 1167 drivers/iio/adc/stm32-adc.c int *val, int *val2, long mask) mask 1172 drivers/iio/adc/stm32-adc.c switch (mask) { mask 1214 drivers/iio/adc/stm32-adc.c if (status & regs->isr_eoc.mask) { mask 1604 drivers/iio/adc/stm32-adc.c u32 period_ns, shift = smpr->shift, mask = smpr->mask; mask 1616 drivers/iio/adc/stm32-adc.c adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); mask 1195 drivers/iio/adc/stm32-dfsdm-adc.c int val, int val2, long mask) mask 1202 drivers/iio/adc/stm32-dfsdm-adc.c switch (mask) { mask 1243 drivers/iio/adc/stm32-dfsdm-adc.c int *val2, long mask) mask 1248 drivers/iio/adc/stm32-dfsdm-adc.c switch (mask) { mask 137 drivers/iio/adc/stmpe-adc.c long mask) mask 142 drivers/iio/adc/stmpe-adc.c switch (mask) { mask 72 drivers/iio/adc/stx104.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) mask 79 drivers/iio/adc/stx104.c switch (mask) { mask 124 drivers/iio/adc/stx104.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 128 drivers/iio/adc/stx104.c switch (mask) { mask 228 drivers/iio/adc/stx104.c static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, mask 242 drivers/iio/adc/stx104.c const unsigned int mask = BIT(offset) >> 4; mask 251 drivers/iio/adc/stx104.c stx104gpio->out_state |= mask; mask 253 drivers/iio/adc/stx104.c stx104gpio->out_state &= ~mask; mask 266 drivers/iio/adc/stx104.c unsigned long *mask, unsigned long *bits) mask 272 drivers/iio/adc/stx104.c if (!(*mask & 0xF0)) mask 275 drivers/iio/adc/stx104.c *mask >>= 4; mask 280 drivers/iio/adc/stx104.c stx104gpio->out_state &= ~*mask; mask 281 drivers/iio/adc/stx104.c stx104gpio->out_state |= *mask & *bits; mask 308 drivers/iio/adc/sun4i-gpadc-iio.c int *val2, long mask) mask 312 drivers/iio/adc/sun4i-gpadc-iio.c switch (mask) { mask 42 drivers/iio/adc/ti-adc081c.c int *shift, long mask) mask 47 drivers/iio/adc/ti-adc081c.c switch (mask) { mask 164 drivers/iio/adc/ti-adc0832.c int *shift, long mask) mask 168 drivers/iio/adc/ti-adc0832.c switch (mask) { mask 86 drivers/iio/adc/ti-adc084s021.c int *val2, long mask) mask 91 drivers/iio/adc/ti-adc084s021.c switch (mask) { mask 222 drivers/iio/adc/ti-adc12138.c int *shift, long mask) mask 228 drivers/iio/adc/ti-adc12138.c switch (mask) { mask 61 drivers/iio/adc/ti-adc128s052.c int *val2, long mask) mask 66 drivers/iio/adc/ti-adc128s052.c switch (mask) { mask 132 drivers/iio/adc/ti-adc161s626.c int *val, int *val2, long mask) mask 137 drivers/iio/adc/ti-adc161s626.c switch (mask) { mask 333 drivers/iio/adc/ti-ads1015.c unsigned int old, mask, cfg; mask 344 drivers/iio/adc/ti-ads1015.c mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK | mask 350 drivers/iio/adc/ti-ads1015.c mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK; mask 357 drivers/iio/adc/ti-ads1015.c cfg = (old & ~mask) | (cfg & mask); mask 441 drivers/iio/adc/ti-ads1015.c int *val2, long mask) mask 447 drivers/iio/adc/ti-ads1015.c switch (mask) { mask 504 drivers/iio/adc/ti-ads1015.c int val2, long mask) mask 510 drivers/iio/adc/ti-ads1015.c switch (mask) { mask 103 drivers/iio/adc/ti-ads8344.c int *shift, long mask) mask 107 drivers/iio/adc/ti-ads8344.c switch (mask) { mask 294 drivers/iio/adc/ti-ads8688.c int val, int val2, long mask) mask 301 drivers/iio/adc/ti-ads8688.c switch (mask) { mask 363 drivers/iio/adc/ti-ads8688.c long mask) mask 365 drivers/iio/adc/ti-ads8688.c switch (mask) { mask 469 drivers/iio/adc/ti_am335x_adc.c int *val, int *val2, long mask) mask 545 drivers/iio/adc/ti_am335x_adc.c dma_cap_mask_t mask; mask 552 drivers/iio/adc/ti_am335x_adc.c dma_cap_zero(mask); mask 553 drivers/iio/adc/ti_am335x_adc.c dma_cap_set(DMA_CYCLIC, mask); mask 176 drivers/iio/adc/twl4030-madc.c int *val, int *val2, long mask) mask 187 drivers/iio/adc/twl4030-madc.c req.raw = !(mask == IIO_CHAN_INFO_PROCESSED); mask 188 drivers/iio/adc/twl4030-madc.c req.do_avg = (mask == IIO_CHAN_INFO_AVERAGE_RAW); mask 351 drivers/iio/adc/twl6030-gpadc.c static int twl6030_gpadc_enable_irq(u8 mask) mask 355 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_interrupt_unmask(mask, REG_INT_MSK_LINE_B); mask 359 drivers/iio/adc/twl6030-gpadc.c ret = twl6030_interrupt_unmask(mask, REG_INT_MSK_STS_B); mask 364 drivers/iio/adc/twl6030-gpadc.c static void twl6030_gpadc_disable_irq(u8 mask) mask 366 drivers/iio/adc/twl6030-gpadc.c twl6030_interrupt_mask(mask, REG_INT_MSK_LINE_B); mask 367 drivers/iio/adc/twl6030-gpadc.c twl6030_interrupt_mask(mask, REG_INT_MSK_STS_B); mask 505 drivers/iio/adc/twl6030-gpadc.c int *val, int *val2, long mask) mask 529 drivers/iio/adc/twl6030-gpadc.c switch (mask) { mask 626 drivers/iio/adc/vf610_adc.c long mask) mask 632 drivers/iio/adc/vf610_adc.c switch (mask) { mask 699 drivers/iio/adc/vf610_adc.c long mask) mask 704 drivers/iio/adc/vf610_adc.c switch (mask) { mask 158 drivers/iio/adc/xilinx-xadc-core.c static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask, mask 161 drivers/iio/adc/xilinx-xadc-core.c xadc->zynq_intmask &= ~mask; mask 486 drivers/iio/adc/xilinx-xadc-core.c uint32_t status, mask; mask 490 drivers/iio/adc/xilinx-xadc-core.c xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask); mask 491 drivers/iio/adc/xilinx-xadc-core.c status &= mask; mask 555 drivers/iio/adc/xilinx-xadc-core.c uint16_t mask, uint16_t val) mask 564 drivers/iio/adc/xilinx-xadc-core.c return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val); mask 568 drivers/iio/adc/xilinx-xadc-core.c uint16_t mask, uint16_t val) mask 573 drivers/iio/adc/xilinx-xadc-core.c ret = _xadc_update_adc_reg(xadc, reg, mask, val); mask 585 drivers/iio/adc/xilinx-xadc-core.c const unsigned long *mask) mask 590 drivers/iio/adc/xilinx-xadc-core.c n = bitmap_weight(mask, indio_dev->masklength); mask 38 drivers/iio/afe/iio-rescale.c int *val, int *val2, long mask) mask 44 drivers/iio/afe/iio-rescale.c switch (mask) { mask 79 drivers/iio/afe/iio-rescale.c long mask) mask 83 drivers/iio/afe/iio-rescale.c switch (mask) { mask 141 drivers/iio/amplifiers/ad8366.c long mask) mask 170 drivers/iio/amplifiers/ad8366.c switch (mask) { mask 94 drivers/iio/chemical/ams-iaq-core.c int *val2, long mask) mask 99 drivers/iio/chemical/ams-iaq-core.c if (mask != IIO_CHAN_INFO_PROCESSED) mask 408 drivers/iio/chemical/atlas-ph-sensor.c int *val, int *val2, long mask) mask 412 drivers/iio/chemical/atlas-ph-sensor.c switch (mask) { mask 476 drivers/iio/chemical/atlas-ph-sensor.c int val, int val2, long mask) mask 484 drivers/iio/chemical/atlas-ph-sensor.c if (mask != IIO_CHAN_INFO_RAW || chan->type != IIO_TEMP) mask 772 drivers/iio/chemical/bme680_core.c int *val, int *val2, long mask) mask 776 drivers/iio/chemical/bme680_core.c switch (mask) { mask 816 drivers/iio/chemical/bme680_core.c int val, int val2, long mask) mask 823 drivers/iio/chemical/bme680_core.c switch (mask) { mask 193 drivers/iio/chemical/ccs811.c int *val, int *val2, long mask) mask 198 drivers/iio/chemical/ccs811.c switch (mask) { mask 139 drivers/iio/chemical/pms7003.c int *val, int *val2, long mask) mask 145 drivers/iio/chemical/pms7003.c switch (mask) { mask 335 drivers/iio/chemical/sgp30.c int *val2, long mask) mask 341 drivers/iio/chemical/sgp30.c switch (mask) { mask 254 drivers/iio/chemical/sps30.c int *val, int *val2, long mask) mask 259 drivers/iio/chemical/sps30.c switch (mask) { mask 264 drivers/iio/chemical/vz89x.c int *val2, long mask) mask 269 drivers/iio/chemical/vz89x.c switch (mask) { mask 69 drivers/iio/common/cros_ec_sensors/cros_ec_lid_angle.c int *val, int *val2, long mask) mask 38 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c int *val, int *val2, long mask) mask 49 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c switch (mask) { mask 142 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c mask); mask 152 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c int val, int val2, long mask) mask 161 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c switch (mask) { mask 207 drivers/iio/common/cros_ec_sensors/cros_ec_sensors.c &st->core, chan, val, val2, mask); mask 30 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c u16 cmd_offset, u16 cmd, u32 *mask) mask 50 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c *mask = buf.resp.version_mask; mask 484 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c int *val, int *val2, long mask) mask 488 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c switch (mask) { mask 527 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c long mask) mask 531 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c switch (mask) { mask 545 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c int val, int val2, long mask) mask 549 drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c switch (mask) { mask 150 drivers/iio/common/ms_sensors/ms_sensors_i2c.c u32 mask = 0xFF8000; mask 156 drivers/iio/common/ms_sensors/ms_sensors_i2c.c result = ((result ^ polynom) & mask) mask 157 drivers/iio/common/ms_sensors/ms_sensors_i2c.c | (result & ~mask); mask 159 drivers/iio/common/ms_sensors/ms_sensors_i2c.c mask >>= 1; mask 30 drivers/iio/common/st_sensors/st_sensors_core.c u8 reg_addr, u8 mask, u8 data) mask 35 drivers/iio/common/st_sensors/st_sensors_core.c reg_addr, mask, data << __ffs(mask)); mask 83 drivers/iio/common/st_sensors/st_sensors_core.c if (!sdata->sensor_settings->odr.mask) mask 92 drivers/iio/common/st_sensors/st_sensors_core.c (sdata->sensor_settings->odr.mask == mask 93 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->pw.mask)) { mask 97 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->odr.mask, mask 105 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->odr.mask, mask 149 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->fs.mask, mask 175 drivers/iio/common/st_sensors/st_sensors_core.c (sdata->sensor_settings->odr.mask == mask 176 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->pw.mask)) { mask 186 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->pw.mask, tmp_value); mask 197 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->pw.mask, mask 218 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->enable_axis.mask, mask 290 drivers/iio/common/st_sensors/st_sensors_core.c if (!sdata->sensor_settings->drdy_irq.int1.mask) { mask 298 drivers/iio/common/st_sensors/st_sensors_core.c if (!sdata->sensor_settings->drdy_irq.int2.mask) { mask 423 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->bdu.mask, true); mask 432 drivers/iio/common/st_sensors/st_sensors_core.c sdata->sensor_settings->das.mask, 1); mask 438 drivers/iio/common/st_sensors/st_sensors_core.c u8 addr, mask; mask 442 drivers/iio/common/st_sensors/st_sensors_core.c mask = sdata->sensor_settings->drdy_irq.int1.mask_od; mask 445 drivers/iio/common/st_sensors/st_sensors_core.c mask = sdata->sensor_settings->drdy_irq.int2.mask_od; mask 452 drivers/iio/common/st_sensors/st_sensors_core.c mask, 1); mask 494 drivers/iio/common/st_sensors/st_sensors_core.c drdy_mask = sdata->sensor_settings->drdy_irq.int1.mask; mask 497 drivers/iio/common/st_sensors/st_sensors_core.c drdy_mask = sdata->sensor_settings->drdy_irq.int2.mask; mask 8 drivers/iio/common/st_sensors/st_sensors_core.h u8 reg_addr, u8 mask, u8 data); mask 49 drivers/iio/common/st_sensors/st_sensors_trigger.c if (status & sdata->sensor_settings->drdy_irq.stat_drdy.mask) mask 343 drivers/iio/dac/ad5064.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 348 drivers/iio/dac/ad5064.c switch (mask) { mask 314 drivers/iio/dac/ad5360.c long mask) mask 320 drivers/iio/dac/ad5360.c switch (mask) { mask 354 drivers/iio/dac/ad5421.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 358 drivers/iio/dac/ad5421.c switch (mask) { mask 387 drivers/iio/dac/ad5421.c unsigned int mask; mask 392 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_OVER_CURRENT; mask 394 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_UNDER_CURRENT; mask 397 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_TEMP_OVER_140; mask 405 drivers/iio/dac/ad5421.c st->fault_mask |= mask; mask 407 drivers/iio/dac/ad5421.c st->fault_mask &= ~mask; mask 418 drivers/iio/dac/ad5421.c unsigned int mask; mask 423 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_OVER_CURRENT; mask 425 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_UNDER_CURRENT; mask 428 drivers/iio/dac/ad5421.c mask = AD5421_FAULT_TEMP_OVER_140; mask 434 drivers/iio/dac/ad5421.c return (bool)(st->fault_mask & mask); mask 187 drivers/iio/dac/ad5446.c long mask) mask 192 drivers/iio/dac/ad5446.c switch (mask) { mask 124 drivers/iio/dac/ad5504.c long mask) mask 128 drivers/iio/dac/ad5504.c switch (mask) { mask 304 drivers/iio/dac/ad5592r-base.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 309 drivers/iio/dac/ad5592r-base.c switch (mask) { mask 459 drivers/iio/dac/ad5592r-base.c struct iio_chan_spec const *chan, long mask) mask 461 drivers/iio/dac/ad5592r-base.c switch (mask) { mask 66 drivers/iio/dac/ad5624r_spi.c long mask) mask 70 drivers/iio/dac/ad5624r_spi.c switch (mask) { mask 150 drivers/iio/dac/ad5686.c long mask) mask 155 drivers/iio/dac/ad5686.c switch (mask) { mask 247 drivers/iio/dac/ad5755.c unsigned int mask = BIT(channel); mask 251 drivers/iio/dac/ad5755.c if ((bool)(st->pwr_down & mask) == pwr_down) mask 255 drivers/iio/dac/ad5755.c st->pwr_down &= ~mask; mask 262 drivers/iio/dac/ad5755.c st->pwr_down |= mask; mask 226 drivers/iio/dac/ad5758.c unsigned long int mask, mask 235 drivers/iio/dac/ad5758.c regval &= ~mask; mask 261 drivers/iio/dac/ad5758.c unsigned int mask) mask 272 drivers/iio/dac/ad5758.c if (!(ret & mask)) mask 279 drivers/iio/dac/ad5758.c "Error reading bit 0x%x in 0x%x register\n", mask, reg); mask 376 drivers/iio/dac/ad5758.c unsigned long int mask; mask 379 drivers/iio/dac/ad5758.c mask = AD5758_DAC_CONFIG_SR_EN_MSK | mask 386 drivers/iio/dac/ad5758.c ret = ad5758_spi_write_mask(st, AD5758_DAC_CONFIG, mask, mode); mask 668 drivers/iio/dac/ad5758.c unsigned int mask; mask 670 drivers/iio/dac/ad5758.c mask = (AD5758_WR_FLAG_MSK(AD5758_DIGITAL_DIAG_CONFIG) << 24) | 0x5C3A; mask 671 drivers/iio/dac/ad5758.c st->d32[0] = cpu_to_be32(mask); mask 201 drivers/iio/dac/ad5761.c long mask) mask 207 drivers/iio/dac/ad5761.c switch (mask) { mask 235 drivers/iio/dac/ad5761.c long mask) mask 239 drivers/iio/dac/ad5761.c if (mask != IIO_CHAN_INFO_RAW) mask 323 drivers/iio/dac/ad5791.c long mask) mask 327 drivers/iio/dac/ad5791.c switch (mask) { mask 137 drivers/iio/dac/ad7303.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 142 drivers/iio/dac/ad7303.c switch (mask) { mask 40 drivers/iio/dac/ad8801.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 45 drivers/iio/dac/ad8801.c switch (mask) { mask 48 drivers/iio/dac/cio-dac.c struct iio_chan_spec const *chan, int *val, int *val2, long mask) mask 52 drivers/iio/dac/cio-dac.c if (mask != IIO_CHAN_INFO_RAW) mask 61 drivers/iio/dac/cio-dac.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 66 drivers/iio/dac/cio-dac.c if (mask != IIO_CHAN_INFO_RAW) mask 54 drivers/iio/dac/dpot-dac.c int *val, int *val2, long mask) mask 60 drivers/iio/dac/dpot-dac.c switch (mask) { mask 97 drivers/iio/dac/dpot-dac.c long mask) mask 101 drivers/iio/dac/dpot-dac.c switch (mask) { mask 112 drivers/iio/dac/dpot-dac.c int val, int val2, long mask) mask 116 drivers/iio/dac/dpot-dac.c switch (mask) { mask 109 drivers/iio/dac/ds4424.c int *val, int *val2, long mask) mask 114 drivers/iio/dac/ds4424.c switch (mask) { mask 135 drivers/iio/dac/ds4424.c int val, int val2, long mask) mask 142 drivers/iio/dac/ds4424.c switch (mask) { mask 51 drivers/iio/dac/lpc18xx_dac.c int *val, int *val2, long mask) mask 56 drivers/iio/dac/lpc18xx_dac.c switch (mask) { mask 76 drivers/iio/dac/lpc18xx_dac.c int val, int val2, long mask) mask 81 drivers/iio/dac/lpc18xx_dac.c switch (mask) { mask 51 drivers/iio/dac/ltc1660.c long mask) mask 55 drivers/iio/dac/ltc1660.c switch (mask) { mask 80 drivers/iio/dac/ltc1660.c long mask) mask 85 drivers/iio/dac/ltc1660.c switch (mask) { mask 104 drivers/iio/dac/ltc2632.c long mask) mask 108 drivers/iio/dac/ltc2632.c switch (mask) { mask 79 drivers/iio/dac/m62332.c long mask) mask 84 drivers/iio/dac/m62332.c switch (mask) { mask 112 drivers/iio/dac/m62332.c long mask) mask 114 drivers/iio/dac/m62332.c switch (mask) { mask 87 drivers/iio/dac/max517.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 91 drivers/iio/dac/max517.c switch (mask) { mask 239 drivers/iio/dac/max5821.c int *val, int *val2, long mask) mask 243 drivers/iio/dac/max5821.c switch (mask) { mask 257 drivers/iio/dac/max5821.c int val, int val2, long mask) mask 262 drivers/iio/dac/max5821.c switch (mask) { mask 309 drivers/iio/dac/mcp4725.c int *val, int *val2, long mask) mask 314 drivers/iio/dac/mcp4725.c switch (mask) { mask 336 drivers/iio/dac/mcp4725.c int val, int val2, long mask) mask 341 drivers/iio/dac/mcp4725.c switch (mask) { mask 63 drivers/iio/dac/mcp4922.c long mask) mask 67 drivers/iio/dac/mcp4922.c switch (mask) { mask 84 drivers/iio/dac/mcp4922.c long mask) mask 92 drivers/iio/dac/mcp4922.c switch (mask) { mask 100 drivers/iio/dac/stm32-dac.c int *val, int *val2, long mask) mask 104 drivers/iio/dac/stm32-dac.c switch (mask) { mask 118 drivers/iio/dac/stm32-dac.c int val, int val2, long mask) mask 122 drivers/iio/dac/stm32-dac.c switch (mask) { mask 187 drivers/iio/dac/ti-dac082s085.c int *val, int *val2, long mask) mask 192 drivers/iio/dac/ti-dac082s085.c switch (mask) { mask 217 drivers/iio/dac/ti-dac082s085.c int val, int val2, long mask) mask 222 drivers/iio/dac/ti-dac082s085.c switch (mask) { mask 248 drivers/iio/dac/ti-dac082s085.c struct iio_chan_spec const *chan, long mask) mask 240 drivers/iio/dac/ti-dac5571.c int *val, int *val2, long mask) mask 245 drivers/iio/dac/ti-dac5571.c switch (mask) { mask 266 drivers/iio/dac/ti-dac5571.c int val, int val2, long mask) mask 271 drivers/iio/dac/ti-dac5571.c switch (mask) { mask 296 drivers/iio/dac/ti-dac5571.c long mask) mask 168 drivers/iio/dac/ti-dac7311.c int *val, int *val2, long mask) mask 173 drivers/iio/dac/ti-dac7311.c switch (mask) { mask 193 drivers/iio/dac/ti-dac7311.c int val, int val2, long mask) mask 199 drivers/iio/dac/ti-dac7311.c switch (mask) { mask 225 drivers/iio/dac/ti-dac7311.c struct iio_chan_spec const *chan, long mask) mask 69 drivers/iio/dac/ti-dac7612.c int *val, int *val2, long mask) mask 73 drivers/iio/dac/ti-dac7612.c switch (mask) { mask 90 drivers/iio/dac/ti-dac7612.c int val, int val2, long mask) mask 95 drivers/iio/dac/ti-dac7612.c if (mask != IIO_CHAN_INFO_RAW) mask 118 drivers/iio/dac/vf610_dac.c long mask) mask 122 drivers/iio/dac/vf610_dac.c switch (mask) { mask 144 drivers/iio/dac/vf610_dac.c long mask) mask 148 drivers/iio/dac/vf610_dac.c switch (mask) { mask 283 drivers/iio/dummy/iio_simple_dummy.c long mask) mask 289 drivers/iio/dummy/iio_simple_dummy.c switch (mask) { mask 426 drivers/iio/dummy/iio_simple_dummy.c long mask) mask 432 drivers/iio/dummy/iio_simple_dummy.c switch (mask) { mask 371 drivers/iio/frequency/ad9523.c unsigned int mask; mask 378 drivers/iio/frequency/ad9523.c mask = AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 << ch; mask 380 drivers/iio/frequency/ad9523.c ret |= mask; mask 383 drivers/iio/frequency/ad9523.c ret &= ~mask; mask 392 drivers/iio/frequency/ad9523.c mask = AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 << (ch - 4); mask 394 drivers/iio/frequency/ad9523.c ret |= mask; mask 396 drivers/iio/frequency/ad9523.c ret &= ~mask; mask 403 drivers/iio/frequency/ad9523.c mask = AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 << (ch - 7); mask 405 drivers/iio/frequency/ad9523.c ret |= mask; mask 407 drivers/iio/frequency/ad9523.c ret &= ~mask; mask 670 drivers/iio/frequency/ad9523.c long mask) mask 683 drivers/iio/frequency/ad9523.c switch (mask) { mask 78 drivers/iio/gyro/adis16080.c long mask) mask 83 drivers/iio/gyro/adis16080.c switch (mask) { mask 71 drivers/iio/gyro/adis16130.c long mask) mask 76 drivers/iio/gyro/adis16130.c switch (mask) { mask 194 drivers/iio/gyro/adis16260.c long mask) mask 203 drivers/iio/gyro/adis16260.c switch (mask) { mask 274 drivers/iio/gyro/adis16260.c long mask) mask 282 drivers/iio/gyro/adis16260.c switch (mask) { mask 286 drivers/iio/gyro/adxrs450.c long mask) mask 289 drivers/iio/gyro/adxrs450.c switch (mask) { mask 307 drivers/iio/gyro/adxrs450.c long mask) mask 312 drivers/iio/gyro/adxrs450.c switch (mask) { mask 550 drivers/iio/gyro/bmg160_core.c int *val, int *val2, long mask) mask 555 drivers/iio/gyro/bmg160_core.c switch (mask) { mask 612 drivers/iio/gyro/bmg160_core.c int val, int val2, long mask) mask 617 drivers/iio/gyro/bmg160_core.c switch (mask) { mask 530 drivers/iio/gyro/fxas21002c_core.c int *val2, long mask) mask 535 drivers/iio/gyro/fxas21002c_core.c switch (mask) { mask 573 drivers/iio/gyro/fxas21002c_core.c int val2, long mask) mask 578 drivers/iio/gyro/fxas21002c_core.c switch (mask) { mask 95 drivers/iio/gyro/hid-sensor-gyro-3d.c long mask) mask 105 drivers/iio/gyro/hid-sensor-gyro-3d.c switch (mask) { mask 157 drivers/iio/gyro/hid-sensor-gyro-3d.c long mask) mask 162 drivers/iio/gyro/hid-sensor-gyro-3d.c switch (mask) { mask 133 drivers/iio/gyro/itg3200_core.c long mask) mask 138 drivers/iio/gyro/itg3200_core.c switch (mask) { mask 264 drivers/iio/gyro/mpu3050-core.c long mask) mask 270 drivers/iio/gyro/mpu3050-core.c switch (mask) { mask 370 drivers/iio/gyro/mpu3050-core.c int val, int val2, long mask) mask 389 drivers/iio/gyro/mpu3050-core.c switch (mask) { mask 29 drivers/iio/gyro/ssp_gyro_sensor.c int *val2, long mask) mask 34 drivers/iio/gyro/ssp_gyro_sensor.c switch (mask) { mask 48 drivers/iio/gyro/ssp_gyro_sensor.c int val2, long mask) mask 53 drivers/iio/gyro/ssp_gyro_sensor.c switch (mask) { mask 68 drivers/iio/gyro/st_gyro_core.c .mask = 0xc0, mask 78 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 84 drivers/iio/gyro/st_gyro_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 88 drivers/iio/gyro/st_gyro_core.c .mask = 0x30, mask 109 drivers/iio/gyro/st_gyro_core.c .mask = 0x80, mask 114 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 123 drivers/iio/gyro/st_gyro_core.c .mask = 0x07, mask 146 drivers/iio/gyro/st_gyro_core.c .mask = 0xc0, mask 156 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 162 drivers/iio/gyro/st_gyro_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 166 drivers/iio/gyro/st_gyro_core.c .mask = 0x30, mask 187 drivers/iio/gyro/st_gyro_core.c .mask = 0x80, mask 192 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 201 drivers/iio/gyro/st_gyro_core.c .mask = 0x07, mask 220 drivers/iio/gyro/st_gyro_core.c .mask = GENMASK(7, 6), mask 230 drivers/iio/gyro/st_gyro_core.c .mask = BIT(3), mask 236 drivers/iio/gyro/st_gyro_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 240 drivers/iio/gyro/st_gyro_core.c .mask = GENMASK(5, 4), mask 261 drivers/iio/gyro/st_gyro_core.c .mask = BIT(7), mask 266 drivers/iio/gyro/st_gyro_core.c .mask = BIT(3), mask 275 drivers/iio/gyro/st_gyro_core.c .mask = GENMASK(2, 0), mask 294 drivers/iio/gyro/st_gyro_core.c .mask = 0xc0, mask 304 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 310 drivers/iio/gyro/st_gyro_core.c .mask = ST_SENSORS_DEFAULT_AXIS_MASK, mask 314 drivers/iio/gyro/st_gyro_core.c .mask = 0x30, mask 335 drivers/iio/gyro/st_gyro_core.c .mask = 0x80, mask 340 drivers/iio/gyro/st_gyro_core.c .mask = 0x08, mask 349 drivers/iio/gyro/st_gyro_core.c .mask = 0x07, mask 363 drivers/iio/gyro/st_gyro_core.c int *val2, long mask) mask 368 drivers/iio/gyro/st_gyro_core.c switch (mask) { mask 391 drivers/iio/gyro/st_gyro_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 395 drivers/iio/gyro/st_gyro_core.c switch (mask) { mask 242 drivers/iio/health/afe4403.c int *val, int *val2, long mask) mask 251 drivers/iio/health/afe4403.c switch (mask) { mask 260 drivers/iio/health/afe4403.c switch (mask) { mask 281 drivers/iio/health/afe4403.c int val, int val2, long mask) mask 288 drivers/iio/health/afe4403.c switch (mask) { mask 248 drivers/iio/health/afe4404.c int *val, int *val2, long mask) mask 258 drivers/iio/health/afe4404.c switch (mask) { mask 272 drivers/iio/health/afe4404.c switch (mask) { mask 293 drivers/iio/health/afe4404.c int val, int val2, long mask) mask 301 drivers/iio/health/afe4404.c switch (mask) { mask 307 drivers/iio/health/afe4404.c switch (mask) { mask 380 drivers/iio/health/max30100.c int *val, int *val2, long mask) mask 385 drivers/iio/health/max30100.c switch (mask) { mask 470 drivers/iio/health/max30102.c int *val, int *val2, long mask) mask 475 drivers/iio/health/max30102.c switch (mask) { mask 192 drivers/iio/humidity/am2315.c int *val, int *val2, long mask) mask 198 drivers/iio/humidity/am2315.c switch (mask) { mask 52 drivers/iio/humidity/hdc100x.c int mask; mask 56 drivers/iio/humidity/hdc100x.c .mask = 1 mask 60 drivers/iio/humidity/hdc100x.c .mask = 3, mask 126 drivers/iio/humidity/hdc100x.c static int hdc100x_update_config(struct hdc100x_data *data, int mask, int val) mask 128 drivers/iio/humidity/hdc100x.c int tmp = (~mask & data->config) | val; mask 148 drivers/iio/humidity/hdc100x.c hdc100x_resolution_shift[chan].mask << shift, mask 193 drivers/iio/humidity/hdc100x.c int *val2, long mask) mask 197 drivers/iio/humidity/hdc100x.c switch (mask) { mask 248 drivers/iio/humidity/hdc100x.c int val, int val2, long mask) mask 253 drivers/iio/humidity/hdc100x.c switch (mask) { mask 53 drivers/iio/humidity/hid-sensor-humidity.c int *val, int *val2, long mask) mask 57 drivers/iio/humidity/hid-sensor-humidity.c switch (mask) { mask 99 drivers/iio/humidity/hid-sensor-humidity.c int val, int val2, long mask) mask 103 drivers/iio/humidity/hid-sensor-humidity.c switch (mask) { mask 57 drivers/iio/humidity/hts221_core.c u8 mask; mask 70 drivers/iio/humidity/hts221_core.c .mask = HTS221_HUMIDITY_AVG_MASK, mask 84 drivers/iio/humidity/hts221_core.c .mask = HTS221_TEMP_AVG_MASK, mask 190 drivers/iio/humidity/hts221_core.c data = ((i << __ffs(avg->mask)) & avg->mask); mask 192 drivers/iio/humidity/hts221_core.c avg->mask, data); mask 429 drivers/iio/humidity/hts221_core.c int *val, int *val2, long mask) mask 438 drivers/iio/humidity/hts221_core.c switch (mask) { mask 487 drivers/iio/humidity/hts221_core.c int val, int val2, long mask) mask 496 drivers/iio/humidity/hts221_core.c switch (mask) { mask 40 drivers/iio/humidity/htu21.c int *val2, long mask) mask 46 drivers/iio/humidity/htu21.c switch (mask) { mask 79 drivers/iio/humidity/htu21.c int val, int val2, long mask) mask 84 drivers/iio/humidity/htu21.c switch (mask) { mask 75 drivers/iio/humidity/si7005.c int *val2, long mask) mask 80 drivers/iio/humidity/si7005.c switch (mask) { mask 38 drivers/iio/humidity/si7020.c int *val2, long mask) mask 43 drivers/iio/humidity/si7020.c switch (mask) { mask 29 drivers/iio/iio_core.h u64 mask, mask 1123 drivers/iio/imu/adis16480.c unsigned int mode, mask; mask 1144 drivers/iio/imu/adis16480.c mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK; mask 1148 drivers/iio/imu/adis16480.c mask |= ADIS16480_SYNC_MODE_MSK; mask 1151 drivers/iio/imu/adis16480.c val &= ~mask; mask 436 drivers/iio/imu/bmi160/bmi160_core.c int *val, int *val2, long mask) mask 441 drivers/iio/imu/bmi160/bmi160_core.c switch (mask) { mask 465 drivers/iio/imu/bmi160/bmi160_core.c int val, int val2, long mask) mask 469 drivers/iio/imu/bmi160/bmi160_core.c switch (mask) { mask 527 drivers/iio/imu/bmi160/bmi160_core.c unsigned int mask, unsigned int bits, mask 537 drivers/iio/imu/bmi160/bmi160_core.c val = (val & ~mask) | bits; mask 186 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask) mask 195 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) { mask 203 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) { mask 218 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c d &= ~mask; mask 220 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c d |= mask; mask 228 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) { mask 451 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int *val, int *val2, long mask) mask 456 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c switch (mask) { mask 541 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c struct iio_chan_spec const *chan, long mask) mask 543 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c switch (mask) { mask 580 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c int val, int val2, long mask) mask 598 drivers/iio/imu/inv_mpu6050/inv_mpu_core.c switch (mask) { mask 347 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); mask 785 drivers/iio/imu/kmx61.c int *val2, long mask) mask 791 drivers/iio/imu/kmx61.c switch (mask) { mask 855 drivers/iio/imu/kmx61.c int val2, long mask) mask 860 drivers/iio/imu/kmx61.c switch (mask) { mask 55 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h #define ST_LSM6DSX_SHIFT_VAL(val, mask) (((val) << __ffs(mask)) & (mask)) mask 77 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u8 mask; mask 120 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u16 mask; mask 124 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h u16 mask; mask 356 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h unsigned int mask, unsigned int val) mask 361 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h err = regmap_update_bits(hw->regmap, addr, mask, val); mask 152 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c int val = ST_LSM6DSX_SHIFT_VAL(data, dec_reg->mask); mask 155 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c dec_reg->mask, mask 174 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c val = ST_LSM6DSX_SHIFT_VAL(ts_dec, ts_dec_reg->mask); mask 176 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c ts_dec_reg->mask, val); mask 219 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c val = ST_LSM6DSX_SHIFT_VAL(data, batch_reg->mask); mask 221 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c batch_reg->mask, val); mask 268 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c fifo_th_mask = hw->settings->fifo_ops.fifo_th.mask; mask 342 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c u16 fifo_diff_mask = hw->settings->fifo_ops.fifo_diff.mask; mask 535 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c fifo_diff_mask = hw->settings->fifo_ops.fifo_diff.mask; mask 116 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 5), mask 128 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 5), mask 142 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(4, 3), mask 153 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(4, 3), mask 189 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 201 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 215 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 226 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 238 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(2, 0), mask 242 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 250 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(11, 0), mask 254 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(11, 0), mask 261 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), mask 265 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), mask 269 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), mask 273 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 303 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 315 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 329 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 340 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 352 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(2, 0), mask 356 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 364 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(11, 0), mask 368 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(11, 0), mask 375 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), mask 379 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), mask 383 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), mask 387 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 426 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 438 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 452 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 463 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 475 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(2, 0), mask 479 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 487 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(10, 0), mask 491 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(10, 0), mask 498 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), mask 502 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(4), mask 506 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(7), mask 510 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(5, 3), mask 543 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 555 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 569 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 580 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 592 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 0), mask 596 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 604 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(8, 0), mask 608 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(9, 0), mask 615 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), mask 619 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 6), mask 625 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), mask 629 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(2), mask 633 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(3), mask 637 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(1, 0), mask 641 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), mask 675 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 687 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 701 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 712 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 724 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 0), mask 728 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 736 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(8, 0), mask 740 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(9, 0), mask 747 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), mask 751 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 6), mask 784 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 796 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 810 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 821 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 2), mask 833 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(3, 0), mask 837 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 4), mask 845 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(8, 0), mask 849 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(9, 0), mask 856 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(5), mask 860 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(7, 6), mask 866 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), mask 870 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(2), mask 874 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(3), mask 878 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = GENMASK(1, 0), mask 882 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c .mask = BIT(6), mask 899 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask); mask 901 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hub_settings->page_mux.mask, data); mask 961 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c fs_table->reg.mask); mask 963 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c fs_table->reg.mask, data); mask 1054 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask); mask 1055 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data); mask 1104 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int *val, int *val2, long mask) mask 1109 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c switch (mask) { mask 1137 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c int val, int val2, long mask) mask 1146 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c switch (mask) { mask 1324 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask); mask 1327 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hub_settings->pullup_en.mask, data); mask 1341 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask); mask 1344 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c hub_settings->aux_sens.mask, data); mask 1360 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask); mask 1363 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->timer_en.mask, val); mask 1370 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask); mask 1373 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->hr_timer.mask, val); mask 1380 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask); mask 1383 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c ts_settings->fifo_en.mask, val); mask 52 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = GENMASK(3, 2), mask 68 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(7), mask 73 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = GENMASK(1, 0), mask 80 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(1), mask 84 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c .mask = BIT(4), mask 154 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u8 mask, u8 val) mask 163 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c err = regmap_update_bits(hw->regmap, addr, mask, val); mask 192 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->master_en.mask); mask 194 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c hub_settings->master_en.mask, data); mask 265 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->wr_once.mask); mask 268 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c hub_settings->wr_once.mask, mask 304 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c u8 addr, u8 mask, u8 val) mask 313 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c data = ((data & ~mask) | (val << __ffs(mask) & mask)); mask 351 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.mask, mask 411 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->odr_table.reg.mask, 0); mask 423 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->pwr_table.reg.mask, val); mask 468 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c int *val, int *val2, long mask) mask 473 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c switch (mask) { mask 502 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c int val, int val2, long mask) mask 511 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c switch (mask) { mask 659 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->bdu.mask, 1); mask 667 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->temp_comp.mask, 1); mask 675 drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c settings->off_canc.mask, 1); mask 276 drivers/iio/industrialio-buffer.c const unsigned long *mask, mask 279 drivers/iio/industrialio-buffer.c if (bitmap_empty(mask, masklength)) mask 283 drivers/iio/industrialio-buffer.c if (bitmap_equal(mask, av_masks, masklength)) mask 286 drivers/iio/industrialio-buffer.c if (bitmap_subset(mask, av_masks, masklength)) mask 295 drivers/iio/industrialio-buffer.c const unsigned long *mask) mask 300 drivers/iio/industrialio-buffer.c return indio_dev->setup_ops->validate_scan_mask(indio_dev, mask); mask 316 drivers/iio/industrialio-buffer.c const unsigned long *mask; mask 334 drivers/iio/industrialio-buffer.c mask = iio_scan_mask_match(indio_dev->available_scan_masks, mask 337 drivers/iio/industrialio-buffer.c if (!mask) mask 566 drivers/iio/industrialio-buffer.c const unsigned long *mask, bool timestamp) mask 572 drivers/iio/industrialio-buffer.c for_each_set_bit(i, mask, mask 664 drivers/iio/industrialio-buffer.c const unsigned long *mask) mask 668 drivers/iio/industrialio-buffer.c bitmap_free(mask); mask 1363 drivers/iio/industrialio-buffer.c const unsigned long *mask) mask 1365 drivers/iio/industrialio-buffer.c return bitmap_weight(mask, indio_dev->masklength) == 1; mask 1018 drivers/iio/industrialio-core.c u64 mask, mask 1035 drivers/iio/industrialio-core.c iio_attr->address = mask; mask 344 drivers/iio/industrialio-event.c enum iio_shared_by shared_by, const unsigned long *mask) mask 354 drivers/iio/industrialio-event.c for_each_set_bit(i, mask, sizeof(*mask)*8) { mask 138 drivers/iio/light/acpi-als.c int *val2, long mask) mask 144 drivers/iio/light/acpi-als.c if ((mask != IIO_CHAN_INFO_PROCESSED) && (mask != IIO_CHAN_INFO_RAW)) mask 170 drivers/iio/light/adjd_s311.c int *val, int *val2, long mask) mask 175 drivers/iio/light/adjd_s311.c switch (mask) { mask 207 drivers/iio/light/adjd_s311.c int val, int val2, long mask) mask 211 drivers/iio/light/adjd_s311.c switch (mask) { mask 112 drivers/iio/light/al3320a.c int *val2, long mask) mask 117 drivers/iio/light/al3320a.c switch (mask) { mask 147 drivers/iio/light/al3320a.c int val2, long mask) mask 152 drivers/iio/light/al3320a.c switch (mask) { mask 237 drivers/iio/light/apds9300.c long mask) mask 470 drivers/iio/light/apds9960.c int *val, int *val2, long mask) mask 479 drivers/iio/light/apds9960.c switch (mask) { mask 538 drivers/iio/light/apds9960.c int val, int val2, long mask) mask 542 drivers/iio/light/apds9960.c switch (mask) { mask 133 drivers/iio/light/bh1750.c int *val, int *val2, long mask) mask 139 drivers/iio/light/bh1750.c switch (mask) { mask 169 drivers/iio/light/bh1750.c int val, int val2, long mask) mask 174 drivers/iio/light/bh1750.c switch (mask) { mask 101 drivers/iio/light/bh1780.c int *val, int *val2, long mask) mask 106 drivers/iio/light/bh1780.c switch (mask) { mask 205 drivers/iio/light/cm32181.c int *val, int *val2, long mask) mask 210 drivers/iio/light/cm32181.c switch (mask) { mask 231 drivers/iio/light/cm32181.c int val, int val2, long mask) mask 236 drivers/iio/light/cm32181.c switch (mask) { mask 236 drivers/iio/light/cm3232.c int *val, int *val2, long mask) mask 242 drivers/iio/light/cm3232.c switch (mask) { mask 261 drivers/iio/light/cm3232.c int val, int val2, long mask) mask 266 drivers/iio/light/cm3232.c switch (mask) { mask 157 drivers/iio/light/cm3323.c int *val2, long mask) mask 162 drivers/iio/light/cm3323.c switch (mask) { mask 194 drivers/iio/light/cm3323.c int val2, long mask) mask 199 drivers/iio/light/cm3323.c switch (mask) { mask 107 drivers/iio/light/cm3605.c int *val, int *val2, long mask) mask 112 drivers/iio/light/cm3605.c switch (mask) { mask 447 drivers/iio/light/cm36651.c int *val, int *val2, long mask) mask 454 drivers/iio/light/cm36651.c switch (mask) { mask 473 drivers/iio/light/cm36651.c int val, int val2, long mask) mask 479 drivers/iio/light/cm36651.c if (mask == IIO_CHAN_INFO_INT_TIME) { mask 41 drivers/iio/light/cros_ec_light_prox.c int *val, int *val2, long mask) mask 51 drivers/iio/light/cros_ec_light_prox.c switch (mask) { mask 116 drivers/iio/light/cros_ec_light_prox.c mask); mask 127 drivers/iio/light/cros_ec_light_prox.c int val, int val2, long mask) mask 135 drivers/iio/light/cros_ec_light_prox.c switch (mask) { mask 154 drivers/iio/light/cros_ec_light_prox.c mask); mask 1282 drivers/iio/light/gp2ap020a00f.c long mask) mask 1287 drivers/iio/light/gp2ap020a00f.c if (mask == IIO_CHAN_INFO_RAW) { mask 77 drivers/iio/light/hid-sensor-als.c long mask) mask 87 drivers/iio/light/hid-sensor-als.c switch (mask) { mask 147 drivers/iio/light/hid-sensor-als.c long mask) mask 152 drivers/iio/light/hid-sensor-als.c switch (mask) { mask 58 drivers/iio/light/hid-sensor-prox.c long mask) mask 68 drivers/iio/light/hid-sensor-prox.c switch (mask) { mask 127 drivers/iio/light/hid-sensor-prox.c long mask) mask 132 drivers/iio/light/hid-sensor-prox.c switch (mask) { mask 363 drivers/iio/light/isl29018.c long mask) mask 373 drivers/iio/light/isl29018.c switch (mask) { mask 403 drivers/iio/light/isl29018.c long mask) mask 413 drivers/iio/light/isl29018.c switch (mask) { mask 356 drivers/iio/light/isl29028.c int val, int val2, long mask) mask 371 drivers/iio/light/isl29028.c if (mask != IIO_CHAN_INFO_SAMP_FREQ) { mask 374 drivers/iio/light/isl29028.c __func__, mask); mask 388 drivers/iio/light/isl29028.c if (mask != IIO_CHAN_INFO_SCALE) { mask 391 drivers/iio/light/isl29028.c __func__, mask); mask 424 drivers/iio/light/isl29028.c int *val, int *val2, long mask) mask 437 drivers/iio/light/isl29028.c switch (mask) { mask 475 drivers/iio/light/isl29028.c __func__, mask); mask 123 drivers/iio/light/isl29125.c int *val, int *val2, long mask) mask 128 drivers/iio/light/isl29125.c switch (mask) { mask 152 drivers/iio/light/isl29125.c int val, int val2, long mask) mask 156 drivers/iio/light/isl29125.c switch (mask) { mask 215 drivers/iio/light/jsa1212.c int *val, int *val2, long mask) mask 220 drivers/iio/light/jsa1212.c switch (mask) { mask 193 drivers/iio/light/lm3533-als.c int *val, int *val2, long mask) mask 197 drivers/iio/light/lm3533-als.c switch (mask) { mask 274 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_INT_ENABLE_MASK; mask 279 drivers/iio/light/lm3533-als.c val = mask; mask 283 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, val, mask); mask 296 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_INT_ENABLE_MASK; mask 306 drivers/iio/light/lm3533-als.c *enable = !!(val & mask); mask 719 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_INPUT_MODE_MASK; mask 724 drivers/iio/light/lm3533-als.c val = mask; /* pwm input */ mask 728 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, val, mask); mask 777 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_INT_ENABLE_MASK; mask 781 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_ZONE_INFO, 0, mask); mask 801 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_ENABLE_MASK; mask 804 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, mask, mask); mask 813 drivers/iio/light/lm3533-als.c u8 mask = LM3533_ALS_ENABLE_MASK; mask 816 drivers/iio/light/lm3533-als.c ret = lm3533_update(als->lm3533, LM3533_REG_ALS_CONF, 0, mask); mask 623 drivers/iio/light/ltr501.c int *val, int *val2, long mask) mask 629 drivers/iio/light/ltr501.c switch (mask) { mask 733 drivers/iio/light/ltr501.c int val, int val2, long mask) mask 743 drivers/iio/light/ltr501.c switch (mask) { mask 1247 drivers/iio/light/ltr501.c u8 mask = 0; mask 1256 drivers/iio/light/ltr501.c mask |= LTR501_STATUS_ALS_RDY; mask 1258 drivers/iio/light/ltr501.c mask |= LTR501_STATUS_PS_RDY; mask 1260 drivers/iio/light/ltr501.c ret = ltr501_drdy(data, mask); mask 1264 drivers/iio/light/ltr501.c if (mask & LTR501_STATUS_ALS_RDY) { mask 1275 drivers/iio/light/ltr501.c if (mask & LTR501_STATUS_PS_RDY) { mask 228 drivers/iio/light/lv0104cs.c int *val, int *val2, long mask) mask 238 drivers/iio/light/lv0104cs.c switch (mask) { mask 371 drivers/iio/light/lv0104cs.c int val, int val2, long mask) mask 378 drivers/iio/light/lv0104cs.c switch (mask) { mask 258 drivers/iio/light/max44000.c int *val, int *val2, long mask) mask 265 drivers/iio/light/max44000.c switch (mask) { mask 342 drivers/iio/light/max44000.c int val, int val2, long mask) mask 347 drivers/iio/light/max44000.c if (mask == IIO_CHAN_INFO_RAW && chan->type == IIO_CURRENT) { mask 352 drivers/iio/light/max44000.c } else if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) { mask 361 drivers/iio/light/max44000.c } else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT) { mask 377 drivers/iio/light/max44000.c long mask) mask 379 drivers/iio/light/max44000.c if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) mask 381 drivers/iio/light/max44000.c else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT) mask 151 drivers/iio/light/max44009.c int val2, long mask) mask 156 drivers/iio/light/max44009.c if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) { mask 167 drivers/iio/light/max44009.c long mask) mask 248 drivers/iio/light/max44009.c int *val2, long mask) mask 254 drivers/iio/light/max44009.c switch (mask) { mask 130 drivers/iio/light/noa1305.c int *val, int *val2, long mask) mask 135 drivers/iio/light/noa1305.c switch (mask) { mask 387 drivers/iio/light/opt3001.c long mask) mask 400 drivers/iio/light/opt3001.c switch (mask) { mask 418 drivers/iio/light/opt3001.c long mask) mask 429 drivers/iio/light/opt3001.c if (mask != IIO_CHAN_INFO_INT_TIME) mask 158 drivers/iio/light/pa12203001.c u8 mask) mask 163 drivers/iio/light/pa12203001.c if (on && (mask & PA12203001_ALS_EN_MASK)) { mask 176 drivers/iio/light/pa12203001.c if (on && (mask & PA12203001_PX_EN_MASK)) { mask 210 drivers/iio/light/pa12203001.c int *val2, long mask) mask 218 drivers/iio/light/pa12203001.c switch (mask) { mask 278 drivers/iio/light/pa12203001.c int val2, long mask) mask 284 drivers/iio/light/pa12203001.c switch (mask) { mask 125 drivers/iio/light/rpr0521.c u8 mask; mask 132 drivers/iio/light/rpr0521.c .mask = RPR0521_PXS_GAIN_MASK, mask 139 drivers/iio/light/rpr0521.c .mask = RPR0521_ALS_DATA0_GAIN_MASK, mask 146 drivers/iio/light/rpr0521.c .mask = RPR0521_ALS_DATA1_GAIN_MASK, mask 587 drivers/iio/light/rpr0521.c idx = (rpr0521_gain[chan].mask & reg) >> rpr0521_gain[chan].shift; mask 611 drivers/iio/light/rpr0521.c rpr0521_gain[chan].mask, mask 717 drivers/iio/light/rpr0521.c int *val2, long mask) mask 725 drivers/iio/light/rpr0521.c switch (mask) { mask 795 drivers/iio/light/rpr0521.c int val2, long mask) mask 800 drivers/iio/light/rpr0521.c switch (mask) { mask 573 drivers/iio/light/si1133.c u8 mask, u8 shift, u8 value) mask 583 drivers/iio/light/si1133.c adc_config &= ~mask; mask 690 drivers/iio/light/si1133.c static int si1133_update_adcsens(struct si1133_data *data, u8 mask, mask 701 drivers/iio/light/si1133.c adc_sens &= ~mask; mask 755 drivers/iio/light/si1133.c int *val, int *val2, long mask) mask 761 drivers/iio/light/si1133.c switch (mask) { mask 829 drivers/iio/light/si1133.c int val, int val2, long mask) mask 833 drivers/iio/light/si1133.c switch (mask) { mask 622 drivers/iio/light/si1145.c int *val, int *val2, long mask) mask 628 drivers/iio/light/si1145.c switch (mask) { mask 721 drivers/iio/light/si1145.c int val, int val2, long mask) mask 727 drivers/iio/light/si1145.c switch (mask) { mask 116 drivers/iio/light/st_uvis25_core.c int *val, int *val2, long mask) mask 124 drivers/iio/light/st_uvis25_core.c switch (mask) { mask 303 drivers/iio/light/stk3310.c int *val, int *val2, long mask) mask 315 drivers/iio/light/stk3310.c switch (mask) { mask 361 drivers/iio/light/stk3310.c int val, int val2, long mask) mask 370 drivers/iio/light/stk3310.c switch (mask) { mask 126 drivers/iio/light/tcs3414.c int *val, int *val2, long mask) mask 131 drivers/iio/light/tcs3414.c switch (mask) { mask 162 drivers/iio/light/tcs3414.c int val, int val2, long mask) mask 167 drivers/iio/light/tcs3414.c switch (mask) { mask 140 drivers/iio/light/tcs3472.c int *val, int *val2, long mask) mask 145 drivers/iio/light/tcs3472.c switch (mask) { mask 175 drivers/iio/light/tcs3472.c int val, int val2, long mask) mask 180 drivers/iio/light/tcs3472.c switch (mask) { mask 446 drivers/iio/light/tsl2563.c long mask) mask 450 drivers/iio/light/tsl2563.c if (mask != IIO_CHAN_INFO_CALIBSCALE) mask 466 drivers/iio/light/tsl2563.c long mask) mask 473 drivers/iio/light/tsl2563.c switch (mask) { mask 652 drivers/iio/light/tsl2583.c int *val, int *val2, long mask) mask 664 drivers/iio/light/tsl2583.c switch (mask) { mask 741 drivers/iio/light/tsl2583.c int val, int val2, long mask) mask 753 drivers/iio/light/tsl2583.c switch (mask) { mask 904 drivers/iio/light/tsl2772.c long mask) mask 908 drivers/iio/light/tsl2772.c switch (mask) { mask 1238 drivers/iio/light/tsl2772.c long mask) mask 1242 drivers/iio/light/tsl2772.c switch (mask) { mask 1292 drivers/iio/light/tsl2772.c long mask) mask 1296 drivers/iio/light/tsl2772.c switch (mask) { mask 76 drivers/iio/light/tsl4531.c int *val, int *val2, long mask) mask 81 drivers/iio/light/tsl4531.c switch (mask) { mask 111 drivers/iio/light/tsl4531.c int val, int val2, long mask) mask 116 drivers/iio/light/tsl4531.c switch (mask) { mask 423 drivers/iio/light/us5182d.c int *val2, long mask) mask 428 drivers/iio/light/us5182d.c switch (mask) { mask 498 drivers/iio/light/us5182d.c int val2, long mask) mask 503 drivers/iio/light/us5182d.c switch (mask) { mask 327 drivers/iio/light/vcnl4000.c int *val, int *val2, long mask) mask 332 drivers/iio/light/vcnl4000.c switch (mask) { mask 173 drivers/iio/light/vcnl4035.c int *val2, long mask) mask 180 drivers/iio/light/vcnl4035.c switch (mask) { mask 220 drivers/iio/light/vcnl4035.c int val, int val2, long mask) mask 225 drivers/iio/light/vcnl4035.c switch (mask) { mask 113 drivers/iio/light/veml6070.c int *val, int *val2, long mask) mask 118 drivers/iio/light/veml6070.c switch (mask) { mask 124 drivers/iio/light/veml6070.c if (mask == IIO_CHAN_INFO_PROCESSED) mask 293 drivers/iio/light/vl6180.c int *val, int *val2, long mask) mask 298 drivers/iio/light/vl6180.c switch (mask) { mask 417 drivers/iio/light/vl6180.c int val, int val2, long mask) mask 421 drivers/iio/light/vl6180.c switch (mask) { mask 254 drivers/iio/light/zopt2201.c int *val, int *val2, long mask) mask 260 drivers/iio/light/zopt2201.c switch (mask) { mask 410 drivers/iio/light/zopt2201.c int val, int val2, long mask) mask 414 drivers/iio/light/zopt2201.c switch (mask) { mask 280 drivers/iio/magnetometer/ak8974.c u8 mask; mask 291 drivers/iio/magnetometer/ak8974.c mask = AK8974_CTRL2_INT_EN | mask 301 drivers/iio/magnetometer/ak8974.c mask, val); mask 540 drivers/iio/magnetometer/ak8974.c long mask) mask 549 drivers/iio/magnetometer/ak8974.c switch (mask) { mask 717 drivers/iio/magnetometer/ak8975.c long mask) mask 721 drivers/iio/magnetometer/ak8975.c switch (mask) { mask 456 drivers/iio/magnetometer/bmc150_magn.c int *val, int *val2, long mask) mask 462 drivers/iio/magnetometer/bmc150_magn.c switch (mask) { mask 531 drivers/iio/magnetometer/bmc150_magn.c int val, int val2, long mask) mask 536 drivers/iio/magnetometer/bmc150_magn.c switch (mask) { mask 147 drivers/iio/magnetometer/hid-sensor-magn-3d.c long mask) mask 157 drivers/iio/magnetometer/hid-sensor-magn-3d.c switch (mask) { mask 242 drivers/iio/magnetometer/hid-sensor-magn-3d.c long mask) mask 247 drivers/iio/magnetometer/hid-sensor-magn-3d.c switch (mask) { mask 366 drivers/iio/magnetometer/hmc5843_core.c int *val, int *val2, long mask) mask 372 drivers/iio/magnetometer/hmc5843_core.c switch (mask) { mask 397 drivers/iio/magnetometer/hmc5843_core.c int val, int val2, long mask) mask 402 drivers/iio/magnetometer/hmc5843_core.c switch (mask) { mask 422 drivers/iio/magnetometer/hmc5843_core.c long mask) mask 424 drivers/iio/magnetometer/hmc5843_core.c switch (mask) { mask 270 drivers/iio/magnetometer/mag3110.c int *val, int *val2, long mask) mask 276 drivers/iio/magnetometer/mag3110.c switch (mask) { mask 343 drivers/iio/magnetometer/mag3110.c int val, int val2, long mask) mask 352 drivers/iio/magnetometer/mag3110.c switch (mask) { mask 353 drivers/iio/magnetometer/mmc35240.c int *val2, long mask) mask 360 drivers/iio/magnetometer/mmc35240.c switch (mask) { mask 396 drivers/iio/magnetometer/mmc35240.c int val2, long mask) mask 401 drivers/iio/magnetometer/mmc35240.c switch (mask) { mask 401 drivers/iio/magnetometer/rm3100-core.c int *val, int *val2, long mask) mask 406 drivers/iio/magnetometer/rm3100-core.c switch (mask) { mask 430 drivers/iio/magnetometer/rm3100-core.c int val, int val2, long mask) mask 432 drivers/iio/magnetometer/rm3100-core.c switch (mask) { mask 115 drivers/iio/magnetometer/st_magn_core.c .mask = 0x1c, mask 129 drivers/iio/magnetometer/st_magn_core.c .mask = 0x03, mask 135 drivers/iio/magnetometer/st_magn_core.c .mask = 0xe0, mask 194 drivers/iio/magnetometer/st_magn_core.c .mask = 0x1c, mask 208 drivers/iio/magnetometer/st_magn_core.c .mask = 0x03, mask 214 drivers/iio/magnetometer/st_magn_core.c .mask = 0xe0, mask 273 drivers/iio/magnetometer/st_magn_core.c .mask = 0x1c, mask 287 drivers/iio/magnetometer/st_magn_core.c .mask = 0x03, mask 293 drivers/iio/magnetometer/st_magn_core.c .mask = 0x60, mask 319 drivers/iio/magnetometer/st_magn_core.c .mask = 0x40, mask 325 drivers/iio/magnetometer/st_magn_core.c .mask = 0x07, mask 345 drivers/iio/magnetometer/st_magn_core.c .mask = 0x0c, mask 355 drivers/iio/magnetometer/st_magn_core.c .mask = 0x03, mask 369 drivers/iio/magnetometer/st_magn_core.c .mask = 0x10, mask 374 drivers/iio/magnetometer/st_magn_core.c .mask = 0x01, mask 378 drivers/iio/magnetometer/st_magn_core.c .mask = 0x07, mask 388 drivers/iio/magnetometer/st_magn_core.c int *val2, long mask) mask 393 drivers/iio/magnetometer/st_magn_core.c switch (mask) { mask 420 drivers/iio/magnetometer/st_magn_core.c struct iio_chan_spec const *chan, int val, int val2, long mask) mask 424 drivers/iio/magnetometer/st_magn_core.c switch (mask) { mask 87 drivers/iio/multiplexer/iio-mux.c int *val, int *val2, long mask) mask 97 drivers/iio/multiplexer/iio-mux.c switch (mask) { mask 118 drivers/iio/multiplexer/iio-mux.c long mask) mask 128 drivers/iio/multiplexer/iio-mux.c switch (mask) { mask 145 drivers/iio/multiplexer/iio-mux.c int val, int val2, long mask) mask 155 drivers/iio/multiplexer/iio-mux.c switch (mask) { mask 96 drivers/iio/orientation/hid-sensor-incl-3d.c long mask) mask 106 drivers/iio/orientation/hid-sensor-incl-3d.c switch (mask) { mask 157 drivers/iio/orientation/hid-sensor-incl-3d.c long mask) mask 162 drivers/iio/orientation/hid-sensor-incl-3d.c switch (mask) { mask 62 drivers/iio/orientation/hid-sensor-rotation.c long mask) mask 71 drivers/iio/orientation/hid-sensor-rotation.c switch (mask) { mask 111 drivers/iio/orientation/hid-sensor-rotation.c long mask) mask 116 drivers/iio/orientation/hid-sensor-rotation.c switch (mask) { mask 100 drivers/iio/potentiometer/ad5272.c int *val, int *val2, long mask) mask 105 drivers/iio/potentiometer/ad5272.c switch (mask) { mask 122 drivers/iio/potentiometer/ad5272.c int val, int val2, long mask) mask 126 drivers/iio/potentiometer/ad5272.c if (mask != IIO_CHAN_INFO_RAW) mask 59 drivers/iio/potentiometer/ds1803.c int *val, int *val2, long mask) mask 66 drivers/iio/potentiometer/ds1803.c switch (mask) { mask 87 drivers/iio/potentiometer/ds1803.c int val, int val2, long mask) mask 95 drivers/iio/potentiometer/ds1803.c switch (mask) { mask 45 drivers/iio/potentiometer/max5432.c int *val, int *val2, long mask) mask 49 drivers/iio/potentiometer/max5432.c if (mask != IIO_CHAN_INFO_SCALE) mask 63 drivers/iio/potentiometer/max5432.c int val, int val2, long mask) mask 68 drivers/iio/potentiometer/max5432.c if (mask != IIO_CHAN_INFO_RAW) mask 87 drivers/iio/potentiometer/max5481.c int *val, int *val2, long mask) mask 91 drivers/iio/potentiometer/max5481.c if (mask != IIO_CHAN_INFO_SCALE) mask 102 drivers/iio/potentiometer/max5481.c int val, int val2, long mask) mask 106 drivers/iio/potentiometer/max5481.c if (mask != IIO_CHAN_INFO_RAW) mask 51 drivers/iio/potentiometer/max5487.c int *val, int *val2, long mask) mask 55 drivers/iio/potentiometer/max5487.c if (mask != IIO_CHAN_INFO_SCALE) mask 66 drivers/iio/potentiometer/max5487.c int val, int val2, long mask) mask 70 drivers/iio/potentiometer/max5487.c if (mask != IIO_CHAN_INFO_RAW) mask 58 drivers/iio/potentiometer/mcp4018.c int *val, int *val2, long mask) mask 63 drivers/iio/potentiometer/mcp4018.c switch (mask) { mask 81 drivers/iio/potentiometer/mcp4018.c int val, int val2, long mask) mask 85 drivers/iio/potentiometer/mcp4018.c switch (mask) { mask 82 drivers/iio/potentiometer/mcp41010.c int *val, int *val2, long mask) mask 87 drivers/iio/potentiometer/mcp41010.c switch (mask) { mask 103 drivers/iio/potentiometer/mcp41010.c int val, int val2, long mask) mask 109 drivers/iio/potentiometer/mcp41010.c if (mask != IIO_CHAN_INFO_RAW) mask 166 drivers/iio/potentiometer/mcp4131.c int *val, int *val2, long mask) mask 172 drivers/iio/potentiometer/mcp4131.c switch (mask) { mask 207 drivers/iio/potentiometer/mcp4131.c int val, int val2, long mask) mask 213 drivers/iio/potentiometer/mcp4131.c switch (mask) { mask 141 drivers/iio/potentiometer/mcp4531.c int *val, int *val2, long mask) mask 147 drivers/iio/potentiometer/mcp4531.c switch (mask) { mask 167 drivers/iio/potentiometer/mcp4531.c long mask) mask 171 drivers/iio/potentiometer/mcp4531.c switch (mask) { mask 184 drivers/iio/potentiometer/mcp4531.c int val, int val2, long mask) mask 189 drivers/iio/potentiometer/mcp4531.c switch (mask) { mask 65 drivers/iio/potentiometer/tpl0102.c int *val, int *val2, long mask) mask 69 drivers/iio/potentiometer/tpl0102.c switch (mask) { mask 87 drivers/iio/potentiometer/tpl0102.c long mask) mask 91 drivers/iio/potentiometer/tpl0102.c switch (mask) { mask 104 drivers/iio/potentiometer/tpl0102.c int val, int val2, long mask) mask 108 drivers/iio/potentiometer/tpl0102.c if (mask != IIO_CHAN_INFO_RAW) mask 157 drivers/iio/potentiostat/lmp91000.c int *val, int *val2, long mask) mask 161 drivers/iio/potentiostat/lmp91000.c switch (mask) { mask 176 drivers/iio/potentiostat/lmp91000.c if (mask == IIO_CHAN_INFO_PROCESSED) { mask 132 drivers/iio/pressure/abp060mg.c int *val2, long mask) mask 139 drivers/iio/pressure/abp060mg.c switch (mask) { mask 428 drivers/iio/pressure/bmp280-core.c int *val, int *val2, long mask) mask 436 drivers/iio/pressure/bmp280-core.c switch (mask) { mask 537 drivers/iio/pressure/bmp280-core.c int val, int val2, long mask) mask 542 drivers/iio/pressure/bmp280-core.c switch (mask) { mask 39 drivers/iio/pressure/cros_ec_baro.c int *val, int *val2, long mask) mask 48 drivers/iio/pressure/cros_ec_baro.c switch (mask) { mask 74 drivers/iio/pressure/cros_ec_baro.c mask); mask 85 drivers/iio/pressure/cros_ec_baro.c int val, int val2, long mask) mask 92 drivers/iio/pressure/cros_ec_baro.c switch (mask) { mask 105 drivers/iio/pressure/cros_ec_baro.c mask); mask 415 drivers/iio/pressure/dps310.c int val2, long mask) mask 423 drivers/iio/pressure/dps310.c switch (mask) { mask 544 drivers/iio/pressure/dps310.c long mask) mask 548 drivers/iio/pressure/dps310.c switch (mask) { mask 603 drivers/iio/pressure/dps310.c long mask) mask 607 drivers/iio/pressure/dps310.c switch (mask) { mask 643 drivers/iio/pressure/dps310.c int *val, int *val2, long mask) mask 649 drivers/iio/pressure/dps310.c return dps310_read_pressure(data, val, val2, mask); mask 652 drivers/iio/pressure/dps310.c return dps310_read_temp(data, val, val2, mask); mask 62 drivers/iio/pressure/hid-sensor-press.c long mask) mask 72 drivers/iio/pressure/hid-sensor-press.c switch (mask) { mask 131 drivers/iio/pressure/hid-sensor-press.c long mask) mask 136 drivers/iio/pressure/hid-sensor-press.c switch (mask) { mask 162 drivers/iio/pressure/hp03.c int *val, int *val2, long mask) mask 174 drivers/iio/pressure/hp03.c switch (mask) { mask 204 drivers/iio/pressure/hp206c.c int *val2, long mask) mask 213 drivers/iio/pressure/hp206c.c switch (mask) { mask 297 drivers/iio/pressure/hp206c.c int val, int val2, long mask) mask 302 drivers/iio/pressure/hp206c.c if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) mask 98 drivers/iio/pressure/mpl115.c int *val, int *val2, long mask) mask 103 drivers/iio/pressure/mpl115.c switch (mask) { mask 74 drivers/iio/pressure/mpl3115.c int *val, int *val2, long mask) mask 80 drivers/iio/pressure/mpl3115.c switch (mask) { mask 235 drivers/iio/pressure/ms5611_core.c int *val, int *val2, long mask) mask 241 drivers/iio/pressure/ms5611_core.c switch (mask) { mask 304 drivers/iio/pressure/ms5611_core.c int val, int val2, long mask) mask 310 drivers/iio/pressure/ms5611_core.c if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) mask 38 drivers/iio/pressure/ms5637.c int *val2, long mask) mask 45 drivers/iio/pressure/ms5637.c switch (mask) { mask 77 drivers/iio/pressure/ms5637.c int val, int val2, long mask) mask 82 drivers/iio/pressure/ms5637.c switch (mask) { mask 247 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 257 drivers/iio/pressure/st_pressure_core.c .mask = 0x80, mask 263 drivers/iio/pressure/st_pressure_core.c .mask = 0x30, mask 278 drivers/iio/pressure/st_pressure_core.c .mask = 0x04, mask 283 drivers/iio/pressure/st_pressure_core.c .mask = 0x04, mask 289 drivers/iio/pressure/st_pressure_core.c .mask = 0x20, mask 297 drivers/iio/pressure/st_pressure_core.c .mask = 0x03, mask 320 drivers/iio/pressure/st_pressure_core.c .mask = 0x30, mask 329 drivers/iio/pressure/st_pressure_core.c .mask = 0x40, mask 348 drivers/iio/pressure/st_pressure_core.c .mask = 0x04, mask 372 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 382 drivers/iio/pressure/st_pressure_core.c .mask = 0x80, mask 401 drivers/iio/pressure/st_pressure_core.c .mask = 0x04, mask 406 drivers/iio/pressure/st_pressure_core.c .mask = 0x01, mask 414 drivers/iio/pressure/st_pressure_core.c .mask = 0x03, mask 441 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 452 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 470 drivers/iio/pressure/st_pressure_core.c .mask = 0x02, mask 475 drivers/iio/pressure/st_pressure_core.c .mask = 0x04, mask 483 drivers/iio/pressure/st_pressure_core.c .mask = 0x03, mask 508 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 521 drivers/iio/pressure/st_pressure_core.c .mask = 0x70, mask 539 drivers/iio/pressure/st_pressure_core.c .mask = BIT(1), mask 544 drivers/iio/pressure/st_pressure_core.c .mask = BIT(2), mask 552 drivers/iio/pressure/st_pressure_core.c .mask = 0x03, mask 568 drivers/iio/pressure/st_pressure_core.c long mask) mask 572 drivers/iio/pressure/st_pressure_core.c switch (mask) { mask 587 drivers/iio/pressure/st_pressure_core.c int *val2, long mask) mask 592 drivers/iio/pressure/st_pressure_core.c switch (mask) { mask 128 drivers/iio/pressure/t5403.c int *val, int *val2, long mask) mask 133 drivers/iio/pressure/t5403.c switch (mask) { mask 160 drivers/iio/pressure/t5403.c int val, int val2, long mask) mask 165 drivers/iio/pressure/t5403.c switch (mask) { mask 1480 drivers/iio/pressure/zpa2326.c long mask) mask 1482 drivers/iio/pressure/zpa2326.c switch (mask) { mask 1544 drivers/iio/pressure/zpa2326.c long mask) mask 1546 drivers/iio/pressure/zpa2326.c if ((mask != IIO_CHAN_INFO_SAMP_FREQ) || val2) mask 776 drivers/iio/proximity/isl29501.c int *val2, long mask) mask 780 drivers/iio/proximity/isl29501.c switch (mask) { mask 885 drivers/iio/proximity/isl29501.c int val, int val2, long mask) mask 889 drivers/iio/proximity/isl29501.c switch (mask) { mask 135 drivers/iio/proximity/mb1232.c int *val2, long mask) mask 143 drivers/iio/proximity/mb1232.c switch (mask) { mask 193 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c int *val, int *val2, long mask) mask 198 drivers/iio/proximity/pulsedlight-lidar-lite-v2.c switch (mask) { mask 163 drivers/iio/proximity/rfd77402.c int *val, int *val2, long mask) mask 168 drivers/iio/proximity/rfd77402.c switch (mask) { mask 205 drivers/iio/proximity/srf08.c int *val2, long mask) mask 213 drivers/iio/proximity/srf08.c switch (mask) { mask 381 drivers/iio/proximity/sx9500.c int *val, int *val2, long mask) mask 388 drivers/iio/proximity/sx9500.c switch (mask) { mask 432 drivers/iio/proximity/sx9500.c int val, int val2, long mask) mask 438 drivers/iio/proximity/sx9500.c switch (mask) { mask 90 drivers/iio/proximity/vl53l0x-i2c.c int *val, int *val2, long mask) mask 98 drivers/iio/proximity/vl53l0x-i2c.c switch (mask) { mask 53 drivers/iio/temperature/hid-sensor-temperature.c int *val, int *val2, long mask) mask 57 drivers/iio/temperature/hid-sensor-temperature.c switch (mask) { mask 99 drivers/iio/temperature/hid-sensor-temperature.c int val, int val2, long mask) mask 103 drivers/iio/temperature/hid-sensor-temperature.c switch (mask) { mask 187 drivers/iio/temperature/max31856.c int *val, int *val2, long mask) mask 192 drivers/iio/temperature/max31856.c switch (mask) { mask 169 drivers/iio/temperature/maxim_thermocouple.c int *val, int *val2, long mask) mask 174 drivers/iio/temperature/maxim_thermocouple.c switch (mask) { mask 219 drivers/iio/temperature/mlx90614.c int *val2, long mask) mask 225 drivers/iio/temperature/mlx90614.c switch (mask) { mask 310 drivers/iio/temperature/mlx90614.c int val2, long mask) mask 315 drivers/iio/temperature/mlx90614.c switch (mask) { mask 349 drivers/iio/temperature/mlx90614.c long mask) mask 351 drivers/iio/temperature/mlx90614.c switch (mask) { mask 521 drivers/iio/temperature/mlx90632.c int *val2, long mask) mask 526 drivers/iio/temperature/mlx90632.c switch (mask) { mask 559 drivers/iio/temperature/mlx90632.c int val2, long mask) mask 563 drivers/iio/temperature/mlx90632.c switch (mask) { mask 75 drivers/iio/temperature/tmp006.c int *val2, long mask) mask 81 drivers/iio/temperature/tmp006.c switch (mask) { mask 127 drivers/iio/temperature/tmp006.c long mask) mask 132 drivers/iio/temperature/tmp006.c if (mask != IIO_CHAN_INFO_SAMP_FREQ) mask 103 drivers/iio/temperature/tmp007.c int *val2, long mask) mask 109 drivers/iio/temperature/tmp007.c switch (mask) { mask 148 drivers/iio/temperature/tmp007.c int val2, long mask) mask 154 drivers/iio/temperature/tmp007.c if (mask == IIO_CHAN_INFO_SAMP_FREQ) { mask 262 drivers/iio/temperature/tmp007.c unsigned int mask; mask 267 drivers/iio/temperature/tmp007.c mask = TMP007_STATUS_LHF; mask 269 drivers/iio/temperature/tmp007.c mask = TMP007_STATUS_LLF; mask 273 drivers/iio/temperature/tmp007.c mask = TMP007_STATUS_OHF; mask 275 drivers/iio/temperature/tmp007.c mask = TMP007_STATUS_OLF; mask 281 drivers/iio/temperature/tmp007.c return !!(data->status_mask & mask); mask 81 drivers/iio/temperature/tsys01.c int *val2, long mask) mask 86 drivers/iio/temperature/tsys01.c switch (mask) { mask 31 drivers/iio/temperature/tsys02d.c int *val2, long mask) mask 37 drivers/iio/temperature/tsys02d.c switch (mask) { mask 62 drivers/iio/temperature/tsys02d.c int val, int val2, long mask) mask 67 drivers/iio/temperature/tsys02d.c switch (mask) { mask 289 drivers/iio/trigger/stm32-timer-trigger.c u32 mask, shift, master_mode_max; mask 293 drivers/iio/trigger/stm32-timer-trigger.c mask = TIM_CR2_MMS2; mask 297 drivers/iio/trigger/stm32-timer-trigger.c mask = TIM_CR2_MMS; mask 305 drivers/iio/trigger/stm32-timer-trigger.c regmap_update_bits(priv->regmap, TIM_CR2, mask, mask 409 drivers/iio/trigger/stm32-timer-trigger.c int *val, int *val2, long mask) mask 414 drivers/iio/trigger/stm32-timer-trigger.c switch (mask) { mask 444 drivers/iio/trigger/stm32-timer-trigger.c int val, int val2, long mask) mask 449 drivers/iio/trigger/stm32-timer-trigger.c switch (mask) { mask 464 drivers/infiniband/core/cache.c unsigned long mask, int *pempty) mask 511 drivers/infiniband/core/cache.c if (mask & GID_ATTR_FIND_MASK_GID_TYPE && mask 515 drivers/infiniband/core/cache.c if (mask & GID_ATTR_FIND_MASK_GID && mask 519 drivers/infiniband/core/cache.c if (mask & GID_ATTR_FIND_MASK_NETDEV && mask 523 drivers/infiniband/core/cache.c if (mask & GID_ATTR_FIND_MASK_DEFAULT && mask 544 drivers/infiniband/core/cache.c unsigned long mask, bool default_gid) mask 562 drivers/infiniband/core/cache.c ix = find_gid(table, gid, attr, default_gid, mask, &empty); mask 589 drivers/infiniband/core/cache.c unsigned long mask = GID_ATTR_FIND_MASK_GID | mask 593 drivers/infiniband/core/cache.c return __ib_cache_gid_add(ib_dev, port, gid, attr, mask, false); mask 599 drivers/infiniband/core/cache.c unsigned long mask, bool default_gid) mask 609 drivers/infiniband/core/cache.c ix = find_gid(table, gid, attr, default_gid, mask, NULL); mask 629 drivers/infiniband/core/cache.c unsigned long mask = GID_ATTR_FIND_MASK_GID | mask 634 drivers/infiniband/core/cache.c return _ib_cache_gid_del(ib_dev, port, gid, attr, mask, false); mask 687 drivers/infiniband/core/cache.c unsigned long mask = GID_ATTR_FIND_MASK_GID | mask 699 drivers/infiniband/core/cache.c mask |= GID_ATTR_FIND_MASK_NETDEV; mask 702 drivers/infiniband/core/cache.c local_index = find_gid(table, gid, &val, false, mask, NULL); mask 847 drivers/infiniband/core/cache.c unsigned long mask; mask 849 drivers/infiniband/core/cache.c mask = GID_ATTR_FIND_MASK_GID_TYPE | mask 864 drivers/infiniband/core/cache.c &gid_attr, mask, true); mask 867 drivers/infiniband/core/cache.c &gid_attr, mask, true); mask 999 drivers/infiniband/core/cache.c unsigned long mask = GID_ATTR_FIND_MASK_GID | mask 1005 drivers/infiniband/core/cache.c mask |= GID_ATTR_FIND_MASK_NETDEV; mask 1014 drivers/infiniband/core/cache.c index = find_gid(table, gid, &gid_attr_val, false, mask, NULL); mask 3245 drivers/infiniband/core/cma.c u64 sid, mask; mask 3261 drivers/infiniband/core/cma.c mask = be64_to_cpu(sib->sib_sid_mask); mask 3262 drivers/infiniband/core/cma.c sib->sib_sid = cpu_to_be64((sid & mask) | (u64) ntohs(port)); mask 3465 drivers/infiniband/core/cma.c u64 sid_ps, mask, sid; mask 3468 drivers/infiniband/core/cma.c mask = be64_to_cpu(sib->sib_sid_mask) & RDMA_IB_IP_PS_MASK; mask 3469 drivers/infiniband/core/cma.c sid = be64_to_cpu(sib->sib_sid) & mask; mask 3471 drivers/infiniband/core/cma.c if ((id_priv->id.ps == RDMA_PS_IB) && (sid == (RDMA_IB_IP_PS_IB & mask))) { mask 3475 drivers/infiniband/core/cma.c (sid == (RDMA_IB_IP_PS_TCP & mask))) { mask 3479 drivers/infiniband/core/cma.c (sid == (RDMA_IB_IP_PS_UDP & mask))) { mask 23 drivers/infiniband/core/counters.c curr->mask = new_mask; mask 35 drivers/infiniband/core/counters.c bool on, enum rdma_nl_counter_mask mask) mask 47 drivers/infiniband/core/counters.c RDMA_COUNTER_MODE_AUTO, mask); mask 140 drivers/infiniband/core/counters.c counter->mode.mask = new_mask; mask 239 drivers/infiniband/core/counters.c if (auto_mode_match(qp, counter, port_counter->mode.mask)) mask 307 drivers/infiniband/core/counters.c auto_mode_init_counter(counter, qp, port_counter->mode.mask); mask 601 drivers/infiniband/core/counters.c enum rdma_nl_counter_mask *mask) mask 607 drivers/infiniband/core/counters.c *mask = port_counter->mode.mask; mask 660 drivers/infiniband/core/nldev.c if ((m->mask & RDMA_COUNTER_MASK_QP_TYPE) && mask 1669 drivers/infiniband/core/nldev.c u32 index, port, mode, mask = 0, qpn, cntn = 0; mask 1710 drivers/infiniband/core/nldev.c mask = nla_get_u32( mask 1714 drivers/infiniband/core/nldev.c mask ? true : false, mask); mask 1917 drivers/infiniband/core/nldev.c static enum rdma_nl_counter_mask mask; mask 1952 drivers/infiniband/core/nldev.c ret = rdma_counter_get_mode(device, port, &mode, &mask); mask 1964 drivers/infiniband/core/nldev.c nla_put_u32(msg, RDMA_NLDEV_ATTR_STAT_AUTO_MODE_MASK, mask)) { mask 73 drivers/infiniband/core/packer.c __be32 mask; mask 84 drivers/infiniband/core/packer.c mask = cpu_to_be32(((1ull << desc[i].size_bits) - 1) << shift); mask 86 drivers/infiniband/core/packer.c *addr = (*addr & ~mask) | (cpu_to_be32(val) & mask); mask 90 drivers/infiniband/core/packer.c __be64 mask; mask 101 drivers/infiniband/core/packer.c mask = cpu_to_be64((~0ull >> (64 - desc[i].size_bits)) << shift); mask 103 drivers/infiniband/core/packer.c *addr = (*addr & ~mask) | (cpu_to_be64(val) & mask); mask 162 drivers/infiniband/core/packer.c u32 mask; mask 166 drivers/infiniband/core/packer.c mask = ((1ull << desc[i].size_bits) - 1) << shift; mask 168 drivers/infiniband/core/packer.c val = (be32_to_cpup(addr) & mask) >> shift; mask 176 drivers/infiniband/core/packer.c u64 mask; mask 180 drivers/infiniband/core/packer.c mask = (~0ull >> (64 - desc[i].size_bits)) << shift; mask 182 drivers/infiniband/core/packer.c val = (be64_to_cpup(addr) & mask) >> shift; mask 931 drivers/infiniband/core/sa_query.c u32 mask = 0; mask 939 drivers/infiniband/core/sa_query.c mask = IB_PATH_PRIMARY | IB_PATH_OUTBOUND; mask 945 drivers/infiniband/core/sa_query.c mask = IB_PATH_PRIMARY | IB_PATH_GMP | mask 956 drivers/infiniband/core/sa_query.c if ((rec->flags & mask) == mask) { mask 1739 drivers/infiniband/core/ucma.c __poll_t mask = 0; mask 1744 drivers/infiniband/core/ucma.c mask = EPOLLIN | EPOLLRDNORM; mask 1746 drivers/infiniband/core/ucma.c return mask; mask 151 drivers/infiniband/core/umem.c dma_addr_t mask; mask 160 drivers/infiniband/core/umem.c mask = roundup_pow_of_two(umem->length); mask 168 drivers/infiniband/core/umem.c mask |= (sg_dma_address(sg) + pgoff) ^ va; mask 175 drivers/infiniband/core/umem.c mask |= va; mask 178 drivers/infiniband/core/umem.c best_pg_bit = rdma_find_pg_bit(mask, pgsz_bitmap); mask 654 drivers/infiniband/core/user_mad.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; mask 659 drivers/infiniband/core/user_mad.c mask |= EPOLLIN | EPOLLRDNORM; mask 661 drivers/infiniband/core/user_mad.c return mask; mask 1724 drivers/infiniband/core/uverbs_cmd.c static int modify_qp_mask(enum ib_qp_type qp_type, int mask) mask 1728 drivers/infiniband/core/uverbs_cmd.c return mask & ~(IB_QP_MAX_DEST_RD_ATOMIC | IB_QP_MIN_RNR_TIMER); mask 1730 drivers/infiniband/core/uverbs_cmd.c return mask & ~(IB_QP_MAX_QP_RD_ATOMIC | IB_QP_RETRY_CNT | mask 1733 drivers/infiniband/core/uverbs_cmd.c return mask; mask 2757 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->eth.mask, kern_spec_mask, actual_filter_sz); mask 2768 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->ipv4.mask, kern_spec_mask, actual_filter_sz); mask 2779 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->ipv6.mask, kern_spec_mask, actual_filter_sz); mask 2781 drivers/infiniband/core/uverbs_cmd.c if ((ntohl(ib_spec->ipv6.mask.flow_label)) >= BIT(20) || mask 2795 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->tcp_udp.mask, kern_spec_mask, actual_filter_sz); mask 2806 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->tunnel.mask, kern_spec_mask, actual_filter_sz); mask 2808 drivers/infiniband/core/uverbs_cmd.c if ((ntohl(ib_spec->tunnel.mask.tunnel_id)) >= BIT(24) || mask 2821 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->esp.mask, kern_spec_mask, actual_filter_sz); mask 2832 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->gre.mask, kern_spec_mask, actual_filter_sz); mask 2843 drivers/infiniband/core/uverbs_cmd.c memcpy(&ib_spec->mpls.mask, kern_spec_mask, actual_filter_sz); mask 1551 drivers/infiniband/core/verbs.c enum ib_qp_type type, enum ib_qp_attr_mask mask) mask 1555 drivers/infiniband/core/verbs.c if (mask & IB_QP_CUR_STATE && mask 1566 drivers/infiniband/core/verbs.c if ((mask & req_param) != req_param) mask 1569 drivers/infiniband/core/verbs.c if (mask & ~(req_param | opt_param | IB_QP_STATE)) mask 1113 drivers/infiniband/hw/bnxt_re/main.c int mask = IB_QP_STATE; mask 1128 drivers/infiniband/hw/bnxt_re/main.c bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, mask, mask 400 drivers/infiniband/hw/bnxt_re/qplib_fp.c cpumask_clear(&nq->mask); mask 401 drivers/infiniband/hw/bnxt_re/qplib_fp.c cpumask_set_cpu(nq_indx, &nq->mask); mask 402 drivers/infiniband/hw/bnxt_re/qplib_fp.c rc = irq_set_affinity_hint(nq->vector, &nq->mask); mask 478 drivers/infiniband/hw/bnxt_re/qplib_fp.h cpumask_t mask; mask 198 drivers/infiniband/hw/cxgb3/iwch_cm.c req->mask = cpu_to_be64(1ULL << S_TCB_RX_QUIESCE); mask 219 drivers/infiniband/hw/cxgb3/iwch_cm.c req->mask = cpu_to_be64(1ULL << S_TCB_RX_QUIESCE); mask 815 drivers/infiniband/hw/cxgb3/iwch_cm.c enum iwch_qp_attr_mask mask; mask 916 drivers/infiniband/hw/cxgb3/iwch_cm.c mask = IWCH_QP_ATTR_NEXT_STATE | mask 922 drivers/infiniband/hw/cxgb3/iwch_cm.c ep->com.qp, mask, &attrs, 1); mask 1784 drivers/infiniband/hw/cxgb3/iwch_cm.c enum iwch_qp_attr_mask mask; mask 1825 drivers/infiniband/hw/cxgb3/iwch_cm.c mask = IWCH_QP_ATTR_NEXT_STATE | mask 1832 drivers/infiniband/hw/cxgb3/iwch_cm.c ep->com.qp, mask, &attrs, 1); mask 358 drivers/infiniband/hw/cxgb3/iwch_provider.c const u64 mask = (total_size + PAGE_SIZE - 1) & PAGE_MASK; mask 397 drivers/infiniband/hw/cxgb3/iwch_provider.c __func__, mask, shift, total_size, npages); mask 858 drivers/infiniband/hw/cxgb3/iwch_provider.c enum iwch_qp_attr_mask mask = 0; mask 882 drivers/infiniband/hw/cxgb3/iwch_provider.c mask |= (attr_mask & IB_QP_STATE) ? IWCH_QP_ATTR_NEXT_STATE : 0; mask 883 drivers/infiniband/hw/cxgb3/iwch_provider.c mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? mask 888 drivers/infiniband/hw/cxgb3/iwch_provider.c return iwch_modify_qp(rhp, qhp, mask, &attrs, 0); mask 262 drivers/infiniband/hw/cxgb3/iwch_provider.h enum iwch_qp_attr_mask mask, mask 816 drivers/infiniband/hw/cxgb3/iwch_qp.c enum iwch_qp_attr_mask mask, mask 868 drivers/infiniband/hw/cxgb3/iwch_qp.c enum iwch_qp_attr_mask mask, mask 883 drivers/infiniband/hw/cxgb3/iwch_qp.c (mask & IWCH_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); mask 888 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_VALID_MODIFY) { mask 893 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_ENABLE_RDMA_READ) mask 895 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_ENABLE_RDMA_WRITE) mask 897 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_ENABLE_RDMA_BIND) mask 899 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_MAX_ORD) { mask 907 drivers/infiniband/hw/cxgb3/iwch_qp.c if (mask & IWCH_QP_ATTR_MAX_IRD) { mask 918 drivers/infiniband/hw/cxgb3/iwch_qp.c if (!(mask & IWCH_QP_ATTR_NEXT_STATE)) mask 927 drivers/infiniband/hw/cxgb3/iwch_qp.c if (!(mask & IWCH_QP_ATTR_LLP_STREAM_HANDLE)) { mask 931 drivers/infiniband/hw/cxgb3/iwch_qp.c if (!(mask & IWCH_QP_ATTR_MPA_ATTR)) { mask 948 drivers/infiniband/hw/cxgb3/iwch_qp.c ret = rdma_init(rhp, qhp, mask, attrs); mask 1467 drivers/infiniband/hw/cxgb4/cm.c enum c4iw_qp_attr_mask mask; mask 1638 drivers/infiniband/hw/cxgb4/cm.c mask = C4IW_QP_ATTR_NEXT_STATE | mask 1644 drivers/infiniband/hw/cxgb4/cm.c ep->com.qp, mask, &attrs, 1); mask 3120 drivers/infiniband/hw/cxgb4/cm.c enum c4iw_qp_attr_mask mask; mask 3197 drivers/infiniband/hw/cxgb4/cm.c mask = C4IW_QP_ATTR_NEXT_STATE | mask 3204 drivers/infiniband/hw/cxgb4/cm.c ep->com.qp, mask, &attrs, 1); mask 3833 drivers/infiniband/hw/cxgb4/cm.c static inline u32 t4_tcb_get_field32(__be64 *tcb, u16 word, u32 mask, u32 shift) mask 3840 drivers/infiniband/hw/cxgb4/cm.c v = (t >> shift) & mask; mask 605 drivers/infiniband/hw/cxgb4/iw_cxgb4.h enum c4iw_qp_attr_mask mask, mask 1832 drivers/infiniband/hw/cxgb4/qp.c enum c4iw_qp_attr_mask mask, mask 1846 drivers/infiniband/hw/cxgb4/qp.c (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); mask 1851 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_VALID_MODIFY) { mask 1856 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) mask 1858 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) mask 1860 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) mask 1862 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_MAX_ORD) { mask 1869 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_MAX_IRD) { mask 1879 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_SQ_DB) { mask 1883 drivers/infiniband/hw/cxgb4/qp.c if (mask & C4IW_QP_ATTR_RQ_DB) { mask 1888 drivers/infiniband/hw/cxgb4/qp.c if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) mask 1897 drivers/infiniband/hw/cxgb4/qp.c if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { mask 1901 drivers/infiniband/hw/cxgb4/qp.c if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { mask 2372 drivers/infiniband/hw/cxgb4/qp.c enum c4iw_qp_attr_mask mask = 0; mask 2396 drivers/infiniband/hw/cxgb4/qp.c mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; mask 2397 drivers/infiniband/hw/cxgb4/qp.c mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? mask 2409 drivers/infiniband/hw/cxgb4/qp.c mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; mask 2410 drivers/infiniband/hw/cxgb4/qp.c mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; mask 2412 drivers/infiniband/hw/cxgb4/qp.c (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB))) mask 2415 drivers/infiniband/hw/cxgb4/qp.c return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); mask 76 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear(&set->mask); mask 84 drivers/infiniband/hw/hfi1/affinity.c if (cpumask_equal(&set->mask, &set->used)) { mask 98 drivers/infiniband/hw/hfi1/affinity.c cpumask_copy(&set->used, &set->mask); mask 113 drivers/infiniband/hw/hfi1/affinity.c cpumask_andnot(diff, &set->mask, &set->used); mask 174 drivers/infiniband/hw/hfi1/affinity.c cpumask_copy(&node_affinity.proc.mask, cpu_online_mask); mask 179 drivers/infiniband/hw/hfi1/affinity.c cpumask_first(&node_affinity.proc.mask) mask 383 drivers/infiniband/hw/hfi1/affinity.c cpumask_andnot(available_cpus, &set->mask, &set->used); mask 540 drivers/infiniband/hw/hfi1/affinity.c struct cpumask *dev_comp_vect_mask = &dd->comp_vect->mask; mask 611 drivers/infiniband/hw/hfi1/affinity.c cpu = per_cpu_affinity_put_max(&dd->comp_vect->mask, mask 615 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear_cpu(cpu, &dd->comp_vect->mask); mask 676 drivers/infiniband/hw/hfi1/affinity.c cpumask_and(&entry->def_intr.mask, &node_affinity.real_cpu_mask, mask 680 drivers/infiniband/hw/hfi1/affinity.c possible = cpumask_weight(&entry->def_intr.mask); mask 681 drivers/infiniband/hw/hfi1/affinity.c curr_cpu = cpumask_first(&entry->def_intr.mask); mask 685 drivers/infiniband/hw/hfi1/affinity.c cpumask_set_cpu(curr_cpu, &entry->rcv_intr.mask); mask 693 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear_cpu(curr_cpu, &entry->def_intr.mask); mask 696 drivers/infiniband/hw/hfi1/affinity.c &entry->def_intr.mask); mask 707 drivers/infiniband/hw/hfi1/affinity.c &entry->def_intr.mask); mask 709 drivers/infiniband/hw/hfi1/affinity.c &entry->rcv_intr.mask); mask 711 drivers/infiniband/hw/hfi1/affinity.c &entry->def_intr.mask); mask 721 drivers/infiniband/hw/hfi1/affinity.c if (cpumask_weight(&entry->def_intr.mask) == 0) mask 722 drivers/infiniband/hw/hfi1/affinity.c cpumask_copy(&entry->def_intr.mask, mask 731 drivers/infiniband/hw/hfi1/affinity.c &entry->rcv_intr.mask); mask 809 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear(&msix->mask); mask 810 drivers/infiniband/hw/hfi1/affinity.c cpumask_set_cpu(cpu, &msix->mask); mask 814 drivers/infiniband/hw/hfi1/affinity.c irq_set_affinity_hint(msix->irq, &msix->mask); mask 821 drivers/infiniband/hw/hfi1/affinity.c cpumask_set_cpu(cpu, &set->mask); mask 830 drivers/infiniband/hw/hfi1/affinity.c if (cpumask_test_cpu(old_cpu, &other_msix->mask)) mask 833 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear_cpu(old_cpu, &set->mask); mask 840 drivers/infiniband/hw/hfi1/affinity.c const cpumask_t *mask) mask 842 drivers/infiniband/hw/hfi1/affinity.c int cpu = cpumask_first(mask); mask 897 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear(&msix->mask); mask 942 drivers/infiniband/hw/hfi1/affinity.c cpumask_set_cpu(cpu, &msix->mask); mask 946 drivers/infiniband/hw/hfi1/affinity.c irq_set_affinity_hint(msix->irq, &msix->mask); mask 996 drivers/infiniband/hw/hfi1/affinity.c cpumask_andnot(&set->used, &set->used, &msix->mask); mask 1001 drivers/infiniband/hw/hfi1/affinity.c cpumask_clear(&msix->mask); mask 1014 drivers/infiniband/hw/hfi1/affinity.c cpumask_copy(hw_thread_mask, &affinity->proc.mask); mask 1062 drivers/infiniband/hw/hfi1/affinity.c } else if (current->nr_cpus_allowed < cpumask_weight(&set->mask)) { mask 1117 drivers/infiniband/hw/hfi1/affinity.c &entry->def_intr.mask : mask 1120 drivers/infiniband/hw/hfi1/affinity.c &entry->rcv_intr.mask : mask 1127 drivers/infiniband/hw/hfi1/affinity.c cpumask_copy(hw_thread_mask, &set->mask); mask 68 drivers/infiniband/hw/hfi1/affinity.h struct cpumask mask; mask 1098 drivers/infiniband/hw/hfi1/chip.c u32 mask; /* mask CSR offset */ mask 5246 drivers/infiniband/hw/hfi1/chip.c u64 mask; mask 5250 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); mask 5251 drivers/infiniband/hw/hfi1/chip.c return !(mask & BIT_ULL(bit)); mask 5846 drivers/infiniband/hw/hfi1/chip.c u64 mask = 1ULL << shift; mask 5850 drivers/infiniband/hw/hfi1/chip.c handled |= mask; mask 5855 drivers/infiniband/hw/hfi1/chip.c handled |= mask; mask 5857 drivers/infiniband/hw/hfi1/chip.c reg_copy &= ~mask; mask 5921 drivers/infiniband/hw/hfi1/chip.c u64 mask; mask 5929 drivers/infiniband/hw/hfi1/chip.c mask = read_kctxt_csr(dd, context, eri->mask); mask 5930 drivers/infiniband/hw/hfi1/chip.c mask &= ~reg; mask 5931 drivers/infiniband/hw/hfi1/chip.c write_kctxt_csr(dd, context, eri->mask, mask); mask 8929 drivers/infiniband/hw/hfi1/chip.c u32 mask; mask 8931 drivers/infiniband/hw/hfi1/chip.c mask = (HOST_INTERFACE_VERSION_MASK << HOST_INTERFACE_VERSION_SHIFT); mask 8934 drivers/infiniband/hw/hfi1/chip.c frame &= ~mask; mask 9430 drivers/infiniband/hw/hfi1/chip.c u64 mask; mask 9448 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, dd->hfi1_id ? mask 9450 drivers/infiniband/hw/hfi1/chip.c if (!(mask & QSFP_HFI0_INT_N)) mask 9464 drivers/infiniband/hw/hfi1/chip.c u64 mask; mask 9466 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); mask 9474 drivers/infiniband/hw/hfi1/chip.c mask |= (u64)QSFP_HFI0_INT_N; mask 9476 drivers/infiniband/hw/hfi1/chip.c mask &= ~(u64)QSFP_HFI0_INT_N; mask 9478 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK, mask); mask 9484 drivers/infiniband/hw/hfi1/chip.c u64 mask, qsfp_mask; mask 9490 drivers/infiniband/hw/hfi1/chip.c mask = (u64)QSFP_HFI0_RESET_N; mask 9494 drivers/infiniband/hw/hfi1/chip.c qsfp_mask &= ~mask; mask 9500 drivers/infiniband/hw/hfi1/chip.c qsfp_mask |= mask; mask 10135 drivers/infiniband/hw/hfi1/chip.c u32 mask = ~((1U << ppd->lmc) - 1); mask 10148 drivers/infiniband/hw/hfi1/chip.c ((mask & DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK) mask 10155 drivers/infiniband/hw/hfi1/chip.c sreg = ((mask & SEND_CTXT_CHECK_SLID_MASK_MASK) << mask 10157 drivers/infiniband/hw/hfi1/chip.c (((lid & mask) & SEND_CTXT_CHECK_SLID_VALUE_MASK) << mask 10167 drivers/infiniband/hw/hfi1/chip.c sdma_update_lmc(dd, mask, lid); mask 11317 drivers/infiniband/hw/hfi1/chip.c static void wait_for_vl_status_clear(struct hfi1_devdata *dd, u64 mask, mask 11325 drivers/infiniband/hw/hfi1/chip.c reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; mask 11336 drivers/infiniband/hw/hfi1/chip.c which, VL_STATUS_CLEAR_TIMEOUT, mask, reg); mask 14783 drivers/infiniband/hw/hfi1/chip.c u64 mask; mask 14786 drivers/infiniband/hw/hfi1/chip.c mask = read_csr(dd, CCE_INT_MASK); mask 14806 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK, mask); mask 14810 drivers/infiniband/hw/hfi1/chip.c write_csr(dd, CCE_INT_MASK, mask); mask 531 drivers/infiniband/hw/hfi1/debugfs.c u32 mask; mask 533 drivers/infiniband/hw/hfi1/debugfs.c mask = flag << (hfi ? CR_DYN_SHIFT : 0); mask 534 drivers/infiniband/hw/hfi1/debugfs.c if (scratch0 & mask) { mask 537 drivers/infiniband/hw/hfi1/debugfs.c mask, hfi, what, mask 1399 drivers/infiniband/hw/hfi1/firmware.c u8 mask = 1 << dd->hfi1_id; mask 1402 drivers/infiniband/hw/hfi1/firmware.c if (user == mask) { mask 1405 drivers/infiniband/hw/hfi1/firmware.c (u32)mask); mask 1412 drivers/infiniband/hw/hfi1/firmware.c write_csr(dd, ASIC_CFG_MUTEX, mask); mask 1414 drivers/infiniband/hw/hfi1/firmware.c if (user == mask) mask 1424 drivers/infiniband/hw/hfi1/firmware.c (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up"); mask 1438 drivers/infiniband/hw/hfi1/firmware.c u8 mask = 1 << dd->hfi1_id; mask 1441 drivers/infiniband/hw/hfi1/firmware.c if (user != mask) mask 1444 drivers/infiniband/hw/hfi1/firmware.c (u32)user, (u32)mask); mask 1740 drivers/infiniband/hw/hfi1/firmware.c u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask; mask 1750 drivers/infiniband/hw/hfi1/firmware.c mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1); mask 1751 drivers/infiniband/hw/hfi1/firmware.c ver_start = meta_ver_meta & mask; mask 1755 drivers/infiniband/hw/hfi1/firmware.c mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1); mask 1756 drivers/infiniband/hw/hfi1/firmware.c ver_len = meta_ver_meta & mask; mask 105 drivers/infiniband/hw/hfi1/hfi.h #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap) mask 106 drivers/infiniband/hw/hfi1/hfi.h #define HFI1_CAP_UGET_MASK(mask, cap) \ mask 107 drivers/infiniband/hw/hfi1/hfi.h (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap) mask 722 drivers/infiniband/hw/hfi1/hfi.h cpumask_t mask; mask 2246 drivers/infiniband/hw/hfi1/hfi.h u64 mask; mask 119 drivers/infiniband/hw/hfi1/intr.c if (hwerrs & hwerrmsgs[i].mask) mask 45 drivers/infiniband/hw/hfi1/opfn.c u16 mask, capcode; mask 62 drivers/infiniband/hw/hfi1/opfn.c mask = priv->opfn.requested & ~priv->opfn.completed; mask 63 drivers/infiniband/hw/hfi1/opfn.c capcode = ilog2(mask & ~(mask - 1)) + 1; mask 77 drivers/infiniband/hw/hfi1/pio.c u64 reg, mask; mask 91 drivers/infiniband/hw/hfi1/pio.c mask = 0; mask 94 drivers/infiniband/hw/hfi1/pio.c mask |= BIT_ULL(i); mask 96 drivers/infiniband/hw/hfi1/pio.c mask = (mask & SEND_CTRL_UNSUPPORTED_VL_MASK) << mask 98 drivers/infiniband/hw/hfi1/pio.c reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask; mask 1823 drivers/infiniband/hw/hfi1/pio.c e = m->map[vl & m->mask]; mask 1824 drivers/infiniband/hw/hfi1/pio.c rval = e->ksc[selector & e->mask]; mask 1944 drivers/infiniband/hw/hfi1/pio.c newmap->mask = (1 << ilog2(newmap->vls)) - 1; mask 1959 drivers/infiniband/hw/hfi1/pio.c newmap->map[i]->mask = (1 << ilog2(sz)) - 1; mask 2017 drivers/infiniband/hw/hfi1/pio.c u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */ mask 2065 drivers/infiniband/hw/hfi1/pio.c mask = all_vl_mask & ~(1LL << 15); mask 2066 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask); mask 2074 drivers/infiniband/hw/hfi1/pio.c mask = all_vl_mask & ~(data_vls_mask); mask 2075 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask); mask 2080 drivers/infiniband/hw/hfi1/pio.c mask = all_vl_mask & ~(data_vls_mask); mask 2081 drivers/infiniband/hw/hfi1/pio.c write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask); mask 245 drivers/infiniband/hw/hfi1/pio.h u32 mask; mask 263 drivers/infiniband/hw/hfi1/pio.h u32 mask; mask 804 drivers/infiniband/hw/hfi1/sdma.c e = m->map[vl & m->mask]; mask 805 drivers/infiniband/hw/hfi1/sdma.c rval = e->sde[selector & e->mask]; mask 834 drivers/infiniband/hw/hfi1/sdma.c u32 mask; mask 890 drivers/infiniband/hw/hfi1/sdma.c sde = map->sde[selector & map->mask]; mask 921 drivers/infiniband/hw/hfi1/sdma.c map->mask = pow - 1; mask 937 drivers/infiniband/hw/hfi1/sdma.c cpumask_var_t mask, new_mask; mask 946 drivers/infiniband/hw/hfi1/sdma.c ret = zalloc_cpumask_var(&mask, GFP_KERNEL); mask 952 drivers/infiniband/hw/hfi1/sdma.c free_cpumask_var(mask); mask 955 drivers/infiniband/hw/hfi1/sdma.c ret = cpulist_parse(buf, mask); mask 959 drivers/infiniband/hw/hfi1/sdma.c if (!cpumask_subset(mask, cpu_online_mask)) { mask 970 drivers/infiniband/hw/hfi1/sdma.c for_each_cpu(cpu, mask) { mask 993 drivers/infiniband/hw/hfi1/sdma.c rht_node->map[vl]->mask = 0; mask 1024 drivers/infiniband/hw/hfi1/sdma.c rht_node->map[vl]->mask = pow - 1; mask 1037 drivers/infiniband/hw/hfi1/sdma.c if (cpumask_test_cpu(cpu, mask)) mask 1081 drivers/infiniband/hw/hfi1/sdma.c free_cpumask_var(mask); mask 1231 drivers/infiniband/hw/hfi1/sdma.c newmap->mask = (1 << ilog2(newmap->vls)) - 1; mask 1249 drivers/infiniband/hw/hfi1/sdma.c newmap->map[i]->mask = (1 << ilog2(sz)) - 1; mask 3181 drivers/infiniband/hw/hfi1/sdma.c void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid) mask 3187 drivers/infiniband/hw/hfi1/sdma.c sreg = ((mask & SD(CHECK_SLID_MASK_MASK)) << mask 3189 drivers/infiniband/hw/hfi1/sdma.c (((lid & mask) & SD(CHECK_SLID_VALUE_MASK)) << mask 1004 drivers/infiniband/hw/hfi1/sdma.h u32 mask; mask 1024 drivers/infiniband/hw/hfi1/sdma.h u32 mask; mask 1091 drivers/infiniband/hw/hfi1/sdma.h void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid); mask 1145 drivers/infiniband/hw/hfi1/user_sdma.c mask = (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffffull : mask 1147 drivers/infiniband/hw/hfi1/user_sdma.c psn = val & mask; mask 1153 drivers/infiniband/hw/hfi1/user_sdma.c return psn & mask; mask 47 drivers/infiniband/hw/hns/hns_roce_alloc.c & bitmap->mask; mask 87 drivers/infiniband/hw/hns/hns_roce_alloc.c & bitmap->mask; mask 126 drivers/infiniband/hw/hns/hns_roce_alloc.c & bitmap->mask; mask 130 drivers/infiniband/hw/hns/hns_roce_alloc.c int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, mask 141 drivers/infiniband/hw/hns/hns_roce_alloc.c bitmap->mask = mask; mask 45 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_get_field(origin, mask, shift) \ mask 46 drivers/infiniband/hw/hns/hns_roce_common.h (((le32_to_cpu(origin)) & (mask)) >> (shift)) mask 51 drivers/infiniband/hw/hns/hns_roce_common.h #define roce_set_field(origin, mask, shift, val) \ mask 53 drivers/infiniband/hw/hns/hns_roce_common.h (origin) &= ~cpu_to_le32(mask); \ mask 54 drivers/infiniband/hw/hns/hns_roce_common.h (origin) |= cpu_to_le32(((u32)(val) << (shift)) & (mask)); \ mask 300 drivers/infiniband/hw/hns/hns_roce_device.h unsigned long mask; mask 1170 drivers/infiniband/hw/hns/hns_roce_device.h int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, mask 287 drivers/infiniband/hw/hns/hns_roce_main.c static int hns_roce_modify_device(struct ib_device *ib_dev, int mask, mask 292 drivers/infiniband/hw/hns/hns_roce_main.c if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) mask 295 drivers/infiniband/hw/hns/hns_roce_main.c if (mask & IB_DEVICE_MODIFY_NODE_DESC) { mask 304 drivers/infiniband/hw/hns/hns_roce_main.c static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask, mask 210 drivers/infiniband/hw/i40iw/i40iw.h cpumask_t mask; mask 551 drivers/infiniband/hw/i40iw/i40iw.h u32 size, u32 mask); mask 529 drivers/infiniband/hw/i40iw/i40iw_main.c u32 mask) mask 536 drivers/infiniband/hw/i40iw/i40iw_main.c if (mask) mask 537 drivers/infiniband/hw/i40iw/i40iw_main.c newva = ALIGN(va, (mask + 1)); mask 699 drivers/infiniband/hw/i40iw/i40iw_main.c cpumask_clear(&msix_vec->mask); mask 700 drivers/infiniband/hw/i40iw/i40iw_main.c cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); mask 701 drivers/infiniband/hw/i40iw/i40iw_main.c irq_set_affinity_hint(msix_vec->irq, &msix_vec->mask); mask 46 drivers/infiniband/hw/i40iw/i40iw_p.h void i40iw_debug_buf(struct i40iw_sc_dev *dev, enum i40iw_debug_flag mask, mask 700 drivers/infiniband/hw/i40iw/i40iw_utils.c enum i40iw_debug_flag mask, mask 707 drivers/infiniband/hw/i40iw/i40iw_utils.c if (!(dev->debug_mask & mask)) mask 709 drivers/infiniband/hw/i40iw/i40iw_utils.c i40iw_debug(dev, mask, "%s\n", desc); mask 710 drivers/infiniband/hw/i40iw/i40iw_utils.c i40iw_debug(dev, mask, "starting address virt=%p phy=%llxh\n", buf, mask 714 drivers/infiniband/hw/i40iw/i40iw_utils.c i40iw_debug(dev, mask, "index %03d val: %016llx\n", i, buf[i / 8]); mask 996 drivers/infiniband/hw/mlx4/main.c static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask, mask 1002 drivers/infiniband/hw/mlx4/main.c if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) mask 1005 drivers/infiniband/hw/mlx4/main.c if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) mask 1058 drivers/infiniband/hw/mlx4/main.c static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, mask 1084 drivers/infiniband/hw/mlx4/main.c !!(mask & IB_PORT_RESET_QKEY_CNTR), mask 1358 drivers/infiniband/hw/mlx4/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) mask 1364 drivers/infiniband/hw/mlx4/main.c memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac, mask 1367 drivers/infiniband/hw/mlx4/main.c mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag; mask 1370 drivers/infiniband/hw/mlx4/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD)) mask 1382 drivers/infiniband/hw/mlx4/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) mask 1387 drivers/infiniband/hw/mlx4/main.c mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip; mask 1389 drivers/infiniband/hw/mlx4/main.c mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip; mask 1394 drivers/infiniband/hw/mlx4/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD)) mask 1401 drivers/infiniband/hw/mlx4/main.c mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port; mask 1403 drivers/infiniband/hw/mlx4/main.c mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port; mask 1678 drivers/infiniband/hw/mlx4/main.c if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) { mask 1682 drivers/infiniband/hw/mlx4/main.c u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01, mask 1683 drivers/infiniband/hw/mlx4/main.c ib_spec->eth.mask.dst_mac[1], mask 1684 drivers/infiniband/hw/mlx4/main.c ib_spec->eth.mask.dst_mac[2], mask 1685 drivers/infiniband/hw/mlx4/main.c ib_spec->eth.mask.dst_mac[3], mask 1686 drivers/infiniband/hw/mlx4/main.c ib_spec->eth.mask.dst_mac[4], mask 1687 drivers/infiniband/hw/mlx4/main.c ib_spec->eth.mask.dst_mac[5]}; mask 3000 drivers/infiniband/hw/mlx4/main.c memset(&ib_spec->mask, 0, sizeof(ib_spec->mask)); mask 277 drivers/infiniband/hw/mlx5/gsi.c int mask; mask 280 drivers/infiniband/hw/mlx5/gsi.c mask = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY | IB_QP_PORT; mask 285 drivers/infiniband/hw/mlx5/gsi.c ret = ib_modify_qp(qp, &attr, mask); mask 1490 drivers/infiniband/hw/mlx5/main.c static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, mask 1498 drivers/infiniband/hw/mlx5/main.c if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) mask 1501 drivers/infiniband/hw/mlx5/main.c if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) mask 1519 drivers/infiniband/hw/mlx5/main.c static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask, mask 1535 drivers/infiniband/hw/mlx5/main.c if (~ctx.cap_mask1_perm & mask) { mask 1537 drivers/infiniband/hw/mlx5/main.c mask, ctx.cap_mask1_perm); mask 1543 drivers/infiniband/hw/mlx5/main.c ctx.cap_mask1_perm = mask; mask 1553 drivers/infiniband/hw/mlx5/main.c static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, mask 2539 drivers/infiniband/hw/mlx5/main.c static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) mask 2545 drivers/infiniband/hw/mlx5/main.c if (!mask) mask 2553 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); mask 2558 drivers/infiniband/hw/mlx5/main.c if (mask != entry_mask || val != entry_val) mask 2564 drivers/infiniband/hw/mlx5/main.c static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val, mask 2569 drivers/infiniband/hw/mlx5/main.c misc_c, inner_ipv6_flow_label, mask); mask 2574 drivers/infiniband/hw/mlx5/main.c misc_c, outer_ipv6_flow_label, mask); mask 2580 drivers/infiniband/hw/mlx5/main.c static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) mask 2582 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); mask 2584 drivers/infiniband/hw/mlx5/main.c MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); mask 2717 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) mask 2722 drivers/infiniband/hw/mlx5/main.c ib_spec->eth.mask.dst_mac); mask 2729 drivers/infiniband/hw/mlx5/main.c ib_spec->eth.mask.src_mac); mask 2734 drivers/infiniband/hw/mlx5/main.c if (ib_spec->eth.mask.vlan_tag) { mask 2741 drivers/infiniband/hw/mlx5/main.c first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); mask 2747 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->eth.mask.vlan_tag) >> 12); mask 2754 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->eth.mask.vlan_tag) >> 13); mask 2760 drivers/infiniband/hw/mlx5/main.c ethertype, ntohs(ib_spec->eth.mask.ether_type)); mask 2765 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) mask 2782 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv4.mask.src_ip, mask 2783 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv4.mask.src_ip)); mask 2790 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv4.mask.dst_ip, mask 2791 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv4.mask.dst_ip)); mask 2798 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); mask 2801 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv4.mask.proto, mask 2806 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) mask 2823 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv6.mask.src_ip, mask 2824 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv6.mask.src_ip)); mask 2831 drivers/infiniband/hw/mlx5/main.c &ib_spec->ipv6.mask.dst_ip, mask 2832 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->ipv6.mask.dst_ip)); mask 2839 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv6.mask.traffic_class, mask 2843 drivers/infiniband/hw/mlx5/main.c ib_spec->ipv6.mask.next_hdr, mask 2848 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->ipv6.mask.flow_label), mask 2853 drivers/infiniband/hw/mlx5/main.c if (ib_spec->esp.mask.seq) mask 2857 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->esp.mask.spi)); mask 2862 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, mask 2870 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.mask.src_port)); mask 2875 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.mask.dst_port)); mask 2880 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, mask 2888 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.mask.src_port)); mask 2893 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->tcp_udp.mask.dst_port)); mask 2898 drivers/infiniband/hw/mlx5/main.c if (ib_spec->gre.mask.c_ks_res0_ver) mask 2910 drivers/infiniband/hw/mlx5/main.c ntohs(ib_spec->gre.mask.protocol)); mask 2916 drivers/infiniband/hw/mlx5/main.c &ib_spec->gre.mask.key, mask 2917 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->gre.mask.key)); mask 2928 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag)) mask 2937 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag, mask 2938 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.mask.tag)); mask 2943 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag)) mask 2952 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag, mask 2953 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.mask.tag)); mask 2959 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag)) mask 2968 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag, mask 2969 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.mask.tag)); mask 2973 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag)) mask 2982 drivers/infiniband/hw/mlx5/main.c &ib_spec->mpls.mask.tag, mask 2983 drivers/infiniband/hw/mlx5/main.c sizeof(ib_spec->mpls.mask.tag)); mask 2988 drivers/infiniband/hw/mlx5/main.c if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask, mask 2993 drivers/infiniband/hw/mlx5/main.c ntohl(ib_spec->tunnel.mask.tunnel_id)); mask 3065 drivers/infiniband/hw/mlx5/main.c return is_multicast_ether_addr(eth_spec->mask.dst_mac) && mask 3135 drivers/infiniband/hw/mlx5/main.c ib_spec->eth.mask.ether_type) { mask 3136 drivers/infiniband/hw/mlx5/main.c mask_valid = (ib_spec->eth.mask.ether_type == mask 3706 drivers/infiniband/hw/mlx5/main.c .mask = {.dst_mac = {0x1} }, mask 3718 drivers/infiniband/hw/mlx5/main.c .mask = {.dst_mac = {0x1} }, mask 133 drivers/infiniband/hw/mlx5/mem.c int mask = (1 << shift) - 1; mask 174 drivers/infiniband/hw/mlx5/mem.c if (!(i & mask)) { mask 646 drivers/infiniband/hw/mlx5/mr.c if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) && mask 1520 drivers/infiniband/hw/mlx5/odp.c param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_FAULT; mask 3744 drivers/infiniband/hw/mlx5/qp.c static inline bool is_valid_mask(int mask, int req, int opt) mask 3746 drivers/infiniband/hw/mlx5/qp.c if ((mask & req) != req) mask 3749 drivers/infiniband/hw/mlx5/qp.c if (mask & ~(req | opt)) mask 4280 drivers/infiniband/hw/mlx5/qp.c static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) mask 4282 drivers/infiniband/hw/mlx5/qp.c if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && mask 4284 drivers/infiniband/hw/mlx5/qp.c (mask & MLX5_MKEY_MASK_A && mask 49 drivers/infiniband/hw/mthca/mthca_allocator.c alloc->top = (alloc->top + alloc->max) & alloc->mask; mask 74 drivers/infiniband/hw/mthca/mthca_allocator.c alloc->top = (alloc->top + alloc->max) & alloc->mask; mask 79 drivers/infiniband/hw/mthca/mthca_allocator.c int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask, mask 91 drivers/infiniband/hw/mthca/mthca_allocator.c alloc->mask = mask; mask 182 drivers/infiniband/hw/mthca/mthca_dev.h u32 mask; mask 416 drivers/infiniband/hw/mthca/mthca_dev.h int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask, mask 189 drivers/infiniband/hw/mthca/mthca_provider.c int mask, mask 192 drivers/infiniband/hw/mthca/mthca_provider.c if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) mask 195 drivers/infiniband/hw/mthca/mthca_provider.c if (mask & IB_DEVICE_MODIFY_NODE_DESC) { mask 193 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask, mask 1559 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c u32 mask = (1U << (idx % 32)); mask 1561 drivers/infiniband/hw/ocrdma/ocrdma_verbs.c srq->idx_bit_fields[i] ^= mask; mask 57 drivers/infiniband/hw/ocrdma/ocrdma_verbs.h int ocrdma_modify_port(struct ib_device *, u8 port, int mask, mask 254 drivers/infiniband/hw/qedr/verbs.c int qedr_modify_port(struct ib_device *ibdev, u8 port, int mask, mask 38 drivers/infiniband/hw/qedr/verbs.h int qedr_modify_port(struct ib_device *, u8 port, int mask, mask 441 drivers/infiniband/hw/qib/qib.h cpumask_var_t mask; mask 693 drivers/infiniband/hw/qib/qib.h u32 offs, u64 *data, u64 mask, int only_32); mask 795 drivers/infiniband/hw/qib/qib.h u32 mask); mask 1504 drivers/infiniband/hw/qib/qib.h u64 mask; mask 1509 drivers/infiniband/hw/qib/qib.h #define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b } mask 1003 drivers/infiniband/hw/qib/qib_iba6120.c u64 mask; mask 1053 drivers/infiniband/hw/qib/qib_iba6120.c mask = ERR_MASK(IBStatusChanged) | ERR_MASK(RcvEgrFullErr) | mask 1055 drivers/infiniband/hw/qib/qib_iba6120.c qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask); mask 1568 drivers/infiniband/hw/qib/qib_iba6120.c const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); mask 1575 drivers/infiniband/hw/qib/qib_iba6120.c if (mask & gpiostatus) { mask 1576 drivers/infiniband/hw/qib/qib_iba6120.c to_clear |= (gpiostatus & mask); mask 1577 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->gpio_mask &= ~(gpiostatus & mask); mask 2098 drivers/infiniband/hw/qib/qib_iba6120.c u64 mask, val; mask 2112 drivers/infiniband/hw/qib/qib_iba6120.c mask = (1ULL << dd->ctxtcnt) - 1; mask 2114 drivers/infiniband/hw/qib/qib_iba6120.c mask = (1ULL << ctxt); mask 2117 drivers/infiniband/hw/qib/qib_iba6120.c dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable)); mask 2130 drivers/infiniband/hw/qib/qib_iba6120.c dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable)); mask 2132 drivers/infiniband/hw/qib/qib_iba6120.c dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); mask 2134 drivers/infiniband/hw/qib/qib_iba6120.c dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); mask 3038 drivers/infiniband/hw/qib/qib_iba6120.c static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) mask 3043 drivers/infiniband/hw/qib/qib_iba6120.c if (mask) { mask 3045 drivers/infiniband/hw/qib/qib_iba6120.c dir &= mask; mask 3046 drivers/infiniband/hw/qib/qib_iba6120.c out &= mask; mask 3048 drivers/infiniband/hw/qib/qib_iba6120.c dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); mask 3050 drivers/infiniband/hw/qib/qib_iba6120.c new_out = (dd->cspec->gpio_out & ~mask) | out; mask 1100 drivers/infiniband/hw/qib/qib_iba7220.c u64 mask; mask 1154 drivers/infiniband/hw/qib/qib_iba7220.c mask = ERR_MASK(IBStatusChanged) | mask 1158 drivers/infiniband/hw/qib/qib_iba7220.c qib_decode_7220_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask); mask 1885 drivers/infiniband/hw/qib/qib_iba7220.c const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); mask 1886 drivers/infiniband/hw/qib/qib_iba7220.c u32 gpio_irq = mask & gpiostatus; mask 2732 drivers/infiniband/hw/qib/qib_iba7220.c u64 mask, val; mask 2745 drivers/infiniband/hw/qib/qib_iba7220.c mask = (1ULL << dd->ctxtcnt) - 1; mask 2747 drivers/infiniband/hw/qib/qib_iba7220.c mask = (1ULL << ctxt); mask 2750 drivers/infiniband/hw/qib/qib_iba7220.c dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable)); mask 2761 drivers/infiniband/hw/qib/qib_iba7220.c dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable)); mask 2763 drivers/infiniband/hw/qib/qib_iba7220.c dd->rcvctrl |= (mask << IBA7220_R_INTRAVAIL_SHIFT); mask 2765 drivers/infiniband/hw/qib/qib_iba7220.c dd->rcvctrl &= ~(mask << IBA7220_R_INTRAVAIL_SHIFT); mask 3749 drivers/infiniband/hw/qib/qib_iba7220.c static int gpio_7220_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) mask 3754 drivers/infiniband/hw/qib/qib_iba7220.c if (mask) { mask 3756 drivers/infiniband/hw/qib/qib_iba7220.c dir &= mask; mask 3757 drivers/infiniband/hw/qib/qib_iba7220.c out &= mask; mask 3759 drivers/infiniband/hw/qib/qib_iba7220.c dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); mask 3761 drivers/infiniband/hw/qib/qib_iba7220.c new_out = (dd->cspec->gpio_out & ~mask) | out; mask 3863 drivers/infiniband/hw/qib/qib_iba7220.c u32 offs, u64 *data, u64 mask, int only_32) mask 3879 drivers/infiniband/hw/qib/qib_iba7220.c if ((mask & all_bits) != all_bits) { mask 3897 drivers/infiniband/hw/qib/qib_iba7220.c *data = (local_data & ~mask) | (*data & mask); mask 3899 drivers/infiniband/hw/qib/qib_iba7220.c if (mask) { mask 3910 drivers/infiniband/hw/qib/qib_iba7220.c sval = (dd->sendctrl & ~mask); mask 3911 drivers/infiniband/hw/qib/qib_iba7220.c sval |= *data & SENDCTRL_SHADOWED & mask; mask 3913 drivers/infiniband/hw/qib/qib_iba7220.c tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); mask 702 drivers/infiniband/hw/qib/qib_iba7322.c u64 mask; mask 1200 drivers/infiniband/hw/qib/qib_iba7322.c #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \ mask 1202 drivers/infiniband/hw/qib/qib_iba7322.c #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \ mask 1221 drivers/infiniband/hw/qib/qib_iba7322.c { .mask = 0, .sz = 0 } mask 1224 drivers/infiniband/hw/qib/qib_iba7322.c #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \ mask 1226 drivers/infiniband/hw/qib/qib_iba7322.c #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \ mask 1243 drivers/infiniband/hw/qib/qib_iba7322.c { .mask = 0, .sz = 0 } mask 1253 drivers/infiniband/hw/qib/qib_iba7322.c {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted", mask 1290 drivers/infiniband/hw/qib/qib_iba7322.c { .mask = 0, .sz = 0 } mask 1297 drivers/infiniband/hw/qib/qib_iba7322.c #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \ mask 1300 drivers/infiniband/hw/qib/qib_iba7322.c #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\ mask 1305 drivers/infiniband/hw/qib/qib_iba7322.c #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\ mask 1313 drivers/infiniband/hw/qib/qib_iba7322.c #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\ mask 1319 drivers/infiniband/hw/qib/qib_iba7322.c { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \ mask 1329 drivers/infiniband/hw/qib/qib_iba7322.c { .mask = 0, .sz = 0 } mask 1374 drivers/infiniband/hw/qib/qib_iba7322.c while (errs && msp && msp->mask) { mask 1375 drivers/infiniband/hw/qib/qib_iba7322.c multi = (msp->mask & (msp->mask - 1)); mask 1376 drivers/infiniband/hw/qib/qib_iba7322.c while (errs & msp->mask) { mask 1377 drivers/infiniband/hw/qib/qib_iba7322.c these = (errs & msp->mask); mask 1398 drivers/infiniband/hw/qib/qib_iba7322.c while (lmask & msp->mask) { mask 1655 drivers/infiniband/hw/qib/qib_iba7322.c u64 mask; mask 1691 drivers/infiniband/hw/qib/qib_iba7322.c mask = QIB_E_HARDWARE; mask 1694 drivers/infiniband/hw/qib/qib_iba7322.c err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, mask 2705 drivers/infiniband/hw/qib/qib_iba7322.c cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; mask 2788 drivers/infiniband/hw/qib/qib_iba7322.c const cpumask_t *mask) mask 2792 drivers/infiniband/hw/qib/qib_iba7322.c int cpu = cpumask_first(mask); mask 2841 drivers/infiniband/hw/qib/qib_iba7322.c free_cpumask_var(dd->cspec->msix_entries[i].mask); mask 2882 drivers/infiniband/hw/qib/qib_iba7322.c u32 mask = QSFP_GPIO_MOD_PRS_N | mask 2888 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->gpio_mask &= ~mask; mask 2981 drivers/infiniband/hw/qib/qib_iba7322.c u32 mask; mask 2985 drivers/infiniband/hw/qib/qib_iba7322.c mask = QSFP_GPIO_MOD_PRS_N; mask 2987 drivers/infiniband/hw/qib/qib_iba7322.c mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); mask 2988 drivers/infiniband/hw/qib/qib_iba7322.c if (gpiostatus & dd->cspec->gpio_mask & mask) { mask 2992 drivers/infiniband/hw/qib/qib_iba7322.c gpiostatus &= ~mask; mask 2995 drivers/infiniband/hw/qib/qib_iba7322.c if (!(pins & mask)) { mask 3004 drivers/infiniband/hw/qib/qib_iba7322.c const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); mask 3005 drivers/infiniband/hw/qib/qib_iba7322.c u32 gpio_irq = mask & gpiostatus; mask 3382 drivers/infiniband/hw/qib/qib_iba7322.c u64 mask; mask 3426 drivers/infiniband/hw/qib/qib_iba7322.c mask = ~0ULL; mask 3511 drivers/infiniband/hw/qib/qib_iba7322.c mask &= ~(1ULL << lsb); mask 3518 drivers/infiniband/hw/qib/qib_iba7322.c &dd->cspec->msix_entries[msixnum].mask, mask 3522 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->msix_entries[msixnum].mask); mask 3529 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->msix_entries[msixnum].mask); mask 3533 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->msix_entries[msixnum].mask); mask 3540 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->main_int_mask = mask; mask 4486 drivers/infiniband/hw/qib/qib_iba7322.c u64 mask, val; mask 4504 drivers/infiniband/hw/qib/qib_iba7322.c mask = (1ULL << dd->ctxtcnt) - 1; mask 4507 drivers/infiniband/hw/qib/qib_iba7322.c mask = (1ULL << ctxt); mask 4512 drivers/infiniband/hw/qib/qib_iba7322.c (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); mask 4526 drivers/infiniband/hw/qib/qib_iba7322.c ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); mask 4528 drivers/infiniband/hw/qib/qib_iba7322.c dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); mask 4530 drivers/infiniband/hw/qib/qib_iba7322.c dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); mask 4532 drivers/infiniband/hw/qib/qib_iba7322.c dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); mask 4534 drivers/infiniband/hw/qib/qib_iba7322.c dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); mask 5696 drivers/infiniband/hw/qib/qib_iba7322.c static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) mask 5701 drivers/infiniband/hw/qib/qib_iba7322.c if (mask) { mask 5703 drivers/infiniband/hw/qib/qib_iba7322.c dir &= mask; mask 5704 drivers/infiniband/hw/qib/qib_iba7322.c out &= mask; mask 5706 drivers/infiniband/hw/qib/qib_iba7322.c dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); mask 5708 drivers/infiniband/hw/qib/qib_iba7322.c new_out = (dd->cspec->gpio_out & ~mask) | out; mask 5731 drivers/infiniband/hw/qib/qib_iba7322.c u32 mask; mask 5733 drivers/infiniband/hw/qib/qib_iba7322.c mask = 1 << QIB_EEPROM_WEN_NUM; mask 5735 drivers/infiniband/hw/qib/qib_iba7322.c gpio_7322_mod(dd, wen ? 0 : mask, mask, mask); mask 5839 drivers/infiniband/hw/qib/qib_iba7322.c u64 *data, u64 mask, int only_32) mask 5879 drivers/infiniband/hw/qib/qib_iba7322.c if (!ppd || (mask & all_bits) != all_bits) { mask 5891 drivers/infiniband/hw/qib/qib_iba7322.c *data = (local_data & ~mask) | (*data & mask); mask 5893 drivers/infiniband/hw/qib/qib_iba7322.c if (mask) { mask 5905 drivers/infiniband/hw/qib/qib_iba7322.c sval = ppd->p_sendctrl & ~mask; mask 5906 drivers/infiniband/hw/qib/qib_iba7322.c sval |= *data & SENDCTRL_SHADOWED & mask; mask 5909 drivers/infiniband/hw/qib/qib_iba7322.c sval = *data & SENDCTRL_SHADOWED & mask; mask 5910 drivers/infiniband/hw/qib/qib_iba7322.c tval = sval | (*data & ~SENDCTRL_SHADOWED & mask); mask 7737 drivers/infiniband/hw/qib/qib_iba7322.c u32 data, u32 mask) mask 7763 drivers/infiniband/hw/qib/qib_iba7322.c wr_data = data & mask & sz_mask; mask 7764 drivers/infiniband/hw/qib/qib_iba7322.c if ((~mask & sz_mask) != 0) { mask 7781 drivers/infiniband/hw/qib/qib_iba7322.c wr_data |= (rd_data & ~mask & sz_mask); mask 7785 drivers/infiniband/hw/qib/qib_iba7322.c if (mask & sz_mask) { mask 7809 drivers/infiniband/hw/qib/qib_iba7322.c unsigned mask) mask 7816 drivers/infiniband/hw/qib/qib_iba7322.c data, mask); mask 68 drivers/infiniband/hw/qib/qib_intr.c if (hwerrs & hwerrmsgs[i].mask) mask 402 drivers/infiniband/hw/qib/qib_pcie.c u32 mask, bits, val; mask 434 drivers/infiniband/hw/qib/qib_pcie.c mask = (3U << 24) | (7U << 10); mask 438 drivers/infiniband/hw/qib/qib_pcie.c mask = (3U << 24) | (7U << 10); mask 442 drivers/infiniband/hw/qib/qib_pcie.c mask = 7U << 10; mask 446 drivers/infiniband/hw/qib/qib_pcie.c mask = (3U << 24) | (7U << 10); mask 452 drivers/infiniband/hw/qib/qib_pcie.c val &= ~mask; mask 50 drivers/infiniband/hw/qib/qib_qsfp.c u32 out, mask; mask 71 drivers/infiniband/hw/qib/qib_qsfp.c mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE; mask 74 drivers/infiniband/hw/qib/qib_qsfp.c mask <<= QSFP_GPIO_PORT2_SHIFT; mask 78 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, out, mask, mask); mask 128 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, mask, mask, mask); mask 161 drivers/infiniband/hw/qib/qib_qsfp.c u32 out, mask; mask 181 drivers/infiniband/hw/qib/qib_qsfp.c mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE; mask 184 drivers/infiniband/hw/qib/qib_qsfp.c mask <<= QSFP_GPIO_PORT2_SHIFT; mask 187 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, out, mask, mask); mask 233 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, mask, mask, mask); mask 446 drivers/infiniband/hw/qib/qib_qsfp.c u32 mask; mask 449 drivers/infiniband/hw/qib/qib_qsfp.c mask = QSFP_GPIO_MOD_PRS_N << mask 453 drivers/infiniband/hw/qib/qib_qsfp.c return !((ret & mask) >> mask 464 drivers/infiniband/hw/qib/qib_qsfp.c u32 mask, highs; mask 476 drivers/infiniband/hw/qib/qib_qsfp.c mask = QSFP_GPIO_MOD_SEL_N | QSFP_GPIO_MOD_RST_N | QSFP_GPIO_LP_MODE; mask 477 drivers/infiniband/hw/qib/qib_qsfp.c highs = mask - QSFP_GPIO_MOD_RST_N; mask 479 drivers/infiniband/hw/qib/qib_qsfp.c mask <<= QSFP_GPIO_PORT2_SHIFT; mask 482 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, highs, mask, mask); mask 485 drivers/infiniband/hw/qib/qib_qsfp.c dd->f_gpio_mod(dd, mask, mask, mask); mask 99 drivers/infiniband/hw/qib/qib_sd7220.c u32 data, u32 mask); mask 101 drivers/infiniband/hw/qib/qib_sd7220.c int mask); mask 657 drivers/infiniband/hw/qib/qib_sd7220.c u32 wd, u32 mask) mask 700 drivers/infiniband/hw/qib/qib_sd7220.c if (mask != 0xFF) { mask 708 drivers/infiniband/hw/qib/qib_sd7220.c if (tries > 0 && mask != 0) { mask 712 drivers/infiniband/hw/qib/qib_sd7220.c wd = (wd & mask) | (transval & ~mask); mask 1128 drivers/infiniband/hw/qib/qib_sd7220.c int mask) mask 1142 drivers/infiniband/hw/qib/qib_sd7220.c if (mask != 0xFF) { mask 1154 drivers/infiniband/hw/qib/qib_sd7220.c val = (ret & ~mask) | (val & mask); mask 1173 drivers/infiniband/hw/qib/qib_sd7220.c ret = qib_sd7220_reg_mod(dd, IB_7220_SERDES, cloc, val, mask); mask 1180 drivers/infiniband/hw/qib/qib_sd7220.c val & 0xFF, mask & 0xFF); mask 91 drivers/infiniband/hw/qib/qib_twsi.c u32 mask; mask 95 drivers/infiniband/hw/qib/qib_twsi.c mask = 1UL << dd->gpio_scl_num; mask 98 drivers/infiniband/hw/qib/qib_twsi.c dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); mask 110 drivers/infiniband/hw/qib/qib_twsi.c if (mask & dd->f_gpio_mod(dd, 0, 0, 0)) mask 123 drivers/infiniband/hw/qib/qib_twsi.c u32 mask; mask 125 drivers/infiniband/hw/qib/qib_twsi.c mask = 1UL << dd->gpio_sda_num; mask 128 drivers/infiniband/hw/qib/qib_twsi.c dd->f_gpio_mod(dd, 0, bit ? 0 : mask, mask); mask 137 drivers/infiniband/hw/qib/qib_twsi.c u32 read_val, mask; mask 140 drivers/infiniband/hw/qib/qib_twsi.c mask = (1UL << bnum); mask 142 drivers/infiniband/hw/qib/qib_twsi.c dd->f_gpio_mod(dd, 0, 0, mask); mask 146 drivers/infiniband/hw/qib/qib_twsi.c return (read_val & mask) >> bnum; mask 267 drivers/infiniband/hw/qib/qib_twsi.c u32 pins, mask; mask 272 drivers/infiniband/hw/qib/qib_twsi.c mask = (1UL << dd->gpio_scl_num) | (1UL << dd->gpio_sda_num); mask 279 drivers/infiniband/hw/qib/qib_twsi.c dd->f_gpio_mod(dd, 0, 0, mask); mask 305 drivers/infiniband/hw/qib/qib_twsi.c if ((pins & mask) != mask) mask 307 drivers/infiniband/hw/qib/qib_twsi.c pins & mask); mask 171 drivers/infiniband/hw/qib/qib_tx.c void qib_disarm_piobufs_set(struct qib_devdata *dd, unsigned long *mask, mask 182 drivers/infiniband/hw/qib/qib_tx.c if (!test_bit(i, mask)) mask 66 drivers/infiniband/hw/usnic/usnic_uiom_interval_tree.c #define FLAGS_EQUAL(flags1, flags2, mask) \ mask 67 drivers/infiniband/hw/usnic/usnic_uiom_interval_tree.c (((flags1) & (mask)) == ((flags2) & (mask))) mask 104 drivers/infiniband/hw/vmw_pvrdma/pvrdma.h u32 mask; mask 55 drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c u32 mask = num - 1; mask 64 drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c tbl->mask = mask; mask 94 drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c tbl->top = (tbl->top + tbl->max) & tbl->mask; mask 125 drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c tbl->top = (tbl->top + tbl->max) & tbl->mask; mask 240 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c int pvrdma_modify_device(struct ib_device *ibdev, int mask, mask 245 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c if (mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID | mask 248 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c "unsupported device modify mask %#x\n", mask); mask 252 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c if (mask & IB_DEVICE_MODIFY_NODE_DESC) { mask 258 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c if (mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) { mask 277 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c int pvrdma_modify_port(struct ib_device *ibdev, u8 port, int mask, mask 284 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c if (mask & ~IB_PORT_SHUTDOWN) { mask 286 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c "unsupported port modify mask %#x\n", mask); mask 298 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c if (mask & IB_PORT_SHUTDOWN) mask 394 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h int pvrdma_modify_device(struct ib_device *ibdev, int mask, mask 397 drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h int mask, struct ib_port_modify *props); mask 209 drivers/infiniband/sw/rxe/rxe_comp.c if (wqe->mask & WR_ATOMIC_OR_READ_MASK) mask 229 drivers/infiniband/sw/rxe/rxe_comp.c } else if ((diff > 0) && (wqe->mask & WR_ATOMIC_OR_READ_MASK)) { mask 240 drivers/infiniband/sw/rxe/rxe_comp.c unsigned int mask = pkt->mask; mask 248 drivers/infiniband/sw/rxe/rxe_comp.c if (!(mask & RXE_START_MASK)) mask 379 drivers/infiniband/sw/rxe/rxe_comp.c if (wqe->dma.resid == 0 && (pkt->mask & RXE_END_MASK)) mask 637 drivers/infiniband/sw/rxe/rxe_comp.c if (pkt->mask & RXE_END_MASK) mask 46 drivers/infiniband/sw/rxe/rxe_hdr.h u32 mask; /* useful info about pkt */ mask 165 drivers/infiniband/sw/rxe/rxe_loc.h struct ib_qp_attr *attr, int mask); mask 168 drivers/infiniband/sw/rxe/rxe_loc.h int mask, struct ib_udata *udata); mask 170 drivers/infiniband/sw/rxe/rxe_loc.h int rxe_qp_to_attr(struct rxe_qp *qp, struct ib_qp_attr *attr, int mask); mask 223 drivers/infiniband/sw/rxe/rxe_loc.h struct ib_srq_attr *attr, enum ib_srq_attr_mask mask); mask 230 drivers/infiniband/sw/rxe/rxe_loc.h struct ib_srq_attr *attr, enum ib_srq_attr_mask mask, mask 247 drivers/infiniband/sw/rxe/rxe_loc.h return rxe_wr_opcode_info[opcode].mask[qp->ibqp.qp_type]; mask 254 drivers/infiniband/sw/rxe/rxe_loc.h int is_request = pkt->mask & RXE_REQ_MASK; mask 263 drivers/infiniband/sw/rxe/rxe_loc.h if (pkt->mask & RXE_LOOPBACK_MASK) { mask 278 drivers/infiniband/sw/rxe/rxe_loc.h (pkt->mask & RXE_END_MASK)) { mask 217 drivers/infiniband/sw/rxe/rxe_net.c pkt->mask = RXE_GRH_MASK; mask 406 drivers/infiniband/sw/rxe/rxe_net.c pkt->mask |= RXE_LOOPBACK_MASK; mask 507 drivers/infiniband/sw/rxe/rxe_net.c pkt->mask |= RXE_GRH_MASK; mask 44 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 51 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 58 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 68 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 78 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 84 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 90 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 96 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 102 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 110 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 116 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 122 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = { mask 131 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_RWR_MASK mask 141 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_SEND_MASK mask 151 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_COMP_MASK mask 161 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 173 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_COMP_MASK mask 184 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 197 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 209 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_WRITE_MASK mask 219 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_WRITE_MASK mask 229 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 242 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 255 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK mask 272 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_REQ_MASK | RXE_READ_MASK mask 284 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK mask 296 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_ACK_MASK | RXE_MIDDLE_MASK, mask 305 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK mask 317 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK mask 329 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_AETH_MASK | RXE_ACK_MASK | RXE_START_MASK mask 341 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_AETH_MASK | RXE_ATMACK_MASK | RXE_ACK_MASK mask 355 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_ATMETH_MASK | RXE_REQ_MASK | RXE_ATOMIC_MASK mask 367 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_ATMETH_MASK | RXE_REQ_MASK | RXE_ATOMIC_MASK mask 379 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 391 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 406 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_RWR_MASK mask 416 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_SEND_MASK mask 426 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_COMP_MASK mask 436 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 448 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_COMP_MASK mask 459 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 472 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 484 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_WRITE_MASK mask 494 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_PAYLOAD_MASK | RXE_REQ_MASK | RXE_WRITE_MASK mask 504 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_IMMDT_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 517 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 530 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK mask 549 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 565 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 581 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 597 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_IMMDT_MASK mask 619 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 635 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_IMMDT_MASK mask 657 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_RETH_MASK mask 678 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 694 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_PAYLOAD_MASK mask 710 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_IMMDT_MASK mask 732 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_RETH_MASK mask 754 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_RETH_MASK mask 782 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_RETH_MASK mask 803 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_AETH_MASK mask 819 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK mask 831 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_AETH_MASK | RXE_PAYLOAD_MASK mask 846 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_AETH_MASK | RXE_PAYLOAD_MASK mask 861 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_AETH_MASK | RXE_ACK_MASK mask 873 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_AETH_MASK | RXE_ATMACK_MASK mask 889 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_ATMETH_MASK mask 910 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_RDETH_MASK | RXE_DETH_MASK | RXE_ATMETH_MASK mask 933 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_DETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK mask 946 drivers/infiniband/sw/rxe/rxe_opcode.c .mask = RXE_DETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK mask 62 drivers/infiniband/sw/rxe/rxe_opcode.h enum rxe_wr_mask mask[WR_MAX_QPT]; mask 122 drivers/infiniband/sw/rxe/rxe_opcode.h enum rxe_hdr_mask mask; mask 415 drivers/infiniband/sw/rxe/rxe_qp.c struct ib_qp_attr *attr, int mask) mask 417 drivers/infiniband/sw/rxe/rxe_qp.c enum ib_qp_state cur_state = (mask & IB_QP_CUR_STATE) ? mask 419 drivers/infiniband/sw/rxe/rxe_qp.c enum ib_qp_state new_state = (mask & IB_QP_STATE) ? mask 422 drivers/infiniband/sw/rxe/rxe_qp.c if (!ib_modify_qp_is_ok(cur_state, new_state, qp_type(qp), mask)) { mask 427 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_STATE) { mask 435 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PORT) { mask 442 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_CAP && rxe_qp_chk_cap(rxe, &attr->cap, !!qp->srq)) mask 445 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_AV && rxe_av_chk_attr(rxe, &attr->ah_attr)) mask 448 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_ALT_PATH) { mask 462 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PATH_MTU) { mask 476 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_MAX_QP_RD_ATOMIC) { mask 485 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_TIMEOUT) { mask 589 drivers/infiniband/sw/rxe/rxe_qp.c int rxe_qp_from_attr(struct rxe_qp *qp, struct ib_qp_attr *attr, int mask, mask 594 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_MAX_QP_RD_ATOMIC) { mask 601 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_MAX_DEST_RD_ATOMIC) { mask 614 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_CUR_STATE) mask 617 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_EN_SQD_ASYNC_NOTIFY) mask 620 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_ACCESS_FLAGS) mask 623 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PKEY_INDEX) mask 626 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PORT) mask 629 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_QKEY) mask 632 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_AV) { mask 636 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_ALT_PATH) { mask 643 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PATH_MTU) { mask 648 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_TIMEOUT) { mask 660 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_RETRY_CNT) { mask 667 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_RNR_RETRY) { mask 674 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_RQ_PSN) { mask 681 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_MIN_RNR_TIMER) { mask 687 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_SQ_PSN) { mask 694 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_PATH_MIG_STATE) mask 697 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_DEST_QPN) mask 700 drivers/infiniband/sw/rxe/rxe_qp.c if (mask & IB_QP_STATE) { mask 746 drivers/infiniband/sw/rxe/rxe_qp.c int rxe_qp_to_attr(struct rxe_qp *qp, struct ib_qp_attr *attr, int mask) mask 71 drivers/infiniband/sw/rxe/rxe_recv.c if (pkt->mask & RXE_REQ_MASK) { mask 137 drivers/infiniband/sw/rxe/rxe_recv.c pkt->mask) { mask 254 drivers/infiniband/sw/rxe/rxe_recv.c if (unlikely((pkt->mask & RXE_GRH_MASK) == 0)) { mask 271 drivers/infiniband/sw/rxe/rxe_recv.c if (pkt->mask & RXE_REQ_MASK) mask 377 drivers/infiniband/sw/rxe/rxe_recv.c pkt->mask |= rxe_opcode[pkt->opcode].mask; mask 46 drivers/infiniband/sw/rxe/rxe_req.c unsigned int mask, int npsn) mask 63 drivers/infiniband/sw/rxe/rxe_req.c if (mask & WR_WRITE_MASK) mask 72 drivers/infiniband/sw/rxe/rxe_req.c unsigned int mask; mask 84 drivers/infiniband/sw/rxe/rxe_req.c mask = wr_opcode_mask(wqe->wr.opcode, qp); mask 92 drivers/infiniband/sw/rxe/rxe_req.c wqe->iova = (mask & WR_ATOMIC_MASK) ? mask 94 drivers/infiniband/sw/rxe/rxe_req.c (mask & WR_READ_OR_WRITE_MASK) ? mask 98 drivers/infiniband/sw/rxe/rxe_req.c if (!first || (mask & WR_READ_MASK) == 0) { mask 107 drivers/infiniband/sw/rxe/rxe_req.c if (mask & WR_WRITE_OR_SEND_MASK) { mask 110 drivers/infiniband/sw/rxe/rxe_req.c retry_first_write_send(qp, wqe, mask, npsn); mask 113 drivers/infiniband/sw/rxe/rxe_req.c if (mask & WR_READ_MASK) { mask 190 drivers/infiniband/sw/rxe/rxe_req.c wqe->mask = wr_opcode_mask(wqe->wr.opcode, qp); mask 404 drivers/infiniband/sw/rxe/rxe_req.c pkt->mask = rxe_opcode[opcode].mask; mask 417 drivers/infiniband/sw/rxe/rxe_req.c (pkt->mask & RXE_END_MASK) && mask 418 drivers/infiniband/sw/rxe/rxe_req.c ((pkt->mask & (RXE_SEND_MASK)) || mask 419 drivers/infiniband/sw/rxe/rxe_req.c (pkt->mask & (RXE_WRITE_MASK | RXE_IMMDT_MASK)) == mask 426 drivers/infiniband/sw/rxe/rxe_req.c qp_num = (pkt->mask & RXE_DETH_MASK) ? ibwr->wr.ud.remote_qpn : mask 429 drivers/infiniband/sw/rxe/rxe_req.c ack_req = ((pkt->mask & RXE_END_MASK) || mask 438 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_RETH_MASK) { mask 444 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_IMMDT_MASK) mask 447 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_IETH_MASK) mask 450 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_ATMETH_MASK) { mask 462 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_DETH_MASK) { mask 486 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_WRITE_OR_SEND) { mask 521 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_END_MASK) { mask 541 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_START_MASK) { mask 546 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_READ_MASK) mask 579 drivers/infiniband/sw/rxe/rxe_req.c if (pkt->mask & RXE_END_MASK) mask 595 drivers/infiniband/sw/rxe/rxe_req.c enum rxe_hdr_mask mask; mask 627 drivers/infiniband/sw/rxe/rxe_req.c if (wqe->mask & WR_REG_MASK) { mask 685 drivers/infiniband/sw/rxe/rxe_req.c mask = rxe_opcode[opcode].mask; mask 686 drivers/infiniband/sw/rxe/rxe_req.c if (unlikely(mask & RXE_READ_OR_ATOMIC)) { mask 692 drivers/infiniband/sw/rxe/rxe_req.c payload = (mask & RXE_WRITE_OR_SEND) ? wqe->dma.resid : 0; mask 172 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_START_MASK) { mask 283 drivers/infiniband/sw/rxe/rxe_resp.c if (((pkt->mask & RXE_READ_MASK) && mask 285 drivers/infiniband/sw/rxe/rxe_resp.c ((pkt->mask & RXE_WRITE_MASK) && mask 287 drivers/infiniband/sw/rxe/rxe_resp.c ((pkt->mask & RXE_ATOMIC_MASK) && mask 295 drivers/infiniband/sw/rxe/rxe_resp.c if ((pkt->mask & RXE_WRITE_MASK) && mask 380 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_READ_OR_ATOMIC) { mask 391 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_RWR_MASK) { mask 429 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & (RXE_READ_MASK | RXE_WRITE_MASK)) { mask 430 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_RETH_MASK) { mask 436 drivers/infiniband/sw/rxe/rxe_resp.c access = (pkt->mask & RXE_READ_MASK) ? IB_ACCESS_REMOTE_READ mask 438 drivers/infiniband/sw/rxe/rxe_resp.c } else if (pkt->mask & RXE_ATOMIC_MASK) { mask 448 drivers/infiniband/sw/rxe/rxe_resp.c if ((pkt->mask & (RXE_READ_MASK | RXE_WRITE_OR_SEND)) && mask 449 drivers/infiniband/sw/rxe/rxe_resp.c (pkt->mask & RXE_RETH_MASK) && mask 475 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_WRITE_MASK) { mask 614 drivers/infiniband/sw/rxe/rxe_resp.c ack->mask = rxe_opcode[opcode].mask; mask 629 drivers/infiniband/sw/rxe/rxe_resp.c if (ack->mask & RXE_AETH_MASK) { mask 634 drivers/infiniband/sw/rxe/rxe_resp.c if (ack->mask & RXE_ATMACK_MASK) mask 788 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_SEND_MASK) { mask 803 drivers/infiniband/sw/rxe/rxe_resp.c } else if (pkt->mask & RXE_WRITE_MASK) { mask 807 drivers/infiniband/sw/rxe/rxe_resp.c } else if (pkt->mask & RXE_READ_MASK) { mask 811 drivers/infiniband/sw/rxe/rxe_resp.c } else if (pkt->mask & RXE_ATOMIC_MASK) { mask 827 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_COMP_MASK) { mask 863 drivers/infiniband/sw/rxe/rxe_resp.c wc->opcode = (pkt->mask & RXE_IMMDT_MASK && mask 864 drivers/infiniband/sw/rxe/rxe_resp.c pkt->mask & RXE_WRITE_MASK) ? mask 867 drivers/infiniband/sw/rxe/rxe_resp.c wc->byte_len = (pkt->mask & RXE_IMMDT_MASK && mask 868 drivers/infiniband/sw/rxe/rxe_resp.c pkt->mask & RXE_WRITE_MASK) ? mask 877 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_IMMDT_MASK) { mask 882 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_IETH_MASK) { mask 889 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_DETH_MASK) mask 907 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_IMMDT_MASK) { mask 912 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_IETH_MASK) { mask 931 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_DETH_MASK) mask 1030 drivers/infiniband/sw/rxe/rxe_resp.c else if (pkt->mask & RXE_ATOMIC_MASK) mask 1082 drivers/infiniband/sw/rxe/rxe_resp.c if (pkt->mask & RXE_SEND_MASK || mask 1083 drivers/infiniband/sw/rxe/rxe_resp.c pkt->mask & RXE_WRITE_MASK) { mask 1089 drivers/infiniband/sw/rxe/rxe_resp.c } else if (pkt->mask & RXE_READ_MASK) { mask 40 drivers/infiniband/sw/rxe/rxe_srq.c struct ib_srq_attr *attr, enum ib_srq_attr_mask mask) mask 47 drivers/infiniband/sw/rxe/rxe_srq.c if (mask & IB_SRQ_MAX_WR) { mask 69 drivers/infiniband/sw/rxe/rxe_srq.c if (mask & IB_SRQ_LIMIT) { mask 84 drivers/infiniband/sw/rxe/rxe_srq.c if (mask == IB_SRQ_INIT_MASK) { mask 150 drivers/infiniband/sw/rxe/rxe_srq.c struct ib_srq_attr *attr, enum ib_srq_attr_mask mask, mask 157 drivers/infiniband/sw/rxe/rxe_srq.c if (mask & IB_SRQ_MAX_WR) { mask 172 drivers/infiniband/sw/rxe/rxe_srq.c if (mask & IB_SRQ_LIMIT) mask 105 drivers/infiniband/sw/rxe/rxe_verbs.c int mask, struct ib_device_modify *attr) mask 109 drivers/infiniband/sw/rxe/rxe_verbs.c if (mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) mask 112 drivers/infiniband/sw/rxe/rxe_verbs.c if (mask & IB_DEVICE_MODIFY_NODE_DESC) { mask 121 drivers/infiniband/sw/rxe/rxe_verbs.c u8 port_num, int mask, struct ib_port_modify *attr) mask 131 drivers/infiniband/sw/rxe/rxe_verbs.c if (mask & IB_PORT_RESET_QKEY_CNTR) mask 332 drivers/infiniband/sw/rxe/rxe_verbs.c enum ib_srq_attr_mask mask, mask 349 drivers/infiniband/sw/rxe/rxe_verbs.c err = rxe_srq_chk_attr(rxe, srq, attr, mask); mask 353 drivers/infiniband/sw/rxe/rxe_verbs.c err = rxe_srq_from_attr(rxe, srq, attr, mask, &ucmd, udata); mask 462 drivers/infiniband/sw/rxe/rxe_verbs.c int mask, struct ib_udata *udata) mask 468 drivers/infiniband/sw/rxe/rxe_verbs.c err = rxe_qp_chk_attr(rxe, qp, attr, mask); mask 472 drivers/infiniband/sw/rxe/rxe_verbs.c err = rxe_qp_from_attr(qp, attr, mask, udata); mask 483 drivers/infiniband/sw/rxe/rxe_verbs.c int mask, struct ib_qp_init_attr *init) mask 488 drivers/infiniband/sw/rxe/rxe_verbs.c rxe_qp_to_attr(qp, attr, mask); mask 504 drivers/infiniband/sw/rxe/rxe_verbs.c unsigned int mask, unsigned int length) mask 512 drivers/infiniband/sw/rxe/rxe_verbs.c if (unlikely(mask & WR_ATOMIC_MASK)) { mask 587 drivers/infiniband/sw/rxe/rxe_verbs.c unsigned int mask, unsigned int length, mask 612 drivers/infiniband/sw/rxe/rxe_verbs.c } else if (mask & WR_REG_MASK) { mask 613 drivers/infiniband/sw/rxe/rxe_verbs.c wqe->mask = mask; mask 620 drivers/infiniband/sw/rxe/rxe_verbs.c wqe->iova = mask & WR_ATOMIC_MASK ? atomic_wr(ibwr)->remote_addr : mask 621 drivers/infiniband/sw/rxe/rxe_verbs.c mask & WR_READ_OR_WRITE_MASK ? rdma_wr(ibwr)->remote_addr : 0; mask 622 drivers/infiniband/sw/rxe/rxe_verbs.c wqe->mask = mask; mask 635 drivers/infiniband/sw/rxe/rxe_verbs.c unsigned int mask, u32 length) mask 642 drivers/infiniband/sw/rxe/rxe_verbs.c err = validate_send_wr(qp, ibwr, mask, length); mask 655 drivers/infiniband/sw/rxe/rxe_verbs.c err = init_send_wqe(qp, ibwr, mask, length, send_wqe); mask 679 drivers/infiniband/sw/rxe/rxe_verbs.c unsigned int mask; mask 684 drivers/infiniband/sw/rxe/rxe_verbs.c mask = wr_opcode_mask(wr->opcode, qp); mask 685 drivers/infiniband/sw/rxe/rxe_verbs.c if (unlikely(!mask)) { mask 692 drivers/infiniband/sw/rxe/rxe_verbs.c !(mask & WR_INLINE_MASK))) { mask 702 drivers/infiniband/sw/rxe/rxe_verbs.c err = post_one_send(qp, wr, mask, length); mask 522 drivers/infiniband/sw/siw/siw.h enum siw_qp_attr_mask mask); mask 613 drivers/infiniband/sw/siw/siw_qp.c enum siw_qp_attr_mask mask) mask 615 drivers/infiniband/sw/siw/siw_qp.c if (mask & SIW_QP_ATTR_ACCESS_FLAGS) { mask 635 drivers/infiniband/sw/siw/siw_qp.c enum siw_qp_attr_mask mask) mask 646 drivers/infiniband/sw/siw/siw_qp.c if (!(mask & SIW_QP_ATTR_LLP_HANDLE)) { mask 651 drivers/infiniband/sw/siw/siw_qp.c if (!(mask & SIW_QP_ATTR_MPA)) { mask 825 drivers/infiniband/sw/siw/siw_qp.c enum siw_qp_attr_mask mask) mask 829 drivers/infiniband/sw/siw/siw_qp.c if (!mask) mask 836 drivers/infiniband/sw/siw/siw_qp.c if (mask != SIW_QP_ATTR_STATE) mask 837 drivers/infiniband/sw/siw/siw_qp.c siw_qp_modify_nonstate(qp, attrs, mask); mask 839 drivers/infiniband/sw/siw/siw_qp.c if (!(mask & SIW_QP_ATTR_STATE)) mask 845 drivers/infiniband/sw/siw/siw_qp.c rv = siw_qp_nextstate_from_idle(qp, attrs, mask); mask 80 drivers/infiniband/sw/siw/siw_verbs.h enum ib_srq_attr_mask mask, struct ib_udata *udata); mask 300 drivers/infiniband/ulp/ipoib/ipoib.h u32 mask; mask 1260 drivers/infiniband/ulp/ipoib/ipoib_main.c return hv & htbl->mask; mask 1529 drivers/infiniband/ulp/ipoib/ipoib_main.c htbl->mask = (size - 1); mask 356 drivers/infiniband/ulp/iser/iser_memory.c iser_set_prot_checks(struct scsi_cmnd *sc, u8 *mask) mask 358 drivers/infiniband/ulp/iser/iser_memory.c *mask = 0; mask 360 drivers/infiniband/ulp/iser/iser_memory.c *mask |= IB_SIG_CHECK_REFTAG; mask 362 drivers/infiniband/ulp/iser/iser_memory.c *mask |= IB_SIG_CHECK_GUARD; mask 79 drivers/input/evdev.c unsigned long *mask; mask 87 drivers/input/evdev.c mask = client->evmasks[0]; mask 88 drivers/input/evdev.c if (mask && !test_bit(type, mask)) mask 96 drivers/input/evdev.c mask = client->evmasks[type]; mask 97 drivers/input/evdev.c return mask && !test_bit(code, mask); mask 104 drivers/input/evdev.c unsigned int mask = client->bufsize - 1; mask 116 drivers/input/evdev.c for (i = client->tail; i != client->head; i = (i + 1) & mask) { mask 132 drivers/input/evdev.c head = (head + 1) & mask; mask 613 drivers/input/evdev.c __poll_t mask; mask 618 drivers/input/evdev.c mask = EPOLLOUT | EPOLLWRNORM; mask 620 drivers/input/evdev.c mask = EPOLLHUP | EPOLLERR; mask 623 drivers/input/evdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 625 drivers/input/evdev.c return mask; mask 960 drivers/input/evdev.c unsigned long flags, *mask, *oldmask; mask 969 drivers/input/evdev.c mask = bitmap_zalloc(cnt, GFP_KERNEL); mask 970 drivers/input/evdev.c if (!mask) mask 973 drivers/input/evdev.c error = bits_from_user(mask, cnt - 1, codes_size, codes, compat); mask 975 drivers/input/evdev.c bitmap_free(mask); mask 981 drivers/input/evdev.c client->evmasks[type] = mask; mask 996 drivers/input/evdev.c unsigned long *mask; mask 1007 drivers/input/evdev.c mask = client->evmasks[type]; mask 1008 drivers/input/evdev.c if (mask) { mask 1009 drivers/input/evdev.c error = bits_to_user(mask, cnt - 1, mask 1035 drivers/input/evdev.c struct input_mask mask; mask 1100 drivers/input/evdev.c if (copy_from_user(&mask, p, sizeof(mask))) mask 1103 drivers/input/evdev.c codes_ptr = (void __user *)(unsigned long)mask.codes_ptr; mask 1105 drivers/input/evdev.c mask.type, codes_ptr, mask.codes_size, mask 1112 drivers/input/evdev.c if (copy_from_user(&mask, p, sizeof(mask))) mask 1115 drivers/input/evdev.c codes_ptr = (const void __user *)(unsigned long)mask.codes_ptr; mask 1117 drivers/input/evdev.c mask.type, codes_ptr, mask.codes_size, mask 99 drivers/input/joystick/analog.c int mask; mask 108 drivers/input/joystick/analog.c unsigned char mask; mask 191 drivers/input/joystick/analog.c if (analog->mask & ANALOG_HAT_FCS) mask 199 drivers/input/joystick/analog.c if (analog->mask & (0x10 << i)) mask 202 drivers/input/joystick/analog.c if (analog->mask & ANALOG_HBTN_CHF) mask 206 drivers/input/joystick/analog.c if (analog->mask & ANALOG_BTN_TL) mask 208 drivers/input/joystick/analog.c if (analog->mask & ANALOG_BTN_TR) mask 210 drivers/input/joystick/analog.c if (analog->mask & ANALOG_BTN_TL2) mask 212 drivers/input/joystick/analog.c if (analog->mask & ANALOG_BTN_TR2) mask 216 drivers/input/joystick/analog.c if (analog->mask & (1 << i)) mask 220 drivers/input/joystick/analog.c if (analog->mask & analog_exts[i]) { mask 252 drivers/input/joystick/analog.c this = port->mask; mask 260 drivers/input/joystick/analog.c this = gameport_read(gameport) & port->mask; mask 281 drivers/input/joystick/analog.c return -(this != port->mask); mask 305 drivers/input/joystick/analog.c while (((u = gameport_read(port->gameport)) & port->mask) && t) t--; mask 321 drivers/input/joystick/analog.c char saitek = !!(port->analog[0].mask & ANALOG_SAITEK); mask 322 drivers/input/joystick/analog.c char chf = !!(port->analog[0].mask & ANALOG_ANY_CHF); mask 342 drivers/input/joystick/analog.c if (port->analog[i].mask) mask 423 drivers/input/joystick/analog.c hweight8(analog->mask & ANALOG_AXES_STD), mask 424 drivers/input/joystick/analog.c hweight8(analog->mask & ANALOG_BTNS_STD) + !!(analog->mask & ANALOG_BTNS_CHF) * 2 + mask 425 drivers/input/joystick/analog.c hweight16(analog->mask & ANALOG_BTNS_GAMEPAD) + !!(analog->mask & ANALOG_HBTN_CHF) * 4); mask 427 drivers/input/joystick/analog.c if (analog->mask & ANALOG_HATS_ALL) mask 429 drivers/input/joystick/analog.c analog->name, hweight16(analog->mask & ANALOG_HATS_ALL)); mask 431 drivers/input/joystick/analog.c if (analog->mask & ANALOG_HAT_FCS) mask 433 drivers/input/joystick/analog.c if (analog->mask & ANALOG_ANY_CHF) mask 434 drivers/input/joystick/analog.c strlcat(analog->name, (analog->mask & ANALOG_SAITEK) ? " Saitek" : " CHF", mask 437 drivers/input/joystick/analog.c strlcat(analog->name, (analog->mask & ANALOG_GAMEPAD) ? " gamepad": " joystick", mask 454 drivers/input/joystick/analog.c analog->buttons = (analog->mask & ANALOG_GAMEPAD) ? analog_pad_btn : analog_joy_btn; mask 464 drivers/input/joystick/analog.c input_dev->id.product = analog->mask >> 4; mask 476 drivers/input/joystick/analog.c if (analog->mask & (1 << i)) { mask 489 drivers/input/joystick/analog.c if (analog->mask & ANALOG_SAITEK) { mask 500 drivers/input/joystick/analog.c if (analog->mask & analog_exts[i]) mask 507 drivers/input/joystick/analog.c if (analog->mask & (0x10 << i)) mask 510 drivers/input/joystick/analog.c if (analog->mask & ANALOG_BTNS_CHF) mask 514 drivers/input/joystick/analog.c if (analog->mask & ANALOG_HBTN_CHF) mask 519 drivers/input/joystick/analog.c if (analog->mask & (ANALOG_BTN_TL << i)) mask 543 drivers/input/joystick/analog.c if (!port->mask) mask 546 drivers/input/joystick/analog.c if ((port->mask & 3) != 3 && port->mask != 0xc) { mask 549 drivers/input/joystick/analog.c port->mask, port->gameport->phys); mask 556 drivers/input/joystick/analog.c analog[0].mask = i & 0xfffff; mask 558 drivers/input/joystick/analog.c analog[0].mask &= ~(ANALOG_AXES_STD | ANALOG_HAT_FCS | ANALOG_BTNS_GAMEPAD) mask 559 drivers/input/joystick/analog.c | port->mask | ((port->mask << 8) & ANALOG_HAT_FCS) mask 560 drivers/input/joystick/analog.c | ((port->mask << 10) & ANALOG_BTNS_TLR) | ((port->mask << 12) & ANALOG_BTNS_TLR2); mask 562 drivers/input/joystick/analog.c analog[0].mask &= ~(ANALOG_HAT2_CHF) mask 563 drivers/input/joystick/analog.c | ((analog[0].mask & ANALOG_HBTN_CHF) ? 0 : ANALOG_HAT2_CHF); mask 565 drivers/input/joystick/analog.c analog[0].mask &= ~(ANALOG_THROTTLE | ANALOG_BTN_TR | ANALOG_BTN_TR2) mask 566 drivers/input/joystick/analog.c | ((~analog[0].mask & ANALOG_HAT_FCS) >> 8) mask 567 drivers/input/joystick/analog.c | ((~analog[0].mask & ANALOG_HAT_FCS) << 2) mask 568 drivers/input/joystick/analog.c | ((~analog[0].mask & ANALOG_HAT_FCS) << 4); mask 570 drivers/input/joystick/analog.c analog[0].mask &= ~(ANALOG_THROTTLE | ANALOG_RUDDER) mask 571 drivers/input/joystick/analog.c | (((~analog[0].mask & ANALOG_BTNS_TLR ) >> 10) mask 572 drivers/input/joystick/analog.c & ((~analog[0].mask & ANALOG_BTNS_TLR2) >> 12)); mask 574 drivers/input/joystick/analog.c analog[1].mask = ((i >> 20) & 0xff) | ((i >> 12) & 0xf0000); mask 576 drivers/input/joystick/analog.c analog[1].mask &= (analog[0].mask & ANALOG_EXTENSIONS) ? ANALOG_GAMEPAD mask 577 drivers/input/joystick/analog.c : (((ANALOG_BTNS_STD | port->mask) & ~analog[0].mask) | ANALOG_GAMEPAD); mask 583 drivers/input/joystick/analog.c if ((analog[0].mask & 0x7) == 0x7) max[2] = (max[0] + max[1]) >> 1; mask 584 drivers/input/joystick/analog.c if ((analog[0].mask & 0xb) == 0xb) max[3] = (max[0] + max[1]) >> 1; mask 585 drivers/input/joystick/analog.c if ((analog[0].mask & ANALOG_BTN_TL) && !(analog[0].mask & ANALOG_BTN_TL2)) max[2] >>= 1; mask 586 drivers/input/joystick/analog.c if ((analog[0].mask & ANALOG_BTN_TR) && !(analog[0].mask & ANALOG_BTN_TR2)) max[3] >>= 1; mask 587 drivers/input/joystick/analog.c if ((analog[0].mask & ANALOG_HAT_FCS)) max[3] >>= 1; mask 595 drivers/input/joystick/analog.c return -!(analog[0].mask || analog[1].mask); mask 613 drivers/input/joystick/analog.c port->mask = (gameport_read(gameport) ^ t) & t & 0xf; mask 627 drivers/input/joystick/analog.c while ((gameport_read(port->gameport) & port->mask) && (u < t)) mask 632 drivers/input/joystick/analog.c while ((gameport_read(port->gameport) & port->mask) && (v < t)) mask 651 drivers/input/joystick/analog.c port->mask |= 1 << i; mask 682 drivers/input/joystick/analog.c if (port->analog[i].mask) { mask 691 drivers/input/joystick/analog.c if (port->analog[i].mask) mask 705 drivers/input/joystick/analog.c if (port->analog[i].mask) mask 206 drivers/input/keyboard/cros_ec_keyb.c unsigned int ev_type, u32 mask) mask 219 drivers/input/keyboard/cros_ec_keyb.c !!(mask & BIT(map->bit)) ^ map->inverted); mask 74 drivers/input/keyboard/nomadik-ske-keypad.c u8 mask, u8 data) mask 81 drivers/input/keyboard/nomadik-ske-keypad.c ret &= ~mask; mask 594 drivers/input/keyboard/pxa27x_keypad.c unsigned int mask = 0, direct_key_num = 0; mask 609 drivers/input/keyboard/pxa27x_keypad.c mask |= 0x03; mask 615 drivers/input/keyboard/pxa27x_keypad.c mask |= 0x0c; mask 630 drivers/input/keyboard/pxa27x_keypad.c keypad->direct_key_mask = ((1 << direct_key_num) - 1) & ~mask; mask 109 drivers/input/keyboard/qt1070.c u8 new_keys, keyval, mask = 0x01; mask 118 drivers/input/keyboard/qt1070.c keyval = new_keys & mask; mask 119 drivers/input/keyboard/qt1070.c if ((data->last_keys & mask) != keyval) mask 121 drivers/input/keyboard/qt1070.c mask <<= 1; mask 164 drivers/input/keyboard/qt2160.c int ret, i, mask; mask 182 drivers/input/keyboard/qt2160.c mask = 0x01; mask 183 drivers/input/keyboard/qt2160.c for (i = 0; i < 16; ++i, mask <<= 1) { mask 184 drivers/input/keyboard/qt2160.c int keyval = new_matrix & mask; mask 186 drivers/input/keyboard/qt2160.c if ((old_matrix & mask) != keyval) { mask 34 drivers/input/keyboard/tc3589x-keypad.c #define TC3589x_IO_PULL_VAL(index, mask) ((mask)<<((index)%4)*2) mask 130 drivers/input/misc/ad714x.c unsigned short mask; mask 132 drivers/input/misc/ad714x.c mask = ((1 << (end_stage + 1)) - 1) - ((1 << start_stage) - 1); mask 139 drivers/input/misc/ad714x.c data &= ~mask; mask 147 drivers/input/misc/ad714x.c unsigned short mask; mask 149 drivers/input/misc/ad714x.c mask = ((1 << (end_stage + 1)) - 1) - ((1 << start_stage) - 1); mask 156 drivers/input/misc/ad714x.c data |= mask; mask 343 drivers/input/misc/ad714x.c unsigned short mask; mask 345 drivers/input/misc/ad714x.c mask = ((1 << (hw->end_stage + 1)) - 1) - ((1 << hw->start_stage) - 1); mask 347 drivers/input/misc/ad714x.c h_state = ad714x->h_state & mask; mask 348 drivers/input/misc/ad714x.c c_state = ad714x->c_state & mask; mask 363 drivers/input/misc/ad714x.c if (c_state == mask) { mask 373 drivers/input/misc/ad714x.c if (c_state == mask) { mask 515 drivers/input/misc/ad714x.c unsigned short mask; mask 517 drivers/input/misc/ad714x.c mask = ((1 << (hw->end_stage + 1)) - 1) - ((1 << hw->start_stage) - 1); mask 519 drivers/input/misc/ad714x.c h_state = ad714x->h_state & mask; mask 520 drivers/input/misc/ad714x.c c_state = ad714x->c_state & mask; mask 535 drivers/input/misc/ad714x.c if (c_state == mask) { mask 545 drivers/input/misc/ad714x.c if (c_state == mask) { mask 796 drivers/input/misc/ad714x.c unsigned short mask; mask 798 drivers/input/misc/ad714x.c mask = (((1 << (hw->x_end_stage + 1)) - 1) - mask 803 drivers/input/misc/ad714x.c h_state = ad714x->h_state & mask; mask 804 drivers/input/misc/ad714x.c c_state = ad714x->c_state & mask; mask 819 drivers/input/misc/ad714x.c if (c_state == mask) { mask 836 drivers/input/misc/ad714x.c if (c_state == mask) { mask 40 drivers/input/misc/ati_remote2.c unsigned int mask; mask 46 drivers/input/misc/ati_remote2.c ret = kstrtouint(val, 0, &mask); mask 50 drivers/input/misc/ati_remote2.c if (mask & ~max) mask 53 drivers/input/misc/ati_remote2.c *(unsigned int *)kp->arg = mask; mask 718 drivers/input/misc/ati_remote2.c unsigned int mask; mask 721 drivers/input/misc/ati_remote2.c r = kstrtouint(buf, 0, &mask); mask 725 drivers/input/misc/ati_remote2.c if (mask & ~ATI_REMOTE2_MAX_CHANNEL_MASK) mask 737 drivers/input/misc/ati_remote2.c if (mask != ar2->channel_mask) { mask 738 drivers/input/misc/ati_remote2.c r = ati_remote2_setup(ar2, mask); mask 740 drivers/input/misc/ati_remote2.c ar2->channel_mask = mask; mask 768 drivers/input/misc/ati_remote2.c unsigned int mask; mask 771 drivers/input/misc/ati_remote2.c err = kstrtouint(buf, 0, &mask); mask 775 drivers/input/misc/ati_remote2.c if (mask & ~ATI_REMOTE2_MAX_MODE_MASK) mask 778 drivers/input/misc/ati_remote2.c ar2->mode_mask = mask; mask 89 drivers/input/misc/axp20x-pek.c unsigned int mask, char *buf) mask 99 drivers/input/misc/axp20x-pek.c val &= mask; mask 100 drivers/input/misc/axp20x-pek.c val >>= ffs(mask) - 1; mask 131 drivers/input/misc/axp20x-pek.c unsigned int mask, const char *buf, mask 165 drivers/input/misc/axp20x-pek.c idx <<= ffs(mask) - 1; mask 167 drivers/input/misc/axp20x-pek.c mask, idx); mask 169 drivers/input/misc/bma150.c int val, int shift, u8 mask, u8 reg) mask 177 drivers/input/misc/bma150.c data = (data & ~mask) | ((val << shift) & mask); mask 59 drivers/input/misc/kxtj9.c u8 mask; mask 173 drivers/input/misc/kxtj9.c tj9->data_ctrl = kxtj9_odr_table[i].mask; mask 130 drivers/input/misc/pmic8xxx-pwrkey.c u8 mask, val; mask 144 drivers/input/misc/pmic8xxx-pwrkey.c mask = PON_CNTL_1_PULL_UP_EN | PON_CNTL_1_USB_PWR_EN; mask 145 drivers/input/misc/pmic8xxx-pwrkey.c mask |= PON_CNTL_1_WD_EN_RESET; mask 146 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; mask 150 drivers/input/misc/pmic8xxx-pwrkey.c regmap_update_bits(pwrkey->regmap, PON_CNTL_1, mask, val); mask 284 drivers/input/misc/pmic8xxx-pwrkey.c u8 mask, val; mask 313 drivers/input/misc/pmic8xxx-pwrkey.c mask = SLEEP_CTRL_SMPL_EN_RESET; mask 316 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; mask 317 drivers/input/misc/pmic8xxx-pwrkey.c return regmap_update_bits(regmap, PM8058_SLEEP_CTRL, mask, val); mask 323 drivers/input/misc/pmic8xxx-pwrkey.c u8 mask = SLEEP_CTRL_SMPL_EN_RESET; mask 328 drivers/input/misc/pmic8xxx-pwrkey.c val = mask; mask 329 drivers/input/misc/pmic8xxx-pwrkey.c return regmap_update_bits(regmap, PM8921_SLEEP_CTRL, mask, val); mask 1496 drivers/input/mouse/cyapa_gen5.c u16 mask, i; mask 1536 drivers/input/mouse/cyapa_gen5.c mask = 0; mask 1538 drivers/input/mouse/cyapa_gen5.c mask |= (0xff << (i * 8)); mask 1539 drivers/input/mouse/cyapa_gen5.c *interval_time = get_unaligned_le16(&resp_data[7]) & mask; mask 64 drivers/input/mouse/trackpoint.c static int trackpoint_toggle_bit(struct ps2dev *ps2dev, u8 loc, u8 mask) mask 66 drivers/input/mouse/trackpoint.c u8 param[3] = { TP_TOGGLE, loc, mask }; mask 76 drivers/input/mouse/trackpoint.c u8 loc, u8 mask, u8 value) mask 85 drivers/input/mouse/trackpoint.c if (((data & mask) == mask) != !!value) mask 86 drivers/input/mouse/trackpoint.c retval = trackpoint_toggle_bit(ps2dev, loc, mask); mask 97 drivers/input/mouse/trackpoint.c u8 mask; mask 163 drivers/input/mouse/trackpoint.c attr->command, attr->mask); mask 175 drivers/input/mouse/trackpoint.c .mask = _mask, \ mask 252 drivers/input/mouse/trackpoint.c if (!_attr->mask) \ mask 257 drivers/input/mouse/trackpoint.c _attr->command, _attr->mask, \ mask 762 drivers/input/mousedev.c __poll_t mask; mask 766 drivers/input/mousedev.c mask = mousedev->exist ? EPOLLOUT | EPOLLWRNORM : EPOLLHUP | EPOLLERR; mask 768 drivers/input/mousedev.c mask |= EPOLLIN | EPOLLRDNORM; mask 770 drivers/input/mousedev.c return mask; mask 367 drivers/input/rmi4/rmi_driver.c unsigned long *mask) mask 375 drivers/input/rmi4/rmi_driver.c data->current_irq_mask, mask, data->irq_count); mask 388 drivers/input/rmi4/rmi_driver.c bitmap_or(data->fn_irq_bits, data->fn_irq_bits, mask, data->irq_count); mask 396 drivers/input/rmi4/rmi_driver.c unsigned long *mask) mask 404 drivers/input/rmi4/rmi_driver.c data->fn_irq_bits, mask, data->irq_count); mask 406 drivers/input/rmi4/rmi_driver.c data->current_irq_mask, mask, data->irq_count); mask 189 drivers/input/serio/ambakmi.c .mask = 0x000fffff, mask 472 drivers/input/serio/hp_sdc.c int mask; mask 475 drivers/input/serio/hp_sdc.c mask = curr->seq[idx]; mask 478 drivers/input/serio/hp_sdc.c idx += !!(mask & 1); mask 479 drivers/input/serio/hp_sdc.c idx += !!(mask & 2); mask 480 drivers/input/serio/hp_sdc.c idx += !!(mask & 4); mask 481 drivers/input/serio/hp_sdc.c idx += !!(mask & 8); mask 486 drivers/input/serio/hp_sdc.c w7[0] = (mask & 1) ? curr->seq[++idx] : hp_sdc.r7[0]; mask 487 drivers/input/serio/hp_sdc.c w7[1] = (mask & 2) ? curr->seq[++idx] : hp_sdc.r7[1]; mask 488 drivers/input/serio/hp_sdc.c w7[2] = (mask & 4) ? curr->seq[++idx] : hp_sdc.r7[2]; mask 489 drivers/input/serio/hp_sdc.c w7[3] = (mask & 8) ? curr->seq[++idx] : hp_sdc.r7[3]; mask 206 drivers/input/serio/sa1111ps2.c unsigned int mask) mask 210 drivers/input/serio/sa1111ps2.c writel_relaxed(PS2CR_ENA | mask, ps2if->base + PS2CR); mask 243 drivers/input/serio/serio_raw.c __poll_t mask; mask 247 drivers/input/serio/serio_raw.c mask = serio_raw->dead ? EPOLLHUP | EPOLLERR : EPOLLOUT | EPOLLWRNORM; mask 249 drivers/input/serio/serio_raw.c mask |= EPOLLIN | EPOLLRDNORM; mask 251 drivers/input/serio/serio_raw.c return mask; mask 272 drivers/input/touchscreen/bcm_iproc_tsc.c u32 mask; mask 310 drivers/input/touchscreen/bcm_iproc_tsc.c mask = (TS_CONTROLLER_AVGDATA_MASK); mask 311 drivers/input/touchscreen/bcm_iproc_tsc.c mask |= (TS_CONTROLLER_PWR_LDO | /* PWR up LDO */ mask 315 drivers/input/touchscreen/bcm_iproc_tsc.c mask |= val; mask 316 drivers/input/touchscreen/bcm_iproc_tsc.c regmap_update_bits(priv->regmap, REGCTL2, mask, val); mask 54 drivers/input/touchscreen/egalax_ts_serial.c u8 mask; mask 57 drivers/input/touchscreen/egalax_ts_serial.c mask = 0xff >> (shift + 1); mask 59 drivers/input/touchscreen/egalax_ts_serial.c x = (((u16)(data[1] & mask) << 7) | (data[2] & 0x7f)) << shift; mask 60 drivers/input/touchscreen/egalax_ts_serial.c y = (((u16)(data[3] & mask) << 7) | (data[4] & 0x7f)) << shift; mask 73 drivers/input/touchscreen/mxs-lradc-ts.c u32 mask; mask 227 drivers/input/touchscreen/mxs-lradc-ts.c u32 reg, mask; mask 230 drivers/input/touchscreen/mxs-lradc-ts.c mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2); mask 231 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; mask 233 drivers/input/touchscreen/mxs-lradc-ts.c while (reg != mask) { mask 234 drivers/input/touchscreen/mxs-lradc-ts.c reg = readl(ts->base + LRADC_CTRL1) & mask; mask 282 drivers/input/touchscreen/mxs-lradc-ts.c writel(info[lradc->soc].mask, mask 304 drivers/input/touchscreen/mxs-lradc-ts.c writel(info[lradc->soc].mask, mask 330 drivers/input/touchscreen/mxs-lradc-ts.c writel(info[lradc->soc].mask, mask 356 drivers/input/touchscreen/mxs-lradc-ts.c writel(info[lradc->soc].mask, mask 544 drivers/input/touchscreen/mxs-lradc-ts.c writel(info[lradc->soc].mask, mask 39 drivers/input/touchscreen/tsc2007_iio.c int *val, int *val2, long mask) mask 49 drivers/input/touchscreen/tsc2007_iio.c if (mask != IIO_CHAN_INFO_RAW) mask 276 drivers/input/touchscreen/ucb1400_ts.c unsigned long mask, timeout; mask 278 drivers/input/touchscreen/ucb1400_ts.c mask = probe_irq_on(); mask 297 drivers/input/touchscreen/ucb1400_ts.c probe_irq_off(mask); mask 310 drivers/input/touchscreen/ucb1400_ts.c ucb->irq = probe_irq_off(mask); mask 94 drivers/input/touchscreen/wm9705.c static int mask; mask 95 drivers/input/touchscreen/wm9705.c module_param(mask, int, 0); mask 96 drivers/input/touchscreen/wm9705.c MODULE_PARM_DESC(mask, "Set adc mask function."); mask 172 drivers/input/touchscreen/wm9705.c dig2 |= ((mask & 0x3) << 4); mask 102 drivers/input/touchscreen/wm9712.c static int mask; mask 103 drivers/input/touchscreen/wm9712.c module_param(mask, int, 0); mask 104 drivers/input/touchscreen/wm9712.c MODULE_PARM_DESC(mask, "Set adc mask function."); mask 198 drivers/input/touchscreen/wm9712.c dig2 |= ((mask & 0x3) << 6); mask 199 drivers/input/touchscreen/wm9712.c if (mask) { mask 102 drivers/input/touchscreen/wm9713.c static int mask; mask 103 drivers/input/touchscreen/wm9713.c module_param(mask, int, 0); mask 104 drivers/input/touchscreen/wm9713.c MODULE_PARM_DESC(mask, "Set adc mask function."); mask 202 drivers/input/touchscreen/wm9713.c dig3 |= ((mask & 0x3) << 4); mask 2549 drivers/iommu/amd_iommu.c unsigned long mask, boundary_size; mask 2553 drivers/iommu/amd_iommu.c mask = dma_get_seg_boundary(dev); mask 2554 drivers/iommu/amd_iommu.c boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : mask 2773 drivers/iommu/amd_iommu.c static int amd_iommu_dma_supported(struct device *dev, u64 mask) mask 2775 drivers/iommu/amd_iommu.c if (!dma_direct_supported(dev, mask)) mask 4190 drivers/iommu/amd_iommu.c entry->mask = 0; mask 4195 drivers/iommu/amd_iommu.c entry->mask = 1; mask 4528 drivers/iommu/amd_iommu.c const struct cpumask *mask, bool force) mask 4540 drivers/iommu/amd_iommu.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 1983 drivers/iommu/amd_iommu_init.c const cpumask_t *mask) mask 1107 drivers/iommu/arm-smmu-v3.c unsigned long mask; mask 1119 drivers/iommu/arm-smmu-v3.c mask = GENMASK(limit - 1, sbidx); mask 1128 drivers/iommu/arm-smmu-v3.c atomic_long_xor(mask, ptr); mask 1132 drivers/iommu/arm-smmu-v3.c valid = (ULONG_MAX + !!Q_WRP(&llq, llq.prod)) & mask; mask 1133 drivers/iommu/arm-smmu-v3.c atomic_long_cond_read_relaxed(ptr, (VAL & mask) == valid); mask 88 drivers/iommu/arm-smmu.c u16 mask; mask 899 drivers/iommu/arm-smmu.c u32 reg = FIELD_PREP(SMR_ID, smr->id) | FIELD_PREP(SMR_MASK, smr->mask); mask 953 drivers/iommu/arm-smmu.c static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) mask 980 drivers/iommu/arm-smmu.c if ((mask & smrs[i].mask) == mask && mask 981 drivers/iommu/arm-smmu.c !((id ^ smrs[i].id) & ~smrs[i].mask)) mask 988 drivers/iommu/arm-smmu.c if (!((id ^ smrs[i].id) & ~(smrs[i].mask | mask))) mask 1020 drivers/iommu/arm-smmu.c u16 mask = FIELD_GET(SMR_MASK, fwspec->ids[i]); mask 1027 drivers/iommu/arm-smmu.c ret = arm_smmu_find_sme(smmu, sid, mask); mask 1034 drivers/iommu/arm-smmu.c smrs[idx].mask = mask; mask 1339 drivers/iommu/arm-smmu.c u16 mask = FIELD_GET(SMR_MASK, fwspec->ids[i]); mask 1346 drivers/iommu/arm-smmu.c if (mask & ~smmu->smr_mask_mask) { mask 1348 drivers/iommu/arm-smmu.c mask, smmu->smr_mask_mask); mask 1517 drivers/iommu/arm-smmu.c u32 mask, fwid = 0; mask 1524 drivers/iommu/arm-smmu.c else if (!of_property_read_u32(args->np, "stream-match-mask", &mask)) mask 1525 drivers/iommu/arm-smmu.c fwid |= FIELD_PREP(SMR_MASK, mask); mask 820 drivers/iommu/dma-iommu.c unsigned long mask = dma_get_seg_boundary(dev); mask 835 drivers/iommu/dma-iommu.c size_t pad_len = (mask - iova_len + 1) & mask; mask 1359 drivers/iommu/dmar.c u16 qdep, u64 addr, unsigned mask) mask 1363 drivers/iommu/dmar.c if (mask) { mask 1364 drivers/iommu/dmar.c addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; mask 39 drivers/iommu/hyperv-iommu.c const struct cpumask *mask, bool force) mask 47 drivers/iommu/hyperv-iommu.c if (!cpumask_subset(mask, &ioapic_max_cpumask)) mask 50 drivers/iommu/hyperv-iommu.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 668 drivers/iommu/intel-iommu.c int mask = 0xf; mask 678 drivers/iommu/intel-iommu.c mask &= cap_super_page_val(iommu->cap); mask 679 drivers/iommu/intel-iommu.c if (!mask) mask 685 drivers/iommu/intel-iommu.c return fls(mask); mask 1464 drivers/iommu/intel-iommu.c u64 addr, unsigned mask) mask 1481 drivers/iommu/intel-iommu.c qdep, addr, mask); mask 1491 drivers/iommu/intel-iommu.c unsigned int mask = ilog2(__roundup_pow_of_two(pages)); mask 1505 drivers/iommu/intel-iommu.c if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) mask 1509 drivers/iommu/intel-iommu.c iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, mask 1517 drivers/iommu/intel-iommu.c iommu_flush_dev_iotlb(domain, addr, mask); mask 285 drivers/iommu/intel-pasid.c static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits) mask 290 drivers/iommu/intel-pasid.c WRITE_ONCE(*ptr, (old & ~mask) | bits); mask 114 drivers/iommu/intel-svm.c int mask = ilog2(__roundup_pow_of_two(pages)); mask 122 drivers/iommu/intel-svm.c QI_EIOTLB_AM(mask); mask 141 drivers/iommu/intel-svm.c unsigned long mask = __rounddown_pow_of_two(address ^ last); mask 143 drivers/iommu/intel-svm.c desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) | mask 144 drivers/iommu/intel-svm.c (mask - 1)) | QI_DEV_EIOTLB_SIZE; mask 108 drivers/iommu/intel_irq_remapping.c unsigned int mask = 0; mask 117 drivers/iommu/intel_irq_remapping.c mask = ilog2(count); mask 120 drivers/iommu/intel_irq_remapping.c if (mask > ecap_max_handle_mask(iommu->ecap)) { mask 122 drivers/iommu/intel_irq_remapping.c " mask value %Lx\n", mask, mask 129 drivers/iommu/intel_irq_remapping.c INTR_REMAP_TABLE_ENTRIES, mask); mask 136 drivers/iommu/intel_irq_remapping.c irq_iommu->irte_mask = mask; mask 144 drivers/iommu/intel_irq_remapping.c static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) mask 148 drivers/iommu/intel_irq_remapping.c desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) mask 1185 drivers/iommu/intel_irq_remapping.c intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, mask 1192 drivers/iommu/intel_irq_remapping.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 1292 drivers/iommu/intel_irq_remapping.c entry->mask = 0; /* enable IRQ */ mask 1296 drivers/iommu/intel_irq_remapping.c entry->mask = 1; /* Mask level triggered irqs. */ mask 205 drivers/iommu/io-pgtable-arm-v7s.c arm_v7s_iopte mask; mask 209 drivers/iommu/io-pgtable-arm-v7s.c mask = ARM_V7S_TABLE_MASK; mask 211 drivers/iommu/io-pgtable-arm-v7s.c mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES; mask 213 drivers/iommu/io-pgtable-arm-v7s.c mask = ARM_V7S_LVL_MASK(lvl); mask 215 drivers/iommu/io-pgtable-arm-v7s.c paddr = pte & mask; mask 734 drivers/iommu/io-pgtable-arm-v7s.c u32 mask; mask 745 drivers/iommu/io-pgtable-arm-v7s.c mask = ARM_V7S_LVL_MASK(lvl); mask 747 drivers/iommu/io-pgtable-arm-v7s.c mask *= ARM_V7S_CONT_PAGES; mask 748 drivers/iommu/io-pgtable-arm-v7s.c return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask); mask 33 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask)) mask 35 drivers/iommu/msm_iommu_hw-8xxx.h #define SET_FIELD(addr, mask, shift, v) \ mask 38 drivers/iommu/msm_iommu_hw-8xxx.h writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\ mask 138 drivers/iommu/omap-iommu.c u32 val, mask; mask 143 drivers/iommu/omap-iommu.c mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT)); mask 144 drivers/iommu/omap-iommu.c val = enable ? mask : 0; mask 145 drivers/iommu/omap-iommu.c regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val); mask 226 drivers/iommu/omap-iommu.c u32 mask = get_cam_va_mask(cr->cam & page_size); mask 228 drivers/iommu/omap-iommu.c return cr->cam & mask; mask 66 drivers/iommu/omap-iopgtable.h static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask) mask 68 drivers/iommu/omap-iopgtable.h return (d & mask) | (va & (~mask)); mask 72 drivers/ipack/carriers/tpci200.c __le16 __iomem *addr, u16 mask) mask 76 drivers/ipack/carriers/tpci200.c iowrite16(ioread16(addr) & (~mask), addr); mask 81 drivers/ipack/carriers/tpci200.c __le16 __iomem *addr, u16 mask) mask 85 drivers/ipack/carriers/tpci200.c iowrite16(ioread16(addr) | mask, addr); mask 404 drivers/ipack/carriers/tpci200.c u16 mask; mask 410 drivers/ipack/carriers/tpci200.c mask = tpci200_status_error[dev->slot]; mask 411 drivers/ipack/carriers/tpci200.c return (ioread16(addr) & mask) ? 1 : 0; mask 418 drivers/ipack/carriers/tpci200.c u16 mask; mask 424 drivers/ipack/carriers/tpci200.c mask = tpci200_status_timeout[dev->slot]; mask 426 drivers/ipack/carriers/tpci200.c return (ioread16(addr) & mask) ? 1 : 0; mask 433 drivers/ipack/carriers/tpci200.c u16 mask; mask 439 drivers/ipack/carriers/tpci200.c mask = tpci200_status_timeout[dev->slot]; mask 441 drivers/ipack/carriers/tpci200.c iowrite16(mask, addr); mask 53 drivers/irqchip/exynos-combiner.c u32 mask = 1 << (data->hwirq % 32); mask 55 drivers/irqchip/exynos-combiner.c writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); mask 60 drivers/irqchip/exynos-combiner.c u32 mask = 1 << (data->hwirq % 32); mask 62 drivers/irqchip/exynos-combiner.c writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET); mask 167 drivers/irqchip/irq-al-fic.c gc->chip_types->regs.mask = AL_FIC_MASK; mask 218 drivers/irqchip/irq-armada-370-xp.c const struct cpumask *mask, bool force) mask 320 drivers/irqchip/irq-armada-370-xp.c unsigned long reg, mask; mask 325 drivers/irqchip/irq-armada-370-xp.c mask = 1UL << cpu_logical_map(cpu); mask 329 drivers/irqchip/irq-armada-370-xp.c reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask; mask 407 drivers/irqchip/irq-armada-370-xp.c static void armada_mpic_send_doorbell(const struct cpumask *mask, mask 414 drivers/irqchip/irq-armada-370-xp.c for_each_cpu(cpu, mask) mask 62 drivers/irqchip/irq-atmel-aic-common.c if (!(d->mask & aic->ext_irqs)) mask 68 drivers/irqchip/irq-atmel-aic-common.c if (!(d->mask & aic->ext_irqs)) mask 83 drivers/irqchip/irq-atmel-aic.c irq_reg_writel(gc, d->mask, AT91_AIC_ISCR); mask 99 drivers/irqchip/irq-atmel-aic5.c gc->mask_cache &= ~d->mask; mask 116 drivers/irqchip/irq-atmel-aic5.c gc->mask_cache |= d->mask; mask 162 drivers/irqchip/irq-atmel-aic5.c u32 mask; mask 172 drivers/irqchip/irq-atmel-aic5.c mask = 1 << i; mask 173 drivers/irqchip/irq-atmel-aic5.c if ((mask & gc->mask_cache) == (mask & gc->wake_active)) mask 177 drivers/irqchip/irq-atmel-aic5.c if (mask & gc->wake_active) mask 192 drivers/irqchip/irq-atmel-aic5.c u32 mask; mask 206 drivers/irqchip/irq-atmel-aic5.c mask = 1 << i; mask 209 drivers/irqchip/irq-atmel-aic5.c ((mask & gc->mask_cache) == (mask & gc->wake_active))) mask 213 drivers/irqchip/irq-atmel-aic5.c if (mask & gc->mask_cache) mask 148 drivers/irqchip/irq-bcm2836.c static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask, mask 160 drivers/irqchip/irq-bcm2836.c for_each_cpu(cpu, mask) { mask 156 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); mask 159 drivers/irqchip/irq-bcm6345-l1.c intc->cpus[cpu_idx]->enable_cache[word] |= mask; mask 168 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); mask 171 drivers/irqchip/irq-bcm6345-l1.c intc->cpus[cpu_idx]->enable_cache[word] &= ~mask; mask 202 drivers/irqchip/irq-bcm6345-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); mask 220 drivers/irqchip/irq-bcm6345-l1.c enabled = intc->cpus[old_cpu]->enable_cache[word] & mask; mask 152 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); mask 154 drivers/irqchip/irq-bcm7038-l1.c intc->cpus[cpu_idx]->mask_cache[word] &= ~mask; mask 155 drivers/irqchip/irq-bcm7038-l1.c l1_writel(mask, intc->cpus[cpu_idx]->map_base + mask 163 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(d->hwirq % IRQS_PER_WORD); mask 165 drivers/irqchip/irq-bcm7038-l1.c intc->cpus[cpu_idx]->mask_cache[word] |= mask; mask 166 drivers/irqchip/irq-bcm7038-l1.c l1_writel(mask, intc->cpus[cpu_idx]->map_base + mask 198 drivers/irqchip/irq-bcm7038-l1.c u32 mask = BIT(hw % IRQS_PER_WORD); mask 205 drivers/irqchip/irq-bcm7038-l1.c mask); mask 220 drivers/irqchip/irq-bcm7038-l1.c struct cpumask *mask = irq_data_get_affinity_mask(d); mask 225 drivers/irqchip/irq-bcm7038-l1.c if (!cpumask_test_cpu(cpu, mask)) mask 228 drivers/irqchip/irq-bcm7038-l1.c if (cpumask_weight(mask) > 1) { mask 233 drivers/irqchip/irq-bcm7038-l1.c cpumask_copy(&new_affinity, mask); mask 94 drivers/irqchip/irq-bcm7120-l2.c ct->regs.mask); mask 104 drivers/irqchip/irq-bcm7120-l2.c irq_reg_writel(gc, gc->mask_cache, ct->regs.mask); mask 289 drivers/irqchip/irq-bcm7120-l2.c ct->regs.mask = data->en_offset[idx]; mask 306 drivers/irqchip/irq-bcm7120-l2.c gc->mask_cache = irq_reg_readl(gc, ct->regs.mask); mask 82 drivers/irqchip/irq-brcmstb-l2.c u32 mask = d->mask; mask 85 drivers/irqchip/irq-brcmstb-l2.c irq_reg_writel(gc, mask, ct->regs.disable); mask 86 drivers/irqchip/irq-brcmstb-l2.c *ct->mask_cache &= ~mask; mask 87 drivers/irqchip/irq-brcmstb-l2.c irq_reg_writel(gc, mask, ct->regs.ack); mask 128 drivers/irqchip/irq-brcmstb-l2.c b->saved_mask = irq_reg_readl(gc, ct->regs.mask); mask 242 drivers/irqchip/irq-brcmstb-l2.c ct->regs.mask = init_params->cpu_mask_status; mask 50 drivers/irqchip/irq-csky-apb-intc.c unsigned long ifr = ct->regs.mask - 8; mask 51 drivers/irqchip/irq-csky-apb-intc.c u32 mask = d->mask; mask 54 drivers/irqchip/irq-csky-apb-intc.c *ct->mask_cache |= mask; mask 55 drivers/irqchip/irq-csky-apb-intc.c irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); mask 56 drivers/irqchip/irq-csky-apb-intc.c irq_reg_writel(gc, irq_reg_readl(gc, ifr) & ~mask, ifr); mask 67 drivers/irqchip/irq-csky-apb-intc.c gc->chip_types[0].regs.mask = mask_reg; mask 213 drivers/irqchip/irq-csky-mpintc.c static void csky_mpintc_send_ipi(const struct cpumask *mask) mask 221 drivers/irqchip/irq-csky-mpintc.c writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ, mask 59 drivers/irqchip/irq-davinci-aintc.c ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0; mask 76 drivers/irqchip/irq-davinci-cp-intc.c unsigned int reg, mask, polarity, type; mask 79 drivers/irqchip/irq-davinci-cp-intc.c mask = BIT_MASK(d->hwirq); mask 85 drivers/irqchip/irq-davinci-cp-intc.c polarity |= mask; mask 86 drivers/irqchip/irq-davinci-cp-intc.c type |= mask; mask 89 drivers/irqchip/irq-davinci-cp-intc.c polarity &= ~mask; mask 90 drivers/irqchip/irq-davinci-cp-intc.c type |= mask; mask 93 drivers/irqchip/irq-davinci-cp-intc.c polarity |= mask; mask 94 drivers/irqchip/irq-davinci-cp-intc.c type &= ~mask; mask 97 drivers/irqchip/irq-davinci-cp-intc.c polarity &= ~mask; mask 98 drivers/irqchip/irq-davinci-cp-intc.c type &= ~mask; mask 65 drivers/irqchip/irq-digicolor.c gc->chip_types[0].regs.mask = en_reg; mask 61 drivers/irqchip/irq-dw-apb-ictl.c writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); mask 142 drivers/irqchip/irq-dw-apb-ictl.c gc->chip_types[0].regs.mask = APB_INT_MASK_L; mask 57 drivers/irqchip/irq-ftintc010.c unsigned int mask; mask 59 drivers/irqchip/irq-ftintc010.c mask = readl(FT010_IRQ_MASK(f->base)); mask 60 drivers/irqchip/irq-ftintc010.c mask &= ~BIT(irqd_to_hwirq(d)); mask 61 drivers/irqchip/irq-ftintc010.c writel(mask, FT010_IRQ_MASK(f->base)); mask 67 drivers/irqchip/irq-ftintc010.c unsigned int mask; mask 69 drivers/irqchip/irq-ftintc010.c mask = readl(FT010_IRQ_MASK(f->base)); mask 70 drivers/irqchip/irq-ftintc010.c mask |= BIT(irqd_to_hwirq(d)); mask 71 drivers/irqchip/irq-ftintc010.c writel(mask, FT010_IRQ_MASK(f->base)); mask 46 drivers/irqchip/irq-gic-common.c if (quirks->iidr != (quirks->mask & iidr)) mask 18 drivers/irqchip/irq-gic-common.h u32 mask; mask 324 drivers/irqchip/irq-gic-v3-its.c u64 mask = GENMASK_ULL(h, l); mask 325 drivers/irqchip/irq-gic-v3-its.c *raw_cmd &= ~mask; mask 326 drivers/irqchip/irq-gic-v3-its.c *raw_cmd |= (val << l) & mask; mask 3306 drivers/irqchip/irq-gic-v3-its.c .mask = 0xffff0fff, mask 3314 drivers/irqchip/irq-gic-v3-its.c .mask = 0xffff0fff, mask 3322 drivers/irqchip/irq-gic-v3-its.c .mask = 0xffffffff, mask 3335 drivers/irqchip/irq-gic-v3-its.c .mask = 0xffffffff, mask 3343 drivers/irqchip/irq-gic-v3-its.c .mask = 0xffffffff, mask 295 drivers/irqchip/irq-gic-v3.c u32 index, mask; mask 298 drivers/irqchip/irq-gic-v3.c mask = 1 << (index % 32); mask 305 drivers/irqchip/irq-gic-v3.c return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask); mask 312 drivers/irqchip/irq-gic-v3.c u32 index, mask; mask 315 drivers/irqchip/irq-gic-v3.c mask = 1 << (index % 32); mask 325 drivers/irqchip/irq-gic-v3.c writel_relaxed(mask, base + offset + (index / 32) * 4); mask 1049 drivers/irqchip/irq-gic-v3.c static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, mask 1059 drivers/irqchip/irq-gic-v3.c next_cpu = cpumask_next(cpu, mask); mask 1095 drivers/irqchip/irq-gic-v3.c static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) mask 1108 drivers/irqchip/irq-gic-v3.c for_each_cpu(cpu, mask) { mask 1112 drivers/irqchip/irq-gic-v3.c tlist = gic_compute_target_list(&cpu, mask, cluster_id); mask 1473 drivers/irqchip/irq-gic-v3.c .mask = 0xffffffff, mask 1479 drivers/irqchip/irq-gic-v3.c .mask = 0xffffffff, mask 1665 drivers/irqchip/irq-gic-v3.c cpumask_set_cpu(cpu, &part->mask); mask 192 drivers/irqchip/irq-gic.c u32 mask = 1 << (gic_irq(d) % 32); mask 193 drivers/irqchip/irq-gic.c writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); mask 198 drivers/irqchip/irq-gic.c u32 mask = 1 << (gic_irq(d) % 32); mask 199 drivers/irqchip/irq-gic.c return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); mask 334 drivers/irqchip/irq-gic.c u32 val, mask, bit; mask 346 drivers/irqchip/irq-gic.c mask = 0xff << shift; mask 348 drivers/irqchip/irq-gic.c val = readl_relaxed(reg) & ~mask; mask 445 drivers/irqchip/irq-gic.c u32 mask, i; mask 447 drivers/irqchip/irq-gic.c for (i = mask = 0; i < 32; i += 4) { mask 448 drivers/irqchip/irq-gic.c mask = readl_relaxed(base + GIC_DIST_TARGET + i); mask 449 drivers/irqchip/irq-gic.c mask |= mask >> 16; mask 450 drivers/irqchip/irq-gic.c mask |= mask >> 8; mask 451 drivers/irqchip/irq-gic.c if (mask) mask 455 drivers/irqchip/irq-gic.c if (!mask && num_possible_cpus() > 1) mask 458 drivers/irqchip/irq-gic.c return mask; mask 806 drivers/irqchip/irq-gic.c static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) mask 821 drivers/irqchip/irq-gic.c for_each_cpu(cpu, mask) mask 93 drivers/irqchip/irq-hip04.c u32 mask = 1 << (hip04_irq(d) % 32); mask 96 drivers/irqchip/irq-hip04.c writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + mask 103 drivers/irqchip/irq-hip04.c u32 mask = 1 << (hip04_irq(d) % 32); mask 106 drivers/irqchip/irq-hip04.c writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + mask 152 drivers/irqchip/irq-hip04.c u32 val, mask, bit; mask 164 drivers/irqchip/irq-hip04.c mask = 0xffff << shift; mask 166 drivers/irqchip/irq-hip04.c val = readl_relaxed(reg) & ~mask; mask 217 drivers/irqchip/irq-hip04.c u32 mask, i; mask 219 drivers/irqchip/irq-hip04.c for (i = mask = 0; i < 32; i += 2) { mask 220 drivers/irqchip/irq-hip04.c mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2); mask 221 drivers/irqchip/irq-hip04.c mask |= mask >> 16; mask 222 drivers/irqchip/irq-hip04.c if (mask) mask 226 drivers/irqchip/irq-hip04.c if (!mask) mask 229 drivers/irqchip/irq-hip04.c return mask; mask 283 drivers/irqchip/irq-hip04.c static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq) mask 291 drivers/irqchip/irq-hip04.c for_each_cpu(cpu, mask) mask 70 drivers/irqchip/irq-i8259.c unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; mask 73 drivers/irqchip/irq-i8259.c mask = 1 << irq; mask 75 drivers/irqchip/irq-i8259.c cached_irq_mask |= mask; mask 85 drivers/irqchip/irq-i8259.c unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; mask 88 drivers/irqchip/irq-i8259.c mask = ~(1 << irq); mask 90 drivers/irqchip/irq-i8259.c cached_irq_mask &= mask; mask 136 drivers/irqchip/irq-imgpdc.c priv->irq_route &= ~data->mask; mask 146 drivers/irqchip/irq-imgpdc.c priv->irq_route |= data->mask; mask 201 drivers/irqchip/irq-imgpdc.c unsigned int mask = (1 << 16) << hw; mask 206 drivers/irqchip/irq-imgpdc.c priv->irq_route |= mask; mask 208 drivers/irqchip/irq-imgpdc.c priv->irq_route &= ~mask; mask 409 drivers/irqchip/irq-imgpdc.c gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE; mask 424 drivers/irqchip/irq-imgpdc.c gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE; mask 437 drivers/irqchip/irq-imgpdc.c gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE; mask 78 drivers/irqchip/irq-imx-gpcv2.c u32 mask, val; mask 81 drivers/irqchip/irq-imx-gpcv2.c mask = BIT(d->hwirq % 32); mask 84 drivers/irqchip/irq-imx-gpcv2.c cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); mask 51 drivers/irqchip/irq-ingenic-tcu.c u32 mask = d->mask; mask 54 drivers/irqchip/irq-ingenic-tcu.c regmap_write(map, ct->regs.ack, mask); mask 55 drivers/irqchip/irq-ingenic-tcu.c regmap_write(map, ct->regs.enable, mask); mask 56 drivers/irqchip/irq-ingenic-tcu.c *ct->mask_cache |= mask; mask 65 drivers/irqchip/irq-ingenic-tcu.c u32 mask = d->mask; mask 68 drivers/irqchip/irq-ingenic-tcu.c regmap_write(map, ct->regs.disable, mask); mask 69 drivers/irqchip/irq-ingenic-tcu.c *ct->mask_cache &= ~mask; mask 78 drivers/irqchip/irq-ingenic-tcu.c u32 mask = d->mask; mask 81 drivers/irqchip/irq-ingenic-tcu.c regmap_write(map, ct->regs.ack, mask); mask 82 drivers/irqchip/irq-ingenic-tcu.c regmap_write(map, ct->regs.disable, mask); mask 53 drivers/irqchip/irq-ingenic.c static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) mask 57 drivers/irqchip/irq-ingenic.c writel(mask, gc->reg_base + regs->enable); mask 58 drivers/irqchip/irq-ingenic.c writel(~mask, gc->reg_base + regs->disable); mask 37 drivers/irqchip/irq-keystone.c u32 mask; mask 70 drivers/irqchip/irq-keystone.c kirq->mask |= BIT(d->hwirq); mask 71 drivers/irqchip/irq-keystone.c dev_dbg(kirq->dev, "mask %lu [%x]\n", d->hwirq, kirq->mask); mask 78 drivers/irqchip/irq-keystone.c kirq->mask &= ~BIT(d->hwirq); mask 79 drivers/irqchip/irq-keystone.c dev_dbg(kirq->dev, "unmask %lu [%x]\n", d->hwirq, kirq->mask); mask 99 drivers/irqchip/irq-keystone.c dev_dbg(kirq->dev, "pending 0x%lx, mask 0x%x\n", pending, kirq->mask); mask 101 drivers/irqchip/irq-keystone.c pending = (pending >> BIT_OFS) & ~kirq->mask; mask 171 drivers/irqchip/irq-keystone.c kirq->mask = ~0x0; mask 48 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); mask 50 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask; mask 57 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); mask 59 drivers/irqchip/irq-lpc32xx.c val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask; mask 66 drivers/irqchip/irq-lpc32xx.c u32 mask = BIT(d->hwirq); mask 68 drivers/irqchip/irq-lpc32xx.c lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask); mask 74 drivers/irqchip/irq-lpc32xx.c u32 val, mask = BIT(d->hwirq); mask 103 drivers/irqchip/irq-lpc32xx.c val |= mask; mask 105 drivers/irqchip/irq-lpc32xx.c val &= ~mask; mask 110 drivers/irqchip/irq-lpc32xx.c val |= mask; mask 113 drivers/irqchip/irq-lpc32xx.c val &= ~mask; mask 94 drivers/irqchip/irq-ls-scfg-msi.c const struct cpumask *mask; mask 96 drivers/irqchip/irq-ls-scfg-msi.c mask = irq_data_get_effective_affinity_mask(data); mask 97 drivers/irqchip/irq-ls-scfg-msi.c msg->data |= cpumask_first(mask); mask 104 drivers/irqchip/irq-ls-scfg-msi.c const struct cpumask *mask, bool force) mask 113 drivers/irqchip/irq-ls-scfg-msi.c cpu = cpumask_any_and(mask, cpu_online_mask); mask 115 drivers/irqchip/irq-ls-scfg-msi.c cpu = cpumask_first(mask); mask 62 drivers/irqchip/irq-ls1x.c u32 mask, bool set) mask 65 drivers/irqchip/irq-ls1x.c writel(readl(gc->reg_base + offset) | mask, mask 68 drivers/irqchip/irq-ls1x.c writel(readl(gc->reg_base + offset) & ~mask, mask 75 drivers/irqchip/irq-ls1x.c u32 mask = data->mask; mask 79 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false); mask 80 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true); mask 83 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false); mask 84 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false); mask 87 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true); mask 88 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true); mask 91 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true); mask 92 drivers/irqchip/irq-ls1x.c ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false); mask 161 drivers/irqchip/irq-ls1x.c ct[0].regs.mask = LS_REG_INTC_EN; mask 170 drivers/irqchip/irq-ls1x.c ct[1].regs.mask = LS_REG_INTC_EN; mask 27 drivers/irqchip/irq-madera.c .mask = MADERA_ ## _irq ## _EINT1 \ mask 80 drivers/irqchip/irq-mbigen.c u32 *mask, u32 *addr) mask 88 drivers/irqchip/irq-mbigen.c *mask = 1 << (irq_ofst % 32); mask 96 drivers/irqchip/irq-mbigen.c u32 *mask, u32 *addr) mask 100 drivers/irqchip/irq-mbigen.c *mask = 1 << (hwirq % 32); mask 107 drivers/irqchip/irq-mbigen.c u32 mask, addr; mask 109 drivers/irqchip/irq-mbigen.c get_mbigen_clear_reg(data->hwirq, &mask, &addr); mask 111 drivers/irqchip/irq-mbigen.c writel_relaxed(mask, base + addr); mask 119 drivers/irqchip/irq-mbigen.c u32 mask, addr, val; mask 124 drivers/irqchip/irq-mbigen.c get_mbigen_type_reg(data->hwirq, &mask, &addr); mask 129 drivers/irqchip/irq-mbigen.c val |= mask; mask 131 drivers/irqchip/irq-mbigen.c val &= ~mask; mask 93 drivers/irqchip/irq-meson-gpio.c unsigned int reg, u32 mask, u32 val) mask 98 drivers/irqchip/irq-meson-gpio.c tmp &= ~mask; mask 63 drivers/irqchip/irq-mips-gic.c bool mask; mask 355 drivers/irqchip/irq-mips-gic.c cd->mask = false; mask 373 drivers/irqchip/irq-mips-gic.c cd->mask = true; mask 392 drivers/irqchip/irq-mips-gic.c if (cd->mask) mask 153 drivers/irqchip/irq-mmp.c unsigned long mask, status, n; mask 169 drivers/irqchip/irq-mmp.c mask = readl_relaxed(data->reg_mask); mask 171 drivers/irqchip/irq-mmp.c status = readl_relaxed(data->reg_status) & ~mask; mask 28 drivers/irqchip/irq-mscc-ocelot.c unsigned int mask = data->mask; mask 34 drivers/irqchip/irq-mscc-ocelot.c if (!(val & mask)) mask 35 drivers/irqchip/irq-mscc-ocelot.c irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY); mask 37 drivers/irqchip/irq-mscc-ocelot.c *ct->mask_cache &= ~mask; mask 38 drivers/irqchip/irq-mscc-ocelot.c irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET); mask 96 drivers/irqchip/irq-mscc-ocelot.c gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR; mask 44 drivers/irqchip/irq-mtk-cirq.c u32 mask = 1 << (cirq_num % 32); mask 46 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); mask 163 drivers/irqchip/irq-mtk-cirq.c u32 value, mask; mask 203 drivers/irqchip/irq-mtk-cirq.c mask = 1 << (i % 32); mask 204 drivers/irqchip/irq-mtk-cirq.c writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); mask 97 drivers/irqchip/irq-ompic.c static void ompic_raise_softirq(const struct cpumask *mask, mask 103 drivers/irqchip/irq-ompic.c for_each_cpu(dst_cpu, mask) { mask 90 drivers/irqchip/irq-orion.c gc->chip_types[0].regs.mask = ORION_IRQ_MASK; mask 190 drivers/irqchip/irq-orion.c gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK; mask 28 drivers/irqchip/irq-partition-percpu.c return cpumask_test_cpu(cpu, &part->parts[hwirq].mask); mask 157 drivers/irqchip/irq-partition-percpu.c irq_set_percpu_devid_partition(virq, &part->parts[hwirq].mask); mask 132 drivers/irqchip/irq-pic32-evic.c u32 reg, mask; mask 150 drivers/irqchip/irq-pic32-evic.c IRQ_REG_MASK(hw, reg, mask); mask 156 drivers/irqchip/irq-pic32-evic.c writel(mask, evic_base + iecclr); mask 157 drivers/irqchip/irq-pic32-evic.c writel(mask, evic_base + ifsclr); mask 275 drivers/irqchip/irq-pic32-evic.c gc->chip_types[0].regs.mask = iec; mask 286 drivers/irqchip/irq-pic32-evic.c gc->chip_types[1].regs.mask = iec; mask 83 drivers/irqchip/irq-s3c24xx.c unsigned long mask; mask 86 drivers/irqchip/irq-s3c24xx.c mask = readl_relaxed(intc->reg_mask); mask 87 drivers/irqchip/irq-s3c24xx.c mask |= (1UL << irq_data->offset); mask 88 drivers/irqchip/irq-s3c24xx.c writel_relaxed(mask, intc->reg_mask); mask 97 drivers/irqchip/irq-s3c24xx.c if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { mask 110 drivers/irqchip/irq-s3c24xx.c unsigned long mask; mask 113 drivers/irqchip/irq-s3c24xx.c mask = readl_relaxed(intc->reg_mask); mask 114 drivers/irqchip/irq-s3c24xx.c mask &= ~(1UL << irq_data->offset); mask 115 drivers/irqchip/irq-s3c24xx.c writel_relaxed(mask, intc->reg_mask); mask 133 drivers/irqchip/irq-sa11x0.c uint32_t icip, icmr, mask; mask 138 drivers/irqchip/irq-sa11x0.c mask = icip & icmr; mask 140 drivers/irqchip/irq-sa11x0.c if (mask == 0) mask 144 drivers/irqchip/irq-sa11x0.c ffs(mask) - 1, regs); mask 86 drivers/irqchip/irq-sifive-plic.c static inline void plic_irq_toggle(const struct cpumask *mask, mask 92 drivers/irqchip/irq-sifive-plic.c for_each_cpu(cpu, mask) { mask 54 drivers/irqchip/irq-sirfsoc.c ct->regs.mask = SIRFSOC_INT_RISC_MASK0; mask 258 drivers/irqchip/irq-stm32-exti.c u32 mask = BIT(d->hwirq % IRQS_PER_BANK); mask 262 drivers/irqchip/irq-stm32-exti.c *rtsr |= mask; mask 263 drivers/irqchip/irq-stm32-exti.c *ftsr &= ~mask; mask 266 drivers/irqchip/irq-stm32-exti.c *rtsr &= ~mask; mask 267 drivers/irqchip/irq-stm32-exti.c *ftsr |= mask; mask 270 drivers/irqchip/irq-stm32-exti.c *rtsr |= mask; mask 271 drivers/irqchip/irq-stm32-exti.c *ftsr |= mask; mask 427 drivers/irqchip/irq-stm32-exti.c irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); mask 429 drivers/irqchip/irq-stm32-exti.c irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); mask 538 drivers/irqchip/irq-stm32-exti.c u32 mask = BIT(d->hwirq % IRQS_PER_BANK); mask 543 drivers/irqchip/irq-stm32-exti.c chip_data->wake_active |= mask; mask 545 drivers/irqchip/irq-stm32-exti.c chip_data->wake_active &= ~mask; mask 764 drivers/irqchip/irq-stm32-exti.c gc->chip_types->regs.mask = stm32_bank->imr_ofst; mask 205 drivers/irqchip/irq-sunxi-nmi.c gc->chip_types[0].regs.mask = reg_offs->enable; mask 215 drivers/irqchip/irq-sunxi-nmi.c gc->chip_types[1].regs.mask = reg_offs->enable; mask 96 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask); mask 97 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask); mask 101 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask); mask 102 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask); mask 106 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_RISE_CLR, d->mask); mask 107 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_FALL_CLR, d->mask); mask 111 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_RISE_SET, d->mask); mask 112 drivers/irqchip/irq-tango.c intc_writel(chip, regs->type + EDGE_CFG_FALL_SET, d->mask); mask 47 drivers/irqchip/irq-tb10x.c im = data->mask; mask 150 drivers/irqchip/irq-tb10x.c gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE; mask 159 drivers/irqchip/irq-tb10x.c gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE; mask 85 drivers/irqchip/irq-tegra.c u32 mask; mask 87 drivers/irqchip/irq-tegra.c mask = BIT(d->hwirq % 32); mask 88 drivers/irqchip/irq-tegra.c writel_relaxed(mask, base + reg); mask 119 drivers/irqchip/irq-tegra.c u32 index, mask; mask 122 drivers/irqchip/irq-tegra.c mask = BIT(irq % 32); mask 124 drivers/irqchip/irq-tegra.c lic->ictlr_wake_mask[index] |= mask; mask 126 drivers/irqchip/irq-tegra.c lic->ictlr_wake_mask[index] &= ~mask; mask 36 drivers/irqchip/irq-ts4800.c u16 mask = 1 << d->hwirq; mask 38 drivers/irqchip/irq-ts4800.c writew(reg | mask, data->base + IRQ_MASK); mask 45 drivers/irqchip/irq-ts4800.c u16 mask = 1 << d->hwirq; mask 47 drivers/irqchip/irq-ts4800.c writew(reg & ~mask, data->base + IRQ_MASK); mask 32 drivers/irqchip/irq-uniphier-aidet.c unsigned int reg, u32 mask, u32 val) mask 39 drivers/irqchip/irq-uniphier-aidet.c tmp &= ~mask; mask 40 drivers/irqchip/irq-uniphier-aidet.c tmp |= mask & val; mask 49 drivers/irqchip/irq-uniphier-aidet.c u32 mask; mask 52 drivers/irqchip/irq-uniphier-aidet.c mask = BIT(index % 32); mask 54 drivers/irqchip/irq-uniphier-aidet.c uniphier_aidet_reg_update(priv, reg, mask, val ? mask : 0); mask 57 drivers/irqchip/irq-versatile-fpga.c u32 mask = 1 << d->hwirq; mask 59 drivers/irqchip/irq-versatile-fpga.c writel(mask, f->base + IRQ_ENABLE_CLEAR); mask 65 drivers/irqchip/irq-versatile-fpga.c u32 mask = 1 << d->hwirq; mask 67 drivers/irqchip/irq-versatile-fpga.c writel(mask, f->base + IRQ_ENABLE_SET); mask 63 drivers/irqchip/irq-xilinx-intc.c unsigned long mask = 1 << d->hwirq; mask 72 drivers/irqchip/irq-xilinx-intc.c xintc_write(IAR, mask); mask 74 drivers/irqchip/irq-xilinx-intc.c xintc_write(SIE, mask); mask 91 drivers/irqchip/irq-xilinx-intc.c unsigned long mask = 1 << d->hwirq; mask 94 drivers/irqchip/irq-xilinx-intc.c xintc_write(CIE, mask); mask 95 drivers/irqchip/irq-xilinx-intc.c xintc_write(IAR, mask); mask 71 drivers/irqchip/irq-xtensa-mx.c unsigned int mask = 1u << d->hwirq; mask 73 drivers/irqchip/irq-xtensa-mx.c if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | mask 82 drivers/irqchip/irq-xtensa-mx.c mask = __this_cpu_read(cached_irq_mask) & ~mask; mask 83 drivers/irqchip/irq-xtensa-mx.c __this_cpu_write(cached_irq_mask, mask); mask 84 drivers/irqchip/irq-xtensa-mx.c xtensa_set_sr(mask, intenable); mask 89 drivers/irqchip/irq-xtensa-mx.c unsigned int mask = 1u << d->hwirq; mask 91 drivers/irqchip/irq-xtensa-mx.c if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | mask 100 drivers/irqchip/irq-xtensa-mx.c mask |= __this_cpu_read(cached_irq_mask); mask 101 drivers/irqchip/irq-xtensa-mx.c __this_cpu_write(cached_irq_mask, mask); mask 102 drivers/irqchip/irq-xtensa-mx.c xtensa_set_sr(mask, intenable); mask 122 drivers/irqchip/irq-xtensa-mx.c unsigned int mask = 1u << d->hwirq; mask 124 drivers/irqchip/irq-xtensa-mx.c if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE)) mask 126 drivers/irqchip/irq-xtensa-mx.c xtensa_set_sr(mask, intset); mask 134 drivers/irqchip/irq-xtensa-mx.c unsigned mask = 1u << cpu; mask 136 drivers/irqchip/irq-xtensa-mx.c set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE)); mask 73 drivers/irqchip/irq-xtensa-pic.c unsigned int mask = 1u << d->hwirq; mask 75 drivers/irqchip/irq-xtensa-pic.c if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE)) mask 77 drivers/irqchip/irq-xtensa-pic.c xtensa_set_sr(mask, intset); mask 109 drivers/irqchip/irq-zevio.c gc->chip_types[0].regs.mask = IO_IRQ_BASE + IO_ENABLE; mask 53 drivers/irqchip/qcom-pdc.c u32 index, mask; mask 57 drivers/irqchip/qcom-pdc.c mask = pin_out % 32; mask 61 drivers/irqchip/qcom-pdc.c enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); mask 45 drivers/irqchip/spear-shirq.c u32 mask; mask 91 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 9) - 1) << 0, mask 107 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 8) - 1) << 0, mask 115 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 5) - 1) << 8, mask 123 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 1) - 1) << 13, mask 131 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 3) - 1) << 14, mask 151 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 7) - 1) << 0, mask 157 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 3) - 1) << 7, mask 165 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 1) - 1) << 10, mask 173 drivers/irqchip/spear-shirq.c .mask = ((0x1 << 11) - 1) << 11, mask 190 drivers/irqchip/spear-shirq.c pend = readl(shirq->base + shirq->status_reg) & shirq->mask; mask 740 drivers/isdn/capi/capi.c __poll_t mask = 0; mask 746 drivers/isdn/capi/capi.c mask = EPOLLOUT | EPOLLWRNORM; mask 748 drivers/isdn/capi/capi.c mask |= EPOLLIN | EPOLLRDNORM; mask 749 drivers/isdn/capi/capi.c return mask; mask 735 drivers/isdn/hardware/mISDN/hfcmulti.c unsigned int mask; mask 762 drivers/isdn/hardware/mISDN/hfcmulti.c mask = 0x02020202 << (x * 4); mask 766 drivers/isdn/hardware/mISDN/hfcmulti.c vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); mask 781 drivers/isdn/hardware/mISDN/hfcmulti.c if (mask & (0x00000001 << i)) mask 801 drivers/isdn/hardware/mISDN/hfcmulti.c if (mask & (0x00000001 << i)) mask 807 drivers/isdn/hardware/mISDN/hfcmulti.c if (mask & (0x00000001 << i)) mask 178 drivers/isdn/hardware/mISDN/netjet.c u32 mask = 0xff, val; mask 184 drivers/isdn/hardware/mISDN/netjet.c mask <<= 8; mask 186 drivers/isdn/hardware/mISDN/netjet.c mask ^= 0xffffffff; mask 189 drivers/isdn/hardware/mISDN/netjet.c val &= mask; mask 47 drivers/isdn/mISDN/dsp_audio.c int mask; mask 57 drivers/isdn/mISDN/dsp_audio.c mask = AMI_MASK | 0x80; mask 60 drivers/isdn/mISDN/dsp_audio.c mask = AMI_MASK; mask 71 drivers/isdn/mISDN/dsp_audio.c ((pcm_val >> ((seg) ? (seg + 3) : 4)) & 0x0F)) ^ mask; mask 139 drivers/isdn/mISDN/timerdev.c __poll_t mask = EPOLLERR; mask 145 drivers/isdn/mISDN/timerdev.c mask = 0; mask 147 drivers/isdn/mISDN/timerdev.c mask |= (EPOLLIN | EPOLLRDNORM); mask 152 drivers/isdn/mISDN/timerdev.c return mask; mask 193 drivers/leds/led-class-flash.c u32 fault, mask = 0x1; mask 204 drivers/leds/led-class-flash.c if (fault & mask) { mask 209 drivers/leds/led-class-flash.c mask <<= 1; mask 19 drivers/leds/leds-cpcap.c u16 mask; mask 27 drivers/leds/leds-cpcap.c .mask = 0x03FF, mask 33 drivers/leds/leds-cpcap.c .mask = 0x03FF, mask 39 drivers/leds/leds-cpcap.c .mask = 0x03FF, mask 46 drivers/leds/leds-cpcap.c .mask = 0x000F, mask 55 drivers/leds/leds-cpcap.c .mask = 0x0007, mask 120 drivers/leds/leds-cpcap.c led->info->reg, led->info->mask, CPCAP_LED_NO_CURRENT); mask 131 drivers/leds/leds-cpcap.c err = regmap_update_bits(led->regmap, led->info->reg, led->info->mask, mask 82 drivers/leds/leds-lm3533.c u8 mask; mask 97 drivers/leds/leds-lm3533.c mask = 1 << (2 * pattern); mask 100 drivers/leds/leds-lm3533.c val = mask; mask 104 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, LM3533_REG_PATTERN_ENABLE, val, mask); mask 430 drivers/leds/leds-lm3533.c u8 mask; mask 441 drivers/leds/leds-lm3533.c mask = LM3533_REG_CTRLBANK_BCONF_ALS_CHANNEL_MASK; mask 444 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); mask 479 drivers/leds/leds-lm3533.c u8 mask; mask 487 drivers/leds/leds-lm3533.c mask = LM3533_REG_CTRLBANK_BCONF_ALS_EN_MASK; mask 490 drivers/leds/leds-lm3533.c val = mask; mask 494 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); mask 532 drivers/leds/leds-lm3533.c u8 mask; mask 540 drivers/leds/leds-lm3533.c mask = LM3533_REG_CTRLBANK_BCONF_MAPPING_MASK; mask 543 drivers/leds/leds-lm3533.c val = mask; mask 547 drivers/leds/leds-lm3533.c ret = lm3533_update(led->lm3533, reg, val, mask); mask 46 drivers/leds/leds-lm355x.c u8 mask; mask 206 drivers/leds/leds-lm355x.c if (chip->last_flag & preg[REG_FLAG].mask) mask 209 drivers/leds/leds-lm355x.c chip->last_flag & preg[REG_FLAG].mask); mask 218 drivers/leds/leds-lm355x.c preg[REG_TORCH_CTRL].mask, mask 228 drivers/leds/leds-lm355x.c preg[REG_TORCH_CFG].mask, mask 243 drivers/leds/leds-lm355x.c preg[REG_FLASH_CTRL].mask, mask 257 drivers/leds/leds-lm355x.c preg[REG_STROBE_CFG].mask, mask 271 drivers/leds/leds-lm355x.c preg[REG_INDI_CTRL].mask, mask 281 drivers/leds/leds-lm355x.c preg[REG_INDI_CFG].mask, mask 296 drivers/leds/leds-lm355x.c preg[REG_OPMODE].mask, mask 124 drivers/leds/leds-lp5521.c static const u8 mask[] = { mask 136 drivers/leds/leds-lp5521.c lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], val[idx]); mask 150 drivers/leds/leds-lp5521.c static const u8 mask[] = { mask 156 drivers/leds/leds-lp5521.c lp55xx_update_bits(chip, LP5521_REG_OP_MODE, mask[idx], 0); mask 158 drivers/leds/leds-lp5523.c static const u8 mask[] = { mask 170 drivers/leds/leds-lp5523.c lp55xx_update_bits(chip, LP5523_REG_OP_MODE, mask[idx], val[idx]); mask 198 drivers/leds/leds-lp5523.c static const u8 mask[] = { mask 204 drivers/leds/leds-lp5523.c lp55xx_update_bits(chip, LP5523_REG_OP_MODE, mask[idx], 0); mask 130 drivers/leds/leds-lp5562.c static const u8 mask[] = { mask 142 drivers/leds/leds-lp5562.c lp55xx_update_bits(chip, LP5562_REG_OP_MODE, mask[idx], val[idx]); mask 439 drivers/leds/leds-lp5562.c u8 mask; mask 450 drivers/leds/leds-lp5562.c mask = LP5562_ENG_FOR_RGB_M; mask 455 drivers/leds/leds-lp5562.c mask = LP5562_ENG_FOR_W_M; mask 476 drivers/leds/leds-lp5562.c lp55xx_update_bits(chip, LP5562_REG_ENG_SEL, mask, val); mask 338 drivers/leds/leds-lp55xx-common.c int lp55xx_update_bits(struct lp55xx_chip *chip, u8 reg, u8 mask, u8 val) mask 347 drivers/leds/leds-lp55xx-common.c tmp &= ~mask; mask 348 drivers/leds/leds-lp55xx-common.c tmp |= val & mask; mask 180 drivers/leds/leds-lp55xx-common.h u8 mask, u8 val); mask 117 drivers/leds/leds-lp8501.c static const u8 mask[] = { mask 135 drivers/leds/leds-lp8501.c lp55xx_update_bits(chip, LP8501_REG_OP_MODE, mask[idx], val[idx]); mask 46 drivers/leds/leds-lp8788.c u8 addr, mask, val; mask 59 drivers/leds/leds-lp8788.c mask = 1 << (cfg->num + LP8788_ISINK_SCALE_OFFSET); mask 61 drivers/leds/leds-lp8788.c ret = lp8788_update_bits(led->lp, addr, mask, val); mask 67 drivers/leds/leds-lp8788.c mask = lp8788_iout_mask[cfg->num]; mask 70 drivers/leds/leds-lp8788.c return lp8788_update_bits(led->lp, addr, mask, val); mask 78 drivers/leds/leds-lp8788.c u8 mask = 1 << num; mask 81 drivers/leds/leds-lp8788.c ret = lp8788_update_bits(led->lp, LP8788_ISINK_CTRL, mask, val); mask 51 drivers/leds/leds-max77650.c int val, mask; mask 53 drivers/leds/leds-max77650.c mask = MAX77650_LED_BR_MASK | MAX77650_LED_EN_MASK; mask 60 drivers/leds/leds-max77650.c return regmap_update_bits(led->map, led->regA, mask, val); mask 52 drivers/leds/leds-max8997.c u8 mask = 0, val; mask 56 drivers/leds/leds-max8997.c mask = MAX8997_LED1_FLASH_MASK | MAX8997_LED0_FLASH_MASK; mask 62 drivers/leds/leds-max8997.c mask = MAX8997_LED1_MOVIE_MASK | MAX8997_LED0_MOVIE_MASK; mask 68 drivers/leds/leds-max8997.c mask = MAX8997_LED1_FLASH_PIN_MASK | mask 75 drivers/leds/leds-max8997.c mask = MAX8997_LED1_MOVIE_PIN_MASK | mask 86 drivers/leds/leds-max8997.c if (mask) { mask 88 drivers/leds/leds-max8997.c mask); mask 101 drivers/leds/leds-max8997.c u8 val = 0, mask = MAX8997_LED_BOOST_ENABLE_MASK; mask 108 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, MAX8997_REG_BOOST_CNTL, val, mask); mask 121 drivers/leds/leds-max8997.c u8 val = 0, mask = 0, reg = 0; mask 127 drivers/leds/leds-max8997.c mask = MAX8997_LED_FLASH_CUR_MASK; mask 133 drivers/leds/leds-max8997.c mask = MAX8997_LED_MOVIE_CUR_MASK; mask 140 drivers/leds/leds-max8997.c if (mask) { mask 141 drivers/leds/leds-max8997.c ret = max8997_update_reg(client, reg, val, mask); mask 74 drivers/leds/leds-mlxcpld.c u8 mask; mask 100 drivers/leds/leds-mlxcpld.c u8 mask; mask 258 drivers/leds/leds-mlxcpld.c static void mlxcpld_led_store_hw(u8 mask, u8 off, u8 vset) mask 275 drivers/leds/leds-mlxcpld.c nib = (mask == 0xf0) ? vset : (vset << 4); mask 276 drivers/leds/leds-mlxcpld.c val = (val & mask) | nib; mask 288 drivers/leds/leds-mlxcpld.c mlxcpld_led_store_hw(pled->param.mask, pled->param.offset, mask 293 drivers/leds/leds-mlxcpld.c mlxcpld_led_store_hw(pled->param.mask, pled->param.offset, mask 315 drivers/leds/leds-mlxcpld.c mlxcpld_led_store_hw(pled->param.mask, pled->param.offset, mask 319 drivers/leds/leds-mlxcpld.c mlxcpld_led_store_hw(pled->param.mask, pled->param.offset, mask 351 drivers/leds/leds-mlxcpld.c cpld->pled[i].param.mask = mlxcpld_led->profile[i].mask; mask 85 drivers/leds/leds-mlxreg.c nib = (ror32(data->mask, data->bit) == 0xf0) ? rol32(vset, data->bit) : mask 87 drivers/leds/leds-mlxreg.c regval = (regval & data->mask) | nib; mask 124 drivers/leds/leds-mlxreg.c regval = regval & ~data->mask; mask 125 drivers/leds/leds-mlxreg.c regval = (ror32(data->mask, data->bit) == 0xf0) ? ror32(regval, mask 250 drivers/leds/leds-mlxreg.c data->label, data->mask, data->reg); mask 34 drivers/leds/leds-nic78bx.c u8 mask; mask 55 drivers/leds/leds-nic78bx.c value &= ~nled->mask; mask 81 drivers/leds/leds-nic78bx.c .mask = NIC78BX_USER1_LED_MASK, mask 91 drivers/leds/leds-nic78bx.c .mask = NIC78BX_USER1_LED_MASK, mask 101 drivers/leds/leds-nic78bx.c .mask = NIC78BX_USER2_LED_MASK, mask 111 drivers/leds/leds-nic78bx.c .mask = NIC78BX_USER2_LED_MASK, mask 22 drivers/leds/leds-ot200.c u8 mask; mask 34 drivers/leds/leds-ot200.c .mask = BIT(0), mask 39 drivers/leds/leds-ot200.c .mask = BIT(1), mask 44 drivers/leds/leds-ot200.c .mask = BIT(2), mask 49 drivers/leds/leds-ot200.c .mask = BIT(6), mask 54 drivers/leds/leds-ot200.c .mask = BIT(5), mask 59 drivers/leds/leds-ot200.c .mask = BIT(4), mask 64 drivers/leds/leds-ot200.c .mask = BIT(3), mask 69 drivers/leds/leds-ot200.c .mask = BIT(2), mask 74 drivers/leds/leds-ot200.c .mask = BIT(1), mask 79 drivers/leds/leds-ot200.c .mask = BIT(0), mask 109 drivers/leds/leds-ot200.c *val &= ~led->mask; mask 111 drivers/leds/leds-ot200.c *val |= led->mask; mask 125 drivers/leds/leds-pca963x.c u8 mask = 0x3 << shift; mask 133 drivers/leds/leds-pca963x.c (ledout & ~mask) | (PCA963X_LED_ON << shift)); mask 137 drivers/leds/leds-pca963x.c ledout_addr, ledout & ~mask); mask 147 drivers/leds/leds-pca963x.c (ledout & ~mask) | (PCA963X_LED_PWM << shift)); mask 162 drivers/leds/leds-pca963x.c u8 mask = 0x3 << shift; mask 176 drivers/leds/leds-pca963x.c if ((ledout & mask) != (PCA963X_LED_GRP_PWM << shift)) mask 178 drivers/leds/leds-pca963x.c (ledout & ~mask) | (PCA963X_LED_GRP_PWM << shift)); mask 33 drivers/leds/leds-pm8058.c unsigned int mask = 0; mask 39 drivers/leds/leds-pm8058.c mask = PM8058_LED_TYPE_COMMON_MASK; mask 44 drivers/leds/leds-pm8058.c mask = PM8058_LED_TYPE_KEYPAD_MASK; mask 51 drivers/leds/leds-pm8058.c ret = regmap_update_bits(led->map, led->reg, mask, val); mask 134 drivers/leds/leds-powernv.c __be64 mask, value, max_type; mask 140 drivers/leds/leds-powernv.c mask = cpu_to_be64(0); mask 145 drivers/leds/leds-powernv.c &mask, &value, &max_type); mask 152 drivers/leds/leds-powernv.c led_mask = be64_to_cpu(mask); mask 31 drivers/leds/leds-syscon.c u32 mask; mask 47 drivers/leds/leds-syscon.c val = sled->mask; mask 51 drivers/leds/leds-syscon.c ret = regmap_update_bits(sled->map, sled->offset, sled->mask, val); mask 85 drivers/leds/leds-syscon.c if (of_property_read_u32(np, "mask", &sled->mask)) mask 100 drivers/leds/leds-syscon.c sled->state = !!(val & sled->mask); mask 104 drivers/leds/leds-syscon.c sled->mask, mask 105 drivers/leds/leds-syscon.c sled->mask); mask 111 drivers/leds/leds-syscon.c sled->mask, 0); mask 275 drivers/leds/leds-tca6507.c int mask = (1 << led); mask 279 drivers/leds/leds-tca6507.c int n = tca->reg_file[bit] & ~mask; mask 281 drivers/leds/leds-tca6507.c n |= mask; mask 295 drivers/leds/leds-tca6507.c int mask = 0xF; mask 298 drivers/leds/leds-tca6507.c mask <<= 4; mask 301 drivers/leds/leds-tca6507.c n = tca->reg_file[reg] & ~mask; mask 91 drivers/leds/leds-tlc591xx.c unsigned int mask = LEDOUT_MASK << i; mask 96 drivers/leds/leds-tlc591xx.c return regmap_update_bits(priv->regmap, addr, mask, val); mask 1253 drivers/macintosh/smu.c __poll_t mask = 0; mask 1264 drivers/macintosh/smu.c mask |= EPOLLIN; mask 1270 drivers/macintosh/smu.c return mask; mask 2243 drivers/macintosh/via-pmu.c __poll_t mask = 0; mask 2251 drivers/macintosh/via-pmu.c mask |= EPOLLIN; mask 2253 drivers/macintosh/via-pmu.c return mask; mask 157 drivers/mailbox/arm_mhu.c .mask = 0xffffff, mask 78 drivers/mailbox/mailbox-altera.c u32 mask; mask 80 drivers/mailbox/mailbox-altera.c mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); mask 82 drivers/mailbox/mailbox-altera.c mask |= INT_PENDING_MSK; mask 84 drivers/mailbox/mailbox-altera.c mask &= ~INT_PENDING_MSK; mask 85 drivers/mailbox/mailbox-altera.c writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); mask 90 drivers/mailbox/mailbox-altera.c u32 mask; mask 92 drivers/mailbox/mailbox-altera.c mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); mask 94 drivers/mailbox/mailbox-altera.c mask |= INT_SPACE_MSK; mask 96 drivers/mailbox/mailbox-altera.c mask &= ~INT_SPACE_MSK; mask 97 drivers/mailbox/mailbox-altera.c writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG); mask 170 drivers/mailbox/pl320-ipc.c .mask = 0x000fffff, mask 63 drivers/mailbox/stm32-ipcc.c u32 mask) mask 68 drivers/mailbox/stm32-ipcc.c writel_relaxed(readl_relaxed(reg) | mask, reg); mask 73 drivers/mailbox/stm32-ipcc.c u32 mask) mask 78 drivers/mailbox/stm32-ipcc.c writel_relaxed(readl_relaxed(reg) & ~mask, reg); mask 104 drivers/mailbox/tegra-hsp.c unsigned long mask; mask 206 drivers/mailbox/tegra-hsp.c unsigned long bit, mask; mask 210 drivers/mailbox/tegra-hsp.c status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; mask 213 drivers/mailbox/tegra-hsp.c mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK; mask 215 drivers/mailbox/tegra-hsp.c for_each_set_bit(bit, &mask, hsp->num_sm) { mask 228 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); mask 229 drivers/mailbox/tegra-hsp.c tegra_hsp_writel(hsp, hsp->mask, mask 239 drivers/mailbox/tegra-hsp.c mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK; mask 241 drivers/mailbox/tegra-hsp.c for_each_set_bit(bit, &mask, hsp->num_sm) { mask 385 drivers/mailbox/tegra-hsp.c hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index); mask 386 drivers/mailbox/tegra-hsp.c tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); mask 438 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); mask 440 drivers/mailbox/tegra-hsp.c hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index); mask 442 drivers/mailbox/tegra-hsp.c tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); mask 477 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index); mask 479 drivers/mailbox/tegra-hsp.c hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index); mask 481 drivers/mailbox/tegra-hsp.c tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq)); mask 420 drivers/md/bcache/journal.c #define nr_to_fifo_front(p, front_p, mask) (((p) - (front_p)) & (mask)) mask 428 drivers/md/bcache/journal.c size_t mask; mask 455 drivers/md/bcache/journal.c mask = c->journal.pin.mask; mask 515 drivers/md/bcache/journal.c mask) != 0) { mask 118 drivers/md/bcache/util.h size_t front, back, size, mask; \ mask 125 drivers/md/bcache/util.h iter = (iter + 1) & (fifo)->mask) mask 135 drivers/md/bcache/util.h (fifo)->mask = _allocated_size - 1; \ mask 162 drivers/md/bcache/util.h #define fifo_used(fifo) (((fifo)->back - (fifo)->front) & (fifo)->mask) mask 170 drivers/md/bcache/util.h ((fifo)->data[((fifo)->back - 1) & (fifo)->mask]) mask 172 drivers/md/bcache/util.h #define fifo_idx(fifo, p) (((p) - &fifo_front(fifo)) & (fifo)->mask) mask 179 drivers/md/bcache/util.h (fifo)->back &= (fifo)->mask; \ mask 189 drivers/md/bcache/util.h (fifo)->front &= (fifo)->mask; \ mask 199 drivers/md/bcache/util.h (fifo)->front &= (fifo)->mask; \ mask 210 drivers/md/bcache/util.h (fifo)->back &= (fifo)->mask; \ mask 224 drivers/md/bcache/util.h swap((l)->mask, (r)->mask); \ mask 1956 drivers/md/dm-ioctl.c __poll_t mask = 0; mask 1961 drivers/md/dm-ioctl.c mask |= EPOLLIN; mask 1963 drivers/md/dm-ioctl.c return mask; mask 66 drivers/md/dm-region-hash.c unsigned mask; mask 200 drivers/md/dm-region-hash.c rh->mask = nr_buckets - 1; mask 268 drivers/md/dm-region-hash.c return (unsigned) ((region * rh->prime) >> rh->shift) & rh->mask; mask 8124 drivers/md/md.c __poll_t mask; mask 8131 drivers/md/md.c mask = EPOLLIN | EPOLLRDNORM; mask 8134 drivers/md/md.c mask |= EPOLLERR | EPOLLPRI; mask 8135 drivers/md/md.c return mask; mask 133 drivers/md/persistent-data/dm-space-map-common.c uint64_t mask = (bits + WORD_MASK_HIGH + 1) & WORD_MASK_HIGH; mask 135 drivers/md/persistent-data/dm-space-map-common.c return !(~bits & mask); mask 47 drivers/media/common/b2c2/flexcop-hw-filter.c u16 pid, u16 mask) mask 52 drivers/media/common/b2c2/flexcop-hw-filter.c v30c.pid_filter_30c_ext_ind_0_7.Group_mask = mask; mask 216 drivers/media/common/b2c2/flexcop-sram.c static void sram_set_size(struct adapter *adapter, u32 mask) mask 219 drivers/media/common/b2c2/flexcop-sram.c (mask | (~0x30000 & read_reg_dw(adapter, 0x71c)))); mask 238 drivers/media/common/b2c2/flexcop-sram.c static int sram_test_location(struct adapter *adapter, u32 mask, u32 addr) mask 241 drivers/media/common/b2c2/flexcop-sram.c dprintk("%s: mask = %x, addr = %x\n", __func__, mask, addr); mask 243 drivers/media/common/b2c2/flexcop-sram.c sram_set_size(adapter, mask); mask 25 drivers/media/common/btcx-risc.h unsigned int n, int mask); mask 1569 drivers/media/common/cx2341x.c u32 id, s32 max, s32 mask, s32 def) mask 1571 drivers/media/common/cx2341x.c return v4l2_ctrl_new_std_menu(hdl, &cx2341x_ops, id, max, mask, def); mask 754 drivers/media/dvb-core/dmxdev.c ¶->filter.mask[1], DMX_FILTER_SIZE - 1); mask 759 drivers/media/dvb-core/dmxdev.c (*secfilter)->filter_mask[0] = para->filter.mask[0]; mask 1196 drivers/media/dvb-core/dmxdev.c __poll_t mask = 0; mask 1211 drivers/media/dvb-core/dmxdev.c mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI | EPOLLERR); mask 1214 drivers/media/dvb-core/dmxdev.c mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI); mask 1216 drivers/media/dvb-core/dmxdev.c return mask; mask 1345 drivers/media/dvb-core/dmxdev.c __poll_t mask = 0; mask 1359 drivers/media/dvb-core/dmxdev.c mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI | EPOLLERR); mask 1362 drivers/media/dvb-core/dmxdev.c mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI); mask 1364 drivers/media/dvb-core/dmxdev.c mask |= (EPOLLOUT | EPOLLWRNORM | EPOLLPRI); mask 1366 drivers/media/dvb-core/dmxdev.c return mask; mask 1783 drivers/media/dvb-core/dvb_ca_en50221.c __poll_t mask = 0; mask 1792 drivers/media/dvb-core/dvb_ca_en50221.c mask |= EPOLLIN; mask 1795 drivers/media/dvb-core/dvb_ca_en50221.c if (mask) mask 1796 drivers/media/dvb-core/dvb_ca_en50221.c return mask; mask 1799 drivers/media/dvb-core/dvb_ca_en50221.c mask |= EPOLLIN; mask 1801 drivers/media/dvb-core/dvb_ca_en50221.c return mask; mask 934 drivers/media/dvb-core/dvb_demux.c u8 mask, mode, doneq; mask 943 drivers/media/dvb-core/dvb_demux.c mask = sf->filter_mask[i]; mask 944 drivers/media/dvb-core/dvb_demux.c f->maskandmode[i] = mask & mode; mask 945 drivers/media/dvb-core/dvb_demux.c doneq |= f->maskandnotmode[i] = mask & ~mode; mask 896 drivers/media/dvb-frontends/af9013.c ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask, mask 949 drivers/media/dvb-frontends/af9013.c ret = regmap_update_bits(state->regmap, tab[i].reg, tab[i].mask, mask 26 drivers/media/dvb-frontends/af9013_priv.h u8 mask; mask 144 drivers/media/dvb-frontends/af9033.c ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask, mask 27 drivers/media/dvb-frontends/af9033_priv.h u8 mask; mask 200 drivers/media/dvb-frontends/ascot2e.c u8 reg, u8 data, u8 mask) mask 205 drivers/media/dvb-frontends/ascot2e.c if (mask != 0xff) { mask 209 drivers/media/dvb-frontends/ascot2e.c data = ((data & mask) | (rdata & (mask ^ 0xFF))); mask 363 drivers/media/dvb-frontends/cx24116.c u8 mask; /* In DVBS mode this is used to autodetect */ mask 436 drivers/media/dvb-frontends/cx24116.c state->dnxt.fec_mask = CX24116_MODFEC_MODES[ret].mask; mask 214 drivers/media/dvb-frontends/cx24117.c u8 mask; /* In DVBS mode this is used to autodetect */ mask 415 drivers/media/dvb-frontends/cx24117.c state->dnxt.fec_mask = cx24117_modfec_modes[ret].mask; mask 139 drivers/media/dvb-frontends/cxd2099.c static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) mask 146 drivers/media/dvb-frontends/cxd2099.c if (!status && reg >= 6 && reg <= 8 && mask != 0xff) { mask 151 drivers/media/dvb-frontends/cxd2099.c ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; mask 17 drivers/media/dvb-frontends/cxd2820r_core.c unsigned int i, reg, mask, val; mask 30 drivers/media/dvb-frontends/cxd2820r_core.c mask = tab[i].mask; mask 32 drivers/media/dvb-frontends/cxd2820r_core.c if (mask == 0xff) mask 35 drivers/media/dvb-frontends/cxd2820r_core.c ret = regmap_write_bits(regmap, reg, mask, val); mask 23 drivers/media/dvb-frontends/cxd2820r_priv.h u8 mask; mask 63 drivers/media/dvb-frontends/cxd2820r_priv.h u8 mask); mask 297 drivers/media/dvb-frontends/cxd2841er.c u8 addr, u8 reg, u8 data, u8 mask) mask 302 drivers/media/dvb-frontends/cxd2841er.c if (mask != 0xff) { mask 306 drivers/media/dvb-frontends/cxd2841er.c data = ((data & mask) | (rdata & (mask ^ 0xFF))); mask 24 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c u8 sub_address, u8 data, u8 mask) mask 31 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c if (mask == 0x00) mask 34 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c if (mask != 0xff) { mask 41 drivers/media/dvb-frontends/cxd2880/cxd2880_io.c data = (data & mask) | (rdata & (mask ^ 0xff)); mask 48 drivers/media/dvb-frontends/cxd2880/cxd2880_io.h u8 sub_address, u8 data, u8 mask); mask 1091 drivers/media/dvb-frontends/dib9000.c if (f->mask) { mask 1094 drivers/media/dvb-frontends/dib9000.c b[0] = (u16) f->mask; mask 1099 drivers/media/dvb-frontends/dib9000.c b[3] = (u16) f->mask; mask 1113 drivers/media/dvb-frontends/dib9000.c b[2 + i * 4] = (u16) state->chip.d9.cfg.subband.subband[i].gpio.mask; mask 253 drivers/media/dvb-frontends/dibx000_common.h u32 mask; mask 376 drivers/media/dvb-frontends/helene.c u8 reg, u8 data, u8 mask) mask 381 drivers/media/dvb-frontends/helene.c if (mask != 0xff) { mask 385 drivers/media/dvb-frontends/helene.c data = ((data & mask) | (rdata & (mask ^ 0xFF))); mask 101 drivers/media/dvb-frontends/lgs8gxx.c static int wait_reg_mask(struct lgs8gxx_state *priv, u8 reg, u8 mask, mask 110 drivers/media/dvb-frontends/lgs8gxx.c if ((t & mask) == val) mask 318 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; mask 322 drivers/media/dvb-frontends/lgs8gxx.c mask = 0x80; mask 326 drivers/media/dvb-frontends/lgs8gxx.c mask = 0xC0; mask 330 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 50, 40); mask 340 drivers/media/dvb-frontends/lgs8gxx.c u8 reg, mask, val; mask 344 drivers/media/dvb-frontends/lgs8gxx.c mask = 0xC0; mask 348 drivers/media/dvb-frontends/lgs8gxx.c mask = 0x03; mask 352 drivers/media/dvb-frontends/lgs8gxx.c ret = wait_reg_mask(priv, reg, mask, val, 10, 20); mask 14 drivers/media/dvb-frontends/m88ds3103.c u8 reg, u8 mask, u8 val) mask 20 drivers/media/dvb-frontends/m88ds3103.c if (mask != 0xff) { mask 25 drivers/media/dvb-frontends/m88ds3103.c val &= mask; mask 26 drivers/media/dvb-frontends/m88ds3103.c tmp &= ~mask; mask 300 drivers/media/dvb-frontends/mxl5xx.c u32 data = 0, mask = 0; mask 306 drivers/media/dvb-frontends/mxl5xx.c mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); mask 307 drivers/media/dvb-frontends/mxl5xx.c data &= mask; mask 317 drivers/media/dvb-frontends/mxl5xx.c u32 data, mask; mask 323 drivers/media/dvb-frontends/mxl5xx.c mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); mask 324 drivers/media/dvb-frontends/mxl5xx.c data = (data & ~mask) | ((val << lsbloc) & mask); mask 24 drivers/media/dvb-frontends/rtl2830.c unsigned int mask, unsigned int val) mask 30 drivers/media/dvb-frontends/rtl2830.c ret = regmap_update_bits(dev->regmap, reg, mask, val); mask 93 drivers/media/dvb-frontends/rtl2830.c ret = rtl2830_update_bits(client, tab[i].reg, tab[i].mask, mask 36 drivers/media/dvb-frontends/rtl2830_priv.h u8 mask; mask 149 drivers/media/dvb-frontends/rtl2832.c u32 reading_tmp, mask; mask 155 drivers/media/dvb-frontends/rtl2832.c mask = REG_MASK(msb - lsb); mask 165 drivers/media/dvb-frontends/rtl2832.c *val = (reading_tmp >> lsb) & mask; mask 179 drivers/media/dvb-frontends/rtl2832.c u32 reading_tmp, writing_tmp, mask; mask 185 drivers/media/dvb-frontends/rtl2832.c mask = REG_MASK(msb - lsb); mask 195 drivers/media/dvb-frontends/rtl2832.c writing_tmp = reading_tmp & ~(mask << lsb); mask 196 drivers/media/dvb-frontends/rtl2832.c writing_tmp |= ((val & mask) << lsb); mask 155 drivers/media/dvb-frontends/si2165.c u8 val, u8 mask) mask 157 drivers/media/dvb-frontends/si2165.c if (mask != 0xff) { mask 164 drivers/media/dvb-frontends/si2165.c val &= mask; mask 165 drivers/media/dvb-frontends/si2165.c tmp &= ~mask; mask 57 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_SETFIELD(mask, val, width, offset) (mask & (~(((1 << width) - 1) << \ mask 61 drivers/media/dvb-frontends/stb0899_priv.h #define STB0899_SETFIELD_VAL(bitf, mask, val) (mask = (mask & (~(((1 << STB0899_WIDTH_##bitf) - 1) <<\ mask 91 drivers/media/dvb-frontends/stb6100.c u8 mask; mask 118 drivers/media/dvb-frontends/stb6100.c regs[i] = (regs[i] & stb6100_template[i].mask) | stb6100_template[i].set; mask 223 drivers/media/dvb-frontends/stb6100.c tmp = (tmp & stb6100_template[reg].mask) | stb6100_template[reg].set; mask 83 drivers/media/dvb-frontends/stv0297.c static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data) mask 88 drivers/media/dvb-frontends/stv0297.c val &= ~mask; mask 89 drivers/media/dvb-frontends/stv0297.c val |= (data & mask); mask 198 drivers/media/dvb-frontends/stv0367.c static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) mask 202 drivers/media/dvb-frontends/stv0367.c (*mask) = label & 0xff; mask 205 drivers/media/dvb-frontends/stv0367.c position = ((*mask) >> i) & 0x01; mask 214 drivers/media/dvb-frontends/stv0367.c u8 reg, mask, pos; mask 217 drivers/media/dvb-frontends/stv0367.c extract_mask_pos(label, &mask, &pos); mask 219 drivers/media/dvb-frontends/stv0367.c val = mask & (val << pos); mask 221 drivers/media/dvb-frontends/stv0367.c reg = (reg & (~mask)) | val; mask 228 drivers/media/dvb-frontends/stv0367.c u8 mask, pos; mask 230 drivers/media/dvb-frontends/stv0367.c extract_mask_pos(label, &mask, &pos); mask 232 drivers/media/dvb-frontends/stv0367.c val = mask & (val << pos); mask 234 drivers/media/dvb-frontends/stv0367.c (*reg) = ((*reg) & (~mask)) | val; mask 240 drivers/media/dvb-frontends/stv0367.c u8 mask, pos; mask 242 drivers/media/dvb-frontends/stv0367.c extract_mask_pos(label, &mask, &pos); mask 245 drivers/media/dvb-frontends/stv0367.c val = (val & mask) >> pos; mask 253 drivers/media/dvb-frontends/stv0367.c u8 mask, pos; mask 255 drivers/media/dvb-frontends/stv0367.c extract_mask_pos(label, &mask, &pos); mask 257 drivers/media/dvb-frontends/stv0367.c return (reg & mask) >> pos; mask 166 drivers/media/dvb-frontends/stv0900_core.c static void extract_mask_pos(u32 label, u8 *mask, u8 *pos) mask 170 drivers/media/dvb-frontends/stv0900_core.c (*mask) = label & 0xff; mask 173 drivers/media/dvb-frontends/stv0900_core.c position = ((*mask) >> i) & 0x01; mask 182 drivers/media/dvb-frontends/stv0900_core.c u8 reg, mask, pos; mask 185 drivers/media/dvb-frontends/stv0900_core.c extract_mask_pos(label, &mask, &pos); mask 187 drivers/media/dvb-frontends/stv0900_core.c val = mask & (val << pos); mask 189 drivers/media/dvb-frontends/stv0900_core.c reg = (reg & (~mask)) | val; mask 197 drivers/media/dvb-frontends/stv0900_core.c u8 mask, pos; mask 199 drivers/media/dvb-frontends/stv0900_core.c extract_mask_pos(label, &mask, &pos); mask 202 drivers/media/dvb-frontends/stv0900_core.c val = (val & mask) >> pos; mask 53 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\ mask 60 drivers/media/dvb-frontends/stv090x_priv.h #define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\ mask 185 drivers/media/dvb-frontends/stv0910.c static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val) mask 193 drivers/media/dvb-frontends/stv0910.c status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); mask 201 drivers/media/dvb-frontends/stv0910.c u8 shift, mask, old, new; mask 206 drivers/media/dvb-frontends/stv0910.c mask = field & 0xff; mask 208 drivers/media/dvb-frontends/stv0910.c new = ((val << shift) & mask) | (old & ~mask); mask 37 drivers/media/dvb-frontends/stv6110x_priv.h #define STV6110x_SETFIELD(mask, bitf, val) \ mask 38 drivers/media/dvb-frontends/stv6110x_priv.h (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \ mask 351 drivers/media/dvb-frontends/stv6111.c static int wait_for_call_done(struct stv *state, u8 mask) mask 363 drivers/media/dvb-frontends/stv6111.c if ((regval & mask) == 0) mask 85 drivers/media/dvb-frontends/tda10023.c static int tda10023_writebit (struct tda10023_state* state, u8 reg, u8 mask,u8 data) mask 87 drivers/media/dvb-frontends/tda10023.c if (mask==0xff) mask 92 drivers/media/dvb-frontends/tda10023.c val&=~mask; mask 93 drivers/media/dvb-frontends/tda10023.c val|=(data&mask); mask 160 drivers/media/dvb-frontends/tda1004x.c static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) mask 164 drivers/media/dvb-frontends/tda1004x.c mask, data); mask 172 drivers/media/dvb-frontends/tda1004x.c val = val & ~mask; mask 19 drivers/media/dvb-frontends/tda10071.c u8 reg, u8 val, u8 mask) mask 25 drivers/media/dvb-frontends/tda10071.c if (mask != 0xff) { mask 30 drivers/media/dvb-frontends/tda10071.c val &= mask; mask 31 drivers/media/dvb-frontends/tda10071.c tmp &= ~mask; mask 823 drivers/media/dvb-frontends/tda10071.c tab[i].val, tab[i].mask); mask 850 drivers/media/dvb-frontends/tda10071.c tab2[i].val, tab2[i].mask); mask 1071 drivers/media/dvb-frontends/tda10071.c tab[i].mask); mask 73 drivers/media/dvb-frontends/tda10071_priv.h u8 mask; mask 76 drivers/media/dvb-frontends/tda10086.c static int tda10086_write_mask(struct tda10086_state *state, int reg, int mask, int data) mask 86 drivers/media/dvb-frontends/tda10086.c val = val & ~mask; mask 1349 drivers/media/firewire/firedtv-avc.c static inline u32 get_opcr(__be32 opcr, u32 mask, u32 shift) mask 1351 drivers/media/firewire/firedtv-avc.c return (be32_to_cpu(opcr) >> shift) & mask; mask 1354 drivers/media/firewire/firedtv-avc.c static inline void set_opcr(__be32 *opcr, u32 value, u32 mask, u32 shift) mask 1356 drivers/media/firewire/firedtv-avc.c *opcr &= ~cpu_to_be32(mask << shift); mask 1357 drivers/media/firewire/firedtv-avc.c *opcr |= cpu_to_be32((value & mask) << shift); mask 271 drivers/media/i2c/adv7511-v4l2.c static inline int adv7511_cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, mask 274 drivers/media/i2c/adv7511-v4l2.c return adv7511_cec_write(sd, reg, (adv7511_cec_read(sd, reg) & mask) | val); mask 388 drivers/media/i2c/adv7604.c static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, mask 391 drivers/media/i2c/adv7604.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); mask 422 drivers/media/i2c/adv7604.c static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, mask 425 drivers/media/i2c/adv7604.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); mask 470 drivers/media/i2c/adv7604.c static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 472 drivers/media/i2c/adv7604.c return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); mask 542 drivers/media/i2c/adv7604.c static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) mask 544 drivers/media/i2c/adv7604.c return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; mask 554 drivers/media/i2c/adv7604.c static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 556 drivers/media/i2c/adv7604.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); mask 573 drivers/media/i2c/adv7604.c static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) mask 575 drivers/media/i2c/adv7604.c return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; mask 585 drivers/media/i2c/adv7604.c static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 587 drivers/media/i2c/adv7604.c return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); mask 376 drivers/media/i2c/adv7842.c static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 378 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & mask) | val); mask 382 drivers/media/i2c/adv7842.c u8 reg, u8 mask, u8 val) mask 384 drivers/media/i2c/adv7842.c return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); mask 415 drivers/media/i2c/adv7842.c static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 417 drivers/media/i2c/adv7842.c return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); mask 448 drivers/media/i2c/adv7842.c static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 450 drivers/media/i2c/adv7842.c return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val); mask 467 drivers/media/i2c/adv7842.c static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 469 drivers/media/i2c/adv7842.c return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val); mask 486 drivers/media/i2c/adv7842.c static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 488 drivers/media/i2c/adv7842.c return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val); mask 505 drivers/media/i2c/adv7842.c static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 507 drivers/media/i2c/adv7842.c return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val); mask 538 drivers/media/i2c/adv7842.c static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 540 drivers/media/i2c/adv7842.c return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val); mask 557 drivers/media/i2c/adv7842.c static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) mask 559 drivers/media/i2c/adv7842.c return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val); mask 712 drivers/media/i2c/adv7842.c u8 mask = 0; mask 718 drivers/media/i2c/adv7842.c mask |= 0x20; mask 720 drivers/media/i2c/adv7842.c mask |= 0x10; mask 721 drivers/media/i2c/adv7842.c io_write_and_or(sd, 0x20, 0xcf, mask); mask 47 drivers/media/i2c/ak881x.c const u8 data, u8 mask) mask 52 drivers/media/i2c/ak881x.c return reg_write(client, reg, (ret & ~mask) | (data & mask)); mask 159 drivers/media/i2c/cx25840/cx25840-core.h int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned int mask, mask 484 drivers/media/i2c/cx25840/cx25840-ir.c static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask) mask 489 drivers/media/i2c/cx25840/cx25840-ir.c mask ^= IRQEN_MSK; mask 490 drivers/media/i2c/cx25840/cx25840-ir.c mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); mask 492 drivers/media/i2c/cx25840/cx25840-ir.c ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); mask 495 drivers/media/i2c/cx25840/cx25840-ir.c static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask) mask 500 drivers/media/i2c/cx25840/cx25840-ir.c mask ^= IRQEN_MSK; mask 501 drivers/media/i2c/cx25840/cx25840-ir.c mask &= IRQEN_TSE; mask 502 drivers/media/i2c/cx25840/cx25840-ir.c cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask); mask 277 drivers/media/i2c/m5mols/m5mols.h int m5mols_busy_wait(struct v4l2_subdev *sd, u32 reg, u32 value, u32 mask, mask 297 drivers/media/i2c/m5mols/m5mols_core.c int m5mols_busy_wait(struct v4l2_subdev *sd, u32 reg, u32 value, u32 mask, mask 307 drivers/media/i2c/m5mols/m5mols_core.c if (ret < 0 && !(mask & M5MOLS_I2C_RDY_WAIT_FL)) mask 309 drivers/media/i2c/m5mols/m5mols_core.c if (!ret && (status & mask & 0xff) == (value & 0xff)) mask 328 drivers/media/i2c/m5mols/m5mols_core.c u8 mask = is_available_af(info) ? REG_INT_AF : 0; mask 334 drivers/media/i2c/m5mols/m5mols_core.c ret = m5mols_write(sd, SYSTEM_INT_ENABLE, reg & ~mask); mask 102 drivers/media/i2c/ml86v7667.c const u8 mask, const u8 data) mask 108 drivers/media/i2c/ml86v7667.c val = (val & ~mask) | (data & mask); mask 143 drivers/media/i2c/mt9m111.c #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ mask 144 drivers/media/i2c/mt9m111.c (val), (mask)) mask 366 drivers/media/i2c/mt9m111.c const u16 data, const u16 mask) mask 372 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data); mask 787 drivers/media/i2c/mt9m111.c static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask) mask 793 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask); mask 795 drivers/media/i2c/mt9m111.c ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask); mask 209 drivers/media/i2c/mt9t112.c u16 command, u16 mask, u16 set) mask 216 drivers/media/i2c/mt9t112.c val &= ~mask; mask 217 drivers/media/i2c/mt9t112.c val |= set & mask; mask 247 drivers/media/i2c/mt9t112.c u16 command, u16 mask, u16 set) mask 254 drivers/media/i2c/mt9t112.c val &= ~mask; mask 255 drivers/media/i2c/mt9t112.c val |= set & mask; mask 335 drivers/media/i2c/mt9v111.c u16 mask, u16 val) mask 350 drivers/media/i2c/mt9v111.c current_val &= ~mask; mask 351 drivers/media/i2c/mt9v111.c current_val |= (val & mask); mask 31 drivers/media/i2c/ov2640.c #define VAL_SET(x, mask, rshift, lshift) \ mask 32 drivers/media/i2c/ov2640.c ((((x) >> rshift) & mask) << lshift) mask 673 drivers/media/i2c/ov2640.c u8 reg, u8 mask, u8 set) mask 679 drivers/media/i2c/ov2640.c val &= ~mask; mask 680 drivers/media/i2c/ov2640.c val |= set & mask; mask 269 drivers/media/i2c/ov2680.c static int ov2680_mod_reg(struct ov2680_dev *sensor, u16 reg, u8 mask, u8 val) mask 278 drivers/media/i2c/ov2680.c readval &= ~mask; mask 279 drivers/media/i2c/ov2680.c val &= mask; mask 179 drivers/media/i2c/ov5640.c u8 mask; mask 702 drivers/media/i2c/ov5640.c u8 mask, u8 val) mask 711 drivers/media/i2c/ov5640.c readval &= ~mask; mask 712 drivers/media/i2c/ov5640.c val &= mask; mask 1103 drivers/media/i2c/ov5640.c u8 mask, val; mask 1110 drivers/media/i2c/ov5640.c mask = regs->mask; mask 1112 drivers/media/i2c/ov5640.c if (mask) mask 1113 drivers/media/i2c/ov5640.c ret = ov5640_mod_reg(sensor, reg_addr, mask, val); mask 280 drivers/media/i2c/ov6650.c static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) mask 293 drivers/media/i2c/ov6650.c val &= ~mask; mask 581 drivers/media/i2c/ov7670.c unsigned char mask, unsigned char value) mask 590 drivers/media/i2c/ov7670.c return ov7670_write(sd, reg, (orig & ~mask) | (value & mask)); mask 465 drivers/media/i2c/rj54n1cb0c.c const u8 data, const u8 mask) mask 472 drivers/media/i2c/rj54n1cb0c.c return reg_write(client, reg, (ret & ~mask) | (data & mask)); mask 1290 drivers/media/i2c/saa7115.c u8 mask = (state->ident <= SAA7111A) ? 0xf8 : 0xf0; mask 1326 drivers/media/i2c/saa7115.c (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) | mask 222 drivers/media/i2c/tc358743.c u8 mask, u8 val) mask 224 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1); mask 237 drivers/media/i2c/tc358743.c static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val) mask 239 drivers/media/i2c/tc358743.c i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2); mask 502 drivers/media/i2c/tc358743.c static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask) mask 506 drivers/media/i2c/tc358743.c i2c_wr16(sd, SYSCTL, sysctl | mask); mask 507 drivers/media/i2c/tc358743.c i2c_wr16(sd, SYSCTL, sysctl & ~mask); mask 1444 drivers/media/i2c/tda1997x.c u8 mask = 1<<input; mask 1447 drivers/media/i2c/tda1997x.c if ((irq_status & mask) != (state->activity_status & mask)) { mask 1449 drivers/media/i2c/tda1997x.c if ((irq_status & mask) == 0) { mask 1476 drivers/media/i2c/tda1997x.c state->activity_status = (irq_status & mask); mask 198 drivers/media/i2c/tvaudio.c int subaddr, int val, int mask) mask 202 drivers/media/i2c/tvaudio.c if (mask != 0) { mask 204 drivers/media/i2c/tvaudio.c val = (chip->shadow.bytes[1] & ~mask) | (val & mask); mask 213 drivers/media/i2c/tvaudio.c val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask); mask 263 drivers/media/i2c/tvp5150.c unsigned int mask, val; mask 299 drivers/media/i2c/tvp5150.c mask = TVP5150_MISC_CTL_GPCL | TVP5150_MISC_CTL_HVLK; mask 304 drivers/media/i2c/tvp5150.c regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val); mask 843 drivers/media/i2c/tvp5150.c unsigned int mask, active = 0, status = 0; mask 845 drivers/media/i2c/tvp5150.c mask = TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_SYNC_OE | mask 858 drivers/media/i2c/tvp5150.c regmap_update_bits(map, TVP5150_MISC_CTL, mask, mask 1213 drivers/media/i2c/tvp5150.c unsigned int mask, val = 0, int_val = 0; mask 1215 drivers/media/i2c/tvp5150.c mask = TVP5150_MISC_CTL_YCBCR_OE | TVP5150_MISC_CTL_SYNC_OE | mask 1230 drivers/media/i2c/tvp5150.c regmap_update_bits(decoder->regmap, TVP5150_MISC_CTL, mask, val); mask 1308 drivers/media/i2c/tvp5150.c int i, mask = 0; mask 1315 drivers/media/i2c/tvp5150.c mask |= svbi->service_lines[0][i]; mask 1317 drivers/media/i2c/tvp5150.c svbi->service_set = mask; mask 339 drivers/media/i2c/tw9910.c u8 mask, u8 set) mask 346 drivers/media/i2c/tw9910.c val &= ~mask; mask 347 drivers/media/i2c/tw9910.c val |= set & mask; mask 177 drivers/media/i2c/video-i2c.c unsigned int mask = AMG88XX_FPSC_1FPS; mask 181 drivers/media/i2c/video-i2c.c val = mask; mask 185 drivers/media/i2c/video-i2c.c return regmap_update_bits(data->regmap, AMG88XX_REG_FPSC, mask, val); mask 827 drivers/media/mc/mc-entity.c const u32 mask = MEDIA_LNK_FL_ENABLED; mask 836 drivers/media/mc/mc-entity.c if ((link->flags & ~mask) != (flags & ~mask)) mask 56 drivers/media/pci/bt8xx/bt878.c #define btaor(dat,mask,adr) btwrite((dat) | ((mask) & btread(adr)), adr) mask 249 drivers/media/pci/bt8xx/bt878.c u32 stat, astat, mask; mask 258 drivers/media/pci/bt8xx/bt878.c mask = btread(BT878_AINT_MASK); mask 259 drivers/media/pci/bt8xx/bt878.c if (!(astat = (stat & mask))) mask 331 drivers/media/pci/bt8xx/bt878.c mp->enb.mask, mask 337 drivers/media/pci/bt8xx/bt878.c mp->outp.mask, mask 123 drivers/media/pci/bt8xx/btcx-risc.c btcx_align(struct v4l2_rect *win, struct v4l2_clip *clips, unsigned int n, int mask) mask 129 drivers/media/pci/bt8xx/btcx-risc.c nx = (win->left + mask) & ~mask; mask 130 drivers/media/pci/bt8xx/btcx-risc.c nw = (win->width) & ~mask; mask 132 drivers/media/pci/bt8xx/btcx-risc.c nw -= mask+1; mask 141 drivers/media/pci/bt8xx/btcx-risc.c nx = (clips[i].c.left-dx) & ~mask; mask 142 drivers/media/pci/bt8xx/btcx-risc.c nw = (clips[i].c.width) & ~mask; mask 144 drivers/media/pci/bt8xx/btcx-risc.c nw += mask+1; mask 23 drivers/media/pci/bt8xx/btcx-risc.h unsigned int n, int mask); mask 3793 drivers/media/pci/bt8xx/bttv-cards.c u32 mask = (1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | mask 3797 drivers/media/pci/bt8xx/bttv-cards.c gpio_inout(mask, (1 << gpio.data) | (1 << gpio.clk) | mask 3800 drivers/media/pci/bt8xx/bttv-cards.c gpio_inout(mask, (1 << gpio.clk) | (1 << gpio.wren)); mask 4116 drivers/media/pci/bt8xx/bttv-cards.c int mask = (1 << pin); mask 4118 drivers/media/pci/bt8xx/bttv-cards.c gpio_inout(mask,mask); mask 4119 drivers/media/pci/bt8xx/bttv-cards.c gpio_bits(mask,0); mask 4122 drivers/media/pci/bt8xx/bttv-cards.c gpio_bits(mask,mask); mask 129 drivers/media/pci/bt8xx/bttv-gpio.c void bttv_gpio_inout(struct bttv_core *core, u32 mask, u32 outbits) mask 137 drivers/media/pci/bt8xx/bttv-gpio.c data = data & ~mask; mask 138 drivers/media/pci/bt8xx/bttv-gpio.c data = data | (mask & outbits); mask 159 drivers/media/pci/bt8xx/bttv-gpio.c void bttv_gpio_bits(struct bttv_core *core, u32 mask, u32 bits) mask 167 drivers/media/pci/bt8xx/bttv-gpio.c data = data & ~mask; mask 168 drivers/media/pci/bt8xx/bttv-gpio.c data = data | (mask & bits); mask 45 drivers/media/pci/bt8xx/bttv-if.c int bttv_gpio_enable(unsigned int card, unsigned long mask, unsigned long data) mask 57 drivers/media/pci/bt8xx/bttv-if.c gpio_inout(mask,data); mask 85 drivers/media/pci/bt8xx/bttv-if.c int bttv_write_gpio(unsigned int card, unsigned long mask, unsigned long data) mask 99 drivers/media/pci/bt8xx/bttv-if.c gpio_bits(mask,data); mask 312 drivers/media/pci/bt8xx/bttv.h unsigned long mask, unsigned long data); mask 324 drivers/media/pci/bt8xx/bttv.h unsigned long mask, unsigned long data); mask 351 drivers/media/pci/bt8xx/bttv.h void bttv_gpio_inout(struct bttv_core *core, u32 mask, u32 outbits); mask 354 drivers/media/pci/bt8xx/bttv.h void bttv_gpio_bits(struct bttv_core *core, u32 mask, u32 bits); mask 356 drivers/media/pci/bt8xx/bttv.h #define gpio_inout(mask,bits) bttv_gpio_inout(&btv->c, mask, bits) mask 359 drivers/media/pci/bt8xx/bttv.h #define gpio_bits(mask,bits) bttv_gpio_bits(&btv->c, mask, bits) mask 521 drivers/media/pci/bt8xx/bttvp.h #define btaor(dat,mask,adr) btwrite((dat) | ((mask) & btread(adr)), adr) mask 55 drivers/media/pci/bt8xx/dst.c static int dst_gpio_outb(struct dst_state *state, u32 mask, u32 enbb, mask 62 drivers/media/pci/bt8xx/dst.c enb.enb.mask = mask; mask 66 drivers/media/pci/bt8xx/dst.c mask, enbb, outhigh); mask 69 drivers/media/pci/bt8xx/dst.c err, mask, enbb); mask 78 drivers/media/pci/bt8xx/dst.c bits.outp.mask = enbb; mask 9 drivers/media/pci/bt8xx/dst_priv.h u32 mask; mask 14 drivers/media/pci/bt8xx/dst_priv.h u32 mask; mask 139 drivers/media/pci/cobalt/cobalt-irq.c u32 mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK); mask 145 drivers/media/pci/cobalt/cobalt-irq.c cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, mask & ~edge); mask 160 drivers/media/pci/cobalt/cobalt-irq.c mask & ~edge); mask 167 drivers/media/pci/cobalt/cobalt-irq.c if ((edge & mask & dma_fifo_mask) && vb2_is_streaming(&s->q)) { mask 175 drivers/media/pci/cobalt/cobalt-irq.c if (edge & mask & (COBALT_SYSSTAT_VI0_INT1_MSK | mask 182 drivers/media/pci/cobalt/cobalt-irq.c if (edge & mask & (COBALT_SYSSTAT_VI0_INT2_MSK | mask 188 drivers/media/pci/cobalt/cobalt-irq.c if (edge & mask & COBALT_SYSSTAT_VOHSMA_INT1_MSK) mask 192 drivers/media/pci/cobalt/cobalt-irq.c if (!(edge & mask) && !dma_interrupt) mask 209 drivers/media/pci/cobalt/cobalt-irq.c u32 mask; mask 213 drivers/media/pci/cobalt/cobalt-irq.c mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK); mask 215 drivers/media/pci/cobalt/cobalt-irq.c mask | s->adv_irq_mask); mask 222 drivers/media/pci/cobalt/cobalt-irq.c u32 mask; mask 236 drivers/media/pci/cobalt/cobalt-irq.c mask = cobalt_read_bar1(cobalt, COBALT_SYS_STAT_MASK); mask 238 drivers/media/pci/cobalt/cobalt-irq.c mask | mask 18 drivers/media/pci/cx18/cx18-av-core.c u32 mask = 0xff; mask 22 drivers/media/pci/cx18/cx18-av-core.c x = (x & ~(mask << shift)) | ((u32)value << shift); mask 27 drivers/media/pci/cx18/cx18-av-core.c int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask) mask 35 drivers/media/pci/cx18/cx18-av-core.c ((u32)eval << shift), ((u32)mask << shift)); mask 46 drivers/media/pci/cx18/cx18-av-core.c cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask) mask 48 drivers/media/pci/cx18/cx18-av-core.c cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); mask 347 drivers/media/pci/cx18/cx18-av-core.h int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask); mask 349 drivers/media/pci/cx18/cx18-av-core.h u32 mask); mask 352 drivers/media/pci/cx18/cx18-av-core.h int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); mask 353 drivers/media/pci/cx18/cx18-av-core.h int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); mask 286 drivers/media/pci/cx18/cx18-cards.c .gpio_audio_input = { .mask = 0x3, mask 346 drivers/media/pci/cx18/cx18-cards.c .gpio_audio_input = { .mask = 0x3, mask 401 drivers/media/pci/cx18/cx18-cards.c .gpio_audio_input = { .mask = 0xf002, mask 498 drivers/media/pci/cx18/cx18-cards.c .gpio_audio_input = { .mask = 0x7, mask 551 drivers/media/pci/cx18/cx18-cards.c .gpio_audio_input = { .mask = 0x7, mask 81 drivers/media/pci/cx18/cx18-cards.h u32 mask; /* leave to 0 if not supported */ mask 55 drivers/media/pci/cx18/cx18-gpio.c static void gpio_update(struct cx18 *cx, u32 mask, u32 data) mask 57 drivers/media/pci/cx18/cx18-gpio.c if (mask == 0) mask 61 drivers/media/pci/cx18/cx18-gpio.c cx->gpio_val = (cx->gpio_val & ~mask) | (data & mask); mask 70 drivers/media/pci/cx18/cx18-gpio.c u32 mask; mask 72 drivers/media/pci/cx18/cx18-gpio.c mask = active_lo | active_hi; mask 73 drivers/media/pci/cx18/cx18-gpio.c if (mask == 0) mask 83 drivers/media/pci/cx18/cx18-gpio.c gpio_update(cx, mask, ~active_lo); mask 87 drivers/media/pci/cx18/cx18-gpio.c gpio_update(cx, mask, ~active_hi); mask 114 drivers/media/pci/cx18/cx18-gpio.c gpio_update(cx, cx->card->gpio_audio_input.mask, mask 140 drivers/media/pci/cx18/cx18-gpio.c gpio_update(cx, cx->card->gpio_audio_input.mask, data); mask 163 drivers/media/pci/cx18/cx18-gpio.c gpio_update(cx, cx->card->gpio_audio_input.mask, data); mask 69 drivers/media/pci/cx18/cx18-io.h u32 eval, u32 mask) mask 73 drivers/media/pci/cx18/cx18-io.h eval &= mask; mask 79 drivers/media/pci/cx18/cx18-io.h if (eval == (r & mask)) mask 148 drivers/media/pci/cx18/cx18-io.h u32 eval, u32 mask) mask 150 drivers/media/pci/cx18/cx18-io.h cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask); mask 621 drivers/media/pci/cx23885/cx23885-417.c void mc417_gpio_set(struct cx23885_dev *dev, u32 mask) mask 627 drivers/media/pci/cx23885/cx23885-417.c val |= (mask & 0x000ffff); mask 631 drivers/media/pci/cx23885/cx23885-417.c void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask) mask 637 drivers/media/pci/cx23885/cx23885-417.c val &= ~(mask & 0x0000ffff); mask 641 drivers/media/pci/cx23885/cx23885-417.c void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) mask 648 drivers/media/pci/cx23885/cx23885-417.c val |= (mask & 0x0000ffff); mask 650 drivers/media/pci/cx23885/cx23885-417.c val &= ~(mask & 0x0000ffff); mask 226 drivers/media/pci/cx23885/cx23885-alsa.c int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask) mask 230 drivers/media/pci/cx23885/cx23885-alsa.c if (0 == (status & mask)) mask 307 drivers/media/pci/cx23885/cx23885-core.c static void cx23885_irq_add(struct cx23885_dev *dev, u32 mask) mask 312 drivers/media/pci/cx23885/cx23885-core.c dev->pci_irqmask |= mask; mask 317 drivers/media/pci/cx23885/cx23885-core.c void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask) mask 322 drivers/media/pci/cx23885/cx23885-core.c dev->pci_irqmask |= mask; mask 323 drivers/media/pci/cx23885/cx23885-core.c cx_set(PCI_INT_MSK, mask); mask 328 drivers/media/pci/cx23885/cx23885-core.c void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask) mask 334 drivers/media/pci/cx23885/cx23885-core.c v = mask & dev->pci_irqmask; mask 346 drivers/media/pci/cx23885/cx23885-core.c void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask) mask 351 drivers/media/pci/cx23885/cx23885-core.c cx_clear(PCI_INT_MSK, mask); mask 361 drivers/media/pci/cx23885/cx23885-core.c void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask) mask 366 drivers/media/pci/cx23885/cx23885-core.c dev->pci_irqmask &= ~mask; mask 367 drivers/media/pci/cx23885/cx23885-core.c cx_clear(PCI_INT_MSK, mask); mask 1993 drivers/media/pci/cx23885/cx23885-core.c void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask) mask 1995 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x7) mask 1996 drivers/media/pci/cx23885/cx23885-core.c cx_set(GP0_IO, mask & 0x7); mask 1998 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x0007fff8) { mask 2002 drivers/media/pci/cx23885/cx23885-core.c cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3); mask 2006 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x00f80000) mask 2010 drivers/media/pci/cx23885/cx23885-core.c void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask) mask 2012 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x00000007) mask 2013 drivers/media/pci/cx23885/cx23885-core.c cx_clear(GP0_IO, mask & 0x7); mask 2015 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x0007fff8) { mask 2019 drivers/media/pci/cx23885/cx23885-core.c cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3); mask 2023 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x00f80000) mask 2027 drivers/media/pci/cx23885/cx23885-core.c u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask) mask 2029 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x00000007) mask 2030 drivers/media/pci/cx23885/cx23885-core.c return (cx_read(GP0_IO) >> 8) & mask & 0x7; mask 2032 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x0007fff8) { mask 2036 drivers/media/pci/cx23885/cx23885-core.c return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3; mask 2040 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x00f80000) mask 2046 drivers/media/pci/cx23885/cx23885-core.c void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput) mask 2048 drivers/media/pci/cx23885/cx23885-core.c if ((mask & 0x00000007) && asoutput) mask 2049 drivers/media/pci/cx23885/cx23885-core.c cx_set(GP0_IO, (mask & 0x7) << 16); mask 2050 drivers/media/pci/cx23885/cx23885-core.c else if ((mask & 0x00000007) && !asoutput) mask 2051 drivers/media/pci/cx23885/cx23885-core.c cx_clear(GP0_IO, (mask & 0x7) << 16); mask 2053 drivers/media/pci/cx23885/cx23885-core.c if (mask & 0x0007fff8) { mask 2060 drivers/media/pci/cx23885/cx23885-core.c if ((mask & 0x0007fff8) && asoutput) mask 2061 drivers/media/pci/cx23885/cx23885-core.c cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3); mask 2063 drivers/media/pci/cx23885/cx23885-core.c else if ((mask & 0x0007fff8) && !asoutput) mask 2064 drivers/media/pci/cx23885/cx23885-core.c cx_set(MC417_OEN, (mask & 0x7fff8) >> 3); mask 1049 drivers/media/pci/cx23885/cx23885-video.c u32 mask, count; mask 1052 drivers/media/pci/cx23885/cx23885-video.c mask = cx_read(VID_A_INT_MSK); mask 1053 drivers/media/pci/cx23885/cx23885-video.c if (0 == (status & mask)) mask 499 drivers/media/pci/cx23885/cx23885.h #define cx_andor(reg, mask, value) \ mask 500 drivers/media/pci/cx23885/cx23885.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ mask 501 drivers/media/pci/cx23885/cx23885.h ((value) & (mask)), dev->lmmio+((reg)>>2)) mask 532 drivers/media/pci/cx23885/cx23885.h extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask); mask 533 drivers/media/pci/cx23885/cx23885.h extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask); mask 534 drivers/media/pci/cx23885/cx23885.h extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask); mask 535 drivers/media/pci/cx23885/cx23885.h extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, mask 538 drivers/media/pci/cx23885/cx23885.h extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask); mask 539 drivers/media/pci/cx23885/cx23885.h extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask); mask 540 drivers/media/pci/cx23885/cx23885.h extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask); mask 541 drivers/media/pci/cx23885/cx23885.h extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask); mask 611 drivers/media/pci/cx23885/cx23885.h extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask); mask 612 drivers/media/pci/cx23885/cx23885.h extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask); mask 613 drivers/media/pci/cx23885/cx23885.h extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); mask 620 drivers/media/pci/cx23885/cx23885.h extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask); mask 504 drivers/media/pci/cx23885/cx23888-ir.c static inline void irqenable_rx(struct cx23885_dev *dev, u32 mask) mask 506 drivers/media/pci/cx23885/cx23888-ir.c mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE); mask 508 drivers/media/pci/cx23885/cx23888-ir.c ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask); mask 511 drivers/media/pci/cx23885/cx23888-ir.c static inline void irqenable_tx(struct cx23885_dev *dev, u32 mask) mask 513 drivers/media/pci/cx23885/cx23888-ir.c mask &= IRQEN_TSE; mask 514 drivers/media/pci/cx23885/cx23888-ir.c cx23888_ir_and_or4(dev, CX23888_IR_IRQEN_REG, ~IRQEN_TSE, mask); mask 313 drivers/media/pci/cx25821/cx25821-alsa.c u32 mask) mask 317 drivers/media/pci/cx25821/cx25821-alsa.c if (0 == (status & mask)) mask 321 drivers/media/pci/cx25821/cx25821-alsa.c if (debug > 1 || (status & mask & ~0xff)) mask 323 drivers/media/pci/cx25821/cx25821-alsa.c ARRAY_SIZE(cx25821_aud_irqs), status, mask); mask 1215 drivers/media/pci/cx25821/cx25821-core.c u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; mask 1223 drivers/media/pci/cx25821/cx25821-core.c if (pci_status & mask[i]) { mask 1231 drivers/media/pci/cx25821/cx25821-core.c cx_write(PCI_INT_STAT, mask[i]); mask 1240 drivers/media/pci/cx25821/cx25821-core.c int len, u32 bits, u32 mask) mask 1253 drivers/media/pci/cx25821/cx25821-core.c if (!(mask & (1 << i))) mask 88 drivers/media/pci/cx25821/cx25821-video.c u32 mask; mask 91 drivers/media/pci/cx25821/cx25821-video.c mask = cx_read(channel->int_msk); mask 92 drivers/media/pci/cx25821/cx25821-video.c if (0 == (status & mask)) mask 354 drivers/media/pci/cx25821/cx25821.h #define cx_andor(reg, mask, value) \ mask 355 drivers/media/pci/cx25821/cx25821.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ mask 356 drivers/media/pci/cx25821/cx25821.h ((value) & (mask)), dev->lmmio+((reg)>>2)) mask 418 drivers/media/pci/cx25821/cx25821.h int len, u32 bits, u32 mask); mask 209 drivers/media/pci/cx88/cx88-alsa.c u32 status, mask; mask 212 drivers/media/pci/cx88/cx88-alsa.c mask = cx_read(MO_AUD_INTMSK); mask 213 drivers/media/pci/cx88/cx88-alsa.c if (0 == (status & mask)) mask 216 drivers/media/pci/cx88/cx88-alsa.c if (debug > 1 || (status & mask & ~0xff)) mask 219 drivers/media/pci/cx88/cx88-alsa.c status, mask); mask 480 drivers/media/pci/cx88/cx88-core.c int len, u32 bits, u32 mask) mask 492 drivers/media/pci/cx88/cx88-core.c if (!(mask & (1 << i))) mask 304 drivers/media/pci/cx88/cx88-mpeg.c u32 status, mask, count; mask 308 drivers/media/pci/cx88/cx88-mpeg.c mask = cx_read(MO_TS_INTMSK); mask 309 drivers/media/pci/cx88/cx88-mpeg.c if (0 == (status & mask)) mask 314 drivers/media/pci/cx88/cx88-mpeg.c if (debug || (status & mask & ~0xff)) mask 317 drivers/media/pci/cx88/cx88-mpeg.c status, mask); mask 884 drivers/media/pci/cx88/cx88-tvaudio.c u32 mask = UNSET; mask 941 drivers/media/pci/cx88/cx88-tvaudio.c mask = 0x3f; mask 962 drivers/media/pci/cx88/cx88-tvaudio.c mask = 0x3f; mask 966 drivers/media/pci/cx88/cx88-tvaudio.c mask = 0x3f; mask 980 drivers/media/pci/cx88/cx88-tvaudio.c mask, ctl, cx_read(AUD_STATUS), mask 982 drivers/media/pci/cx88/cx88-tvaudio.c cx_andor(AUD_CTL, mask, ctl); mask 149 drivers/media/pci/cx88/cx88-video.c u32 mask; mask 163 drivers/media/pci/cx88/cx88-video.c .mask = 0x00ff, mask 173 drivers/media/pci/cx88/cx88-video.c .mask = 0xff00, mask 183 drivers/media/pci/cx88/cx88-video.c .mask = 0x00ff, mask 196 drivers/media/pci/cx88/cx88-video.c .mask = 0x00ff, mask 210 drivers/media/pci/cx88/cx88-video.c .mask = 7 << 7, mask 218 drivers/media/pci/cx88/cx88-video.c .mask = 1 << 10, mask 226 drivers/media/pci/cx88/cx88-video.c .mask = 1 << 9, mask 236 drivers/media/pci/cx88/cx88-video.c .mask = 3 << 11, mask 250 drivers/media/pci/cx88/cx88-video.c .mask = (1 << 6), mask 260 drivers/media/pci/cx88/cx88-video.c .mask = 0x3f, mask 270 drivers/media/pci/cx88/cx88-video.c .mask = 0x7f, mask 612 drivers/media/pci/cx88/cx88-video.c u32 value, mask; mask 614 drivers/media/pci/cx88/cx88-video.c mask = cc->mask; mask 619 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; mask 628 drivers/media/pci/cx88/cx88-video.c mask = 0xffff; mask 634 drivers/media/pci/cx88/cx88-video.c cx_andor(MO_FILTER_EVEN, mask, value); mask 637 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; mask 640 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; mask 646 drivers/media/pci/cx88/cx88-video.c mask, cc->sreg ? " [shadowed]" : ""); mask 648 drivers/media/pci/cx88/cx88-video.c cx_sandor(cc->sreg, cc->reg, mask, value); mask 650 drivers/media/pci/cx88/cx88-video.c cx_andor(cc->reg, mask, value); mask 659 drivers/media/pci/cx88/cx88-video.c u32 value, mask; mask 679 drivers/media/pci/cx88/cx88-video.c mask = cc->mask; mask 689 drivers/media/pci/cx88/cx88-video.c value = ((ctrl->val - cc->off) << cc->shift) & cc->mask; mask 695 drivers/media/pci/cx88/cx88-video.c mask, cc->sreg ? " [shadowed]" : ""); mask 697 drivers/media/pci/cx88/cx88-video.c cx_sandor(cc->sreg, cc->reg, mask, value); mask 699 drivers/media/pci/cx88/cx88-video.c cx_andor(cc->reg, mask, value); mask 1065 drivers/media/pci/cx88/cx88-video.c u32 status, mask, count; mask 1068 drivers/media/pci/cx88/cx88-video.c mask = cx_read(MO_VID_INTMSK); mask 1069 drivers/media/pci/cx88/cx88-video.c if (0 == (status & mask)) mask 1072 drivers/media/pci/cx88/cx88-video.c if (irq_debug || (status & mask & ~0xff)) mask 1075 drivers/media/pci/cx88/cx88-video.c status, mask); mask 587 drivers/media/pci/cx88/cx88.h #define cx_andor(reg, mask, value) \ mask 588 drivers/media/pci/cx88/cx88.h writel((readl(core->lmmio + ((reg) >> 2)) & ~(mask)) |\ mask 589 drivers/media/pci/cx88/cx88.h ((value) & (mask)), core->lmmio + ((reg) >> 2)) mask 600 drivers/media/pci/cx88/cx88.h #define cx_sandor(sreg, reg, mask, value) \ mask 601 drivers/media/pci/cx88/cx88.h (core->shadow[sreg] = (core->shadow[sreg] & ~(mask)) | \ mask 602 drivers/media/pci/cx88/cx88.h ((value) & (mask)), \ mask 612 drivers/media/pci/cx88/cx88.h int len, u32 bits, u32 mask); mask 180 drivers/media/pci/ddbridge/ddbridge-ci.c static int write_creg(struct ddb_ci *ci, u8 data, u8 mask) mask 185 drivers/media/pci/ddbridge/ddbridge-ci.c ci->port->creg = (ci->port->creg & ~mask) | data; mask 780 drivers/media/pci/ddbridge/ddbridge-core.c __poll_t mask = 0; mask 785 drivers/media/pci/ddbridge/ddbridge-core.c mask |= EPOLLIN | EPOLLRDNORM; mask 787 drivers/media/pci/ddbridge/ddbridge-core.c mask |= EPOLLOUT | EPOLLWRNORM; mask 788 drivers/media/pci/ddbridge/ddbridge-core.c return mask; mask 2521 drivers/media/pci/ddbridge/ddbridge-core.c u32 mask = 0x8fffff00; mask 2522 drivers/media/pci/ddbridge/ddbridge-core.c u32 s = mask & ddbreadl(dev, INTERRUPT_STATUS); mask 2531 drivers/media/pci/ddbridge/ddbridge-core.c } while ((s = mask & ddbreadl(dev, INTERRUPT_STATUS))); mask 2539 drivers/media/pci/ddbridge/ddbridge-core.c u32 mask = 0x8000000f; mask 2540 drivers/media/pci/ddbridge/ddbridge-core.c u32 s = mask & ddbreadl(dev, INTERRUPT_STATUS); mask 2549 drivers/media/pci/ddbridge/ddbridge-core.c } while ((s = mask & ddbreadl(dev, INTERRUPT_STATUS))); mask 130 drivers/media/pci/ddbridge/ddbridge-max.c u32 mask = (1ULL << input); mask 134 drivers/media/pci/ddbridge/ddbridge-max.c if (!(dev->link[link].lnb.tone & mask)) mask 139 drivers/media/pci/ddbridge/ddbridge-max.c if (dev->link[link].lnb.tone & mask) mask 375 drivers/media/pci/ddbridge/ddbridge-sx8.c u32 mask; mask 390 drivers/media/pci/ddbridge/ddbridge-sx8.c mask = 0x0f; mask 393 drivers/media/pci/ddbridge/ddbridge-sx8.c mask = 0x07; mask 396 drivers/media/pci/ddbridge/ddbridge-sx8.c mask = 0x03; mask 399 drivers/media/pci/ddbridge/ddbridge-sx8.c stat = start(fe, 3, mask, ts_config); mask 198 drivers/media/pci/dm1105/dm1105.c u32 mask, off, v13, v18; mask 213 drivers/media/pci/dm1105/dm1105.c .mask = DM1105_LNB_MASK, mask 222 drivers/media/pci/dm1105/dm1105.c .mask = DM1105_LNB_MASK, mask 231 drivers/media/pci/dm1105/dm1105.c .mask = DM1105_LNB_MASK, mask 240 drivers/media/pci/dm1105/dm1105.c .mask = DM05_LNB_MASK, mask 249 drivers/media/pci/dm1105/dm1105.c .mask = UNBR_LNB_MASK, mask 370 drivers/media/pci/dm1105/dm1105.c #define dm_andorl(reg, mask, value) \ mask 371 drivers/media/pci/dm1105/dm1105.c outl((inl(dm_io_mem(reg)) & ~(mask)) |\ mask 372 drivers/media/pci/dm1105/dm1105.c ((value) & (mask)), (dm_io_mem(reg))) mask 381 drivers/media/pci/dm1105/dm1105.c static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask) mask 383 drivers/media/pci/dm1105/dm1105.c if (mask & 0xfffc0000) mask 386 drivers/media/pci/dm1105/dm1105.c if (mask & 0x0003ffff) mask 387 drivers/media/pci/dm1105/dm1105.c dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff); mask 391 drivers/media/pci/dm1105/dm1105.c static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask) mask 393 drivers/media/pci/dm1105/dm1105.c if (mask & 0xfffc0000) mask 396 drivers/media/pci/dm1105/dm1105.c if (mask & 0x0003ffff) mask 397 drivers/media/pci/dm1105/dm1105.c dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff); mask 401 drivers/media/pci/dm1105/dm1105.c static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val) mask 403 drivers/media/pci/dm1105/dm1105.c if (mask & 0xfffc0000) mask 406 drivers/media/pci/dm1105/dm1105.c if (mask & 0x0003ffff) mask 407 drivers/media/pci/dm1105/dm1105.c dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val); mask 411 drivers/media/pci/dm1105/dm1105.c static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask) mask 413 drivers/media/pci/dm1105/dm1105.c if (mask & 0xfffc0000) mask 416 drivers/media/pci/dm1105/dm1105.c if (mask & 0x0003ffff) mask 417 drivers/media/pci/dm1105/dm1105.c return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff; mask 422 drivers/media/pci/dm1105/dm1105.c static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput) mask 424 drivers/media/pci/dm1105/dm1105.c if (mask & 0xfffc0000) mask 427 drivers/media/pci/dm1105/dm1105.c if ((mask & 0x0003ffff) && asoutput) mask 428 drivers/media/pci/dm1105/dm1105.c dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff); mask 429 drivers/media/pci/dm1105/dm1105.c else if ((mask & 0x0003ffff) && !asoutput) mask 430 drivers/media/pci/dm1105/dm1105.c dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff); mask 584 drivers/media/pci/dm1105/dm1105.c dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1); mask 587 drivers/media/pci/dm1105/dm1105.c dm1105_boards[dev->boardnr].lnb.mask, mask 591 drivers/media/pci/dm1105/dm1105.c dm1105_boards[dev->boardnr].lnb.mask, mask 595 drivers/media/pci/dm1105/dm1105.c dm1105_boards[dev->boardnr].lnb.mask, mask 244 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x8040, .tuner = 0x8000, .linein = 0x0000 }, mask 245 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x2000, .mute = 0x2000 }, mask 246 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x4300, .mono = 0x4000, .stereo = 0x0200, mask 248 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_freq = { .mask = 0x0018, .f32000 = 0x0000, mask 250 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_detect = { .mask = 0x4000, .stereo = 0x0000 }, mask 287 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x3000, .tuner = 0x0000, .linein = 0x2000 }, mask 288 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x0001, .mute = 0x0001 }, mask 289 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x000e, .mono = 0x0006, .stereo = 0x0004, mask 291 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_detect = { .mask = 0x0900, .stereo = 0x0100 }, mask 329 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x3000, .tuner = 0x0000, .linein = 0x2000 }, mask 330 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x0001, .mute = 0x0001 }, mask 331 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x000e, .mono = 0x0006, .stereo = 0x0004, mask 333 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_detect = { .mask = 0x0900, .stereo = 0x0100 }, mask 480 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x8080, .tuner = 0x8000, .linein = 0x0080 }, mask 481 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x6000, .mute = 0x6000 }, mask 482 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x4300, .mono = 0x4000, .stereo = 0x0200, mask 484 drivers/media/pci/ivtv/ivtv-cards.c .gpio_video_input = { .mask = 0x0030, .tuner = 0x0000, mask 557 drivers/media/pci/ivtv/ivtv-cards.c .gpio_video_input = { .mask = 0x0020, .tuner = 0x0000, mask 559 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_freq = { .mask = 0xc000, .f32000 = 0x0000, mask 589 drivers/media/pci/ivtv/ivtv-cards.c .gpio_video_input = { .mask = 0x0020, .tuner = 0x0000, mask 591 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_freq = { .mask = 0xc000, .f32000 = 0x0000, mask 619 drivers/media/pci/ivtv/ivtv-cards.c .gpio_video_input = { .mask = 0x0020, .tuner = 0x0000, mask 621 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_freq = { .mask = 0xc000, .f32000 = 0x0000, mask 661 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0xffff, .tuner = 0x0200, .linein = 0x0300 }, mask 698 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0xffff, .tuner = 0x0200, .linein = 0x0300 }, mask 772 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x0800, .tuner = 0, .linein = 0, .radio = 0x0800 }, mask 846 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x8080, .tuner = 0x8000, .linein = 0x0080 }, mask 847 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x6000, .mute = 0x6000 }, mask 848 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x4300, .mono = 0x4000, .stereo = 0x0200, mask 850 drivers/media/pci/ivtv/ivtv-cards.c .gpio_video_input = { .mask = 0x0030, .tuner = 0x0000, mask 1004 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0xc000, mask 1050 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0xc000, mask 1229 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_input = { .mask = 0x0060, mask 1233 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mute = { .mask = 0x0000, mask 1235 drivers/media/pci/ivtv/ivtv-cards.c .gpio_audio_mode = { .mask = 0x0080, mask 195 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 202 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 209 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 214 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 223 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 230 drivers/media/pci/ivtv/ivtv-cards.h u16 mask; /* leave to 0 if not supported */ mask 314 drivers/media/pci/ivtv/ivtv-driver.c void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask) mask 316 drivers/media/pci/ivtv/ivtv-driver.c itv->irqmask &= ~mask; mask 320 drivers/media/pci/ivtv/ivtv-driver.c void ivtv_set_irq_mask(struct ivtv *itv, u32 mask) mask 322 drivers/media/pci/ivtv/ivtv-driver.c itv->irqmask |= mask; mask 774 drivers/media/pci/ivtv/ivtv-driver.h void ivtv_set_irq_mask(struct ivtv *itv, u32 mask); mask 775 drivers/media/pci/ivtv/ivtv-driver.h void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask); mask 149 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 151 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_freq.mask; mask 164 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 165 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); mask 172 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask; mask 174 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_detect.mask; mask 175 drivers/media/pci/ivtv/ivtv-gpio.c if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) mask 186 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 188 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_mode.mask; mask 205 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 206 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); mask 213 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 215 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_input.mask; mask 217 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 218 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); mask 226 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 230 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_input.mask; mask 243 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 244 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); mask 252 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 256 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_audio_mute.mask; mask 258 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 259 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | mask 260 drivers/media/pci/ivtv/ivtv-gpio.c (data & mask), IVTV_REG_GPIO_OUT); mask 282 drivers/media/pci/ivtv/ivtv-gpio.c u16 mask, data; mask 286 drivers/media/pci/ivtv/ivtv-gpio.c mask = itv->card->gpio_video_input.mask; mask 293 drivers/media/pci/ivtv/ivtv-gpio.c if (mask) mask 294 drivers/media/pci/ivtv/ivtv-gpio.c write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); mask 56 drivers/media/pci/mantis/hopper_cards.c u32 stat = 0, mask = 0; mask 70 drivers/media/pci/mantis/hopper_cards.c mask = mmread(MANTIS_INT_MASK); mask 71 drivers/media/pci/mantis/hopper_cards.c if (!(stat & mask)) mask 84 drivers/media/pci/mantis/hopper_cards.c mantis->mantis_int_mask = mask; mask 85 drivers/media/pci/mantis/hopper_cards.c dprintk(MANTIS_DEBUG, 0, "\n-- Stat=<%02x> Mask=<%02x> --", stat, mask); mask 140 drivers/media/pci/mantis/hopper_cards.c dprintk(MANTIS_DEBUG, 0, "<Unknown> Stat=<%02x> Mask=<%02x>", stat, mask); mask 65 drivers/media/pci/mantis/mantis_cards.c u32 stat = 0, mask = 0; mask 79 drivers/media/pci/mantis/mantis_cards.c mask = mmread(MANTIS_INT_MASK); mask 80 drivers/media/pci/mantis/mantis_cards.c if (!(stat & mask)) mask 93 drivers/media/pci/mantis/mantis_cards.c mantis->mantis_int_mask = mask; mask 94 drivers/media/pci/mantis/mantis_cards.c dprintk(MANTIS_DEBUG, 0, "\n-- Stat=<%02x> Mask=<%02x> --", stat, mask); mask 149 drivers/media/pci/mantis/mantis_cards.c dprintk(MANTIS_DEBUG, 0, "<Unknown> Stat=<%02x> Mask=<%02x>", stat, mask); mask 174 drivers/media/pci/mantis/mantis_common.h static inline void mantis_mask_ints(struct mantis_pci *mantis, u32 mask) mask 179 drivers/media/pci/mantis/mantis_common.h mmwrite(mmread(MANTIS_INT_MASK) & ~mask, MANTIS_INT_MASK); mask 183 drivers/media/pci/mantis/mantis_common.h static inline void mantis_unmask_ints(struct mantis_pci *mantis, u32 mask) mask 188 drivers/media/pci/mantis/mantis_common.h mmwrite(mmread(MANTIS_INT_MASK) | mask, MANTIS_INT_MASK); mask 418 drivers/media/pci/meye/meye.c u32 mask = (reg < 0x100) ? MCHIP_HIC_STATUS_MCC_RDY mask 422 drivers/media/pci/meye/meye.c if (status & mask) mask 144 drivers/media/pci/netup_unidvb/netup_unidvb_core.c u8 reg, mask; mask 154 drivers/media/pci/netup_unidvb/netup_unidvb_core.c mask = (dma->num == 0) ? GPIO_RFA_CTL : GPIO_RFB_CTL; mask 161 drivers/media/pci/netup_unidvb/netup_unidvb_core.c reg |= mask; mask 163 drivers/media/pci/netup_unidvb/netup_unidvb_core.c reg &= ~mask; mask 84 drivers/media/pci/ngene/ngene-dvb.c __poll_t mask = 0; mask 90 drivers/media/pci/ngene/ngene-dvb.c mask |= EPOLLIN | EPOLLRDNORM; mask 92 drivers/media/pci/ngene/ngene-dvb.c mask |= EPOLLOUT | EPOLLWRNORM; mask 94 drivers/media/pci/ngene/ngene-dvb.c return mask; mask 135 drivers/media/pci/pluto2/pluto2.c static inline void pluto_rw(struct pluto *pluto, u32 reg, u32 mask, u32 bits) mask 138 drivers/media/pci/pluto2/pluto2.c val &= ~mask; mask 77 drivers/media/pci/pt3/pt3_i2c.c u8 mask; mask 79 drivers/media/pci/pt3/pt3_i2c.c for (mask = 0x80; mask > 0; mask >>= 1) mask 80 drivers/media/pci/pt3/pt3_i2c.c cmdbuf_add(cbuf, (val & mask) ? I_DATA_H_NOP : I_DATA_L_NOP); mask 176 drivers/media/pci/saa7134/saa7134-tvaudio.c int mask; mask 233 drivers/media/pci/saa7134/saa7134-tvaudio.c mask = card(dev).gpiomask; mask 234 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask); mask 235 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, in->gpio); mask 714 drivers/media/pci/saa7134/saa7134-tvaudio.c int mask; mask 744 drivers/media/pci/saa7134/saa7134-tvaudio.c mask = card(dev).gpiomask; mask 751 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, mask, mask); mask 752 drivers/media/pci/saa7134/saa7134-tvaudio.c saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, mask, in->gpio); mask 692 drivers/media/pci/saa7134/saa7134.h #define saa_andorl(reg,mask,value) \ mask 693 drivers/media/pci/saa7134/saa7134.h writel((readl(dev->lmmio+(reg)) & ~(mask)) |\ mask 694 drivers/media/pci/saa7134/saa7134.h ((value) & (mask)), dev->lmmio+(reg)) mask 700 drivers/media/pci/saa7134/saa7134.h #define saa_andorb(reg,mask,value) \ mask 701 drivers/media/pci/saa7134/saa7134.h writeb((readb(dev->bmmio+(reg)) & ~(mask)) |\ mask 702 drivers/media/pci/saa7134/saa7134.h ((value) & (mask)), dev->bmmio+(reg)) mask 900 drivers/media/pci/saa7164/saa7164-encoder.c __poll_t mask = v4l2_ctrl_poll(file, wait); mask 911 drivers/media/pci/saa7164/saa7164-encoder.c return mask; mask 916 drivers/media/pci/saa7164/saa7164-encoder.c return mask | EPOLLERR; mask 924 drivers/media/pci/saa7164/saa7164-encoder.c mask |= EPOLLIN | EPOLLRDNORM; mask 926 drivers/media/pci/saa7164/saa7164-encoder.c return mask; mask 604 drivers/media/pci/saa7164/saa7164-vbi.c __poll_t mask = 0; mask 636 drivers/media/pci/saa7164/saa7164-vbi.c mask |= EPOLLIN | EPOLLRDNORM; mask 638 drivers/media/pci/saa7164/saa7164-vbi.c return mask; mask 298 drivers/media/pci/smipcie/smipcie.h #define smi_andor(reg, mask, value) \ mask 299 drivers/media/pci/smipcie/smipcie.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ mask 300 drivers/media/pci/smipcie/smipcie.h ((value) & (mask)), dev->lmmio+((reg)>>2)) mask 227 drivers/media/pci/solo6x10/solo6x10-regs.h #define SOLO_VI_MOTION_EN(mask) ((mask)<<16) mask 120 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c u32 mask = 1 << solo_enc->ch; mask 126 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_dev->motion_mask |= mask; mask 128 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_dev->motion_mask &= ~mask; mask 130 drivers/media/pci/solo6x10/solo6x10-v4l2-enc.c solo_reg_write(solo_dev, SOLO_VI_MOT_CLEAR, mask); mask 289 drivers/media/pci/solo6x10/solo6x10.h static inline void solo_irq_on(struct solo_dev *dev, u32 mask) mask 291 drivers/media/pci/solo6x10/solo6x10.h dev->irq_mask |= mask; mask 295 drivers/media/pci/solo6x10/solo6x10.h static inline void solo_irq_off(struct solo_dev *dev, u32 mask) mask 297 drivers/media/pci/solo6x10/solo6x10.h dev->irq_mask &= ~mask; mask 929 drivers/media/pci/ttpci/av7110_av.c __poll_t mask = 0; mask 939 drivers/media/pci/ttpci/av7110_av.c mask = EPOLLPRI; mask 944 drivers/media/pci/ttpci/av7110_av.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 947 drivers/media/pci/ttpci/av7110_av.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 951 drivers/media/pci/ttpci/av7110_av.c return mask; mask 981 drivers/media/pci/ttpci/av7110_av.c __poll_t mask = 0; mask 989 drivers/media/pci/ttpci/av7110_av.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 991 drivers/media/pci/ttpci/av7110_av.c mask = (EPOLLOUT | EPOLLWRNORM); mask 993 drivers/media/pci/ttpci/av7110_av.c return mask; mask 218 drivers/media/pci/ttpci/av7110_ca.c __poll_t mask = 0; mask 226 drivers/media/pci/ttpci/av7110_ca.c mask |= (EPOLLIN | EPOLLRDNORM); mask 229 drivers/media/pci/ttpci/av7110_ca.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 231 drivers/media/pci/ttpci/av7110_ca.c return mask; mask 167 drivers/media/pci/tw5864/tw5864.h #define tw_mask_readl(reg, mask) \ mask 168 drivers/media/pci/tw5864/tw5864.h (tw_readl(reg) & (mask)) mask 169 drivers/media/pci/tw5864/tw5864.h #define tw_mask_shift_readl(reg, mask, shift) \ mask 170 drivers/media/pci/tw5864/tw5864.h (tw_mask_readl((reg), ((mask) << (shift))) >> (shift)) mask 173 drivers/media/pci/tw5864/tw5864.h #define tw_mask_writel(reg, mask, value) \ mask 174 drivers/media/pci/tw5864/tw5864.h tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask))) mask 175 drivers/media/pci/tw5864/tw5864.h #define tw_mask_shift_writel(reg, mask, shift, value) \ mask 176 drivers/media/pci/tw5864/tw5864.h tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift))) mask 172 drivers/media/pci/tw68/tw68.h #define tw_andorl(reg, mask, value) \ mask 173 drivers/media/pci/tw68/tw68.h writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ mask 174 drivers/media/pci/tw68/tw68.h ((value) & (mask)), dev->lmmio+((reg)>>2)) mask 175 drivers/media/pci/tw68/tw68.h #define tw_andorb(reg, mask, value) \ mask 176 drivers/media/pci/tw68/tw68.h writeb((readb(dev->bmmio + (reg)) & ~(mask)) |\ mask 177 drivers/media/pci/tw68/tw68.h ((value) & (mask)), dev->bmmio+(reg)) mask 366 drivers/media/pci/tw686x/tw686x-video.c unsigned long mask; mask 371 drivers/media/pci/tw686x/tw686x-video.c mask = GENMASK(max_fps - 1, 0); mask 372 drivers/media/pci/tw686x/tw686x-video.c return hweight_long(fps_map[index] & mask); mask 1504 drivers/media/platform/aspeed-video.c const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) | mask 1529 drivers/media/platform/aspeed-video.c V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask, mask 728 drivers/media/platform/atmel/atmel-isc-base.c u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; mask 739 drivers/media/platform/atmel/atmel-isc-base.c mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | mask 744 drivers/media/platform/atmel/atmel-isc-base.c regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); mask 214 drivers/media/platform/atmel/atmel-isi.c u32 status, mask, pending; mask 220 drivers/media/platform/atmel/atmel-isi.c mask = isi_readl(isi, ISI_INTMASK); mask 221 drivers/media/platform/atmel/atmel-isi.c pending = status & mask; mask 155 drivers/media/platform/coda/coda-bit.c kfifo->out = (kfifo->in & ~kfifo->mask) | mask 158 drivers/media/platform/coda/coda-bit.c kfifo->out -= kfifo->mask + 1; mask 167 drivers/media/platform/coda/coda-bit.c rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask); mask 169 drivers/media/platform/coda/coda-bit.c wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask); mask 179 drivers/media/platform/coda/coda-bit.c wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask); mask 100 drivers/media/platform/coda/trace.h __entry->start = meta->start & ctx->bitstream_fifo.kfifo.mask; mask 101 drivers/media/platform/coda/trace.h __entry->end = meta->end & ctx->bitstream_fifo.kfifo.mask; mask 131 drivers/media/platform/coda/trace.h ctx->bitstream_fifo.kfifo.mask) : 0; mask 133 drivers/media/platform/coda/trace.h ctx->bitstream_fifo.kfifo.mask) : 0; mask 147 drivers/media/platform/davinci/isif.c static inline u32 reg_modify(u32 mask, u32 val, u32 offset) mask 149 drivers/media/platform/davinci/isif.c u32 new_val = (regr(offset) & ~mask) | (val & mask); mask 64 drivers/media/platform/davinci/vpbe_osd.c static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset) mask 69 drivers/media/platform/davinci/vpbe_osd.c u32 val = readl(addr) | mask; mask 76 drivers/media/platform/davinci/vpbe_osd.c static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset) mask 81 drivers/media/platform/davinci/vpbe_osd.c u32 val = readl(addr) & ~mask; mask 88 drivers/media/platform/davinci/vpbe_osd.c static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val, mask 94 drivers/media/platform/davinci/vpbe_osd.c u32 new_val = (readl(addr) & ~mask) | (val & mask); mask 87 drivers/media/platform/davinci/vpbe_venc.c u32 val, u32 mask) mask 89 drivers/media/platform/davinci/vpbe_venc.c u32 new_val = (venc_read(sd, offset) & ~mask) | (val & mask); mask 495 drivers/media/platform/davinci/vpif.h u32 mask; mask 498 drivers/media/platform/davinci/vpif.h mask = VPIF_CH_VANC_EN_BIT; mask 500 drivers/media/platform/davinci/vpif.h mask = VPIF_CH_HANC_EN_BIT; mask 503 drivers/media/platform/davinci/vpif.h vpif_set_bit(VPIF_CH2_CTRL, mask); mask 505 drivers/media/platform/davinci/vpif.h vpif_clr_bit(VPIF_CH2_CTRL, mask); mask 511 drivers/media/platform/davinci/vpif.h u32 mask; mask 514 drivers/media/platform/davinci/vpif.h mask = VPIF_CH_VANC_EN_BIT; mask 516 drivers/media/platform/davinci/vpif.h mask = VPIF_CH_HANC_EN_BIT; mask 519 drivers/media/platform/davinci/vpif.h vpif_set_bit(VPIF_CH3_CTRL, mask); mask 521 drivers/media/platform/davinci/vpif.h vpif_clr_bit(VPIF_CH3_CTRL, mask); mask 605 drivers/media/platform/davinci/vpif.h int mask; mask 610 drivers/media/platform/davinci/vpif.h mask = 1 << channel; mask 611 drivers/media/platform/davinci/vpif.h status = regr(VPIF_STATUS) & mask; mask 188 drivers/media/platform/davinci/vpss.c u32 mask = 1, val; mask 195 drivers/media/platform/davinci/vpss.c mask = ~(mask << wbl_sel); mask 196 drivers/media/platform/davinci/vpss.c val = bl_regr(DM644X_SBL_PCR_VPSS) & mask; mask 229 drivers/media/platform/davinci/vpss.c u32 utemp, mask = 0x1, shift = 0; mask 259 drivers/media/platform/davinci/vpss.c utemp &= ~(mask << shift); mask 261 drivers/media/platform/davinci/vpss.c utemp |= (mask << shift); mask 271 drivers/media/platform/davinci/vpss.c u32 utemp, mask = 0x1, shift = 0, offset = DM365_ISP5_PCCR; mask 343 drivers/media/platform/davinci/vpss.c mask = ~mask; mask 344 drivers/media/platform/davinci/vpss.c utemp &= (mask << shift); mask 346 drivers/media/platform/davinci/vpss.c utemp |= (mask << shift); mask 461 drivers/media/platform/exynos-gsc/gsc-core.h static inline bool gsc_ctx_state_is_set(u32 mask, struct gsc_ctx *ctx) mask 467 drivers/media/platform/exynos-gsc/gsc-core.h ret = (ctx->state & mask) == mask; mask 492 drivers/media/platform/exynos-gsc/gsc-core.h void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask); mask 493 drivers/media/platform/exynos-gsc/gsc-core.h void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask); mask 34 drivers/media/platform/exynos-gsc/gsc-regs.c void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask) mask 39 drivers/media/platform/exynos-gsc/gsc-regs.c if (mask) mask 46 drivers/media/platform/exynos-gsc/gsc-regs.c void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask) mask 51 drivers/media/platform/exynos-gsc/gsc-regs.c if (mask) mask 62 drivers/media/platform/exynos-gsc/gsc-regs.c u32 mask = 1 << shift; mask 64 drivers/media/platform/exynos-gsc/gsc-regs.c cfg &= ~mask; mask 76 drivers/media/platform/exynos-gsc/gsc-regs.c u32 mask = 1 << shift; mask 78 drivers/media/platform/exynos-gsc/gsc-regs.c cfg &= ~mask; mask 582 drivers/media/platform/exynos4-is/fimc-capture.c u32 mask = FMT_FLAGS_CAM; mask 591 drivers/media/platform/exynos4-is/fimc-capture.c mask |= FMT_FLAGS_M2M; mask 594 drivers/media/platform/exynos4-is/fimc-capture.c mask = FMT_FLAGS_WRITEBACK; mask 596 drivers/media/platform/exynos4-is/fimc-capture.c ffmt = fimc_find_format(fourcc, code, mask, 0); mask 757 drivers/media/platform/exynos4-is/fimc-core.c unsigned int mask, int index) mask 768 drivers/media/platform/exynos4-is/fimc-core.c if (!(fmt->flags & mask)) mask 552 drivers/media/platform/exynos4-is/fimc-core.h static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx) mask 558 drivers/media/platform/exynos4-is/fimc-core.h ret = (ctx->state & mask) == mask; mask 626 drivers/media/platform/exynos4-is/fimc-core.h unsigned int mask, int index); mask 105 drivers/media/platform/exynos4-is/fimc-is-regs.c void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask) mask 107 drivers/media/platform/exynos4-is/fimc-is-regs.c if (hweight32(mask) == 1) { mask 109 drivers/media/platform/exynos4-is/fimc-is-regs.c __func__, mask); mask 116 drivers/media/platform/exynos4-is/fimc-is-regs.c mcuctl_write(mask, is, MCUCTL_REG_ISSR(23)); mask 147 drivers/media/platform/exynos4-is/fimc-is-regs.h void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask); mask 150 drivers/media/platform/exynos4-is/fimc-lite-reg.h static inline void flite_hw_set_dma_buf_mask(struct fimc_lite *dev, u32 mask) mask 152 drivers/media/platform/exynos4-is/fimc-lite-reg.h writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ); mask 108 drivers/media/platform/exynos4-is/fimc-lite.c const u32 *mbus_code, unsigned int mask, int index) mask 119 drivers/media/platform/exynos4-is/fimc-lite.c if (mask && !(fmt->flags & mask)) mask 804 drivers/media/platform/exynos4-is/fimc-reg.c unsigned int mask, val, camblk_cfg; mask 819 drivers/media/platform/exynos4-is/fimc-reg.c mask = SYSREG_CAMBLK_FIFORST_ISP | SYSREG_CAMBLK_ISPWB_FULL_EN; mask 820 drivers/media/platform/exynos4-is/fimc-reg.c ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val); mask 827 drivers/media/platform/exynos4-is/fimc-reg.c ret = regmap_update_bits(map, SYSREG_CAMBLK, mask, val); mask 831 drivers/media/platform/exynos4-is/fimc-reg.c mask = SYSREG_ISPBLK_FIFORST_CAM_BLK; mask 832 drivers/media/platform/exynos4-is/fimc-reg.c ret = regmap_update_bits(map, SYSREG_ISPBLK, mask, ~mask); mask 838 drivers/media/platform/exynos4-is/fimc-reg.c return regmap_update_bits(map, SYSREG_ISPBLK, mask, mask); mask 332 drivers/media/platform/exynos4-is/fimc-reg.h static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask) mask 334 drivers/media/platform/exynos4-is/fimc-reg.h writel(mask, dev->regs + FIMC_REG_CIFCNTSEQ); mask 139 drivers/media/platform/exynos4-is/mipi-csis.c u32 mask; mask 310 drivers/media/platform/exynos4-is/mipi-csis.c u32 val, mask; mask 322 drivers/media/platform/exynos4-is/mipi-csis.c mask = (1 << (state->num_lanes + 1)) - 1; mask 323 drivers/media/platform/exynos4-is/mipi-csis.c val |= (mask & S5PCSIS_DPHYCTRL_ENABLE); mask 699 drivers/media/platform/exynos4-is/mipi-csis.c if (!(status & state->events[i].mask)) mask 923 drivers/media/platform/m2m-deinterlace.c dma_cap_mask_t mask; mask 932 drivers/media/platform/m2m-deinterlace.c dma_cap_zero(mask); mask 933 drivers/media/platform/m2m-deinterlace.c dma_cap_set(DMA_INTERLEAVE, mask); mask 934 drivers/media/platform/m2m-deinterlace.c pcdev->dma_chan = dma_request_channel(mask, NULL, pcdev); mask 213 drivers/media/platform/marvell-ccic/mcam-core.h unsigned int val, unsigned int mask) mask 217 drivers/media/platform/marvell-ccic/mcam-core.h v = (v & ~mask) | (val & mask); mask 228 drivers/media/platform/meson/ao-cec.c #define writel_bits_relaxed(mask, val, addr) \ mask 229 drivers/media/platform/meson/ao-cec.c writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) mask 379 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c static bool mtk_mdp_ctx_state_is_set(struct mtk_mdp_ctx *ctx, u32 mask) mask 384 drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c ret = (ctx->state & mask) == mask; mask 457 drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c int ref_index = 0, mask; mask 459 drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c for (mask = vsi->refresh_frm_flags; mask; mask >>= 1) { mask 460 drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c if (mask & 1) mask 998 drivers/media/platform/omap/omap_vout.c u32 addr = 0, mask = 0; mask 1024 drivers/media/platform/omap/omap_vout.c mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD mask 1035 drivers/media/platform/omap/omap_vout.c omap_dispc_register_isr(omap_vout_isr, vout, mask); mask 1055 drivers/media/platform/omap/omap_vout.c mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD mask 1058 drivers/media/platform/omap/omap_vout.c omap_dispc_unregister_isr(omap_vout_isr, vout, mask); mask 1086 drivers/media/platform/omap/omap_vout.c u32 mask = 0; mask 1089 drivers/media/platform/omap/omap_vout.c mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD mask 1092 drivers/media/platform/omap/omap_vout.c omap_dispc_unregister_isr(omap_vout_isr, vout, mask); mask 96 drivers/media/platform/omap/omap_vout_vrfb.c dma_cap_mask_t mask; mask 133 drivers/media/platform/omap/omap_vout_vrfb.c dma_cap_zero(mask); mask 134 drivers/media/platform/omap/omap_vout_vrfb.c dma_cap_set(DMA_INTERLEAVE, mask); mask 135 drivers/media/platform/omap/omap_vout_vrfb.c vout->vrfb_dma_tx.chan = dma_request_chan_by_mask(&mask); mask 55 drivers/media/platform/omap3isp/ispccp2.c #define BIT_SET(var, shift, mask, val) \ mask 57 drivers/media/platform/omap3isp/ispccp2.c var = ((var) & ~((mask) << (shift))) \ mask 487 drivers/media/platform/omap3isp/isphist.c dma_cap_mask_t mask; mask 496 drivers/media/platform/omap3isp/isphist.c dma_cap_zero(mask); mask 497 drivers/media/platform/omap3isp/isphist.c dma_cap_set(DMA_SLAVE, mask); mask 498 drivers/media/platform/omap3isp/isphist.c hist->dma_ch = dma_request_chan_by_mask(&mask); mask 197 drivers/media/platform/qcom/venus/hfi_parser.c struct hfi_codec_mask_supported *mask = data; mask 199 drivers/media/platform/qcom/venus/hfi_parser.c *codecs = mask->codecs; mask 200 drivers/media/platform/qcom/venus/hfi_parser.c *domain = mask->video_domains; mask 72 drivers/media/platform/rcar-vin/rcar-core.c unsigned int mask = 0; mask 74 drivers/media/platform/rcar-vin/rcar-core.c for (route = vin->info->routes; route->mask; route++) { mask 81 drivers/media/platform/rcar-vin/rcar-core.c mask |= route->mask; mask 85 drivers/media/platform/rcar-vin/rcar-core.c return mask; mask 118 drivers/media/platform/rcar-vin/rcar-core.c unsigned int mask = ~0; mask 169 drivers/media/platform/rcar-vin/rcar-core.c mask &= rvin_group_get_mask(group->vin[i], csi_id, channel); mask 203 drivers/media/platform/rcar-vin/rcar-core.c mask_new = mask & rvin_group_get_mask(vin, csi_id, channel); mask 204 drivers/media/platform/rcar-vin/rcar-core.c vin_dbg(vin, "Try link change mask: 0x%x new: 0x%x\n", mask, mask_new); mask 703 drivers/media/platform/rcar-vin/rcar-core.c for (route = vin->info->routes; route->mask; route++) { mask 948 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 949 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, mask 950 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, mask 951 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, mask 952 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, mask 953 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 954 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, mask 955 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, mask 956 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 957 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, mask 958 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 959 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, mask 960 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 961 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, mask 962 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 963 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, mask 964 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 965 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, mask 966 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, mask 967 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, mask 968 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, mask 969 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 970 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, mask 971 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, mask 972 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, mask 973 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, mask 974 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, mask 975 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, mask 976 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, mask 977 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, mask 978 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, mask 979 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, mask 992 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 993 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, mask 994 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 0, .mask = BIT(2) | BIT(5) }, mask 995 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, mask 996 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 1, .mask = BIT(1) }, mask 997 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 998 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, mask 999 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, mask 1000 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 1, .mask = BIT(5) }, mask 1001 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 2, .mask = BIT(0) }, mask 1002 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 1003 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, mask 1004 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 1005 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, mask 1006 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 2, .vin = 2, .mask = BIT(5) }, mask 1007 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 1008 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) }, mask 1009 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 3, .mask = BIT(2) }, mask 1010 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 1011 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, mask 1012 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 3, .vin = 3, .mask = BIT(5) }, mask 1013 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 1014 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, mask 1015 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 4, .mask = BIT(2) | BIT(5) }, mask 1016 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, mask 1017 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 5, .mask = BIT(1) }, mask 1018 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 1019 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(3) }, mask 1020 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, mask 1021 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 5, .mask = BIT(5) }, mask 1022 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 0, .vin = 6, .mask = BIT(0) }, mask 1023 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, mask 1024 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, mask 1025 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, mask 1026 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, mask 1027 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 2, .vin = 6, .mask = BIT(5) }, mask 1028 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, mask 1029 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) }, mask 1030 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 1, .vin = 7, .mask = BIT(2) }, mask 1031 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, mask 1032 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, mask 1033 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI21, .channel = 3, .vin = 7, .mask = BIT(5) }, mask 1046 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 1047 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, mask 1048 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, mask 1049 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 1050 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, mask 1051 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, mask 1052 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 1053 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, mask 1054 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 1055 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, mask 1056 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 1057 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) }, mask 1058 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 1059 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, mask 1060 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 1061 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, mask 1062 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, mask 1063 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 1064 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(3) }, mask 1065 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, mask 1066 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) }, mask 1067 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, mask 1068 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) }, mask 1069 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, mask 1070 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) }, mask 1071 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) }, mask 1072 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) }, mask 1073 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, mask 1086 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 1087 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) }, mask 1088 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, mask 1089 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) }, mask 1090 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, mask 1091 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 1092 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) }, mask 1093 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) }, mask 1094 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 1095 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) }, mask 1096 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 1097 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) }, mask 1098 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 1099 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) }, mask 1100 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 1101 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) }, mask 1102 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 1103 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) }, mask 1104 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) }, mask 1105 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) }, mask 1106 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, mask 1107 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 1108 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) }, mask 1109 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) }, mask 1110 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) }, mask 1111 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) }, mask 1112 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) }, mask 1113 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) }, mask 1114 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) }, mask 1115 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) }, mask 1116 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) }, mask 1117 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) }, mask 1130 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 1131 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 1132 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(3) }, mask 1133 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 1134 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 1135 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 1136 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 1149 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) }, mask 1150 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) }, mask 1151 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) }, mask 1152 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) }, mask 1153 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) }, mask 1154 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) }, mask 1155 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) }, mask 1156 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) }, mask 1157 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 1158 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 4, .mask = BIT(2) }, mask 1159 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 1160 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, mask 1161 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 0, .vin = 6, .mask = BIT(1) }, mask 1162 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 2, .vin = 6, .mask = BIT(3) }, mask 1163 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 1, .vin = 7, .mask = BIT(0) }, mask 1164 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI41, .channel = 3, .vin = 7, .mask = BIT(3) }, mask 1177 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) }, mask 1178 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) }, mask 1179 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) }, mask 1180 drivers/media/platform/rcar-vin/rcar-core.c { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) }, mask 122 drivers/media/platform/rcar-vin/rcar-vin.h unsigned int mask; mask 105 drivers/media/platform/rockchip/rga/rga.h static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask) mask 107 drivers/media/platform/rockchip/rga/rga.h u32 temp = rga_read(rga, reg) & ~(mask); mask 109 drivers/media/platform/rockchip/rga/rga.h temp |= val & mask; mask 1963 drivers/media/platform/s5p-jpeg/jpeg-core.c unsigned int mask = ~0x27; /* 444, 422, 420, GRAY */ mask 1978 drivers/media/platform/s5p-jpeg/jpeg-core.c mask = ~0x06; /* 422, 420 */ mask 1983 drivers/media/platform/s5p-jpeg/jpeg-core.c V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY, mask, mask 118 drivers/media/platform/sh_vou.c u32 value, u32 mask) mask 122 drivers/media/platform/sh_vou.c value = (value & mask) | (old & ~mask); mask 127 drivers/media/platform/sh_vou.c u32 value, u32 mask) mask 129 drivers/media/platform/sh_vou.c sh_vou_reg_a_set(vou_dev, reg + 0x1000, value, mask); mask 133 drivers/media/platform/sh_vou.c u32 value, u32 mask) mask 135 drivers/media/platform/sh_vou.c sh_vou_reg_a_set(vou_dev, reg, value, mask); mask 136 drivers/media/platform/sh_vou.c sh_vou_reg_b_set(vou_dev, reg, value, mask); mask 138 drivers/media/platform/sti/bdisp/bdisp-v4l2.c static inline bool bdisp_ctx_state_is_set(u32 mask, struct bdisp_ctx *ctx) mask 144 drivers/media/platform/sti/bdisp/bdisp-v4l2.c ret = (ctx->state & mask) == mask; mask 696 drivers/media/platform/sti/hva/hva-v4l2.c u64 mask; mask 716 drivers/media/platform/sti/hva/hva-v4l2.c mask = ~(1 << V4L2_MPEG_VIDEO_ASPECT_1x1); mask 720 drivers/media/platform/sti/hva/hva-v4l2.c mask, mask 723 drivers/media/platform/sti/hva/hva-v4l2.c mask = ~((1 << V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | mask 730 drivers/media/platform/sti/hva/hva-v4l2.c mask, mask 765 drivers/media/platform/sti/hva/hva-v4l2.c mask = ~(1 << V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1); mask 769 drivers/media/platform/sti/hva/hva-v4l2.c mask, mask 776 drivers/media/platform/sti/hva/hva-v4l2.c mask = ~(1 << sei_fp_type); mask 780 drivers/media/platform/sti/hva/hva-v4l2.c mask, mask 193 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_set(void __iomem *base, u32 reg, u32 mask) mask 195 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) | mask); mask 198 drivers/media/platform/stm32/stm32-dcmi.c static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) mask 200 drivers/media/platform/stm32/stm32-dcmi.c reg_write(base, reg, reg_read(base, reg) & ~mask); mask 97 drivers/media/platform/tegra-cec/tegra_cec.c u32 status, mask; mask 100 drivers/media/platform/tegra-cec/tegra_cec.c mask = cec_read(cec, TEGRA_CEC_INT_MASK); mask 102 drivers/media/platform/tegra-cec/tegra_cec.c status &= mask; mask 112 drivers/media/platform/tegra-cec/tegra_cec.c mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); mask 123 drivers/media/platform/tegra-cec/tegra_cec.c mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); mask 155 drivers/media/platform/tegra-cec/tegra_cec.c mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); mask 285 drivers/media/platform/tegra-cec/tegra_cec.c u32 mask; mask 303 drivers/media/platform/tegra-cec/tegra_cec.c mask = cec_read(cec, TEGRA_CEC_INT_MASK); mask 305 drivers/media/platform/tegra-cec/tegra_cec.c mask | TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY); mask 79 drivers/media/platform/ti-vpe/cal.c #define reg_read_field(dev, offset, mask) get_field(reg_read(dev, offset), \ mask 80 drivers/media/platform/ti-vpe/cal.c mask) mask 81 drivers/media/platform/ti-vpe/cal.c #define reg_write_field(dev, offset, field, mask) { \ mask 83 drivers/media/platform/ti-vpe/cal.c set_field(&val, field, mask); \ mask 346 drivers/media/platform/ti-vpe/cal.c static inline int get_field(u32 value, u32 mask) mask 348 drivers/media/platform/ti-vpe/cal.c return (value & mask) >> __ffs(mask); mask 351 drivers/media/platform/ti-vpe/cal.c static inline void set_field(u32 *valp, u32 field, u32 mask) mask 355 drivers/media/platform/ti-vpe/cal.c val &= ~mask; mask 356 drivers/media/platform/ti-vpe/cal.c val |= (field << __ffs(mask)) & mask; mask 286 drivers/media/platform/ti-vpe/vpdma.c u32 mask, int shift) mask 288 drivers/media/platform/ti-vpe/vpdma.c return (read_reg(vpdma, offset) & (mask << shift)) >> shift; mask 292 drivers/media/platform/ti-vpe/vpdma.c u32 mask, int shift) mask 296 drivers/media/platform/ti-vpe/vpdma.c val &= ~(mask << shift); mask 297 drivers/media/platform/ti-vpe/vpdma.c val |= (field & mask) << shift; mask 449 drivers/media/platform/ti-vpe/vpe.c static int get_field(u32 value, u32 mask, int shift) mask 451 drivers/media/platform/ti-vpe/vpe.c return (value & (mask << shift)) >> shift; mask 454 drivers/media/platform/ti-vpe/vpe.c static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift) mask 456 drivers/media/platform/ti-vpe/vpe.c return get_field(read_reg(dev, offset), mask, shift); mask 459 drivers/media/platform/ti-vpe/vpe.c static void write_field(u32 *valp, u32 field, u32 mask, int shift) mask 463 drivers/media/platform/ti-vpe/vpe.c val &= ~(mask << shift); mask 464 drivers/media/platform/ti-vpe/vpe.c val |= (field & mask) << shift; mask 469 drivers/media/platform/ti-vpe/vpe.c u32 mask, int shift) mask 473 drivers/media/platform/ti-vpe/vpe.c write_field(&val, field, mask, shift); mask 294 drivers/media/platform/via-camera.c int reg, int value, int mask) mask 298 drivers/media/platform/via-camera.c tmp = (tmp & ~mask) | (value & mask); mask 47 drivers/media/platform/vsp1/vsp1_drv.c u32 mask = VI6_WFP_IRQ_STA_DFE | VI6_WFP_IRQ_STA_FRE; mask 60 drivers/media/platform/vsp1/vsp1_drv.c vsp1_write(vsp1, VI6_WPF_IRQ_STA(i), ~status & mask); mask 365 drivers/media/platform/vsp1/vsp1_pipe.c unsigned int mask; mask 367 drivers/media/platform/vsp1/vsp1_pipe.c mask = ((1 << pipe->num_inputs) - 1) << 1; mask 369 drivers/media/platform/vsp1/vsp1_pipe.c mask |= 1 << 0; mask 371 drivers/media/platform/vsp1/vsp1_pipe.c return pipe->buffers_ready == mask; mask 370 drivers/media/platform/vsp1/vsp1_wpf.c const unsigned int mask = BIT(WPF_CTRL_VFLIP) mask 377 drivers/media/platform/vsp1/vsp1_wpf.c wpf->flip.active = (wpf->flip.active & ~mask) mask 378 drivers/media/platform/vsp1/vsp1_wpf.c | (wpf->flip.pending & mask); mask 174 drivers/media/platform/xilinx/xilinx-vip.c void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set) mask 179 drivers/media/platform/xilinx/xilinx-vip.c reg = set ? reg | mask : reg & ~mask; mask 154 drivers/media/platform/xilinx/xilinx-vip.h void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set); mask 75 drivers/media/radio/radio-trust.c unsigned char val, mask; mask 90 drivers/media/radio/radio-trust.c for (mask = 0x80; mask; mask >>= 1) { mask 91 drivers/media/radio/radio-trust.c if (val & mask) mask 926 drivers/media/radio/si4713/si4713.c s32 *bit, s32 *mask, u16 *property, int *mul, mask 969 drivers/media/radio/si4713/si4713.c *mask = 0x1F << 5; mask 974 drivers/media/radio/si4713/si4713.c *mask = 1 << 15; mask 979 drivers/media/radio/si4713/si4713.c *mask = 1 << 14; mask 984 drivers/media/radio/si4713/si4713.c *mask = 1 << 13; mask 989 drivers/media/radio/si4713/si4713.c *mask = 1 << 12; mask 994 drivers/media/radio/si4713/si4713.c *mask = 1 << 10; mask 999 drivers/media/radio/si4713/si4713.c *mask = 1 << 4; mask 1004 drivers/media/radio/si4713/si4713.c *mask = 1 << 3; mask 1009 drivers/media/radio/si4713/si4713.c *mask = 1 << 1; mask 1014 drivers/media/radio/si4713/si4713.c *mask = 1 << 0; mask 1019 drivers/media/radio/si4713/si4713.c *mask = 1 << 0; mask 1108 drivers/media/radio/si4713/si4713.c s32 bit = 0, mask = 0; mask 1184 drivers/media/radio/si4713/si4713.c &mask, &property, &mul, &table, &size); mask 1199 drivers/media/radio/si4713/si4713.c if (mask) { mask 1203 drivers/media/radio/si4713/si4713.c val = set_bits(val, ctrl->val, bit, mask); mask 1209 drivers/media/radio/si4713/si4713.c if (mask) mask 102 drivers/media/radio/wl128x/fmdrv.h u16 mask; /* FM interrupt mask */ mask 594 drivers/media/radio/wl128x/fmdrv_common.c if (fmdev->irq_info.flag & FM_MAL_EVENT & fmdev->irq_info.mask) mask 603 drivers/media/radio/wl128x/fmdrv_common.c if (fmdev->irq_info.flag & FM_RDS_EVENT & fmdev->irq_info.mask) { mask 820 drivers/media/radio/wl128x/fmdrv_common.c irq_info.mask) { mask 847 drivers/media/radio/wl128x/fmdrv_common.c (fmdev->irq_info.flag & FM_LEV_EVENT & fmdev->irq_info.mask) && mask 853 drivers/media/radio/wl128x/fmdrv_common.c fmdev->irq_info.mask &= ~FM_LEV_EVENT; mask 989 drivers/media/radio/wl128x/fmdrv_common.c fmdev->irq_info.mask |= FM_LEV_EVENT; mask 1018 drivers/media/radio/wl128x/fmdrv_common.c payload = fmdev->irq_info.mask; mask 1550 drivers/media/radio/wl128x/fmdrv_common.c fmdev->irq_info.mask = FM_MAL_EVENT; mask 23 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask |= FM_LEV_EVENT; mask 75 drivers/media/radio/wl128x/fmdrv_rx.c intr_flag = fmdev->irq_info.mask; mask 76 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT); mask 77 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 118 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask = intr_flag; mask 119 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 219 drivers/media/radio/wl128x/fmdrv_rx.c intr_flag = fmdev->irq_info.mask; mask 220 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT); mask 221 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 247 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask = intr_flag; mask 248 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 700 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask |= FM_RDS_EVENT; mask 701 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 705 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask &= ~FM_RDS_EVENT; mask 727 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask &= ~(FM_RDS_EVENT); mask 791 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask |= FM_LEV_EVENT; mask 793 drivers/media/radio/wl128x/fmdrv_rx.c fmdev->irq_info.mask &= ~FM_LEV_EVENT; mask 795 drivers/media/radio/wl128x/fmdrv_rx.c payload = fmdev->irq_info.mask; mask 60 drivers/media/rc/ene_ir.c static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask) mask 62 drivers/media/rc/ene_ir.c dbg_regs("reg %04x |= %02x", reg, mask); mask 64 drivers/media/rc/ene_ir.c outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO); mask 68 drivers/media/rc/ene_ir.c static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask) mask 70 drivers/media/rc/ene_ir.c dbg_regs("reg %04x &= ~%02x ", reg, mask); mask 72 drivers/media/rc/ene_ir.c outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO); mask 76 drivers/media/rc/ene_ir.c static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask, mask 80 drivers/media/rc/ene_ir.c ene_set_reg_mask(dev, reg, mask); mask 82 drivers/media/rc/ene_ir.c ene_clear_reg_mask(dev, reg, mask); mask 322 drivers/media/rc/iguanair.c static int iguanair_set_tx_mask(struct rc_dev *dev, uint32_t mask) mask 326 drivers/media/rc/iguanair.c if (mask > 15) mask 330 drivers/media/rc/iguanair.c ir->packet->channels = mask << 4; mask 399 drivers/media/rc/img-ir/img-ir-hw.c (unsigned long long)filter->mask); mask 403 drivers/media/rc/img-ir/img-ir-hw.c img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask); mask 404 drivers/media/rc/img-ir/img-ir-hw.c img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask mask 468 drivers/media/rc/img-ir/img-ir-hw.c sc_filter->mask); mask 473 drivers/media/rc/img-ir/img-ir-hw.c if (!sc_filter->mask) { mask 501 drivers/media/rc/img-ir/img-ir-hw.c (unsigned long long)filter.mask); mask 587 drivers/media/rc/img-ir/img-ir-hw.c rdev->scancode_wakeup_filter.mask = 0; mask 110 drivers/media/rc/img-ir/img-ir-hw.h u64 mask; mask 35 drivers/media/rc/img-ir/img-ir-jvc.c cust_m = (in->mask >> 8) & 0xff; mask 37 drivers/media/rc/img-ir/img-ir-jvc.c data_m = (in->mask >> 0) & 0xff; mask 40 drivers/media/rc/img-ir/img-ir-jvc.c out->mask = cust_m | data_m << 8; mask 60 drivers/media/rc/img-ir/img-ir-nec.c data_m = in->mask & 0xff; mask 70 drivers/media/rc/img-ir/img-ir-nec.c if ((in->data | in->mask) & 0xff000000) mask 72 drivers/media/rc/img-ir/img-ir-nec.c else if ((in->data | in->mask) & 0x00ff0000) mask 82 drivers/media/rc/img-ir/img-ir-nec.c addr_m = bitrev8(in->mask >> 24); mask 84 drivers/media/rc/img-ir/img-ir-nec.c addr_inv_m = bitrev8(in->mask >> 16); mask 86 drivers/media/rc/img-ir/img-ir-nec.c data_m = bitrev8(in->mask >> 8); mask 88 drivers/media/rc/img-ir/img-ir-nec.c data_inv_m = bitrev8(in->mask >> 0); mask 93 drivers/media/rc/img-ir/img-ir-nec.c addr_m = (in->mask >> 16) & 0xff; mask 95 drivers/media/rc/img-ir/img-ir-nec.c addr_inv_m = (in->mask >> 8) & 0xff; mask 102 drivers/media/rc/img-ir/img-ir-nec.c addr_m = (in->mask >> 8) & 0xff; mask 114 drivers/media/rc/img-ir/img-ir-nec.c out->mask = data_inv_m << 24 | mask 56 drivers/media/rc/img-ir/img-ir-sanyo.c data_m = in->mask & 0xff; mask 63 drivers/media/rc/img-ir/img-ir-sanyo.c addr_m = (in->mask >> 8) & 0x1fff; mask 70 drivers/media/rc/img-ir/img-ir-sanyo.c out->mask = (u64)data_m << 34 | mask 44 drivers/media/rc/img-ir/img-ir-sharp.c addr_m = (in->mask >> 8) & 0x1f; mask 46 drivers/media/rc/img-ir/img-ir-sharp.c cmd_m = (in->mask >> 0) & 0xff; mask 59 drivers/media/rc/img-ir/img-ir-sharp.c out->mask = addr_m | mask 61 drivers/media/rc/img-ir/img-ir-sony.c dev_m = (in->mask >> 16) & 0xff; mask 63 drivers/media/rc/img-ir/img-ir-sony.c subdev_m = (in->mask >> 8) & 0xff; mask 65 drivers/media/rc/img-ir/img-ir-sony.c func_m = (in->mask >> 0) & 0x7f; mask 111 drivers/media/rc/img-ir/img-ir-sony.c out->mask = func_m | mask 1005 drivers/media/rc/mceusb.c static int mceusb_set_tx_mask(struct rc_dev *dev, u32 mask) mask 1012 drivers/media/rc/mceusb.c if (mask >= (1 << emitters)) mask 1016 drivers/media/rc/mceusb.c ir->tx_mask = mask; mask 1018 drivers/media/rc/mceusb.c ir->tx_mask = (mask != MCE_DEFAULT_TX_MASK ? mask 1019 drivers/media/rc/mceusb.c mask ^ MCE_DEFAULT_TX_MASK : mask) << 1; mask 69 drivers/media/rc/meson-ir.c u32 mask, u32 value) mask 74 drivers/media/rc/meson-ir.c data &= ~mask; mask 75 drivers/media/rc/meson-ir.c data |= (value & mask); mask 93 drivers/media/rc/mtk-cir.c u32 mask; mask 171 drivers/media/rc/mtk-cir.c static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) mask 176 drivers/media/rc/mtk-cir.c tmp = (tmp & ~mask) | val; mask 190 drivers/media/rc/mtk-cir.c static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) mask 195 drivers/media/rc/mtk-cir.c mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); mask 198 drivers/media/rc/mtk-cir.c static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) mask 203 drivers/media/rc/mtk-cir.c mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); mask 391 drivers/media/rc/mtk-cir.c ir->data->fields[MTK_CHK_PERIOD].mask; mask 392 drivers/media/rc/mtk-cir.c mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, mask 400 drivers/media/rc/mtk-cir.c ir->data->fields[MTK_HW_PERIOD].mask; mask 401 drivers/media/rc/mtk-cir.c mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, mask 670 drivers/media/rc/nuvoton-cir.c if (!sc_filter->mask) mask 526 drivers/media/rc/rc-ir-raw.c u64 mask = 1ULL << protocol; mask 528 drivers/media/rc/rc-ir-raw.c ir_raw_load_modules(&mask); mask 532 drivers/media/rc/rc-ir-raw.c if (handler->protocols & mask && handler->encode) { mask 596 drivers/media/rc/rc-ir-raw.c u64 mask = BIT_ULL(protocol); mask 600 drivers/media/rc/rc-ir-raw.c if (handler->protocols & mask && handler->encode) { mask 39 drivers/media/rc/rc-loopback.c static int loop_set_tx_mask(struct rc_dev *dev, u32 mask) mask 43 drivers/media/rc/rc-loopback.c if ((mask & (RXMASK_REGULAR | RXMASK_LEARNING)) != mask) { mask 44 drivers/media/rc/rc-loopback.c dprintk("invalid tx mask: %u\n", mask); mask 48 drivers/media/rc/rc-loopback.c dprintk("setting tx mask: %u\n", mask); mask 49 drivers/media/rc/rc-loopback.c lodev->txmask = mask; mask 175 drivers/media/rc/rc-loopback.c if (!sc->mask) mask 910 drivers/media/rc/rc-main.c u32 mask, s = filter->data; mask 916 drivers/media/rc/rc-main.c mask = protocols[protocol].scancode_bits; mask 921 drivers/media/rc/rc-main.c filter->data &= mask; mask 922 drivers/media/rc/rc-main.c filter->mask &= mask; mask 927 drivers/media/rc/rc-main.c if (dev->encode_wakeup && filter->mask != 0 && filter->mask != mask) mask 1043 drivers/media/rc/rc-main.c bool mask; mask 1051 drivers/media/rc/rc-main.c .mask = (_mask), \ mask 1128 drivers/media/rc/rc-main.c u64 mask; mask 1150 drivers/media/rc/rc-main.c mask = proto_names[i].type; mask 1157 drivers/media/rc/rc-main.c mask = 0; mask 1168 drivers/media/rc/rc-main.c *protocols |= mask; mask 1170 drivers/media/rc/rc-main.c *protocols &= ~mask; mask 1172 drivers/media/rc/rc-main.c *protocols = mask; mask 1289 drivers/media/rc/rc-main.c if (dev->s_filter && filter->mask) { mask 1297 drivers/media/rc/rc-main.c filter->mask = 0; mask 1342 drivers/media/rc/rc-main.c if (fattr->mask) mask 1343 drivers/media/rc/rc-main.c val = filter->mask; mask 1399 drivers/media/rc/rc-main.c if (fattr->mask) mask 1400 drivers/media/rc/rc-main.c new_filter.mask = val; mask 1529 drivers/media/rc/rc-main.c u64 mask = 1ULL << protocol; mask 1531 drivers/media/rc/rc-main.c ir_raw_load_modules(&mask); mask 1532 drivers/media/rc/rc-main.c if (!mask) { mask 1547 drivers/media/rc/rc-main.c dev->scancode_wakeup_filter.mask = 0; mask 231 drivers/media/rc/winbond-cir.c wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) mask 236 drivers/media/rc/winbond-cir.c val = ((val & ~mask) | (bits & mask)); mask 583 drivers/media/rc/winbond-cir.c wbcir_txmask(struct rc_dev *dev, u32 mask) mask 590 drivers/media/rc/winbond-cir.c if (mask > 15) mask 594 drivers/media/rc/winbond-cir.c switch (mask) { mask 617 drivers/media/rc/winbond-cir.c if (data->txmask != mask) { mask 619 drivers/media/rc/winbond-cir.c data->txmask = mask; mask 675 drivers/media/rc/winbond-cir.c u8 mask[11]; mask 679 drivers/media/rc/winbond-cir.c u32 mask_sc = rc->scancode_wakeup_filter.mask; mask 683 drivers/media/rc/winbond-cir.c memset(mask, 0, sizeof(mask)); mask 693 drivers/media/rc/winbond-cir.c mask[0] = (mask_sc & 0x003f); mask 694 drivers/media/rc/winbond-cir.c mask[0] |= (mask_sc & 0x0300) >> 2; mask 695 drivers/media/rc/winbond-cir.c mask[1] = (mask_sc & 0x1c00) >> 10; mask 709 drivers/media/rc/winbond-cir.c mask[1] = bitrev8(mask_sc); mask 710 drivers/media/rc/winbond-cir.c mask[0] = mask[1]; mask 711 drivers/media/rc/winbond-cir.c mask[3] = bitrev8(mask_sc >> 8); mask 712 drivers/media/rc/winbond-cir.c mask[2] = mask[3]; mask 723 drivers/media/rc/winbond-cir.c mask[1] = bitrev8(mask_sc); mask 724 drivers/media/rc/winbond-cir.c mask[0] = mask[1]; mask 725 drivers/media/rc/winbond-cir.c mask[2] = bitrev8(mask_sc >> 8); mask 726 drivers/media/rc/winbond-cir.c mask[3] = bitrev8(mask_sc >> 16); mask 737 drivers/media/rc/winbond-cir.c mask[0] = bitrev8(mask_sc); mask 738 drivers/media/rc/winbond-cir.c mask[1] = bitrev8(mask_sc >> 8); mask 739 drivers/media/rc/winbond-cir.c mask[2] = bitrev8(mask_sc >> 16); mask 740 drivers/media/rc/winbond-cir.c mask[3] = bitrev8(mask_sc >> 24); mask 753 drivers/media/rc/winbond-cir.c mask[0] = wbcir_to_rc6cells(mask_sc >> 0); mask 755 drivers/media/rc/winbond-cir.c mask[1] = wbcir_to_rc6cells(mask_sc >> 4); mask 759 drivers/media/rc/winbond-cir.c mask[2] = wbcir_to_rc6cells(mask_sc >> 8); mask 761 drivers/media/rc/winbond-cir.c mask[3] = wbcir_to_rc6cells(mask_sc >> 12); mask 765 drivers/media/rc/winbond-cir.c mask[4] = 0xF0; mask 767 drivers/media/rc/winbond-cir.c mask[5] = 0x0F; mask 780 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 0); mask 782 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 4); mask 786 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 8); mask 788 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 12); mask 792 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 16); mask 798 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 20); mask 805 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 24); mask 807 drivers/media/rc/winbond-cir.c mask[i++] = wbcir_to_rc6cells(mask_sc >> 28); mask 814 drivers/media/rc/winbond-cir.c mask[i++] = 0xFF; mask 816 drivers/media/rc/winbond-cir.c mask[i++] = 0x0F; mask 834 drivers/media/rc/winbond-cir.c outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); mask 1088 drivers/media/rc/winbond-cir.c data->dev->scancode_wakeup_filter.mask = 0xffff7fff; mask 38 drivers/media/rc/zx-irdec.c u32 mask, u32 value) mask 43 drivers/media/rc/zx-irdec.c data &= ~mask; mask 44 drivers/media/rc/zx-irdec.c data |= value & mask; mask 78 drivers/media/tuners/max2165.c u8 mask, u8 data) mask 83 drivers/media/tuners/max2165.c data &= mask; mask 87 drivers/media/tuners/max2165.c v &= ~mask; mask 163 drivers/media/tuners/mxl5007t.c static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val) mask 169 drivers/media/tuners/mxl5007t.c reg_pair[i].val &= ~mask; mask 184 drivers/media/tuners/qm1d1c0042.c u8 val, mask; mask 267 drivers/media/tuners/qm1d1c0042.c mask = state->cfg.lpf ? 0x3f : 0x7f; mask 268 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x0c] & mask; mask 273 drivers/media/tuners/qm1d1c0042.c val = state->regs[0x0c] | ~mask; mask 83 drivers/media/usb/au0828/au0828-input.c static int au8522_rc_andor(struct au0828_rc *ir, u16 reg, u8 mask, u8 value) mask 93 drivers/media/usb/au0828/au0828-input.c buf = (buf & ~mask) | (value & mask); mask 290 drivers/media/usb/au0828/au0828.h #define au0828_andor(dev, reg, mask, value) \ mask 292 drivers/media/usb/au0828/au0828.h (au0828_readreg(dev, reg) & ~(mask)) | ((value) & (mask))) mask 1718 drivers/media/usb/cx231xx/cx231xx-core.c u32 mask = 0; mask 1737 drivers/media/usb/cx231xx/cx231xx-core.c mask = 1 << bit_end; mask 1739 drivers/media/usb/cx231xx/cx231xx-core.c mask = mask + (1 << (i - 1)); mask 1744 drivers/media/usb/cx231xx/cx231xx-core.c tmp &= ~mask; mask 1751 drivers/media/usb/cx231xx/cx231xx-core.c tmp &= ~mask; mask 1762 drivers/media/usb/cx231xx/cx231xx-core.c u16 saddr, u32 mask, u32 value) mask 1772 drivers/media/usb/cx231xx/cx231xx-core.c temp &= ~mask; mask 772 drivers/media/usb/cx231xx/cx231xx.h u16 saddr, u32 mask, u32 value); mask 161 drivers/media/usb/dvb-usb-v2/af9035.c u8 mask) mask 167 drivers/media/usb/dvb-usb-v2/af9035.c if (mask != 0xff) { mask 172 drivers/media/usb/dvb-usb-v2/af9035.c val &= mask; mask 173 drivers/media/usb/dvb-usb-v2/af9035.c tmp &= ~mask; mask 1723 drivers/media/usb/dvb-usb-v2/af9035.c tab[i].mask); mask 1805 drivers/media/usb/dvb-usb-v2/af9035.c tab[i].val, tab[i].mask); mask 33 drivers/media/usb/dvb-usb-v2/af9035.h u8 mask; mask 122 drivers/media/usb/dvb-usb-v2/anysee.c u8 mask) mask 128 drivers/media/usb/dvb-usb-v2/anysee.c if (mask != 0xff) { mask 133 drivers/media/usb/dvb-usb-v2/anysee.c val &= mask; mask 134 drivers/media/usb/dvb-usb-v2/anysee.c tmp &= ~mask; mask 143 drivers/media/usb/dvb-usb-v2/anysee.c u8 mask) mask 152 drivers/media/usb/dvb-usb-v2/anysee.c tmp &= mask; mask 156 drivers/media/usb/dvb-usb-v2/anysee.c if ((mask >> i) & 0x01) mask 331 drivers/media/usb/dvb-usb-v2/gl861.c u32 mask; mask 356 drivers/media/usb/dvb-usb-v2/gl861.c mask = 1UL << 31; mask 359 drivers/media/usb/dvb-usb-v2/gl861.c if (sat_color & mask) mask 364 drivers/media/usb/dvb-usb-v2/gl861.c mask >>= 1; mask 132 drivers/media/usb/dvb-usb-v2/mxl111sf.c u8 addr, u8 mask, u8 data) mask 137 drivers/media/usb/dvb-usb-v2/mxl111sf.c if (mask != 0xff) { mask 143 drivers/media/usb/dvb-usb-v2/mxl111sf.c addr, mask, data); mask 150 drivers/media/usb/dvb-usb-v2/mxl111sf.c val &= ~mask; mask 167 drivers/media/usb/dvb-usb-v2/mxl111sf.c ctrl_reg_info[i].mask | mask 172 drivers/media/usb/dvb-usb-v2/mxl111sf.c ctrl_reg_info[i].mask, mask 109 drivers/media/usb/dvb-usb-v2/mxl111sf.h u8 mask; mask 114 drivers/media/usb/dvb-usb-v2/mxl111sf.h u8 addr, u8 mask, u8 data); mask 110 drivers/media/usb/dvb-usb-v2/rtl28xxu.c u8 mask) mask 116 drivers/media/usb/dvb-usb-v2/rtl28xxu.c if (mask != 0xff) { mask 121 drivers/media/usb/dvb-usb-v2/rtl28xxu.c val &= mask; mask 122 drivers/media/usb/dvb-usb-v2/rtl28xxu.c tmp &= ~mask; mask 1742 drivers/media/usb/dvb-usb-v2/rtl28xxu.c init_tab[i].val, init_tab[i].mask); mask 1771 drivers/media/usb/dvb-usb-v2/rtl28xxu.c refresh_tab[i].val, refresh_tab[i].mask); mask 130 drivers/media/usb/dvb-usb-v2/rtl28xxu.h u8 mask; mask 215 drivers/media/usb/dvb-usb/af9005.c u8 temp, mask; mask 223 drivers/media/usb/dvb-usb/af9005.c mask = regmask[len - 1] << pos; mask 224 drivers/media/usb/dvb-usb/af9005.c temp = (temp & ~mask) | ((value << pos) & mask); mask 2296 drivers/media/usb/dvb-usb/dib0700_devices.c { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 }, mask 2297 drivers/media/usb/dvb-usb/dib0700_devices.c { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 }, mask 2327 drivers/media/usb/dvb-usb/dib0700_devices.c { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_ON, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = (0x10 & ~0x1) | 0x20 }, mask 2328 drivers/media/usb/dvb-usb/dib0700_devices.c { .component = BOARD_GPIO_COMPONENT_DEMOD, .function = BOARD_GPIO_FUNCTION_COMPONENT_OFF, .mask = 0x10 | 0x21, .direction = 0 & ~0x21, .value = 0 | 0x21 }, mask 560 drivers/media/usb/em28xx/em28xx-cards.c .mask = EM28XX_R0C_USBSUSP_SNAPSHOT, mask 570 drivers/media/usb/em28xx/em28xx-cards.c .mask = 0x80, mask 576 drivers/media/usb/em28xx/em28xx-cards.c .mask = 0x08, mask 735 drivers/media/usb/em28xx/em28xx-core.c gpio->mask); mask 856 drivers/media/usb/em28xx/em28xx-dvb.c gpio[i].mask); mask 536 drivers/media/usb/em28xx/em28xx-input.c is_pressed = regval & button->mask; mask 538 drivers/media/usb/em28xx/em28xx-input.c & button->mask; mask 546 drivers/media/usb/em28xx/em28xx-input.c (~regval & button->mask) mask 547 drivers/media/usb/em28xx/em28xx-input.c | (regval & ~button->mask)); mask 415 drivers/media/usb/em28xx/em28xx.h unsigned char val, mask; mask 473 drivers/media/usb/em28xx/em28xx.h u8 mask; mask 580 drivers/media/usb/go7007/s2250-board.c u8 mask; mask 583 drivers/media/usb/go7007/s2250-board.c mask = 1<<5; mask 584 drivers/media/usb/go7007/s2250-board.c data[0] &= ~mask; mask 585 drivers/media/usb/go7007/s2250-board.c data[1] |= mask; mask 2128 drivers/media/usb/gspca/ov519.c u8 mask) mask 2133 drivers/media/usb/gspca/ov519.c if (mask != 0xff) { mask 2134 drivers/media/usb/gspca/ov519.c value &= mask; /* Enforce mask on value */ mask 2139 drivers/media/usb/gspca/ov519.c oldval = ret & ~mask; /* Clear the masked bits */ mask 2448 drivers/media/usb/gspca/ov519.c u8 mask) mask 2453 drivers/media/usb/gspca/ov519.c value &= mask; /* Enforce mask on value */ mask 2457 drivers/media/usb/gspca/ov519.c oldval = rc & ~mask; /* Clear the masked bits */ mask 584 drivers/media/usb/gspca/sq930x.c static void gpio_set(struct sd *sd, u16 val, u16 mask) mask 588 drivers/media/usb/gspca/sq930x.c if (mask & 0x00ff) { mask 589 drivers/media/usb/gspca/sq930x.c sd->gpio[0] &= ~mask; mask 594 drivers/media/usb/gspca/sq930x.c mask >>= 8; mask 596 drivers/media/usb/gspca/sq930x.c if (mask) { mask 597 drivers/media/usb/gspca/sq930x.c sd->gpio[1] &= ~mask; mask 95 drivers/media/usb/gspca/stk1135.c static void reg_w_mask(struct gspca_dev *gspca_dev, u16 index, u8 val, u8 mask) mask 97 drivers/media/usb/gspca/stk1135.c val = (reg_r(gspca_dev, index) & ~mask) | (val & mask); mask 190 drivers/media/usb/gspca/stk1135.c u16 reg, u16 val, u16 mask) mask 192 drivers/media/usb/gspca/stk1135.c val = (sensor_read(gspca_dev, reg) & ~mask) | (val & mask); mask 532 drivers/media/usb/hdpvr/hdpvr-video.c __poll_t mask = v4l2_ctrl_poll(filp, wait); mask 535 drivers/media/usb/hdpvr/hdpvr-video.c return mask; mask 559 drivers/media/usb/hdpvr/hdpvr-video.c mask |= EPOLLIN | EPOLLRDNORM; mask 561 drivers/media/usb/hdpvr/hdpvr-video.c return mask; mask 479 drivers/media/usb/pulse8-cec/pulse8-cec.c u16 mask = 0; mask 486 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = 1 << log_addr; mask 488 drivers/media/usb/pulse8-cec/pulse8-cec.c cmd[1] = mask >> 8; mask 489 drivers/media/usb/pulse8-cec/pulse8-cec.c cmd[2] = mask & 0xff; mask 492 drivers/media/usb/pulse8-cec/pulse8-cec.c if ((err && mask != 0) || pulse8->restoring_config) mask 514 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_TV; mask 517 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_RECORD; mask 520 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_TUNER; mask 523 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_PLAYBACK; mask 526 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_AUDIOSYSTEM; mask 529 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_UNREGISTERED; mask 532 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = CEC_LOG_ADDR_MASK_SPECIFIC; mask 535 drivers/media/usb/pulse8-cec/pulse8-cec.c mask = 0; mask 539 drivers/media/usb/pulse8-cec/pulse8-cec.c cmd[1] = mask >> 8; mask 540 drivers/media/usb/pulse8-cec/pulse8-cec.c cmd[2] = mask & 0xff; mask 46 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *cptr,int mask,int val) mask 53 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c mask &= cptr->info->def.type_bitmask.valid_bits; mask 61 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ret = cptr->info->set_value(cptr,mask,val); mask 270 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, mask 276 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c return cptr->info->val_to_sym(cptr,mask,val,buf,maxlen,len); mask 422 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,val,kv,mode,ret; mask 423 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c mask = 0; mask 454 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c mask = valid_bits; mask 458 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c mask |= kv; mask 462 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c mask |= kv; mask 469 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c *maskptr = mask; mask 534 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, mask 563 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c val & mask & cptr->info->def.type_bitmask.valid_bits, mask 574 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c int mask,int val, mask 580 drivers/media/usb/pvrusb2/pvrusb2-ctrl.c ret = pvr2_ctrl_value_to_sym_internal(cptr,mask,val, mask 23 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *,int mask,int val); mask 71 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, mask 82 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, mask 94 drivers/media/usb/pvrusb2/pvrusb2-ctrl.h int mask,int val, mask 244 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c int mask,val; mask 247 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c &mask, &val); mask 250 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c &mask, &val); mask 253 drivers/media/usb/pvrusb2/pvrusb2-sysfs.c ret = pvr2_ctrl_set_mask_value(cip->cptr, mask, val); mask 1145 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c __poll_t mask = 0; mask 1150 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c mask |= EPOLLIN | EPOLLRDNORM; mask 1151 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c return mask; mask 1162 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c mask |= EPOLLIN | EPOLLRDNORM; mask 1165 drivers/media/usb/pvrusb2/pvrusb2-v4l2.c return mask; mask 71 drivers/media/usb/pwc/pwc-dec23.c unsigned int bit, byte, mask, val; mask 75 drivers/media/usb/pwc/pwc-dec23.c mask = bitpower - 1; mask 78 drivers/media/usb/pwc/pwc-dec23.c val = (byte & mask); mask 541 drivers/media/usb/pwc/pwc-dec23.c unsigned int mask, shift; mask 556 drivers/media/usb/pwc/pwc-dec23.c mask = pdec->table_bitpowermask[nbits][col1]; mask 558 drivers/media/usb/pwc/pwc-dec23.c rows = ((mask << shift) + 0x80) & 0xFF; mask 124 drivers/media/usb/tm6000/tm6000-core.c u16 index, u16 mask) mask 136 drivers/media/usb/tm6000/tm6000-core.c new_index = (buf[0] & ~mask) | (index & mask); mask 313 drivers/media/usb/tm6000/tm6000.h u16 index, u16 mask); mask 367 drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c int associated_chan, u8 filter[8], u8 mask[8]) mask 375 drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c mask[0], mask[1], mask[2], mask[3], mask 376 drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c mask[4], mask[5], mask[6], mask[7], mask 377 drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c mask[8], mask[9], mask[10], mask[11] mask 770 drivers/media/usb/uvc/uvc_ctrl.c u8 mask; mask 774 drivers/media/usb/uvc/uvc_ctrl.c mask = ((1LL << bits) - 1) << offset; mask 777 drivers/media/usb/uvc/uvc_ctrl.c u8 byte = *data & mask; mask 781 drivers/media/usb/uvc/uvc_ctrl.c mask = (1 << bits) - 1; mask 799 drivers/media/usb/uvc/uvc_ctrl.c u8 mask; mask 813 drivers/media/usb/uvc/uvc_ctrl.c mask = ((1LL << bits) - 1) << offset; mask 814 drivers/media/usb/uvc/uvc_ctrl.c *data = (*data & ~mask) | ((value << offset) & mask); mask 98 drivers/media/v4l2-core/v4l2-common.c unsigned int mask = ~((1 << align) - 1); mask 101 drivers/media/v4l2-core/v4l2-common.c x = clamp(x, (min + ~mask) & mask, max & mask); mask 105 drivers/media/v4l2-core/v4l2-common.c x = (x + (1 << (align - 1))) & mask; mask 2589 drivers/media/v4l2-core/v4l2-ctrls.c u32 id, u8 _max, u64 mask, u8 _def) mask 2614 drivers/media/v4l2-core/v4l2-ctrls.c 0, max, mask, def, NULL, 0, mask 2622 drivers/media/v4l2-core/v4l2-ctrls.c u64 mask, u8 _def, const char * const *qmenu) mask 2646 drivers/media/v4l2-core/v4l2-ctrls.c 0, max, mask, def, NULL, 0, mask 2952 drivers/media/v4l2-core/v4l2-ctrls.c unsigned mask = 1; mask 2960 drivers/media/v4l2-core/v4l2-ctrls.c mask = 0; mask 2975 drivers/media/v4l2-core/v4l2-ctrls.c (is_compound & mask) == match) mask 2989 drivers/media/v4l2-core/v4l2-ctrls.c (is_compound & mask) == match) mask 301 drivers/media/v4l2-core/v4l2-flash-led-class.c u32 mask; mask 330 drivers/media/v4l2-core/v4l2-flash-led-class.c mask = 1 << V4L2_FLASH_LED_MODE_NONE | mask 333 drivers/media/v4l2-core/v4l2-flash-led-class.c mask |= 1 << V4L2_FLASH_LED_MODE_FLASH; mask 339 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl_cfg->menu_skip_mask = ~mask; mask 363 drivers/media/v4l2-core/v4l2-flash-led-class.c mask = (1 << V4L2_FLASH_STROBE_SOURCE_SOFTWARE) | mask 370 drivers/media/v4l2-core/v4l2-flash-led-class.c ctrl_cfg->menu_skip_mask = ~mask; mask 982 drivers/media/v4l2-core/v4l2-mem2mem.c u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; mask 985 drivers/media/v4l2-core/v4l2-mem2mem.c mask |= V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_PFRAME | mask 993 drivers/media/v4l2-core/v4l2-mem2mem.c cap_vb->flags &= ~mask; mask 994 drivers/media/v4l2-core/v4l2-mem2mem.c cap_vb->flags |= out_vb->flags & mask; mask 32 drivers/memory/da8xx-ddrctl.c u32 mask; mask 40 drivers/memory/da8xx-ddrctl.c .mask = 0xffffff00, mask 143 drivers/memory/da8xx-ddrctl.c reg &= knob->mask; mask 605 drivers/memory/emif.c if (custom_configs && (custom_configs->mask & mask 752 drivers/memory/emif.c u32 mask; mask 757 drivers/memory/emif.c if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) { mask 783 drivers/memory/emif.c mask = CS_TIM_MASK; mask 791 drivers/memory/emif.c mask = SR_TIM_MASK; mask 795 drivers/memory/emif.c mask = PD_TIM_MASK; mask 799 drivers/memory/emif.c mask = 0; mask 804 drivers/memory/emif.c if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) { mask 811 drivers/memory/emif.c timeout, mask >> shift); mask 812 drivers/memory/emif.c timeout = mask >> shift; mask 816 drivers/memory/emif.c pwr_mgmt_ctrl = (timeout << shift) & mask; mask 819 drivers/memory/emif.c ~mask; mask 974 drivers/memory/emif.c if (custom_configs && !(custom_configs->mask & mask 1243 drivers/memory/emif.c if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) && mask 1249 drivers/memory/emif.c if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL) mask 1277 drivers/memory/emif.c cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE; mask 1291 drivers/memory/emif.c cust_cfgs->mask |= mask 1298 drivers/memory/emif.c cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART; mask 374 drivers/memory/omap-gpmc.c static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) mask 380 drivers/memory/omap-gpmc.c l |= mask; mask 382 drivers/memory/omap-gpmc.c l &= ~mask; mask 439 drivers/memory/omap-gpmc.c int mask; mask 444 drivers/memory/omap-gpmc.c mask = (1 << nr_bits) - 1; mask 445 drivers/memory/omap-gpmc.c l = (l >> st_bit) & mask; mask 447 drivers/memory/omap-gpmc.c max = mask; mask 607 drivers/memory/omap-gpmc.c int ticks, mask, nr_bits; mask 614 drivers/memory/omap-gpmc.c mask = (1 << nr_bits) - 1; mask 617 drivers/memory/omap-gpmc.c max = mask; mask 631 drivers/memory/omap-gpmc.c (l >> st_bit) & mask, time); mask 633 drivers/memory/omap-gpmc.c l &= ~(mask << st_bit); mask 804 drivers/memory/omap-gpmc.c u32 mask; mask 814 drivers/memory/omap-gpmc.c mask = (1 << GPMC_SECTION_SHIFT) - size; mask 815 drivers/memory/omap-gpmc.c mask >>= GPMC_CHUNK_SHIFT; mask 816 drivers/memory/omap-gpmc.c mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; mask 821 drivers/memory/omap-gpmc.c l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; mask 849 drivers/memory/omap-gpmc.c u32 mask; mask 853 drivers/memory/omap-gpmc.c mask = (l >> 8) & 0x0f; mask 854 drivers/memory/omap-gpmc.c *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); mask 293 drivers/memory/pl172.c .mask = 0x3f0fffff, mask 298 drivers/memory/pl172.c .mask = 0x3f0fffff, mask 303 drivers/memory/pl172.c .mask = 0xff0fffff, mask 442 drivers/memory/pl353-smc.c .mask = 0x000fffff, mask 299 drivers/memory/tegra/mc.c value &= ~(la->mask << la->shift); mask 300 drivers/memory/tegra/mc.c value |= (la->def & la->mask) << la->shift; mask 29 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 43 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 57 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 71 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 85 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 99 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 113 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 127 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 141 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 155 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 169 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 183 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 197 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 211 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 225 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 239 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 253 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 267 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 281 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 295 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 309 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 323 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 337 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 351 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 365 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 379 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 393 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 403 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 413 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 427 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 441 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 455 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 469 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 483 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 497 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 511 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 525 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 539 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 553 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 567 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 581 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 595 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 609 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 623 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 633 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 643 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 657 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 671 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 685 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 699 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 713 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 727 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 741 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 755 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 769 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 783 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 797 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 811 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 825 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 839 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 849 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 859 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 873 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 887 drivers/memory/tegra/tegra114.c .mask = 0xff, mask 564 drivers/memory/tegra/tegra124-emc.c u32 val, val2, mask; mask 592 drivers/memory/tegra/tegra124-emc.c mask = EMC_SEL_DPD_CTRL_DDR3_MASK; mask 594 drivers/memory/tegra/tegra124-emc.c mask = EMC_SEL_DPD_CTRL_MASK; mask 597 drivers/memory/tegra/tegra124-emc.c if (val & mask) { mask 598 drivers/memory/tegra/tegra124-emc.c val &= ~mask; mask 49 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 63 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 77 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 91 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 105 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 119 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 133 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 147 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 161 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 175 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 189 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 203 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 217 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 231 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 245 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 259 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 273 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 287 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 301 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 315 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 329 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 339 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 349 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 363 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 377 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 391 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 405 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 419 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 429 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 439 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 453 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 467 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 481 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 495 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 509 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 523 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 537 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 551 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 565 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 579 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 593 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 607 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 621 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 635 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 649 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 663 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 677 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 691 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 705 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 719 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 733 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 748 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 763 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 777 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 791 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 805 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 819 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 833 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 847 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 861 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 875 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 889 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 903 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 917 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 931 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 945 drivers/memory/tegra/tegra124.c .mask = 0xff, mask 26 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 40 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 54 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 68 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 82 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 96 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 110 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 124 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 138 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 152 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 166 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 180 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 194 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 208 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 222 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 236 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 250 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 260 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 274 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 288 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 302 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 316 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 330 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 340 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 354 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 368 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 382 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 396 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 410 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 424 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 438 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 452 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 466 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 480 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 494 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 508 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 522 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 536 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 550 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 564 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 578 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 593 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 608 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 622 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 636 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 650 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 664 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 678 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 692 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 706 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 720 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 734 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 748 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 762 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 776 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 790 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 804 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 818 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 832 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 846 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 860 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 874 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 888 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 902 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 916 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 930 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 944 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 958 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 972 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 986 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 1001 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 1016 drivers/memory/tegra/tegra210.c .mask = 0xff, mask 29 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 43 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 57 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 71 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 85 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 99 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 113 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 127 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 141 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 155 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 169 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 183 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 197 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 211 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 225 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 239 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 253 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 267 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 281 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 295 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 309 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 323 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 337 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 351 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 365 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 379 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 393 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 407 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 421 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 435 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 449 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 463 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 477 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 491 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 505 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 519 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 533 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 543 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 553 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 567 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 581 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 595 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 609 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 623 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 637 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 651 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 665 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 679 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 693 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 707 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 721 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 735 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 749 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 763 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 777 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 787 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 797 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 811 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 825 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 839 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 853 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 867 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 881 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 895 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 909 drivers/memory/tegra/tegra30.c .mask = 0xff, mask 88 drivers/memstick/host/r592.c int address, u32 mask) mask 91 drivers/memstick/host/r592.c dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg); mask 92 drivers/memstick/host/r592.c writel(reg | mask , dev->mmio + address); mask 97 drivers/memstick/host/r592.c int address, u32 mask) mask 101 drivers/memstick/host/r592.c address, ~mask, reg, mask); mask 102 drivers/memstick/host/r592.c writel(reg & ~mask, dev->mmio + address); mask 107 drivers/memstick/host/r592.c static int r592_wait_status(struct r592_device *dev, u32 mask, u32 wanted_mask) mask 112 drivers/memstick/host/r592.c if ((reg & mask) == wanted_mask) mask 119 drivers/memstick/host/r592.c if ((reg & mask) == wanted_mask) mask 170 drivers/mfd/88pm800.c .mask = PM800_ONKEY_INT_ENA1, mask 173 drivers/mfd/88pm800.c .mask = PM800_EXTON_INT_ENA1, mask 176 drivers/mfd/88pm800.c .mask = PM800_CHG_INT_ENA1, mask 179 drivers/mfd/88pm800.c .mask = PM800_BAT_INT_ENA1, mask 182 drivers/mfd/88pm800.c .mask = PM800_RTC_INT_ENA1, mask 185 drivers/mfd/88pm800.c .mask = PM800_CLASSD_OC_INT_ENA1, mask 190 drivers/mfd/88pm800.c .mask = PM800_VBAT_INT_ENA2, mask 194 drivers/mfd/88pm800.c .mask = PM800_VSYS_INT_ENA2, mask 198 drivers/mfd/88pm800.c .mask = PM800_VCHG_INT_ENA2, mask 202 drivers/mfd/88pm800.c .mask = PM800_TINT_INT_ENA2, mask 207 drivers/mfd/88pm800.c .mask = PM800_GPADC0_INT_ENA3, mask 211 drivers/mfd/88pm800.c .mask = PM800_GPADC1_INT_ENA3, mask 215 drivers/mfd/88pm800.c .mask = PM800_GPADC2_INT_ENA3, mask 219 drivers/mfd/88pm800.c .mask = PM800_GPADC3_INT_ENA3, mask 223 drivers/mfd/88pm800.c .mask = PM800_GPADC4_INT_ENA3, mask 228 drivers/mfd/88pm800.c .mask = PM800_GPIO0_INT_ENA4, mask 232 drivers/mfd/88pm800.c .mask = PM800_GPIO1_INT_ENA4, mask 236 drivers/mfd/88pm800.c .mask = PM800_GPIO2_INT_ENA4, mask 240 drivers/mfd/88pm800.c .mask = PM800_GPIO3_INT_ENA4, mask 244 drivers/mfd/88pm800.c .mask = PM800_GPIO4_INT_ENA4, mask 253 drivers/mfd/88pm800.c int data = 0, mask = 0, ret = 0; mask 293 drivers/mfd/88pm800.c mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 | mask 303 drivers/mfd/88pm800.c ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data); mask 370 drivers/mfd/88pm800.c int data, mask, ret = -EINVAL; mask 381 drivers/mfd/88pm800.c mask = mask 386 drivers/mfd/88pm800.c ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data); mask 92 drivers/mfd/88pm805.c .mask = PM805_INT1_HP1_SHRT, mask 95 drivers/mfd/88pm805.c .mask = PM805_INT1_HP2_SHRT, mask 98 drivers/mfd/88pm805.c .mask = PM805_INT1_MIC_CONFLICT, mask 101 drivers/mfd/88pm805.c .mask = PM805_INT1_CLIP_FAULT, mask 104 drivers/mfd/88pm805.c .mask = PM805_INT1_LDO_OFF, mask 107 drivers/mfd/88pm805.c .mask = PM805_INT1_SRC_DPLL_LOCK, mask 112 drivers/mfd/88pm805.c .mask = PM805_INT2_MIC_DET, mask 116 drivers/mfd/88pm805.c .mask = PM805_INT2_SHRT_BTN_DET, mask 120 drivers/mfd/88pm805.c .mask = PM805_INT2_VOLM_BTN_DET, mask 124 drivers/mfd/88pm805.c .mask = PM805_INT2_VOLP_BTN_DET, mask 128 drivers/mfd/88pm805.c .mask = PM805_INT2_RAW_PLL_FAULT, mask 132 drivers/mfd/88pm805.c .mask = PM805_INT2_FINE_PLL_FAULT, mask 140 drivers/mfd/88pm805.c int data, mask, ret = -EINVAL; mask 151 drivers/mfd/88pm805.c mask = mask 156 drivers/mfd/88pm805.c ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data); mask 496 drivers/mfd/88pm860x-core.c unsigned char mask[3]; mask 502 drivers/mfd/88pm860x-core.c mask[i] = cached[i]; mask 507 drivers/mfd/88pm860x-core.c mask[0] &= ~irq_data->offs; mask 508 drivers/mfd/88pm860x-core.c mask[0] |= irq_data->enable; mask 511 drivers/mfd/88pm860x-core.c mask[1] &= ~irq_data->offs; mask 512 drivers/mfd/88pm860x-core.c mask[1] |= irq_data->enable; mask 515 drivers/mfd/88pm860x-core.c mask[2] &= ~irq_data->offs; mask 516 drivers/mfd/88pm860x-core.c mask[2] |= irq_data->enable; mask 525 drivers/mfd/88pm860x-core.c if (mask[i] != cached[i]) { mask 526 drivers/mfd/88pm860x-core.c cached[i] = mask[i]; mask 527 drivers/mfd/88pm860x-core.c pm860x_reg_write(i2c, PM8607_INT_MASK_1 + i, mask[i]); mask 574 drivers/mfd/88pm860x-core.c int data, mask, ret = -EINVAL; mask 578 drivers/mfd/88pm860x-core.c mask = PM8607_B0_MISC1_INV_INT | PM8607_B0_MISC1_INT_CLEAR mask 591 drivers/mfd/88pm860x-core.c ret = pm860x_set_bits(i2c, PM8607_B0_MISC1, mask, data); mask 71 drivers/mfd/88pm860x-i2c.c unsigned char mask, unsigned char data) mask 78 drivers/mfd/88pm860x-i2c.c ret = regmap_update_bits(map, reg, mask, data); mask 175 drivers/mfd/aat2870-core.c static int aat2870_update(struct aat2870_data *aat2870, u8 addr, u8 mask, mask 188 drivers/mfd/aat2870-core.c new_val = (old_val & ~mask) | (val & mask); mask 176 drivers/mfd/ab8500-core.c static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask, mask 182 drivers/mfd/ab8500-core.c &mask, 1); mask 358 drivers/mfd/ab8500-core.c u8 new = ab8500->mask[i]; mask 389 drivers/mfd/ab8500-core.c int mask = 1 << (offset % 8); mask 391 drivers/mfd/ab8500-core.c ab8500->mask[index] |= mask; mask 395 drivers/mfd/ab8500-core.c ab8500->mask[index + 2] |= mask; mask 397 drivers/mfd/ab8500-core.c ab8500->mask[index + 1] |= mask; mask 400 drivers/mfd/ab8500-core.c ab8500->mask[index] |= (mask << 1); mask 409 drivers/mfd/ab8500-core.c int mask = 1 << (offset % 8); mask 412 drivers/mfd/ab8500-core.c ab8500->mask[index] &= ~mask; mask 417 drivers/mfd/ab8500-core.c ab8500->mask[index + 2] &= ~mask; mask 420 drivers/mfd/ab8500-core.c ab8500->mask[index + 1] &= ~mask; mask 424 drivers/mfd/ab8500-core.c ab8500->mask[index] &= ~(mask << 1); mask 426 drivers/mfd/ab8500-core.c ab8500->mask[index] &= ~mask; mask 429 drivers/mfd/ab8500-core.c ab8500->mask[index] &= ~mask; mask 476 drivers/mfd/ab8500-core.c latch_val &= ~ab8500->mask[i]; mask 919 drivers/mfd/ab8500-core.c void ab8500_override_turn_on_stat(u8 mask, u8 set) mask 922 drivers/mfd/ab8500-core.c turn_on_stat_mask = mask; mask 1170 drivers/mfd/ab8500-core.c ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size, mask 1172 drivers/mfd/ab8500-core.c if (!ab8500->mask) mask 1260 drivers/mfd/ab8500-core.c ab8500->mask[i] = ab8500->oldmask[i] = 0xff; mask 140 drivers/mfd/ab8500-debugfs.c unsigned long mask; /* read/write mask, applied before any bit shift */ mask 150 drivers/mfd/ab8500-debugfs.c .mask = 0xFFFFFFFF, /* default: no mask */ mask 1571 drivers/mfd/ab8500-debugfs.c regvalue &= hwreg_cfg.mask; mask 2318 drivers/mfd/ab8500-debugfs.c .mask = 0xFFFFFFFF, /* default: no mask */ mask 2351 drivers/mfd/ab8500-debugfs.c ret = kstrtoul(b, 0, &loc.mask); mask 2397 drivers/mfd/ab8500-debugfs.c cfg->addr, cfg->mask, cfg->shift, val); mask 2412 drivers/mfd/ab8500-debugfs.c regvalue &= ~(cfg->mask << (cfg->shift)); mask 2413 drivers/mfd/ab8500-debugfs.c val = (val & cfg->mask) << (cfg->shift); mask 2415 drivers/mfd/ab8500-debugfs.c regvalue &= ~(cfg->mask >> (-cfg->shift)); mask 2416 drivers/mfd/ab8500-debugfs.c val = (val & cfg->mask) >> (-cfg->shift); mask 115 drivers/mfd/ab8500-sysctrl.c int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) mask 129 drivers/mfd/ab8500-sysctrl.c (u8)(reg & 0xFF), mask, value); mask 249 drivers/mfd/arizona-core.c unsigned int mask, unsigned int target) mask 258 drivers/mfd/arizona-core.c if ((val & mask) == target) mask 72 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_LID, mask 75 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_ACOK, mask 78 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_ENABLE1, mask 81 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0, mask 84 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG, mask 87 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_ONKEY, mask 90 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_OVTMP, mask 93 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK1_LOWBAT, mask 98 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_SD0_LV, mask 102 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_SD1_LV, mask 106 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_SD2345_LV, mask 110 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT, mask 114 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT, mask 118 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_ENABLE2, mask 122 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_SD6_LV, mask 126 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK2_RTC_REP, mask 132 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_RTC_ALARM, mask 136 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_GPIO1, mask 140 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_GPIO2, mask 144 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_GPIO3, mask 148 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_GPIO4, mask 152 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_GPIO5, mask 156 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_WATCHDOG, mask 160 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK3_ENABLE3, mask 166 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN, mask 170 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN, mask 174 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN, mask 178 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM, mask 182 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM, mask 186 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM, mask 190 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6, mask 194 drivers/mfd/as3722.c .mask = AS3722_INTERRUPT_MASK4_ADC, mask 442 drivers/mfd/asic3.c u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg; mask 462 drivers/mfd/asic3.c out_reg |= mask; mask 464 drivers/mfd/asic3.c out_reg &= ~mask; mask 490 drivers/mfd/asic3.c u32 mask = ASIC3_GPIO_TO_MASK(offset); mask 503 drivers/mfd/asic3.c gpio_base + ASIC3_GPIO_STATUS) & mask); mask 509 drivers/mfd/asic3.c u32 mask, out_reg; mask 523 drivers/mfd/asic3.c mask = ASIC3_GPIO_TO_MASK(offset); mask 530 drivers/mfd/asic3.c out_reg |= mask; mask 532 drivers/mfd/asic3.c out_reg &= ~mask; mask 284 drivers/mfd/axp20x.c [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } mask 36 drivers/mfd/cs47l24-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 37 drivers/mfd/cs47l24-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 40 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 mask 43 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 mask 46 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 mask 49 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 mask 52 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 mask 55 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 mask 58 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 mask 61 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 mask 64 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 mask 67 drivers/mfd/cs47l24-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 mask 71 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 74 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 77 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 80 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 mask 83 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 86 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 mask 89 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 mask 92 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 95 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 98 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 101 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 104 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 107 drivers/mfd/cs47l24-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 111 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 mask 114 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 mask 117 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 mask 120 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 mask 123 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 mask 126 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 mask 129 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 mask 132 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 mask 135 drivers/mfd/cs47l24-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 mask 139 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 142 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 mask 145 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 148 drivers/mfd/cs47l24-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 152 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 mask 155 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 mask 158 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 mask 161 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 mask 164 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 mask 167 drivers/mfd/cs47l24-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 mask 214 drivers/mfd/da903x.c int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) mask 226 drivers/mfd/da903x.c if ((reg_val & mask) != val) { mask 227 drivers/mfd/da903x.c reg_val = (reg_val & ~mask) | val; mask 38 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_1, mask 42 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_2, mask 46 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_3, mask 50 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_4, mask 54 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_5, mask 58 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_6, mask 62 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_7, mask 66 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_8, mask 70 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_1, mask 74 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_2, mask 78 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_3, mask 82 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_4, mask 86 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_5, mask 90 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_6, mask 94 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_7, mask 98 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_8, mask 102 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_1, mask 106 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_2, mask 110 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_3, mask 114 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_4, mask 118 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_5, mask 122 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_6, mask 126 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_7, mask 130 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_8, mask 134 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_1, mask 138 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_2, mask 142 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_3, mask 146 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_4, mask 150 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_5, mask 154 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_6, mask 158 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_7, mask 162 drivers/mfd/da9052-irq.c .mask = DA9052_IRQ_MASK_POS_8, mask 224 drivers/mfd/da9055-core.c .mask = DA9055_IRQ_NONKEY_MASK, mask 228 drivers/mfd/da9055-core.c .mask = DA9055_IRQ_ALM_MASK, mask 232 drivers/mfd/da9055-core.c .mask = DA9055_IRQ_TICK_MASK, mask 236 drivers/mfd/da9055-core.c .mask = DA9055_IRQ_ADC_MASK, mask 240 drivers/mfd/da9055-core.c .mask = DA9055_IRQ_BUCK_ILIM_MASK, mask 28 drivers/mfd/da9062-core.c .mask = DA9062AA_M_NONKEY_MASK, mask 32 drivers/mfd/da9062-core.c .mask = DA9062AA_M_WDG_WARN_MASK, mask 36 drivers/mfd/da9062-core.c .mask = DA9062AA_M_SEQ_RDY_MASK, mask 41 drivers/mfd/da9062-core.c .mask = DA9062AA_M_TEMP_MASK, mask 45 drivers/mfd/da9062-core.c .mask = DA9062AA_M_LDO_LIM_MASK, mask 49 drivers/mfd/da9062-core.c .mask = DA9062AA_M_DVC_RDY_MASK, mask 53 drivers/mfd/da9062-core.c .mask = DA9062AA_M_VDD_WARN_MASK, mask 58 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI0_MASK, mask 62 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI1_MASK, mask 66 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI2_MASK, mask 70 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI3_MASK, mask 74 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI4_MASK, mask 92 drivers/mfd/da9062-core.c .mask = DA9062AA_M_NONKEY_MASK, mask 96 drivers/mfd/da9062-core.c .mask = DA9062AA_M_ALARM_MASK, mask 100 drivers/mfd/da9062-core.c .mask = DA9062AA_M_TICK_MASK, mask 104 drivers/mfd/da9062-core.c .mask = DA9062AA_M_WDG_WARN_MASK, mask 108 drivers/mfd/da9062-core.c .mask = DA9062AA_M_SEQ_RDY_MASK, mask 113 drivers/mfd/da9062-core.c .mask = DA9062AA_M_TEMP_MASK, mask 117 drivers/mfd/da9062-core.c .mask = DA9062AA_M_LDO_LIM_MASK, mask 121 drivers/mfd/da9062-core.c .mask = DA9062AA_M_DVC_RDY_MASK, mask 125 drivers/mfd/da9062-core.c .mask = DA9062AA_M_VDD_WARN_MASK, mask 130 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI0_MASK, mask 134 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI1_MASK, mask 138 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI2_MASK, mask 142 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI3_MASK, mask 146 drivers/mfd/da9062-core.c .mask = DA9062AA_M_GPI4_MASK, mask 223 drivers/mfd/da9150-core.c void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val) mask 227 drivers/mfd/da9150-core.c ret = regmap_update_bits(da9150->regmap, reg, mask, val); mask 259 drivers/mfd/da9150-core.c .mask = DA9150_E_VBUS_MASK, mask 263 drivers/mfd/da9150-core.c .mask = DA9150_E_CHG_MASK, mask 267 drivers/mfd/da9150-core.c .mask = DA9150_E_TCLASS_MASK, mask 271 drivers/mfd/da9150-core.c .mask = DA9150_E_TJUNC_MASK, mask 275 drivers/mfd/da9150-core.c .mask = DA9150_E_VFAULT_MASK, mask 279 drivers/mfd/da9150-core.c .mask = DA9150_E_CONF_MASK, mask 283 drivers/mfd/da9150-core.c .mask = DA9150_E_DAT_MASK, mask 287 drivers/mfd/da9150-core.c .mask = DA9150_E_DTYPE_MASK, mask 291 drivers/mfd/da9150-core.c .mask = DA9150_E_ID_MASK, mask 295 drivers/mfd/da9150-core.c .mask = DA9150_E_ADP_MASK, mask 299 drivers/mfd/da9150-core.c .mask = DA9150_E_SESS_END_MASK, mask 303 drivers/mfd/da9150-core.c .mask = DA9150_E_SESS_VLD_MASK, mask 307 drivers/mfd/da9150-core.c .mask = DA9150_E_FG_MASK, mask 311 drivers/mfd/da9150-core.c .mask = DA9150_E_GP_MASK, mask 315 drivers/mfd/da9150-core.c .mask = DA9150_E_TBAT_MASK, mask 319 drivers/mfd/da9150-core.c .mask = DA9150_E_GPIOA_MASK, mask 323 drivers/mfd/da9150-core.c .mask = DA9150_E_GPIOB_MASK, mask 327 drivers/mfd/da9150-core.c .mask = DA9150_E_GPIOC_MASK, mask 331 drivers/mfd/da9150-core.c .mask = DA9150_E_GPIOD_MASK, mask 335 drivers/mfd/da9150-core.c .mask = DA9150_E_GPADC_MASK, mask 339 drivers/mfd/da9150-core.c .mask = DA9150_E_WKUP_MASK, mask 654 drivers/mfd/db8500-prcmu.c void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) mask 661 drivers/mfd/db8500-prcmu.c val = ((val & ~mask) | (value & mask)); mask 732 drivers/mfd/db8500-prcmu.c u32 mask; mask 744 drivers/mfd/db8500-prcmu.c mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK); mask 749 drivers/mfd/db8500-prcmu.c mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK | mask 754 drivers/mfd/db8500-prcmu.c bits &= mask; mask 761 drivers/mfd/db8500-prcmu.c if ((val & mask) != bits) { mask 766 drivers/mfd/db8500-prcmu.c if ((val & mask & ~div_mask) != bits) { mask 772 drivers/mfd/db8500-prcmu.c writel((bits | (val & ~mask)), PRCM_CLKOCR); mask 2222 drivers/mfd/db8500-prcmu.c int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size) mask 2234 drivers/mfd/db8500-prcmu.c writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5)); mask 2268 drivers/mfd/db8500-prcmu.c u8 mask = ~0; mask 2270 drivers/mfd/db8500-prcmu.c return prcmu_abb_write_masked(slave, reg, value, &mask, size); mask 151 drivers/mfd/dm355evm_msp.c int mask, bits; mask 160 drivers/mfd/dm355evm_msp.c mask = MSP_GPIO_MASK(offset); mask 163 drivers/mfd/dm355evm_msp.c bits &= ~mask; mask 165 drivers/mfd/dm355evm_msp.c bits |= mask; mask 58 drivers/mfd/exynos-lpass.c static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) mask 64 drivers/mfd/exynos-lpass.c val &= ~mask; mask 69 drivers/mfd/exynos-lpass.c val |= mask; mask 109 drivers/mfd/ezx-pcap.c int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) mask 121 drivers/mfd/ezx-pcap.c tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask); mask 122 drivers/mfd/ezx-pcap.c tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT | mask 25 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = OTMP_D1R_INT_MASK }, mask 26 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_2P5_R_INT_MASK }, mask 27 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_UV_D3R_INT_MASK }, mask 28 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT_MASK }, mask 29 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D4SR_INT_MASK }, mask 30 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D20F_INT_MASK }, mask 31 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = PWRON_D20R_INT_MASK }, mask 32 drivers/mfd/hi655x-pmic.c { .reg_offset = 0, .mask = RESERVE_INT_MASK }, mask 207 drivers/mfd/intel_msic.c int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask) mask 209 drivers/mfd/intel_msic.c return intel_scu_ipc_update_register(reg, val, mask); mask 119 drivers/mfd/lm3533-core.c int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask) mask 123 drivers/mfd/lm3533-core.c dev_dbg(lm3533->dev, "update [%02x]: %02x/%02x\n", reg, val, mask); mask 125 drivers/mfd/lm3533-core.c ret = regmap_update_bits(lm3533->regmap, reg, mask, val); mask 170 drivers/mfd/lm3533-core.c u8 mask; mask 181 drivers/mfd/lm3533-core.c mask = LM3533_BL_ID_MASK << shift; mask 184 drivers/mfd/lm3533-core.c ret = lm3533_update(lm3533, LM3533_REG_OUTPUT_CONF1, val, mask); mask 198 drivers/mfd/lm3533-core.c u8 mask; mask 216 drivers/mfd/lm3533-core.c mask = LM3533_LED_ID_MASK << shift; mask 219 drivers/mfd/lm3533-core.c ret = lm3533_update(lm3533, reg, val, mask); mask 264 drivers/mfd/lm3533-core.c u8 mask; mask 271 drivers/mfd/lm3533-core.c mask = LM3533_BL_ID_MASK << shift; mask 280 drivers/mfd/lm3533-core.c mask = LM3533_LED_ID_MASK << shift; mask 287 drivers/mfd/lm3533-core.c val = (val & mask) >> shift; mask 36 drivers/mfd/lm3533-ctrlbank.c u8 mask; mask 41 drivers/mfd/lm3533-ctrlbank.c mask = 1 << cb->id; mask 43 drivers/mfd/lm3533-ctrlbank.c mask, mask); mask 53 drivers/mfd/lm3533-ctrlbank.c u8 mask; mask 58 drivers/mfd/lm3533-ctrlbank.c mask = 1 << cb->id; mask 59 drivers/mfd/lm3533-ctrlbank.c ret = lm3533_update(cb->lm3533, LM3533_REG_CTRLBANK_ENABLE, 0, mask); mask 93 drivers/mfd/lp3943.c int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data) mask 95 drivers/mfd/lp3943.c return regmap_update_bits(lp3943->regmap, reg, mask, data); mask 87 drivers/mfd/lp8788-irq.c u8 addr, mask, val; mask 90 drivers/mfd/lp8788-irq.c mask = _irq_to_mask(irq); mask 93 drivers/mfd/lp8788-irq.c lp8788_update_bits(irqd->lp, addr, mask, val); mask 110 drivers/mfd/lp8788-irq.c u8 status[NUM_REGS], addr, mask; mask 119 drivers/mfd/lp8788-irq.c mask = _irq_to_mask(i); mask 122 drivers/mfd/lp8788-irq.c if (status[addr] & mask) { mask 150 drivers/mfd/lp8788.c int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data) mask 152 drivers/mfd/lp8788.c return regmap_update_bits(lp->regmap, reg, mask, data); mask 193 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, }, mask 194 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, }, mask 195 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, }, mask 197 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, }, mask 198 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, }, mask 199 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, }, mask 200 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, }, mask 201 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, }, mask 203 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, }, mask 204 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, }, mask 205 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, }, mask 206 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, }, mask 221 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, }, mask 222 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, }, mask 223 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, }, mask 224 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, }, mask 226 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, }, mask 227 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, }, mask 228 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, }, mask 229 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, }, mask 230 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, }, mask 231 drivers/mfd/max14577.c { .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, }, mask 233 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, }, mask 234 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, }, mask 235 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, }, mask 236 drivers/mfd/max14577.c { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, }, mask 250 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T120C_MASK, }, mask 251 drivers/mfd/max14577.c { .reg_offset = 0, .mask = MAX77836_TOPSYS_INT_T140C_MASK, }, mask 314 drivers/mfd/max77620.c unsigned int mask = 0, config = 0; mask 349 drivers/mfd/max77620.c mask |= MAX77620_FPS_TIME_PERIOD_MASK; mask 370 drivers/mfd/max77620.c mask |= MAX77620_FPS_EN_SRC_MASK; mask 373 drivers/mfd/max77620.c mask |= MAX77620_FPS_ENFPS_SW_MASK; mask 391 drivers/mfd/max77620.c mask, config); mask 100 drivers/mfd/max77650.c .mask = MAX77650_INT_GPI_MSK, mask 117 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_PWRONF_MSK, }, mask 118 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_PWRONR_MSK, }, mask 119 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBF_MSK, }, mask 120 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_JIGONBR_MSK, }, mask 121 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBF_MSK, }, mask 122 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ACOKBR_MSK, }, mask 123 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_ONKEY1S_MSK, }, mask 124 drivers/mfd/max77686.c { .reg_offset = 0, .mask = MAX77686_INT1_MRSTB_MSK, }, mask 126 drivers/mfd/max77686.c { .reg_offset = 1, .mask = MAX77686_INT2_140C_MSK, }, mask 127 drivers/mfd/max77686.c { .reg_offset = 1, .mask = MAX77686_INT2_120C_MSK, }, mask 58 drivers/mfd/max77693.c { .mask = LED_IRQ_FLED2_OPEN, }, mask 59 drivers/mfd/max77693.c { .mask = LED_IRQ_FLED2_SHORT, }, mask 60 drivers/mfd/max77693.c { .mask = LED_IRQ_FLED1_OPEN, }, mask 61 drivers/mfd/max77693.c { .mask = LED_IRQ_FLED1_SHORT, }, mask 62 drivers/mfd/max77693.c { .mask = LED_IRQ_MAX_FLASH, }, mask 76 drivers/mfd/max77693.c { .mask = TOPSYS_IRQ_T120C_INT, }, mask 77 drivers/mfd/max77693.c { .mask = TOPSYS_IRQ_T140C_INT, }, mask 78 drivers/mfd/max77693.c { .mask = TOPSYS_IRQ_LOWSYS_INT, }, mask 92 drivers/mfd/max77693.c { .mask = CHG_IRQ_BYP_I, }, mask 93 drivers/mfd/max77693.c { .mask = CHG_IRQ_THM_I, }, mask 94 drivers/mfd/max77693.c { .mask = CHG_IRQ_BAT_I, }, mask 95 drivers/mfd/max77693.c { .mask = CHG_IRQ_CHG_I, }, mask 96 drivers/mfd/max77693.c { .mask = CHG_IRQ_CHGIN_I, }, mask 116 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, }, mask 117 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, }, mask 118 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, }, mask 119 drivers/mfd/max77693.c { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, }, mask 121 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, }, mask 122 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, }, mask 123 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, }, mask 124 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, }, mask 125 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, }, mask 126 drivers/mfd/max77693.c { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, }, mask 128 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, }, mask 129 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, }, mask 130 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, }, mask 131 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, }, mask 132 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, }, mask 133 drivers/mfd/max77693.c { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, }, mask 52 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSUVLO_INT, }, mask 53 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_SYSOVLO_INT, }, mask 54 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TSHDN_INT, }, mask 55 drivers/mfd/max77843.c { .reg_offset = 0, .mask = MAX77843_SYS_IRQ_TM_INT, }, mask 116 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 0, }, mask 117 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 1, }, mask 118 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, mask 119 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 0, }, mask 120 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 1, }, mask 121 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 2, }, mask 122 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 3, }, mask 123 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 4, }, mask 124 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 5, }, mask 125 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 6, }, mask 126 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 7, }, mask 141 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 0, }, mask 142 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 1, }, mask 143 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, mask 144 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 3, }, mask 145 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 4, }, mask 146 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 5, }, mask 147 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 6, }, mask 148 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 7, }, mask 149 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 0, }, mask 150 drivers/mfd/max8907.c { .reg_offset = 1, .mask = 1 << 1, }, mask 164 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 2, }, mask 165 drivers/mfd/max8907.c { .reg_offset = 0, .mask = 1 << 3, }, mask 109 drivers/mfd/max8925-i2c.c unsigned char mask, unsigned char data) mask 119 drivers/mfd/max8925-i2c.c value &= ~mask; mask 50 drivers/mfd/max8997-irq.c int mask; mask 55 drivers/mfd/max8997-irq.c [(idx)] = { .group = (_group), .mask = (_mask) } mask 140 drivers/mfd/max8997-irq.c max8997->irq_masks_cur[irq_data->group] |= irq_data->mask; mask 149 drivers/mfd/max8997-irq.c max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask; mask 258 drivers/mfd/max8997-irq.c if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) { mask 105 drivers/mfd/max8997.c int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) mask 114 drivers/mfd/max8997.c u8 new_val = (val & mask) | (old_val & (~mask)); mask 16 drivers/mfd/max8998-irq.c int mask; mask 22 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_DCINF_MASK, mask 26 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_DCINR_MASK, mask 30 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_JIGF_MASK, mask 34 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_JIGR_MASK, mask 38 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_PWRONF_MASK, mask 42 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_PWRONR_MASK, mask 46 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_WTSREVNT_MASK, mask 50 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_SMPLEVNT_MASK, mask 54 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_ALARM1_MASK, mask 58 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_ALARM0_MASK, mask 62 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_ONKEY1S_MASK, mask 66 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_TOPOFFR_MASK, mask 70 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_DCINOVPR_MASK, mask 74 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_CHGRSTF_MASK, mask 78 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_DONER_MASK, mask 82 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_CHGFAULT_MASK, mask 86 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_LOBAT1_MASK, mask 90 drivers/mfd/max8998-irq.c .mask = MAX8998_IRQ_LOBAT2_MASK, mask 132 drivers/mfd/max8998-irq.c max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; mask 140 drivers/mfd/max8998-irq.c max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; mask 172 drivers/mfd/max8998-irq.c if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) { mask 101 drivers/mfd/max8998.c int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) mask 110 drivers/mfd/max8998.c u8 new_val = (val & mask) | (old_val & (~mask)); mask 92 drivers/mfd/mc13xxx-core.c u32 mask, u32 val) mask 94 drivers/mfd/mc13xxx-core.c BUG_ON(val & ~mask); mask 96 drivers/mfd/mc13xxx-core.c offset, val, mask); mask 98 drivers/mfd/mc13xxx-core.c return regmap_update_bits(mc13xxx->regmap, offset, mask, val); mask 134 drivers/mfd/mc13xxx-core.c u32 mask; mask 136 drivers/mfd/mc13xxx-core.c ret = mc13xxx_reg_read(mc13xxx, offmask, &mask); mask 140 drivers/mfd/mc13xxx-core.c *enabled = mask & irqbit; mask 177 drivers/mfd/mc13xxx-core.c #define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask)) mask 442 drivers/mfd/mc13xxx-core.c mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG); mask 165 drivers/mfd/menelaus.c void (*mmc_callback)(void *data, u8 mask); mask 38 drivers/mfd/motorola-cpcap.c int mask = BIT(irq % CPCAP_REGISTER_BITS); mask 49 drivers/mfd/motorola-cpcap.c return !!(val & mask); mask 127 drivers/mfd/motorola-cpcap.c unsigned int bit, mask; mask 134 drivers/mfd/motorola-cpcap.c mask = (1 << bit); mask 137 drivers/mfd/motorola-cpcap.c rirq->mask = mask; mask 47 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 50 drivers/mfd/palmas.c .mask = TPS65917_INT1_STATUS_PWRON, mask 53 drivers/mfd/palmas.c .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY, mask 56 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 59 drivers/mfd/palmas.c .mask = TPS65917_INT1_STATUS_PWRDOWN, mask 62 drivers/mfd/palmas.c .mask = TPS65917_INT1_STATUS_HOTDIE, mask 65 drivers/mfd/palmas.c .mask = TPS65917_INT1_STATUS_VSYS_MON, mask 68 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 72 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 76 drivers/mfd/palmas.c .mask = TPS65917_INT2_STATUS_OTP_ERROR, mask 80 drivers/mfd/palmas.c .mask = TPS65917_INT2_STATUS_WDT, mask 84 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 88 drivers/mfd/palmas.c .mask = TPS65917_INT2_STATUS_RESET_IN, mask 92 drivers/mfd/palmas.c .mask = TPS65917_INT2_STATUS_FSD, mask 96 drivers/mfd/palmas.c .mask = TPS65917_INT2_STATUS_SHORT, mask 100 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 105 drivers/mfd/palmas.c .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0, mask 109 drivers/mfd/palmas.c .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1, mask 113 drivers/mfd/palmas.c .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW, mask 117 drivers/mfd/palmas.c .mask = TPS65917_RESERVED6, mask 121 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 125 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 129 drivers/mfd/palmas.c .mask = TPS65917_RESERVED, mask 133 drivers/mfd/palmas.c .mask = TPS65917_INT3_STATUS_VBUS, mask 138 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_0, mask 142 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_1, mask 146 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_2, mask 150 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_3, mask 154 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_4, mask 158 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_5, mask 162 drivers/mfd/palmas.c .mask = TPS65917_INT4_STATUS_GPIO_6, mask 166 drivers/mfd/palmas.c .mask = TPS65917_RESERVED10, mask 174 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV, mask 177 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_PWRON, mask 180 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY, mask 183 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_RPWRON, mask 186 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_PWRDOWN, mask 189 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_HOTDIE, mask 192 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_VSYS_MON, mask 195 drivers/mfd/palmas.c .mask = PALMAS_INT1_STATUS_VBAT_MON, mask 199 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_RTC_ALARM, mask 203 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_RTC_TIMER, mask 207 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_WDT, mask 211 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_BATREMOVAL, mask 215 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_RESET_IN, mask 219 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_FBI_BB, mask 223 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_SHORT, mask 227 drivers/mfd/palmas.c .mask = PALMAS_INT2_STATUS_VAC_ACOK, mask 232 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0, mask 236 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1, mask 240 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW, mask 244 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT, mask 248 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_ID_OTG, mask 252 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_ID, mask 256 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_VBUS_OTG, mask 260 drivers/mfd/palmas.c .mask = PALMAS_INT3_STATUS_VBUS, mask 265 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_0, mask 269 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_1, mask 273 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_2, mask 277 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_3, mask 281 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_4, mask 285 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_5, mask 289 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_6, mask 293 drivers/mfd/palmas.c .mask = PALMAS_INT4_STATUS_GPIO_7, mask 67 drivers/mfd/pcf50633-core.c int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) mask 69 drivers/mfd/pcf50633-core.c return regmap_update_bits(pcf->regmap, reg, mask, val); mask 79 drivers/mfd/pcf50633-gpio.c u8 reg, val, mask; mask 85 drivers/mfd/pcf50633-gpio.c mask = 1 << (gpio - PCF50633_GPIO1); mask 87 drivers/mfd/pcf50633-gpio.c return pcf50633_reg_set_bit_mask(pcf, reg, mask, val); mask 50 drivers/mfd/pcf50633-irq.c static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) mask 59 drivers/mfd/pcf50633-irq.c pcf50633_reg_set_bit_mask(pcf, reg, bit, mask ? bit : 0); mask 63 drivers/mfd/pcf50633-irq.c if (mask) mask 70 drivers/mfd/retu-mfd.c .mask = 1 << RETU_INT_PWR, mask 106 drivers/mfd/retu-mfd.c .mask = 1 << TAHVO_INT_VBUS, mask 26 drivers/mfd/rk808.c int mask; mask 243 drivers/mfd/rk808.c .mask = RK805_IRQ_PWRON_RISE_MSK, mask 247 drivers/mfd/rk808.c .mask = RK805_IRQ_VB_LOW_MSK, mask 251 drivers/mfd/rk808.c .mask = RK805_IRQ_PWRON_MSK, mask 255 drivers/mfd/rk808.c .mask = RK805_IRQ_PWRON_LP_MSK, mask 259 drivers/mfd/rk808.c .mask = RK805_IRQ_HOTDIE_MSK, mask 263 drivers/mfd/rk808.c .mask = RK805_IRQ_RTC_ALARM_MSK, mask 267 drivers/mfd/rk808.c .mask = RK805_IRQ_RTC_PERIOD_MSK, mask 271 drivers/mfd/rk808.c .mask = RK805_IRQ_PWRON_FALL_MSK, mask 279 drivers/mfd/rk808.c .mask = RK808_IRQ_VOUT_LO_MSK, mask 283 drivers/mfd/rk808.c .mask = RK808_IRQ_VB_LO_MSK, mask 287 drivers/mfd/rk808.c .mask = RK808_IRQ_PWRON_MSK, mask 291 drivers/mfd/rk808.c .mask = RK808_IRQ_PWRON_LP_MSK, mask 295 drivers/mfd/rk808.c .mask = RK808_IRQ_HOTDIE_MSK, mask 299 drivers/mfd/rk808.c .mask = RK808_IRQ_RTC_ALARM_MSK, mask 303 drivers/mfd/rk808.c .mask = RK808_IRQ_RTC_PERIOD_MSK, mask 309 drivers/mfd/rk808.c .mask = RK808_IRQ_PLUG_IN_INT_MSK, mask 313 drivers/mfd/rk808.c .mask = RK808_IRQ_PLUG_OUT_INT_MSK, mask 321 drivers/mfd/rk808.c .mask = RK818_IRQ_VOUT_LO_MSK, mask 325 drivers/mfd/rk808.c .mask = RK818_IRQ_VB_LO_MSK, mask 329 drivers/mfd/rk808.c .mask = RK818_IRQ_PWRON_MSK, mask 333 drivers/mfd/rk808.c .mask = RK818_IRQ_PWRON_LP_MSK, mask 337 drivers/mfd/rk808.c .mask = RK818_IRQ_HOTDIE_MSK, mask 341 drivers/mfd/rk808.c .mask = RK818_IRQ_RTC_ALARM_MSK, mask 345 drivers/mfd/rk808.c .mask = RK818_IRQ_RTC_PERIOD_MSK, mask 349 drivers/mfd/rk808.c .mask = RK818_IRQ_USB_OV_MSK, mask 355 drivers/mfd/rk808.c .mask = RK818_IRQ_PLUG_IN_MSK, mask 359 drivers/mfd/rk808.c .mask = RK818_IRQ_PLUG_OUT_MSK, mask 363 drivers/mfd/rk808.c .mask = RK818_IRQ_CHG_OK_MSK, mask 367 drivers/mfd/rk808.c .mask = RK818_IRQ_CHG_TE_MSK, mask 371 drivers/mfd/rk808.c .mask = RK818_IRQ_CHG_TS1_MSK, mask 375 drivers/mfd/rk808.c .mask = RK818_IRQ_TS2_MSK, mask 379 drivers/mfd/rk808.c .mask = RK818_IRQ_CHG_CVTLIM_MSK, mask 383 drivers/mfd/rk808.c .mask = RK818_IRQ_DISCHG_ILIM_MSK, mask 671 drivers/mfd/rk808.c pre_init_reg[i].mask, mask 21 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_BUCKOCP, }, mask 22 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_BUCKLV, }, mask 23 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_SAFELDOLV, }, mask 24 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_LDOLV, }, mask 25 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_OT, }, mask 26 drivers/mfd/rt5033.c { .mask = RT5033_PMIC_IRQ_VDDA_UV, }, mask 475 drivers/mfd/sec-core.c unsigned int reg, mask; mask 483 drivers/mfd/sec-core.c mask = S2MPS11_CTRL1_PWRHOLD_MASK; mask 496 drivers/mfd/sec-core.c regmap_update_bits(sec_pmic->regmap_pmic, reg, mask, 0); mask 23 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONF_MASK, mask 27 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONR_MASK, mask 31 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBF_MASK, mask 35 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBR_MASK, mask 39 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBF_MASK, mask 43 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBR_MASK, mask 47 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRON1S_MASK, mask 51 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_MRB_MASK, mask 55 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC60S_MASK, mask 59 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA1_MASK, mask 63 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA0_MASK, mask 67 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_SMPL_MASK, mask 71 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC1S_MASK, mask 75 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_WTSR_MASK, mask 79 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT120C_MASK, mask 83 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT140C_MASK, mask 90 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONF_MASK, mask 94 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONR_MASK, mask 98 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBF_MASK, mask 102 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBR_MASK, mask 106 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBF_MASK, mask 110 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBR_MASK, mask 114 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRON1S_MASK, mask 118 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_MRB_MASK, mask 122 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC60S_MASK, mask 126 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA1_MASK, mask 130 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA0_MASK, mask 134 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_SMPL_MASK, mask 138 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC1S_MASK, mask 142 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_WTSR_MASK, mask 146 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT120C_MASK, mask 150 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT140C_MASK, mask 154 drivers/mfd/sec-irq.c .mask = S2MPS14_IRQ_TSD_MASK, mask 161 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONF_MASK, mask 165 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRONR_MASK, mask 169 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBF_MASK, mask 173 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_JIGONBR_MASK, mask 177 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBF_MASK, mask 181 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_ACOKBR_MASK, mask 185 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_PWRON1S_MASK, mask 189 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_MRB_MASK, mask 193 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC60S_MASK, mask 197 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA1_MASK, mask 201 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTCA0_MASK, mask 205 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_SMPL_MASK, mask 209 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_RTC1S_MASK, mask 213 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_WTSR_MASK, mask 217 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT120C_MASK, mask 221 drivers/mfd/sec-irq.c .mask = S2MPS11_IRQ_INT140C_MASK, mask 225 drivers/mfd/sec-irq.c .mask = S2MPS14_IRQ_TSD_MASK, mask 232 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_PWRR_MASK, mask 236 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_PWRF_MASK, mask 240 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_PWR1S_MASK, mask 244 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_JIGR_MASK, mask 248 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_JIGF_MASK, mask 252 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_LOWBAT2_MASK, mask 256 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_LOWBAT1_MASK, mask 260 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_MRB_MASK, mask 264 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_DVSOK2_MASK, mask 268 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_DVSOK3_MASK, mask 272 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_DVSOK4_MASK, mask 276 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_RTC60S_MASK, mask 280 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_RTCA1_MASK, mask 284 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_RTCA2_MASK, mask 288 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_SMPL_MASK, mask 292 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_RTC1S_MASK, mask 296 drivers/mfd/sec-irq.c .mask = S5M8767_IRQ_WTSR_MASK, mask 303 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_DCINF_MASK, mask 307 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_DCINR_MASK, mask 311 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_JIGF_MASK, mask 315 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_JIGR_MASK, mask 319 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_PWRONF_MASK, mask 323 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_PWRONR_MASK, mask 327 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_WTSREVNT_MASK, mask 331 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_SMPLEVNT_MASK, mask 335 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_ALARM1_MASK, mask 339 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_ALARM0_MASK, mask 343 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_ONKEY1S_MASK, mask 347 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_TOPOFFR_MASK, mask 351 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_DCINOVPR_MASK, mask 355 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_CHGRSTF_MASK, mask 359 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_DONER_MASK, mask 363 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_CHGFAULT_MASK, mask 367 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_LOBAT1_MASK, mask 371 drivers/mfd/sec-irq.c .mask = S5M8763_IRQ_LOBAT2_MASK, mask 118 drivers/mfd/sm501.c unsigned long mask) mask 123 drivers/mfd/sm501.c return pll2 / div_tab[(val >> lshft) & mask]; mask 1242 drivers/mfd/sm501.c tmp &= ~r->mask; mask 1257 drivers/mfd/sm501.c init->misc_control.mask); mask 1526 drivers/mfd/sm501.c .mask = 0x0, mask 1530 drivers/mfd/sm501.c .mask = 0x1F1F00, mask 1534 drivers/mfd/sm501.c .mask = 0, mask 203 drivers/mfd/sprd-sc27xx-spi.c ddata->irqs[i].mask = BIT(i % pdata->num_irqs); mask 92 drivers/mfd/sta2x11-mfd.c u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val, mask 112 drivers/mfd/sta2x11-mfd.c r &= ~mask; mask 114 drivers/mfd/sta2x11-mfd.c if (mask) mask 99 drivers/mfd/stmfx.c u8 mask = 0; mask 102 drivers/mfd/stmfx.c mask |= STMFX_REG_SYS_CTRL_GPIO_EN; mask 105 drivers/mfd/stmfx.c mask |= STMFX_REG_SYS_CTRL_ALTGPIO_EN; mask 108 drivers/mfd/stmfx.c mask |= STMFX_REG_SYS_CTRL_TS_EN; mask 111 drivers/mfd/stmfx.c mask |= STMFX_REG_SYS_CTRL_IDD_EN; mask 113 drivers/mfd/stmfx.c return mask; mask 119 drivers/mfd/stmfx.c u8 mask; mask 152 drivers/mfd/stmfx.c mask = stmfx_func_to_mask(func); mask 154 drivers/mfd/stmfx.c return regmap_update_bits(stmfx->map, STMFX_REG_SYS_CTRL, mask, mask); mask 160 drivers/mfd/stmfx.c u8 mask = stmfx_func_to_mask(func); mask 162 drivers/mfd/stmfx.c return regmap_update_bits(stmfx->map, STMFX_REG_SYS_CTRL, mask, 0); mask 83 drivers/mfd/stmpe.c static int __stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) mask 91 drivers/mfd/stmpe.c ret &= ~mask; mask 203 drivers/mfd/stmpe.c int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val) mask 208 drivers/mfd/stmpe.c ret = __stmpe_set_bits(stmpe, reg, mask, val); mask 272 drivers/mfd/stmpe.c int mask = (1 << af_bits) - 1; mask 297 drivers/mfd/stmpe.c regs[regoffset] &= ~(mask << pos); mask 532 drivers/mfd/stmpe.c unsigned int mask = 0; mask 535 drivers/mfd/stmpe.c mask |= STMPE811_SYS_CTRL2_GPIO_OFF; mask 538 drivers/mfd/stmpe.c mask |= STMPE811_SYS_CTRL2_ADC_OFF; mask 541 drivers/mfd/stmpe.c mask |= STMPE811_SYS_CTRL2_TSC_OFF; mask 543 drivers/mfd/stmpe.c return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, mask 544 drivers/mfd/stmpe.c enable ? 0 : mask); mask 781 drivers/mfd/stmpe.c unsigned int mask = 0; mask 784 drivers/mfd/stmpe.c mask |= STMPE1601_SYS_CTRL_ENABLE_GPIO; mask 786 drivers/mfd/stmpe.c mask &= ~STMPE1601_SYS_CTRL_ENABLE_GPIO; mask 789 drivers/mfd/stmpe.c mask |= STMPE1601_SYS_CTRL_ENABLE_KPC; mask 791 drivers/mfd/stmpe.c mask &= ~STMPE1601_SYS_CTRL_ENABLE_KPC; mask 794 drivers/mfd/stmpe.c mask |= STMPE1601_SYS_CTRL_ENABLE_SPWM; mask 796 drivers/mfd/stmpe.c mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; mask 798 drivers/mfd/stmpe.c return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, mask 799 drivers/mfd/stmpe.c enable ? mask : 0); mask 882 drivers/mfd/stmpe.c unsigned int mask = 0; mask 884 drivers/mfd/stmpe.c mask |= STMPE1801_MSK_INT_EN_GPIO; mask 887 drivers/mfd/stmpe.c mask |= STMPE1801_MSK_INT_EN_KPC; mask 889 drivers/mfd/stmpe.c return __stmpe_set_bits(stmpe, STMPE1801_REG_INT_EN_MASK_LOW, mask, mask 890 drivers/mfd/stmpe.c enable ? mask : 0); mask 1004 drivers/mfd/stmpe.c unsigned int mask = 0; mask 1007 drivers/mfd/stmpe.c mask |= STMPE24XX_SYS_CTRL_ENABLE_GPIO; mask 1010 drivers/mfd/stmpe.c mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; mask 1012 drivers/mfd/stmpe.c return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, mask 1013 drivers/mfd/stmpe.c enable ? mask : 0); mask 1167 drivers/mfd/stmpe.c int mask = 1 << (offset % 8); mask 1169 drivers/mfd/stmpe.c stmpe->ier[regoffset] &= ~mask; mask 1177 drivers/mfd/stmpe.c int mask = 1 << (offset % 8); mask 1179 drivers/mfd/stmpe.c stmpe->ier[regoffset] |= mask; mask 123 drivers/mfd/tc3589x.c int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val) mask 133 drivers/mfd/tc3589x.c ret &= ~mask; mask 309 drivers/mfd/tps65010.c u8 tmp = 0, mask, poll; mask 319 drivers/mfd/tps65010.c mask = tmp ^ tps->regstatus; mask 321 drivers/mfd/tps65010.c mask &= tps->nmask2; mask 323 drivers/mfd/tps65010.c mask = 0; mask 324 drivers/mfd/tps65010.c if (mask) { mask 346 drivers/mfd/tps65010.c mask = tmp ^ tps->chgstatus; mask 348 drivers/mfd/tps65010.c mask &= tps->nmask1; mask 350 drivers/mfd/tps65010.c mask = 0; mask 351 drivers/mfd/tps65010.c if (mask) { mask 368 drivers/mfd/tps65010.c if (mask & TPS_CHG_USB) mask 69 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_VAC_STATUS_CHANGE, mask 72 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_VSYS_STATUS_CHANGE, mask 75 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_BAT_STATUS_CHANGE, mask 78 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE, mask 81 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_CHARGING_COMPLETE, mask 84 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC1, mask 87 drivers/mfd/tps65090.c .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC2, mask 92 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_DCDC3, mask 96 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET1, mask 100 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET2, mask 104 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET3, mask 108 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET4, mask 112 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET5, mask 116 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET6, mask 120 drivers/mfd/tps65090.c .mask = TPS65090_INT2_MASK_OVERLOAD_FET7, mask 68 drivers/mfd/tps65217.c u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT; mask 70 drivers/mfd/tps65217.c tps->irq_mask &= ~mask; mask 76 drivers/mfd/tps65217.c u8 mask = BIT(data->hwirq) << TPS65217_INT_SHIFT; mask 78 drivers/mfd/tps65217.c tps->irq_mask |= mask; mask 260 drivers/mfd/tps65217.c unsigned int mask, unsigned int val, unsigned int level) mask 271 drivers/mfd/tps65217.c data &= ~mask; mask 272 drivers/mfd/tps65217.c data |= val & mask; mask 282 drivers/mfd/tps65217.c unsigned int mask, unsigned int val, unsigned int level) mask 284 drivers/mfd/tps65217.c return tps65217_update_bits(tps, reg, mask, val, level); mask 289 drivers/mfd/tps65217.c unsigned int mask, unsigned int level) mask 291 drivers/mfd/tps65217.c return tps65217_update_bits(tps, reg, mask, 0, level); mask 89 drivers/mfd/tps65218.c unsigned int mask, unsigned int val, unsigned int level) mask 100 drivers/mfd/tps65218.c data &= ~mask; mask 101 drivers/mfd/tps65218.c data |= val & mask; mask 113 drivers/mfd/tps65218.c unsigned int mask, unsigned int val, unsigned int level) mask 115 drivers/mfd/tps65218.c return tps65218_update_bits(tps, reg, mask, val, level); mask 120 drivers/mfd/tps65218.c unsigned int mask, unsigned int level) mask 122 drivers/mfd/tps65218.c return tps65218_update_bits(tps, reg, mask, 0, level); mask 146 drivers/mfd/tps65218.c .mask = TPS65218_INT1_PRGC, mask 149 drivers/mfd/tps65218.c .mask = TPS65218_INT1_CC_AQC, mask 152 drivers/mfd/tps65218.c .mask = TPS65218_INT1_HOT, mask 155 drivers/mfd/tps65218.c .mask = TPS65218_INT1_PB, mask 158 drivers/mfd/tps65218.c .mask = TPS65218_INT1_AC, mask 161 drivers/mfd/tps65218.c .mask = TPS65218_INT1_VPRG, mask 169 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS1_I, mask 173 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS2_I, mask 177 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS3_I, mask 181 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS1_F, mask 185 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS2_F, mask 189 drivers/mfd/tps65218.c .mask = TPS65218_INT2_LS3_F, mask 193 drivers/mfd/tps6586x.c int tps6586x_update(struct device *dev, int reg, uint8_t val, uint8_t mask) mask 197 drivers/mfd/tps6586x.c return regmap_update_bits(tps6586x->regmap, reg, mask, val); mask 53 drivers/mfd/tps65910.c .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK, mask 57 drivers/mfd/tps65910.c .mask = INT_MSK_VMBHI_IT_MSK_MASK, mask 61 drivers/mfd/tps65910.c .mask = INT_MSK_PWRON_IT_MSK_MASK, mask 65 drivers/mfd/tps65910.c .mask = INT_MSK_PWRON_LP_IT_MSK_MASK, mask 69 drivers/mfd/tps65910.c .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK, mask 73 drivers/mfd/tps65910.c .mask = INT_MSK_HOTDIE_IT_MSK_MASK, mask 77 drivers/mfd/tps65910.c .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK, mask 81 drivers/mfd/tps65910.c .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK, mask 87 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK, mask 91 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK, mask 95 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK, mask 99 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK, mask 103 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK, mask 107 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK, mask 111 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK, mask 115 drivers/mfd/tps65910.c .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK, mask 121 drivers/mfd/tps65910.c .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK, mask 125 drivers/mfd/tps65910.c .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK, mask 129 drivers/mfd/tps65910.c .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK, mask 133 drivers/mfd/tps65910.c .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK, mask 137 drivers/mfd/tps65910.c .mask = INT_MSK3_WTCHDG_IT_MSK_MASK, mask 141 drivers/mfd/tps65910.c .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK, mask 145 drivers/mfd/tps65910.c .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK, mask 149 drivers/mfd/tps65910.c .mask = INT_MSK3_PWRDN_IT_MSK_MASK, mask 157 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK, mask 161 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK, mask 165 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK, mask 169 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK, mask 173 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK, mask 177 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK, mask 181 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK, mask 185 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK, mask 191 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK, mask 195 drivers/mfd/tps65910.c .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK, mask 86 drivers/mfd/tps80031.c .mask = BIT(_mask), \ mask 30 drivers/mfd/twl4030-audio.c u8 mask; mask 53 drivers/mfd/twl4030-audio.c val |= audio->resource[id].mask; mask 55 drivers/mfd/twl4030-audio.c val &= ~audio->resource[id].mask; mask 219 drivers/mfd/twl4030-audio.c audio->resource[TWL4030_AUDIO_RES_POWER].mask = TWL4030_CODECPDZ; mask 223 drivers/mfd/twl4030-audio.c audio->resource[TWL4030_AUDIO_RES_APLL].mask = TWL4030_APLL_EN; mask 73 drivers/mfd/twl4030-irq.c } mask[2]; mask 88 drivers/mfd/twl4030-irq.c .mask = { { \ mask 120 drivers/mfd/twl4030-irq.c .mask = { { mask 144 drivers/mfd/twl4030-irq.c .mask = { { mask 180 drivers/mfd/twl4030-irq.c .mask = { { mask 203 drivers/mfd/twl4030-irq.c .mask = { { mask 235 drivers/mfd/twl4030-irq.c .mask = { { mask 252 drivers/mfd/twl4030-irq.c .mask = { { mask 340 drivers/mfd/twl4030-irq.c sih->mask[line].imr_offset, sih->bytes_ixr); mask 384 drivers/mfd/twl4030-irq.c sih->mask[line].isr_offset, sih->bytes_ixr); mask 391 drivers/mfd/twl4030-irq.c sih->mask[line].isr_offset, mask 490 drivers/mfd/twl4030-irq.c sih->mask[irq_line].imr_offset, mask 571 drivers/mfd/twl4030-irq.c sih->mask[irq_line].isr_offset, sih->bytes_ixr); mask 370 drivers/mfd/twl6030-irq.c u8 mask[3]; mask 385 drivers/mfd/twl6030-irq.c mask[0] = 0xFF; mask 386 drivers/mfd/twl6030-irq.c mask[1] = 0xFF; mask 387 drivers/mfd/twl6030-irq.c mask[2] = 0xFF; mask 390 drivers/mfd/twl6030-irq.c status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3); mask 392 drivers/mfd/twl6030-irq.c status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3); mask 394 drivers/mfd/twl6030-irq.c status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3); mask 122 drivers/mfd/twl6040.c int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) mask 124 drivers/mfd/twl6040.c return regmap_update_bits(twl6040->regmap, reg, mask, mask); mask 128 drivers/mfd/twl6040.c int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) mask 130 drivers/mfd/twl6040.c return regmap_update_bits(twl6040->regmap, reg, mask, 0); mask 618 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_THINT, }, mask 619 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, }, mask 620 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_HOOKINT, }, mask 621 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_HFINT, }, mask 622 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_VIBINT, }, mask 623 drivers/mfd/twl6040.c { .reg_offset = 0, .mask = TWL6040_READYINT, }, mask 156 drivers/mfd/ucb1x00-core.c unsigned old, mask = 1 << offset; mask 161 drivers/mfd/ucb1x00-core.c ucb->io_out |= mask; mask 163 drivers/mfd/ucb1x00-core.c ucb->io_out &= ~mask; mask 169 drivers/mfd/ucb1x00-core.c if (!(ucb->io_dir & mask)) { mask 170 drivers/mfd/ucb1x00-core.c ucb->io_dir |= mask; mask 298 drivers/mfd/ucb1x00-core.c static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) mask 301 drivers/mfd/ucb1x00-core.c if (ucb->irq_ris_enbl & mask) mask 304 drivers/mfd/ucb1x00-core.c if (ucb->irq_fal_enbl & mask) mask 317 drivers/mfd/ucb1x00-core.c unsigned mask = 1 << (data->irq - ucb->irq_base); mask 320 drivers/mfd/ucb1x00-core.c ucb->irq_mask &= ~mask; mask 321 drivers/mfd/ucb1x00-core.c ucb1x00_irq_update(ucb, mask); mask 328 drivers/mfd/ucb1x00-core.c unsigned mask = 1 << (data->irq - ucb->irq_base); mask 331 drivers/mfd/ucb1x00-core.c ucb->irq_mask |= mask; mask 332 drivers/mfd/ucb1x00-core.c ucb1x00_irq_update(ucb, mask); mask 339 drivers/mfd/ucb1x00-core.c unsigned mask = 1 << (data->irq - ucb->irq_base); mask 343 drivers/mfd/ucb1x00-core.c ucb->irq_ris_enbl |= mask; mask 345 drivers/mfd/ucb1x00-core.c ucb->irq_ris_enbl &= ~mask; mask 348 drivers/mfd/ucb1x00-core.c ucb->irq_fal_enbl |= mask; mask 350 drivers/mfd/ucb1x00-core.c ucb->irq_fal_enbl &= ~mask; mask 351 drivers/mfd/ucb1x00-core.c if (ucb->irq_mask & mask) { mask 366 drivers/mfd/ucb1x00-core.c unsigned mask = 1 << (data->irq - ucb->irq_base); mask 373 drivers/mfd/ucb1x00-core.c ucb->irq_wake |= mask; mask 375 drivers/mfd/ucb1x00-core.c ucb->irq_wake &= ~mask; mask 443 drivers/mfd/ucb1x00-core.c unsigned long mask; mask 445 drivers/mfd/ucb1x00-core.c mask = probe_irq_on(); mask 478 drivers/mfd/ucb1x00-core.c return probe_irq_off(mask); mask 100 drivers/mfd/wm5102-tables.c .mask = ARIZONA_MICD_CLAMP_FALL_EINT1 mask 103 drivers/mfd/wm5102-tables.c .mask = ARIZONA_MICD_CLAMP_RISE_EINT1 mask 105 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, mask 106 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, mask 107 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, mask 108 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, mask 124 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, mask 125 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, mask 126 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 127 drivers/mfd/wm5102-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 130 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 mask 133 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 mask 136 drivers/mfd/wm5102-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 mask 140 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 143 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 146 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 mask 149 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 mask 152 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 155 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 mask 158 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 161 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 mask 164 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 mask 167 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 170 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 173 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 176 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 179 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 182 drivers/mfd/wm5102-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 186 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 mask 189 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 mask 192 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 mask 195 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 mask 198 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 mask 201 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 mask 204 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 mask 207 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 mask 210 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 mask 213 drivers/mfd/wm5102-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 mask 217 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 220 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 mask 223 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 mask 226 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 229 drivers/mfd/wm5102-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 285 drivers/mfd/wm5110-tables.c .mask = ARIZONA_MICD_CLAMP_FALL_EINT1 mask 288 drivers/mfd/wm5110-tables.c .mask = ARIZONA_MICD_CLAMP_RISE_EINT1 mask 290 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, mask 291 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, mask 292 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, mask 293 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, mask 310 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, mask 311 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, mask 312 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 313 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 316 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1 mask 319 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 mask 322 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 mask 325 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 mask 328 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 mask 331 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 mask 334 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 mask 337 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 mask 340 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 mask 343 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 mask 346 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 mask 349 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 mask 353 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 356 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 359 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 mask 362 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 mask 365 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 368 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 mask 371 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 374 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 mask 377 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 mask 380 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 383 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 386 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 389 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 392 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 395 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 399 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 mask 402 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 mask 405 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 mask 408 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 mask 411 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 mask 414 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 mask 417 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 mask 420 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 mask 423 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 mask 426 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 mask 429 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 mask 432 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 mask 435 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 mask 438 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 mask 441 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 mask 444 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 mask 448 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 451 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 454 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 470 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, mask 471 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, mask 472 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 473 drivers/mfd/wm5110-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 476 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP4_RAM_RDY_EINT1 mask 479 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP3_RAM_RDY_EINT1 mask 482 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP2_RAM_RDY_EINT1 mask 485 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1 mask 488 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1 mask 491 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1 mask 494 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1 mask 497 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1 mask 500 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1 mask 503 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ3_EINT1 mask 506 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1 mask 509 drivers/mfd/wm5110-tables.c .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1 mask 513 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 516 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 519 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 mask 522 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 mask 525 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 528 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1 mask 531 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 534 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 mask 537 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 mask 540 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 543 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 546 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 549 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 552 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 555 drivers/mfd/wm5110-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 559 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_CTRLIF_ERR_EINT1 mask 562 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 mask 565 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 mask 568 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 mask 571 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC1_CFG_ERR_EINT1 mask 574 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC2_CFG_ERR_EINT1 mask 577 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_V2_ISRC3_CFG_ERR_EINT1 mask 580 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3R_DONE_EINT1 mask 583 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP3L_DONE_EINT1 mask 586 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2R_DONE_EINT1 mask 589 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP2L_DONE_EINT1 mask 592 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1R_DONE_EINT1 mask 595 drivers/mfd/wm5110-tables.c .reg_offset = 3, .mask = ARIZONA_HP1L_DONE_EINT1 mask 599 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 602 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_V2_ASRC_CFG_ERR_EINT1 mask 605 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 608 drivers/mfd/wm5110-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 612 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_DSP_SHARED_WR_COLL_EINT1 mask 615 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK_SHUTDOWN_EINT1 mask 618 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1R_SHORT_EINT1 mask 621 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_SPK1L_SHORT_EINT1 mask 624 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3R_SC_NEG_EINT1 mask 627 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3R_SC_POS_EINT1 mask 630 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3L_SC_NEG_EINT1 mask 633 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP3L_SC_POS_EINT1 mask 636 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2R_SC_NEG_EINT1 mask 639 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2R_SC_POS_EINT1 mask 642 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2L_SC_NEG_EINT1 mask 645 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP2L_SC_POS_EINT1 mask 648 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_NEG_EINT1 mask 651 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1R_SC_POS_EINT1 mask 654 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_NEG_EINT1 mask 657 drivers/mfd/wm5110-tables.c .reg_offset = 5, .mask = ARIZONA_HP1L_SC_POS_EINT1 mask 598 drivers/mfd/wm831x-core.c unsigned short mask, unsigned short val) mask 605 drivers/mfd/wm831x-core.c ret = regmap_update_bits(wm831x->regmap, reg, mask, val); mask 1893 drivers/mfd/wm831x-core.c int reg, mask; mask 1903 drivers/mfd/wm831x-core.c mask = WM831X_CHG_BATT_HOT_EINT | mask 1911 drivers/mfd/wm831x-core.c if (reg & mask) mask 1915 drivers/mfd/wm831x-core.c if (reg & mask) { mask 1918 drivers/mfd/wm831x-core.c reg & mask); mask 1920 drivers/mfd/wm831x-core.c reg & mask); mask 28 drivers/mfd/wm831x-irq.c int mask; mask 35 drivers/mfd/wm831x-irq.c .mask = WM831X_TEMP_THW_EINT, mask 40 drivers/mfd/wm831x-irq.c .mask = WM831X_GP1_EINT, mask 45 drivers/mfd/wm831x-irq.c .mask = WM831X_GP2_EINT, mask 50 drivers/mfd/wm831x-irq.c .mask = WM831X_GP3_EINT, mask 55 drivers/mfd/wm831x-irq.c .mask = WM831X_GP4_EINT, mask 60 drivers/mfd/wm831x-irq.c .mask = WM831X_GP5_EINT, mask 65 drivers/mfd/wm831x-irq.c .mask = WM831X_GP6_EINT, mask 70 drivers/mfd/wm831x-irq.c .mask = WM831X_GP7_EINT, mask 75 drivers/mfd/wm831x-irq.c .mask = WM831X_GP8_EINT, mask 80 drivers/mfd/wm831x-irq.c .mask = WM831X_GP9_EINT, mask 85 drivers/mfd/wm831x-irq.c .mask = WM831X_GP10_EINT, mask 90 drivers/mfd/wm831x-irq.c .mask = WM831X_GP11_EINT, mask 95 drivers/mfd/wm831x-irq.c .mask = WM831X_GP12_EINT, mask 100 drivers/mfd/wm831x-irq.c .mask = WM831X_GP13_EINT, mask 105 drivers/mfd/wm831x-irq.c .mask = WM831X_GP14_EINT, mask 110 drivers/mfd/wm831x-irq.c .mask = WM831X_GP15_EINT, mask 115 drivers/mfd/wm831x-irq.c .mask = WM831X_GP16_EINT, mask 120 drivers/mfd/wm831x-irq.c .mask = WM831X_ON_PIN_EINT, mask 125 drivers/mfd/wm831x-irq.c .mask = WM831X_PPM_SYSLO_EINT, mask 130 drivers/mfd/wm831x-irq.c .mask = WM831X_PPM_PWR_SRC_EINT, mask 135 drivers/mfd/wm831x-irq.c .mask = WM831X_PPM_USB_CURR_EINT, mask 140 drivers/mfd/wm831x-irq.c .mask = WM831X_WDOG_TO_EINT, mask 145 drivers/mfd/wm831x-irq.c .mask = WM831X_RTC_PER_EINT, mask 150 drivers/mfd/wm831x-irq.c .mask = WM831X_RTC_ALM_EINT, mask 155 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_BATT_HOT_EINT, mask 160 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_BATT_COLD_EINT, mask 165 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_BATT_FAIL_EINT, mask 170 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_OV_EINT, mask 175 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_END_EINT, mask 180 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_TO_EINT, mask 185 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_MODE_EINT, mask 190 drivers/mfd/wm831x-irq.c .mask = WM831X_CHG_START_EINT, mask 195 drivers/mfd/wm831x-irq.c .mask = WM831X_TCHDATA_EINT, mask 200 drivers/mfd/wm831x-irq.c .mask = WM831X_TCHPD_EINT, mask 205 drivers/mfd/wm831x-irq.c .mask = WM831X_AUXADC_DATA_EINT, mask 210 drivers/mfd/wm831x-irq.c .mask = WM831X_AUXADC_DCOMP1_EINT, mask 215 drivers/mfd/wm831x-irq.c .mask = WM831X_AUXADC_DCOMP2_EINT, mask 220 drivers/mfd/wm831x-irq.c .mask = WM831X_AUXADC_DCOMP3_EINT, mask 225 drivers/mfd/wm831x-irq.c .mask = WM831X_AUXADC_DCOMP4_EINT, mask 230 drivers/mfd/wm831x-irq.c .mask = WM831X_CS1_EINT, mask 235 drivers/mfd/wm831x-irq.c .mask = WM831X_CS2_EINT, mask 240 drivers/mfd/wm831x-irq.c .mask = WM831X_HC_DC1_EINT, mask 245 drivers/mfd/wm831x-irq.c .mask = WM831X_HC_DC2_EINT, mask 250 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO1_EINT, mask 255 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO2_EINT, mask 260 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO3_EINT, mask 265 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO4_EINT, mask 270 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO5_EINT, mask 275 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO6_EINT, mask 280 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO7_EINT, mask 285 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO8_EINT, mask 290 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO9_EINT, mask 295 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_LDO10_EINT, mask 300 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_DC1_EINT, mask 305 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_DC2_EINT, mask 310 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_DC3_EINT, mask 315 drivers/mfd/wm831x-irq.c .mask = WM831X_UV_DC4_EINT, mask 375 drivers/mfd/wm831x-irq.c wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; mask 384 drivers/mfd/wm831x-irq.c wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; mask 510 drivers/mfd/wm831x-irq.c if (*status & wm831x_irqs[i].mask) mask 63 drivers/mfd/wm8350-core.c int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask) mask 65 drivers/mfd/wm8350-core.c return regmap_update_bits(wm8350->regmap, reg, mask, 0); mask 69 drivers/mfd/wm8350-core.c int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask) mask 71 drivers/mfd/wm8350-core.c return regmap_update_bits(wm8350->regmap, reg, mask, mask); mask 37 drivers/mfd/wm8350-irq.c int mask; mask 45 drivers/mfd/wm8350-irq.c .mask = WM8350_OC_LS_EINT, mask 51 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC1_EINT, mask 56 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC2_EINT, mask 61 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC3_EINT, mask 66 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC4_EINT, mask 71 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC5_EINT, mask 76 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_DC6_EINT, mask 81 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_LDO1_EINT, mask 86 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_LDO2_EINT, mask 91 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_LDO3_EINT, mask 96 drivers/mfd/wm8350-irq.c .mask = WM8350_UV_LDO4_EINT, mask 101 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_BAT_HOT_EINT, mask 106 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_BAT_COLD_EINT, mask 111 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_BAT_FAIL_EINT, mask 116 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_TO_EINT, mask 121 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_END_EINT, mask 126 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_START_EINT, mask 131 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_FAST_RDY_EINT, mask 136 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_VBATT_LT_3P9_EINT, mask 141 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_VBATT_LT_3P1_EINT, mask 146 drivers/mfd/wm8350-irq.c .mask = WM8350_CHG_VBATT_LT_2P85_EINT, mask 151 drivers/mfd/wm8350-irq.c .mask = WM8350_RTC_ALM_EINT, mask 156 drivers/mfd/wm8350-irq.c .mask = WM8350_RTC_SEC_EINT, mask 161 drivers/mfd/wm8350-irq.c .mask = WM8350_RTC_PER_EINT, mask 166 drivers/mfd/wm8350-irq.c .mask = WM8350_CS1_EINT, mask 171 drivers/mfd/wm8350-irq.c .mask = WM8350_CS2_EINT, mask 176 drivers/mfd/wm8350-irq.c .mask = WM8350_SYS_HYST_COMP_FAIL_EINT, mask 181 drivers/mfd/wm8350-irq.c .mask = WM8350_SYS_CHIP_GT115_EINT, mask 186 drivers/mfd/wm8350-irq.c .mask = WM8350_SYS_CHIP_GT140_EINT, mask 191 drivers/mfd/wm8350-irq.c .mask = WM8350_SYS_WDOG_TO_EINT, mask 196 drivers/mfd/wm8350-irq.c .mask = WM8350_AUXADC_DATARDY_EINT, mask 201 drivers/mfd/wm8350-irq.c .mask = WM8350_AUXADC_DCOMP4_EINT, mask 206 drivers/mfd/wm8350-irq.c .mask = WM8350_AUXADC_DCOMP3_EINT, mask 211 drivers/mfd/wm8350-irq.c .mask = WM8350_AUXADC_DCOMP2_EINT, mask 216 drivers/mfd/wm8350-irq.c .mask = WM8350_AUXADC_DCOMP1_EINT, mask 221 drivers/mfd/wm8350-irq.c .mask = WM8350_USB_LIMIT_EINT, mask 227 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_OFF_STATE_EINT, mask 232 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_HIB_STATE_EINT, mask 237 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_CONV_FAULT_EINT, mask 242 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_WDOG_RST_EINT, mask 247 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_GP_PWR_ON_EINT, mask 252 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_ONKEY_EINT, mask 257 drivers/mfd/wm8350-irq.c .mask = WM8350_WKUP_GP_WAKEUP_EINT, mask 262 drivers/mfd/wm8350-irq.c .mask = WM8350_CODEC_JCK_DET_L_EINT, mask 267 drivers/mfd/wm8350-irq.c .mask = WM8350_CODEC_JCK_DET_R_EINT, mask 272 drivers/mfd/wm8350-irq.c .mask = WM8350_CODEC_MICSCD_EINT, mask 277 drivers/mfd/wm8350-irq.c .mask = WM8350_CODEC_MICD_EINT, mask 282 drivers/mfd/wm8350-irq.c .mask = WM8350_EXT_USB_FB_EINT, mask 287 drivers/mfd/wm8350-irq.c .mask = WM8350_EXT_WALL_FB_EINT, mask 292 drivers/mfd/wm8350-irq.c .mask = WM8350_EXT_BAT_FB_EINT, mask 297 drivers/mfd/wm8350-irq.c .mask = WM8350_GP0_EINT, mask 302 drivers/mfd/wm8350-irq.c .mask = WM8350_GP1_EINT, mask 307 drivers/mfd/wm8350-irq.c .mask = WM8350_GP2_EINT, mask 312 drivers/mfd/wm8350-irq.c .mask = WM8350_GP3_EINT, mask 317 drivers/mfd/wm8350-irq.c .mask = WM8350_GP4_EINT, mask 322 drivers/mfd/wm8350-irq.c .mask = WM8350_GP5_EINT, mask 327 drivers/mfd/wm8350-irq.c .mask = WM8350_GP6_EINT, mask 332 drivers/mfd/wm8350-irq.c .mask = WM8350_GP7_EINT, mask 337 drivers/mfd/wm8350-irq.c .mask = WM8350_GP8_EINT, mask 342 drivers/mfd/wm8350-irq.c .mask = WM8350_GP9_EINT, mask 347 drivers/mfd/wm8350-irq.c .mask = WM8350_GP10_EINT, mask 352 drivers/mfd/wm8350-irq.c .mask = WM8350_GP11_EINT, mask 357 drivers/mfd/wm8350-irq.c .mask = WM8350_GP12_EINT, mask 407 drivers/mfd/wm8350-irq.c if (sub_reg[data->reg] & data->mask) mask 443 drivers/mfd/wm8350-irq.c wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; mask 452 drivers/mfd/wm8350-irq.c wm8350->irq_masks[irq_data->reg] |= irq_data->mask; mask 29 drivers/mfd/wm8994-irq.c .mask = WM8994_TEMP_SHUT_EINT, mask 33 drivers/mfd/wm8994-irq.c .mask = WM8994_MIC1_DET_EINT, mask 37 drivers/mfd/wm8994-irq.c .mask = WM8994_MIC1_SHRT_EINT, mask 41 drivers/mfd/wm8994-irq.c .mask = WM8994_MIC2_DET_EINT, mask 45 drivers/mfd/wm8994-irq.c .mask = WM8994_MIC2_SHRT_EINT, mask 49 drivers/mfd/wm8994-irq.c .mask = WM8994_FLL1_LOCK_EINT, mask 53 drivers/mfd/wm8994-irq.c .mask = WM8994_FLL2_LOCK_EINT, mask 57 drivers/mfd/wm8994-irq.c .mask = WM8994_SRC1_LOCK_EINT, mask 61 drivers/mfd/wm8994-irq.c .mask = WM8994_SRC2_LOCK_EINT, mask 65 drivers/mfd/wm8994-irq.c .mask = WM8994_AIF1DRC1_SIG_DET, mask 69 drivers/mfd/wm8994-irq.c .mask = WM8994_AIF1DRC2_SIG_DET_EINT, mask 73 drivers/mfd/wm8994-irq.c .mask = WM8994_AIF2DRC_SIG_DET_EINT, mask 77 drivers/mfd/wm8994-irq.c .mask = WM8994_FIFOS_ERR_EINT, mask 81 drivers/mfd/wm8994-irq.c .mask = WM8994_WSEQ_DONE_EINT, mask 85 drivers/mfd/wm8994-irq.c .mask = WM8994_DCS_DONE_EINT, mask 89 drivers/mfd/wm8994-irq.c .mask = WM8994_TEMP_WARN_EINT, mask 92 drivers/mfd/wm8994-irq.c .mask = WM8994_GP1_EINT, mask 95 drivers/mfd/wm8994-irq.c .mask = WM8994_GP2_EINT, mask 98 drivers/mfd/wm8994-irq.c .mask = WM8994_GP3_EINT, mask 101 drivers/mfd/wm8994-irq.c .mask = WM8994_GP4_EINT, mask 104 drivers/mfd/wm8994-irq.c .mask = WM8994_GP5_EINT, mask 107 drivers/mfd/wm8994-irq.c .mask = WM8994_GP6_EINT, mask 110 drivers/mfd/wm8994-irq.c .mask = WM8994_GP7_EINT, mask 113 drivers/mfd/wm8994-irq.c .mask = WM8994_GP8_EINT, mask 116 drivers/mfd/wm8994-irq.c .mask = WM8994_GP8_EINT, mask 119 drivers/mfd/wm8994-irq.c .mask = WM8994_GP10_EINT, mask 122 drivers/mfd/wm8994-irq.c .mask = WM8994_GP11_EINT, mask 42 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, mask 43 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, mask 44 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, mask 45 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, mask 60 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, mask 61 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, mask 62 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 63 drivers/mfd/wm8997-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 66 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 69 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 72 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 mask 75 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 mask 78 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 81 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 84 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 87 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 90 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 93 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 96 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 99 drivers/mfd/wm8997-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 103 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 mask 106 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 mask 109 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 mask 112 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 mask 115 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 mask 118 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 mask 121 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 mask 124 drivers/mfd/wm8997-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 mask 128 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 131 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1 mask 134 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1 mask 137 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 140 drivers/mfd/wm8997-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 52 drivers/mfd/wm8998-tables.c .mask = ARIZONA_MICD_CLAMP_FALL_EINT1 mask 55 drivers/mfd/wm8998-tables.c .mask = ARIZONA_MICD_CLAMP_RISE_EINT1 mask 57 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 }, mask 58 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 }, mask 59 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 }, mask 60 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 }, mask 76 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 }, mask 77 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 }, mask 78 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 }, mask 79 drivers/mfd/wm8998-tables.c [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 }, mask 82 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_WARN_EINT1 mask 85 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_SPK_OVERHEAT_EINT1 mask 88 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1 mask 91 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1 mask 94 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1 mask 97 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1 mask 100 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1 mask 103 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1 mask 106 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1 mask 109 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1 mask 112 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1 mask 115 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1 mask 118 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1 mask 121 drivers/mfd/wm8998-tables.c .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1 mask 125 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1 mask 128 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1 mask 131 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1 mask 134 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1 mask 137 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1 mask 140 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 mask 143 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 mask 146 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1 mask 149 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1 mask 152 drivers/mfd/wm8998-tables.c .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1 mask 156 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1 mask 159 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1 mask 162 drivers/mfd/wm8998-tables.c .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1 mask 332 drivers/mfd/wm97xx-core.c { .id = WM9705_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK }, mask 333 drivers/mfd/wm97xx-core.c { .id = WM9712_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK }, mask 334 drivers/mfd/wm97xx-core.c { .id = WM9713_VENDOR_ID, .mask = WM97xx_VENDOR_ID_MASK }, mask 2012 drivers/misc/altera-stapl/altera.c u8 *mask = (u8 *)vars[args[2]]; mask 2059 drivers/misc/altera-stapl/altera.c if (mask[mask_index >> 3] & mask 185 drivers/misc/cardreader/rtl8411.c u8 mask, val; mask 188 drivers/misc/cardreader/rtl8411.c mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK; mask 205 drivers/misc/cardreader/rtl8411.c return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); mask 365 drivers/misc/cardreader/rts5249.c u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; mask 369 drivers/misc/cardreader/rts5249.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); mask 302 drivers/misc/cardreader/rts5260.c u8 mask, val; mask 313 drivers/misc/cardreader/rts5260.c mask = SD_OCP_GLITCH_MASK; mask 315 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); mask 341 drivers/misc/cardreader/rts5260.c u8 mask = 0; mask 343 drivers/misc/cardreader/rts5260.c mask = SD_OCP_INT_EN | SD_DETECT_EN; mask 344 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); mask 361 drivers/misc/cardreader/rts5260.c u8 mask = 0; mask 364 drivers/misc/cardreader/rts5260.c mask = SD_OCP_INT_CLR | SD_OC_CLR; mask 367 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); mask 372 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); mask 588 drivers/misc/cardreader/rts5260.c u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; mask 592 drivers/misc/cardreader/rts5260.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); mask 108 drivers/misc/cardreader/rtsx_pcr.c u8 mask = FORCE_ASPM_VAL_MASK; mask 113 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); mask 181 drivers/misc/cardreader/rtsx_pcr.c int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) mask 187 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)mask << 8; mask 341 drivers/misc/cardreader/rtsx_pcr.c u8 cmd_type, u16 reg_addr, u8 mask, u8 data) mask 349 drivers/misc/cardreader/rtsx_pcr.c val |= (u32)mask << 8; mask 1163 drivers/misc/cardreader/rtsx_pcr.c u8 mask = SD_OCP_INT_EN | SD_DETECT_EN; mask 1168 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); mask 1213 drivers/misc/cardreader/rtsx_pcr.c u8 mask = SD_OCP_INT_CLR | SD_OC_CLR; mask 1216 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); mask 1218 drivers/misc/cardreader/rtsx_pcr.c rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); mask 170 drivers/misc/cardreader/rtsx_usb.c u8 mask, u8 data) mask 176 drivers/misc/cardreader/rtsx_usb.c index = mask | data << 8; mask 213 drivers/misc/cardreader/rtsx_usb.c u8 mask, u8 data) mask 223 drivers/misc/cardreader/rtsx_usb.c ucr->cmd_buf[i++] = mask; mask 340 drivers/misc/cardreader/rtsx_usb.c int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask, u8 data) mask 343 drivers/misc/cardreader/rtsx_usb.c rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, addr, mask, data); mask 18 drivers/misc/cb710/core.c int reg, uint32_t mask, uint32_t xor) mask 23 drivers/misc/cb710/core.c rval = (rval & mask) ^ xor; mask 24 drivers/misc/cb710/debug.c unsigned mask = (1 << bits/8) - 1; mask 26 drivers/misc/cb710/debug.c return ((allow[block] >> offset) & mask) == mask; mask 47 drivers/misc/cs5535-mfgpt.c uint32_t msr, mask, value, dummy; mask 67 drivers/misc/cs5535-mfgpt.c mask = 1 << (timer->nr + 24); mask 72 drivers/misc/cs5535-mfgpt.c mask = 1 << (timer->nr + shift); mask 77 drivers/misc/cs5535-mfgpt.c mask = 1 << (timer->nr + shift); mask 87 drivers/misc/cs5535-mfgpt.c value |= mask; mask 89 drivers/misc/cs5535-mfgpt.c value &= ~mask; mask 36 drivers/misc/cxl/fault.c unsigned int mask = (ctx->sst_size >> 7) - 1; /* SSTP0[SegTableSize] */ mask 41 drivers/misc/cxl/fault.c hash = (slb->esid >> SID_SHIFT_1T) & mask; mask 43 drivers/misc/cxl/fault.c hash = (slb->esid >> SID_SHIFT) & mask; mask 367 drivers/misc/cxl/file.c __poll_t mask = 0; mask 377 drivers/misc/cxl/file.c mask |= EPOLLIN | EPOLLRDNORM; mask 381 drivers/misc/cxl/file.c mask |= EPOLLERR; mask 384 drivers/misc/cxl/file.c pr_devel("afu_poll pe: %i returning %#x\n", ctx->pe, mask); mask 386 drivers/misc/cxl/file.c return mask; mask 22 drivers/misc/cxl/native.c u64 result, u64 mask, bool enabled) mask 37 drivers/misc/cxl/native.c while ((AFU_Cntl & mask) != result) { mask 1533 drivers/misc/cxl/native.c u32 val32, mask, shift; mask 1541 drivers/misc/cxl/native.c mask = 0xffff << shift; mask 1542 drivers/misc/cxl/native.c val32 = (val32 & ~mask) | (in << shift); mask 1551 drivers/misc/cxl/native.c u32 val32, mask, shift; mask 1558 drivers/misc/cxl/native.c mask = 0xff << shift; mask 1559 drivers/misc/cxl/native.c val32 = (val32 & ~mask) | (in << shift); mask 631 drivers/misc/genwqe/card_base.c u64 mask, fir, fec, uid, gfir, gfir_masked, sfir, sfec; mask 681 drivers/misc/genwqe/card_base.c for (j = 0, mask = 1ULL; j < 64; j++, mask <<= 1) { mask 684 drivers/misc/genwqe/card_base.c if ((fir & mask) == 0x0) mask 736 drivers/misc/genwqe/card_base.c __genwqe_writeq(cd, fir_clr_addr, mask); mask 740 drivers/misc/genwqe/card_base.c fir_clr_addr, mask); mask 5010 drivers/misc/habanalabs/goya/goya.c static bool goya_is_device_idle(struct hl_device *hdev, u32 *mask, mask 5034 drivers/misc/habanalabs/goya/goya.c if (mask) mask 5035 drivers/misc/habanalabs/goya/goya.c *mask |= !is_eng_idle << (GOYA_ENGINE_ID_DMA_0 + i); mask 5057 drivers/misc/habanalabs/goya/goya.c if (mask) mask 5058 drivers/misc/habanalabs/goya/goya.c *mask |= !is_eng_idle << (GOYA_ENGINE_ID_TPC_0 + i); mask 5077 drivers/misc/habanalabs/goya/goya.c if (mask) mask 5078 drivers/misc/habanalabs/goya/goya.c *mask |= !is_eng_idle << GOYA_ENGINE_ID_MME_0; mask 30 drivers/misc/habanalabs/goya/goya_security.c u32 pb_addr, mask; mask 69 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); mask 70 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); mask 71 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); mask 72 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 73 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 74 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); mask 75 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); mask 76 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); mask 77 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); mask 78 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_DBGMEM_RC & 0x7F) >> 2); mask 79 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_LOG_SHADOW & 0x7F) >> 2); mask 81 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 85 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_STORE_MAX_CREDIT & 0x7F) >> 2); mask 86 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_AGU & 0x7F) >> 2); mask 87 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBA & 0x7F) >> 2); mask 88 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBB & 0x7F) >> 2); mask 89 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBC & 0x7F) >> 2); mask 90 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_WBC & 0x7F) >> 2); mask 91 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBA_CONTROL_DATA & 0x7F) >> 2); mask 92 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBB_CONTROL_DATA & 0x7F) >> 2); mask 93 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBC_CONTROL_DATA & 0x7F) >> 2); mask 94 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_WBC_CONTROL_DATA & 0x7F) >> 2); mask 95 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_TE & 0x7F) >> 2); mask 96 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_TE2DEC & 0x7F) >> 2); mask 97 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_REI_STATUS & 0x7F) >> 2); mask 98 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_REI_MASK & 0x7F) >> 2); mask 99 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SEI_STATUS & 0x7F) >> 2); mask 100 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SEI_MASK & 0x7F) >> 2); mask 101 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SPI_STATUS & 0x7F) >> 2); mask 102 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SPI_MASK & 0x7F) >> 2); mask 104 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 108 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_QM_GLBL_CFG0 & 0x7F) >> 2); mask 109 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_CFG1 & 0x7F) >> 2); mask 110 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_PROT & 0x7F) >> 2); mask 111 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 112 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 113 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 114 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 115 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 116 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 117 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_STS0 & 0x7F) >> 2); mask 118 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_GLBL_STS1 & 0x7F) >> 2); mask 119 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_BASE_LO & 0x7F) >> 2); mask 120 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_BASE_HI & 0x7F) >> 2); mask 121 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_SIZE & 0x7F) >> 2); mask 122 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_PI & 0x7F) >> 2); mask 123 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_CI & 0x7F) >> 2); mask 124 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_CFG0 & 0x7F) >> 2); mask 125 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_CFG1 & 0x7F) >> 2); mask 126 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_ARUSER & 0x7F) >> 2); mask 128 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 132 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_QM_PQ_PUSH0 & 0x7F) >> 2); mask 133 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_PUSH1 & 0x7F) >> 2); mask 134 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_PUSH2 & 0x7F) >> 2); mask 135 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_PUSH3 & 0x7F) >> 2); mask 136 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_STS0 & 0x7F) >> 2); mask 137 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_STS1 & 0x7F) >> 2); mask 138 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 139 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 140 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 141 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 142 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_CFG0 & 0x7F) >> 2); mask 143 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_CFG1 & 0x7F) >> 2); mask 144 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_ARUSER & 0x7F) >> 2); mask 145 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_PTR_LO & 0x7F) >> 2); mask 146 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_PTR_HI & 0x7F) >> 2); mask 147 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_TSIZE & 0x7F) >> 2); mask 148 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_CTL & 0x7F) >> 2); mask 149 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 150 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 151 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 152 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_CTL_STS & 0x7F) >> 2); mask 153 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_STS0 & 0x7F) >> 2); mask 154 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_STS1 & 0x7F) >> 2); mask 155 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 156 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 157 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 158 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 160 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 164 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 165 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 166 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 167 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 168 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 169 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 170 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 171 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 172 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 173 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 174 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 175 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 176 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 177 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 178 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 180 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 184 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_QM_CP_STS & 0x7F) >> 2); mask 185 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 186 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 187 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_BARRIER_CFG & 0x7F) >> 2); mask 188 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CP_DBG_0 & 0x7F) >> 2); mask 189 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_BUF_ADDR & 0x7F) >> 2); mask 190 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_PQ_BUF_RDATA & 0x7F) >> 2); mask 191 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_BUF_ADDR & 0x7F) >> 2); mask 192 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_QM_CQ_BUF_RDATA & 0x7F) >> 2); mask 194 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 198 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 199 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 200 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 201 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 202 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 203 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 204 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 205 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 206 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 207 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 208 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 210 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 214 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 215 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 216 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 217 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 218 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 219 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 220 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 221 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 222 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 223 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 224 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 225 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 226 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 228 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 233 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 234 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 235 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 236 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 237 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 238 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 239 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 240 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 241 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 242 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 243 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 244 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 245 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 246 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 247 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 248 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_STS & 0x7F) >> 2); mask 249 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 251 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 256 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 257 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 258 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 259 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 260 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 262 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 266 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmMME_SBB_POWER_ECO1 & 0x7F) >> 2); mask 267 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmMME_SBB_POWER_ECO2 & 0x7F) >> 2); mask 269 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 274 drivers/misc/habanalabs/goya/goya_security.c u32 pb_addr, mask; mask 283 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_0_GLBL_CFG0 & 0x7F) >> 2); mask 284 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_CFG1 & 0x7F) >> 2); mask 285 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_PROT & 0x7F) >> 2); mask 286 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_CFG & 0x7F) >> 2); mask 287 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 288 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 289 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_ERR_WDATA & 0x7F) >> 2); mask 290 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 291 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 292 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_STS0 & 0x7F) >> 2); mask 293 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_GLBL_STS1 & 0x7F) >> 2); mask 294 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_BASE_LO & 0x7F) >> 2); mask 295 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_BASE_HI & 0x7F) >> 2); mask 296 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_SIZE & 0x7F) >> 2); mask 297 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_PI & 0x7F) >> 2); mask 298 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_CI & 0x7F) >> 2); mask 299 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_CFG0 & 0x7F) >> 2); mask 300 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_CFG1 & 0x7F) >> 2); mask 301 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_ARUSER & 0x7F) >> 2); mask 303 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 307 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_0_PQ_PUSH0 & 0x7F) >> 2); mask 308 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_PUSH1 & 0x7F) >> 2); mask 309 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_PUSH2 & 0x7F) >> 2); mask 310 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_PUSH3 & 0x7F) >> 2); mask 311 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_STS0 & 0x7F) >> 2); mask 312 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_STS1 & 0x7F) >> 2); mask 313 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 314 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 315 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 316 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 317 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_CFG0 & 0x7F) >> 2); mask 318 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_CFG1 & 0x7F) >> 2); mask 319 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_ARUSER & 0x7F) >> 2); mask 320 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO & 0x7F) >> 2); mask 321 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI & 0x7F) >> 2); mask 322 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE & 0x7F) >> 2); mask 323 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_CTL & 0x7F) >> 2); mask 324 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_PTR_LO_STS & 0x7F) >> 2); mask 325 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_PTR_HI_STS & 0x7F) >> 2); mask 326 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_TSIZE_STS & 0x7F) >> 2); mask 327 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_CTL_STS & 0x7F) >> 2); mask 328 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_STS0 & 0x7F) >> 2); mask 329 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_STS1 & 0x7F) >> 2); mask 330 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 331 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 332 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 333 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 335 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 339 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_0_CQ_IFIFO_CNT & 0x7F) >> 2); mask 340 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 341 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 342 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 343 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 344 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 345 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 346 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 347 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 348 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 349 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 350 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 351 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 352 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 353 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 355 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 361 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_1_GLBL_CFG0 & 0x7F) >> 2); mask 362 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_CFG1 & 0x7F) >> 2); mask 363 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_PROT & 0x7F) >> 2); mask 364 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_CFG & 0x7F) >> 2); mask 365 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 366 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 367 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_ERR_WDATA & 0x7F) >> 2); mask 368 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 369 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 370 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_STS0 & 0x7F) >> 2); mask 371 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_GLBL_STS1 & 0x7F) >> 2); mask 372 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_BASE_LO & 0x7F) >> 2); mask 373 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_BASE_HI & 0x7F) >> 2); mask 374 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_SIZE & 0x7F) >> 2); mask 375 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_PI & 0x7F) >> 2); mask 376 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_CI & 0x7F) >> 2); mask 377 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_CFG0 & 0x7F) >> 2); mask 378 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_CFG1 & 0x7F) >> 2); mask 379 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_ARUSER & 0x7F) >> 2); mask 381 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 385 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_1_PQ_PUSH0 & 0x7F) >> 2); mask 386 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_PUSH1 & 0x7F) >> 2); mask 387 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_PUSH2 & 0x7F) >> 2); mask 388 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_PUSH3 & 0x7F) >> 2); mask 389 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_STS0 & 0x7F) >> 2); mask 390 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_STS1 & 0x7F) >> 2); mask 391 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 392 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 393 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 394 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 395 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_CFG0 & 0x7F) >> 2); mask 396 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_CFG1 & 0x7F) >> 2); mask 397 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_ARUSER & 0x7F) >> 2); mask 398 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO & 0x7F) >> 2); mask 399 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI & 0x7F) >> 2); mask 400 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE & 0x7F) >> 2); mask 401 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_CTL & 0x7F) >> 2); mask 402 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_PTR_LO_STS & 0x7F) >> 2); mask 403 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_PTR_HI_STS & 0x7F) >> 2); mask 404 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_TSIZE_STS & 0x7F) >> 2); mask 405 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_CTL_STS & 0x7F) >> 2); mask 406 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_STS0 & 0x7F) >> 2); mask 407 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_STS1 & 0x7F) >> 2); mask 408 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 409 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 410 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 411 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 413 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 417 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_1_CQ_IFIFO_CNT & 0x7F) >> 2); mask 418 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 419 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 420 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 421 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 422 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 423 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 424 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 425 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 426 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 427 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 428 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 429 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 430 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 431 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_1_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 433 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 439 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_2_GLBL_CFG0 & 0x7F) >> 2); mask 440 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_CFG1 & 0x7F) >> 2); mask 441 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_PROT & 0x7F) >> 2); mask 442 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_CFG & 0x7F) >> 2); mask 443 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 444 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 445 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_ERR_WDATA & 0x7F) >> 2); mask 446 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 447 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 448 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_STS0 & 0x7F) >> 2); mask 449 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_GLBL_STS1 & 0x7F) >> 2); mask 450 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_BASE_LO & 0x7F) >> 2); mask 451 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_BASE_HI & 0x7F) >> 2); mask 452 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_SIZE & 0x7F) >> 2); mask 453 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_PI & 0x7F) >> 2); mask 454 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_CI & 0x7F) >> 2); mask 455 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_CFG0 & 0x7F) >> 2); mask 456 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_CFG1 & 0x7F) >> 2); mask 457 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_ARUSER & 0x7F) >> 2); mask 459 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 463 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_2_PQ_PUSH0 & 0x7F) >> 2); mask 464 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_PUSH1 & 0x7F) >> 2); mask 465 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_PUSH2 & 0x7F) >> 2); mask 466 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_PUSH3 & 0x7F) >> 2); mask 467 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_STS0 & 0x7F) >> 2); mask 468 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_STS1 & 0x7F) >> 2); mask 469 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 470 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 471 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 472 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 473 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_CFG0 & 0x7F) >> 2); mask 474 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_CFG1 & 0x7F) >> 2); mask 475 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_ARUSER & 0x7F) >> 2); mask 476 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO & 0x7F) >> 2); mask 477 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI & 0x7F) >> 2); mask 478 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE & 0x7F) >> 2); mask 479 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_CTL & 0x7F) >> 2); mask 480 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_PTR_LO_STS & 0x7F) >> 2); mask 481 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_PTR_HI_STS & 0x7F) >> 2); mask 482 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_TSIZE_STS & 0x7F) >> 2); mask 483 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_CTL_STS & 0x7F) >> 2); mask 484 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_STS0 & 0x7F) >> 2); mask 485 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_STS1 & 0x7F) >> 2); mask 486 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 487 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 488 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 489 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 491 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 495 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_2_CQ_IFIFO_CNT & 0x7F) >> 2); mask 496 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 497 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 498 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 499 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 500 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 501 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 502 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 503 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 504 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 505 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 506 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 507 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 508 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 509 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_2_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 511 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 517 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_3_GLBL_CFG0 & 0x7F) >> 2); mask 518 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_CFG1 & 0x7F) >> 2); mask 519 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_PROT & 0x7F) >> 2); mask 520 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_CFG & 0x7F) >> 2); mask 521 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 522 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 523 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_ERR_WDATA & 0x7F) >> 2); mask 524 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 525 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 526 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_STS0 & 0x7F) >> 2); mask 527 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_GLBL_STS1 & 0x7F) >> 2); mask 528 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_BASE_LO & 0x7F) >> 2); mask 529 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_BASE_HI & 0x7F) >> 2); mask 530 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_SIZE & 0x7F) >> 2); mask 531 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_PI & 0x7F) >> 2); mask 532 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_CI & 0x7F) >> 2); mask 533 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_CFG0 & 0x7F) >> 2); mask 534 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_CFG1 & 0x7F) >> 2); mask 535 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_ARUSER & 0x7F) >> 2); mask 537 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 541 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_3_PQ_PUSH0 & 0x7F) >> 2); mask 542 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_PUSH1 & 0x7F) >> 2); mask 543 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_PUSH2 & 0x7F) >> 2); mask 544 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_PUSH3 & 0x7F) >> 2); mask 545 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_STS0 & 0x7F) >> 2); mask 546 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_STS1 & 0x7F) >> 2); mask 547 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 548 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 549 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 550 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 551 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_CFG0 & 0x7F) >> 2); mask 552 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_CFG1 & 0x7F) >> 2); mask 553 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_ARUSER & 0x7F) >> 2); mask 554 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO & 0x7F) >> 2); mask 555 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI & 0x7F) >> 2); mask 556 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE & 0x7F) >> 2); mask 557 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_CTL & 0x7F) >> 2); mask 558 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_PTR_LO_STS & 0x7F) >> 2); mask 559 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_PTR_HI_STS & 0x7F) >> 2); mask 560 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_TSIZE_STS & 0x7F) >> 2); mask 561 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_CTL_STS & 0x7F) >> 2); mask 562 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_STS0 & 0x7F) >> 2); mask 563 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_STS1 & 0x7F) >> 2); mask 564 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 565 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 566 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 567 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 569 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 573 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_3_CQ_IFIFO_CNT & 0x7F) >> 2); mask 574 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 575 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 576 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 577 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 578 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 579 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 580 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 581 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 582 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 583 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 584 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 585 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 586 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 587 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_3_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 589 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 595 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_4_GLBL_CFG0 & 0x7F) >> 2); mask 596 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_CFG1 & 0x7F) >> 2); mask 597 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_PROT & 0x7F) >> 2); mask 598 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_CFG & 0x7F) >> 2); mask 599 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 600 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 601 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_ERR_WDATA & 0x7F) >> 2); mask 602 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 603 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 604 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_STS0 & 0x7F) >> 2); mask 605 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_GLBL_STS1 & 0x7F) >> 2); mask 606 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_BASE_LO & 0x7F) >> 2); mask 607 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_BASE_HI & 0x7F) >> 2); mask 608 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_SIZE & 0x7F) >> 2); mask 609 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_PI & 0x7F) >> 2); mask 610 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_CI & 0x7F) >> 2); mask 611 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_CFG0 & 0x7F) >> 2); mask 612 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_CFG1 & 0x7F) >> 2); mask 613 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_ARUSER & 0x7F) >> 2); mask 615 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 619 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_4_PQ_PUSH0 & 0x7F) >> 2); mask 620 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_PUSH1 & 0x7F) >> 2); mask 621 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_PUSH2 & 0x7F) >> 2); mask 622 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_PUSH3 & 0x7F) >> 2); mask 623 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_STS0 & 0x7F) >> 2); mask 624 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_STS1 & 0x7F) >> 2); mask 625 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 626 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 627 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 628 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 629 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_CFG0 & 0x7F) >> 2); mask 630 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_CFG1 & 0x7F) >> 2); mask 631 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_ARUSER & 0x7F) >> 2); mask 632 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO & 0x7F) >> 2); mask 633 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI & 0x7F) >> 2); mask 634 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE & 0x7F) >> 2); mask 635 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_CTL & 0x7F) >> 2); mask 636 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_PTR_LO_STS & 0x7F) >> 2); mask 637 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_PTR_HI_STS & 0x7F) >> 2); mask 638 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_TSIZE_STS & 0x7F) >> 2); mask 639 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_CTL_STS & 0x7F) >> 2); mask 640 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_STS0 & 0x7F) >> 2); mask 641 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_STS1 & 0x7F) >> 2); mask 642 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 643 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 644 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 645 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 647 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 651 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmDMA_QM_4_CQ_IFIFO_CNT & 0x7F) >> 2); mask 652 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 653 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 654 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 655 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 656 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 657 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 658 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 659 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 660 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 661 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 662 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 663 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 664 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 665 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmDMA_QM_4_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 667 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 674 drivers/misc/habanalabs/goya/goya_security.c u32 pb_addr, mask; mask 683 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CFG_SEMAPHORE & 0x7F) >> 2); mask 684 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_VFLAGS & 0x7F) >> 2); mask 685 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_SFLAGS & 0x7F) >> 2); mask 686 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_LFSR_POLYNOM & 0x7F) >> 2); mask 687 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_STATUS & 0x7F) >> 2); mask 689 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 694 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 695 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 696 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 697 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 698 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 699 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_TPC_STALL & 0x7F) >> 2); mask 700 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_MSS_CONFIG & 0x7F) >> 2); mask 701 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_TPC_INTR_CAUSE & 0x7F) >> 2); mask 702 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_TPC_INTR_MASK & 0x7F) >> 2); mask 704 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 708 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CFG_ARUSER & 0x7F) >> 2); mask 709 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_AWUSER & 0x7F) >> 2); mask 711 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 716 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 717 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 718 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 719 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 720 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 721 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 722 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 723 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 724 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 725 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 726 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 727 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 729 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 733 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_QM_GLBL_CFG0 & 0x7F) >> 2); mask 734 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_CFG1 & 0x7F) >> 2); mask 735 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_PROT & 0x7F) >> 2); mask 736 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 737 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 738 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 739 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 740 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 741 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 742 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_STS0 & 0x7F) >> 2); mask 743 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_GLBL_STS1 & 0x7F) >> 2); mask 744 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_BASE_LO & 0x7F) >> 2); mask 745 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_BASE_HI & 0x7F) >> 2); mask 746 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_SIZE & 0x7F) >> 2); mask 747 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_PI & 0x7F) >> 2); mask 748 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_CI & 0x7F) >> 2); mask 749 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_CFG0 & 0x7F) >> 2); mask 750 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_CFG1 & 0x7F) >> 2); mask 751 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_ARUSER & 0x7F) >> 2); mask 753 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 757 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_QM_PQ_PUSH0 & 0x7F) >> 2); mask 758 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_PUSH1 & 0x7F) >> 2); mask 759 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_PUSH2 & 0x7F) >> 2); mask 760 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_PUSH3 & 0x7F) >> 2); mask 761 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_STS0 & 0x7F) >> 2); mask 762 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_STS1 & 0x7F) >> 2); mask 763 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 764 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 765 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 766 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 767 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_CFG0 & 0x7F) >> 2); mask 768 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_CFG1 & 0x7F) >> 2); mask 769 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_ARUSER & 0x7F) >> 2); mask 770 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO & 0x7F) >> 2); mask 771 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI & 0x7F) >> 2); mask 772 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_TSIZE & 0x7F) >> 2); mask 773 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_CTL & 0x7F) >> 2); mask 774 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 775 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 776 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 777 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_CTL_STS & 0x7F) >> 2); mask 778 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_STS0 & 0x7F) >> 2); mask 779 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_STS1 & 0x7F) >> 2); mask 780 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 781 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 782 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 783 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 785 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 789 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 790 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 791 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 792 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 793 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 794 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 795 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 796 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 797 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 798 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 799 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 800 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 801 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 802 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 803 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 805 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 809 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 810 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 811 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 812 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 813 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 814 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 815 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 816 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 817 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 818 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 819 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 821 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 825 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 826 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 827 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 828 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 829 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 830 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 831 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 832 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 833 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 834 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 835 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 836 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 837 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 839 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 843 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 844 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 845 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 846 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 847 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 848 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 849 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 850 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 851 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 852 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 853 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 854 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 855 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 856 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 857 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 858 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_STS & 0x7F) >> 2); mask 859 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 861 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 866 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC0_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 867 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 868 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 869 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 870 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC0_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 872 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 881 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 882 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 883 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 884 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 886 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 890 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CFG_ARUSER & 0x7F) >> 2); mask 891 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_AWUSER & 0x7F) >> 2); mask 893 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 898 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 899 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 900 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 901 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 902 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 903 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 904 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 905 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 906 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 907 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 908 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 909 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 911 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 915 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_QM_GLBL_CFG0 & 0x7F) >> 2); mask 916 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_CFG1 & 0x7F) >> 2); mask 917 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_PROT & 0x7F) >> 2); mask 918 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 919 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 920 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 921 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 922 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 923 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 924 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_STS0 & 0x7F) >> 2); mask 925 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_GLBL_STS1 & 0x7F) >> 2); mask 926 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_BASE_LO & 0x7F) >> 2); mask 927 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_BASE_HI & 0x7F) >> 2); mask 928 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_SIZE & 0x7F) >> 2); mask 929 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_PI & 0x7F) >> 2); mask 930 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_CI & 0x7F) >> 2); mask 931 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_CFG0 & 0x7F) >> 2); mask 932 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_CFG1 & 0x7F) >> 2); mask 933 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_ARUSER & 0x7F) >> 2); mask 935 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 939 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_QM_PQ_PUSH0 & 0x7F) >> 2); mask 940 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_PUSH1 & 0x7F) >> 2); mask 941 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_PUSH2 & 0x7F) >> 2); mask 942 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_PUSH3 & 0x7F) >> 2); mask 943 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_STS0 & 0x7F) >> 2); mask 944 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_STS1 & 0x7F) >> 2); mask 945 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 946 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 947 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 948 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 949 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_CFG0 & 0x7F) >> 2); mask 950 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_CFG1 & 0x7F) >> 2); mask 951 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_ARUSER & 0x7F) >> 2); mask 952 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO & 0x7F) >> 2); mask 953 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI & 0x7F) >> 2); mask 954 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_TSIZE & 0x7F) >> 2); mask 955 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_CTL & 0x7F) >> 2); mask 956 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 957 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 958 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 959 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_CTL_STS & 0x7F) >> 2); mask 960 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_STS0 & 0x7F) >> 2); mask 961 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_STS1 & 0x7F) >> 2); mask 962 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 963 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 964 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 965 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 967 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 971 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 972 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 973 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 974 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 975 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 976 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 977 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 978 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 979 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 980 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 981 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 982 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 983 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 984 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 985 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 987 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 991 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 992 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 993 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 994 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 995 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 996 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 997 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 998 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 999 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1000 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1001 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1003 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1007 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1008 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1009 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1010 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1011 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1012 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1013 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1014 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1015 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1016 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1017 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1018 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1019 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1021 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1025 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1026 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1027 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1028 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1029 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1030 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1031 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1032 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1033 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1034 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1035 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1036 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1037 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1038 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1039 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1040 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_STS & 0x7F) >> 2); mask 1041 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1043 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1048 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC1_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1049 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1050 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1051 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1052 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC1_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1054 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1063 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1064 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1065 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1066 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1068 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1072 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CFG_ARUSER & 0x7F) >> 2); mask 1073 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_AWUSER & 0x7F) >> 2); mask 1075 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1080 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1081 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1082 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1083 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1084 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1085 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1086 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1087 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1088 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1089 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 1090 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 1091 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 1093 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1097 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_QM_GLBL_CFG0 & 0x7F) >> 2); mask 1098 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_CFG1 & 0x7F) >> 2); mask 1099 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_PROT & 0x7F) >> 2); mask 1100 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 1101 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1102 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1103 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1104 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1105 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1106 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_STS0 & 0x7F) >> 2); mask 1107 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_GLBL_STS1 & 0x7F) >> 2); mask 1108 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_BASE_LO & 0x7F) >> 2); mask 1109 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_BASE_HI & 0x7F) >> 2); mask 1110 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_SIZE & 0x7F) >> 2); mask 1111 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_PI & 0x7F) >> 2); mask 1112 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_CI & 0x7F) >> 2); mask 1113 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_CFG0 & 0x7F) >> 2); mask 1114 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_CFG1 & 0x7F) >> 2); mask 1115 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_ARUSER & 0x7F) >> 2); mask 1117 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1121 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_QM_PQ_PUSH0 & 0x7F) >> 2); mask 1122 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_PUSH1 & 0x7F) >> 2); mask 1123 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_PUSH2 & 0x7F) >> 2); mask 1124 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_PUSH3 & 0x7F) >> 2); mask 1125 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_STS0 & 0x7F) >> 2); mask 1126 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_STS1 & 0x7F) >> 2); mask 1127 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1128 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1129 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1130 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1131 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_CFG0 & 0x7F) >> 2); mask 1132 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_CFG1 & 0x7F) >> 2); mask 1133 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_ARUSER & 0x7F) >> 2); mask 1134 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO & 0x7F) >> 2); mask 1135 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI & 0x7F) >> 2); mask 1136 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_TSIZE & 0x7F) >> 2); mask 1137 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_CTL & 0x7F) >> 2); mask 1138 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1139 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1140 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 1141 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_CTL_STS & 0x7F) >> 2); mask 1142 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_STS0 & 0x7F) >> 2); mask 1143 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_STS1 & 0x7F) >> 2); mask 1144 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1145 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1146 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1147 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1149 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1153 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1154 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1155 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1156 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1157 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1158 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1159 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1160 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1161 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1162 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1163 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1164 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1165 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1166 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1167 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1169 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1173 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 1174 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 1175 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 1176 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 1177 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1178 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1179 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1180 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1181 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1182 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1183 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1185 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1189 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1190 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1191 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1192 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1193 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1194 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1195 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1196 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1197 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1198 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1199 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1200 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1201 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1203 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1207 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1208 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1209 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1210 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1211 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1212 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1213 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1214 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1215 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1216 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1217 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1218 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1219 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1220 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1221 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1222 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_STS & 0x7F) >> 2); mask 1223 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1225 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1230 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC2_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1231 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1232 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1233 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1234 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC2_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1236 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1245 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1246 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1247 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1248 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1250 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1254 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CFG_ARUSER & 0x7F) >> 2); mask 1255 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_AWUSER & 0x7F) >> 2); mask 1257 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1262 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1263 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1264 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1265 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1266 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1267 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1268 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1269 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1270 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1271 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 1272 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 1273 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 1275 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1279 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2); mask 1280 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_CFG1 & 0x7F) >> 2); mask 1281 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_PROT & 0x7F) >> 2); mask 1282 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 1283 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1284 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1285 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1286 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1287 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1288 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_STS0 & 0x7F) >> 2); mask 1289 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_GLBL_STS1 & 0x7F) >> 2); mask 1290 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_BASE_LO & 0x7F) >> 2); mask 1291 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_BASE_HI & 0x7F) >> 2); mask 1292 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_SIZE & 0x7F) >> 2); mask 1293 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_PI & 0x7F) >> 2); mask 1294 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_CI & 0x7F) >> 2); mask 1295 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_CFG0 & 0x7F) >> 2); mask 1296 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_CFG1 & 0x7F) >> 2); mask 1297 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_ARUSER & 0x7F) >> 2); mask 1299 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1303 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_QM_PQ_PUSH0 & 0x7F) >> 2); mask 1304 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_PUSH1 & 0x7F) >> 2); mask 1305 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_PUSH2 & 0x7F) >> 2); mask 1306 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_PUSH3 & 0x7F) >> 2); mask 1307 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_STS0 & 0x7F) >> 2); mask 1308 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_STS1 & 0x7F) >> 2); mask 1309 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1310 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1311 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1312 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1313 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_CFG0 & 0x7F) >> 2); mask 1314 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_CFG1 & 0x7F) >> 2); mask 1315 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_ARUSER & 0x7F) >> 2); mask 1316 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO & 0x7F) >> 2); mask 1317 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI & 0x7F) >> 2); mask 1318 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_TSIZE & 0x7F) >> 2); mask 1319 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_CTL & 0x7F) >> 2); mask 1320 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1321 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1322 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 1323 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_CTL_STS & 0x7F) >> 2); mask 1324 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_STS0 & 0x7F) >> 2); mask 1325 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_STS1 & 0x7F) >> 2); mask 1326 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1327 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1328 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1329 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1331 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1335 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1336 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1337 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1338 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1339 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1340 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1341 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1342 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1343 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1344 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1345 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1346 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1347 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1348 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1349 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1351 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1355 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 1356 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 1357 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 1358 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 1359 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1360 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1361 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1362 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1363 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1364 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1365 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1367 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1371 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1372 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1373 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1374 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1375 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1376 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1377 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1378 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1379 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1380 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1381 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1382 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1383 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1385 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1389 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1390 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1391 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1392 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1393 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1394 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1395 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1396 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1397 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1398 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1399 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1400 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1401 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1402 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1403 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1404 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_STS & 0x7F) >> 2); mask 1405 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1407 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1412 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC3_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1413 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1414 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1415 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1416 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC3_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1418 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1427 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1428 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1429 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1430 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1432 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1436 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CFG_ARUSER & 0x7F) >> 2); mask 1437 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_AWUSER & 0x7F) >> 2); mask 1439 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1444 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1445 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1446 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1447 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1448 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1449 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1450 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1451 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1452 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1453 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 1454 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 1455 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 1457 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1461 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_QM_GLBL_CFG0 & 0x7F) >> 2); mask 1462 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_CFG1 & 0x7F) >> 2); mask 1463 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_PROT & 0x7F) >> 2); mask 1464 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 1465 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1466 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1467 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1468 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1469 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1470 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_STS0 & 0x7F) >> 2); mask 1471 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_GLBL_STS1 & 0x7F) >> 2); mask 1472 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_BASE_LO & 0x7F) >> 2); mask 1473 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_BASE_HI & 0x7F) >> 2); mask 1474 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_SIZE & 0x7F) >> 2); mask 1475 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_PI & 0x7F) >> 2); mask 1476 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_CI & 0x7F) >> 2); mask 1477 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_CFG0 & 0x7F) >> 2); mask 1478 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_CFG1 & 0x7F) >> 2); mask 1479 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_ARUSER & 0x7F) >> 2); mask 1481 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1485 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_QM_PQ_PUSH0 & 0x7F) >> 2); mask 1486 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_PUSH1 & 0x7F) >> 2); mask 1487 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_PUSH2 & 0x7F) >> 2); mask 1488 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_PUSH3 & 0x7F) >> 2); mask 1489 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_STS0 & 0x7F) >> 2); mask 1490 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_STS1 & 0x7F) >> 2); mask 1491 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1492 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1493 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1494 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1495 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_CFG0 & 0x7F) >> 2); mask 1496 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_CFG1 & 0x7F) >> 2); mask 1497 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_ARUSER & 0x7F) >> 2); mask 1498 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO & 0x7F) >> 2); mask 1499 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI & 0x7F) >> 2); mask 1500 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_TSIZE & 0x7F) >> 2); mask 1501 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_CTL & 0x7F) >> 2); mask 1502 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1503 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1504 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 1505 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_CTL_STS & 0x7F) >> 2); mask 1506 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_STS0 & 0x7F) >> 2); mask 1507 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_STS1 & 0x7F) >> 2); mask 1508 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1509 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1510 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1511 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1513 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1517 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1518 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1519 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1520 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1521 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1522 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1523 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1524 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1525 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1526 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1527 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1528 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1529 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1530 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1531 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1533 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1537 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 1538 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 1539 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 1540 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 1541 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1542 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1543 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1544 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1545 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1546 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1547 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1549 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1553 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1554 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1555 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1556 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1557 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1558 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1559 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1560 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1561 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1562 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1563 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1564 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1565 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1567 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1571 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1572 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1573 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1574 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1575 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1576 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1577 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1578 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1579 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1580 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1581 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1582 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1583 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1584 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1585 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1586 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_STS & 0x7F) >> 2); mask 1587 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1589 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1594 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC4_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1595 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1596 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1597 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1598 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC4_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1600 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1609 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1610 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1611 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1612 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1614 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1618 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CFG_ARUSER & 0x7F) >> 2); mask 1619 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_AWUSER & 0x7F) >> 2); mask 1621 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1626 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1627 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1628 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1629 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1630 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1631 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1632 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1633 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1634 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1635 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 1636 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 1637 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 1639 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1643 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_QM_GLBL_CFG0 & 0x7F) >> 2); mask 1644 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_CFG1 & 0x7F) >> 2); mask 1645 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_PROT & 0x7F) >> 2); mask 1646 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 1647 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1648 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1649 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1650 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1651 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1652 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_STS0 & 0x7F) >> 2); mask 1653 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_GLBL_STS1 & 0x7F) >> 2); mask 1654 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_BASE_LO & 0x7F) >> 2); mask 1655 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_BASE_HI & 0x7F) >> 2); mask 1656 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_SIZE & 0x7F) >> 2); mask 1657 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_PI & 0x7F) >> 2); mask 1658 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_CI & 0x7F) >> 2); mask 1659 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_CFG0 & 0x7F) >> 2); mask 1660 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_CFG1 & 0x7F) >> 2); mask 1661 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_ARUSER & 0x7F) >> 2); mask 1663 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1667 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_QM_PQ_PUSH0 & 0x7F) >> 2); mask 1668 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_PUSH1 & 0x7F) >> 2); mask 1669 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_PUSH2 & 0x7F) >> 2); mask 1670 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_PUSH3 & 0x7F) >> 2); mask 1671 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_STS0 & 0x7F) >> 2); mask 1672 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_STS1 & 0x7F) >> 2); mask 1673 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1674 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1675 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1676 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1677 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_CFG0 & 0x7F) >> 2); mask 1678 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_CFG1 & 0x7F) >> 2); mask 1679 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_ARUSER & 0x7F) >> 2); mask 1680 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO & 0x7F) >> 2); mask 1681 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI & 0x7F) >> 2); mask 1682 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_TSIZE & 0x7F) >> 2); mask 1683 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_CTL & 0x7F) >> 2); mask 1684 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1685 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1686 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 1687 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_CTL_STS & 0x7F) >> 2); mask 1688 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_STS0 & 0x7F) >> 2); mask 1689 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_STS1 & 0x7F) >> 2); mask 1690 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1691 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1692 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1693 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1695 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1699 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1700 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1701 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1702 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1703 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1704 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1705 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1706 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1707 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1708 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1709 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1710 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1711 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1712 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1713 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1715 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1719 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 1720 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 1721 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 1722 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 1723 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1724 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1725 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1726 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1727 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1728 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1729 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1731 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1735 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1736 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1737 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1738 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1739 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1740 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1741 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1742 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1743 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1744 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1745 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1746 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1747 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1749 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1753 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1754 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1755 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1756 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1757 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1758 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1759 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1760 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1761 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1762 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1763 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1764 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1765 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1766 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1767 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1768 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_STS & 0x7F) >> 2); mask 1769 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1771 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1776 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC5_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1777 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1778 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1779 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1780 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC5_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1782 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1791 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1792 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1793 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1794 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1796 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1800 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CFG_ARUSER & 0x7F) >> 2); mask 1801 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_AWUSER & 0x7F) >> 2); mask 1803 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1808 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1809 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1810 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1811 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1812 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1813 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1814 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1815 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1816 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1817 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 1818 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 1819 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 1821 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1825 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_QM_GLBL_CFG0 & 0x7F) >> 2); mask 1826 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_CFG1 & 0x7F) >> 2); mask 1827 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_PROT & 0x7F) >> 2); mask 1828 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 1829 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1830 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1831 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1832 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1833 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1834 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_STS0 & 0x7F) >> 2); mask 1835 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_GLBL_STS1 & 0x7F) >> 2); mask 1836 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_BASE_LO & 0x7F) >> 2); mask 1837 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_BASE_HI & 0x7F) >> 2); mask 1838 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_SIZE & 0x7F) >> 2); mask 1839 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_PI & 0x7F) >> 2); mask 1840 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_CI & 0x7F) >> 2); mask 1841 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_CFG0 & 0x7F) >> 2); mask 1842 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_CFG1 & 0x7F) >> 2); mask 1843 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_ARUSER & 0x7F) >> 2); mask 1845 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1849 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_QM_PQ_PUSH0 & 0x7F) >> 2); mask 1850 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_PUSH1 & 0x7F) >> 2); mask 1851 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_PUSH2 & 0x7F) >> 2); mask 1852 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_PUSH3 & 0x7F) >> 2); mask 1853 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_STS0 & 0x7F) >> 2); mask 1854 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_STS1 & 0x7F) >> 2); mask 1855 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1856 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1857 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1858 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1859 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_CFG0 & 0x7F) >> 2); mask 1860 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_CFG1 & 0x7F) >> 2); mask 1861 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_ARUSER & 0x7F) >> 2); mask 1862 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO & 0x7F) >> 2); mask 1863 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI & 0x7F) >> 2); mask 1864 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_TSIZE & 0x7F) >> 2); mask 1865 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_CTL & 0x7F) >> 2); mask 1866 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1867 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1868 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 1869 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_CTL_STS & 0x7F) >> 2); mask 1870 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_STS0 & 0x7F) >> 2); mask 1871 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_STS1 & 0x7F) >> 2); mask 1872 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1873 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1874 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1875 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1877 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1881 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1882 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1883 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1884 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1885 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1886 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1887 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1888 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1889 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1890 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1891 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1892 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1893 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1894 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1895 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1897 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1901 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 1902 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 1903 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 1904 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 1905 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 1906 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 1907 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 1908 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 1909 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 1910 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 1911 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 1913 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1917 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 1918 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 1919 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 1920 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 1921 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 1922 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 1923 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 1924 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 1925 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 1926 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 1927 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 1928 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 1929 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 1931 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1935 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 1936 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 1937 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 1938 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 1939 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 1940 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 1941 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 1942 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 1943 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 1944 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 1945 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 1946 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 1947 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 1948 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 1949 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 1950 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_STS & 0x7F) >> 2); mask 1951 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 1953 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1958 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC6_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 1959 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 1960 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 1961 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 1962 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC6_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 1964 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1973 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CFG_CFG_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1974 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_CFG_SUBTRACT_VALUE & 0x7F) >> 2); mask 1975 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); mask 1976 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); mask 1978 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1982 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CFG_ARUSER & 0x7F) >> 2); mask 1983 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_AWUSER & 0x7F) >> 2); mask 1985 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 1990 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CFG_FUNC_MBIST_CNTRL & 0x7F) >> 2); mask 1991 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_PAT & 0x7F) >> 2); mask 1992 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_0 & 0x7F) >> 2); mask 1993 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_1 & 0x7F) >> 2); mask 1994 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_2 & 0x7F) >> 2); mask 1995 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_3 & 0x7F) >> 2); mask 1996 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_4 & 0x7F) >> 2); mask 1997 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_5 & 0x7F) >> 2); mask 1998 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_6 & 0x7F) >> 2); mask 1999 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_7 & 0x7F) >> 2); mask 2000 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_8 & 0x7F) >> 2); mask 2001 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CFG_FUNC_MBIST_MEM_9 & 0x7F) >> 2); mask 2003 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2007 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_QM_GLBL_CFG0 & 0x7F) >> 2); mask 2008 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_CFG1 & 0x7F) >> 2); mask 2009 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_PROT & 0x7F) >> 2); mask 2010 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_ERR_CFG & 0x7F) >> 2); mask 2011 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 2012 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 2013 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_ERR_WDATA & 0x7F) >> 2); mask 2014 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 2015 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 2016 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_STS0 & 0x7F) >> 2); mask 2017 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_GLBL_STS1 & 0x7F) >> 2); mask 2018 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_BASE_LO & 0x7F) >> 2); mask 2019 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_BASE_HI & 0x7F) >> 2); mask 2020 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_SIZE & 0x7F) >> 2); mask 2021 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_PI & 0x7F) >> 2); mask 2022 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_CI & 0x7F) >> 2); mask 2023 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_CFG0 & 0x7F) >> 2); mask 2024 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_CFG1 & 0x7F) >> 2); mask 2025 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_ARUSER & 0x7F) >> 2); mask 2027 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2031 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_QM_PQ_PUSH0 & 0x7F) >> 2); mask 2032 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_PUSH1 & 0x7F) >> 2); mask 2033 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_PUSH2 & 0x7F) >> 2); mask 2034 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_PUSH3 & 0x7F) >> 2); mask 2035 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_STS0 & 0x7F) >> 2); mask 2036 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_STS1 & 0x7F) >> 2); mask 2037 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 2038 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 2039 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 2040 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_PQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 2041 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_CFG0 & 0x7F) >> 2); mask 2042 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_CFG1 & 0x7F) >> 2); mask 2043 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_ARUSER & 0x7F) >> 2); mask 2044 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO & 0x7F) >> 2); mask 2045 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI & 0x7F) >> 2); mask 2046 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_TSIZE & 0x7F) >> 2); mask 2047 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_CTL & 0x7F) >> 2); mask 2048 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_PTR_LO_STS & 0x7F) >> 2); mask 2049 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_PTR_HI_STS & 0x7F) >> 2); mask 2050 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_TSIZE_STS & 0x7F) >> 2); mask 2051 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_CTL_STS & 0x7F) >> 2); mask 2052 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_STS0 & 0x7F) >> 2); mask 2053 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_STS1 & 0x7F) >> 2); mask 2054 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 2055 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 2056 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 2057 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 2059 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2063 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_QM_CQ_IFIFO_CNT & 0x7F) >> 2); mask 2064 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 2065 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 2066 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 2067 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 2068 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 2069 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 2070 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 2071 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 2072 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 2073 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 2074 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 2075 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 2076 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 2077 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_QM_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 2079 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2083 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CMDQ_GLBL_CFG0 & 0x7F) >> 2); mask 2084 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_CFG1 & 0x7F) >> 2); mask 2085 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_PROT & 0x7F) >> 2); mask 2086 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_CFG & 0x7F) >> 2); mask 2087 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_LO & 0x7F) >> 2); mask 2088 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_ADDR_HI & 0x7F) >> 2); mask 2089 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_ERR_WDATA & 0x7F) >> 2); mask 2090 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_SECURE_PROPS & 0x7F) >> 2); mask 2091 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS & 0x7F) >> 2); mask 2092 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS0 & 0x7F) >> 2); mask 2093 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_GLBL_STS1 & 0x7F) >> 2); mask 2095 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2099 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CMDQ_CQ_CFG0 & 0x7F) >> 2); mask 2100 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_CFG1 & 0x7F) >> 2); mask 2101 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_ARUSER & 0x7F) >> 2); mask 2102 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_LO_STS & 0x7F) >> 2); mask 2103 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_PTR_HI_STS & 0x7F) >> 2); mask 2104 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_TSIZE_STS & 0x7F) >> 2); mask 2105 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_CTL_STS & 0x7F) >> 2); mask 2106 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_STS0 & 0x7F) >> 2); mask 2107 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_STS1 & 0x7F) >> 2); mask 2108 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_EN & 0x7F) >> 2); mask 2109 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN & 0x7F) >> 2); mask 2110 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_SAT & 0x7F) >> 2); mask 2111 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_RD_RATE_LIM_TOUT & 0x7F) >> 2); mask 2113 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2117 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CMDQ_CQ_IFIFO_CNT & 0x7F) >> 2); mask 2118 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_LO & 0x7F) >> 2); mask 2119 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE0_ADDR_HI & 0x7F) >> 2); mask 2120 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_LO & 0x7F) >> 2); mask 2121 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE1_ADDR_HI & 0x7F) >> 2); mask 2122 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_LO & 0x7F) >> 2); mask 2123 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE2_ADDR_HI & 0x7F) >> 2); mask 2124 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_LO & 0x7F) >> 2); mask 2125 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_MSG_BASE3_ADDR_HI & 0x7F) >> 2); mask 2126 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_TSIZE_OFFSET & 0x7F) >> 2); mask 2127 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET & 0x7F) >> 2); mask 2128 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET & 0x7F) >> 2); mask 2129 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET & 0x7F) >> 2); mask 2130 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET & 0x7F) >> 2); mask 2131 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_LDMA_COMMIT_OFFSET & 0x7F) >> 2); mask 2132 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_STS & 0x7F) >> 2); mask 2133 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_LO & 0x7F) >> 2); mask 2135 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2140 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC7_CMDQ_CP_CURRENT_INST_HI & 0x7F) >> 2); mask 2141 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_BARRIER_CFG & 0x7F) >> 2); mask 2142 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CP_DBG_0 & 0x7F) >> 2); mask 2143 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_ADDR & 0x7F) >> 2); mask 2144 drivers/misc/habanalabs/goya/goya_security.c mask |= 1 << ((mmTPC7_CMDQ_CQ_BUF_RDATA & 0x7F) >> 2); mask 2146 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, ~mask); mask 2179 drivers/misc/habanalabs/goya/goya_security.c u32 pb_addr, mask; mask 2264 drivers/misc/habanalabs/goya/goya_security.c mask = 1 << ((mmTPC_PLL_CLK_RLX_0 & 0x7C) >> 2); mask 2266 drivers/misc/habanalabs/goya/goya_security.c WREG32(pb_addr + word_offset, mask); mask 570 drivers/misc/habanalabs/habanalabs.h bool (*is_device_idle)(struct hl_device *hdev, u32 *mask, mask 1039 drivers/misc/habanalabs/habanalabs.h #define WREG32_P(reg, val, mask) \ mask 1042 drivers/misc/habanalabs/habanalabs.h tmp_ &= (mask); \ mask 1043 drivers/misc/habanalabs/habanalabs.h tmp_ |= ((val) & ~(mask)); \ mask 168 drivers/misc/habanalabs/mmu.c u64 virt_addr, u64 mask, u64 shift) mask 171 drivers/misc/habanalabs/mmu.c ((virt_addr & mask) >> shift); mask 51 drivers/misc/ibmasm/lowlevel.h static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask) mask 54 drivers/misc/ibmasm/lowlevel.h writel( readl(ctrl_reg) & ~mask, ctrl_reg); mask 57 drivers/misc/ibmasm/lowlevel.h static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask) mask 60 drivers/misc/ibmasm/lowlevel.h writel( readl(ctrl_reg) | mask, ctrl_reg); mask 1009 drivers/misc/ibmvmc.c unsigned int mask = 0; mask 1022 drivers/misc/ibmvmc.c mask |= POLLIN | POLLRDNORM; mask 1024 drivers/misc/ibmvmc.c return mask; mask 65 drivers/misc/isl29003.c u32 reg, u8 mask, u8 shift) mask 69 drivers/misc/isl29003.c return (data->reg_cache[reg] & mask) >> shift; mask 73 drivers/misc/isl29003.c u32 reg, u8 mask, u8 shift, u8 val) mask 85 drivers/misc/isl29003.c tmp &= ~mask; mask 566 drivers/misc/mei/main.c __poll_t mask = 0; mask 580 drivers/misc/mei/main.c mask = EPOLLERR; mask 587 drivers/misc/mei/main.c mask |= EPOLLPRI; mask 594 drivers/misc/mei/main.c mask |= EPOLLIN | EPOLLRDNORM; mask 602 drivers/misc/mei/main.c mask |= EPOLLOUT | EPOLLWRNORM; mask 607 drivers/misc/mei/main.c return mask; mask 57 drivers/misc/mei/pci-txe.c const int mask = BIT(SEC_BAR) | BIT(BRIDGE_BAR); mask 69 drivers/misc/mei/pci-txe.c err = pcim_iomap_regions(pdev, mask, KBUILD_MODNAME); mask 313 drivers/misc/mic/card/mic_device.c dma_cap_mask_t mask; mask 316 drivers/misc/mic/card/mic_device.c dma_cap_zero(mask); mask 317 drivers/misc/mic/card/mic_device.c dma_cap_set(DMA_MEMCPY, mask); mask 320 drivers/misc/mic/card/mic_device.c chan = dma_request_channel(mask, NULL, NULL); mask 410 drivers/misc/mic/host/mic_boot.c dma_cap_mask_t mask; mask 413 drivers/misc/mic/host/mic_boot.c dma_cap_zero(mask); mask 414 drivers/misc/mic/host/mic_boot.c dma_cap_set(DMA_MEMCPY, mask); mask 417 drivers/misc/mic/host/mic_boot.c chan = dma_request_channel(mask, mdev->ops->dma_filter, mask 27 drivers/misc/mic/host/mic_intr.c if (test_and_clear_bit(i, &irq_info->mask)) { mask 48 drivers/misc/mic/host/mic_intr.c u32 mask; mask 51 drivers/misc/mic/host/mic_intr.c mask = mdev->ops->ack_interrupt(mdev); mask 52 drivers/misc/mic/host/mic_intr.c if (!mask) mask 58 drivers/misc/mic/host/mic_intr.c if (mask & BIT(i)) { mask 64 drivers/misc/mic/host/mic_intr.c set_bit(i, &irq_info->mask); mask 78 drivers/misc/mic/host/mic_intr.h unsigned long mask; mask 1307 drivers/misc/mic/scif/scif_api.c __poll_t mask = 0; mask 1321 drivers/misc/mic/scif/scif_api.c mask |= EPOLLOUT; mask 1331 drivers/misc/mic/scif/scif_api.c mask |= EPOLLIN; mask 1346 drivers/misc/mic/scif/scif_api.c mask |= EPOLLIN; mask 1349 drivers/misc/mic/scif/scif_api.c mask |= EPOLLOUT; mask 1352 drivers/misc/mic/scif/scif_api.c mask |= EPOLLHUP; mask 1358 drivers/misc/mic/scif/scif_api.c mask |= EPOLLERR; mask 1361 drivers/misc/mic/scif/scif_api.c return mask; mask 1383 drivers/misc/mic/scif/scif_api.c __poll_t mask; mask 1392 drivers/misc/mic/scif/scif_api.c mask = __scif_pollfd(ufds[i].epd->anon, mask 1394 drivers/misc/mic/scif/scif_api.c mask &= ufds[i].events | EPOLLERR | EPOLLHUP; mask 1395 drivers/misc/mic/scif/scif_api.c if (mask) { mask 1399 drivers/misc/mic/scif/scif_api.c ufds[i].revents = mask; mask 1018 drivers/misc/mic/vop/vop_vringh.c __poll_t mask = 0; mask 1022 drivers/misc/mic/vop/vop_vringh.c mask = EPOLLERR; mask 1027 drivers/misc/mic/vop/vop_vringh.c mask = EPOLLERR; mask 1030 drivers/misc/mic/vop/vop_vringh.c mask = EPOLLIN | EPOLLOUT; mask 1034 drivers/misc/mic/vop/vop_vringh.c return mask; mask 327 drivers/misc/ocxl/file.c unsigned int mask = 0; mask 339 drivers/misc/ocxl/file.c mask = EPOLLIN | EPOLLRDNORM; mask 341 drivers/misc/ocxl/file.c mask = EPOLLERR; mask 343 drivers/misc/ocxl/file.c return mask; mask 110 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u32 mask) mask 125 drivers/misc/ocxl/mmio.c tmp |= mask; mask 131 drivers/misc/ocxl/mmio.c tmp |= mask; mask 141 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u64 mask) mask 156 drivers/misc/ocxl/mmio.c tmp |= mask; mask 162 drivers/misc/ocxl/mmio.c tmp |= mask; mask 172 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u32 mask) mask 187 drivers/misc/ocxl/mmio.c tmp &= ~mask; mask 193 drivers/misc/ocxl/mmio.c tmp &= ~mask; mask 204 drivers/misc/ocxl/mmio.c enum ocxl_endian endian, u64 mask) mask 219 drivers/misc/ocxl/mmio.c tmp &= ~mask; mask 225 drivers/misc/ocxl/mmio.c tmp &= ~mask; mask 144 drivers/misc/pch_phub.c unsigned int data, unsigned int mask) mask 147 drivers/misc/pch_phub.c iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); mask 302 drivers/misc/pch_phub.c unsigned int mask; mask 304 drivers/misc/pch_phub.c mask = ~(0xFF << pos); mask 310 drivers/misc/pch_phub.c iowrite32((word_data & mask) | (u32)data << pos, mem_addr); mask 132 drivers/misc/phantom.c pr_debug("phantom: SRS %u regs %x\n", rs.count, rs.mask); mask 139 drivers/misc/phantom.c if (rs.mask & BIT(i)) mask 167 drivers/misc/phantom.c pr_debug("phantom: GRS %u regs %x\n", rs.count, rs.mask); mask 170 drivers/misc/phantom.c if (rs.mask & BIT(i)) mask 258 drivers/misc/phantom.c __poll_t mask = 0; mask 264 drivers/misc/phantom.c mask = EPOLLERR; mask 266 drivers/misc/phantom.c mask = EPOLLIN | EPOLLRDNORM; mask 268 drivers/misc/phantom.c pr_debug("phantom_poll end: %x/%d\n", mask, atomic_read(&dev->counter)); mask 270 drivers/misc/phantom.c return mask; mask 303 drivers/misc/phantom.c if (r->mask & BIT(i)) mask 239 drivers/misc/pti.c int i, j, mask; mask 254 drivers/misc/pti.c mask = 0x80; mask 256 drivers/misc/pti.c if ((id_array[i] & mask) == 0) mask 258 drivers/misc/pti.c mask >>= 1; mask 262 drivers/misc/pti.c id_array[i] |= mask; mask 47 drivers/misc/sgi-xp/xpc_uv.c mask : 1, mask 164 drivers/misc/vmw_vmci/vmci_host.c __poll_t mask = 0; mask 176 drivers/misc/vmw_vmci/vmci_host.c mask = EPOLLIN; mask 180 drivers/misc/vmw_vmci/vmci_host.c return mask; mask 1030 drivers/misc/xilinx_sdfec.c __poll_t mask = 0; mask 1043 drivers/misc/xilinx_sdfec.c mask |= EPOLLIN | EPOLLPRI; mask 1046 drivers/misc/xilinx_sdfec.c mask |= EPOLLIN | EPOLLRDNORM; mask 1049 drivers/misc/xilinx_sdfec.c return mask; mask 1065 drivers/mmc/core/core.c u32 mask = 0; mask 1082 drivers/mmc/core/core.c mask |= 1 << vdd_max--; mask 1084 drivers/mmc/core/core.c return mask; mask 354 drivers/mmc/core/host.c int mmc_of_parse_voltage(struct device_node *np, u32 *mask) mask 382 drivers/mmc/core/host.c *mask |= ocr_mask; mask 891 drivers/mmc/core/sdio_uart.c unsigned int mask = TIOCM_DTR; mask 893 drivers/mmc/core/sdio_uart.c mask |= TIOCM_RTS; mask 894 drivers/mmc/core/sdio_uart.c sdio_uart_set_mctrl(port, mask); mask 2074 drivers/mmc/host/atmel-mci.c u32 status, mask, pending; mask 2079 drivers/mmc/host/atmel-mci.c mask = atmci_readl(host, ATMCI_IMR); mask 2080 drivers/mmc/host/atmel-mci.c pending = status & mask; mask 2355 drivers/mmc/host/atmel-mci.c dma_cap_mask_t mask; mask 2360 drivers/mmc/host/atmel-mci.c dma_cap_zero(mask); mask 2361 drivers/mmc/host/atmel-mci.c dma_cap_set(DMA_SLAVE, mask); mask 2363 drivers/mmc/host/atmel-mci.c host->dma.chan = dma_request_channel(mask, pdata->dma_filter, mask 164 drivers/mmc/host/au1xmmc.c static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask) mask 167 drivers/mmc/host/au1xmmc.c val |= mask; mask 187 drivers/mmc/host/au1xmmc.c static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask) mask 190 drivers/mmc/host/au1xmmc.c val &= ~mask; mask 592 drivers/mmc/host/au1xmmc.c u32 mask = SD_STATUS_DB | SD_STATUS_NE; mask 594 drivers/mmc/host/au1xmmc.c while((status & mask) != mask) mask 61 drivers/mmc/host/cb710-mmc.c unsigned short enable, unsigned short mask) mask 65 drivers/mmc/host/cb710-mmc.c mask |= CB710_MMC_IE_IRQ_ENABLE; mask 73 drivers/mmc/host/cb710-mmc.c & ~mask) | enable; mask 82 drivers/mmc/host/cb710-mmc.c unsigned short enable, unsigned short mask) mask 89 drivers/mmc/host/cb710-mmc.c __cb710_mmc_enable_irq(slot, enable, mask); mask 176 drivers/mmc/host/cb710-mmc.c static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask) mask 186 drivers/mmc/host/cb710-mmc.c while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) { mask 203 drivers/mmc/host/cb710-mmc.c limit, mask, e, x); mask 464 drivers/mmc/host/davinci_mmc.c int mask = rw_threshold - 1; mask 472 drivers/mmc/host/davinci_mmc.c if (sg_dma_len(data->sg + i) & mask) { mask 453 drivers/mmc/host/meson-gx-mmc.c mux->mask = CLK_SRC_MASK >> mux->shift; mask 125 drivers/mmc/host/meson-mx-sdio.c static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, mask 132 drivers/mmc/host/meson-mx-sdio.c regval &= ~mask; mask 133 drivers/mmc/host/meson-mx-sdio.c regval |= (val & mask); mask 564 drivers/mmc/host/mmci.c static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) mask 573 drivers/mmc/host/mmci.c mask0 |= mask; mask 579 drivers/mmc/host/mmci.c writel(mask, base + MMCIMASK1); mask 581 drivers/mmc/host/mmci.c host->mask1_reg = mask; mask 2176 drivers/mmc/host/mmci.c .mask = 0xff0fffff, mask 2181 drivers/mmc/host/mmci.c .mask = 0xff0fffff, mask 2186 drivers/mmc/host/mmci.c .mask = 0xff0fffff, mask 2191 drivers/mmc/host/mmci.c .mask = 0x000fffff, mask 2197 drivers/mmc/host/mmci.c .mask = 0x00ffffff, mask 2202 drivers/mmc/host/mmci.c .mask = 0xf0ffffff, mask 2207 drivers/mmc/host/mmci.c .mask = 0x00ffffff, mask 2212 drivers/mmc/host/mmci.c .mask = 0xf0ffffff, mask 2217 drivers/mmc/host/mmci.c .mask = 0xf0ffffff, mask 2222 drivers/mmc/host/mmci.c .mask = 0x00ffffff, mask 2227 drivers/mmc/host/mmci.c .mask = 0xf0ffffff, mask 2233 drivers/mmc/host/mmci.c .mask = 0x000fffff, mask 181 drivers/mmc/host/moxart-mmc.c u32 mask, u32 *status) mask 188 drivers/mmc/host/moxart-mmc.c if (!(*status & mask)) { mask 192 drivers/mmc/host/moxart-mmc.c writel(*status & mask, host->base + REG_CLEAR); mask 526 drivers/mmc/host/mxcmmc.c static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) mask 540 drivers/mmc/host/mxcmmc.c if (stat & mask) mask 1003 drivers/mmc/host/mxcmmc.c dma_cap_mask_t mask; mask 1132 drivers/mmc/host/mxcmmc.c dma_cap_zero(mask); mask 1133 drivers/mmc/host/mxcmmc.c dma_cap_set(DMA_SLAVE, mask); mask 1134 drivers/mmc/host/mxcmmc.c host->dma = dma_request_channel(mask, filter, host); mask 137 drivers/mmc/host/pxamci.c static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) mask 142 drivers/mmc/host/pxamci.c host->imask &= ~mask; mask 147 drivers/mmc/host/pxamci.c static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) mask 152 drivers/mmc/host/pxamci.c host->imask |= mask; mask 349 drivers/mmc/host/renesas_sdhi_sys_dmac.c dma_cap_mask_t mask; mask 355 drivers/mmc/host/renesas_sdhi_sys_dmac.c dma_cap_zero(mask); mask 356 drivers/mmc/host/renesas_sdhi_sys_dmac.c dma_cap_set(DMA_SLAVE, mask); mask 358 drivers/mmc/host/renesas_sdhi_sys_dmac.c host->chan_tx = dma_request_slave_channel_compat(mask, mask 378 drivers/mmc/host/renesas_sdhi_sys_dmac.c host->chan_rx = dma_request_slave_channel_compat(mask, mask 1172 drivers/mmc/host/rtsx_pci_sdmmc.c u8 stat, mask, val; mask 1192 drivers/mmc/host/rtsx_pci_sdmmc.c mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | mask 1196 drivers/mmc/host/rtsx_pci_sdmmc.c if ((stat & mask) != val) { mask 1207 drivers/mmc/host/rtsx_usb_sdmmc.c u8 mask = SD_DAT3_STATUS | SD_DAT2_STATUS | SD_DAT1_STATUS mask 1235 drivers/mmc/host/rtsx_usb_sdmmc.c if ((stat & mask) != mask) mask 288 drivers/mmc/host/s3cmci.c u32 mask = readl(host->base + host->sdiimsk); mask 291 drivers/mmc/host/s3cmci.c mask &= S3C2410_SDIIMSK_SDIOIRQ; mask 292 drivers/mmc/host/s3cmci.c writel(mask, host->base + host->sdiimsk); mask 297 drivers/mmc/host/sdhci-esdhc-imx.c static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) mask 302 drivers/mmc/host/sdhci-esdhc-imx.c writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); mask 649 drivers/mmc/host/sdhci-esdhc-imx.c u32 mask; mask 675 drivers/mmc/host/sdhci-esdhc-imx.c mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); mask 677 drivers/mmc/host/sdhci-esdhc-imx.c esdhc_clrset_le(host, mask, new_val, reg); mask 1095 drivers/mmc/host/sdhci-esdhc-imx.c static void esdhc_reset(struct sdhci_host *host, u8 mask) mask 1097 drivers/mmc/host/sdhci-esdhc-imx.c sdhci_reset(host, mask); mask 120 drivers/mmc/host/sdhci-iproc.c u32 mask = 0xffff << word_shift; mask 140 drivers/mmc/host/sdhci-iproc.c newval = (oldval & ~mask) | (val << word_shift); mask 160 drivers/mmc/host/sdhci-iproc.c u32 mask = 0xff << byte_shift; mask 161 drivers/mmc/host/sdhci-iproc.c u32 newval = (oldval & ~mask) | (val << byte_shift); mask 41 drivers/mmc/host/sdhci-of-arasan.c #define HIWORD_UPDATE(val, mask, shift) \ mask 42 drivers/mmc/host/sdhci-of-arasan.c ((val) << (shift) | (mask) << ((shift) + 16)) mask 251 drivers/mmc/host/sdhci-of-arasan.c static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask) mask 257 drivers/mmc/host/sdhci-of-arasan.c sdhci_reset(host, mask); mask 117 drivers/mmc/host/sdhci-of-at91.c static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) mask 119 drivers/mmc/host/sdhci-of-at91.c sdhci_reset(host, mask); mask 733 drivers/mmc/host/sdhci-of-esdhc.c static void esdhc_reset(struct sdhci_host *host, u8 mask) mask 744 drivers/mmc/host/sdhci-of-esdhc.c (mask & SDHCI_RESET_DATA) && mask 752 drivers/mmc/host/sdhci-of-esdhc.c if ((mask & SDHCI_RESET_DATA) && mask 758 drivers/mmc/host/sdhci-of-esdhc.c sdhci_reset(host, mask); mask 764 drivers/mmc/host/sdhci-of-esdhc.c if ((mask & SDHCI_RESET_DATA) && mask 779 drivers/mmc/host/sdhci-of-esdhc.c if ((mask & SDHCI_RESET_ALL) && mask 777 drivers/mmc/host/sdhci-omap.c static void sdhci_omap_reset(struct sdhci_host *host, u8 mask) mask 784 drivers/mmc/host/sdhci-omap.c mask &= ~SDHCI_RESET_DATA; mask 786 drivers/mmc/host/sdhci-omap.c sdhci_reset(host, mask); mask 93 drivers/mmc/host/sdhci-pci-arasan.c static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask) mask 102 drivers/mmc/host/sdhci-pci-arasan.c if (!(val & mask)) mask 129 drivers/mmc/host/sdhci-pci-arasan.c static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask) mask 141 drivers/mmc/host/sdhci-pci-arasan.c else if (val & mask) mask 1610 drivers/mmc/host/sdhci-pci-core.c static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) mask 1621 drivers/mmc/host/sdhci-pci-core.c if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { mask 1650 drivers/mmc/host/sdhci-pci-core.c return sdhci_reset(host, mask); mask 325 drivers/mmc/host/sdhci-pci-gli.c static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) mask 327 drivers/mmc/host/sdhci-pci-gli.c sdhci_reset(host, mask); mask 44 drivers/mmc/host/sdhci-pxav2.c static void pxav2_reset(struct sdhci_host *host, u8 mask) mask 49 drivers/mmc/host/sdhci-pxav2.c sdhci_reset(host, mask); mask 51 drivers/mmc/host/sdhci-pxav2.c if (mask == SDHCI_RESET_ALL) { mask 166 drivers/mmc/host/sdhci-pxav3.c static void pxav3_reset(struct sdhci_host *host, u8 mask) mask 171 drivers/mmc/host/sdhci-pxav3.c sdhci_reset(host, mask); mask 173 drivers/mmc/host/sdhci-pxav3.c if (mask == SDHCI_RESET_ALL) { mask 178 drivers/mmc/host/sdhci-sprd.c sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) mask 184 drivers/mmc/host/sdhci-sprd.c dll_dly_offset |= mask; mask 186 drivers/mmc/host/sdhci-sprd.c dll_dly_offset &= ~mask; mask 218 drivers/mmc/host/sdhci-sprd.c u32 div, val, mask; mask 228 drivers/mmc/host/sdhci-sprd.c mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | mask 230 drivers/mmc/host/sdhci-sprd.c if (mask != (val & mask)) { mask 231 drivers/mmc/host/sdhci-sprd.c val |= mask; mask 353 drivers/mmc/host/sdhci-tegra.c static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) mask 360 drivers/mmc/host/sdhci-tegra.c sdhci_reset(host, mask); mask 362 drivers/mmc/host/sdhci-tegra.c if (!(mask & SDHCI_RESET_ALL)) mask 55 drivers/mmc/host/sdhci-xenon.c u32 mask; mask 59 drivers/mmc/host/sdhci-xenon.c mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id)); mask 61 drivers/mmc/host/sdhci-xenon.c reg |= mask; mask 63 drivers/mmc/host/sdhci-xenon.c reg &= ~mask; mask 161 drivers/mmc/host/sdhci-xenon.c unsigned char sdhc_id, u8 mask) mask 164 drivers/mmc/host/sdhci-xenon.c if (!(mask & SDHCI_RESET_ALL)) mask 177 drivers/mmc/host/sdhci-xenon.c static void xenon_reset(struct sdhci_host *host, u8 mask) mask 182 drivers/mmc/host/sdhci-xenon.c sdhci_reset(host, mask); mask 183 drivers/mmc/host/sdhci-xenon.c xenon_reset_exit(host, priv->sdhc_id, mask); mask 198 drivers/mmc/host/sdhci.c void sdhci_reset(struct sdhci_host *host, u8 mask) mask 202 drivers/mmc/host/sdhci.c sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); mask 204 drivers/mmc/host/sdhci.c if (mask & SDHCI_RESET_ALL) { mask 218 drivers/mmc/host/sdhci.c if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) mask 222 drivers/mmc/host/sdhci.c mmc_hostname(host->mmc), (int)mask); mask 231 drivers/mmc/host/sdhci.c static void sdhci_do_reset(struct sdhci_host *host, u8 mask) mask 240 drivers/mmc/host/sdhci.c host->ops->reset(host, mask); mask 242 drivers/mmc/host/sdhci.c if (mask & SDHCI_RESET_ALL) { mask 564 drivers/mmc/host/sdhci.c u32 mask; mask 570 drivers/mmc/host/sdhci.c mask = SDHCI_DATA_AVAILABLE; mask 572 drivers/mmc/host/sdhci.c mask = SDHCI_SPACE_AVAILABLE; mask 581 drivers/mmc/host/sdhci.c mask = ~0; mask 583 drivers/mmc/host/sdhci.c while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { mask 1347 drivers/mmc/host/sdhci.c u32 mask; mask 1362 drivers/mmc/host/sdhci.c mask = SDHCI_CMD_INHIBIT; mask 1364 drivers/mmc/host/sdhci.c mask |= SDHCI_DATA_INHIBIT; mask 1369 drivers/mmc/host/sdhci.c mask &= ~SDHCI_DATA_INHIBIT; mask 1371 drivers/mmc/host/sdhci.c while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { mask 3046 drivers/mmc/host/sdhci.c u32 intmask, mask, unexpected = 0; mask 3073 drivers/mmc/host/sdhci.c mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | mask 3075 drivers/mmc/host/sdhci.c sdhci_writel(host, mask, SDHCI_INT_STATUS); mask 3223 drivers/mmc/host/sdhci.c u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | mask 3243 drivers/mmc/host/sdhci.c val &= ~mask; mask 3257 drivers/mmc/host/sdhci.c u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE mask 3261 drivers/mmc/host/sdhci.c val &= ~mask; mask 3477 drivers/mmc/host/sdhci.c u32 mask; mask 3499 drivers/mmc/host/sdhci.c mask = intmask & host->cqe_ier; mask 3500 drivers/mmc/host/sdhci.c sdhci_writel(host, mask, SDHCI_INT_STATUS); mask 640 drivers/mmc/host/sdhci.h void (*reset)(struct sdhci_host *host, u8 mask); mask 768 drivers/mmc/host/sdhci.h void sdhci_reset(struct sdhci_host *host, u8 mask); mask 102 drivers/mmc/host/sdhci_am654.c u32 mask, val; mask 115 drivers/mmc/host/sdhci_am654.c mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; mask 118 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); mask 122 drivers/mmc/host/sdhci_am654.c mask = STRBSEL_4BIT_MASK; mask 124 drivers/mmc/host/sdhci_am654.c mask = STRBSEL_8BIT_MASK; mask 126 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, mask 147 drivers/mmc/host/sdhci_am654.c mask = SEL50_MASK | SEL100_MASK; mask 149 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, mask 166 drivers/mmc/host/sdhci_am654.c mask = DLL_TRIM_ICP_MASK; mask 170 drivers/mmc/host/sdhci_am654.c mask |= DR_TY_MASK; mask 172 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); mask 197 drivers/mmc/host/sdhci_am654.c int val, mask; mask 199 drivers/mmc/host/sdhci_am654.c mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; mask 202 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); mask 325 drivers/mmc/host/sdhci_am654.c u32 mask; mask 330 drivers/mmc/host/sdhci_am654.c mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; mask 331 drivers/mmc/host/sdhci_am654.c regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); mask 86 drivers/mmc/host/sdhci_f_sdh30.c static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask) mask 94 drivers/mmc/host/sdhci_f_sdh30.c sdhci_reset(host, mask); mask 390 drivers/mmc/host/sh_mmcif.c dma_cap_mask_t mask; mask 392 drivers/mmc/host/sh_mmcif.c dma_cap_zero(mask); mask 393 drivers/mmc/host/sh_mmcif.c dma_cap_set(DMA_SLAVE, mask); mask 397 drivers/mmc/host/sh_mmcif.c return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); mask 909 drivers/mmc/host/sh_mmcif.c u32 mask = 0; mask 913 drivers/mmc/host/sh_mmcif.c mask = MASK_START_CMD | MASK_MRBSYE; mask 915 drivers/mmc/host/sh_mmcif.c mask = MASK_START_CMD | MASK_MCRSPE; mask 918 drivers/mmc/host/sh_mmcif.c mask |= MASK_MCCSTO; mask 931 drivers/mmc/host/sh_mmcif.c sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); mask 1282 drivers/mmc/host/sh_mmcif.c u32 state, mask; mask 1285 drivers/mmc/host/sh_mmcif.c mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); mask 1287 drivers/mmc/host/sh_mmcif.c sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); mask 1289 drivers/mmc/host/sh_mmcif.c sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); mask 148 drivers/mmc/host/ushc.c static int ushc_hw_set_host_ctrl(struct ushc_data *ushc, u16 mask, u16 val) mask 153 drivers/mmc/host/ushc.c host_ctrl = (ushc->host_ctrl & ~mask) | val; mask 1914 drivers/mtd/chips/jedec_probe.c unsigned long mask; mask 1923 drivers/mtd/chips/jedec_probe.c mask = (1 << (cfi->device_type * 8)) - 1; mask 1928 drivers/mtd/chips/jedec_probe.c } while ((result.x[0] & mask) == CFI_MFR_CONTINUATION); mask 1930 drivers/mtd/chips/jedec_probe.c return result.x[0] & mask; mask 1937 drivers/mtd/chips/jedec_probe.c unsigned long mask; mask 1939 drivers/mtd/chips/jedec_probe.c mask = (1 << (cfi->device_type * 8)) -1; mask 1941 drivers/mtd/chips/jedec_probe.c return result.x[0] & mask; mask 177 drivers/mtd/devices/bcm47xxsflash.c u32 mask = b47s->blocksize - 1; mask 178 drivers/mtd/devices/bcm47xxsflash.c u32 page = (offset & ~mask) << 1; mask 179 drivers/mtd/devices/bcm47xxsflash.c u32 byte = offset & mask; mask 462 drivers/mtd/nand/onenand/omap2.c dma_cap_mask_t mask; mask 514 drivers/mtd/nand/onenand/omap2.c dma_cap_zero(mask); mask 515 drivers/mtd/nand/onenand/omap2.c dma_cap_set(DMA_MEMCPY, mask); mask 517 drivers/mtd/nand/onenand/omap2.c c->dma_chan = dma_request_channel(mask, NULL, NULL); mask 1988 drivers/mtd/nand/raw/atmel/nand-controller.c dma_cap_mask_t mask; mask 1990 drivers/mtd/nand/raw/atmel/nand-controller.c dma_cap_zero(mask); mask 1991 drivers/mtd/nand/raw/atmel/nand-controller.c dma_cap_set(DMA_MEMCPY, mask); mask 1993 drivers/mtd/nand/raw/atmel/nand-controller.c nc->dmac = dma_request_channel(mask, NULL, NULL); mask 359 drivers/mtd/nand/raw/au1550nd.c unsigned long addr, staddr, start, mask, end; mask 367 drivers/mtd/nand/raw/au1550nd.c mask = (staddr << 18) & 0xfffc0000; mask 368 drivers/mtd/nand/raw/au1550nd.c end = (start | (start - 1)) & ~(start ^ mask); mask 625 drivers/mtd/nand/raw/brcmnand/brcmnand.c enum brcmnand_reg reg, u32 mask, unsigned mask 630 drivers/mtd/nand/raw/brcmnand/brcmnand.c tmp &= ~mask; mask 793 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; mask 795 drivers/mtd/nand/raw/brcmnand/brcmnand.c mask <<= NAND_ACC_CONTROL_ECC_SHIFT; mask 799 drivers/mtd/nand/raw/brcmnand/brcmnand.c mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; mask 801 drivers/mtd/nand/raw/brcmnand/brcmnand.c return mask; mask 875 drivers/mtd/nand/raw/brcmnand/brcmnand.c u32 mask, u32 expected_val, mask 887 drivers/mtd/nand/raw/brcmnand/brcmnand.c if ((val & mask) == expected_val) mask 894 drivers/mtd/nand/raw/brcmnand/brcmnand.c expected_val, val & mask); mask 245 drivers/mtd/nand/raw/davinci_nand.c const u32 mask = 0x03ff03ff; mask 247 drivers/mtd/nand/raw/davinci_nand.c code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; mask 248 drivers/mtd/nand/raw/davinci_nand.c code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; mask 249 drivers/mtd/nand/raw/davinci_nand.c code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; mask 250 drivers/mtd/nand/raw/davinci_nand.c code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; mask 977 drivers/mtd/nand/raw/fsmc_nand.c dma_cap_mask_t mask; mask 1064 drivers/mtd/nand/raw/fsmc_nand.c dma_cap_zero(mask); mask 1065 drivers/mtd/nand/raw/fsmc_nand.c dma_cap_set(DMA_MEMCPY, mask); mask 1066 drivers/mtd/nand/raw/fsmc_nand.c host->read_dma_chan = dma_request_channel(mask, filter, NULL); mask 1071 drivers/mtd/nand/raw/fsmc_nand.c host->write_dma_chan = dma_request_channel(mask, filter, NULL); mask 38 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c static int clear_poll_bit(void __iomem *addr, u32 mask) mask 43 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c writel(mask, addr + MXS_CLR_ADDR); mask 52 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c while ((readl(addr) & mask) && --timeout) mask 1299 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c unsigned char mask; mask 1328 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c mask = (0x1 << bit) - 1; mask 1329 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c p[0] = (p[0] & mask) | (from_oob << bit); mask 1331 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c mask = ~0 << bit; mask 1332 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); mask 99 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c static void jz_nand_correct_data(uint8_t *buf, int index, int mask) mask 109 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c mask ^= (data >> offset) & 0x1ff; mask 111 drivers/mtd/nand/raw/ingenic/jz4740_ecc.c data |= (mask << offset); mask 187 drivers/mtd/nand/raw/ingenic/jz4780_bch.c u32 reg, mask, index; mask 215 drivers/mtd/nand/raw/ingenic/jz4780_bch.c mask = (reg & BCH_BHERR_MASK_MASK) >> mask 219 drivers/mtd/nand/raw/ingenic/jz4780_bch.c buf[(index * 2) + 0] ^= mask; mask 220 drivers/mtd/nand/raw/ingenic/jz4780_bch.c buf[(index * 2) + 1] ^= mask >> 8; mask 575 drivers/mtd/nand/raw/lpc32xx_mlc.c dma_cap_mask_t mask; mask 582 drivers/mtd/nand/raw/lpc32xx_mlc.c dma_cap_zero(mask); mask 583 drivers/mtd/nand/raw/lpc32xx_mlc.c dma_cap_set(DMA_SLAVE, mask); mask 584 drivers/mtd/nand/raw/lpc32xx_mlc.c host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, mask 724 drivers/mtd/nand/raw/lpc32xx_slc.c dma_cap_mask_t mask; mask 731 drivers/mtd/nand/raw/lpc32xx_slc.c dma_cap_zero(mask); mask 732 drivers/mtd/nand/raw/lpc32xx_slc.c dma_cap_set(DMA_SLAVE, mask); mask 733 drivers/mtd/nand/raw/lpc32xx_slc.c host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, mask 1919 drivers/mtd/nand/raw/omap2.c dma_cap_mask_t mask; mask 1939 drivers/mtd/nand/raw/omap2.c dma_cap_zero(mask); mask 1940 drivers/mtd/nand/raw/omap2.c dma_cap_set(DMA_SLAVE, mask); mask 294 drivers/mtd/nand/raw/s3c2410.c unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); mask 324 drivers/mtd/nand/raw/s3c2410.c mask = (S3C2410_NFCONF_TACLS(3) | mask 335 drivers/mtd/nand/raw/s3c2410.c mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | mask 351 drivers/mtd/nand/raw/s3c2410.c cfg &= ~mask; mask 168 drivers/mtd/nand/raw/sh_flctl.c dma_cap_mask_t mask; mask 181 drivers/mtd/nand/raw/sh_flctl.c dma_cap_zero(mask); mask 182 drivers/mtd/nand/raw/sh_flctl.c dma_cap_set(DMA_SLAVE, mask); mask 184 drivers/mtd/nand/raw/sh_flctl.c flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter, mask 200 drivers/mtd/nand/raw/sh_flctl.c flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter, mask 194 drivers/mtd/nand/raw/vf610_nfc.c u32 mask, u32 shift, u32 val) mask 197 drivers/mtd/nand/raw/vf610_nfc.c (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); mask 92 drivers/mtd/nand/spi/core.c int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val) mask 101 drivers/mtd/nand/spi/core.c cfg &= ~mask; mask 126 drivers/mtd/nftlcore.c loff_t mask = mtd->writesize - 1; mask 131 drivers/mtd/nftlcore.c ops.ooboffs = offs & mask; mask 136 drivers/mtd/nftlcore.c res = mtd_read_oob(mtd, offs & ~mask, &ops); mask 147 drivers/mtd/nftlcore.c loff_t mask = mtd->writesize - 1; mask 152 drivers/mtd/nftlcore.c ops.ooboffs = offs & mask; mask 157 drivers/mtd/nftlcore.c res = mtd_write_oob(mtd, offs & ~mask, &ops); mask 170 drivers/mtd/nftlcore.c loff_t mask = mtd->writesize - 1; mask 175 drivers/mtd/nftlcore.c ops.ooboffs = offs & mask; mask 181 drivers/mtd/nftlcore.c res = mtd_write_oob(mtd, offs & ~mask, &ops); mask 124 drivers/mtd/parsers/afs.c u_int mask; mask 140 drivers/mtd/parsers/afs.c mask = mtd->size - 1; mask 163 drivers/mtd/parsers/afs.c iis_ptr = fs.image_info_base & mask; mask 164 drivers/mtd/parsers/afs.c img_ptr = fs.image_start & mask; mask 753 drivers/mtd/spi-nor/aspeed-smc.c .mask = SNOR_HWCAPS_READ | mask 245 drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) mask 250 drivers/mtd/spi-nor/cadence-quadspi.c (((clr ? ~val : val) & mask) == mask), mask 1206 drivers/mtd/spi-nor/cadence-quadspi.c dma_cap_mask_t mask; mask 1208 drivers/mtd/spi-nor/cadence-quadspi.c dma_cap_zero(mask); mask 1209 drivers/mtd/spi-nor/cadence-quadspi.c dma_cap_set(DMA_MEMCPY, mask); mask 1211 drivers/mtd/spi-nor/cadence-quadspi.c cqspi->rx_chan = dma_request_chan_by_mask(&mask); mask 1236 drivers/mtd/spi-nor/cadence-quadspi.c hwcaps.mask = ddata->hwcaps_mask; mask 321 drivers/mtd/spi-nor/hisi-sfc.c .mask = SNOR_HWCAPS_READ | mask 871 drivers/mtd/spi-nor/intel-spi.c .mask = SNOR_HWCAPS_READ | mask 426 drivers/mtd/spi-nor/mtk-quadspi.c .mask = SNOR_HWCAPS_READ | mask 273 drivers/mtd/spi-nor/nxp-spifi.c .mask = SNOR_HWCAPS_READ | mask 310 drivers/mtd/spi-nor/nxp-spifi.c hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; mask 313 drivers/mtd/spi-nor/nxp-spifi.c hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; mask 1324 drivers/mtd/spi-nor/spi-nor.c static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) mask 1341 drivers/mtd/spi-nor/spi-nor.c return ((ret & mask) != (status_new & mask)) ? -EIO : 0; mask 1348 drivers/mtd/spi-nor/spi-nor.c u8 mask = SR_BP2 | SR_BP1 | SR_BP0; mask 1349 drivers/mtd/spi-nor/spi-nor.c int shift = ffs(mask) - 1; mask 1352 drivers/mtd/spi-nor/spi-nor.c if (!(sr & mask)) { mask 1357 drivers/mtd/spi-nor/spi-nor.c pow = ((sr & mask) ^ mask) >> shift; mask 1437 drivers/mtd/spi-nor/spi-nor.c u8 mask = SR_BP2 | SR_BP1 | SR_BP0; mask 1438 drivers/mtd/spi-nor/spi-nor.c u8 shift = ffs(mask) - 1, pow, val; mask 1482 drivers/mtd/spi-nor/spi-nor.c val = mask - (pow << shift); mask 1483 drivers/mtd/spi-nor/spi-nor.c if (val & ~mask) mask 1486 drivers/mtd/spi-nor/spi-nor.c if (!(val & mask)) mask 1489 drivers/mtd/spi-nor/spi-nor.c status_new = (status_old & ~mask & ~SR_TB) | val; mask 1502 drivers/mtd/spi-nor/spi-nor.c if ((status_new & mask) < (status_old & mask)) mask 1505 drivers/mtd/spi-nor/spi-nor.c return write_sr_and_check(nor, status_new, mask); mask 1517 drivers/mtd/spi-nor/spi-nor.c u8 mask = SR_BP2 | SR_BP1 | SR_BP0; mask 1518 drivers/mtd/spi-nor/spi-nor.c u8 shift = ffs(mask) - 1, pow, val; mask 1565 drivers/mtd/spi-nor/spi-nor.c val = mask - (pow << shift); mask 1567 drivers/mtd/spi-nor/spi-nor.c if (val & ~mask) mask 1571 drivers/mtd/spi-nor/spi-nor.c status_new = (status_old & ~mask & ~SR_TB) | val; mask 1585 drivers/mtd/spi-nor/spi-nor.c if ((status_new & mask) > (status_old & mask)) mask 1588 drivers/mtd/spi-nor/spi-nor.c return write_sr_and_check(nor, status_new, mask); mask 1957 drivers/mtd/spi-nor/spi-nor.c u8 mask = SR_BP2 | SR_BP1 | SR_BP0; mask 1967 drivers/mtd/spi-nor/spi-nor.c ret = write_sr(nor, ret & ~mask); mask 1995 drivers/mtd/spi-nor/spi-nor.c u8 mask = SR_BP2 | SR_BP1 | SR_BP0; mask 2019 drivers/mtd/spi-nor/spi-nor.c sr_cr[0] = ret & ~mask; mask 3424 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask &= ~rd->hwcaps; mask 3428 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= rd->hwcaps; mask 3943 drivers/mtd/spi-nor/spi-nor.c if ((params->hwcaps.mask & read->hwcaps) && mask 3994 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask &= ~discard_hwcaps; mask 3995 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= (read_hwcaps | pp_hwcaps); mask 4326 drivers/mtd/spi-nor/spi-nor.c shared_mask = hwcaps->mask & params->hwcaps.mask; mask 4479 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; mask 4483 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; mask 4487 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_READ; mask 4492 drivers/mtd/spi-nor/spi-nor.c if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST) mask 4498 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; mask 4505 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; mask 4512 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8; mask 4519 drivers/mtd/spi-nor/spi-nor.c params->hwcaps.mask |= SNOR_HWCAPS_PP; mask 4990 drivers/mtd/spi-nor/spi-nor.c const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL }; mask 78 drivers/mux/mmio.c u32 reg, mask; mask 85 drivers/mux/mmio.c 2 * i + 1, &mask); mask 93 drivers/mux/mmio.c field.msb = fls(mask) - 1; mask 94 drivers/mux/mmio.c field.lsb = ffs(mask) - 1; mask 96 drivers/mux/mmio.c if (mask != GENMASK(field.msb, field.lsb)) { mask 98 drivers/mux/mmio.c i, mask); mask 50 drivers/net/arcnet/arc-rimi.c static void arcrimi_setmask(struct net_device *dev, int mask); mask 263 drivers/net/arcnet/arc-rimi.c static void arcrimi_setmask(struct net_device *dev, int mask) mask 268 drivers/net/arcnet/arc-rimi.c arcnet_writeb(mask, ioaddr, COM9026_REG_W_INTMASK); mask 316 drivers/net/arcnet/arcdevice.h void (*intmask)(struct net_device *dev, int mask); mask 53 drivers/net/arcnet/com20020.c static void com20020_setmask(struct net_device *dev, int mask); mask 332 drivers/net/arcnet/com20020.c static void com20020_setmask(struct net_device *dev, int mask) mask 336 drivers/net/arcnet/com20020.c arc_printk(D_DURING, dev, "Setting mask to %x at %x\n", mask, ioaddr); mask 337 drivers/net/arcnet/com20020.c arcnet_outb(mask, ioaddr, COM20020_REG_W_INTMASK); mask 50 drivers/net/arcnet/com90io.c static void com90io_setmask(struct net_device *dev, int mask); mask 325 drivers/net/arcnet/com90io.c static void com90io_setmask(struct net_device *dev, int mask) mask 329 drivers/net/arcnet/com90io.c arcnet_outb(mask, ioaddr, COM9026_REG_W_INTMASK); mask 61 drivers/net/arcnet/com90xx.c static void com90xx_setmask(struct net_device *dev, int mask); mask 575 drivers/net/arcnet/com90xx.c static void com90xx_setmask(struct net_device *dev, int mask) mask 579 drivers/net/arcnet/com90xx.c arcnet_outb(mask, ioaddr, COM9026_REG_W_INTMASK); mask 1058 drivers/net/bonding/bond_main.c netdev_features_t mask; mask 1061 drivers/net/bonding/bond_main.c mask = features; mask 1069 drivers/net/bonding/bond_main.c mask); mask 1071 drivers/net/bonding/bond_main.c features = netdev_add_tso_features(features, mask); mask 517 drivers/net/can/at91_can.c u32 mask = get_mb_rx_low_mask(priv); mask 518 drivers/net/can/at91_can.c at91_write(priv, AT91_TCR, mask); mask 531 drivers/net/can/at91_can.c u32 mask = 1 << mb; mask 532 drivers/net/can/at91_can.c at91_write(priv, AT91_TCR, mask); mask 448 drivers/net/can/c_can/c_can.c u32 obj, u32 mask, u32 id, u32 mcont) mask 452 drivers/net/can/c_can/c_can.c mask |= BIT(29); mask 453 drivers/net/can/c_can/c_can.c priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); mask 75 drivers/net/can/c_can/c_can_platform.c u32 mask, u32 val) mask 82 drivers/net/can/c_can/c_can_platform.c val &= mask; mask 92 drivers/net/can/c_can/c_can_platform.c } while ((ctrl & mask) != val); mask 99 drivers/net/can/c_can/c_can_platform.c u32 mask; mask 103 drivers/net/can/c_can/c_can_platform.c mask = 1 << raminit->bits.start | 1 << raminit->bits.done; mask 113 drivers/net/can/c_can/c_can_platform.c ctrl &= ~mask; /* START = 0, DONE = 0 */ mask 114 drivers/net/can/c_can/c_can_platform.c regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); mask 126 drivers/net/can/c_can/c_can_platform.c regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); mask 133 drivers/net/can/c_can/c_can_platform.c mask, ctrl); mask 137 drivers/net/can/c_can/c_can_platform.c c_can_hw_raminit_wait_syscon(priv, mask, ctrl); mask 170 drivers/net/can/c_can/c_can_platform.c static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask) mask 172 drivers/net/can/c_can/c_can_platform.c while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask) mask 907 drivers/net/can/dev.c is_can_fd = cm->flags & cm->mask & CAN_CTRLMODE_FD; mask 982 drivers/net/can/dev.c maskedflags = cm->flags & cm->mask; mask 985 drivers/net/can/dev.c if (cm->mask & ~(priv->ctrlmode_supported | ctrlstatic)) mask 997 drivers/net/can/dev.c priv->ctrlmode &= ~cm->mask; mask 339 drivers/net/can/grcan.c static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask) mask 341 drivers/net/can/grcan.c grcan_write_reg(reg, grcan_read_reg(reg) & ~mask); mask 344 drivers/net/can/grcan.c static inline void grcan_set_bits(u32 __iomem *reg, u32 mask) mask 346 drivers/net/can/grcan.c grcan_write_reg(reg, grcan_read_reg(reg) | mask); mask 349 drivers/net/can/grcan.c static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask) mask 351 drivers/net/can/grcan.c return grcan_read_reg(reg) & mask; mask 354 drivers/net/can/grcan.c static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask) mask 358 drivers/net/can/grcan.c grcan_write_reg(reg, (old & ~mask) | (value & mask)); mask 691 drivers/net/can/ifi_canfd/ifi_canfd.c const u32 mask, const u32 ident) mask 695 drivers/net/can/ifi_canfd/ifi_canfd.c writel(mask, priv->base + IFI_CANFD_FILTER_MASK(id)); mask 442 drivers/net/can/mscan/mscan.c u8 mask = entry->mask; mask 444 drivers/net/can/mscan/mscan.c if (!(cantflg & mask)) mask 447 drivers/net/can/mscan/mscan.c out_8(®s->cantbsel, mask); mask 451 drivers/net/can/mscan/mscan.c priv->tx_active &= ~mask; mask 697 drivers/net/can/mscan/mscan.c priv->tx_queue[i].mask = 1 << i; mask 266 drivers/net/can/mscan/mscan.h u8 mask; mask 192 drivers/net/can/pch_can.c static inline void pch_can_bit_set(void __iomem *addr, u32 mask) mask 194 drivers/net/can/pch_can.c iowrite32(ioread32(addr) | mask, addr); mask 197 drivers/net/can/pch_can.c static inline void pch_can_bit_clear(void __iomem *addr, u32 mask) mask 199 drivers/net/can/pch_can.c iowrite32(ioread32(addr) & ~mask, addr); mask 436 drivers/net/can/pch_can.c static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) mask 439 drivers/net/can/pch_can.c if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { mask 451 drivers/net/can/pch_can.c pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask); mask 452 drivers/net/can/pch_can.c } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) { mask 468 drivers/net/can/pch_can.c pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask); mask 158 drivers/net/can/peak_canfd/peak_canfd.c static int pucan_set_std_filter(struct peak_canfd_priv *priv, u8 row, u32 mask) mask 177 drivers/net/can/peak_canfd/peak_canfd.c cmd->mask = cpu_to_le32(mask); mask 558 drivers/net/can/rcar/rcar_canfd.c static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg) mask 562 drivers/net/can/rcar/rcar_canfd.c data &= ~mask; mask 563 drivers/net/can/rcar/rcar_canfd.c data |= (val & mask); mask 588 drivers/net/can/rcar/rcar_canfd.c u32 mask, u32 val) mask 590 drivers/net/can/rcar/rcar_canfd.c rcar_canfd_update(mask, val, base + (reg)); mask 155 drivers/net/can/sja1000/peak_pcmcia.c static void pcan_set_leds(struct pcan_pccard *card, u8 mask, u8 state); mask 325 drivers/net/can/spi/mcp251x.c u8 mask, u8 val) mask 331 drivers/net/can/spi/mcp251x.c priv->spi_tx_buf[2] = mask; mask 149 drivers/net/can/usb/esd_usb2.c __le32 mask[ESD_MAX_ID_SEGMENT + 1]; mask 635 drivers/net/can/usb/esd_usb2.c msg->msg.filter.mask[i] = cpu_to_le32(0xffffffff); mask 637 drivers/net/can/usb/esd_usb2.c msg->msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001); mask 846 drivers/net/can/usb/esd_usb2.c msg->msg.filter.mask[i] = 0; mask 163 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c __le32 mask; mask 705 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c u32 mask = 0; mask 740 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c mask = le32_to_cpu(cmd->cap_res.mask); mask 749 drivers/net/can/usb/kvaser_usb/kvaser_usb_hydra.c if (BIT(i) & (value & mask)) { mask 313 drivers/net/can/usb/peak_usb/pcan_usb_fd.c u32 mask) mask 332 drivers/net/can/usb/peak_usb/pcan_usb_fd.c cmd->mask = cpu_to_le32(mask); mask 1134 drivers/net/can/xilinx_can.c u32 fsr, mask; mask 1145 drivers/net/can/xilinx_can.c mask = XCAN_2_FSR_FL_MASK; mask 1147 drivers/net/can/xilinx_can.c mask = XCAN_FSR_FL_MASK; mask 1149 drivers/net/can/xilinx_can.c if (!(fsr & mask)) mask 459 drivers/net/dsa/b53/b53_common.c static int b53_flush_arl(struct b53_device *dev, u8 mask) mask 464 drivers/net/dsa/b53/b53_common.c FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask); mask 1172 drivers/net/dsa/b53/b53_common.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 1175 drivers/net/dsa/b53/b53_common.c dev->ops->serdes_phylink_validate(dev, port, mask, state); mask 1178 drivers/net/dsa/b53/b53_common.c phylink_set(mask, Autoneg); mask 1179 drivers/net/dsa/b53/b53_common.c phylink_set_port_modes(mask); mask 1180 drivers/net/dsa/b53/b53_common.c phylink_set(mask, Pause); mask 1181 drivers/net/dsa/b53/b53_common.c phylink_set(mask, Asym_Pause); mask 1190 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 1000baseT_Full); mask 1191 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 1000baseT_Half); mask 1195 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 10baseT_Half); mask 1196 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 10baseT_Full); mask 1197 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 100baseT_Half); mask 1198 drivers/net/dsa/b53/b53_common.c phylink_set(mask, 100baseT_Full); mask 1201 drivers/net/dsa/b53/b53_common.c bitmap_and(supported, supported, mask, mask 1203 drivers/net/dsa/b53/b53_common.c bitmap_and(state->advertising, state->advertising, mask, mask 492 drivers/net/dsa/bcm_sf2.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 509 drivers/net/dsa/bcm_sf2.c phylink_set(mask, Autoneg); mask 510 drivers/net/dsa/bcm_sf2.c phylink_set_port_modes(mask); mask 511 drivers/net/dsa/bcm_sf2.c phylink_set(mask, Pause); mask 512 drivers/net/dsa/bcm_sf2.c phylink_set(mask, Asym_Pause); mask 519 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 1000baseT_Full); mask 520 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 1000baseT_Half); mask 523 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 10baseT_Half); mask 524 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 10baseT_Full); mask 525 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 100baseT_Half); mask 526 drivers/net/dsa/bcm_sf2.c phylink_set(mask, 100baseT_Full); mask 528 drivers/net/dsa/bcm_sf2.c bitmap_and(supported, supported, mask, mask 530 drivers/net/dsa/bcm_sf2.c bitmap_and(state->advertising, state->advertising, mask, mask 161 drivers/net/dsa/bcm_sf2.h u32 mask) \ mask 163 drivers/net/dsa/bcm_sf2.h priv->irq##which##_mask &= ~(mask); \ mask 164 drivers/net/dsa/bcm_sf2.h intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ mask 167 drivers/net/dsa/bcm_sf2.h u32 mask) \ mask 169 drivers/net/dsa/bcm_sf2.h intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ mask 170 drivers/net/dsa/bcm_sf2.h priv->irq##which##_mask |= (mask); \ mask 265 drivers/net/dsa/bcm_sf2_cfp.c bool mask) mask 274 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 285 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 298 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 311 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 326 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 435 drivers/net/dsa/bcm_sf2_cfp.c bcm_sf2_cfp_slice_ipv4(priv, ipv4.mask, ports.mask, SLICE_NUM_MASK, true); mask 472 drivers/net/dsa/bcm_sf2_cfp.c bool mask) mask 482 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 495 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 508 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 521 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 535 drivers/net/dsa/bcm_sf2_cfp.c if (mask) mask 719 drivers/net/dsa/bcm_sf2_cfp.c bcm_sf2_cfp_slice_ipv6(priv, ipv6.mask->src.in6_u.u6_addr32, mask 720 drivers/net/dsa/bcm_sf2_cfp.c ports.mask->src, SLICE_NUM_MASK, true); mask 779 drivers/net/dsa/bcm_sf2_cfp.c bcm_sf2_cfp_slice_ipv6(priv, ipv6.mask->dst.in6_u.u6_addr32, mask 243 drivers/net/dsa/lan9303-core.c static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask) mask 257 drivers/net/dsa/lan9303-core.c if (!(reg & mask)) mask 441 drivers/net/dsa/lan9303-core.c u32 val, u32 mask) mask 450 drivers/net/dsa/lan9303-core.c reg = (reg & ~mask) | val; mask 532 drivers/net/dsa/lan9303-core.c static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask) mask 540 drivers/net/dsa/lan9303-core.c if (!(reg & mask)) mask 264 drivers/net/dsa/lantiq_gswip.c u16 mask; mask 534 drivers/net/dsa/lantiq_gswip.c tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); mask 576 drivers/net/dsa/lantiq_gswip.c gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); mask 1398 drivers/net/dsa/lantiq_gswip.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 1427 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, Autoneg); mask 1428 drivers/net/dsa/lantiq_gswip.c phylink_set_port_modes(mask); mask 1429 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, Pause); mask 1430 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, Asym_Pause); mask 1437 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 1000baseT_Full); mask 1438 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 1000baseT_Half); mask 1441 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 10baseT_Half); mask 1442 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 10baseT_Full); mask 1443 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 100baseT_Half); mask 1444 drivers/net/dsa/lantiq_gswip.c phylink_set(mask, 100baseT_Full); mask 1446 drivers/net/dsa/lantiq_gswip.c bitmap_and(supported, supported, mask, mask 1448 drivers/net/dsa/lantiq_gswip.c bitmap_and(state->advertising, state->advertising, mask, mask 144 drivers/net/dsa/mt7530.c core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) mask 152 drivers/net/dsa/mt7530.c val &= ~mask; mask 262 drivers/net/dsa/mt7530.c u32 mask, u32 set) mask 270 drivers/net/dsa/mt7530.c val &= ~mask; mask 496 drivers/net/dsa/mt7530.c u32 mask = PMCR_TX_EN | PMCR_RX_EN | PMCR_FORCE_LNK; mask 499 drivers/net/dsa/mt7530.c mt7530_set(priv, MT7530_PMCR_P(port), mask); mask 501 drivers/net/dsa/mt7530.c mt7530_clear(priv, MT7530_PMCR_P(port), mask); mask 1415 drivers/net/dsa/mt7530.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 1447 drivers/net/dsa/mt7530.c phylink_set_port_modes(mask); mask 1448 drivers/net/dsa/mt7530.c phylink_set(mask, Autoneg); mask 1451 drivers/net/dsa/mt7530.c phylink_set(mask, 1000baseT_Full); mask 1453 drivers/net/dsa/mt7530.c phylink_set(mask, 10baseT_Half); mask 1454 drivers/net/dsa/mt7530.c phylink_set(mask, 10baseT_Full); mask 1455 drivers/net/dsa/mt7530.c phylink_set(mask, 100baseT_Half); mask 1456 drivers/net/dsa/mt7530.c phylink_set(mask, 100baseT_Full); mask 1459 drivers/net/dsa/mt7530.c phylink_set(mask, 1000baseT_Half); mask 1460 drivers/net/dsa/mt7530.c phylink_set(mask, 1000baseT_Full); mask 1462 drivers/net/dsa/mt7530.c phylink_set(mask, 1000baseX_Full); mask 1466 drivers/net/dsa/mt7530.c phylink_set(mask, Pause); mask 1467 drivers/net/dsa/mt7530.c phylink_set(mask, Asym_Pause); mask 1469 drivers/net/dsa/mt7530.c linkmode_and(supported, supported, mask); mask 1470 drivers/net/dsa/mt7530.c linkmode_and(state->advertising, state->advertising, mask); mask 85 drivers/net/dsa/mv88e6xxx/chip.c u16 mask, u16 val) mask 97 drivers/net/dsa/mv88e6xxx/chip.c if ((data & mask) == val) mask 201 drivers/net/dsa/mv88e6xxx/chip.c u16 mask = GENMASK(chip->g1_irq.nirqs, 0); mask 209 drivers/net/dsa/mv88e6xxx/chip.c reg &= ~mask; mask 210 drivers/net/dsa/mv88e6xxx/chip.c reg |= (~chip->g1_irq.masked & mask); mask 250 drivers/net/dsa/mv88e6xxx/chip.c u16 mask; mask 252 drivers/net/dsa/mv88e6xxx/chip.c mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); mask 253 drivers/net/dsa/mv88e6xxx/chip.c mask &= ~GENMASK(chip->g1_irq.nirqs, 0); mask 254 drivers/net/dsa/mv88e6xxx/chip.c mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); mask 280 drivers/net/dsa/mv88e6xxx/chip.c u16 reg, mask; mask 295 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); mask 299 drivers/net/dsa/mv88e6xxx/chip.c mask &= ~GENMASK(chip->g1_irq.nirqs, 0); mask 301 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); mask 313 drivers/net/dsa/mv88e6xxx/chip.c mask &= ~GENMASK(chip->g1_irq.nirqs, 0); mask 314 drivers/net/dsa/mv88e6xxx/chip.c mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); mask 479 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 484 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 10baseT_Half); mask 485 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 10baseT_Full); mask 486 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 100baseT_Half); mask 487 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 100baseT_Full); mask 492 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 498 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseT_Full); mask 499 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseX_Full); mask 501 drivers/net/dsa/mv88e6xxx/chip.c mv88e6065_phylink_validate(chip, port, mask, state); mask 505 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 509 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 2500baseX_Full); mask 512 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseT_Full); mask 513 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseX_Full); mask 515 drivers/net/dsa/mv88e6xxx/chip.c mv88e6065_phylink_validate(chip, port, mask, state); mask 519 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 523 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseT_Full); mask 524 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseX_Full); mask 526 drivers/net/dsa/mv88e6xxx/chip.c mv88e6065_phylink_validate(chip, port, mask, state); mask 530 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 534 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 2500baseX_Full); mask 535 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 2500baseT_Full); mask 539 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseT_Full); mask 540 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 1000baseX_Full); mask 542 drivers/net/dsa/mv88e6xxx/chip.c mv88e6065_phylink_validate(chip, port, mask, state); mask 546 drivers/net/dsa/mv88e6xxx/chip.c unsigned long *mask, mask 550 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 10000baseT_Full); mask 551 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, 10000baseKR_Full); mask 554 drivers/net/dsa/mv88e6xxx/chip.c mv88e6390_phylink_validate(chip, port, mask, state); mask 561 drivers/net/dsa/mv88e6xxx/chip.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 565 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, Autoneg); mask 566 drivers/net/dsa/mv88e6xxx/chip.c phylink_set(mask, Pause); mask 567 drivers/net/dsa/mv88e6xxx/chip.c phylink_set_port_modes(mask); mask 570 drivers/net/dsa/mv88e6xxx/chip.c chip->info->ops->phylink_validate(chip, port, mask, state); mask 572 drivers/net/dsa/mv88e6xxx/chip.c bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); mask 573 drivers/net/dsa/mv88e6xxx/chip.c bitmap_and(state->advertising, state->advertising, mask, mask 520 drivers/net/dsa/mv88e6xxx/chip.h unsigned long *mask, mask 635 drivers/net/dsa/mv88e6xxx/chip.h u16 mask, u16 val); mask 38 drivers/net/dsa/mv88e6xxx/global1.c u16 mask, u16 val) mask 41 drivers/net/dsa/mv88e6xxx/global1.c mask, val); mask 377 drivers/net/dsa/mv88e6xxx/global1.c static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, mask 387 drivers/net/dsa/mv88e6xxx/global1.c reg &= ~mask; mask 388 drivers/net/dsa/mv88e6xxx/global1.c reg |= val & mask; mask 395 drivers/net/dsa/mv88e6xxx/global1.c const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; mask 397 drivers/net/dsa/mv88e6xxx/global1.c return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); mask 273 drivers/net/dsa/mv88e6xxx/global1.h u16 mask, u16 val); mask 290 drivers/net/dsa/mv88e6xxx/global1_atu.c unsigned long mask; mask 296 drivers/net/dsa/mv88e6xxx/global1_atu.c mask = chip->info->atu_move_port_mask; mask 297 drivers/net/dsa/mv88e6xxx/global1_atu.c shift = bitmap_weight(&mask, 16); mask 300 drivers/net/dsa/mv88e6xxx/global1_atu.c entry.portvec = from_port & mask; mask 301 drivers/net/dsa/mv88e6xxx/global1_atu.c entry.portvec |= (to_port & mask) << shift; mask 46 drivers/net/dsa/mv88e6xxx/global2.c static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask) mask 48 drivers/net/dsa/mv88e6xxx/global2.c return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask); mask 130 drivers/net/dsa/mv88e6xxx/global2.c bool hash, u16 mask) mask 132 drivers/net/dsa/mv88e6xxx/global2.c u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip)); mask 55 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 mask = (1 << (offset & 0x7)); mask 63 drivers/net/dsa/mv88e6xxx/global2_scratch.c *set = !!(mask & val); mask 81 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 mask = (1 << (offset & 0x7)); mask 90 drivers/net/dsa/mv88e6xxx/global2_scratch.c val |= mask; mask 92 drivers/net/dsa/mv88e6xxx/global2_scratch.c val &= ~mask; mask 128 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 mask = (1 << (pin & 0x7)); mask 135 drivers/net/dsa/mv88e6xxx/global2_scratch.c chip->gpio_data[offset] |= mask; mask 137 drivers/net/dsa/mv88e6xxx/global2_scratch.c chip->gpio_data[offset] &= ~mask; mask 193 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 mask = (0x7 << offset); mask 201 drivers/net/dsa/mv88e6xxx/global2_scratch.c *func = (val & mask) >> offset; mask 217 drivers/net/dsa/mv88e6xxx/global2_scratch.c u8 mask = (0x7 << offset); mask 225 drivers/net/dsa/mv88e6xxx/global2_scratch.c val = (val & ~mask) | ((func & mask) << offset); mask 1001 drivers/net/dsa/mv88e6xxx/port.c const u16 mask = mv88e6xxx_port_mask(chip); mask 1009 drivers/net/dsa/mv88e6xxx/port.c reg &= ~mask; mask 1010 drivers/net/dsa/mv88e6xxx/port.c reg |= map & mask; mask 1351 drivers/net/dsa/mv88e6xxx/port.c u16 reg, mask, val; mask 1358 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_DA_MASK; mask 1362 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_SA_MASK; mask 1366 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_VTU_MASK; mask 1370 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK; mask 1374 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK; mask 1378 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK; mask 1382 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK; mask 1386 drivers/net/dsa/mv88e6xxx/port.c mask = MV88E6XXX_PORT_POLICY_CTL_UDP_MASK; mask 1413 drivers/net/dsa/mv88e6xxx/port.c reg &= ~mask; mask 1414 drivers/net/dsa/mv88e6xxx/port.c reg |= (val << shift) & mask; mask 456 drivers/net/dsa/mv88e6xxx/ptp.c chip->tstamp_cc.mask = CYCLECOUNTER_MASK(32); mask 175 drivers/net/dsa/qca8k.c qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) mask 186 drivers/net/dsa/qca8k.c ret &= ~mask; mask 262 drivers/net/dsa/qca8k.c qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) mask 271 drivers/net/dsa/qca8k.c int busy = val & mask; mask 473 drivers/net/dsa/qca8k.c u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; mask 477 drivers/net/dsa/qca8k.c mask |= QCA8K_PORT_STATUS_LINK_AUTO; mask 480 drivers/net/dsa/qca8k.c qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask); mask 482 drivers/net/dsa/qca8k.c qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask); mask 643 drivers/net/dsa/qca8k.c u32 mask; mask 674 drivers/net/dsa/qca8k.c mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW | mask 676 drivers/net/dsa/qca8k.c qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask); mask 269 drivers/net/dsa/rtl8366.c u32 mask; mask 275 drivers/net/dsa/rtl8366.c mask = GENMASK(smi->num_ports - 1, 0); mask 280 drivers/net/dsa/rtl8366.c mask = BIT(port) | BIT(smi->cpu_port); mask 288 drivers/net/dsa/rtl8366.c (port + 1), port, mask); mask 289 drivers/net/dsa/rtl8366.c ret = rtl8366_set_vlan(smi, (port + 1), mask, mask, 0); mask 846 drivers/net/dsa/sja1105/sja1105_main.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 865 drivers/net/dsa/sja1105/sja1105_main.c phylink_set(mask, Autoneg); mask 866 drivers/net/dsa/sja1105/sja1105_main.c phylink_set(mask, MII); mask 867 drivers/net/dsa/sja1105/sja1105_main.c phylink_set(mask, 10baseT_Full); mask 868 drivers/net/dsa/sja1105/sja1105_main.c phylink_set(mask, 100baseT_Full); mask 870 drivers/net/dsa/sja1105/sja1105_main.c phylink_set(mask, 1000baseT_Full); mask 872 drivers/net/dsa/sja1105/sja1105_main.c bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); mask 873 drivers/net/dsa/sja1105/sja1105_main.c bitmap_and(state->advertising, state->advertising, mask, mask 367 drivers/net/dsa/sja1105/sja1105_ptp.c .mask = CYCLECOUNTER_MASK(64), mask 389 drivers/net/dsa/vitesse-vsc73xx-core.c u8 reg, u32 mask, u32 val) mask 398 drivers/net/dsa/vitesse-vsc73xx-core.c tmp = orig & ~mask; mask 399 drivers/net/dsa/vitesse-vsc73xx-core.c tmp |= val & mask; mask 338 drivers/net/ethernet/3com/3c515.c mask:8, /* The transceiver-present bit in Wn3_Config. */ mask 731 drivers/net/ethernet/3com/3c515.c while (!(vp->available_media & media_tbl[dev->if_port].mask)) mask 925 drivers/net/ethernet/3com/3c515.c while (!(vp->available_media & media_tbl[dev->if_port].mask)); mask 723 drivers/net/ethernet/3com/3c59x.c mask:8, /* The transceiver-present bit in Wn3_Config.*/ mask 1581 drivers/net/ethernet/3com/3c59x.c while (! (vp->available_media & media_tbl[dev->if_port].mask)) mask 1840 drivers/net/ethernet/3com/3c59x.c } while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); mask 119 drivers/net/ethernet/8390/etherh.c static inline void etherh_set_ctrl(struct etherh_priv *eh, unsigned char mask) mask 121 drivers/net/ethernet/8390/etherh.c unsigned char ctrl = eh->ctrl | mask; mask 126 drivers/net/ethernet/8390/etherh.c static inline void etherh_clr_ctrl(struct etherh_priv *eh, unsigned char mask) mask 128 drivers/net/ethernet/8390/etherh.c unsigned char ctrl = eh->ctrl & ~mask; mask 699 drivers/net/ethernet/8390/pcnet_cs.c int bits, mask = inb(addr) & MDIO_MASK; mask 701 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | MDIO_DATA_WRITE1, addr); mask 702 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, addr); mask 709 drivers/net/ethernet/8390/pcnet_cs.c int i, retval = 0, mask = inb(addr) & MDIO_MASK; mask 714 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | dat, addr); mask 715 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | dat | MDIO_SHIFT_CLK, addr); mask 718 drivers/net/ethernet/8390/pcnet_cs.c outb(mask, addr); mask 720 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | MDIO_SHIFT_CLK, addr); mask 728 drivers/net/ethernet/8390/pcnet_cs.c int i, mask = inb(addr) & MDIO_MASK; mask 733 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | dat, addr); mask 734 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | dat | MDIO_SHIFT_CLK, addr); mask 737 drivers/net/ethernet/8390/pcnet_cs.c outb(mask, addr); mask 738 drivers/net/ethernet/8390/pcnet_cs.c outb(mask | MDIO_SHIFT_CLK, addr); mask 974 drivers/net/ethernet/aeroflex/greth.c u32 mask, ctrl; mask 996 drivers/net/ethernet/aeroflex/greth.c mask = GRETH_INT_RX | GRETH_INT_RE | mask 1000 drivers/net/ethernet/aeroflex/greth.c mask = GRETH_INT_RX | GRETH_INT_RE; mask 1003 drivers/net/ethernet/aeroflex/greth.c if (GRETH_REGLOAD(greth->regs->status) & mask) { mask 1306 drivers/net/ethernet/agere/et131x.c u16 mask = 1 << bitnum; mask 1310 drivers/net/ethernet/agere/et131x.c *value = (reg & mask) >> bitnum; mask 1706 drivers/net/ethernet/agere/et131x.c u32 mask; mask 1709 drivers/net/ethernet/agere/et131x.c mask = INT_MASK_ENABLE; mask 1711 drivers/net/ethernet/agere/et131x.c mask = INT_MASK_ENABLE_NO_FLOW; mask 1713 drivers/net/ethernet/agere/et131x.c writel(mask, &adapter->regs->global.int_mask); mask 209 drivers/net/ethernet/alacritech/slicoss.c u64 mask = *mcmask; mask 218 drivers/net/ethernet/alacritech/slicoss.c mask |= (u64)1 << crc; mask 219 drivers/net/ethernet/alacritech/slicoss.c *mcmask = mask; mask 2605 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int mask; mask 2640 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask = 0; mask 2644 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask |= (1 << prio); mask 2651 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask |= (1 << prio); mask 2655 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); mask 2715 drivers/net/ethernet/amd/xgbe/xgbe-dev.c unsigned int mask, reg, reg_val; mask 2734 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask = 0; mask 2737 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask |= (1 << prio); mask 2739 drivers/net/ethernet/amd/xgbe/xgbe-dev.c mask &= 0xff; mask 2742 drivers/net/ethernet/amd/xgbe/xgbe-dev.c i, mask); mask 2747 drivers/net/ethernet/amd/xgbe/xgbe-dev.c reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3)); mask 262 drivers/net/ethernet/amd/xgbe/xgbe-ptp.c cc->mask = CLOCKSOURCE_MASK(64); mask 62 drivers/net/ethernet/apm/xgene-v2/mac.h u32 mask = GENMASK(pos + len, pos); mask 64 drivers/net/ethernet/apm/xgene-v2/mac.h *var &= ~mask; mask 65 drivers/net/ethernet/apm/xgene-v2/mac.h *var |= ((val << pos) & mask); mask 70 drivers/net/ethernet/apm/xgene-v2/mac.h u32 mask = GENMASK(pos + len, pos); mask 72 drivers/net/ethernet/apm/xgene-v2/mac.h return (var & mask) >> pos; mask 100 drivers/net/ethernet/apm/xgene-v2/mdio.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 142 drivers/net/ethernet/apm/xgene-v2/mdio.c mask); mask 143 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mask); mask 144 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_set_bit(ETHTOOL_LINK_MODE_AUI_BIT, mask); mask 145 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); mask 146 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); mask 147 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_set_bit(ETHTOOL_LINK_MODE_BNC_BIT, mask); mask 149 drivers/net/ethernet/apm/xgene-v2/mdio.c linkmode_andnot(phydev->supported, phydev->supported, mask); mask 101 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c SET_VAL(CLE_BR_MASK, br->mask); mask 218 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0x0 mask 229 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 254 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0x00ff mask 266 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0x00ff mask 277 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 302 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 314 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 326 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 338 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 350 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 362 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 387 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 399 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 411 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 423 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 435 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 447 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 472 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 484 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 496 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 508 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 520 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 532 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 557 drivers/net/ethernet/apm/xgene/xgene_enet_cle.c .mask = 0xffff mask 207 drivers/net/ethernet/apm/xgene/xgene_enet_cle.h u16 mask; mask 15 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c u32 mask; mask 23 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c .mask = m \ mask 221 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c u32 mask, tmp; mask 226 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c if (gstrings_extd_stats[i].mask) { mask 227 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c mask = GENMASK(gstrings_extd_stats[i].mask - 1, 0); mask 228 drivers/net/ethernet/apm/xgene/xgene_enet_ethtool.c pdata->extd_stats[i] += (tmp & mask); mask 23 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h u32 mask = GENMASK(end, start); mask 25 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h *dst &= ~mask; mask 26 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h *dst |= (val << start) & mask; mask 40 drivers/net/ethernet/apm/xgene/xgene_enet_main.c u16 hw_len, mask; mask 47 drivers/net/ethernet/apm/xgene/xgene_enet_main.c mask = GENMASK(13, 0); mask 48 drivers/net/ethernet/apm/xgene/xgene_enet_main.c return (hw_len & mask) ? (hw_len & mask) : SIZE_16K; mask 50 drivers/net/ethernet/apm/xgene/xgene_enet_main.c mask = GENMASK(11, 0); mask 51 drivers/net/ethernet/apm/xgene/xgene_enet_main.c return (hw_len & mask) ? (hw_len & mask) : SIZE_4K; mask 53 drivers/net/ethernet/apm/xgene/xgene_enet_main.c mask = GENMASK(11, 0); mask 54 drivers/net/ethernet/apm/xgene/xgene_enet_main.c return (hw_len & mask) ? (hw_len & mask) : SIZE_2K; mask 865 drivers/net/ethernet/apple/bmac.c unsigned short mask; mask 871 drivers/net/ethernet/apple/bmac.c mask = crc % 16; mask 872 drivers/net/ethernet/apple/bmac.c mask = (unsigned char)1 << mask; mask 873 drivers/net/ethernet/apple/bmac.c bp->hash_use_count[crc/16] |= mask; mask 880 drivers/net/ethernet/apple/bmac.c unsigned char mask; mask 887 drivers/net/ethernet/apple/bmac.c mask = crc % 16; mask 888 drivers/net/ethernet/apple/bmac.c mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */ mask 889 drivers/net/ethernet/apple/bmac.c bp->hash_table_mask[crc/16] &= mask; mask 188 drivers/net/ethernet/aquantia/atlantic/aq_hw.h int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); mask 190 drivers/net/ethernet/aquantia/atlantic/aq_hw.h int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); mask 192 drivers/net/ethernet/aquantia/atlantic/aq_hw.h int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); mask 14 drivers/net/ethernet/aquantia/atlantic/aq_utils.h static inline void aq_utils_obj_set(atomic_t *flags, u32 mask) mask 20 drivers/net/ethernet/aquantia/atlantic/aq_utils.h flags_new = flags_old | (mask); mask 24 drivers/net/ethernet/aquantia/atlantic/aq_utils.h static inline void aq_utils_obj_clear(atomic_t *flags, u32 mask) mask 30 drivers/net/ethernet/aquantia/atlantic/aq_utils.h flags_new = flags_old & ~(mask); mask 34 drivers/net/ethernet/aquantia/atlantic/aq_utils.h static inline bool aq_utils_obj_test(atomic_t *flags, u32 mask) mask 36 drivers/net/ethernet/aquantia/atlantic/aq_utils.h return atomic_read(flags) & mask; mask 719 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask) mask 721 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) | mask 726 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask) mask 728 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); mask 729 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); mask 737 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask) mask 739 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c *mask = hw_atl_itr_irq_statuslsw_get(self); mask 784 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask) mask 786 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask)); mask 790 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask) mask 792 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask)); mask 793 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask)); mask 799 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask) mask 801 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c *mask = hw_atl_itr_irq_statuslsw_get(self); mask 89 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h union ip_addr mask; mask 51 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c u8 mask[16]; mask 198 drivers/net/ethernet/arc/emac.h static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask) mask 202 drivers/net/ethernet/arc/emac.h arc_reg_set(priv, reg, value | mask); mask 214 drivers/net/ethernet/arc/emac.h static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask) mask 218 drivers/net/ethernet/arc/emac.h arc_reg_set(priv, reg, value & ~mask); mask 364 drivers/net/ethernet/atheros/ag71xx.c static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask) mask 369 drivers/net/ethernet/atheros/ag71xx.c iowrite32(ioread32(r) | mask, r); mask 374 drivers/net/ethernet/atheros/ag71xx.c static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask) mask 379 drivers/net/ethernet/atheros/ag71xx.c iowrite32(ioread32(r) & ~mask, r); mask 1034 drivers/net/ethernet/atheros/alx/hw.c void alx_mask_msix(struct alx_hw *hw, int index, bool mask) mask 1041 drivers/net/ethernet/atheros/alx/hw.c val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0; mask 564 drivers/net/ethernet/atheros/alx/hw.h void alx_mask_msix(struct alx_hw *hw, int index, bool mask); mask 61 drivers/net/ethernet/aurora/nb8800.c u32 mask, u32 val) mask 64 drivers/net/ethernet/aurora/nb8800.c u32 new = (old & ~mask) | (val & mask); mask 71 drivers/net/ethernet/aurora/nb8800.c u32 mask, u32 val) mask 74 drivers/net/ethernet/aurora/nb8800.c u32 new = (old & ~mask) | (val & mask); mask 2254 drivers/net/ethernet/broadcom/b44.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 2310 drivers/net/ethernet/broadcom/b44.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); mask 2311 drivers/net/ethernet/broadcom/b44.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); mask 2312 drivers/net/ethernet/broadcom/b44.c linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); mask 2313 drivers/net/ethernet/broadcom/b44.c linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); mask 2314 drivers/net/ethernet/broadcom/b44.c linkmode_and(phydev->supported, phydev->supported, mask); mask 86 drivers/net/ethernet/broadcom/bcmsysport.c u32 mask) \ mask 88 drivers/net/ethernet/broadcom/bcmsysport.c priv->irq##which##_mask &= ~(mask); \ mask 89 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ mask 92 drivers/net/ethernet/broadcom/bcmsysport.c u32 mask) \ mask 94 drivers/net/ethernet/broadcom/bcmsysport.c intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ mask 95 drivers/net/ethernet/broadcom/bcmsysport.c priv->irq##which##_mask |= (mask); \ mask 1737 drivers/net/ethernet/broadcom/bcmsysport.c u32 mask, unsigned int enable) mask 1744 drivers/net/ethernet/broadcom/bcmsysport.c reg |= mask; mask 1746 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~mask; mask 1751 drivers/net/ethernet/broadcom/bcmsysport.c reg |= mask; mask 1753 drivers/net/ethernet/broadcom/bcmsysport.c reg &= ~mask; mask 15 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask, mask 23 drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c if ((val & mask) == value) mask 64 drivers/net/ethernet/broadcom/bgmac-bcma.c u32 mask, u32 set) mask 68 drivers/net/ethernet/broadcom/bgmac-bcma.c bcma_chipco_chipctl_maskset(cc, offset, mask, set); mask 78 drivers/net/ethernet/broadcom/bgmac-bcma.c static void bcma_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, u32 mask, mask 81 drivers/net/ethernet/broadcom/bgmac-bcma.c bcma_maskset32(bgmac->bcma.cmn, offset, mask, set); mask 97 drivers/net/ethernet/broadcom/bgmac-platform.c u32 mask, u32 set) mask 112 drivers/net/ethernet/broadcom/bgmac-platform.c u32 mask, u32 set) mask 21 drivers/net/ethernet/broadcom/bgmac.c static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, mask 29 drivers/net/ethernet/broadcom/bgmac.c if ((val & mask) == value) mask 749 drivers/net/ethernet/broadcom/bgmac.c static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, mask 753 drivers/net/ethernet/broadcom/bgmac.c u32 new_val = (cmdcfg & mask) | set; mask 828 drivers/net/ethernet/broadcom/bgmac.c u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); mask 852 drivers/net/ethernet/broadcom/bgmac.c bgmac_cmdcfg_maskset(bgmac, mask, set, true); mask 529 drivers/net/ethernet/broadcom/bgmac.h void (*cco_ctl_maskset)(struct bgmac *bgmac, u32 offset, u32 mask, mask 532 drivers/net/ethernet/broadcom/bgmac.h void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask, mask 579 drivers/net/ethernet/broadcom/bgmac.h u32 mask, u32 set) mask 581 drivers/net/ethernet/broadcom/bgmac.h bgmac->cco_ctl_maskset(bgmac, offset, mask, set); mask 590 drivers/net/ethernet/broadcom/bgmac.h u32 mask, u32 set) mask 592 drivers/net/ethernet/broadcom/bgmac.h bgmac->cmn_maskset32(bgmac, offset, mask, set); mask 595 drivers/net/ethernet/broadcom/bgmac.h static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, mask 598 drivers/net/ethernet/broadcom/bgmac.h bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set); mask 601 drivers/net/ethernet/broadcom/bgmac.h static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask) mask 603 drivers/net/ethernet/broadcom/bgmac.h bgmac_maskset(bgmac, offset, mask, 0); mask 4368 drivers/net/ethernet/broadcom/bnx2.c u32 mask; mask 4372 drivers/net/ethernet/broadcom/bnx2.c mask = FLASH_BACKUP_STRAP_MASK; mask 4374 drivers/net/ethernet/broadcom/bnx2.c mask = FLASH_STRAP_MASK; mask 4379 drivers/net/ethernet/broadcom/bnx2.c if ((val & mask) == (flash->strapping & mask)) { mask 2491 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define SET_FLAG(value, mask, flag) \ mask 2493 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h (value) &= ~(mask);\ mask 2494 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h (value) |= ((flag) << (mask##_SHIFT));\ mask 2497 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h #define GET_FLAG(value, mask) \ mask 2498 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h (((value) & (mask)) >> (mask##_SHIFT)) mask 1235 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) mask 1242 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h if (!(bp->sp_state & mask)) { mask 1254 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h if (bp->sp_state & mask) { mask 1256 drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h bp->sp_state, mask); mask 2239 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 mask; mask 2353 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 offset, mask, save_val, val; mask 2358 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c mask = reg_tbl[i].mask; mask 2362 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c REG_WR(bp, offset, wr_val & mask); mask 2370 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if ((val & mask) != (wr_val & mask)) { mask 2373 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c offset, val, wr_val, mask); mask 6041 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 mask; mask 6046 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = NIG_MASK_XGXS0_LINK_STATUS; mask 6048 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask |= NIG_MASK_MI_INT; mask 6050 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = (NIG_MASK_XGXS0_LINK10G | mask 6056 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask |= NIG_MASK_MI_INT; mask 6061 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = NIG_MASK_SERDES0_LINK_STATUS; mask 6066 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask |= NIG_MASK_MI_INT; mask 6072 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask); mask 6125 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 mask; mask 6135 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = NIG_STATUS_XGXS0_LINK_STATUS; mask 6138 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = NIG_STATUS_XGXS0_LINK10G; mask 6147 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = ((1 << ser_lane) << mask 6150 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask = NIG_STATUS_SERDES0_LINK_STATUS; mask 6153 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask); mask 6156 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c mask); mask 1906 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u16 mask; mask 1925 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); mask 1926 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (status & mask) { mask 1932 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c status &= ~mask; mask 1937 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c mask = 0x2; mask 1938 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (status & (mask | 0x1)) { mask 1948 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c status &= ~mask; mask 4484 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : mask 4495 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val1 = (val & mask) >> shift; mask 4501 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~mask; mask 4504 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= ((val1 << shift) & mask); mask 4522 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : mask 4532 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val1 = (val & mask) >> shift; mask 4538 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val &= ~mask; mask 4541 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val |= ((val1 << shift) & mask); mask 4555 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : mask 4563 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c val = (val & mask) >> shift; mask 10476 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; mask 10479 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if (!(mask & reset_reg)) mask 10494 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c u32 val, base_addr, offset, mask, reset_reg; mask 10505 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; mask 10506 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c if ((mask & reset_reg) && val) { mask 15323 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); mask 2309 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c u32 mask = (1 << p->cl_id); mask 2347 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->ucast_drop_all | mask : mask 2348 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->ucast_drop_all & ~mask; mask 2351 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->mcast_drop_all | mask : mask 2352 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->mcast_drop_all & ~mask; mask 2355 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->ucast_accept_all | mask : mask 2356 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->ucast_accept_all & ~mask; mask 2359 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->mcast_accept_all | mask : mask 2360 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->mcast_accept_all & ~mask; mask 2363 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->bcast_accept_all | mask : mask 2364 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->bcast_accept_all & ~mask; mask 2367 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->unmatched_unicast | mask : mask 2368 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c mac_filters->unmatched_unicast & ~mask; mask 4572 drivers/net/ethernet/broadcom/bnxt/bnxt.c req.mask = cpu_to_le32(vnic->rx_mask); mask 7780 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 mask = 0; mask 7782 drivers/net/ethernet/broadcom/bnxt/bnxt.c bnxt_mc_list_updated(bp, &mask); mask 7783 drivers/net/ethernet/broadcom/bnxt/bnxt.c vnic->rx_mask |= mask; mask 9573 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 mask; mask 9579 drivers/net/ethernet/broadcom/bnxt/bnxt.c mask = vnic->rx_mask; mask 9580 drivers/net/ethernet/broadcom/bnxt/bnxt.c mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | mask 9586 drivers/net/ethernet/broadcom/bnxt/bnxt.c mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; mask 9591 drivers/net/ethernet/broadcom/bnxt/bnxt.c mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; mask 9593 drivers/net/ethernet/broadcom/bnxt/bnxt.c mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; mask 9596 drivers/net/ethernet/broadcom/bnxt/bnxt.c mc_update = bnxt_mc_list_updated(bp, &mask); mask 9599 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (mask != vnic->rx_mask || uc_update || mc_update) { mask 9600 drivers/net/ethernet/broadcom/bnxt/bnxt.c vnic->rx_mask = mask; mask 429 drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c dscp2pri->mask = 0x3f; mask 431 drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.c dscp2pri->mask = 0; mask 38 drivers/net/ethernet/broadcom/bnxt/bnxt_dcb.h u8 mask; mask 5561 drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h __le32 mask; mask 192 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l2_mask.ether_type = match.mask->n_proto; mask 197 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l4_mask.ip_proto = match.mask->ip_proto; mask 207 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c ether_addr_copy(flow->l2_mask.dmac, match.mask->dst); mask 209 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c ether_addr_copy(flow->l2_mask.smac, match.mask->src); mask 220 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c cpu_to_be16((VLAN_TCI(match.mask->vlan_id, mask 221 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c match.mask->vlan_priority))); mask 233 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l3_mask.ipv4.daddr.s_addr = match.mask->dst; mask 235 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l3_mask.ipv4.saddr.s_addr = match.mask->src; mask 242 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l3_mask.ipv6.daddr = match.mask->dst; mask 244 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l3_mask.ipv6.saddr = match.mask->src; mask 253 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l4_mask.ports.dport = match.mask->dst; mask 255 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l4_mask.ports.sport = match.mask->src; mask 265 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l4_mask.icmp.type = match.mask->type; mask 266 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->l4_mask.icmp.code = match.mask->code; mask 275 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->tun_mask.u.ipv4.dst = match.mask->dst; mask 277 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->tun_mask.u.ipv4.src = match.mask->src; mask 289 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->tun_mask.tun_id = key32_to_tunnel_id(match.mask->keyid); mask 298 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->tun_mask.tp_dst = match.mask->dst; mask 300 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c flow->tun_mask.tp_src = match.mask->src; mask 325 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c static int ipv6_mask_len(struct in6_addr *mask) mask 330 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c mask_len += inet_mask_len(mask->s6_addr32[i]); mask 335 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c static bool is_wildcard(void *mask, int len) mask 337 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c const u8 *p = mask; mask 347 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c static bool is_exactmatch(void *mask, int len) mask 349 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c const u8 *p = mask; mask 1452 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c static void accumulate_val(u64 *accum, u64 val, u64 mask) mask 1454 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c #define low_bits(x, mask) ((x) & (mask)) mask 1455 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c #define high_bits(x, mask) ((x) & ~(mask)) mask 1456 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c bool wrapped = val < low_bits(*accum, mask); mask 1458 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c *accum = high_bits(*accum, mask) + val; mask 1460 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c *accum += (mask + 1); mask 1631 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c tc_info->bytes_mask = mask(36); mask 1632 drivers/net/ethernet/broadcom/bnxt/bnxt_tc.c tc_info->packets_mask = mask(28); mask 1667 drivers/net/ethernet/broadcom/cnic.c unsigned long mask = cp->ctx_align - 1; mask 1669 drivers/net/ethernet/broadcom/cnic.c if (cp->ctx_arr[blk].mapping & mask) mask 1671 drivers/net/ethernet/broadcom/cnic.c (cp->ctx_arr[blk].mapping & mask); mask 4857 drivers/net/ethernet/broadcom/cnic.c unsigned long mask = cp->ctx_align - 1; mask 4859 drivers/net/ethernet/broadcom/cnic.c map = (map + mask) & ~mask; mask 1748 drivers/net/ethernet/broadcom/genet/bcmgenet.c unsigned int p_index, mask; mask 1757 drivers/net/ethernet/broadcom/genet/bcmgenet.c mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); mask 1759 drivers/net/ethernet/broadcom/genet/bcmgenet.c mask, mask 1973 drivers/net/ethernet/broadcom/genet/bcmgenet.c static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) mask 1979 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg |= mask; mask 1981 drivers/net/ethernet/broadcom/genet/bcmgenet.c reg &= ~mask; mask 12249 drivers/net/ethernet/broadcom/tg3.c u32 mask = ADVERTISED_Autoneg | mask 12254 drivers/net/ethernet/broadcom/tg3.c mask |= ADVERTISED_1000baseT_Half | mask 12258 drivers/net/ethernet/broadcom/tg3.c mask |= ADVERTISED_100baseT_Half | mask 12264 drivers/net/ethernet/broadcom/tg3.c mask |= ADVERTISED_FIBRE; mask 12266 drivers/net/ethernet/broadcom/tg3.c if (advertising & ~mask) mask 12269 drivers/net/ethernet/broadcom/tg3.c mask &= (ADVERTISED_1000baseT_Half | mask 12276 drivers/net/ethernet/broadcom/tg3.c advertising &= mask; mask 546 drivers/net/ethernet/brocade/bna/bfi_enet.h u8 mask; mask 173 drivers/net/ethernet/brocade/bna/bna_hw_defs.h u32 mask; \ mask 174 drivers/net/ethernet/brocade/bna/bna_hw_defs.h mask = readl((bna)->regs.fn_int_mask); \ mask 175 drivers/net/ethernet/brocade/bna/bna_hw_defs.h writel((mask | (bna)->bits.mbox_mask_bits | \ mask 177 drivers/net/ethernet/brocade/bna/bna_hw_defs.h mask = readl((bna)->regs.fn_int_mask); \ mask 182 drivers/net/ethernet/brocade/bna/bna_hw_defs.h u32 mask; \ mask 183 drivers/net/ethernet/brocade/bna/bna_hw_defs.h mask = readl((bna)->regs.fn_int_mask); \ mask 184 drivers/net/ethernet/brocade/bna/bna_hw_defs.h writel((mask & ~((bna)->bits.mbox_mask_bits | \ mask 186 drivers/net/ethernet/brocade/bna/bna_hw_defs.h mask = readl((bna)->regs.fn_int_mask); \ mask 322 drivers/net/ethernet/brocade/bna/bna_tx_rx.c req->cfg.mask = rxf->rss_cfg.hash_mask; mask 249 drivers/net/ethernet/cavium/common/cavium_ptp.c cc->mask = CYCLECOUNTER_MASK(64); mask 1070 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c static void cn23xx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask) mask 1072 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c lio_pci_writeq(oct, mask, mask 332 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 mask; mask 334 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE); mask 335 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask |= oct->io_qmask.iq64B; mask 336 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_SIZE, mask); mask 338 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); mask 339 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask |= oct->io_qmask.iq; mask 340 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); mask 342 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); mask 343 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask |= oct->io_qmask.oq; mask 344 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); mask 352 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 mask, loop = HZ; mask 356 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB); mask 357 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask ^= oct->io_qmask.iq; mask 358 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, mask); mask 361 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = (u32)oct->io_qmask.iq; mask 363 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c while (((d32 & mask) != mask) && loop--) { mask 377 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); mask 378 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask ^= oct->io_qmask.oq; mask 379 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, mask); mask 383 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c mask = (u32)oct->io_qmask.oq; mask 385 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c while (((d32 & mask) != mask) && loop--) { mask 438 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u32 mask) mask 440 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c lio_pci_writeq(oct, mask, CN6XXX_BAR1_REG(idx, oct->pcie_port)); mask 474 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c u64 mask = cn6xxx->intr_mask64 | CN6XXX_INTR_DMA0_FORCE; mask 477 drivers/net/ethernet/cavium/liquidio/cn66xx_device.c writeq(mask, cn6xxx->intr_enb_reg64); mask 83 drivers/net/ethernet/cavium/liquidio/cn66xx_device.h void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask); mask 293 drivers/net/ethernet/cavium/liquidio/lio_main.c u32 status, mask; mask 298 drivers/net/ethernet/cavium/liquidio/lio_main.c pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask); mask 300 drivers/net/ethernet/cavium/liquidio/lio_main.c status &= ~mask; /* Clear corresponding nonfatal bits */ mask 302 drivers/net/ethernet/cavium/liquidio/lio_main.c status &= mask; /* Clear corresponding fatal bits */ mask 152 drivers/net/ethernet/cavium/liquidio/lio_vf_main.c u32 status, mask; mask 158 drivers/net/ethernet/cavium/liquidio/lio_vf_main.c pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask); mask 160 drivers/net/ethernet/cavium/liquidio/lio_vf_main.c status &= ~mask; /* Clear corresponding nonfatal bits */ mask 162 drivers/net/ethernet/cavium/liquidio/lio_vf_main.c status &= mask; /* Clear corresponding fatal bits */ mask 32 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c u32 mask; mask 34 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c mask = oct->fn_list.bar1_idx_read(oct, idx); mask 35 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c mask = (mask & 0x2) ? (mask & ~2) : (mask | 2); mask 36 drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c oct->fn_list.bar1_idx_write(oct, idx, mask); mask 1758 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 mask = nicvf_int_type_to_mask(int_type, q_idx); mask 1760 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!mask) { mask 1766 drivers/net/ethernet/cavium/thunder/nicvf_queues.c nicvf_reg_read(nic, NIC_VF_ENA_W1S) | mask); mask 1772 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 mask = nicvf_int_type_to_mask(int_type, q_idx); mask 1774 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!mask) { mask 1780 drivers/net/ethernet/cavium/thunder/nicvf_queues.c nicvf_reg_write(nic, NIC_VF_ENA_W1C, mask); mask 1786 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 mask = nicvf_int_type_to_mask(int_type, q_idx); mask 1788 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!mask) { mask 1794 drivers/net/ethernet/cavium/thunder/nicvf_queues.c nicvf_reg_write(nic, NIC_VF_INT, mask); mask 1800 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 mask = nicvf_int_type_to_mask(int_type, q_idx); mask 1802 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (!mask) { mask 1808 drivers/net/ethernet/cavium/thunder/nicvf_queues.c return mask & nicvf_reg_read(nic, NIC_VF_ENA_W1S); mask 128 drivers/net/ethernet/cavium/thunder/thunder_bgx.c static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero) mask 135 drivers/net/ethernet/cavium/thunder/thunder_bgx.c if (zero && !(reg_val & mask)) mask 137 drivers/net/ethernet/cavium/thunder/thunder_bgx.c if (!zero && (reg_val & mask)) mask 317 drivers/net/ethernet/chelsio/cxgb/cpl5_cmd.h u32 mask; mask 61 drivers/net/ethernet/chelsio/cxgb/subr.c static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, mask 65 drivers/net/ethernet/chelsio/cxgb/subr.c u32 val = readl(adapter->regs + reg) & mask; mask 642 drivers/net/ethernet/chelsio/cxgb3/common.h void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, mask 646 drivers/net/ethernet/chelsio/cxgb3/common.h int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, mask 648 drivers/net/ethernet/chelsio/cxgb3/common.h static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, mask 651 drivers/net/ethernet/chelsio/cxgb3/common.h return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, mask 541 drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c greq->mask = cpu_to_be64(1); mask 1105 drivers/net/ethernet/chelsio/cxgb3/cxgb3_offload.c req->mask = cpu_to_be64(V_TCB_L2T_IX(M_TCB_L2T_IX)); mask 674 drivers/net/ethernet/chelsio/cxgb3/t3_cpl.h __be64 mask; mask 55 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, mask 61 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (!!(val & mask) == polarity) { mask 103 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, mask 106 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 v = t3_read_reg(adapter, addr) & ~mask; mask 1411 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int mask; /* bits to check in interrupt status */ mask 1433 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int mask, mask 1438 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c unsigned int status = t3_read_reg(adapter, reg) & mask; mask 1440 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c for (; acts->mask; ++acts) { mask 1441 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c if (!(status & acts->mask)) mask 1446 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c acts->msg, status & acts->mask); mask 1447 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c status &= ~acts->mask; mask 1450 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c acts->msg, status & acts->mask); mask 2999 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c u32 addr, key[4], mask[4]; mask 3006 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c mask[0] = tp->sport_mask | (tp->sip_mask << 16); mask 3007 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c mask[1] = (tp->sip_mask >> 16) | (tp->dport_mask << 16); mask 3008 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c mask[2] = tp->dip_mask; mask 3009 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c mask[3] = tp->proto_mask | (tp->vlan_mask << 8) | (tp->intf_mask << 20); mask 3018 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c tp_wr_indirect(adapter, addr++, mask[0]); mask 3020 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c tp_wr_indirect(adapter, addr++, mask[1]); mask 3022 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c tp_wr_indirect(adapter, addr++, mask[2]); mask 3024 drivers/net/ethernet/chelsio/cxgb3/t3_hw.c tp_wr_indirect(adapter, addr, mask[3]); mask 205 drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h u64 mask; mask 2085 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) mask 2087 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c *mask = x | y; mask 2236 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask); mask 475 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u32 mask[TRACE_LEN / 4]; mask 920 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h u8 mask[ETH_ALEN]; mask 1224 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h struct ch_filter_tuple mask; mask 1499 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, mask 1731 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h unsigned int mask, unsigned int val); mask 1797 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *addr, const u8 *mask, unsigned int idx, mask 1802 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *addr, const u8 *mask, unsigned int vni, mask 1806 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *addr, const u8 *mask, unsigned int idx, mask 1928 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *addr, const u8 *mask, mask 1936 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *mask, mask 1944 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h const u8 *mask, mask 460 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u64 mask = (1ULL << p->width) - 1; mask 462 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c ((unsigned long long)v >> p->start) & mask); mask 1365 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); mask 1374 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c seq_printf(seq, "%08x%08x", tp.mask[i], tp.mask[i + 1]); mask 1414 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u32 *data, *mask; mask 1547 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c mask = &tp.mask[i / 8]; mask 1564 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c *mask = (*mask << 4) + xdigit2int(*word++); mask 1566 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c mask++; mask 1572 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c *mask++ = 0xffffffff; mask 1574 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c *mask = (1 << (i % 8) * 4) - 1; mask 1592 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c *mask <<= (8 - i % 8) * 4; mask 1664 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask) mask 1666 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c *mask = x | y; mask 1695 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c u64 mask; mask 1810 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c tcamxy2valmask(tcamx, tcamy, addr, &mask); mask 1821 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c (unsigned long long)mask, mask 1836 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c (unsigned long long)mask); mask 1856 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c addr[4], addr[5], (unsigned long long)mask, mask 2267 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c #define G_PFnMSKSIZE(mask, n) \ mask 2268 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c (((mask) >> PF1MSKSIZE_S*(n)) & PF1MSKSIZE_M) mask 46 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c static inline bool is_field_set(u32 val, u32 mask) mask 48 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c return val || mask; mask 51 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c static inline bool unsupported(u32 conf, u32 conf_mask, u32 val, u32 mask) mask 53 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c return !(conf & conf_mask) && is_field_set(val, mask); mask 57 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsigned int ftid, u16 word, u64 mask, u64 val, mask 73 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->mask = cpu_to_be64(mask); mask 122 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsigned int word, u64 mask, u64 val, mask 136 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c req->mask = cpu_to_be64(mask); mask 255 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (unsupported(fconf, FCOE_F, fs->val.fcoe, fs->mask.fcoe) || mask 256 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, PORT_F, fs->val.iport, fs->mask.iport) || mask 257 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, TOS_F, fs->val.tos, fs->mask.tos) || mask 259 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.ethtype) || mask 260 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, MACMATCH_F, fs->val.macidx, fs->mask.macidx) || mask 262 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.matchtype) || mask 263 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, FRAGMENTATION_F, fs->val.frag, fs->mask.frag) || mask 264 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, PROTOCOL_F, fs->val.proto, fs->mask.proto) || mask 266 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.pfvf_vld) || mask 268 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.ovlan_vld) || mask 270 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.encap_vld) || mask 271 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c unsupported(fconf, VLAN_F, fs->val.ivlan_vld, fs->mask.ivlan_vld)) mask 281 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if ((is_field_set(fs->val.pfvf_vld, fs->mask.pfvf_vld) && mask 282 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld)) || mask 283 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.pfvf_vld, fs->mask.pfvf_vld) && mask 284 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.encap_vld, fs->mask.encap_vld)) || mask 285 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld) && mask 286 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c is_field_set(fs->val.encap_vld, fs->mask.encap_vld))) mask 288 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (unsupported(iconf, VNIC_F, fs->val.pfvf_vld, fs->mask.pfvf_vld) || mask 289 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c (is_field_set(fs->val.ovlan_vld, fs->mask.ovlan_vld) && mask 294 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.pf &= 0x7; mask 295 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.vf &= 0x7f; mask 620 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ethtypem = htons(f->fs.mask.ethtype); mask 623 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) | mask 626 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) | mask 627 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld)); mask 634 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) | mask 636 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) | mask 638 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_PORTM_V(f->fs.mask.iport) | mask 640 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype)); mask 642 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ptclm = f->fs.mask.proto; mask 644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ttypm = f->fs.mask.tos; mask 646 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ivlanm = htons(f->fs.mask.ivlan); mask 648 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->ovlanm = htons(f->fs.mask.ovlan); mask 650 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm)); mask 652 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm)); mask 654 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->lpm = htons(f->fs.mask.lport); mask 656 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fwr->fpm = htons(f->fs.mask.fport); mask 789 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.iport && !fs->mask.iport) mask 790 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.iport |= ~0; mask 791 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.fcoe && !fs->mask.fcoe) mask 792 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.fcoe |= ~0; mask 793 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.matchtype && !fs->mask.matchtype) mask 794 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.matchtype |= ~0; mask 795 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.macidx && !fs->mask.macidx) mask 796 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.macidx |= ~0; mask 797 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ethtype && !fs->mask.ethtype) mask 798 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.ethtype |= ~0; mask 799 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ivlan && !fs->mask.ivlan) mask 800 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.ivlan |= ~0; mask 801 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.ovlan && !fs->mask.ovlan) mask 802 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.ovlan |= ~0; mask 803 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.frag && !fs->mask.frag) mask 804 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.frag |= ~0; mask 805 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.tos && !fs->mask.tos) mask 806 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.tos |= ~0; mask 807 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.proto && !fs->mask.proto) mask 808 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.proto |= ~0; mask 812 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c lip_mask |= fs->mask.lip[i]; mask 814 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fip_mask |= fs->mask.fip[i]; mask 818 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memset(fs->mask.lip, ~0, sizeof(fs->mask.lip)); mask 821 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c memset(fs->mask.fip, ~0, sizeof(fs->mask.lip)); mask 823 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.lport && !fs->mask.lport) mask 824 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.lport = ~0; mask 825 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->val.fport && !fs->mask.fport) mask 826 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.fport = ~0; mask 883 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (fs->mask.encap_vld) mask 888 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c !is_addr_all_mask(fs->mask.fip, AF_INET6)) mask 892 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c !is_addr_all_mask(fs->mask.lip, AF_INET6)) mask 896 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c !is_addr_all_mask(fs->mask.fip, AF_INET)) mask 900 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c !is_addr_all_mask(fs->mask.lip, AF_INET)) mask 904 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (!fs->val.lport || fs->mask.lport != 0xffff) mask 907 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (!fs->val.fport || fs->mask.fport != 0xffff) mask 912 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.fcoe << tp->fcoe_shift; mask 915 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.iport << tp->port_shift; mask 919 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.pfvf_vld << tp->vnic_shift; mask 921 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.ovlan_vld << mask 926 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.ivlan << tp->vlan_shift; mask 929 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.tos << tp->tos_shift; mask 932 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift; mask 935 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift; mask 938 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.macidx << tp->macmatch_shift; mask 941 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.matchtype << tp->matchtype_shift; mask 944 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c ntuple_mask |= (u64)fs->mask.frag << tp->frag_shift; mask 962 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->vlan_shift >= 0 && fs->mask.ivlan) mask 965 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->port_shift >= 0 && fs->mask.iport) mask 975 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->tos_shift >= 0 && fs->mask.tos) mask 980 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.encap_vld) mask 984 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c fs->mask.pfvf_vld) mask 993 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->macmatch_shift >= 0 && fs->mask.macidx) mask 996 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->ethertype_shift >= 0 && fs->mask.ethtype) mask 999 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->matchtype_shift >= 0 && fs->mask.matchtype) mask 1002 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->frag_shift >= 0 && fs->mask.frag) mask 1005 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c if (tp->fcoe_shift >= 0 && fs->mask.fcoe) mask 1160 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan = (fs->mask.pf << 13) | fs->mask.vf; mask 1162 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan_vld = fs->mask.pfvf_vld; mask 1173 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.vni, mask 1179 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan = 0xffff; mask 1181 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan_vld = 1; mask 1402 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan = (fs->mask.pf << 13) | fs->mask.vf; mask 1404 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan_vld = fs->mask.pfvf_vld; mask 1415 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.vni, mask 1421 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan = 0x1ff; mask 1423 drivers/net/ethernet/chelsio/cxgb4/cxgb4_filter.c f->fs.mask.ovlan_vld = 1; mask 2478 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c unsigned int queue, unsigned char port, unsigned char mask) mask 2508 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.mask.lport = ~0; mask 2513 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.mask.lip[i] = ~0; mask 2517 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.mask.iport = mask; mask 2523 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c f->fs.mask.proto = ~0; mask 7 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c const u8 *addr, const u8 *mask) mask 16 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c ether_addr_equal(mps_entry->mask, mask ? mask : bitmask)) { mask 54 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c u16 idx, const u8 *mask) mask 72 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c ether_addr_copy(mps_entry->mask, mask ? mask : bitmask); mask 147 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c const u8 *mask, mask 157 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c mask, idx, lookup_type, mask 166 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c const u8 *mask, mask 175 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c mask, idx, lookup_type, mask 180 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c if (cxgb4_mps_ref_inc(adap, addr, ret, mask)) { mask 183 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c mask, idx, lookup_type, mask 202 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c const u8 *addr, const u8 *mask, mask 208 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c ret = t4_alloc_encap_mac_filt(adap, viid, addr, mask, vni, vni_mask, mask 213 drivers/net/ethernet/chelsio/cxgb4/cxgb4_mps.c if (cxgb4_mps_ref_inc(adap, addr, ret, mask)) { mask 103 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c ethtype_mask = ntohs(match.mask->n_proto); mask 114 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.ethtype = ethtype_mask; mask 116 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.proto = match.mask->ip_proto; mask 126 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->mask.lip[0], &match.mask->dst, sizeof(match.mask->dst)); mask 127 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->mask.fip[0], &match.mask->src, sizeof(match.mask->src)); mask 143 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->mask.lip[0], match.mask->dst.s6_addr, mask 144 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c sizeof(match.mask->dst)); mask 145 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c memcpy(&fs->mask.fip[0], match.mask->src.s6_addr, mask 146 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c sizeof(match.mask->src)); mask 160 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.lport = cpu_to_be16(match.mask->dst); mask 162 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.fport = cpu_to_be16(match.mask->src); mask 174 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.tos = match.mask->tos; mask 182 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.vni = be32_to_cpu(match.mask->keyid); mask 183 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (fs->mask.vni) { mask 185 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.encap_vld = 1; mask 196 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c vlan_tci_mask = match.mask->vlan_id | (match.mask->vlan_priority << mask 199 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.ivlan = vlan_tci_mask; mask 202 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.ivlan_vld = 1; mask 215 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.ethtype = 0; mask 223 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c fs->mask.iport = ~0; mask 253 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c ethtype_mask = ntohs(match.mask->n_proto); mask 266 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (match.mask->ttl) { mask 275 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c static void offload_pedit(struct ch_filter_specification *fs, u32 val, u32 mask, mask 278 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 set_val = val & ~mask; mask 294 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 mask, u32 offset, u8 htype) mask 301 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_DMAC_31_0); mask 304 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (~mask & PEDIT_ETH_DMAC_MASK) mask 305 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_DMAC_47_32); mask 307 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val >> 16, mask >> 16, mask 312 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, ETH_SMAC_47_16); mask 318 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP4_SRC); mask 321 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP4_DST); mask 328 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_31_0); mask 331 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_63_32); mask 334 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_95_64); mask 337 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_SRC_127_96); mask 340 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_31_0); mask 343 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_63_32); mask 346 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_95_64); mask 349 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c offload_pedit(fs, val, mask, IP6_DST_127_96); mask 356 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (~mask & PEDIT_TCP_UDP_SPORT_MASK) mask 358 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c cpu_to_be32(mask) >> 16, mask 362 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c cpu_to_be32(mask), TCP_DPORT); mask 369 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (~mask & PEDIT_TCP_UDP_SPORT_MASK) mask 371 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c cpu_to_be32(mask) >> 16, mask 375 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c cpu_to_be32(mask), UDP_DPORT); mask 429 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 mask, val, offset; mask 433 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c mask = act->mangle.mask; mask 437 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c process_pedit_field(fs, val, mask, offset, htype); mask 446 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c static bool valid_l4_mask(u32 mask) mask 453 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c hi = (mask >> 16) & 0xFFFF; mask 454 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c lo = mask & 0xFFFF; mask 462 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c u32 mask, offset; mask 466 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c mask = act->mangle.mask; mask 513 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (!valid_l4_mask(~mask)) { mask 528 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c if (!valid_l4_mask(~mask)) { mask 50 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c u32 val, mask; mask 57 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c mask = cls->knode.sel->keys[i].mask; mask 74 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c err = entry[j].val(fs, val, mask); mask 219 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c u32 val, mask; mask 235 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c next[i].mask != cls->knode.sel->offmask || mask 246 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c mask = cls->knode.sel->keys[j].mask; mask 250 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c next[i].match_mask == mask) { mask 316 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32.c fs.mask.iport = ~0; mask 41 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h int (*val)(struct ch_filter_specification *f, u32 val, u32 mask); mask 46 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 49 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; mask 55 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 61 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h mask_val = ntohl(mask) & 0x0000FFFF; mask 65 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.frag = 1; mask 68 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.frag = 1; mask 77 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 80 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.proto = (ntohl(mask) >> 16) & 0x000000FF; mask 86 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 89 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.fip[0], &mask, sizeof(u32)); mask 95 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 98 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.lip[0], &mask, sizeof(u32)); mask 114 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 117 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.tos = (ntohl(mask) >> 20) & 0x000000FF; mask 123 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 126 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.proto = (ntohl(mask) >> 8) & 0x000000FF; mask 132 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 135 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.fip[0], &mask, sizeof(u32)); mask 141 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 144 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.fip[4], &mask, sizeof(u32)); mask 150 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 153 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.fip[8], &mask, sizeof(u32)); mask 159 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 162 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.fip[12], &mask, sizeof(u32)); mask 168 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 171 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.lip[0], &mask, sizeof(u32)); mask 177 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 180 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.lip[4], &mask, sizeof(u32)); mask 186 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 189 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.lip[8], &mask, sizeof(u32)); mask 195 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 198 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h memcpy(&f->mask.lip[12], &mask, sizeof(u32)); mask 219 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 val, u32 mask) mask 222 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.fport = ntohl(mask) >> 16; mask 224 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h f->mask.lport = ntohl(mask) & 0x0000FFFF; mask 248 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h u32 mask; mask 261 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .offset = 0, .offoff = 0, .shift = 6, .mask = 0xF, mask 264 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .offset = 0, .offoff = 0, .shift = 6, .mask = 0xF, mask 274 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .offset = 0x28, .offoff = 0, .shift = 0, .mask = 0, mask 277 drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_u32_parse.h { .offset = 0x28, .offoff = 0, .shift = 0, .mask = 0, mask 199 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h unsigned char port, unsigned char mask); mask 57 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, mask 63 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (!!(val & mask) == polarity) { mask 75 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, mask 78 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, mask 92 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, mask 95 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 v = t4_read_reg(adapter, addr) & ~mask; mask 4297 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mask; /* bits to check in interrupt status */ mask 4321 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mask = 0; mask 4324 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c for ( ; acts->mask; ++acts) { mask 4325 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (!(status & acts->mask)) mask 4330 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c status & acts->mask); mask 4333 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c status & acts->mask); mask 4336 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mask |= acts->mask; mask 4338 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c status &= mask; mask 5539 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c u32 vrt, mask, data; mask 5542 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mask = VFWRADDR_V(VFWRADDR_M); mask 5545 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c mask = T6_VFWRADDR_V(T6_VFWRADDR_M); mask 5552 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask); mask 5797 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c unsigned int mask, unsigned int val) mask 5800 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; mask 5994 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c t4_write_reg(adap, mask_reg, ~tp->mask[i]); mask 6047 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c tp->mask[i] = ~t4_read_reg(adap, mask_reg); mask 6048 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; mask 7803 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c const u8 *addr, const u8 *mask, unsigned int idx, mask 7832 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); mask 7854 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c const u8 *addr, const u8 *mask, unsigned int vni, mask 7873 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); mask 7902 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c const u8 *addr, const u8 *mask, unsigned int idx, mask 7930 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN); mask 704 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h __be64 mask; mask 40 drivers/net/ethernet/cisco/enic/vnic_intr.h u32 mask; /* 0x20 */ mask 56 drivers/net/ethernet/cisco/enic/vnic_intr.h iowrite32(0, &intr->ctrl->mask); mask 61 drivers/net/ethernet/cisco/enic/vnic_intr.h iowrite32(1, &intr->ctrl->mask); mask 66 drivers/net/ethernet/cisco/enic/vnic_intr.h return ioread32(&intr->ctrl->mask); mask 1115 drivers/net/ethernet/cortina/gemini.c u32 val, mask; mask 1119 drivers/net/ethernet/cortina/gemini.c mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq); mask 1122 drivers/net/ethernet/cortina/gemini.c writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG); mask 1125 drivers/net/ethernet/cortina/gemini.c val = en ? val | mask : val & ~mask; mask 1312 drivers/net/ethernet/cortina/gemini.c u32 val, mask; mask 1318 drivers/net/ethernet/cortina/gemini.c mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2); mask 1320 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); mask 1323 drivers/net/ethernet/cortina/gemini.c mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; mask 1325 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); mask 1328 drivers/net/ethernet/cortina/gemini.c mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8); mask 1330 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); mask 1341 drivers/net/ethernet/cortina/gemini.c u32 val, mask; mask 1346 drivers/net/ethernet/cortina/gemini.c mask = DEFAULT_Q0_INT_BIT << netdev->dev_id; mask 1349 drivers/net/ethernet/cortina/gemini.c val = enable ? (val | mask) : (val & ~mask); mask 57 drivers/net/ethernet/cortina/gemini.h #define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask)) mask 58 drivers/net/ethernet/cortina/gemini.h #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask)) mask 59 drivers/net/ethernet/cortina/gemini.h #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask)) mask 496 drivers/net/ethernet/dec/tulip/de4x5.c int mask; mask 507 drivers/net/ethernet/dec/tulip/de4x5.c int mask; mask 932 drivers/net/ethernet/dec/tulip/de4x5.c static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec); mask 3445 drivers/net/ethernet/dec/tulip/de4x5.c test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec) mask 3455 drivers/net/ethernet/dec/tulip/de4x5.c reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; mask 3456 drivers/net/ethernet/dec/tulip/de4x5.c test = (reg ^ (pol ? ~0 : 0)) & mask; mask 3477 drivers/net/ethernet/dec/tulip/de4x5.c spd &= lp->phy[lp->active].spd.mask; mask 5005 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ mask 325 drivers/net/ethernet/ec_bhf.c u32 mask; mask 329 drivers/net/ethernet/ec_bhf.c mask = ioread32(priv->dma_io + offset); mask 330 drivers/net/ethernet/ec_bhf.c mask &= DMA_WINDOW_SIZE_MASK; mask 338 drivers/net/ethernet/ec_bhf.c buf->len = min_t(int, ~mask + 1, size); mask 348 drivers/net/ethernet/ec_bhf.c buf->buf_phys = (buf->alloc_phys + buf->len) & mask; mask 842 drivers/net/ethernet/emulex/benet/be.h amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) mask 845 drivers/net/ethernet/emulex/benet/be.h *dw &= ~(mask << offset); mask 846 drivers/net/ethernet/emulex/benet/be.h *dw |= (mask & value) << offset; mask 856 drivers/net/ethernet/emulex/benet/be.h static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) mask 859 drivers/net/ethernet/emulex/benet/be.h return mask & (*(dw + dw_offset) >> offset); mask 4780 drivers/net/ethernet/emulex/benet/be_cmds.c int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask) mask 4788 drivers/net/ethernet/emulex/benet/be_cmds.c iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET); mask 2487 drivers/net/ethernet/emulex/benet/be_cmds.h int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask); mask 265 drivers/net/ethernet/ethoc.c static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask) mask 268 drivers/net/ethernet/ethoc.c imask |= mask; mask 272 drivers/net/ethernet/ethoc.c static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask) mask 275 drivers/net/ethernet/ethoc.c imask &= ~mask; mask 279 drivers/net/ethernet/ethoc.c static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) mask 281 drivers/net/ethernet/ethoc.c ethoc_write(dev, INT_SOURCE, mask); mask 551 drivers/net/ethernet/ethoc.c u32 mask; mask 561 drivers/net/ethernet/ethoc.c mask = ethoc_read(priv, INT_MASK); mask 563 drivers/net/ethernet/ethoc.c pending &= mask; mask 710 drivers/net/ethernet/fealnx.c unsigned int mask, data; mask 733 drivers/net/ethernet/fealnx.c mask = 0x8000; mask 734 drivers/net/ethernet/fealnx.c while (mask) { mask 737 drivers/net/ethernet/fealnx.c if (mask & data) mask 747 drivers/net/ethernet/fealnx.c mask >>= 1; mask 748 drivers/net/ethernet/fealnx.c if (mask == 0x2 && opcode == OP_READ) mask 760 drivers/net/ethernet/fealnx.c unsigned int mask, data; mask 765 drivers/net/ethernet/fealnx.c mask = 0x8000; mask 767 drivers/net/ethernet/fealnx.c while (mask) { mask 775 drivers/net/ethernet/fealnx.c data |= mask; mask 783 drivers/net/ethernet/fealnx.c mask >>= 1; mask 799 drivers/net/ethernet/fealnx.c unsigned int mask; mask 804 drivers/net/ethernet/fealnx.c mask = 0x8000; mask 805 drivers/net/ethernet/fealnx.c while (mask) { mask 808 drivers/net/ethernet/fealnx.c if (mask & data) mask 817 drivers/net/ethernet/fealnx.c mask >>= 1; mask 2491 drivers/net/ethernet/freescale/dpaa/dpaa_eth.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 2511 drivers/net/ethernet/freescale/dpaa/dpaa_eth.c ethtool_convert_legacy_u32_to_link_mode(mask, mask 2513 drivers/net/ethernet/freescale/dpaa/dpaa_eth.c linkmode_and(phy_dev->supported, phy_dev->supported, mask); mask 275 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c void *key, void *mask, u64 *fields) mask 282 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = eth_mask->h_proto; mask 289 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c ether_addr_copy(mask + off, eth_mask->h_source); mask 296 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c ether_addr_copy(mask + off, eth_mask->h_dest); mask 305 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c void *key, void *mask, u64 *fields) mask 316 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be32 *)(mask + off) = uip_mask->ip4src; mask 323 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be32 *)(mask + off) = uip_mask->ip4dst; mask 330 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(u8 *)(mask + off) = uip_mask->proto; mask 340 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = htons(tmp_mask >> 16); mask 345 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = htons(tmp_mask & 0xFFFF); mask 352 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = htons(0xFFFF); mask 360 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c void *key, void *mask, u8 l4_proto, u64 *fields) mask 370 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be32 *)(mask + off) = l4_mask->ip4src; mask 377 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be32 *)(mask + off) = l4_mask->ip4dst; mask 384 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = l4_mask->psrc; mask 391 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = l4_mask->pdst; mask 398 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = htons(0xFFFF); mask 403 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(u8 *)(mask + off) = 0xFF; mask 411 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c void *key, void *mask, u64 *fields) mask 421 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(__be16 *)(mask + off) = ext_mask->vlan_tci; mask 430 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c void *key, void *mask, u64 *fields) mask 437 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c ether_addr_copy(mask + off, ext_mask->h_dest); mask 444 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c static int prep_cls_rule(struct ethtool_rx_flow_spec *fs, void *key, void *mask, mask 452 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c key, mask, fields); mask 456 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c &fs->m_u.usr_ip4_spec, key, mask, fields); mask 460 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c key, mask, IPPROTO_TCP, fields); mask 464 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c key, mask, IPPROTO_UDP, fields); mask 468 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c &fs->m_u.sctp_ip4_spec, key, mask, mask 479 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c err = prep_ext_rule(&fs->h_ext, &fs->m_ext, key, mask, fields); mask 485 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c err = prep_mac_ext_rule(&fs->h_ext, &fs->m_ext, key, mask, mask 22 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c u32 mask = 0; mask 38 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c DPRTC_IRQ_INDEX, &mask); mask 45 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c mask |= bit; mask 47 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c mask &= ~bit; mask 50 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c DPRTC_IRQ_INDEX, mask); mask 56 drivers/net/ethernet/freescale/dpaa2/dpkg.h u8 mask; mask 150 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h __le32 mask; mask 160 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h __le32 mask; mask 396 drivers/net/ethernet/freescale/dpaa2/dpni-cmd.h u8 mask; mask 66 drivers/net/ethernet/freescale/dpaa2/dpni.c extr->masks[j].mask = cfg->extracts[i].masks[j].mask; mask 386 drivers/net/ethernet/freescale/dpaa2/dpni.c u32 mask) mask 396 drivers/net/ethernet/freescale/dpaa2/dpni.c cmd_params->mask = cpu_to_le32(mask); mask 420 drivers/net/ethernet/freescale/dpaa2/dpni.c u32 *mask) mask 441 drivers/net/ethernet/freescale/dpaa2/dpni.c *mask = le32_to_cpu(rsp_params->mask); mask 159 drivers/net/ethernet/freescale/dpaa2/dpni.h u32 mask); mask 165 drivers/net/ethernet/freescale/dpaa2/dpni.h u32 *mask); mask 48 drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h __le32 mask; mask 53 drivers/net/ethernet/freescale/dpaa2/dprtc-cmd.h __le32 mask; mask 167 drivers/net/ethernet/freescale/dpaa2/dprtc.c u32 mask) mask 176 drivers/net/ethernet/freescale/dpaa2/dprtc.c cmd_params->mask = cpu_to_le32(mask); mask 199 drivers/net/ethernet/freescale/dpaa2/dprtc.c u32 *mask) mask 217 drivers/net/ethernet/freescale/dpaa2/dprtc.c *mask = le32_to_cpu(rsp_params->mask); mask 49 drivers/net/ethernet/freescale/dpaa2/dprtc.h u32 mask); mask 55 drivers/net/ethernet/freescale/dpaa2/dprtc.h u32 *mask); mask 99 drivers/net/ethernet/freescale/enetc/enetc_pf.c u64 mask = 0; mask 104 drivers/net/ethernet/freescale/enetc/enetc_pf.c mask |= BIT_ULL(i * 6); mask 107 drivers/net/ethernet/freescale/enetc/enetc_pf.c res |= (hweight64(fold & (mask << i)) & 0x1) << i; mask 177 drivers/net/ethernet/freescale/fec_ptp.c val &= fep->cc.mask; mask 181 drivers/net/ethernet/freescale/fec_ptp.c fep->next_counter = (val + fep->reload_period) & fep->cc.mask; mask 200 drivers/net/ethernet/freescale/fec_ptp.c fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; mask 267 drivers/net/ethernet/freescale/fec_ptp.c fep->cc.mask = CLOCKSOURCE_MASK(31); mask 423 drivers/net/ethernet/freescale/fec_ptp.c counter = ns & fep->cc.mask; mask 553 drivers/net/ethernet/freescale/fec_ptp.c fep->cc.mask; mask 1227 drivers/net/ethernet/freescale/fman/fman.c u32 event, mask, force; mask 1232 drivers/net/ethernet/freescale/fman/fman.c mask = ioread32be(&bmi_rg->fmbm_ier); mask 1233 drivers/net/ethernet/freescale/fman/fman.c event &= mask; mask 1255 drivers/net/ethernet/freescale/fman/fman.c u32 event, mask, force; mask 1260 drivers/net/ethernet/freescale/fman/fman.c mask = ioread32be(&qmi_rg->fmqm_eien); mask 1261 drivers/net/ethernet/freescale/fman/fman.c event &= mask; mask 1281 drivers/net/ethernet/freescale/fman/fman.c u32 status, mask, com_id; mask 1288 drivers/net/ethernet/freescale/fman/fman.c mask = ioread32be(&dma_rg->fmdmmr); mask 1291 drivers/net/ethernet/freescale/fman/fman.c if ((mask & DMA_MODE_BER) != DMA_MODE_BER) mask 1295 drivers/net/ethernet/freescale/fman/fman.c if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC) mask 1357 drivers/net/ethernet/freescale/fman/fman.c u32 event, mask; mask 1362 drivers/net/ethernet/freescale/fman/fman.c mask = ioread32be(&fpm_rg->fm_rie); mask 1367 drivers/net/ethernet/freescale/fman/fman.c if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC)) mask 1375 drivers/net/ethernet/freescale/fman/fman.c u32 event, mask, force; mask 1380 drivers/net/ethernet/freescale/fman/fman.c mask = ioread32be(&qmi_rg->fmqm_ien); mask 1381 drivers/net/ethernet/freescale/fman/fman.c event &= mask; mask 1672 drivers/net/ethernet/freescale/gianfar.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 1680 drivers/net/ethernet/freescale/gianfar.c mask); mask 1681 drivers/net/ethernet/freescale/gianfar.c linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); mask 1682 drivers/net/ethernet/freescale/gianfar.c linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); mask 1684 drivers/net/ethernet/freescale/gianfar.c linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask); mask 1701 drivers/net/ethernet/freescale/gianfar.c linkmode_and(phydev->supported, phydev->supported, mask); mask 858 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_mask(u32 mask, struct filer_table *tab) mask 861 drivers/net/ethernet/freescale/gianfar_ethtool.c tab->fe[tab->index].prop = mask; mask 866 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_parse_bits(u32 value, u32 mask, struct filer_table *tab) mask 868 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_mask(mask, tab); mask 875 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_general_attribute(u32 value, u32 mask, u32 flag, mask 878 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_mask(mask, tab); mask 898 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_attribute(u32 value, u32 mask, u32 flag, mask 904 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!(value | mask)) mask 906 drivers/net/ethernet/freescale/gianfar_ethtool.c mask |= RQFCR_PID_PRI_MASK; mask 911 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!~(mask | RQFCR_PID_L4P_MASK)) mask 913 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!mask) mask 914 drivers/net/ethernet/freescale/gianfar_ethtool.c mask = ~0; mask 916 drivers/net/ethernet/freescale/gianfar_ethtool.c mask |= RQFCR_PID_L4P_MASK; mask 920 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!(value | mask)) mask 922 drivers/net/ethernet/freescale/gianfar_ethtool.c mask |= RQFCR_PID_VID_MASK; mask 928 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!~(mask | RQFCR_PID_PORT_MASK)) mask 930 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!mask) mask 931 drivers/net/ethernet/freescale/gianfar_ethtool.c mask = ~0; mask 933 drivers/net/ethernet/freescale/gianfar_ethtool.c mask |= RQFCR_PID_PORT_MASK; mask 940 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!(value | mask)) mask 942 drivers/net/ethernet/freescale/gianfar_ethtool.c mask |= RQFCR_PID_MAC_MASK; mask 946 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!~mask) mask 948 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!mask) mask 949 drivers/net/ethernet/freescale/gianfar_ethtool.c mask = ~0; mask 952 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_general_attribute(value, mask, flag, tab); mask 957 drivers/net/ethernet/freescale/gianfar_ethtool.c struct ethtool_tcpip4_spec *mask, mask 961 drivers/net/ethernet/freescale/gianfar_ethtool.c be32_to_cpu(mask->ip4src), mask 964 drivers/net/ethernet/freescale/gianfar_ethtool.c be32_to_cpu(mask->ip4dst), mask 967 drivers/net/ethernet/freescale/gianfar_ethtool.c be16_to_cpu(mask->pdst), mask 970 drivers/net/ethernet/freescale/gianfar_ethtool.c be16_to_cpu(mask->psrc), mask 972 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_attribute(value->tos, mask->tos, RQFCR_PID_TOS, tab); mask 977 drivers/net/ethernet/freescale/gianfar_ethtool.c struct ethtool_usrip4_spec *mask, mask 981 drivers/net/ethernet/freescale/gianfar_ethtool.c be32_to_cpu(mask->ip4src), mask 984 drivers/net/ethernet/freescale/gianfar_ethtool.c be32_to_cpu(mask->ip4dst), mask 986 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_attribute(value->tos, mask->tos, RQFCR_PID_TOS, tab); mask 987 drivers/net/ethernet/freescale/gianfar_ethtool.c gfar_set_attribute(value->proto, mask->proto, RQFCR_PID_L4P, tab); mask 989 drivers/net/ethernet/freescale/gianfar_ethtool.c be32_to_cpu(mask->l4_4_bytes), mask 995 drivers/net/ethernet/freescale/gianfar_ethtool.c static void gfar_set_ether(struct ethhdr *value, struct ethhdr *mask, mask 1002 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!is_broadcast_ether_addr(mask->h_source)) { mask 1003 drivers/net/ethernet/freescale/gianfar_ethtool.c if (is_zero_ether_addr(mask->h_source)) { mask 1007 drivers/net/ethernet/freescale/gianfar_ethtool.c upper_temp_mask = mask->h_source[0] << 16 | mask 1008 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_source[1] << 8 | mask 1009 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_source[2]; mask 1010 drivers/net/ethernet/freescale/gianfar_ethtool.c lower_temp_mask = mask->h_source[3] << 16 | mask 1011 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_source[4] << 8 | mask 1012 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_source[5]; mask 1026 drivers/net/ethernet/freescale/gianfar_ethtool.c if (!is_broadcast_ether_addr(mask->h_dest)) { mask 1029 drivers/net/ethernet/freescale/gianfar_ethtool.c is_zero_ether_addr(mask->h_dest))) { mask 1032 drivers/net/ethernet/freescale/gianfar_ethtool.c if (is_zero_ether_addr(mask->h_dest)) { mask 1036 drivers/net/ethernet/freescale/gianfar_ethtool.c upper_temp_mask = mask->h_dest[0] << 16 | mask 1037 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_dest[1] << 8 | mask 1038 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_dest[2]; mask 1039 drivers/net/ethernet/freescale/gianfar_ethtool.c lower_temp_mask = mask->h_dest[3] << 16 | mask 1040 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_dest[4] << 8 | mask 1041 drivers/net/ethernet/freescale/gianfar_ethtool.c mask->h_dest[5]; mask 1058 drivers/net/ethernet/freescale/gianfar_ethtool.c be16_to_cpu(mask->h_proto), mask 73 drivers/net/ethernet/google/gve/gve.h u32 mask; /* masks the cnt and fill_cnt to the size of the ring */ mask 128 drivers/net/ethernet/google/gve/gve.h u32 mask; /* masks req and done down to queue size */ mask 40 drivers/net/ethernet/google/gve/gve_rx.c slots = rx->mask + 1; mask 67 drivers/net/ethernet/google/gve/gve_rx.c slots = rx->mask + 1; mask 114 drivers/net/ethernet/google/gve/gve_rx.c rx->mask = slots - 1; mask 159 drivers/net/ethernet/google/gve/gve_rx.c rx->mask = slots - 1; mask 371 drivers/net/ethernet/google/gve/gve_rx.c next_idx = rx->cnt & rx->mask; mask 387 drivers/net/ethernet/google/gve/gve_rx.c u32 idx = cnt & rx->mask; mask 405 drivers/net/ethernet/google/gve/gve_rx.c idx = cnt & rx->mask; mask 153 drivers/net/ethernet/google/gve/gve_tx.c slots = tx->mask + 1; mask 196 drivers/net/ethernet/google/gve/gve_tx.c tx->mask = slots - 1; mask 282 drivers/net/ethernet/google/gve/gve_tx.c return tx->mask + 1 - (tx->req - tx->done); mask 414 drivers/net/ethernet/google/gve/gve_tx.c u32 idx = tx->req & tx->mask; mask 456 drivers/net/ethernet/google/gve/gve_tx.c next_idx = (tx->req + 1 + i - payload_iov) & tx->mask; mask 521 drivers/net/ethernet/google/gve/gve_tx.c idx = tx->done & tx->mask; mask 699 drivers/net/ethernet/hisilicon/hns/hnae.h #define hnae_set_field(origin, mask, shift, val) \ mask 701 drivers/net/ethernet/hisilicon/hns/hnae.h (origin) &= (~(mask)); \ mask 702 drivers/net/ethernet/hisilicon/hns/hnae.h (origin) |= ((val) << (shift)) & (mask); \ mask 708 drivers/net/ethernet/hisilicon/hns/hnae.h #define hnae_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) mask 392 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c static void hns_ae_toggle_ring_irq(struct hnae_ring *ring, u32 mask) mask 401 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c hns_rcb_int_ctrl_hw(ring->q, flag, mask); mask 404 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c static void hns_aev2_toggle_ring_irq(struct hnae_ring *ring, u32 mask) mask 413 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c hns_rcbv2_int_ctrl_hw(ring->q, flag, mask); mask 1724 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c u8 port_num, u8 *mask, u8 *addr) mask 1727 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c memset(mask, 0xff, ETH_ALEN); mask 1729 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN); mask 142 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask) mask 144 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c u32 int_mask_en = !!mask; mask 172 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask) mask 174 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c u32 int_mask_en = !!mask; mask 129 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask); mask 1043 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_field(origin, mask, shift, val) \ mask 1045 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h (origin) &= (~(mask)); \ mask 1046 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h (origin) |= (((val) << (shift)) & (mask)); \ mask 1052 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline void dsaf_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, mask 1057 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_field(origin, mask, shift, val); mask 1061 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_set_dev_field(dev, reg, mask, shift, val) \ mask 1062 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val)) mask 1067 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) mask 1072 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h static inline u32 dsaf_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, mask 1078 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h return dsaf_get_field(origin, mask, shift); mask 1081 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h #define dsaf_get_dev_field(dev, reg, mask, shift) \ mask 1082 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift)) mask 1234 drivers/net/ethernet/hisilicon/hns/hns_enet.c struct hnae_ring *ring, cpumask_t *mask) mask 1254 drivers/net/ethernet/hisilicon/hns/hns_enet.c cpumask_clear(mask); mask 1255 drivers/net/ethernet/hisilicon/hns/hns_enet.c cpumask_set_cpu(cpu, mask); mask 1306 drivers/net/ethernet/hisilicon/hns/hns_enet.c rd->ring, &rd->mask); mask 1310 drivers/net/ethernet/hisilicon/hns/hns_enet.c &rd->mask); mask 36 drivers/net/ethernet/hisilicon/hns/hns_enet.h cpumask_t mask; /* affinity mask */ mask 653 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define hnae3_set_field(origin, mask, shift, val) \ mask 655 drivers/net/ethernet/hisilicon/hns3/hnae3.h (origin) &= (~(mask)); \ mask 656 drivers/net/ethernet/hisilicon/hns3/hnae3.h (origin) |= ((val) << (shift)) & (mask); \ mask 658 drivers/net/ethernet/hisilicon/hns3/hnae3.h #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) mask 929 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h u8 mask; mask 1927 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c unsigned int mask = BIT((unsigned int)i); mask 1929 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->hw_tc_map & mask && mask 1930 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c !(hdev->tm_info.hw_pfc_map & mask)) { mask 1957 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c unsigned int mask = BIT((unsigned int)i); mask 1959 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c if (hdev->hw_tc_map & mask && mask 1960 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c hdev->tm_info.hw_pfc_map & mask) { mask 3052 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c const cpumask_t *mask) mask 3057 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c cpumask_copy(&hdev->affinity_mask, mask); mask 6421 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c req->mask = loop_mode_b; mask 6423 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c req->mask = loop_mode_b; mask 205 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 223 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c linkmode_copy(mask, hdev->hw.mac.supported); mask 224 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c linkmode_and(phydev->supported, phydev->supported, mask); mask 108 drivers/net/ethernet/hisilicon/hns_mdio.c #define mdio_set_field(origin, mask, shift, val) \ mask 110 drivers/net/ethernet/hisilicon/hns_mdio.c (origin) &= (~((mask) << (shift))); \ mask 111 drivers/net/ethernet/hisilicon/hns_mdio.c (origin) |= (((val) & (mask)) << (shift)); \ mask 114 drivers/net/ethernet/hisilicon/hns_mdio.c #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask)) mask 116 drivers/net/ethernet/hisilicon/hns_mdio.c static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift, mask 121 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_set_field(origin, mask, shift, val); mask 125 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \ mask 126 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val)) mask 128 drivers/net/ethernet/hisilicon/hns_mdio.c static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift) mask 133 drivers/net/ethernet/hisilicon/hns_mdio.c return mdio_get_field(origin, mask, shift); mask 136 drivers/net/ethernet/hisilicon/hns_mdio.c #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \ mask 137 drivers/net/ethernet/hisilicon/hns_mdio.c mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift)) mask 61 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c #define SQ_MASKED_IDX(sq, idx) ((idx) & (sq)->wq->mask) mask 62 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.c #define RQ_MASKED_IDX(rq, idx) ((idx) & (rq)->wq->mask) mask 71 drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c #define MASKED_WQE_IDX(wq, idx) ((idx) & (wq)->mask) mask 567 drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c wq->mask = q_depth - 1; mask 671 drivers/net/ethernet/huawei/hinic/hinic_hw_wq.c wq[i].mask = q_depth - 1; mask 47 drivers/net/ethernet/huawei/hinic/hinic_hw_wq.h u16 mask; mask 623 drivers/net/ethernet/huawei/hinic/hinic_tx.c hw_ci = HW_CONS_IDX(sq) & wq->mask; mask 630 drivers/net/ethernet/huawei/hinic/hinic_tx.c (((hw_ci - sw_ci) & wq->mask) * wq->wqebb_size < wqe_size)) mask 119 drivers/net/ethernet/ibm/ehea/ehea.h #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff) mask 121 drivers/net/ethernet/ibm/ehea/ehea.h #define EHEA_BMASK_MASK(mask) \ mask 122 drivers/net/ethernet/ibm/ehea/ehea.h (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff)) mask 124 drivers/net/ethernet/ibm/ehea/ehea.h #define EHEA_BMASK_SET(mask, value) \ mask 125 drivers/net/ethernet/ibm/ehea/ehea.h ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask)) mask 127 drivers/net/ethernet/ibm/ehea/ehea.h #define EHEA_BMASK_GET(mask, value) \ mask 128 drivers/net/ethernet/ibm/ehea/ehea.h (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask))) mask 1345 drivers/net/ethernet/ibm/ehea/ehea_main.c u64 hret, mask; mask 1372 drivers/net/ethernet/ibm/ehea/ehea_main.c mask = EHEA_BMASK_SET(H_PORT_CB0_PRC, 1) mask 1377 drivers/net/ethernet/ibm/ehea/ehea_main.c H_PORT_CB0, mask, cb0); mask 430 drivers/net/ethernet/ibm/emac/core.c int slot, reg, mask; mask 436 drivers/net/ethernet/ibm/emac/core.c mask = EMAC_XAHT_SLOT_TO_MASK(dev, slot); mask 438 drivers/net/ethernet/ibm/emac/core.c gaht_temp[reg] |= mask; mask 654 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u32 mask, u32 write) mask 667 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (read != (write & test[i] & mask)) { mask 670 drivers/net/ethernet/intel/e1000/e1000_ethtool.c reg, read, (write & test[i] & mask)); mask 679 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u32 mask, u32 write) mask 685 drivers/net/ethernet/intel/e1000/e1000_ethtool.c writel(write & mask, address); mask 687 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if ((read & mask) != (write & mask)) { mask 690 drivers/net/ethernet/intel/e1000/e1000_ethtool.c reg, (read & mask), (write & mask)); mask 697 drivers/net/ethernet/intel/e1000/e1000_ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ mask 702 drivers/net/ethernet/intel/e1000/e1000_ethtool.c mask, write)) \ mask 706 drivers/net/ethernet/intel/e1000/e1000_ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ mask 711 drivers/net/ethernet/intel/e1000/e1000_ethtool.c mask, write)) \ mask 827 drivers/net/ethernet/intel/e1000/e1000_ethtool.c u32 mask, i = 0; mask 856 drivers/net/ethernet/intel/e1000/e1000_ethtool.c mask = 1 << i; mask 866 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(IMC, mask); mask 867 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(ICS, mask); mask 871 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (adapter->test_icr & mask) { mask 884 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(IMS, mask); mask 885 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(ICS, mask); mask 889 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (!(adapter->test_icr & mask)) { mask 902 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(IMC, ~mask & 0x00007FFF); mask 903 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(ICS, ~mask & 0x00007FFF); mask 2693 drivers/net/ethernet/intel/e1000/e1000_hw.c u32 mask; mask 2699 drivers/net/ethernet/intel/e1000/e1000_hw.c mask = 0x01; mask 2700 drivers/net/ethernet/intel/e1000/e1000_hw.c mask <<= (count - 1); mask 2707 drivers/net/ethernet/intel/e1000/e1000_hw.c while (mask) { mask 2713 drivers/net/ethernet/intel/e1000/e1000_hw.c if (data & mask) mask 2726 drivers/net/ethernet/intel/e1000/e1000_hw.c mask = mask >> 1; mask 3581 drivers/net/ethernet/intel/e1000/e1000_hw.c u32 mask; mask 3587 drivers/net/ethernet/intel/e1000/e1000_hw.c mask = 0x01 << (count - 1); mask 3603 drivers/net/ethernet/intel/e1000/e1000_hw.c if (data & mask) mask 3614 drivers/net/ethernet/intel/e1000/e1000_hw.c mask = mask >> 1; mask 3616 drivers/net/ethernet/intel/e1000/e1000_hw.c } while (mask); mask 745 drivers/net/ethernet/intel/e1000/e1000_hw.h volatile u32 mask; /* Flexible Filter Mask (RW) */ mask 22 drivers/net/ethernet/intel/e1000e/80003es2lan.c static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); mask 23 drivers/net/ethernet/intel/e1000e/80003es2lan.c static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); mask 180 drivers/net/ethernet/intel/e1000e/80003es2lan.c u16 mask; mask 182 drivers/net/ethernet/intel/e1000e/80003es2lan.c mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; mask 183 drivers/net/ethernet/intel/e1000e/80003es2lan.c return e1000_acquire_swfw_sync_80003es2lan(hw, mask); mask 194 drivers/net/ethernet/intel/e1000e/80003es2lan.c u16 mask; mask 196 drivers/net/ethernet/intel/e1000e/80003es2lan.c mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; mask 197 drivers/net/ethernet/intel/e1000e/80003es2lan.c e1000_release_swfw_sync_80003es2lan(hw, mask); mask 209 drivers/net/ethernet/intel/e1000e/80003es2lan.c u16 mask; mask 211 drivers/net/ethernet/intel/e1000e/80003es2lan.c mask = E1000_SWFW_CSR_SM; mask 213 drivers/net/ethernet/intel/e1000e/80003es2lan.c return e1000_acquire_swfw_sync_80003es2lan(hw, mask); mask 224 drivers/net/ethernet/intel/e1000e/80003es2lan.c u16 mask; mask 226 drivers/net/ethernet/intel/e1000e/80003es2lan.c mask = E1000_SWFW_CSR_SM; mask 228 drivers/net/ethernet/intel/e1000e/80003es2lan.c e1000_release_swfw_sync_80003es2lan(hw, mask); mask 273 drivers/net/ethernet/intel/e1000e/80003es2lan.c static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) mask 276 drivers/net/ethernet/intel/e1000e/80003es2lan.c u32 swmask = mask; mask 277 drivers/net/ethernet/intel/e1000e/80003es2lan.c u32 fwmask = mask << 16; mask 318 drivers/net/ethernet/intel/e1000e/80003es2lan.c static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) mask 326 drivers/net/ethernet/intel/e1000e/80003es2lan.c swfw_sync &= ~mask; mask 495 drivers/net/ethernet/intel/e1000e/80003es2lan.c u32 mask = E1000_NVM_CFG_DONE_PORT_0; mask 498 drivers/net/ethernet/intel/e1000e/80003es2lan.c mask = E1000_NVM_CFG_DONE_PORT_1; mask 501 drivers/net/ethernet/intel/e1000e/80003es2lan.c if (er32(EEMNGCTL) & mask) mask 769 drivers/net/ethernet/intel/e1000e/ethtool.c int reg, int offset, u32 mask, u32 write) mask 779 drivers/net/ethernet/intel/e1000e/ethtool.c if (val != (test[pat] & write & mask)) { mask 782 drivers/net/ethernet/intel/e1000e/ethtool.c (test[pat] & write & mask)); mask 791 drivers/net/ethernet/intel/e1000e/ethtool.c int reg, u32 mask, u32 write) mask 795 drivers/net/ethernet/intel/e1000e/ethtool.c __ew32(&adapter->hw, reg, write & mask); mask 797 drivers/net/ethernet/intel/e1000e/ethtool.c if ((write & mask) != (val & mask)) { mask 799 drivers/net/ethernet/intel/e1000e/ethtool.c reg, (val & mask), (write & mask)); mask 806 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_PATTERN_TEST_ARRAY(reg, offset, mask, write) \ mask 808 drivers/net/ethernet/intel/e1000e/ethtool.c if (reg_pattern_test(adapter, data, reg, offset, mask, write)) \ mask 811 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ mask 812 drivers/net/ethernet/intel/e1000e/ethtool.c REG_PATTERN_TEST_ARRAY(reg, 0, mask, write) mask 814 drivers/net/ethernet/intel/e1000e/ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ mask 816 drivers/net/ethernet/intel/e1000e/ethtool.c if (reg_set_and_check(adapter, data, reg, mask, write)) \ mask 829 drivers/net/ethernet/intel/e1000e/ethtool.c u32 mask; mask 890 drivers/net/ethernet/intel/e1000e/ethtool.c mask = 0x8003FFFF; mask 899 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(18); mask 917 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(30); mask 919 drivers/net/ethernet/intel/e1000e/ethtool.c mask &= ~BIT(30); mask 924 drivers/net/ethernet/intel/e1000e/ethtool.c mask &= 0xFFF4FFFF; mask 927 drivers/net/ethernet/intel/e1000e/ethtool.c mask |= BIT(30); mask 933 drivers/net/ethernet/intel/e1000e/ethtool.c REG_PATTERN_TEST_ARRAY(E1000_RA, ((i << 1) + 1), mask, mask 986 drivers/net/ethernet/intel/e1000e/ethtool.c u32 mask; mask 1022 drivers/net/ethernet/intel/e1000e/ethtool.c mask = BIT(i); mask 1025 drivers/net/ethernet/intel/e1000e/ethtool.c switch (mask) { mask 1046 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(IMC, mask); mask 1047 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(ICS, mask); mask 1051 drivers/net/ethernet/intel/e1000e/ethtool.c if (adapter->test_icr & mask) { mask 1064 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(IMS, mask); mask 1065 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(ICS, mask); mask 1069 drivers/net/ethernet/intel/e1000e/ethtool.c if (!(adapter->test_icr & mask)) { mask 1082 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(IMC, ~mask & 0x00007FFF); mask 1083 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(ICS, ~mask & 0x00007FFF); mask 4445 drivers/net/ethernet/intel/e1000e/netdev.c adapter->cc.mask = CYCLECOUNTER_MASK(64); mask 50 drivers/net/ethernet/intel/e1000e/nvm.c u32 mask; mask 52 drivers/net/ethernet/intel/e1000e/nvm.c mask = BIT(count - 1); mask 59 drivers/net/ethernet/intel/e1000e/nvm.c if (data & mask) mask 70 drivers/net/ethernet/intel/e1000e/nvm.c mask >>= 1; mask 71 drivers/net/ethernet/intel/e1000e/nvm.c } while (mask); mask 1554 drivers/net/ethernet/intel/e1000e/phy.c u16 phy_data, offset, mask; mask 1562 drivers/net/ethernet/intel/e1000e/phy.c mask = M88E1000_PSSR_DOWNSHIFT; mask 1567 drivers/net/ethernet/intel/e1000e/phy.c mask = IGP01E1000_PLHR_SS_DOWNGRADE; mask 1578 drivers/net/ethernet/intel/e1000e/phy.c phy->speed_downgraded = !!(phy_data & mask); mask 1620 drivers/net/ethernet/intel/e1000e/phy.c u16 data, offset, mask; mask 1632 drivers/net/ethernet/intel/e1000e/phy.c mask = IGP01E1000_PHY_POLARITY_MASK; mask 1638 drivers/net/ethernet/intel/e1000e/phy.c mask = IGP01E1000_PSSR_POLARITY_REVERSED; mask 1644 drivers/net/ethernet/intel/e1000e/phy.c phy->cable_polarity = ((data & mask) mask 1661 drivers/net/ethernet/intel/e1000e/phy.c u16 phy_data, offset, mask; mask 1667 drivers/net/ethernet/intel/e1000e/phy.c mask = IFE_PESC_POLARITY_REVERSED; mask 1670 drivers/net/ethernet/intel/e1000e/phy.c mask = IFE_PSC_FORCE_POLARITY; mask 1676 drivers/net/ethernet/intel/e1000e/phy.c phy->cable_polarity = ((phy_data & mask) mask 213 drivers/net/ethernet/intel/fm10k/fm10k.h u16 mask; /* Mask used for feature to ring mapping */ mask 1504 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(pcs - 1)) - 1; mask 1514 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(rss_i - 1)) - 1; mask 1544 drivers/net/ethernet/intel/fm10k/fm10k_main.c f->mask = BIT(fls(rss_i - 1)) - 1; mask 1876 drivers/net/ethernet/intel/fm10k/fm10k_main.c u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1; mask 336 drivers/net/ethernet/intel/fm10k/fm10k_mbx.c u16 end, len, tail, mask; mask 342 drivers/net/ethernet/intel/fm10k/fm10k_mbx.c mask = mbx->mbmem_len - 1; mask 345 drivers/net/ethernet/intel/fm10k/fm10k_mbx.c if (tail > mask) mask 359 drivers/net/ethernet/intel/fm10k/fm10k_mbx.c tail &= mask; mask 342 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c u16 mask = (~hw->mac.dglort_map) >> FM10K_DGLORTMAP_MASK_SHIFT; mask 357 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c if (mask <= hw->iov.total_vfs) { mask 359 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c interface->glort += mask; mask 360 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c } else if (mask < 64) { mask 361 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c interface->glort_count = (mask + 1) / 2; mask 364 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c interface->glort_count = mask - 63; mask 1528 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); mask 1529 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); mask 1607 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); mask 1608 drivers/net/ethernet/intel/fm10k/fm10k_netdev.c dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); mask 1122 drivers/net/ethernet/intel/fm10k/fm10k_pci.c dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); mask 1123 drivers/net/ethernet/intel/fm10k/fm10k_pci.c dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); mask 1140 drivers/net/ethernet/intel/fm10k/fm10k_pci.c dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); mask 1141 drivers/net/ethernet/intel/fm10k/fm10k_pci.c dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); mask 196 drivers/net/ethernet/intel/fm10k/fm10k_pf.c u32 vlan_table, reg, mask, bit, len; mask 230 drivers/net/ethernet/intel/fm10k/fm10k_pf.c mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; mask 233 drivers/net/ethernet/intel/fm10k/fm10k_pf.c mask &= set ? ~vlan_table : vlan_table; mask 234 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (mask) mask 235 drivers/net/ethernet/intel/fm10k/fm10k_pf.c fm10k_write_reg(hw, reg, vlan_table ^ mask); mask 1646 drivers/net/ethernet/intel/fm10k/fm10k_pf.c u16 glort, mask; mask 1657 drivers/net/ethernet/intel/fm10k/fm10k_pf.c mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); mask 1660 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (!mask || (glort & ~mask)) mask 1664 drivers/net/ethernet/intel/fm10k/fm10k_pf.c if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) mask 601 drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h u8 mask[16]; mask 281 drivers/net/ethernet/intel/i40e/i40e_common.c void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, mask 285 drivers/net/ethernet/intel/i40e/i40e_common.c u32 effective_mask = hw->debug_mask & mask; mask 295 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, mask 301 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, mask 305 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, mask 309 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR, mask 316 drivers/net/ethernet/intel/i40e/i40e_common.c i40e_debug(hw, mask, "AQ CMD Buffer:\n"); mask 1908 drivers/net/ethernet/intel/i40e/i40e_common.c u16 mask, mask 1919 drivers/net/ethernet/intel/i40e/i40e_common.c cmd->event_mask = cpu_to_le16(mask); mask 14 drivers/net/ethernet/intel/i40e/i40e_diag.c u32 reg, u32 mask) mask 25 drivers/net/ethernet/intel/i40e/i40e_diag.c wr32(hw, reg, (pat & mask)); mask 27 drivers/net/ethernet/intel/i40e/i40e_diag.c if ((val & mask) != (pat & mask)) { mask 80 drivers/net/ethernet/intel/i40e/i40e_diag.c u32 reg, mask; mask 100 drivers/net/ethernet/intel/i40e/i40e_diag.c mask = i40e_reg_list[i].mask; mask 104 drivers/net/ethernet/intel/i40e/i40e_diag.c ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); mask 18 drivers/net/ethernet/intel/i40e/i40e_diag.h u32 mask; /* bits that can be tested */ mask 3059 drivers/net/ethernet/intel/i40e/i40e_ethtool.c static int i40e_check_mask(u64 mask, u64 field) mask 3061 drivers/net/ethernet/intel/i40e/i40e_ethtool.c u64 value = mask & field; mask 3093 drivers/net/ethernet/intel/i40e/i40e_ethtool.c u64 value, mask; mask 3103 drivers/net/ethernet/intel/i40e/i40e_ethtool.c mask = be64_to_cpu(*((__be64 *)fsp->m_ext.data)); mask 3109 drivers/net/ethernet/intel/i40e/i40e_ethtool.c valid = i40e_check_mask(mask, I40E_USERDEF_FLEX_FILTER); mask 3133 drivers/net/ethernet/intel/i40e/i40e_ethtool.c u64 value = 0, mask = 0; mask 3138 drivers/net/ethernet/intel/i40e/i40e_ethtool.c mask |= I40E_USERDEF_FLEX_FILTER; mask 3141 drivers/net/ethernet/intel/i40e/i40e_ethtool.c if (value || mask) mask 3145 drivers/net/ethernet/intel/i40e/i40e_ethtool.c *((__be64 *)fsp->m_ext.data) = cpu_to_be64(mask); mask 734 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c u8 src_byte, dest_byte, mask; mask 743 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = (u8)(BIT(ce_info->width) - 1); mask 746 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c src_byte &= mask; mask 749 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask <<= shift_width; mask 757 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c dest_byte &= ~mask; /* get the bits not changing */ mask 774 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c u16 src_word, mask; mask 784 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = BIT(ce_info->width) - 1; mask 790 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c src_word &= mask; mask 793 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask <<= shift_width; mask 801 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ mask 818 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c u32 src_dword, mask; mask 834 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = BIT(ce_info->width) - 1; mask 836 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = ~(u32)0; mask 842 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c src_dword &= mask; mask 845 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask <<= shift_width; mask 853 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ mask 870 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c u64 src_qword, mask; mask 886 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = BIT_ULL(ce_info->width) - 1; mask 888 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask = ~(u64)0; mask 894 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c src_qword &= mask; mask 897 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c mask <<= shift_width; mask 905 drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ mask 3742 drivers/net/ethernet/intel/i40e/i40e_main.c const cpumask_t *mask) mask 3747 drivers/net/ethernet/intel/i40e/i40e_main.c cpumask_copy(&q_vector->affinity_mask, mask); mask 6701 drivers/net/ethernet/intel/i40e/i40e_main.c u64 mask; mask 6742 drivers/net/ethernet/intel/i40e/i40e_main.c mask = I40E_PHY_TYPES_BITMASK; mask 6743 drivers/net/ethernet/intel/i40e/i40e_main.c config.phy_type = is_up ? cpu_to_le32((u32)(mask & 0xffffffff)) : 0; mask 6744 drivers/net/ethernet/intel/i40e/i40e_main.c config.phy_type_ext = is_up ? (u8)((mask >> 32) & 0xff) : 0; mask 7770 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->keyid != 0) mask 7781 drivers/net/ethernet/intel/i40e/i40e_main.c n_proto_mask = ntohs(match.mask->n_proto); mask 7797 drivers/net/ethernet/intel/i40e/i40e_main.c if (!is_zero_ether_addr(match.mask->dst)) { mask 7798 drivers/net/ethernet/intel/i40e/i40e_main.c if (is_broadcast_ether_addr(match.mask->dst)) { mask 7802 drivers/net/ethernet/intel/i40e/i40e_main.c match.mask->dst); mask 7807 drivers/net/ethernet/intel/i40e/i40e_main.c if (!is_zero_ether_addr(match.mask->src)) { mask 7808 drivers/net/ethernet/intel/i40e/i40e_main.c if (is_broadcast_ether_addr(match.mask->src)) { mask 7812 drivers/net/ethernet/intel/i40e/i40e_main.c match.mask->src); mask 7824 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->vlan_id) { mask 7825 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->vlan_id == VLAN_VID_MASK) { mask 7830 drivers/net/ethernet/intel/i40e/i40e_main.c match.mask->vlan_id); mask 7849 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->dst) { mask 7850 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->dst == cpu_to_be32(0xffffffff)) { mask 7854 drivers/net/ethernet/intel/i40e/i40e_main.c &match.mask->dst); mask 7859 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->src) { mask 7860 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->src == cpu_to_be32(0xffffffff)) { mask 7864 drivers/net/ethernet/intel/i40e/i40e_main.c &match.mask->src); mask 7891 drivers/net/ethernet/intel/i40e/i40e_main.c if (!ipv6_addr_any(&match.mask->dst) || mask 7892 drivers/net/ethernet/intel/i40e/i40e_main.c !ipv6_addr_any(&match.mask->src)) mask 7905 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->src) { mask 7906 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->src == cpu_to_be16(0xffff)) { mask 7910 drivers/net/ethernet/intel/i40e/i40e_main.c be16_to_cpu(match.mask->src)); mask 7915 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->dst) { mask 7916 drivers/net/ethernet/intel/i40e/i40e_main.c if (match.mask->dst == cpu_to_be16(0xffff)) { mask 7920 drivers/net/ethernet/intel/i40e/i40e_main.c be16_to_cpu(match.mask->dst)); mask 32 drivers/net/ethernet/intel/i40e/i40e_prototype.h void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, mask 89 drivers/net/ethernet/intel/i40e/i40e_prototype.h i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask, mask 16 drivers/net/ethernet/intel/i40e/i40e_type.h #define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) mask 3128 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c struct virtchnl_l4_spec mask = tc_filter->mask.tcp_spec; mask 3161 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_mac[0] && !mask.dst_ip[0]) { mask 3172 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.vlan_id) { mask 3197 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_mac[0] & data.dst_mac[0]) { mask 3206 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.src_mac[0] & data.src_mac[0]) { mask 3215 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_port & data.dst_port) { mask 3223 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.src_port & data.src_port) { mask 3238 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.vlan_id & data.vlan_id) { mask 3322 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c struct virtchnl_l4_spec mask = vcf->mask.tcp_spec; mask 3355 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter.dst_mac[i] = mask.dst_mac[i] & tcf.dst_mac[i]; mask 3359 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter.src_mac[i] = mask.src_mac[i] & tcf.src_mac[i]; mask 3361 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter.vlan_id = mask.vlan_id & tcf.vlan_id; mask 3362 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter.dst_port = mask.dst_port & tcf.dst_port; mask 3363 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter.src_port = mask.src_port & tcf.src_port; mask 3368 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_ip[0] & tcf.dst_ip[0]) mask 3371 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c else if (mask.src_ip[0] & tcf.dst_ip[0]) mask 3377 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_ip[3] & tcf.dst_ip[3]) mask 3380 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.src_ip[3] & tcf.src_ip[3]) mask 3414 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_port) mask 3417 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_mac[0]) mask 3421 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (cfilter.n_proto == ETH_P_IP && mask.dst_ip[0]) mask 3426 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (cfilter.n_proto == ETH_P_IPV6 && mask.dst_ip[3]) mask 3430 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.vlan_id) mask 3454 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c struct virtchnl_l4_spec mask = vcf->mask.tcp_spec; mask 3489 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter->dst_mac[i] = mask.dst_mac[i] & tcf.dst_mac[i]; mask 3493 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter->src_mac[i] = mask.src_mac[i] & tcf.src_mac[i]; mask 3495 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter->vlan_id = mask.vlan_id & tcf.vlan_id; mask 3496 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter->dst_port = mask.dst_port & tcf.dst_port; mask 3497 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c cfilter->src_port = mask.src_port & tcf.src_port; mask 3502 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_ip[0] & tcf.dst_ip[0]) mask 3505 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c else if (mask.src_ip[0] & tcf.dst_ip[0]) mask 3511 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.dst_ip[3] & tcf.dst_ip[3]) mask 3514 drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c if (mask.src_ip[3] & tcf.src_ip[3]) mask 451 drivers/net/ethernet/intel/i40e/i40e_xsk.c u64 hr, mask; mask 456 drivers/net/ethernet/intel/i40e/i40e_xsk.c mask = rx_ring->xsk_umem->chunk_mask; mask 464 drivers/net/ethernet/intel/i40e/i40e_xsk.c handle &= mask; mask 372 drivers/net/ethernet/intel/iavf/iavf.h void iavf_irq_enable_queues(struct iavf_adapter *adapter, u32 mask); mask 260 drivers/net/ethernet/intel/iavf/iavf_common.c void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc, mask 266 drivers/net/ethernet/intel/iavf/iavf_common.c if ((!(mask & hw->debug_mask)) || !desc) mask 269 drivers/net/ethernet/intel/iavf/iavf_common.c iavf_debug(hw, mask, mask 275 drivers/net/ethernet/intel/iavf/iavf_common.c iavf_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", mask 278 drivers/net/ethernet/intel/iavf/iavf_common.c iavf_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", mask 281 drivers/net/ethernet/intel/iavf/iavf_common.c iavf_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", mask 288 drivers/net/ethernet/intel/iavf/iavf_common.c iavf_debug(hw, mask, "AQ CMD Buffer:\n"); mask 292 drivers/net/ethernet/intel/iavf/iavf_common.c if (hw->debug_mask & mask) { mask 227 drivers/net/ethernet/intel/iavf/iavf_main.c void iavf_irq_enable_queues(struct iavf_adapter *adapter, u32 mask) mask 233 drivers/net/ethernet/intel/iavf/iavf_main.c if (mask & BIT(i - 1)) { mask 388 drivers/net/ethernet/intel/iavf/iavf_main.c const cpumask_t *mask) mask 393 drivers/net/ethernet/intel/iavf/iavf_main.c cpumask_copy(&q_vector->affinity_mask, mask); mask 2719 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->keyid != 0) mask 2728 drivers/net/ethernet/intel/iavf/iavf_main.c n_proto_mask = ntohs(match.mask->n_proto); mask 2754 drivers/net/ethernet/intel/iavf/iavf_main.c if (!is_zero_ether_addr(match.mask->dst)) { mask 2755 drivers/net/ethernet/intel/iavf/iavf_main.c if (is_broadcast_ether_addr(match.mask->dst)) { mask 2759 drivers/net/ethernet/intel/iavf/iavf_main.c match.mask->dst); mask 2764 drivers/net/ethernet/intel/iavf/iavf_main.c if (!is_zero_ether_addr(match.mask->src)) { mask 2765 drivers/net/ethernet/intel/iavf/iavf_main.c if (is_broadcast_ether_addr(match.mask->src)) { mask 2769 drivers/net/ethernet/intel/iavf/iavf_main.c match.mask->src); mask 2779 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.dst_mac[i] |= 0xff; mask 2789 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.src_mac[i] |= 0xff; mask 2799 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->vlan_id) { mask 2800 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->vlan_id == VLAN_VID_MASK) { mask 2804 drivers/net/ethernet/intel/iavf/iavf_main.c match.mask->vlan_id); mask 2808 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.vlan_id |= cpu_to_be16(0xffff); mask 2823 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->dst) { mask 2824 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->dst == cpu_to_be32(0xffffffff)) { mask 2828 drivers/net/ethernet/intel/iavf/iavf_main.c be32_to_cpu(match.mask->dst)); mask 2833 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->src) { mask 2834 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->src == cpu_to_be32(0xffffffff)) { mask 2838 drivers/net/ethernet/intel/iavf/iavf_main.c be32_to_cpu(match.mask->dst)); mask 2848 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.dst_ip[0] |= cpu_to_be32(0xffffffff); mask 2852 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.src_ip[0] |= cpu_to_be32(0xffffffff); mask 2863 drivers/net/ethernet/intel/iavf/iavf_main.c if (ipv6_addr_any(&match.mask->dst)) { mask 2878 drivers/net/ethernet/intel/iavf/iavf_main.c if (!ipv6_addr_any(&match.mask->dst) || mask 2879 drivers/net/ethernet/intel/iavf/iavf_main.c !ipv6_addr_any(&match.mask->src)) mask 2883 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.dst_ip[i] |= cpu_to_be32(0xffffffff); mask 2887 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.src_ip[i] |= cpu_to_be32(0xffffffff); mask 2895 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->src) { mask 2896 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->src == cpu_to_be16(0xffff)) { mask 2900 drivers/net/ethernet/intel/iavf/iavf_main.c be16_to_cpu(match.mask->src)); mask 2905 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->dst) { mask 2906 drivers/net/ethernet/intel/iavf/iavf_main.c if (match.mask->dst == cpu_to_be16(0xffff)) { mask 2910 drivers/net/ethernet/intel/iavf/iavf_main.c be16_to_cpu(match.mask->dst)); mask 2915 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.dst_port |= cpu_to_be16(0xffff); mask 2920 drivers/net/ethernet/intel/iavf/iavf_main.c vf->mask.tcp_spec.src_port |= cpu_to_be16(0xffff); mask 2984 drivers/net/ethernet/intel/iavf/iavf_main.c memset(&filter->f.mask.tcp_spec, 0, sizeof(struct virtchnl_l4_spec)); mask 33 drivers/net/ethernet/intel/iavf/iavf_prototype.h void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, mask 16 drivers/net/ethernet/intel/iavf/iavf_type.h #define IAVF_MASK(mask, shift) ((u32)(mask) << (shift)) mask 1203 drivers/net/ethernet/intel/ice/ice_common.c ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf, mask 1210 drivers/net/ethernet/intel/ice/ice_common.c if (!(mask & hw->debug_mask)) mask 1219 drivers/net/ethernet/intel/ice/ice_common.c ice_debug(hw, mask, mask 1224 drivers/net/ethernet/intel/ice/ice_common.c ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", mask 1227 drivers/net/ethernet/intel/ice/ice_common.c ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", mask 1230 drivers/net/ethernet/intel/ice/ice_common.c ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", mask 1234 drivers/net/ethernet/intel/ice/ice_common.c ice_debug(hw, mask, "Buffer:\n"); mask 1238 drivers/net/ethernet/intel/ice/ice_common.c ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); mask 2498 drivers/net/ethernet/intel/ice/ice_common.c ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, mask 2510 drivers/net/ethernet/intel/ice/ice_common.c cmd->event_mask = cpu_to_le16(mask); mask 2939 drivers/net/ethernet/intel/ice/ice_common.c u8 src_byte, dest_byte, mask; mask 2948 drivers/net/ethernet/intel/ice/ice_common.c mask = (u8)(BIT(ce_info->width) - 1); mask 2951 drivers/net/ethernet/intel/ice/ice_common.c src_byte &= mask; mask 2954 drivers/net/ethernet/intel/ice/ice_common.c mask <<= shift_width; mask 2962 drivers/net/ethernet/intel/ice/ice_common.c dest_byte &= ~mask; /* get the bits not changing */ mask 2978 drivers/net/ethernet/intel/ice/ice_common.c u16 src_word, mask; mask 2988 drivers/net/ethernet/intel/ice/ice_common.c mask = BIT(ce_info->width) - 1; mask 2994 drivers/net/ethernet/intel/ice/ice_common.c src_word &= mask; mask 2997 drivers/net/ethernet/intel/ice/ice_common.c mask <<= shift_width; mask 3005 drivers/net/ethernet/intel/ice/ice_common.c dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ mask 3021 drivers/net/ethernet/intel/ice/ice_common.c u32 src_dword, mask; mask 3037 drivers/net/ethernet/intel/ice/ice_common.c mask = BIT(ce_info->width) - 1; mask 3039 drivers/net/ethernet/intel/ice/ice_common.c mask = (u32)~0; mask 3045 drivers/net/ethernet/intel/ice/ice_common.c src_dword &= mask; mask 3048 drivers/net/ethernet/intel/ice/ice_common.c mask <<= shift_width; mask 3056 drivers/net/ethernet/intel/ice/ice_common.c dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ mask 3072 drivers/net/ethernet/intel/ice/ice_common.c u64 src_qword, mask; mask 3088 drivers/net/ethernet/intel/ice/ice_common.c mask = BIT_ULL(ce_info->width) - 1; mask 3090 drivers/net/ethernet/intel/ice/ice_common.c mask = (u64)~0; mask 3096 drivers/net/ethernet/intel/ice/ice_common.c src_qword &= mask; mask 3099 drivers/net/ethernet/intel/ice/ice_common.c mask <<= shift_width; mask 3107 drivers/net/ethernet/intel/ice/ice_common.c dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ mask 16 drivers/net/ethernet/intel/ice/ice_common.h ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len); mask 112 drivers/net/ethernet/intel/ice/ice_common.h ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, mask 342 drivers/net/ethernet/intel/ice/ice_ethtool.c static int ice_reg_pattern_test(struct ice_hw *hw, u32 reg, u32 mask) mask 354 drivers/net/ethernet/intel/ice/ice_ethtool.c u32 pattern = patterns[i] & mask; mask 393 drivers/net/ethernet/intel/ice/ice_ethtool.c u32 mask; mask 412 drivers/net/ethernet/intel/ice/ice_ethtool.c u32 mask = ice_reg_list[i].mask; mask 417 drivers/net/ethernet/intel/ice/ice_ethtool.c if (ice_reg_pattern_test(hw, reg, mask)) mask 907 drivers/net/ethernet/intel/ice/ice_main.c u16 mask; mask 909 drivers/net/ethernet/intel/ice/ice_main.c mask = ~((u16)(ICE_AQ_LINK_EVENT_UPDOWN | ICE_AQ_LINK_EVENT_MEDIA_NA | mask 912 drivers/net/ethernet/intel/ice/ice_main.c if (ice_aq_set_event_mask(pi->hw, pi->lport, mask, NULL)) { mask 1563 drivers/net/ethernet/intel/ice/ice_main.c const cpumask_t *mask) mask 1568 drivers/net/ethernet/intel/ice/ice_main.c cpumask_copy(&q_vector->affinity_mask, mask); mask 720 drivers/net/ethernet/intel/igb/e1000_82575.c u16 mask = E1000_SWFW_PHY0_SM; mask 723 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY1_SM; mask 725 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY2_SM; mask 727 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY3_SM; mask 729 drivers/net/ethernet/intel/igb/e1000_82575.c return hw->mac.ops.acquire_swfw_sync(hw, mask); mask 741 drivers/net/ethernet/intel/igb/e1000_82575.c u16 mask = E1000_SWFW_PHY0_SM; mask 744 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY1_SM; mask 746 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY2_SM; mask 748 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_SWFW_PHY3_SM; mask 750 drivers/net/ethernet/intel/igb/e1000_82575.c hw->mac.ops.release_swfw_sync(hw, mask); mask 1157 drivers/net/ethernet/intel/igb/e1000_82575.c static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) mask 1160 drivers/net/ethernet/intel/igb/e1000_82575.c u32 swmask = mask; mask 1161 drivers/net/ethernet/intel/igb/e1000_82575.c u32 fwmask = mask << 16; mask 1206 drivers/net/ethernet/intel/igb/e1000_82575.c static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) mask 1214 drivers/net/ethernet/intel/igb/e1000_82575.c swfw_sync &= ~mask; mask 1233 drivers/net/ethernet/intel/igb/e1000_82575.c u32 mask = E1000_NVM_CFG_DONE_PORT_0; mask 1236 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_NVM_CFG_DONE_PORT_1; mask 1238 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_NVM_CFG_DONE_PORT_2; mask 1240 drivers/net/ethernet/intel/igb/e1000_82575.c mask = E1000_NVM_CFG_DONE_PORT_3; mask 1243 drivers/net/ethernet/intel/igb/e1000_82575.c if (rd32(E1000_EEMNGCTL) & mask) mask 117 drivers/net/ethernet/intel/igb/e1000_i210.c s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask) mask 120 drivers/net/ethernet/intel/igb/e1000_i210.c u32 swmask = mask; mask 121 drivers/net/ethernet/intel/igb/e1000_i210.c u32 fwmask = mask << 16; mask 163 drivers/net/ethernet/intel/igb/e1000_i210.c void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask) mask 171 drivers/net/ethernet/intel/igb/e1000_i210.c swfw_sync &= ~mask; mask 899 drivers/net/ethernet/intel/igb/e1000_i210.c u32 mask = E1000_NVM_CFG_DONE_PORT_0; mask 902 drivers/net/ethernet/intel/igb/e1000_i210.c if (rd32(E1000_EEMNGCTL_I210) & mask) mask 7 drivers/net/ethernet/intel/igb/e1000_i210.h s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask); mask 8 drivers/net/ethernet/intel/igb/e1000_i210.h void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask); mask 241 drivers/net/ethernet/intel/igb/e1000_mbx.c static s32 igb_check_for_bit_pf(struct e1000_hw *hw, u32 mask) mask 246 drivers/net/ethernet/intel/igb/e1000_mbx.c if (mbvficr & mask) { mask 248 drivers/net/ethernet/intel/igb/e1000_mbx.c wr32(E1000_MBVFICR, mask); mask 54 drivers/net/ethernet/intel/igb/e1000_nvm.c u32 mask; mask 56 drivers/net/ethernet/intel/igb/e1000_nvm.c mask = 1u << (count - 1); mask 63 drivers/net/ethernet/intel/igb/e1000_nvm.c if (data & mask) mask 74 drivers/net/ethernet/intel/igb/e1000_nvm.c mask >>= 1; mask 75 drivers/net/ethernet/intel/igb/e1000_nvm.c } while (mask); mask 1481 drivers/net/ethernet/intel/igb/e1000_phy.c u16 phy_data, offset, mask; mask 1488 drivers/net/ethernet/intel/igb/e1000_phy.c mask = M88E1000_PSSR_DOWNSHIFT; mask 1494 drivers/net/ethernet/intel/igb/e1000_phy.c mask = IGP01E1000_PLHR_SS_DOWNGRADE; mask 1506 drivers/net/ethernet/intel/igb/e1000_phy.c phy->speed_downgraded = (phy_data & mask) ? true : false; mask 1549 drivers/net/ethernet/intel/igb/e1000_phy.c u16 data, offset, mask; mask 1561 drivers/net/ethernet/intel/igb/e1000_phy.c mask = IGP01E1000_PHY_POLARITY_MASK; mask 1567 drivers/net/ethernet/intel/igb/e1000_phy.c mask = IGP01E1000_PSSR_POLARITY_REVERSED; mask 1573 drivers/net/ethernet/intel/igb/e1000_phy.c phy->cable_polarity = (data & mask) mask 991 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 mask; mask 1204 drivers/net/ethernet/intel/igb/igb_ethtool.c int reg, u32 mask, u32 write) mask 1212 drivers/net/ethernet/intel/igb/igb_ethtool.c val = rd32(reg) & mask; mask 1213 drivers/net/ethernet/intel/igb/igb_ethtool.c if (val != (_test[pat] & write & mask)) { mask 1216 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, val, (_test[pat] & write & mask)); mask 1226 drivers/net/ethernet/intel/igb/igb_ethtool.c int reg, u32 mask, u32 write) mask 1231 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(reg, write & mask); mask 1233 drivers/net/ethernet/intel/igb/igb_ethtool.c if ((write & mask) != (val & mask)) { mask 1236 drivers/net/ethernet/intel/igb/igb_ethtool.c reg, (val & mask), (write & mask)); mask 1244 drivers/net/ethernet/intel/igb/igb_ethtool.c #define REG_PATTERN_TEST(reg, mask, write) \ mask 1246 drivers/net/ethernet/intel/igb/igb_ethtool.c if (reg_pattern_test(adapter, data, reg, mask, write)) \ mask 1250 drivers/net/ethernet/intel/igb/igb_ethtool.c #define REG_SET_AND_CHECK(reg, mask, write) \ mask 1252 drivers/net/ethernet/intel/igb/igb_ethtool.c if (reg_set_and_check(adapter, data, reg, mask, write)) \ mask 1316 drivers/net/ethernet/intel/igb/igb_ethtool.c test->mask, mask 1322 drivers/net/ethernet/intel/igb/igb_ethtool.c test->mask, mask 1332 drivers/net/ethernet/intel/igb/igb_ethtool.c test->mask, mask 1337 drivers/net/ethernet/intel/igb/igb_ethtool.c test->mask, mask 1342 drivers/net/ethernet/intel/igb/igb_ethtool.c test->mask, mask 1392 drivers/net/ethernet/intel/igb/igb_ethtool.c u32 mask, ics_mask, i = 0, shared_int = true; mask 1452 drivers/net/ethernet/intel/igb/igb_ethtool.c mask = BIT(i); mask 1454 drivers/net/ethernet/intel/igb/igb_ethtool.c if (!(mask & ics_mask)) mask 1469 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_IMC, mask); mask 1470 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_ICS, mask); mask 1474 drivers/net/ethernet/intel/igb/igb_ethtool.c if (adapter->test_icr & mask) { mask 1491 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_IMS, mask); mask 1492 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_ICS, mask); mask 1496 drivers/net/ethernet/intel/igb/igb_ethtool.c if (!(adapter->test_icr & mask)) { mask 1513 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_IMC, ~mask); mask 1514 drivers/net/ethernet/intel/igb/igb_ethtool.c wr32(E1000_ICS, ~mask); mask 1518 drivers/net/ethernet/intel/igb/igb_ethtool.c if (adapter->test_icr & mask) { mask 2605 drivers/net/ethernet/intel/igb/igb_main.c if (!is_zero_ether_addr(match.mask->dst)) { mask 2606 drivers/net/ethernet/intel/igb/igb_main.c if (!is_broadcast_ether_addr(match.mask->dst)) { mask 2616 drivers/net/ethernet/intel/igb/igb_main.c if (!is_zero_ether_addr(match.mask->src)) { mask 2617 drivers/net/ethernet/intel/igb/igb_main.c if (!is_broadcast_ether_addr(match.mask->src)) { mask 2632 drivers/net/ethernet/intel/igb/igb_main.c if (match.mask->n_proto) { mask 2633 drivers/net/ethernet/intel/igb/igb_main.c if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { mask 2647 drivers/net/ethernet/intel/igb/igb_main.c if (match.mask->vlan_priority) { mask 2648 drivers/net/ethernet/intel/igb/igb_main.c if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { mask 395 drivers/net/ethernet/intel/igb/igb_ptp.c static const u32 mask[IGB_N_SDP] = { mask 403 drivers/net/ethernet/intel/igb/igb_ptp.c *ptr &= ~mask[pin]; mask 405 drivers/net/ethernet/intel/igb/igb_ptp.c *ptr |= mask[pin]; mask 1195 drivers/net/ethernet/intel/igb/igb_ptp.c adapter->cc.mask = CYCLECOUNTER_MASK(64); mask 1214 drivers/net/ethernet/intel/igb/igb_ptp.c adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580); mask 137 drivers/net/ethernet/intel/igbvf/mbx.c static s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask) mask 142 drivers/net/ethernet/intel/igbvf/mbx.c if (v2p_mailbox & mask) mask 145 drivers/net/ethernet/intel/igbvf/mbx.c hw->dev_spec.vf.v2p_mailbox &= ~mask; mask 256 drivers/net/ethernet/intel/igc/igc_base.c u16 mask = IGC_SWFW_PHY0_SM; mask 258 drivers/net/ethernet/intel/igc/igc_base.c return hw->mac.ops.acquire_swfw_sync(hw, mask); mask 270 drivers/net/ethernet/intel/igc/igc_base.c u16 mask = IGC_SWFW_PHY0_SM; mask 272 drivers/net/ethernet/intel/igc/igc_base.c hw->mac.ops.release_swfw_sync(hw, mask); mask 37 drivers/net/ethernet/intel/igc/igc_hw.h s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); mask 38 drivers/net/ethernet/intel/igc/igc_hw.h void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); mask 109 drivers/net/ethernet/intel/igc/igc_i225.c s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) mask 112 drivers/net/ethernet/intel/igc/igc_i225.c u32 fwmask = mask << 16; mask 113 drivers/net/ethernet/intel/igc/igc_i225.c u32 swmask = mask; mask 155 drivers/net/ethernet/intel/igc/igc_i225.c void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) mask 163 drivers/net/ethernet/intel/igc/igc_i225.c swfw_sync &= ~mask; mask 7 drivers/net/ethernet/intel/igc/igc_i225.h s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask); mask 8 drivers/net/ethernet/intel/igc/igc_i225.h void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask); mask 71 drivers/net/ethernet/intel/ixgb/ixgb_ee.c u32 mask; mask 77 drivers/net/ethernet/intel/ixgb/ixgb_ee.c mask = 0x01 << (count - 1); mask 88 drivers/net/ethernet/intel/ixgb/ixgb_ee.c if (data & mask) mask 99 drivers/net/ethernet/intel/ixgb/ixgb_ee.c mask = mask >> 1; mask 101 drivers/net/ethernet/intel/ixgb/ixgb_ee.c } while (mask); mask 386 drivers/net/ethernet/intel/ixgbe/ixgbe.h u16 mask; /* Mask used for feature to ring mapping */ mask 907 drivers/net/ethernet/intel/ixgbe/ixgbe.h union ixgbe_atr_input *mask); mask 1493 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c u32 mask = ntohs(input_mask->formatted.dst_port); mask 1495 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT; mask 1496 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c mask |= ntohs(input_mask->formatted.src_port); mask 1497 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1); mask 1498 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2); mask 1499 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4); mask 1500 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8); mask 1543 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 mask; mask 1552 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mask = BIT(count - 1); mask 1562 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c if (data & mask) mask 1579 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c mask = mask >> 1; mask 2589 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) mask 2592 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 swmask = mask; mask 2593 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 fwmask = mask << 5; mask 2634 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) mask 2637 drivers/net/ethernet/intel/ixgbe/ixgbe_common.c u32 swmask = mask; mask 64 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask); mask 65 drivers/net/ethernet/intel/ixgbe/ixgbe_common.h void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask); mask 739 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c u8 mask = BIT_PFC | BIT_PG_TX | BIT_PG_RX | BIT_APP_UPCHG; mask 741 drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.c adapter->dcb_set_bitmap |= mask; mask 1342 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 mask; mask 1416 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 mask, u32 write) mask 1430 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if (val != (test_pattern[pat] & write & mask)) { mask 1432 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, val, (test_pattern[pat] & write & mask)); mask 1443 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 mask, u32 write) mask 1452 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_write_reg(&adapter->hw, reg, write & mask); mask 1454 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if ((write & mask) != (val & mask)) { mask 1456 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c reg, (val & mask), (write & mask)); mask 1525 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->mask, mask 1531 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->mask, mask 1542 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->mask, mask 1548 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->mask, mask 1554 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c test->mask, mask 1591 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u32 mask, i = 0, shared_int = true; mask 1626 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask = BIT(i); mask 1638 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ~mask & 0x00007FFF); mask 1640 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ~mask & 0x00007FFF); mask 1644 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if (adapter->test_icr & mask) { mask 1657 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); mask 1658 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); mask 1662 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c if (!(adapter->test_icr & mask)) { mask 1677 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ~mask & 0x00007FFF); mask 1679 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ~mask & 0x00007FFF); mask 2413 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c union ixgbe_atr_input *mask = &adapter->fdir_mask; mask 2455 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port; mask 2457 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port; mask 2459 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0]; mask 2461 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0]; mask 2463 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_ext.vlan_tci = mask->formatted.vlan_id; mask 2465 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_ext.vlan_etype = mask->formatted.flex_bytes; mask 2467 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool); mask 2681 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c union ixgbe_atr_input mask; mask 2722 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c memset(&mask, 0, sizeof(union ixgbe_atr_input)); mask 2734 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | mask 2738 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; mask 2742 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src; mask 2744 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst; mask 2746 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc; mask 2748 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst; mask 2753 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.vm_pool = mask 2756 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.vlan_id = fsp->m_ext.vlan_tci; mask 2759 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c mask.formatted.flex_bytes = fsp->m_ext.vlan_etype; mask 2772 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); mask 2773 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c err = ixgbe_fdir_set_input_mask_82599(hw, &mask); mask 2778 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { mask 2784 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); mask 2978 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c u16 rss_m = adapter->ring_feature[RING_F_RSS].mask; mask 3099 drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c max_combined = adapter->ring_feature[RING_F_RSS].mask + 1; mask 36 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); mask 39 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c if ((reg_idx & ~vmdq->mask) >= tcs) { mask 41 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); mask 47 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); mask 50 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c if ((reg_idx & ~vmdq->mask) >= tcs) mask 51 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); mask 66 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 71 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; mask 79 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; mask 198 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); mask 206 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c if ((reg_idx & ~vmdq->mask) >= rss->indices) { mask 208 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); mask 222 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); mask 230 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c if ((reg_idx & rss->mask) >= rss->indices) mask 231 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); mask 365 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; mask 372 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; mask 455 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c f->mask = rss_m; mask 541 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; mask 545 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c adapter->ring_feature[RING_F_RSS].mask = rss_m; mask 632 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c f->mask = IXGBE_RSS_16Q_MASK; mask 634 drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c f->mask = IXGBE_RSS_64Q_MASK; mask 904 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 mask; mask 908 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (IXGBE_EIMS_RTX_QUEUE & qmask); mask 909 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); mask 916 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask & 0xFFFFFFFF); mask 917 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); mask 918 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask >> 32); mask 919 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); mask 2440 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 mask; mask 2483 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = IXGBE_EIMS_ENABLE_MASK; mask 2484 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask &= ~(IXGBE_EIMS_OTHER | mask 2488 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); mask 2931 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 mask; mask 2936 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (IXGBE_EIMS_RTX_QUEUE & qmask); mask 2937 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); mask 2944 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask & 0xFFFFFFFF); mask 2945 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask) mask 2946 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); mask 2947 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask >> 32); mask 2948 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask) mask 2949 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); mask 2960 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 mask; mask 2965 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (IXGBE_EIMS_RTX_QUEUE & qmask); mask 2966 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); mask 2973 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask & 0xFFFFFFFF); mask 2974 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask) mask 2975 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); mask 2976 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = (qmask >> 32); mask 2977 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask) mask 2978 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); mask 2996 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); mask 3000 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask &= ~IXGBE_EIMS_LSC; mask 3005 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_GPI_SDP0(hw); mask 3011 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_TS; mask 3017 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_GPI_SDP1(hw); mask 3020 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_GPI_SDP1(hw); mask 3021 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_GPI_SDP2(hw); mask 3030 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); mask 3032 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EICR_GPI_SDP0_X540; mask 3033 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_ECC; mask 3034 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_MAILBOX; mask 3042 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask |= IXGBE_EIMS_FLOW_DIR; mask 3044 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); mask 3588 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c else if (adapter->ring_feature[RING_F_VMDQ].mask == mask 3715 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u16 mask = adapter->ring_feature[RING_F_RSS].mask; mask 3721 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c reg_idx &= mask; mask 3946 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (adapter->ring_feature[RING_F_RSS].mask) mask 3956 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c else if (adapter->ring_feature[RING_F_VMDQ].mask == mask 4237 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c switch (adapter->ring_feature[RING_F_VMDQ].mask) { mask 5012 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c static void ixgbe_clear_udp_tunnel_port(struct ixgbe_adapter *adapter, u32 mask) mask 5021 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c vxlanctrl = IXGBE_READ_REG(hw, IXGBE_VXLANCTRL) & ~mask; mask 5024 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask & IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK) mask 5027 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (mask & IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK) mask 5570 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c switch (adapter->ring_feature[RING_F_VMDQ].mask) { mask 7561 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 9208 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c kfree(jump->mask); mask 9289 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); mask 9353 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c union ixgbe_atr_input *mask, mask 9365 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c m = cls->knode.sel->keys[i].mask; mask 9369 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c field_ptr[j].val(input, mask, (__force u32)val, mask 9381 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c nexthdr->mask == mask 9382 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c (__force u32)cls->knode.sel->keys[i].mask) mask 9395 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | mask 9399 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; mask 9412 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c union ixgbe_atr_input *mask = NULL; mask 9498 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = kzalloc(sizeof(*mask), GFP_KERNEL); mask 9499 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (!mask) { mask 9504 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c jump->mask = mask; mask 9507 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c err = ixgbe_clsu32_build_input(input, mask, cls, mask 9514 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c kfree(mask); mask 9525 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c mask = kzalloc(sizeof(*mask), GFP_KERNEL); mask 9526 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (!mask) { mask 9535 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if ((adapter->jump_tables[uhtid])->mask) mask 9536 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c memcpy(mask, (adapter->jump_tables[uhtid])->mask, mask 9537 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c sizeof(*mask)); mask 9553 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); mask 9567 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); mask 9568 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c err = ixgbe_fdir_set_input_mask_82599(hw, mask); mask 9571 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { mask 9576 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); mask 9586 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c kfree(mask); mask 9591 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c kfree(mask); mask 11266 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c kfree(adapter->jump_tables[i]->mask); mask 211 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c static s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index) mask 215 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c if (mbvficr & mask) { mask 216 drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.c IXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask); mask 13 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h union ixgbe_atr_input *mask, mask 21 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h union ixgbe_atr_input *mask; mask 29 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h union ixgbe_atr_input *mask, mask 33 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h mask->formatted.src_ip[0] = (__force __be32)m; mask 38 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h union ixgbe_atr_input *mask, mask 42 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h mask->formatted.dst_ip[0] = (__force __be32)m; mask 55 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h union ixgbe_atr_input *mask, mask 59 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h mask->formatted.src_port = (__force __be16)(m & 0xffff); mask 61 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h mask->formatted.dst_port = (__force __be16)(m >> 16); mask 86 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h u32 mask; mask 93 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h .off = 8, .val = 0x600, .mask = 0xff00, .jump = ixgbe_tcp_fields}, mask 95 drivers/net/ethernet/intel/ixgbe/ixgbe_model.h .off = 8, .val = 0x1100, .mask = 0xff00, .jump = ixgbe_udp_fields}, mask 1228 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c cc.mask = CLOCKSOURCE_MASK(64); mask 588 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 mask; mask 618 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c mask = BIT(vid % 32); mask 622 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c if (vfta & mask) mask 623 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid / 32), vfta ^ mask); mask 699 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 809 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 833 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 1051 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c msgbuf[IXGBE_VF_TX_QUEUES] = __ALIGN_MASK(1, ~vmdq->mask); mask 1052 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c msgbuf[IXGBE_VF_RX_QUEUES] = __ALIGN_MASK(1, ~vmdq->mask); mask 1556 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); mask 555 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) mask 557 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; mask 558 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; mask 569 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c if (mask & IXGBE_GSSR_SW_MNG_SM) mask 641 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) mask 643 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); mask 646 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c if (mask & IXGBE_GSSR_I2C_MASK) mask 647 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c swmask |= mask & IXGBE_GSSR_I2C_MASK; mask 16 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.h s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask); mask 17 drivers/net/ethernet/intel/ixgbe/ixgbe_x540.h void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask); mask 855 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; mask 863 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = hw->mac.ops.acquire_swfw_sync(hw, mask); mask 912 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c hw->mac.ops.release_swfw_sync(hw, mask); mask 1083 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; mask 1097 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = hw->mac.ops.acquire_swfw_sync(hw, mask); mask 1108 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c hw->mac.ops.release_swfw_sync(hw, mask); mask 3662 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) mask 3666 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c status = ixgbe_acquire_swfw_sync_X540(hw, mask); mask 3670 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (mask & IXGBE_GSSR_I2C_MASK) mask 3683 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) mask 3685 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (mask & IXGBE_GSSR_I2C_MASK) mask 3688 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c ixgbe_release_swfw_sync_X540(hw, mask); mask 3698 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) mask 3700 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; mask 3710 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (!(mask & IXGBE_GSSR_TOKEN_SM)) mask 3733 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) mask 3735 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; mask 3737 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (mask & IXGBE_GSSR_TOKEN_SM) mask 3758 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; mask 3761 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (hw->mac.ops.acquire_swfw_sync(hw, mask)) mask 3766 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c hw->mac.ops.release_swfw_sync(hw, mask); mask 3784 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; mask 3787 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c if (hw->mac.ops.acquire_swfw_sync(hw, mask)) mask 3791 drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c hw->mac.ops.release_swfw_sync(hw, mask); mask 230 drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c u64 hr, mask; mask 235 drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c mask = rx_ring->xsk_umem->chunk_mask; mask 243 drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c handle &= mask; mask 569 drivers/net/ethernet/intel/ixgbevf/ethtool.c u32 mask; mask 609 drivers/net/ethernet/intel/ixgbevf/ethtool.c int reg, u32 mask, u32 write) mask 622 drivers/net/ethernet/intel/ixgbevf/ethtool.c if (val != (register_test_patterns[pat] & write & mask)) { mask 626 drivers/net/ethernet/intel/ixgbevf/ethtool.c register_test_patterns[pat] & write & mask); mask 637 drivers/net/ethernet/intel/ixgbevf/ethtool.c int reg, u32 mask, u32 write) mask 646 drivers/net/ethernet/intel/ixgbevf/ethtool.c ixgbe_write_reg(&adapter->hw, reg, write & mask); mask 648 drivers/net/ethernet/intel/ixgbevf/ethtool.c if ((write & mask) != (val & mask)) { mask 650 drivers/net/ethernet/intel/ixgbevf/ethtool.c reg, (val & mask), write & mask); mask 683 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->mask, mask 689 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->mask, mask 700 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->mask, mask 706 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->mask, mask 712 drivers/net/ethernet/intel/ixgbevf/ethtool.c test->mask, mask 132 drivers/net/ethernet/intel/ixgbevf/mbx.c static s32 ixgbevf_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask) mask 137 drivers/net/ethernet/intel/ixgbevf/mbx.c if (v2p_mailbox & mask) mask 140 drivers/net/ethernet/intel/ixgbevf/mbx.c hw->mbx.v2p_mailbox &= ~mask; mask 298 drivers/net/ethernet/intel/ixgbevf/vf.c u32 mask = 0; mask 349 drivers/net/ethernet/intel/ixgbevf/vf.c mask = 0x1; mask 353 drivers/net/ethernet/intel/ixgbevf/vf.c reta[i * 16 + j] = (hw_reta[i] >> (2 * j)) & mask; mask 125 drivers/net/ethernet/jme.c const u32 *mask, u32 crc, int fnr) mask 145 drivers/net/ethernet/jme.c jwrite32(jme, JME_WFODP, mask[i]); mask 214 drivers/net/ethernet/jme.c static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0}; mask 250 drivers/net/ethernet/jme.c jme_setup_wakeup_frame(jme, mask, crc, i); mask 1058 drivers/net/ethernet/jme.c int i, j, ccnt, desccnt, mask = jme->rx_ring_mask; mask 1097 drivers/net/ethernet/jme.c j = (j + 1) & (mask); mask 1104 drivers/net/ethernet/jme.c i = (i + desccnt) & (mask); mask 1426 drivers/net/ethernet/jme.c int i, j, cnt = 0, max, err, mask; mask 1440 drivers/net/ethernet/jme.c mask = jme->tx_ring_mask; mask 1455 drivers/net/ethernet/jme.c ttxbi = txbi + ((i + j) & (mask)); mask 1456 drivers/net/ethernet/jme.c txdesc[(i + j) & (mask)].dw[0] = 0; mask 1486 drivers/net/ethernet/jme.c i = (i + ctxbi->nr_desc) & mask; mask 1950 drivers/net/ethernet/jme.c int idx, nr_alloc, mask = jme->tx_ring_mask; mask 1960 drivers/net/ethernet/jme.c txring->next_to_use = (txring->next_to_use + nr_alloc) & mask; mask 2008 drivers/net/ethernet/jme.c int mask = jme->tx_ring_mask; mask 2012 drivers/net/ethernet/jme.c ctxbi = txbi + ((startidx + j + 2) & (mask)); mask 2031 drivers/net/ethernet/jme.c int mask = jme->tx_ring_mask; mask 2038 drivers/net/ethernet/jme.c ctxdesc = txdesc + ((idx + i + 2) & (mask)); mask 2039 drivers/net/ethernet/jme.c ctxbi = txbi + ((idx + i + 2) & (mask)); mask 2051 drivers/net/ethernet/jme.c ctxdesc = txdesc + ((idx + 1) & (mask)); mask 2052 drivers/net/ethernet/jme.c ctxbi = txbi + ((idx + 1) & (mask)); mask 459 drivers/net/ethernet/marvell/mv643xx_eth.c u8 mask = 1 << rxq->index; mask 461 drivers/net/ethernet/marvell/mv643xx_eth.c wrlp(mp, RXQ_COMMAND, mask << 8); mask 462 drivers/net/ethernet/marvell/mv643xx_eth.c while (rdlp(mp, RXQ_COMMAND) & mask) mask 485 drivers/net/ethernet/marvell/mv643xx_eth.c u8 mask = 1 << txq->index; mask 487 drivers/net/ethernet/marvell/mv643xx_eth.c wrlp(mp, TXQ_COMMAND, mask << 8); mask 488 drivers/net/ethernet/marvell/mv643xx_eth.c while (rdlp(mp, TXQ_COMMAND) & mask) mask 3380 drivers/net/ethernet/marvell/mvneta.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 3393 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, Autoneg); mask 3394 drivers/net/ethernet/marvell/mvneta.c phylink_set_port_modes(mask); mask 3397 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, Pause); mask 3401 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 1000baseT_Full); mask 3402 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 1000baseX_Full); mask 3405 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 2500baseT_Full); mask 3406 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 2500baseX_Full); mask 3411 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 10baseT_Half); mask 3412 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 10baseT_Full); mask 3413 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 100baseT_Half); mask 3414 drivers/net/ethernet/marvell/mvneta.c phylink_set(mask, 100baseT_Full); mask 3417 drivers/net/ethernet/marvell/mvneta.c bitmap_and(supported, supported, mask, mask 3419 drivers/net/ethernet/marvell/mvneta.c bitmap_and(state->advertising, state->advertising, mask, mask 61 drivers/net/ethernet/marvell/mvneta_bm.c static inline void mvneta_bm_config_set(struct mvneta_bm *priv, u32 mask) mask 66 drivers/net/ethernet/marvell/mvneta_bm.c val |= mask; mask 70 drivers/net/ethernet/marvell/mvneta_bm.c static inline void mvneta_bm_config_clear(struct mvneta_bm *priv, u32 mask) mask 75 drivers/net/ethernet/marvell/mvneta_bm.c val &= ~mask; mask 262 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) mask 263 drivers/net/ethernet/marvell/mvpp2/mvpp2.h #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) mask 850 drivers/net/ethernet/marvell/mvpp2/mvpp2.h struct cpumask *mask; mask 1246 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c if (match.mask->vlan_id) { mask 1250 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c rule->c2_tcam_mask |= ((u64)match.mask->vlan_id) << offs; mask 1255 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c if (match.mask->vlan_priority) { mask 1263 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c rule->c2_tcam_mask |= ((u64)match.mask->vlan_priority) << mask 1267 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c if (match.mask->vlan_dei) mask 1280 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c if (match.mask->src) { mask 1284 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c rule->c2_tcam_mask |= ((u64)ntohs(match.mask->src)) << offs; mask 1288 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c if (match.mask->dst) { mask 1292 drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c rule->c2_tcam_mask |= ((u64)ntohs(match.mask->dst)) << offs; mask 389 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c unsigned char data[8], mask[8]; mask 395 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c mvpp2_prs_tcam_data_byte_get(&pe, i, &data[i], &mask[i]); mask 397 drivers/net/ethernet/marvell/mvpp2/mvpp2_debugfs.c seq_printf(s, "%*phN %*phN\n", 8, data, 8, mask); mask 592 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, mask; mask 599 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mask = MVPP21_RXQ_POOL_LONG_MASK; mask 601 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mask = MVPP22_RXQ_POOL_LONG_MASK; mask 604 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~mask; mask 605 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; mask 613 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c u32 val, mask; mask 620 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mask = MVPP21_RXQ_POOL_SHORT_MASK; mask 622 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mask = MVPP22_RXQ_POOL_SHORT_MASK; mask 625 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val &= ~mask; mask 626 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; mask 1090 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) mask 1098 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (mask) mask 3556 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); mask 3557 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c if (!qv->mask) { mask 3575 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c cpumask_set_cpu(cpu, qv->mask); mask 3578 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c irq_set_affinity_hint(qv->irq, qv->mask); mask 3588 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c kfree(qv->mask); mask 3589 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c qv->mask = NULL; mask 3604 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c kfree(qv->mask); mask 3605 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c qv->mask = NULL; mask 4753 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 4773 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, Autoneg); mask 4774 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set_port_modes(mask); mask 4775 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, Pause); mask 4776 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, Asym_Pause); mask 4783 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseT_Full); mask 4784 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseCR_Full); mask 4785 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseSR_Full); mask 4786 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseLR_Full); mask 4787 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseLRM_Full); mask 4788 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseER_Full); mask 4789 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10000baseKR_Full); mask 4797 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10baseT_Half); mask 4798 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 10baseT_Full); mask 4799 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 100baseT_Half); mask 4800 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 100baseT_Full); mask 4804 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 1000baseT_Full); mask 4805 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 1000baseX_Full); mask 4806 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 2500baseT_Full); mask 4807 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c phylink_set(mask, 2500baseX_Full); mask 4813 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); mask 4814 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c bitmap_and(state->advertising, state->advertising, mask, mask 225 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int bits, unsigned int mask) mask 230 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (!(mask & BIT(i))) mask 253 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int bits, unsigned int mask) mask 258 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (!(mask & BIT(i))) mask 939 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c int mask, tid; mask 958 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mask = MVPP2_PRS_IPV4_BC_MASK; mask 959 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); mask 960 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); mask 961 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); mask 962 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); mask 1909 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c static int mvpp2_prs_vid_range_find(struct mvpp2_port *port, u16 vid, u16 mask) mask 1931 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (rvid != vid || rmask != mask) mask 1945 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned int mask = 0xfff, reg_val, shift; mask 1953 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c tid = mvpp2_prs_vid_range_find(port, vid, mask); mask 2164 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c const u8 *da, unsigned char *mask) mask 2171 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (tcam_mask != mask[index]) mask 2174 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) mask 2184 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned char *mask, int udf_type) mask 2202 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c if (mvpp2_prs_mac_range_equals(&pe, da, mask) && mask 2213 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; mask 2222 drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c tid = mvpp2_prs_mac_da_range_find(priv, BIT(port->id), da, mask, mask 131 drivers/net/ethernet/marvell/octeontx2/af/npc.h u8 mask; mask 62 drivers/net/ethernet/marvell/octeontx2/af/rvu.c int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) mask 71 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (zero && !(reg_val & mask)) mask 73 drivers/net/ethernet/marvell/octeontx2/af/rvu.c if (!zero && (reg_val & mask)) mask 318 drivers/net/ethernet/marvell/octeontx2/af/rvu.h int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); mask 460 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c void *ctx, *mask; mask 550 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c mask = aq->res->base + 256; mask 555 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy(mask, &req->rq_mask, mask 558 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy(mask, &req->sq_mask, mask 561 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy(mask, &req->cq_mask, mask 564 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy(mask, &req->rss_mask, mask 567 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c memcpy(mask, &req->mce_mask, mask 65 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c void *ctx, *mask; mask 102 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c mask = aq->res->base + 256; mask 108 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c memcpy(mask, &req->aura_mask, mask 112 drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c memcpy(mask, &req->pool_mask, mask 870 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c action0.var_len_mask = kpuaction->mask; mask 27 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c u64 mask; mask 63 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c reg &= map->mask; mask 46 drivers/net/ethernet/mediatek/mtk_eth_path.c u32 val, mask, set; mask 50 drivers/net/ethernet/mediatek/mtk_eth_path.c mask = ~(u32)MTK_MUX_TO_ESW; mask 54 drivers/net/ethernet/mediatek/mtk_eth_path.c mask = ~(u32)MTK_MUX_TO_ESW; mask 64 drivers/net/ethernet/mediatek/mtk_eth_path.c val = (val & mask) | set; mask 68 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) mask 73 drivers/net/ethernet/mediatek/mtk_eth_soc.c val &= ~mask; mask 457 drivers/net/ethernet/mediatek/mtk_eth_soc.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 473 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set_port_modes(mask); mask 474 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, Autoneg); mask 478 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Full); mask 482 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseX_Full); mask 483 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 2500baseX_Full); mask 490 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Half); mask 493 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Full); mask 494 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseX_Full); mask 501 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 10baseT_Half); mask 502 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 10baseT_Full); mask 503 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 100baseT_Half); mask 504 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 100baseT_Full); mask 510 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Full); mask 511 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseX_Full); mask 512 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 2500baseX_Full); mask 515 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Full); mask 516 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Half); mask 517 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseX_Full); mask 520 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Full); mask 521 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, 1000baseT_Half); mask 525 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, Pause); mask 526 drivers/net/ethernet/mediatek/mtk_eth_soc.c phylink_set(mask, Asym_Pause); mask 528 drivers/net/ethernet/mediatek/mtk_eth_soc.c linkmode_and(supported, supported, mask); mask 529 drivers/net/ethernet/mediatek/mtk_eth_soc.c linkmode_and(state->advertising, state->advertising, mask); mask 590 drivers/net/ethernet/mediatek/mtk_eth_soc.c static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) mask 597 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); mask 601 drivers/net/ethernet/mediatek/mtk_eth_soc.c static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) mask 608 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val | mask, eth->tx_int_mask_reg); mask 612 drivers/net/ethernet/mediatek/mtk_eth_soc.c static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) mask 619 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); mask 623 drivers/net/ethernet/mediatek/mtk_eth_soc.c static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) mask 630 drivers/net/ethernet/mediatek/mtk_eth_soc.c mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); mask 1470 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 status, mask; mask 1480 drivers/net/ethernet/mediatek/mtk_eth_soc.c mask = mtk_r32(eth, eth->tx_int_mask_reg); mask 1483 drivers/net/ethernet/mediatek/mtk_eth_soc.c tx_done, status, mask); mask 1502 drivers/net/ethernet/mediatek/mtk_eth_soc.c u32 status, mask; mask 1514 drivers/net/ethernet/mediatek/mtk_eth_soc.c mask = mtk_r32(eth, MTK_PDMA_INT_MASK); mask 1517 drivers/net/ethernet/mediatek/mtk_eth_soc.c rx_done, status, mask); mask 53 drivers/net/ethernet/mellanox/mlx4/alloc.c & bitmap->mask; mask 123 drivers/net/ethernet/mellanox/mlx4/alloc.c & bitmap->mask; mask 166 drivers/net/ethernet/mellanox/mlx4/alloc.c & bitmap->mask; mask 173 drivers/net/ethernet/mellanox/mlx4/alloc.c int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, mask 183 drivers/net/ethernet/mellanox/mlx4/alloc.c bitmap->mask = mask; mask 206 drivers/net/ethernet/mellanox/mlx4/alloc.c u32 mask; mask 235 drivers/net/ethernet/mellanox/mlx4/alloc.c zones->mask = 0; mask 248 drivers/net/ethernet/mellanox/mlx4/alloc.c u32 mask = mlx4_bitmap_masked_value(bitmap, (u32)-1); mask 266 drivers/net/ethernet/mellanox/mlx4/alloc.c if (zone_alloc->mask < mask) mask 267 drivers/net/ethernet/mellanox/mlx4/alloc.c zone_alloc->mask = mask; mask 306 drivers/net/ethernet/mellanox/mlx4/alloc.c u32 mask = 0; mask 312 drivers/net/ethernet/mellanox/mlx4/alloc.c if (mask < cur_mask) mask 313 drivers/net/ethernet/mellanox/mlx4/alloc.c mask = cur_mask; mask 315 drivers/net/ethernet/mellanox/mlx4/alloc.c zone_alloc->mask = mask; mask 492 drivers/net/ethernet/mellanox/mlx4/alloc.c u32 mobj = (obj - zone->offset) & zones->mask; mask 47 drivers/net/ethernet/mellanox/mlx4/en_clock.c return mlx4_read_clock(dev) & tc->mask; mask 279 drivers/net/ethernet/mellanox/mlx4/en_clock.c mdev->cycles.mask = CLOCKSOURCE_MASK(48); mask 233 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c u64 mask; mask 240 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : mask 243 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c if (!(caps->flags & mask)) { mask 272 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c u64 mask; mask 277 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 : mask 280 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c if (!(priv->mdev->dev->caps.flags & mask)) mask 550 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c static void ptys2ethtool_update_supported_port(unsigned long *mask, mask 558 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c __set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); mask 565 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mask); mask 572 drivers/net/ethernet/mellanox/mlx4/en_ethtool.c __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mask); mask 138 drivers/net/ethernet/mellanox/mlx4/icm.c gfp_t mask; mask 182 drivers/net/ethernet/mellanox/mlx4/icm.c mask = gfp_mask; mask 184 drivers/net/ethernet/mellanox/mlx4/icm.c mask &= ~__GFP_DIRECT_RECLAIM; mask 189 drivers/net/ethernet/mellanox/mlx4/icm.c cur_order, mask); mask 192 drivers/net/ethernet/mellanox/mlx4/icm.c cur_order, mask, mask 244 drivers/net/ethernet/mellanox/mlx4/mlx4.h u32 mask; mask 945 drivers/net/ethernet/mellanox/mlx4/mlx4.h int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, mask 39 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define MASK_VAL(type, spec, name, mask, val, fld) \ mask 41 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c {.m = MLX5_GET(spec, mask, fld),\ mask 43 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define MASK_VAL_BE(type, spec, name, mask, val, fld) \ mask 45 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c {.m = MLX5_GET_BE(type, spec, mask, fld),\ mask 49 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c #define GET_MASK_VAL(name, type, mask, val, fld) \ mask 50 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c (name.m = MLX5_GET(type, mask, fld), \ mask 64 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c const u32 *mask, const u32 *value) mask 67 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MASK_VAL(type, fte_match_set_lyr_2_4, name, mask, value, fld) mask 69 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c .m = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16) << 16 | mask 70 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0), mask 74 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c .m = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_47_16) << 16 | mask 75 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_15_0), mask 87 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MASK_VAL_BE(type, fte_match_set_lyr_2_4, name, mask, value, fld) mask 108 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask, mask 112 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask, mask 155 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c const u32 *mask, const u32 *value) mask 158 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MASK_VAL(type, fte_match_set_misc, name, mask, value, fld) mask 164 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c .m = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.hi) << 8 | mask 165 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.lo), mask 119 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h __entry->mask_enable = fg->mask.match_criteria_enable; mask 122 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fg->mask.match_criteria, mask 127 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fg->mask.match_criteria, mask 132 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &fg->mask.match_criteria, mask 207 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h __entry->mask_enable = __entry->fg->mask.match_criteria_enable; mask 212 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &__entry->fg->mask.match_criteria, mask 217 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &__entry->fg->mask.match_criteria, mask 222 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.h &__entry->fg->mask.match_criteria, mask 484 drivers/net/ethernet/mellanox/mlx5/core/en.h u32 mask; mask 532 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c if (memchr_inv(&enc_ports.mask->dst, 0xff, mask 533 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c sizeof(enc_ports.mask->dst))) { mask 547 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c ntohs(enc_ports.mask->dst)); mask 557 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c ntohs(enc_ports.mask->src)); mask 140 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c if (!enc_keyid.mask->keyid) mask 149 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c MLX5_SET(fte_match_set_misc, misc_c, geneve_vni, be32_to_cpu(enc_keyid.mask->keyid)); mask 179 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c if (memchr_inv(&enc_opts.mask->data, 0, sizeof(enc_opts.mask->data)) && mask 199 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c if (enc_opts.mask->len && mask 223 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c MLX5_SET(fte_match_set_misc, misc_c, geneve_opt_len, enc_opts.mask->len / 4); mask 228 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_geneve.c option_mask = (struct geneve_opt *)&enc_opts.mask->data[0]; mask 78 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_gre.c gre_key.key, be32_to_cpu(enc_keyid.mask->keyid)); mask 120 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c if (!enc_keyid.mask->keyid) mask 135 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_vxlan.c be32_to_cpu(enc_keyid.mask->keyid)); mask 206 drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h u32 i = (*fifo->pc)++ & fifo->mask; mask 214 drivers/net/ethernet/mellanox/mlx5/core/en/xdp.h return fifo->xi[(*fifo->cc)++ & fifo->mask]; mask 115 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c static void mask_spec(u8 *mask, u8 *val, size_t size) mask 119 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c for (i = 0; i < size; i++, mask++, val++) mask 120 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c *((u8 *)val) = *((u8 *)mask) & *((u8 *)val); mask 964 drivers/net/ethernet/mellanox/mlx5/core/en_main.c xdpi_fifo->mask = dsegs_per_wq - 1; mask 1687 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ntohl(match.mask->src)); mask 1694 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ntohl(match.mask->dst)); mask 1709 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, mask 1718 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, mask 1737 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->tos & 0x3); mask 1742 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->tos >> 2); mask 1747 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->ttl); mask 1751 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->ttl && mask 1865 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ntohs(match.mask->n_proto)); mask 1869 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->n_proto) mask 1883 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask = &filter_dev_mask; mask 1884 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c memset(match.mask, 0xff, sizeof(*match.mask)); mask 1885 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_priority = 0; mask 1889 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->vlan_id || mask 1890 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_priority || mask 1891 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_tpid) { mask 1905 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_id); mask 1910 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_priority); mask 1929 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->vlan_id || mask 1930 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_priority || mask 1931 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_tpid) { mask 1945 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_id); mask 1949 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->vlan_priority); mask 1963 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->dst); mask 1970 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->src); mask 1975 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (!is_zero_ether_addr(match.mask->src) || mask 1976 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c !is_zero_ether_addr(match.mask->dst)) mask 1987 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->flags & FLOW_DIS_FIRST_FRAG) mask 1990 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) { mask 2011 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->ip_proto); mask 2015 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->ip_proto) mask 2025 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->src, sizeof(match.mask->src)); mask 2031 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->dst, sizeof(match.mask->dst)); mask 2036 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->src || match.mask->dst) mask 2046 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->src, sizeof(match.mask->src)); mask 2053 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c &match.mask->dst, sizeof(match.mask->dst)); mask 2058 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY || mask 2059 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY) mask 2068 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->tos & 0x3); mask 2073 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->tos >> 2); mask 2078 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c match.mask->ttl); mask 2082 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->ttl && mask 2090 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->tos || match.mask->ttl) mask 2103 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c tcp_sport, ntohs(match.mask->src)); mask 2108 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c tcp_dport, ntohs(match.mask->dst)); mask 2115 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c udp_sport, ntohs(match.mask->src)); mask 2120 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c udp_dport, ntohs(match.mask->dst)); mask 2132 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->src || match.mask->dst) mask 2141 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c ntohs(match.mask->flags)); mask 2145 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (match.mask->flags) mask 2225 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset, mask 2233 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c if (*curr_pmask & mask) /* disallow acting twice on the same location */ mask 2236 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c *curr_pmask |= mask; mask 2237 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c *curr_pval |= (val & mask); mask 2347 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c unsigned long mask; mask 2401 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = s_mask; mask 2413 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = a_mask; mask 2427 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask_be32 = *(__be32 *)&mask; mask 2428 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32)); mask 2430 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask_be16 = *(__be16 *)&mask; mask 2431 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16)); mask 2434 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c first = find_first_bit(&mask, field_bsize); mask 2435 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c next_z = find_next_zero_bit(&mask, field_bsize, first); mask 2436 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c last = find_last_bit(&mask, field_bsize); mask 2441 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask); mask 2511 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c u32 mask, val, offset; mask 2528 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = act->mangle.mask; mask 2532 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]); mask 2627 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c u32 mask, offset; mask 2632 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c mask = ~act->mangle.mask; mask 2639 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c (struct ip_ttl_word *)&mask; mask 2648 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c (struct ipv6_hoplimit_word *)&mask; mask 2756 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16), mask 283 drivers/net/ethernet/mellanox/mlx5/core/eq.c if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx)) mask 288 drivers/net/ethernet/mellanox/mlx5/core/eq.c param->mask[i]); mask 507 drivers/net/ethernet/mellanox/mlx5/core/eq.c static void gather_user_async_events(struct mlx5_core_dev *dev, u64 mask[4]) mask 519 drivers/net/ethernet/mellanox/mlx5/core/eq.c mask[i] |= be64_to_cpu(user_affiliated_events[i] | mask 523 drivers/net/ethernet/mellanox/mlx5/core/eq.c static void gather_async_events_mask(struct mlx5_core_dev *dev, u64 mask[4]) mask 560 drivers/net/ethernet/mellanox/mlx5/core/eq.c mask[0] = async_event_mask; mask 563 drivers/net/ethernet/mellanox/mlx5/core/eq.c gather_user_async_events(dev, mask); mask 581 drivers/net/ethernet/mellanox/mlx5/core/eq.c param.mask[0] = 1ull << MLX5_EVENT_TYPE_CMD; mask 600 drivers/net/ethernet/mellanox/mlx5/core/eq.c gather_async_events_mask(dev, param.mask); mask 619 drivers/net/ethernet/mellanox/mlx5/core/eq.c param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_REQUEST; mask 768 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fg->mask.match_criteria_enable, mask 769 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fg->mask.match_criteria, mask 775 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fg->mask.match_criteria_enable, mask 776 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c fg->mask.match_criteria, mask 785 drivers/net/ethernet/mellanox/mlx5/core/fpga/ipsec.c if (mlx5_fs_is_outer_ipv4_flow(mdev, fg->mask.match_criteria, mask 220 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c .key_len = FIELD_SIZEOF(struct mlx5_flow_group, mask), mask 221 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c .key_offset = offsetof(struct mlx5_flow_group, mask), mask 664 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c fg->mask.match_criteria_enable = match_criteria_enable; mask 665 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c memcpy(&fg->mask.match_criteria, match_criteria, mask 666 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c sizeof(fg->mask.match_criteria)); mask 1383 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c fg->mask.match_criteria_enable); mask 1388 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c misc = MLX5_ADDR_OF(fte_match_param, fg->mask.match_criteria, mask 1397 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c memcpy(match_criteria_addr, fg->mask.match_criteria, mask 1398 drivers/net/ethernet/mellanox/mlx5/core/fs_core.c sizeof(fg->mask.match_criteria)); mask 234 drivers/net/ethernet/mellanox/mlx5/core/fs_core.h struct mlx5_flow_group_mask mask; mask 75 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c return mlx5_read_internal_timer(mdev, NULL) & cc->mask; mask 534 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c clock->cycles.mask = CLOCKSOURCE_MASK(41); mask 548 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c overflow_cycles = min(overflow_cycles, div_u64(clock->cycles.mask, 3)); mask 560 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c mdev->clock_info->mask = clock->cycles.mask; mask 97 drivers/net/ethernet/mellanox/mlx5/core/main.c .mask = 0, mask 100 drivers/net/ethernet/mellanox/mlx5/core/main.c .mask = MLX5_PROF_MASK_QP_SIZE, mask 104 drivers/net/ethernet/mellanox/mlx5/core/main.c .mask = MLX5_PROF_MASK_QP_SIZE | mask 550 drivers/net/ethernet/mellanox/mlx5/core/main.c if (prof->mask & MLX5_PROF_MASK_QP_SIZE) mask 62 drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h #define mlx5_core_dbg_mask(__dev, mask, format, ...) \ mask 64 drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h if ((mask) & mlx5_core_debug_mask) \ mask 17 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c cpumask_var_t mask; mask 181 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) { mask 187 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c irq->mask); mask 189 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c irq_set_affinity_hint(irqn, irq->mask)) mask 205 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c free_cpumask_var(irq->mask); mask 241 drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c return irq_table->irq[vecidx].mask; mask 71 drivers/net/ethernet/mellanox/mlx5/core/qp.c u64 mask; mask 73 drivers/net/ethernet/mellanox/mlx5/core/qp.c mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) | mask 82 drivers/net/ethernet/mellanox/mlx5/core/qp.c return mask; mask 87 drivers/net/ethernet/mellanox/mlx5/core/qp.c u64 mask; mask 89 drivers/net/ethernet/mellanox/mlx5/core/qp.c mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) | mask 92 drivers/net/ethernet/mellanox/mlx5/core/qp.c return mask; mask 174 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c struct mlx5dr_match_param mask = {}; mask 194 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mask.outer = matcher->mask.outer; mask 197 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mask.misc = matcher->mask.misc; mask 200 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mask.inner = matcher->mask.inner; mask 203 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mask.misc2 = matcher->mask.misc2; mask 206 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mask.misc3 = matcher->mask.misc3; mask 209 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c &matcher->mask, NULL); mask 220 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_wqe_metadata_set(&mask.misc2)) mask 221 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_general_purpose(&sb[idx++], &mask, inner, rx); mask 223 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_reg_c_0_3_set(&mask.misc2)) mask 224 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_register_0(&sb[idx++], &mask, inner, rx); mask 226 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_reg_c_4_7_set(&mask.misc2)) mask 227 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_register_1(&sb[idx++], &mask, inner, rx); mask 229 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_gvmi_or_qpn_set(&mask.misc) && mask 232 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c ret = mlx5dr_ste_build_src_gvmi_qpn(&sb[idx++], &mask, mask 238 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_smac_set(&mask.outer) && mask 239 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c dr_mask_is_dmac_set(&mask.outer)) { mask 240 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c ret = mlx5dr_ste_build_eth_l2_src_des(&sb[idx++], &mask, mask 246 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_smac_set(&mask.outer)) mask 247 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l2_src(&sb[idx++], &mask, inner, rx); mask 249 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_L2_DST(mask.outer, mask.misc, outer)) mask 250 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l2_dst(&sb[idx++], &mask, inner, rx); mask 253 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_dst_addr_set(&mask.outer)) mask 254 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv6_dst(&sb[idx++], &mask, mask 257 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_src_addr_set(&mask.outer)) mask 258 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv6_src(&sb[idx++], &mask, mask 261 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_ETH_L4_SET(mask.outer, mask.misc, outer)) mask 262 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_ipv6_l3_l4(&sb[idx++], &mask, mask 265 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_ipv4_5_tuple_set(&mask.outer)) mask 266 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv4_5_tuple(&sb[idx++], &mask, mask 269 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_ttl_set(&mask.outer)) mask 270 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv4_misc(&sb[idx++], &mask, mask 274 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_flex_parser_tnl_set(&mask.misc3) && mask 276 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_flex_parser_tnl(&sb[idx++], &mask, mask 279 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_ETH_L4_MISC_SET(mask.misc3, outer)) mask 280 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l4_misc(&sb[idx++], &mask, inner, rx); mask 282 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_FIRST_MPLS_SET(mask.misc2, outer)) mask 283 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_mpls(&sb[idx++], &mask, inner, rx); mask 285 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_FLEX_PARSER_0_SET(mask.misc2)) mask 286 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_flex_parser_0(&sb[idx++], &mask, mask 289 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c misc3 = &mask.misc3; mask 292 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c (dr_mask_is_flex_parser_icmpv6_set(&mask.misc3) && mask 295 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c &mask, &dmn->info.caps, mask 300 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_gre_set(&mask.misc)) mask 301 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_gre(&sb[idx++], &mask, inner, rx); mask 311 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_eth_l2_tnl_set(&mask.misc)) mask 312 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l2_tnl(&sb[idx++], &mask, inner, rx); mask 314 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_smac_set(&mask.inner) && mask 315 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c dr_mask_is_dmac_set(&mask.inner)) { mask 317 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c &mask, inner, rx); mask 322 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_smac_set(&mask.inner)) mask 323 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l2_src(&sb[idx++], &mask, inner, rx); mask 325 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_L2_DST(mask.inner, mask.misc, inner)) mask 326 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l2_dst(&sb[idx++], &mask, inner, rx); mask 329 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_dst_addr_set(&mask.inner)) mask 330 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv6_dst(&sb[idx++], &mask, mask 333 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_src_addr_set(&mask.inner)) mask 334 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv6_src(&sb[idx++], &mask, mask 337 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_ETH_L4_SET(mask.inner, mask.misc, inner)) mask 338 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_ipv6_l3_l4(&sb[idx++], &mask, mask 341 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_ipv4_5_tuple_set(&mask.inner)) mask 342 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv4_5_tuple(&sb[idx++], &mask, mask 345 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (dr_mask_is_ttl_set(&mask.inner)) mask 346 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l3_ipv4_misc(&sb[idx++], &mask, mask 350 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_ETH_L4_MISC_SET(mask.misc3, inner)) mask 351 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_eth_l4_misc(&sb[idx++], &mask, inner, rx); mask 353 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_FIRST_MPLS_SET(mask.misc2, inner)) mask 354 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_mpls(&sb[idx++], &mask, inner, rx); mask 356 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (DR_MASK_IS_FLEX_PARSER_0_SET(mask.misc2)) mask 357 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c mlx5dr_ste_build_flex_parser_0(&sb[idx++], &mask, inner, rx); mask 370 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (((u8 *)&mask)[i] != 0) { mask 593 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c struct mlx5dr_match_parameters *mask) mask 604 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (mask) { mask 605 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c if (mask->match_sz > sizeof(struct mlx5dr_match_param)) { mask 610 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c &matcher->mask, mask); mask 639 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c struct mlx5dr_match_parameters *mask) mask 658 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c ret = dr_matcher_init(matcher, mask); mask 853 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c static bool dr_rule_cmp_value_to_mask(u8 *mask, u8 *value, mask 859 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c if (value[i] & ~mask[i]) { mask 873 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c u8 *mask_p = (u8 *)&matcher->mask; mask 985 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c struct mlx5dr_match_param *mask, mask 991 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c if (mask->misc.source_port) { mask 1002 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c if (mask->misc2.metadata_reg_c_0) { mask 1039 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c if (dr_rule_skip(dmn->type, nic_dmn->ste_type, &matcher->mask, param)) mask 442 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c u8 *formatted_ste, u8 *mask) mask 479 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c mask, DR_STE_SIZE_MASK); mask 52 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c #define DR_STE_SET_MPLS_MASK(lookup_type, mask, in_out, bit_mask) do { \ mask 53 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(lookup_type, mask, mpls0_label, mask, \ mask 55 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(lookup_type, mask, mpls0_s_bos, mask, \ mask 57 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(lookup_type, mask, mpls0_exp, mask, \ mask 59 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(lookup_type, mask, mpls0_ttl, mask, \ mask 63 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c #define DR_STE_SET_MPLS_TAG(lookup_type, mask, in_out, tag) do { \ mask 64 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TAG(lookup_type, tag, mpls0_label, mask, \ mask 66 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TAG(lookup_type, tag, mpls0_s_bos, mask, \ mask 68 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TAG(lookup_type, tag, mpls0_exp, mask, \ mask 70 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TAG(lookup_type, tag, mpls0_ttl, mask, \ mask 107 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c u8 mask[DR_STE_SIZE_MASK]; mask 154 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c memcpy(hw_ste->mask, bit_mask, DR_STE_SIZE_MASK); mask 258 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c memset(&hw_ste->mask, 0, sizeof(hw_ste->mask)); mask 264 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c hw_ste->mask[0] = 0; mask 718 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 722 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->misc.source_port && mask->misc.source_port != 0xffff) { mask 742 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c &matcher->mask, value); mask 776 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 778 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); mask 779 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); mask 781 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->smac_47_16 || mask->smac_15_0) { mask 783 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->smac_47_16 >> 16); mask 785 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->smac_47_16 << 16 | mask->smac_15_0); mask 786 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->smac_47_16 = 0; mask 787 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->smac_15_0 = 0; mask 790 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); mask 791 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); mask 792 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); mask 793 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); mask 795 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->cvlan_tag) { mask 797 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->cvlan_tag = 0; mask 798 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c } else if (mask->svlan_tag) { mask 800 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->svlan_tag = 0; mask 803 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->cvlan_tag || mask->svlan_tag) { mask 811 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c static void dr_ste_copy_mask_misc(char *mask, struct mlx5dr_match_misc *spec) mask 813 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_c_present = MLX5_GET(fte_match_set_misc, mask, gre_c_present); mask 814 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_k_present = MLX5_GET(fte_match_set_misc, mask, gre_k_present); mask 815 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_s_present = MLX5_GET(fte_match_set_misc, mask, gre_s_present); mask 816 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->source_vhca_port = MLX5_GET(fte_match_set_misc, mask, source_vhca_port); mask 817 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->source_sqn = MLX5_GET(fte_match_set_misc, mask, source_sqn); mask 819 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->source_port = MLX5_GET(fte_match_set_misc, mask, source_port); mask 820 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->source_eswitch_owner_vhca_id = MLX5_GET(fte_match_set_misc, mask, mask 823 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->outer_second_prio = MLX5_GET(fte_match_set_misc, mask, outer_second_prio); mask 824 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->outer_second_cfi = MLX5_GET(fte_match_set_misc, mask, outer_second_cfi); mask 825 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->outer_second_vid = MLX5_GET(fte_match_set_misc, mask, outer_second_vid); mask 826 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->inner_second_prio = MLX5_GET(fte_match_set_misc, mask, inner_second_prio); mask 827 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->inner_second_cfi = MLX5_GET(fte_match_set_misc, mask, inner_second_cfi); mask 828 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->inner_second_vid = MLX5_GET(fte_match_set_misc, mask, inner_second_vid); mask 831 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, outer_second_cvlan_tag); mask 833 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, inner_second_cvlan_tag); mask 835 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, outer_second_svlan_tag); mask 837 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, inner_second_svlan_tag); mask 839 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_protocol = MLX5_GET(fte_match_set_misc, mask, gre_protocol); mask 841 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_key_h = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.hi); mask 842 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->gre_key_l = MLX5_GET(fte_match_set_misc, mask, gre_key.nvgre.lo); mask 844 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->vxlan_vni = MLX5_GET(fte_match_set_misc, mask, vxlan_vni); mask 846 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->geneve_vni = MLX5_GET(fte_match_set_misc, mask, geneve_vni); mask 847 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->geneve_oam = MLX5_GET(fte_match_set_misc, mask, geneve_oam); mask 850 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, outer_ipv6_flow_label); mask 853 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, inner_ipv6_flow_label); mask 855 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->geneve_opt_len = MLX5_GET(fte_match_set_misc, mask, geneve_opt_len); mask 857 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc, mask, geneve_protocol_type); mask 859 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->bth_dst_qp = MLX5_GET(fte_match_set_misc, mask, bth_dst_qp); mask 862 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c static void dr_ste_copy_mask_spec(char *mask, struct mlx5dr_match_spec *spec) mask 866 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->smac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_47_16); mask 868 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->smac_15_0 = MLX5_GET(fte_match_set_lyr_2_4, mask, smac_15_0); mask 869 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ethertype = MLX5_GET(fte_match_set_lyr_2_4, mask, ethertype); mask 871 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->dmac_47_16 = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_47_16); mask 873 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->dmac_15_0 = MLX5_GET(fte_match_set_lyr_2_4, mask, dmac_15_0); mask 874 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->first_prio = MLX5_GET(fte_match_set_lyr_2_4, mask, first_prio); mask 875 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->first_cfi = MLX5_GET(fte_match_set_lyr_2_4, mask, first_cfi); mask 876 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->first_vid = MLX5_GET(fte_match_set_lyr_2_4, mask, first_vid); mask 878 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ip_protocol = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_protocol); mask 879 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ip_dscp = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_dscp); mask 880 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ip_ecn = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_ecn); mask 881 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->cvlan_tag = MLX5_GET(fte_match_set_lyr_2_4, mask, cvlan_tag); mask 882 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->svlan_tag = MLX5_GET(fte_match_set_lyr_2_4, mask, svlan_tag); mask 883 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->frag = MLX5_GET(fte_match_set_lyr_2_4, mask, frag); mask 884 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ip_version = MLX5_GET(fte_match_set_lyr_2_4, mask, ip_version); mask 885 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->tcp_flags = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_flags); mask 886 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->tcp_sport = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_sport); mask 887 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->tcp_dport = MLX5_GET(fte_match_set_lyr_2_4, mask, tcp_dport); mask 889 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->ttl_hoplimit = MLX5_GET(fte_match_set_lyr_2_4, mask, ttl_hoplimit); mask 891 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->udp_sport = MLX5_GET(fte_match_set_lyr_2_4, mask, udp_sport); mask 892 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->udp_dport = MLX5_GET(fte_match_set_lyr_2_4, mask, udp_dport); mask 894 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c memcpy(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask, mask 903 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c memcpy(raw_ip, MLX5_ADDR_OF(fte_match_set_lyr_2_4, mask, mask 913 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c static void dr_ste_copy_mask_misc2(char *mask, struct mlx5dr_match_misc2 *spec) mask 916 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_label); mask 918 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_exp); mask 920 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_s_bos); mask 922 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls.mpls_ttl); mask 924 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_label); mask 926 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_exp); mask 928 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_s_bos); mask 930 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, inner_first_mpls.mpls_ttl); mask 932 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_label); mask 934 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_exp); mask 936 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_s_bos); mask 938 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_gre.mpls_ttl); mask 940 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_label); mask 942 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_exp); mask 944 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_s_bos); mask 946 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc2, mask, outer_first_mpls_over_udp.mpls_ttl); mask 947 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_7 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_7); mask 948 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_6 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_6); mask 949 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_5 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_5); mask 950 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_4 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_4); mask 951 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_3 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_3); mask 952 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_2 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_2); mask 953 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_1 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_1); mask 954 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_c_0 = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_c_0); mask 955 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_a = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_a); mask 956 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->metadata_reg_b = MLX5_GET(fte_match_set_misc2, mask, metadata_reg_b); mask 959 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c static void dr_ste_copy_mask_misc3(char *mask, struct mlx5dr_match_misc3 *spec) mask 961 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->inner_tcp_seq_num = MLX5_GET(fte_match_set_misc3, mask, inner_tcp_seq_num); mask 962 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->outer_tcp_seq_num = MLX5_GET(fte_match_set_misc3, mask, outer_tcp_seq_num); mask 963 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->inner_tcp_ack_num = MLX5_GET(fte_match_set_misc3, mask, inner_tcp_ack_num); mask 964 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->outer_tcp_ack_num = MLX5_GET(fte_match_set_misc3, mask, outer_tcp_ack_num); mask 966 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_vni); mask 968 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_next_protocol); mask 970 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc3, mask, outer_vxlan_gpe_flags); mask 971 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->icmpv4_header_data = MLX5_GET(fte_match_set_misc3, mask, icmp_header_data); mask 973 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c MLX5_GET(fte_match_set_misc3, mask, icmpv6_header_data); mask 974 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->icmpv4_type = MLX5_GET(fte_match_set_misc3, mask, icmp_type); mask 975 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->icmpv4_code = MLX5_GET(fte_match_set_misc3, mask, icmp_code); mask 976 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->icmpv6_type = MLX5_GET(fte_match_set_misc3, mask, icmpv6_type); mask 977 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c spec->icmpv6_code = MLX5_GET(fte_match_set_misc3, mask, icmpv6_code); mask 982 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_parameters *mask) mask 985 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c u8 *data = (u8 *)mask->match_buf; mask 990 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->match_sz < sizeof(struct mlx5dr_match_spec)) { mask 991 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c memcpy(tail_param, data, mask->match_sz); mask 994 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c buff = mask->match_buf; mask 1001 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->match_sz < param_location + mask 1004 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->match_sz - param_location); mask 1014 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->match_sz < param_location + mask 1017 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->match_sz - param_location); mask 1027 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->match_sz < param_location + mask 1030 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->match_sz - param_location); mask 1041 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->match_sz < param_location + mask 1044 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->match_sz - param_location); mask 1101 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1106 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c ret = dr_ste_build_eth_l2_src_des_bit_mask(mask, inner, sb->bit_mask); mask 1122 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1124 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_dst, bit_mask, dst_ip_127_96, mask, dst_ip_127_96); mask 1125 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_dst, bit_mask, dst_ip_95_64, mask, dst_ip_95_64); mask 1126 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_dst, bit_mask, dst_ip_63_32, mask, dst_ip_63_32); mask 1127 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_dst, bit_mask, dst_ip_31_0, mask, dst_ip_31_0); mask 1147 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1150 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l3_ipv6_dst_bit_mask(mask, inner, sb->bit_mask); mask 1162 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1164 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_src, bit_mask, src_ip_127_96, mask, src_ip_127_96); mask 1165 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_src, bit_mask, src_ip_95_64, mask, src_ip_95_64); mask 1166 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_src, bit_mask, src_ip_63_32, mask, src_ip_63_32); mask 1167 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv6_src, bit_mask, src_ip_31_0, mask, src_ip_31_0); mask 1187 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1190 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l3_ipv6_src_bit_mask(mask, inner, sb->bit_mask); mask 1203 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1206 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c destination_address, mask, dst_ip_31_0); mask 1208 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c source_address, mask, src_ip_31_0); mask 1210 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c destination_port, mask, tcp_dport); mask 1212 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c destination_port, mask, udp_dport); mask 1214 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c source_port, mask, tcp_sport); mask 1216 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c source_port, mask, udp_sport); mask 1218 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c protocol, mask, ip_protocol); mask 1220 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c fragmented, mask, frag); mask 1222 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dscp, mask, ip_dscp); mask 1224 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c ecn, mask, ip_ecn); mask 1226 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->tcp_flags) { mask 1227 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TCP_FLAGS(eth_l3_ipv4_5_tuple, bit_mask, mask); mask 1228 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->tcp_flags = 0; mask 1260 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1263 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l3_ipv4_5_tuple_bit_mask(mask, inner, sb->bit_mask); mask 1276 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1279 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); mask 1280 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, first_cfi, mask, first_cfi); mask 1281 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, first_priority, mask, first_prio); mask 1282 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, ip_fragmented, mask, frag); mask 1283 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, l3_ethertype, mask, ethertype); mask 1284 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK(eth_l2_src, bit_mask, l3_type, mask, ip_version); mask 1286 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->svlan_tag || mask->cvlan_tag) { mask 1288 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->cvlan_tag = 0; mask 1289 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->svlan_tag = 0; mask 1389 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1391 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); mask 1392 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); mask 1412 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1415 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l2_src_bit_mask(mask, inner, sb->bit_mask); mask 1426 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1428 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_dst, bit_mask, dmac_47_16, mask, dmac_47_16); mask 1429 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_dst, bit_mask, dmac_15_0, mask, dmac_15_0); mask 1449 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1452 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l2_dst_bit_mask(mask, inner, sb->bit_mask); mask 1464 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1467 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, dmac_47_16, mask, dmac_47_16); mask 1468 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, dmac_15_0, mask, dmac_15_0); mask 1469 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); mask 1470 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, first_cfi, mask, first_cfi); mask 1471 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, first_priority, mask, first_prio); mask 1472 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, ip_fragmented, mask, frag); mask 1473 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, l3_ethertype, mask, ethertype); mask 1474 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK(eth_l2_tnl, bit_mask, l3_type, mask, ip_version); mask 1482 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->svlan_tag || mask->cvlan_tag) { mask 1484 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->cvlan_tag = 0; mask 1485 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->svlan_tag = 0; mask 1536 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, bool inner, bool rx) mask 1538 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l2_tnl_bit_mask(mask, inner, sb->bit_mask); mask 1550 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1552 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l3_ipv4_misc, bit_mask, time_to_live, mask, ttl_hoplimit); mask 1569 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1572 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l3_ipv4_misc_bit_mask(mask, inner, sb->bit_mask); mask 1584 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; mask 1586 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, dst_port, mask, tcp_dport); mask 1587 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, src_port, mask, tcp_sport); mask 1588 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, dst_port, mask, udp_dport); mask 1589 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, src_port, mask, udp_sport); mask 1590 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, protocol, mask, ip_protocol); mask 1591 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, fragmented, mask, frag); mask 1592 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, dscp, mask, ip_dscp); mask 1593 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, ecn, mask, ip_ecn); mask 1594 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_MASK_V(eth_l4, bit_mask, ipv6_hop_limit, mask, ttl_hoplimit); mask 1596 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c if (mask->tcp_flags) { mask 1597 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c DR_STE_SET_TCP_FLAGS(eth_l4, bit_mask, mask); mask 1598 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c mask->tcp_flags = 0; mask 1629 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1632 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_ipv6_l3_l4_bit_mask(mask, inner, sb->bit_mask); mask 1684 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1687 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_mpls_bit_mask(mask, inner, sb->bit_mask); mask 1732 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, bool inner, bool rx) mask 1734 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_gre_bit_mask(mask, inner, sb->bit_mask); mask 1812 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1815 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_flex_parser_0_bit_mask(mask, inner, sb->bit_mask); mask 1828 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c static int dr_ste_build_flex_parser_1_bit_mask(struct mlx5dr_match_param *mask, mask 1832 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_misc3 *misc_3_mask = &mask->misc3; mask 1971 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 1977 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c ret = dr_ste_build_flex_parser_1_bit_mask(mask, caps, sb->bit_mask); mask 2016 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2019 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_general_purpose_bit_mask(mask, inner, sb->bit_mask); mask 2066 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2069 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_eth_l4_misc_bit_mask(mask, inner, sb->bit_mask); mask 2130 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2133 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_flex_parser_tnl_bit_mask(mask, inner, sb->bit_mask); mask 2174 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2177 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_register_0_bit_mask(mask, sb->bit_mask); mask 2218 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2221 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c dr_ste_build_register_1_bit_mask(mask, sb->bit_mask); mask 2294 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c struct mlx5dr_match_param *mask, mask 2301 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c sb->vhca_id_valid = mask->misc.source_eswitch_owner_vhca_id; mask 2303 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c ret = dr_ste_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); mask 275 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 282 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 285 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 288 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 291 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 294 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 297 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 300 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 303 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 306 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 309 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 312 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 315 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 318 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 321 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 325 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 328 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 331 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 334 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 337 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param *mask, mask 699 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_param mask; mask 965 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h struct mlx5dr_match_parameters *mask); mask 1041 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h u8 *formatted_ste, u8 *mask); mask 143 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c struct mlx5dr_match_parameters mask; mask 149 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c mask.match_buf = MLX5_ADDR_OF(create_flow_group_in, mask 151 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c mask.match_sz = sizeof(fg->mask.match_criteria); mask 156 drivers/net/ethernet/mellanox/mlx5/core/steering/fs_dr.c &mask); mask 59 drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h struct mlx5dr_match_parameters *mask); mask 146 drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h struct mlx5dr_match_parameters *mask) { return NULL; } mask 360 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c __mlxsw_item_set32(values->storage.mask, storage_item, 0, mask_value); mask 381 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c __mlxsw_item_memcpy_to(values->storage.mask, mask_value, mask 428 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c char *key, char *mask) mask 453 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c values->storage.mask, 0); mask 457 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.c mlxsw_afk->ops->encode_block(mask, i, block_mask); mask 236 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.h char mask[MLXSW_AFK_ELEMENT_STORAGE_SIZE]; mask 250 drivers/net/ethernet/mellanox/mlxsw/core_acl_flex_keys.h char *key, char *mask); mask 65 drivers/net/ethernet/mellanox/mlxsw/item.h u8 mask = GENMASK(item->size.bits - 1, 0) << item->shift; mask 70 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; mask 72 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= ~mask; mask 99 drivers/net/ethernet/mellanox/mlxsw/item.h u16 mask = GENMASK(item->size.bits - 1, 0) << item->shift; mask 104 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; mask 106 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= ~mask; mask 133 drivers/net/ethernet/mellanox/mlxsw/item.h u32 mask = GENMASK(item->size.bits - 1, 0) << item->shift; mask 138 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; mask 140 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= ~mask; mask 166 drivers/net/ethernet/mellanox/mlxsw/item.h u64 mask = GENMASK_ULL(item->size.bits - 1, 0) << item->shift; mask 171 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; mask 173 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= ~mask; mask 248 drivers/net/ethernet/mellanox/mlxsw/item.h u8 mask = GENMASK(item->element_size - 1, 0) << shift; mask 251 drivers/net/ethernet/mellanox/mlxsw/item.h val &= mask; mask 253 drivers/net/ethernet/mellanox/mlxsw/item.h tmp &= ~mask; mask 1038 drivers/net/ethernet/mellanox/mlxsw/pci.c u8 mask = 0; mask 1043 drivers/net/ethernet/mellanox/mlxsw/pci.c mask |= 1; mask 1048 drivers/net/ethernet/mellanox/mlxsw/pci.c mask |= 2; mask 1050 drivers/net/ethernet/mellanox/mlxsw/pci.c mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); mask 2628 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, mask 2733 drivers/net/ethernet/mellanox/mlxsw/reg.h MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); mask 2749 drivers/net/ethernet/mellanox/mlxsw/reg.h char *mask) mask 2760 drivers/net/ethernet/mellanox/mlxsw/reg.h mlxsw_reg_perpt_mask_memcpy_to(payload, mask); mask 2533 drivers/net/ethernet/mellanox/mlxsw/spectrum.c u32 mask; mask 2539 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, mask 2544 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | mask 2550 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, mask 2555 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | mask 2561 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | mask 2569 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, mask 2574 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, mask 2579 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, mask 2584 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, mask 2589 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, mask 2594 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, mask 2599 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, mask 2604 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, mask 2609 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, mask 2614 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, mask 2619 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, mask 2624 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, mask 2629 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, mask 2634 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, mask 2639 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, mask 2675 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) mask 2687 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) mask 2720 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; mask 2733 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; mask 2746 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp1_port_link_mode[i].mask; mask 2936 drivers/net/ethernet/mellanox/mlxsw/spectrum.c u32 mask; mask 2943 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M, mask 2952 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII, mask 2961 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII, mask 2970 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R, mask 2979 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G, mask 2988 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G, mask 2995 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR, mask 3004 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, mask 3012 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR, mask 3019 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4, mask 3026 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2, mask 3033 drivers/net/ethernet/mellanox/mlxsw/spectrum.c .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4, mask 3070 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) && mask 3083 drivers/net/ethernet/mellanox/mlxsw/spectrum.c if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) mask 3133 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; mask 3148 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; mask 3161 drivers/net/ethernet/mellanox/mlxsw/spectrum.c ptys_proto |= mlxsw_sp2_port_link_mode[i].mask; mask 33 drivers/net/ethernet/mellanox/mlxsw/spectrum1_acl_tcam.c const char *mask) mask 33 drivers/net/ethernet/mellanox/mlxsw/spectrum2_acl_tcam.c const char *mask) mask 42 drivers/net/ethernet/mellanox/mlxsw/spectrum2_acl_tcam.c erp_mask = mlxsw_sp_acl_erp_mask_get(aregion, mask, true); mask 406 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c aentry->delta_info.mask, mask 435 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c aentry->delta_info.mask, mask 464 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c aentry->delta_info.mask, mask 478 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c char mask[MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN] = { 0 }; mask 485 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c aentry->ht_key.full_enc_key, mask); mask 487 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c erp_mask = mlxsw_sp_acl_erp_mask_get(aregion, mask, false); mask 500 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_atcam.c aentry->delta_info.mask = mlxsw_sp_acl_erp_delta_mask(delta); mask 51 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_ctcam.c char *mask; mask 64 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_ctcam.c mask = mlxsw_reg_ptce2_mask_data(ptce2_pl); mask 65 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_ctcam.c mlxsw_afk_encode(afk, region->key_info, &rulei->values, key, mask); mask 67 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_ctcam.c err = cregion->ops->entry_insert(cregion, centry, mask); mask 33 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c char mask[MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN]; mask 166 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c struct mlxsw_sp_acl_erp_master_mask *mask) mask 168 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if (mask->count[bit]++ == 0) mask 169 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c __set_bit(bit, mask->bitmap); mask 174 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c struct mlxsw_sp_acl_erp_master_mask *mask) mask 176 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if (--mask->count[bit] == 0) mask 177 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c __clear_bit(bit, mask->bitmap); mask 204 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c bitmap_from_arr32(mask_bitmap, (u32 *) key->mask, mask 231 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c bitmap_from_arr32(mask_bitmap, (u32 *) key->mask, mask 395 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c erp->key.mask); mask 804 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c bitmap_from_arr32(erp->mask_bitmap, (u32 *) key->mask, mask 1004 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c const char *mask, bool ctcam) mask 1010 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c memcpy(key.mask, mask, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); mask 1087 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c u8 mask; mask 1097 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c return delta->mask; mask 1104 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c u8 mask = delta->mask; mask 1107 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if (!mask) mask 1114 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c tmp &= mask; mask 1122 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c u8 mask = delta->mask; mask 1126 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c tmp = mask; mask 1161 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c u16 mask; mask 1166 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if (parent_key->mask[__MASK_IDX(i)] == key->mask[__MASK_IDX(i)]) mask 1181 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c pmask = (unsigned char) parent_key->mask[__MASK_IDX(si)]; mask 1182 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c mask = (unsigned char) key->mask[__MASK_IDX(si)]; mask 1184 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c pmask |= (unsigned char) parent_key->mask[__MASK_IDX(si + 1)] << 8; mask 1185 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c mask |= (unsigned char) key->mask[__MASK_IDX(si + 1)] << 8; mask 1188 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if ((pmask ^ mask) & pmask) mask 1190 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c mask &= ~pmask; mask 1191 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c while (!(mask & (1 << offset))) mask 1193 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c while (!(mask & 1)) mask 1194 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c mask >>= 1; mask 1195 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c if (mask & 0xff00) mask 1199 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c *delta_mask = mask; mask 1227 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c return memcmp(key1->mask, key2->mask, sizeof(key1->mask)); mask 1253 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_erp.c delta->mask = delta_mask; mask 110 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.h const char *mask); mask 192 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.h u8 mask; mask 265 drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_tcam.h const char *mask, bool ctcam); mask 155 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c if (match.mask->ingress_ifindex != 0xFFFFFFFF) { mask 194 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c (char *) &match.mask->src, 4); mask 197 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c (char *) &match.mask->dst, 4); mask 209 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->src.s6_addr[0x0], 4); mask 212 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->src.s6_addr[0x4], 4); mask 215 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->src.s6_addr[0x8], 4); mask 218 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->src.s6_addr[0xC], 4); mask 221 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->dst.s6_addr[0x0], 4); mask 224 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->dst.s6_addr[0x4], 4); mask 227 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->dst.s6_addr[0x8], 4); mask 230 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c &match.mask->dst.s6_addr[0xC], 4); mask 253 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c ntohs(match.mask->dst)); mask 256 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c ntohs(match.mask->src)); mask 279 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c if (match.mask->flags & htons(0x0E00)) { mask 287 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c ntohs(match.mask->flags)); mask 311 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.key->ttl, match.mask->ttl); mask 315 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->tos & 0x3); mask 319 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->tos >> 2); mask 371 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c n_proto_mask = ntohs(match.mask->n_proto); mask 385 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->ip_proto); mask 395 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->dst, 2); mask 399 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->dst + 2, 4); mask 403 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->src, 2); mask 407 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->src + 2, 4); mask 424 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c if (match.mask->vlan_id != 0) mask 428 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->vlan_id); mask 429 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c if (match.mask->vlan_priority != 0) mask 433 drivers/net/ethernet/mellanox/mlxsw/spectrum_flower.c match.mask->vlan_priority); mask 100 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c return __mlxsw_sp1_ptp_read_frc(clock, NULL) & cc->mask; mask 267 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c clock->cycles.mask = CLOCKSOURCE_MASK(MLXSW_SP1_PTP_CLOCK_MASK); mask 281 drivers/net/ethernet/mellanox/mlxsw/spectrum_ptp.c overflow_cycles = min(overflow_cycles, div_u64(clock->cycles.mask, 3)); mask 6863 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c u8 mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; mask 6865 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c return ether_addr_equal_masked(mac, vrrp4, mask); mask 6871 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c u8 mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; mask 6873 drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c return ether_addr_equal_masked(mac, vrrp6, mask); mask 546 drivers/net/ethernet/mellanox/mlxsw/switchx2.c u32 mask; mask 554 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, mask 560 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX, mask 564 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | mask 571 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, mask 577 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | mask 584 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | mask 593 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, mask 599 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, mask 605 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, mask 611 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, mask 617 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, mask 623 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR | mask 629 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 | mask 635 drivers/net/ethernet/mellanox/mlxsw/switchx2.c .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 | mask 671 drivers/net/ethernet/mellanox/mlxsw/switchx2.c if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) mask 683 drivers/net/ethernet/mellanox/mlxsw/switchx2.c if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) mask 700 drivers/net/ethernet/mellanox/mlxsw/switchx2.c if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) { mask 783 drivers/net/ethernet/mellanox/mlxsw/switchx2.c ptys_proto |= mlxsw_sx_port_link_mode[i].mask; mask 795 drivers/net/ethernet/mellanox/mlxsw/switchx2.c ptys_proto |= mlxsw_sx_port_link_mode[i].mask; mask 807 drivers/net/ethernet/mellanox/mlxsw/switchx2.c ptys_proto |= mlxsw_sx_port_link_mode[i].mask; mask 919 drivers/net/ethernet/micrel/ks8842.c dma_cap_mask_t mask; mask 921 drivers/net/ethernet/micrel/ks8842.c dma_cap_zero(mask); mask 922 drivers/net/ethernet/micrel/ks8842.c dma_cap_set(DMA_SLAVE, mask); mask 923 drivers/net/ethernet/micrel/ks8842.c dma_cap_set(DMA_PRIVATE, mask); mask 927 drivers/net/ethernet/micrel/ks8842.c tx_ctl->chan = dma_request_channel(mask, ks8842_dma_filter_fn, mask 949 drivers/net/ethernet/micrel/ks8842.c rx_ctl->chan = dma_request_channel(mask, ks8842_dma_filter_fn, mask 1009 drivers/net/ethernet/micrel/ksz884x.c int mask; mask 1610 drivers/net/ethernet/micrel/ksz884x.c info->last &= info->mask; mask 1630 drivers/net/ethernet/micrel/ksz884x.c info->next &= info->mask; mask 3555 drivers/net/ethernet/micrel/ksz884x.c const u8 *mask, uint frame_size, const u8 *pattern) mask 3583 drivers/net/ethernet/micrel/ksz884x.c val = mask[len]; mask 3594 drivers/net/ethernet/micrel/ksz884x.c bits = mask[len - 1]; mask 3613 drivers/net/ethernet/micrel/ksz884x.c static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 }; mask 3625 drivers/net/ethernet/micrel/ksz884x.c hw_set_wol_frame(hw, 3, 6, mask, 42, pattern); mask 3636 drivers/net/ethernet/micrel/ksz884x.c static const u8 mask[] = { 0x3F }; mask 3639 drivers/net/ethernet/micrel/ksz884x.c hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern); mask 3654 drivers/net/ethernet/micrel/ksz884x.c static const u8 mask[] = { 0x3F }; mask 3658 drivers/net/ethernet/micrel/ksz884x.c hw_set_wol_frame(hw, 1, 1, mask, 6, pattern); mask 3672 drivers/net/ethernet/micrel/ksz884x.c static const u8 mask[] = { 0x3F }; mask 3674 drivers/net/ethernet/micrel/ksz884x.c hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr); mask 3823 drivers/net/ethernet/micrel/ksz884x.c info->mask = info->alloc - 1; mask 4774 drivers/net/ethernet/micrel/ksz884x.c last &= info->mask; mask 5059 drivers/net/ethernet/micrel/ksz884x.c next &= info->mask; mask 5104 drivers/net/ethernet/micrel/ksz884x.c next &= info->mask; mask 5163 drivers/net/ethernet/micrel/ksz884x.c next &= info->mask; mask 239 drivers/net/ethernet/microchip/enc28j60.c static void nolock_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask) mask 242 drivers/net/ethernet/microchip/enc28j60.c spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask); mask 245 drivers/net/ethernet/microchip/enc28j60.c static void locked_reg_bfset(struct enc28j60_net *priv, u8 addr, u8 mask) mask 248 drivers/net/ethernet/microchip/enc28j60.c nolock_reg_bfset(priv, addr, mask); mask 255 drivers/net/ethernet/microchip/enc28j60.c static void nolock_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask) mask 258 drivers/net/ethernet/microchip/enc28j60.c spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask); mask 261 drivers/net/ethernet/microchip/enc28j60.c static void locked_reg_bfclr(struct enc28j60_net *priv, u8 addr, u8 mask) mask 264 drivers/net/ethernet/microchip/enc28j60.c nolock_reg_bfclr(priv, addr, mask); mask 410 drivers/net/ethernet/microchip/enc28j60.c static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val) mask 416 drivers/net/ethernet/microchip/enc28j60.c while ((nolock_regb_read(priv, reg) & mask) != val) { mask 20 drivers/net/ethernet/microchip/encx24j600-regmap.c static inline bool is_bits_set(int value, int mask) mask 22 drivers/net/ethernet/microchip/encx24j600-regmap.c return (value & mask) == mask; mask 194 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int mask, mask 200 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int set_mask = mask & val; mask 201 drivers/net/ethernet/microchip/encx24j600-regmap.c unsigned int clr_mask = mask & ~val; mask 121 drivers/net/ethernet/microchip/encx24j600.c u16 mask, u16 val) mask 124 drivers/net/ethernet/microchip/encx24j600.c int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val); mask 128 drivers/net/ethernet/microchip/encx24j600.c __func__, ret, reg, val, mask); mask 153 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) mask 155 drivers/net/ethernet/microchip/encx24j600.c encx24j600_update_reg(priv, reg, mask, 0); mask 158 drivers/net/ethernet/microchip/encx24j600.c static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask) mask 160 drivers/net/ethernet/microchip/encx24j600.c encx24j600_update_reg(priv, reg, mask, mask); mask 159 drivers/net/ethernet/mscc/ocelot.c static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) mask 165 drivers/net/ethernet/mscc/ocelot.c ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | mask 1245 drivers/net/ethernet/mscc/ocelot.c unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(port); mask 1254 drivers/net/ethernet/mscc/ocelot.c mask &= ~bond_mask; mask 1260 drivers/net/ethernet/mscc/ocelot.c BIT(ocelot->num_phys_ports) | mask, mask 526 drivers/net/ethernet/mscc/ocelot.h void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, mask 84 drivers/net/ethernet/mscc/ocelot_ace.c u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */ mask 139 drivers/net/ethernet/mscc/ocelot_ace.c ocelot_write_rix(oc, ~data->mask[i], S2_CACHE_MASK_DAT, i); mask 151 drivers/net/ethernet/mscc/ocelot_ace.c data->mask[i] = ~ocelot_read_rix(oc, S2_CACHE_MASK_DAT, i); mask 158 drivers/net/ethernet/mscc/ocelot_ace.c u32 i, width, mask; mask 163 drivers/net/ethernet/mscc/ocelot_ace.c mask = GENMASK(width, 0); mask 164 drivers/net/ethernet/mscc/ocelot_ace.c data->action[0] = ((data->action[0] & ~mask) | data->type); mask 246 drivers/net/ethernet/mscc/ocelot_ace.c u32 value, u32 mask) mask 249 drivers/net/ethernet/mscc/ocelot_ace.c vcap_data_set(data->mask, offset + data->key_offset, width, mask); mask 255 drivers/net/ethernet/mscc/ocelot_ace.c u32 i, j, n = 0, value = 0, mask = 0; mask 264 drivers/net/ethernet/mscc/ocelot_ace.c mask += (msk[j] << n); mask 268 drivers/net/ethernet/mscc/ocelot_ace.c vcap_key_set(data, offset, n, value, mask); mask 271 drivers/net/ethernet/mscc/ocelot_ace.c mask = 0; mask 279 drivers/net/ethernet/mscc/ocelot_ace.c vcap_key_set(data, offset, 16, port->value, port->mask); mask 361 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_SET(VID, tag->vid.value, tag->vid.mask); mask 362 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_SET(PCP, tag->pcp.value[0], tag->pcp.mask[0]); mask 371 drivers/net/ethernet/mscc/ocelot_ace.c etype->dmac.mask); mask 373 drivers/net/ethernet/mscc/ocelot_ace.c etype->smac.mask); mask 375 drivers/net/ethernet/mscc/ocelot_ace.c etype->etype.mask); mask 378 drivers/net/ethernet/mscc/ocelot_ace.c etype->data.value, etype->data.mask, 2); mask 385 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(L2_DMAC, llc->dmac.value, llc->dmac.mask); mask 386 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(L2_SMAC, llc->smac.value, llc->smac.mask); mask 389 drivers/net/ethernet/mscc/ocelot_ace.c payload.mask[i] = llc->llc.mask[i]; mask 391 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(MAC_LLC_L2_LLC, payload.value, payload.mask); mask 398 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(L2_DMAC, snap->dmac.value, snap->dmac.mask); mask 399 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(L2_SMAC, snap->smac.value, snap->smac.mask); mask 402 drivers/net/ethernet/mscc/ocelot_ace.c ace->frame.snap.snap.mask); mask 410 drivers/net/ethernet/mscc/ocelot_ace.c arp->smac.mask); mask 425 drivers/net/ethernet/mscc/ocelot_ace.c arp->dip.value.addr, arp->dip.mask.addr, 4); mask 427 drivers/net/ethernet/mscc/ocelot_ace.c arp->sip.value.addr, arp->sip.mask.addr, 4); mask 474 drivers/net/ethernet/mscc/ocelot_ace.c msk = ipv6->sip.mask[i + 8]; mask 477 drivers/net/ethernet/mscc/ocelot_ace.c dip.mask.addr[i] = msk; mask 480 drivers/net/ethernet/mscc/ocelot_ace.c sip.mask.addr[i - 4] = msk; mask 502 drivers/net/ethernet/mscc/ocelot_ace.c VCAP_KEY_BYTES_SET(L3_TOS, ds.value, ds.mask); mask 504 drivers/net/ethernet/mscc/ocelot_ace.c dip.mask.addr, 4); mask 506 drivers/net/ethernet/mscc/ocelot_ace.c sip.mask.addr, 4); mask 509 drivers/net/ethernet/mscc/ocelot_ace.c msk = proto.mask[0]; mask 543 drivers/net/ethernet/mscc/ocelot_ace.c payload.mask[i] = ip_data->mask[i]; mask 547 drivers/net/ethernet/mscc/ocelot_ace.c proto.mask); mask 549 drivers/net/ethernet/mscc/ocelot_ace.c payload.mask); mask 25 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[1]; mask 30 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[2]; mask 35 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[3]; mask 40 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[4]; mask 45 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[5]; mask 50 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[6]; mask 55 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[8]; mask 60 drivers/net/ethernet/mscc/ocelot_ace.h u8 mask[16]; mask 65 drivers/net/ethernet/mscc/ocelot_ace.h u16 mask; mask 70 drivers/net/ethernet/mscc/ocelot_ace.h struct ocelot_ipv4 mask; mask 75 drivers/net/ethernet/mscc/ocelot_ace.h u16 mask; mask 92 drivers/net/ethernet/mscc/ocelot_flower.c ether_addr_copy(ocelot_rule->frame.etype.dmac.mask, mask 93 drivers/net/ethernet/mscc/ocelot_flower.c match.mask->dst); mask 94 drivers/net/ethernet/mscc/ocelot_flower.c ether_addr_copy(ocelot_rule->frame.etype.smac.mask, mask 95 drivers/net/ethernet/mscc/ocelot_flower.c match.mask->src); mask 107 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->frame.ipv4.proto.mask[0] = mask 108 drivers/net/ethernet/mscc/ocelot_flower.c match.mask->ip_proto; mask 114 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->frame.ipv6.proto.mask[0] = mask 115 drivers/net/ethernet/mscc/ocelot_flower.c match.mask->ip_proto; mask 128 drivers/net/ethernet/mscc/ocelot_flower.c tmp = &ocelot_rule->frame.ipv4.sip.mask.addr[0]; mask 129 drivers/net/ethernet/mscc/ocelot_flower.c memcpy(tmp, &match.mask->src, 4); mask 134 drivers/net/ethernet/mscc/ocelot_flower.c tmp = &ocelot_rule->frame.ipv4.dip.mask.addr[0]; mask 135 drivers/net/ethernet/mscc/ocelot_flower.c memcpy(tmp, &match.mask->dst, 4); mask 148 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->frame.ipv4.sport.mask = ntohs(match.mask->src); mask 150 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->frame.ipv4.dport.mask = ntohs(match.mask->dst); mask 159 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->vlan.vid.mask = match.mask->vlan_id; mask 161 drivers/net/ethernet/mscc/ocelot_flower.c ocelot_rule->vlan.pcp.mask[0] = match.mask->vlan_priority; mask 37 drivers/net/ethernet/mscc/ocelot_io.c void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg, mask 46 drivers/net/ethernet/mscc/ocelot_io.c mask, val); mask 134 drivers/net/ethernet/myricom/myri10ge/myri10ge.c int mask; /* number of rx slots -1 */ mask 145 drivers/net/ethernet/myricom/myri10ge/myri10ge.c int mask; /* number of transmit slots -1 */ mask 1204 drivers/net/ethernet/myricom/myri10ge/myri10ge.c while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) { mask 1205 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = rx->fill_cnt & rx->mask; mask 1337 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = rx->cnt & rx->mask; mask 1348 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = rx->cnt & rx->mask; mask 1362 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = rx->cnt & rx->mask; mask 1396 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = tx->done & tx->mask; mask 1448 drivers/net/ethernet/myricom/myri10ge/myri10ge.c tx->req - tx->done < (tx->mask >> 1) && mask 1717 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1; mask 1718 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1; mask 1720 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ring->tx_max_pending = mgp->ss[0].tx.mask + 1; mask 1962 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ss->tx.mask = tx_ring_entries - 1; mask 1963 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1; mask 2017 drivers/net/ethernet/myricom/myri10ge/myri10ge.c ss->rx_small.fill_cnt = ss->rx_small.mask + 1; mask 2023 drivers/net/ethernet/myricom/myri10ge/myri10ge.c if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) { mask 2030 drivers/net/ethernet/myricom/myri10ge/myri10ge.c if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) { mask 2040 drivers/net/ethernet/myricom/myri10ge/myri10ge.c int idx = i & ss->rx_big.mask; mask 2050 drivers/net/ethernet/myricom/myri10ge/myri10ge.c int idx = i & ss->rx_small.mask; mask 2091 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = i & ss->rx_big.mask; mask 2102 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = i & ss->rx_small.mask; mask 2112 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = tx->done & tx->mask; mask 2529 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = (starting_slot + cnt) & tx->mask; mask 2551 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = tx->req & tx->mask; mask 2559 drivers/net/ethernet/myricom/myri10ge/myri10ge.c if ((idx + cnt) < tx->mask) { mask 2592 drivers/net/ethernet/myricom/myri10ge/myri10ge.c last_idx = (idx + 1) & tx->mask; mask 2593 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = tx->req & tx->mask; mask 2610 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = (idx + 1) & tx->mask; mask 2649 drivers/net/ethernet/myricom/myri10ge/myri10ge.c avail = tx->mask - 1 - (tx->req - tx->done); mask 2733 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = tx->req & tx->mask; mask 2842 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = (count + tx->req) & tx->mask; mask 2854 drivers/net/ethernet/myricom/myri10ge/myri10ge.c idx = ((count - 1) + tx->req) & tx->mask; mask 3257 drivers/net/ethernet/myricom/myri10ge/myri10ge.c u32 mask; mask 3267 drivers/net/ethernet/myricom/myri10ge/myri10ge.c pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask); mask 3268 drivers/net/ethernet/myricom/myri10ge/myri10ge.c mask |= 0x20; mask 3269 drivers/net/ethernet/myricom/myri10ge/myri10ge.c pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask); mask 120 drivers/net/ethernet/natsemi/sonic.c static void sonic_quiesce(struct net_device *dev, u16 mask) mask 127 drivers/net/ethernet/natsemi/sonic.c bits = SONIC_READ(SONIC_CMD) & mask; mask 1848 drivers/net/ethernet/neterion/s2io.c static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag) mask 1855 drivers/net/ethernet/neterion/s2io.c if (mask & TX_DMA_INTR) { mask 1894 drivers/net/ethernet/neterion/s2io.c if (mask & TX_MAC_INTR) { mask 1904 drivers/net/ethernet/neterion/s2io.c if (mask & TX_XGXS_INTR) { mask 1913 drivers/net/ethernet/neterion/s2io.c if (mask & RX_DMA_INTR) { mask 1940 drivers/net/ethernet/neterion/s2io.c if (mask & RX_MAC_INTR) { mask 1953 drivers/net/ethernet/neterion/s2io.c if (mask & RX_XGXS_INTR) { mask 1961 drivers/net/ethernet/neterion/s2io.c if (mask & MC_INTR) { mask 1986 drivers/net/ethernet/neterion/s2io.c static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) mask 1995 drivers/net/ethernet/neterion/s2io.c if (mask & TX_PIC_INTR) { mask 2023 drivers/net/ethernet/neterion/s2io.c if (mask & TX_TRAFFIC_INTR) { mask 2041 drivers/net/ethernet/neterion/s2io.c if (mask & RX_TRAFFIC_INTR) { mask 3173 drivers/net/ethernet/neterion/s2io.c u64 mask = 0x3; mask 3177 drivers/net/ethernet/neterion/s2io.c mask = mask << 0x2; mask 3181 drivers/net/ethernet/neterion/s2io.c val64 = *regs_stat & mask; mask 3211 drivers/net/ethernet/neterion/s2io.c *regs_stat = (*regs_stat & (~mask)) | (val64); mask 3214 drivers/net/ethernet/neterion/s2io.c *regs_stat = *regs_stat & (~mask); mask 4882 drivers/net/ethernet/neterion/s2io.c u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = mask 4892 drivers/net/ethernet/neterion/s2io.c writeq(RMAC_ADDR_DATA1_MEM_MASK(mask), mask 119 drivers/net/ethernet/neterion/vxge/vxge-config.c __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis) mask 128 drivers/net/ethernet/neterion/vxge/vxge-config.c if (!(val64 & mask)) mask 136 drivers/net/ethernet/neterion/vxge/vxge-config.c if (!(val64 & mask)) mask 146 drivers/net/ethernet/neterion/vxge/vxge-config.c u64 mask, u32 max_millis) mask 153 drivers/net/ethernet/neterion/vxge/vxge-config.c return __vxge_hw_device_register_poll(addr, mask, max_millis); mask 1846 drivers/net/ethernet/neterion/vxge/vxge-config.c enum vxge_debug_level level, u32 mask) mask 1853 drivers/net/ethernet/neterion/vxge/vxge-config.c hldev->debug_module_mask = mask; mask 1467 drivers/net/ethernet/neterion/vxge/vxge-config.h u32 mask); mask 2044 drivers/net/ethernet/neterion/vxge/vxge-config.h #define vxge_debug_ll(level, mask, fmt, ...) do { \ mask 2047 drivers/net/ethernet/neterion/vxge/vxge-config.h if ((mask & VXGE_DEBUG_MASK) == mask) \ mask 2051 drivers/net/ethernet/neterion/vxge/vxge-config.h #define vxge_debug_ll(level, mask, fmt, ...) mask 502 drivers/net/ethernet/neterion/vxge/vxge-main.h #define VXGE_DEVICE_DEBUG_LEVEL_SET(level, mask, vdev) {\ mask 504 drivers/net/ethernet/neterion/vxge/vxge-main.h level, mask);\ mask 15 drivers/net/ethernet/netronome/nfp/abm/cls.c u8 mask; mask 49 drivers/net/ethernet/netronome/nfp/abm/cls.c if (knode->val || knode->mask) { mask 88 drivers/net/ethernet/netronome/nfp/abm/cls.c if (k->val & ~k->mask) { mask 92 drivers/net/ethernet/netronome/nfp/abm/cls.c if (be32_to_cpu(k->mask) >> tos_off & ~abm->dscp_mask) { mask 96 drivers/net/ethernet/netronome/nfp/abm/cls.c be32_to_cpu(k->mask) >> tos_off, abm->dscp_mask); mask 113 drivers/net/ethernet/netronome/nfp/abm/cls.c if ((prio & iter->mask) == iter->val) mask 176 drivers/net/ethernet/netronome/nfp/abm/cls.c u8 mask, val; mask 186 drivers/net/ethernet/netronome/nfp/abm/cls.c mask = be32_to_cpu(knode->sel->keys[0].mask) >> tos_off & 0xff; mask 197 drivers/net/ethernet/netronome/nfp/abm/cls.c cmask = iter->mask & mask; mask 213 drivers/net/ethernet/netronome/nfp/abm/cls.c match->mask = mask; mask 141 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_br(struct nfp_prog *nfp_prog, enum br_mask mask, enum br_ev_pip ev_pip, mask 151 drivers/net/ethernet/netronome/nfp/bpf/jit.c FIELD_PREP(OP_BR_MASK, mask) | mask 162 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_br_relo(struct nfp_prog *nfp_prog, enum br_mask mask, u16 addr, u8 defer, mask 165 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (mask == BR_UNC && defer > 2) { mask 171 drivers/net/ethernet/netronome/nfp/bpf/jit.c __emit_br(nfp_prog, mask, mask 172 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask != BR_UNC ? BR_EV_PIP_COND : BR_EV_PIP_UNCOND, mask 180 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_br(struct nfp_prog *nfp_prog, enum br_mask mask, u16 addr, u8 defer) mask 182 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_br_relo(nfp_prog, mask, addr, defer, RELO_BR_REL); mask 697 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 mask = (1 << field_len) - 1; mask 699 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field_any(nfp_prog, dst, mask, src, sc, offset * 8, true); mask 710 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 mask = ((1 << field_len) - 1) << offset; mask 712 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field(nfp_prog, dst, mask, src, sc, 32 - offset * 8); mask 903 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 mask, sz; mask 909 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask = size < 4 ? GENMASK(size - 1, 0) : 0; mask 915 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (mask) mask 916 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field_any(nfp_prog, reg_both(dst_gpr), mask, mask 1029 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 mask; mask 1048 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask = (1 << size) - 1; mask 1049 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask <<= dst_byte; mask 1051 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (WARN_ON_ONCE(mask > 0xf)) mask 1080 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field_any(nfp_prog, reg_both(dst), mask, reg, sc, shf, new_gpr); mask 1098 drivers/net/ethernet/netronome/nfp/bpf/jit.c u8 mask; mask 1118 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask = (1 << size) - 1; mask 1119 drivers/net/ethernet/netronome/nfp/bpf/jit.c mask <<= dst_byte; mask 1121 drivers/net/ethernet/netronome/nfp/bpf/jit.c if (WARN_ON_ONCE(mask > 0xf)) mask 1148 drivers/net/ethernet/netronome/nfp/bpf/jit.c emit_ld_field(nfp_prog, reg, mask, reg_b(src), sc, shf); mask 247 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg3->var_off.mask & BPF_F_INDEX_MASK || mask 543 drivers/net/ethernet/netronome/nfp/bpf/verifier.c sreg->var_off.value > 0xffff || sreg->var_off.mask > 0xffff; mask 545 drivers/net/ethernet/netronome/nfp/bpf/verifier.c (sreg->var_off.value & ~sreg->var_off.mask) <= 0xffff; mask 475 drivers/net/ethernet/netronome/nfp/flower/action.c static void nfp_fl_set_helper32(u32 value, u32 mask, u8 *p_exact, u8 *p_mask) mask 480 drivers/net/ethernet/netronome/nfp/flower/action.c value &= mask; mask 481 drivers/net/ethernet/netronome/nfp/flower/action.c value |= oldvalue & ~mask; mask 483 drivers/net/ethernet/netronome/nfp/flower/action.c put_unaligned(oldmask | mask, (u32 *)p_mask); mask 491 drivers/net/ethernet/netronome/nfp/flower/action.c u32 exact, mask; mask 498 drivers/net/ethernet/netronome/nfp/flower/action.c mask = ~act->mangle.mask; mask 501 drivers/net/ethernet/netronome/nfp/flower/action.c if (exact & ~mask) { mask 506 drivers/net/ethernet/netronome/nfp/flower/action.c nfp_fl_set_helper32(exact, mask, &set_eth->eth_addr_val[off], mask 532 drivers/net/ethernet/netronome/nfp/flower/action.c __be32 exact, mask; mask 535 drivers/net/ethernet/netronome/nfp/flower/action.c mask = (__force __be32)~act->mangle.mask; mask 538 drivers/net/ethernet/netronome/nfp/flower/action.c if (exact & ~mask) { mask 545 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_dst_mask |= mask; mask 546 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_dst &= ~mask; mask 547 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_dst |= exact & mask; mask 553 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_src_mask |= mask; mask 554 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_src &= ~mask; mask 555 drivers/net/ethernet/netronome/nfp/flower/action.c set_ip_addr->ipv4_src |= exact & mask; mask 561 drivers/net/ethernet/netronome/nfp/flower/action.c ttl_word_mask = (struct ipv4_ttl_word *)&mask; mask 578 drivers/net/ethernet/netronome/nfp/flower/action.c tos_word_mask = (struct iphdr *)&mask; mask 604 drivers/net/ethernet/netronome/nfp/flower/action.c nfp_fl_set_ip6_helper(int opcode_tag, u8 word, __be32 exact, __be32 mask, mask 607 drivers/net/ethernet/netronome/nfp/flower/action.c ip6->ipv6[word].mask |= mask; mask 608 drivers/net/ethernet/netronome/nfp/flower/action.c ip6->ipv6[word].exact &= ~mask; mask 609 drivers/net/ethernet/netronome/nfp/flower/action.c ip6->ipv6[word].exact |= exact & mask; mask 623 drivers/net/ethernet/netronome/nfp/flower/action.c nfp_fl_set_ip6_hop_limit_flow_label(u32 off, __be32 exact, __be32 mask, mask 632 drivers/net/ethernet/netronome/nfp/flower/action.c fl_hl_mask = (struct ipv6_hop_limit_word *)&mask; mask 646 drivers/net/ethernet/netronome/nfp/flower/action.c if (mask & ~IPV6_FLOW_LABEL_MASK || mask 652 drivers/net/ethernet/netronome/nfp/flower/action.c ip_hl_fl->ipv6_label_mask |= mask; mask 653 drivers/net/ethernet/netronome/nfp/flower/action.c ip_hl_fl->ipv6_label &= ~mask; mask 654 drivers/net/ethernet/netronome/nfp/flower/action.c ip_hl_fl->ipv6_label |= exact & mask; mask 671 drivers/net/ethernet/netronome/nfp/flower/action.c __be32 exact, mask; mask 676 drivers/net/ethernet/netronome/nfp/flower/action.c mask = (__force __be32)~act->mangle.mask; mask 679 drivers/net/ethernet/netronome/nfp/flower/action.c if (exact & ~mask) { mask 685 drivers/net/ethernet/netronome/nfp/flower/action.c err = nfp_fl_set_ip6_hop_limit_flow_label(off, exact, mask, mask 690 drivers/net/ethernet/netronome/nfp/flower/action.c exact, mask, ip_src); mask 695 drivers/net/ethernet/netronome/nfp/flower/action.c exact, mask, ip_dst); mask 709 drivers/net/ethernet/netronome/nfp/flower/action.c u32 exact, mask; mask 716 drivers/net/ethernet/netronome/nfp/flower/action.c mask = ~act->mangle.mask; mask 719 drivers/net/ethernet/netronome/nfp/flower/action.c if (exact & ~mask) { mask 724 drivers/net/ethernet/netronome/nfp/flower/action.c nfp_fl_set_helper32(exact, mask, set_tport->tp_port_val, mask 168 drivers/net/ethernet/netronome/nfp/flower/cmsg.h __be32 mask; mask 42 drivers/net/ethernet/netronome/nfp/flower/match.c match.mask->vlan_priority) | mask 44 drivers/net/ethernet/netronome/nfp/flower/match.c match.mask->vlan_id); mask 95 drivers/net/ethernet/netronome/nfp/flower/match.c ether_addr_copy(msk->mac_dst, &match.mask->dst[0]); mask 96 drivers/net/ethernet/netronome/nfp/flower/match.c ether_addr_copy(msk->mac_src, &match.mask->src[0]); mask 109 drivers/net/ethernet/netronome/nfp/flower/match.c t_mpls = FIELD_PREP(NFP_FLOWER_MASK_MPLS_LB, match.mask->mpls_label) | mask 110 drivers/net/ethernet/netronome/nfp/flower/match.c FIELD_PREP(NFP_FLOWER_MASK_MPLS_TC, match.mask->mpls_tc) | mask 111 drivers/net/ethernet/netronome/nfp/flower/match.c FIELD_PREP(NFP_FLOWER_MASK_MPLS_BOS, match.mask->mpls_bos) | mask 146 drivers/net/ethernet/netronome/nfp/flower/match.c msk->port_src = match.mask->src; mask 147 drivers/net/ethernet/netronome/nfp/flower/match.c msk->port_dst = match.mask->dst; mask 163 drivers/net/ethernet/netronome/nfp/flower/match.c msk->proto = match.mask->ip_proto; mask 172 drivers/net/ethernet/netronome/nfp/flower/match.c msk->tos = match.mask->tos; mask 173 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ttl = match.mask->ttl; mask 182 drivers/net/ethernet/netronome/nfp/flower/match.c tcp_flags_mask = be16_to_cpu(match.mask->flags); mask 216 drivers/net/ethernet/netronome/nfp/flower/match.c if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) mask 220 drivers/net/ethernet/netronome/nfp/flower/match.c if (match.mask->flags & FLOW_DIS_FIRST_FRAG) mask 240 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ipv4_src = match.mask->src; mask 241 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ipv4_dst = match.mask->dst; mask 263 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ipv6_src = match.mask->src; mask 264 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ipv6_dst = match.mask->dst; mask 278 drivers/net/ethernet/netronome/nfp/flower/match.c memcpy(msk, match.mask->data, match.mask->len); mask 296 drivers/net/ethernet/netronome/nfp/flower/match.c msk->src = match.mask->src; mask 297 drivers/net/ethernet/netronome/nfp/flower/match.c msk->dst = match.mask->dst; mask 314 drivers/net/ethernet/netronome/nfp/flower/match.c msk->tos = match.mask->tos; mask 315 drivers/net/ethernet/netronome/nfp/flower/match.c msk->ttl = match.mask->ttl; mask 338 drivers/net/ethernet/netronome/nfp/flower/match.c msk->tun_key = match.mask->keyid; mask 365 drivers/net/ethernet/netronome/nfp/flower/match.c temp_vni = be32_to_cpu(match.mask->keyid) << NFP_FL_TUN_VNI_OFFSET; mask 276 drivers/net/ethernet/netronome/nfp/flower/offload.c if (enc_ctl.mask->addr_type != 0xffff) { mask 287 drivers/net/ethernet/netronome/nfp/flower/offload.c if (ipv4_addrs.mask->dst != cpu_to_be32(~0)) { mask 316 drivers/net/ethernet/netronome/nfp/flower/offload.c if (enc_ports.mask->dst != cpu_to_be16(~0)) { mask 343 drivers/net/ethernet/netronome/nfp/flower/offload.c if (basic.mask && basic.mask->n_proto) { mask 384 drivers/net/ethernet/netronome/nfp/flower/offload.c if (basic.mask && basic.mask->ip_proto) { mask 576 drivers/net/ethernet/netronome/nfp/flower/offload.c ipv6_add->ipv6[i].mask; mask 582 drivers/net/ethernet/netronome/nfp/flower/offload.c ipv6_add->ipv6[i].mask; mask 622 drivers/net/ethernet/netronome/nfp/flower/offload.c u8 *mask = flow->mask_data; mask 627 drivers/net/ethernet/netronome/nfp/flower/offload.c meta_tci = (struct nfp_flower_meta_tci *)mask; mask 634 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_meta_tci); mask 637 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_ext_meta); mask 639 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_in_port); mask 643 drivers/net/ethernet/netronome/nfp/flower/offload.c memcpy(&merge->l2, mask, match_size); mask 644 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += match_size; mask 649 drivers/net/ethernet/netronome/nfp/flower/offload.c memcpy(&merge->l4, mask, match_size); mask 650 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += match_size; mask 655 drivers/net/ethernet/netronome/nfp/flower/offload.c memcpy(&merge->ipv4, mask, match_size); mask 660 drivers/net/ethernet/netronome/nfp/flower/offload.c memcpy(&merge->ipv6, mask, match_size); mask 1023 drivers/net/ethernet/netronome/nfp/flower/offload.c u8 *mask = flow->mask_data; mask 1051 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_meta_tci); mask 1052 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_in_port); mask 1055 drivers/net/ethernet/netronome/nfp/flower/offload.c mac = (struct nfp_flower_mac_mpls *)mask; mask 1066 drivers/net/ethernet/netronome/nfp/flower/offload.c mask += sizeof(struct nfp_flower_mac_mpls); mask 1070 drivers/net/ethernet/netronome/nfp/flower/offload.c if (mask[i] && i != ip_flags && i != ip_proto) { mask 134 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u64 mask; /* Bit mask of the bar */ mask 225 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u64 mask = ~(NFP_PCIE_P2C_FIXED_SIZE(bar) - 1); mask 233 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c if ((offset & mask) != ((offset + size - 1) & mask)) mask 235 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c offset &= mask; mask 239 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c u64 mask = ~(NFP_PCIE_P2C_BULK_SIZE(bar) - 1); mask 247 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c if ((offset & mask) != ((offset + size - 1) & mask)) mask 250 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c offset &= mask; mask 589 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c bar->mask = nfp_bar_resource_len(bar) - 1; mask 590 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c bar->bitsize = fls(bar->mask); mask 842 drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c priv->bar_offset = priv->offset & priv->bar->mask; mask 249 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpp.h int nfp_xpb_writelm(struct nfp_cpp *cpp, u32 xpb_tgt, u32 mask, u32 value); mask 406 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cpp.h u8 len, u8 mask); mask 1127 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c u32 mask, u32 value) mask 1136 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c tmp &= ~mask; mask 1137 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c tmp |= mask & value; mask 1167 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c u32 mask[2]; mask 1240 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c &mask[0]); mask 1242 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c &mask[1]); mask 1342 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c u32 cpp_id, u8 len, u8 mask) mask 1346 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c expl->cmd.byte_mask = mask; mask 321 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c u64 mask, u64 val, u32 timeout_sec) mask 333 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.c if ((*reg & mask) == val) mask 463 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c const u64 mask, const unsigned int shift, mask 481 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c if (val == (reg & mask) >> shift) mask 484 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg &= ~mask; mask 485 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c reg |= (val << shift) & mask; mask 495 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c #define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \ mask 497 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c __BF_FIELD_CHECK(mask, 0ULL, val, "NFP_ETH_SET_BIT_CONFIG: "); \ mask 498 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c nfp_eth_set_bit_config(nsp, raw_idx, mask, __bf_shf(mask), \ mask 694 drivers/net/ethernet/nvidia/forcedeth.c __u32 mask; mask 968 drivers/net/ethernet/nvidia/forcedeth.c static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, mask 979 drivers/net/ethernet/nvidia/forcedeth.c } while ((readl(base + offset) & mask) != target); mask 1103 drivers/net/ethernet/nvidia/forcedeth.c static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) mask 1107 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); mask 1110 drivers/net/ethernet/nvidia/forcedeth.c static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) mask 1116 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); mask 3177 drivers/net/ethernet/nvidia/forcedeth.c u32 mask[2]; mask 3181 drivers/net/ethernet/nvidia/forcedeth.c memset(mask, 0, sizeof(mask)); mask 3212 drivers/net/ethernet/nvidia/forcedeth.c mask[0] = alwaysOn[0] | alwaysOff[0]; mask 3213 drivers/net/ethernet/nvidia/forcedeth.c mask[1] = alwaysOn[1] | alwaysOff[1]; mask 3215 drivers/net/ethernet/nvidia/forcedeth.c mask[0] = NVREG_MCASTMASKA_NONE; mask 3216 drivers/net/ethernet/nvidia/forcedeth.c mask[1] = NVREG_MCASTMASKB_NONE; mask 3225 drivers/net/ethernet/nvidia/forcedeth.c writel(mask[0], base + NvRegMulticastMaskA); mask 3226 drivers/net/ethernet/nvidia/forcedeth.c writel(mask[1], base + NvRegMulticastMaskB); mask 4126 drivers/net/ethernet/nvidia/forcedeth.c u32 mask = 0; mask 4141 drivers/net/ethernet/nvidia/forcedeth.c mask = np->irqmask; mask 4145 drivers/net/ethernet/nvidia/forcedeth.c mask |= NVREG_IRQ_RX_ALL; mask 4149 drivers/net/ethernet/nvidia/forcedeth.c mask |= NVREG_IRQ_TX_ALL; mask 4153 drivers/net/ethernet/nvidia/forcedeth.c mask |= NVREG_IRQ_OTHER; mask 4202 drivers/net/ethernet/nvidia/forcedeth.c writel(mask, base + NvRegIrqMask); mask 4396 drivers/net/ethernet/nvidia/forcedeth.c u32 mask; mask 4398 drivers/net/ethernet/nvidia/forcedeth.c mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | mask 4401 drivers/net/ethernet/nvidia/forcedeth.c mask |= ADVERTISED_1000baseT_Full; mask 4403 drivers/net/ethernet/nvidia/forcedeth.c if ((advertising & mask) == 0) mask 5016 drivers/net/ethernet/nvidia/forcedeth.c orig_read ^= nv_registers_test[i].mask; mask 5022 drivers/net/ethernet/nvidia/forcedeth.c if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) mask 5026 drivers/net/ethernet/nvidia/forcedeth.c orig_read ^= nv_registers_test[i].mask; mask 461 drivers/net/ethernet/pensando/ionic/ionic_dev.c unsigned int mask, tail, head; mask 463 drivers/net/ethernet/pensando/ionic/ionic_dev.c mask = q->num_descs - 1; mask 467 drivers/net/ethernet/pensando/ionic/ionic_dev.c return ((pos - tail) & mask) < ((head - tail) & mask); mask 18 drivers/net/ethernet/pensando/ionic/ionic_regs.h u32 mask; mask 60 drivers/net/ethernet/pensando/ionic/ionic_regs.h int intr_idx, u32 mask) mask 62 drivers/net/ethernet/pensando/ionic/ionic_regs.h iowrite32(mask, &intr_ctrl[intr_idx].mask); mask 88 drivers/net/ethernet/pensando/ionic/ionic_regs.h int intr_idx, u32 mask) mask 90 drivers/net/ethernet/pensando/ionic/ionic_regs.h iowrite32(mask, &intr_ctrl[intr_idx].mask_assert); mask 230 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c uint64_t mask, cmask; mask 234 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c mask = DMA_BIT_MASK(32); mask 239 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c mask = DMA_BIT_MASK(35); mask 242 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c mask = DMA_BIT_MASK(39); mask 243 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c cmask = mask; mask 246 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if (pci_set_dma_mask(pdev, mask) == 0 && mask 260 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c uint64_t mask, old_mask, old_cmask; mask 278 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c mask = DMA_BIT_MASK(32+shift); mask 280 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c err = pci_set_dma_mask(pdev, mask); mask 286 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c err = pci_set_consistent_dma_mask(pdev, mask); mask 2285 drivers/net/ethernet/qlogic/qed/qed_hsi.h u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ mask 2291 drivers/net/ethernet/qlogic/qed/qed_hsi.h struct dbg_bus_storm_eid_mask_params mask; mask 803 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c u32 mask = (QM_OPPOR_LINE_VOQ_DEF << mask 819 drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask); mask 957 drivers/net/ethernet/qlogic/qed/qed_int.c u32 block_id = p_aeu->block_index, mask, val; mask 976 drivers/net/ethernet/qlogic/qed/qed_int.c mask = ~BIT(bit_index); mask 978 drivers/net/ethernet/qlogic/qed/qed_int.c qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); mask 2073 drivers/net/ethernet/qlogic/qed/qed_main.c u32 offset, mask, value, cur_value; mask 2078 drivers/net/ethernet/qlogic/qed/qed_main.c mask = *((u32 *)*data); mask 2095 drivers/net/ethernet/qlogic/qed/qed_main.c (cur_value & ~mask) | (value & mask), value, mask); mask 2096 drivers/net/ethernet/qlogic/qed/qed_main.c value = (value & mask) | (cur_value & ~mask); mask 2209 drivers/net/ethernet/qlogic/qed/qed_sriov.c enum qed_tunn_mode mask, u8 tun_cls) mask 2211 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_req->tun_mode_update_mask & BIT(mask)) { mask 2214 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (p_req->tunn_mode & BIT(mask)) mask 2225 drivers/net/ethernet/qlogic/qed/qed_sriov.c enum qed_tunn_mode mask, mask 2233 drivers/net/ethernet/qlogic/qed/qed_sriov.c __qed_iov_pf_update_tun_param(p_req, p_tun, mask, tun_cls); mask 3002 drivers/net/ethernet/qlogic/qed/qed_sriov.c u8 mask = QED_ACCEPT_UCAST_UNMATCHED | QED_ACCEPT_MCAST_UNMATCHED; mask 3018 drivers/net/ethernet/qlogic/qed/qed_sriov.c flags->rx_accept_filter &= ~mask; mask 3024 drivers/net/ethernet/qlogic/qed/qed_sriov.c flags->tx_accept_filter &= ~mask; mask 5114 drivers/net/ethernet/qlogic/qed/qed_sriov.c u8 mask; mask 5117 drivers/net/ethernet/qlogic/qed/qed_sriov.c mask = QED_ACCEPT_UCAST_UNMATCHED | QED_ACCEPT_MCAST_UNMATCHED; mask 5146 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (vf_info->rx_accept_mode & mask) { mask 5151 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (vf_info->tx_accept_mode & mask) { mask 5158 drivers/net/ethernet/qlogic/qed/qed_sriov.c flags->rx_accept_filter &= ~mask; mask 5159 drivers/net/ethernet/qlogic/qed/qed_sriov.c flags->tx_accept_filter &= ~mask; mask 584 drivers/net/ethernet/qlogic/qed/qed_vf.c enum qed_tunn_mode mask, u8 *p_cls) mask 587 drivers/net/ethernet/qlogic/qed/qed_vf.c p_req->tun_mode_update_mask |= BIT(mask); mask 590 drivers/net/ethernet/qlogic/qed/qed_vf.c p_req->tunn_mode |= BIT(mask); mask 599 drivers/net/ethernet/qlogic/qed/qed_vf.c enum qed_tunn_mode mask, mask 608 drivers/net/ethernet/qlogic/qed/qed_vf.c __qed_vf_prep_tunn_req_tlv(p_req, p_src, mask, p_cls); mask 1788 drivers/net/ethernet/qlogic/qede/qede_filter.c if ((match.key->src && match.mask->src != U16_MAX) || mask 1789 drivers/net/ethernet/qlogic/qede/qede_filter.c (match.key->dst && match.mask->dst != U16_MAX)) { mask 1815 drivers/net/ethernet/qlogic/qede/qede_filter.c memcmp(&match.mask->src, &addr, sizeof(addr))) || mask 1817 drivers/net/ethernet/qlogic/qede/qede_filter.c memcmp(&match.mask->dst, &addr, sizeof(addr)))) { mask 1841 drivers/net/ethernet/qlogic/qede/qede_filter.c if ((match.key->src && match.mask->src != U32_MAX) || mask 1842 drivers/net/ethernet/qlogic/qede/qede_filter.c (match.key->dst && match.mask->dst != U32_MAX)) { mask 453 drivers/net/ethernet/qlogic/qede/qede_ptp.c ptp->cc.mask = CYCLECOUNTER_MASK(64); mask 391 drivers/net/ethernet/qlogic/qla3xxx.c u32 mask; mask 409 drivers/net/ethernet/qlogic/qla3xxx.c mask = 1 << (FM93C56A_CMD_BITS - 1); mask 413 drivers/net/ethernet/qlogic/qla3xxx.c dataBit = (cmd & mask) mask 432 drivers/net/ethernet/qlogic/qla3xxx.c mask = 1 << (addrBits - 1); mask 436 drivers/net/ethernet/qlogic/qla3xxx.c dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 mask 2132 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h void *tmpl_hdr, u32 mask) mask 2134 drivers/net/ethernet/qlogic/qlcnic/qlcnic.h adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask); mask 431 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 mask; mask 438 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); mask 439 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c writel(0, adapter->ahw->pci_base0 + mask); mask 444 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 mask; mask 446 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); mask 447 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c writel(1, adapter->ahw->pci_base0 + mask); mask 2344 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c u32 mask, resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED; mask 2366 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK); mask 2367 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c writel(0, adapter->ahw->pci_base0 + mask); mask 86 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 mask; mask 92 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 mask; mask 1649 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c int duration, u32 mask, u32 status) mask 1661 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c if ((value & mask) != status) { mask 1680 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c value, mask, status); mask 1785 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c value &= p_rmw_hdr->mask; mask 1849 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c delay, poll->mask, mask 1858 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c poll->mask, mask 1894 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c poll->mask, poll->status); mask 1948 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c poll->mask, poll->status)){ mask 1727 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c static int qlcnic_set_dump_mask(struct qlcnic_adapter *adapter, u32 mask) mask 1735 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c mask); mask 1739 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c fw_dump->cap_mask = mask; mask 1742 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c qlcnic_store_cap_mask(adapter, fw_dump->tmpl_hdr, mask); mask 1744 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c netdev_info(netdev, "Driver mask changed to: 0x%x\n", mask); mask 51 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u8 mask; mask 57 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c u8 mask; mask 316 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c void qlcnic_82xx_store_cap_mask(void *tmpl_hdr, u32 mask) mask 320 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c hdr->drv_cap_mask = mask; mask 371 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c void qlcnic_83xx_store_cap_mask(void *tmpl_hdr, u32 mask) mask 376 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c hdr->drv_cap_mask = mask; mask 870 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c entry->hdr.mask); mask 879 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c entry->hdr.mask); mask 900 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c entry->hdr.type, entry->hdr.mask, size, mask 1354 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (!(entry->hdr.mask & fw_dump->cap_mask)) { mask 952 drivers/net/ethernet/qualcomm/emac/emac-mac.c writel(adpt->irq.mask, adpt->base + EMAC_INT_MASK); mask 1233 drivers/net/ethernet/qualcomm/emac/emac-mac.c adpt->rx_q.intr = adpt->irq.mask & ISR_RX_PKT; mask 73 drivers/net/ethernet/qualcomm/emac/emac.c void emac_reg_update32(void __iomem *addr, u32 mask, u32 val) mask 77 drivers/net/ethernet/qualcomm/emac/emac.c writel(((data & ~mask) | val), addr); mask 110 drivers/net/ethernet/qualcomm/emac/emac.c irq->mask |= rx_q->intr; mask 111 drivers/net/ethernet/qualcomm/emac/emac.c writel(irq->mask, adpt->base + EMAC_INT_MASK); mask 138 drivers/net/ethernet/qualcomm/emac/emac.c status = isr & irq->mask; mask 154 drivers/net/ethernet/qualcomm/emac/emac.c irq->mask &= ~rx_q->intr; mask 168 drivers/net/ethernet/qualcomm/emac/emac.c writel(irq->mask, adpt->base + EMAC_INT_MASK); mask 632 drivers/net/ethernet/qualcomm/emac/emac.c adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK; mask 321 drivers/net/ethernet/qualcomm/emac/emac.h u32 mask; mask 381 drivers/net/ethernet/qualcomm/emac/emac.h void emac_reg_update32(void __iomem *addr, u32 mask, u32 val); mask 159 drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c data_format = flags->flags & flags->mask; mask 323 drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c port->data_format = flags->flags & flags->mask; mask 357 drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c f.mask = ~0; mask 574 drivers/net/ethernet/realtek/8139cp.c u16 mask; mask 582 drivers/net/ethernet/realtek/8139cp.c mask = cpr16(IntrMask); mask 583 drivers/net/ethernet/realtek/8139cp.c if (!mask) mask 766 drivers/net/ethernet/realtek/8139too.c unsigned long mask; mask 808 drivers/net/ethernet/realtek/8139too.c if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { mask 895 drivers/net/ethernet/realtek/r8169_main.c static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, mask 900 drivers/net/ethernet/realtek/r8169_main.c r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); mask 1124 drivers/net/ethernet/realtek/r8169_main.c static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, mask 1127 drivers/net/ethernet/realtek/r8169_main.c BUG_ON((addr & 3) || (mask == 0)); mask 1129 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); mask 1134 drivers/net/ethernet/realtek/r8169_main.c static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, mask 1137 drivers/net/ethernet/realtek/r8169_main.c _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); mask 1153 drivers/net/ethernet/realtek/r8169_main.c static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, mask 1159 drivers/net/ethernet/realtek/r8169_main.c rtl_eri_write(tp, addr, mask, (val & ~m) | p); mask 1162 drivers/net/ethernet/realtek/r8169_main.c static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, mask 1165 drivers/net/ethernet/realtek/r8169_main.c rtl_w0w1_eri(tp, addr, mask, p, 0); mask 1168 drivers/net/ethernet/realtek/r8169_main.c static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, mask 1171 drivers/net/ethernet/realtek/r8169_main.c rtl_w0w1_eri(tp, addr, mask, 0, m); mask 1174 drivers/net/ethernet/realtek/r8169_main.c static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) mask 1176 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); mask 1181 drivers/net/ethernet/realtek/r8169_main.c static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) mask 1186 drivers/net/ethernet/realtek/r8169_main.c static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, mask 1190 drivers/net/ethernet/realtek/r8169_main.c RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); mask 1194 drivers/net/ethernet/realtek/r8169_main.c static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, mask 1197 drivers/net/ethernet/realtek/r8169_main.c _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, mask 1461 drivers/net/ethernet/realtek/r8169_main.c u8 mask; mask 1492 drivers/net/ethernet/realtek/r8169_main.c options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; mask 1494 drivers/net/ethernet/realtek/r8169_main.c options |= cfg[i].mask; mask 2139 drivers/net/ethernet/realtek/r8169_main.c u16 mask; mask 2229 drivers/net/ethernet/realtek/r8169_main.c while ((reg & p->mask) != p->val) mask 4403 drivers/net/ethernet/realtek/r8169_main.c u16 mask; mask 4413 drivers/net/ethernet/realtek/r8169_main.c w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; mask 1059 drivers/net/ethernet/renesas/ravb.h int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value); mask 59 drivers/net/ethernet/renesas/ravb_main.c int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) mask 64 drivers/net/ethernet/renesas/ravb_main.c if ((ravb_read(ndev, reg) & mask) == value) mask 129 drivers/net/ethernet/renesas/ravb_main.c static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) mask 134 drivers/net/ethernet/renesas/ravb_main.c ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); mask 912 drivers/net/ethernet/renesas/ravb_main.c int mask = BIT(q); mask 919 drivers/net/ethernet/renesas/ravb_main.c if (!((ris0 & mask) || (tis & mask))) mask 923 drivers/net/ethernet/renesas/ravb_main.c if (ris0 & mask) { mask 925 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); mask 930 drivers/net/ethernet/renesas/ravb_main.c if (tis & mask) { mask 933 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); mask 945 drivers/net/ethernet/renesas/ravb_main.c ravb_modify(ndev, RIC0, mask, mask); mask 946 drivers/net/ethernet/renesas/ravb_main.c ravb_modify(ndev, TIC, mask, mask); mask 948 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, mask, RIE0); mask 949 drivers/net/ethernet/renesas/ravb_main.c ravb_write(ndev, mask, TIE); mask 1211 drivers/net/ethernet/renesas/sh_eth.c static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) mask 1221 drivers/net/ethernet/renesas/sh_eth.c pir |= mask; mask 1223 drivers/net/ethernet/renesas/sh_eth.c pir &= ~mask; mask 1805 drivers/net/ethernet/renesas/sh_eth.c u32 mask; mask 1851 drivers/net/ethernet/renesas/sh_eth.c mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; mask 1853 drivers/net/ethernet/renesas/sh_eth.c mask &= ~EESR_ADE; mask 1854 drivers/net/ethernet/renesas/sh_eth.c if (intr_status & mask) { mask 427 drivers/net/ethernet/sfc/bitfield.h #define EFX_AND_OWORD(oword, from, mask) \ mask 429 drivers/net/ethernet/sfc/bitfield.h (oword).u64[0] = (from).u64[0] & (mask).u64[0]; \ mask 430 drivers/net/ethernet/sfc/bitfield.h (oword).u64[1] = (from).u64[1] & (mask).u64[1]; \ mask 433 drivers/net/ethernet/sfc/bitfield.h #define EFX_AND_QWORD(qword, from, mask) \ mask 434 drivers/net/ethernet/sfc/bitfield.h (qword).u64[0] = (from).u64[0] & (mask).u64[0] mask 436 drivers/net/ethernet/sfc/bitfield.h #define EFX_OR_OWORD(oword, from, mask) \ mask 438 drivers/net/ethernet/sfc/bitfield.h (oword).u64[0] = (from).u64[0] | (mask).u64[0]; \ mask 439 drivers/net/ethernet/sfc/bitfield.h (oword).u64[1] = (from).u64[1] | (mask).u64[1]; \ mask 1820 drivers/net/ethernet/sfc/ef10.c static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) mask 1850 drivers/net/ethernet/sfc/ef10.c mask[0] = raw_mask[0]; mask 1851 drivers/net/ethernet/sfc/ef10.c mask[1] = raw_mask[1]; mask 1854 drivers/net/ethernet/sfc/ef10.c mask[0] = raw_mask[0] & 0xffffffff; mask 1855 drivers/net/ethernet/sfc/ef10.c mask[1] = raw_mask[0] >> 32; mask 1856 drivers/net/ethernet/sfc/ef10.c mask[2] = raw_mask[1] & 0xffffffff; mask 1862 drivers/net/ethernet/sfc/ef10.c DECLARE_BITMAP(mask, EF10_STAT_COUNT); mask 1864 drivers/net/ethernet/sfc/ef10.c efx_ef10_get_stat_mask(efx, mask); mask 1866 drivers/net/ethernet/sfc/ef10.c mask, names); mask 1872 drivers/net/ethernet/sfc/ef10.c DECLARE_BITMAP(mask, EF10_STAT_COUNT); mask 1877 drivers/net/ethernet/sfc/ef10.c efx_ef10_get_stat_mask(efx, mask); mask 1880 drivers/net/ethernet/sfc/ef10.c for_each_set_bit(index, mask, EF10_STAT_COUNT) { mask 1941 drivers/net/ethernet/sfc/ef10.c DECLARE_BITMAP(mask, EF10_STAT_COUNT); mask 1946 drivers/net/ethernet/sfc/ef10.c efx_ef10_get_stat_mask(efx, mask); mask 1954 drivers/net/ethernet/sfc/ef10.c efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, mask 1995 drivers/net/ethernet/sfc/ef10.c DECLARE_BITMAP(mask, EF10_STAT_COUNT); mask 2014 drivers/net/ethernet/sfc/ef10.c efx_ef10_get_stat_mask(efx, mask); mask 2048 drivers/net/ethernet/sfc/ef10.c efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, mask 802 drivers/net/ethernet/sfc/ethtool.c static inline void ip6_fill_mask(__be32 *mask) mask 804 drivers/net/ethernet/sfc/ethtool.c mask[0] = mask[1] = mask[2] = mask[3] = ~(__be32)0; mask 1066 drivers/net/ethernet/sfc/ethtool.c static inline bool ip6_mask_is_full(__be32 mask[4]) mask 1068 drivers/net/ethernet/sfc/ethtool.c return !~(mask[0] & mask[1] & mask[2] & mask[3]); mask 1071 drivers/net/ethernet/sfc/ethtool.c static inline bool ip6_mask_is_empty(__be32 mask[4]) mask 1073 drivers/net/ethernet/sfc/ethtool.c return !(mask[0] | mask[1] | mask[2] | mask[3]); mask 427 drivers/net/ethernet/sfc/falcon/bitfield.h #define EF4_AND_OWORD(oword, from, mask) \ mask 429 drivers/net/ethernet/sfc/falcon/bitfield.h (oword).u64[0] = (from).u64[0] & (mask).u64[0]; \ mask 430 drivers/net/ethernet/sfc/falcon/bitfield.h (oword).u64[1] = (from).u64[1] & (mask).u64[1]; \ mask 433 drivers/net/ethernet/sfc/falcon/bitfield.h #define EF4_OR_OWORD(oword, from, mask) \ mask 435 drivers/net/ethernet/sfc/falcon/bitfield.h (oword).u64[0] = (from).u64[0] | (mask).u64[0]; \ mask 436 drivers/net/ethernet/sfc/falcon/bitfield.h (oword).u64[1] = (from).u64[1] | (mask).u64[1]; \ mask 780 drivers/net/ethernet/sfc/falcon/ethtool.c static inline void ip6_fill_mask(__be32 *mask) mask 782 drivers/net/ethernet/sfc/falcon/ethtool.c mask[0] = mask[1] = mask[2] = mask[3] = ~(__be32)0; mask 1011 drivers/net/ethernet/sfc/falcon/ethtool.c static inline bool ip6_mask_is_full(__be32 mask[4]) mask 1013 drivers/net/ethernet/sfc/falcon/ethtool.c return !~(mask[0] & mask[1] & mask[2] & mask[3]); mask 1016 drivers/net/ethernet/sfc/falcon/ethtool.c static inline bool ip6_mask_is_empty(__be32 mask[4]) mask 1018 drivers/net/ethernet/sfc/falcon/ethtool.c return !(mask[0] | mask[1] | mask[2] | mask[3]); mask 121 drivers/net/ethernet/sfc/falcon/falcon_boards.c static int ef4_check_lm87(struct ef4_nic *efx, unsigned mask) mask 140 drivers/net/ethernet/sfc/falcon/falcon_boards.c alarms &= mask; mask 187 drivers/net/ethernet/sfc/falcon/falcon_boards.c static inline int ef4_check_lm87(struct ef4_nic *efx, unsigned mask) mask 92 drivers/net/ethernet/sfc/falcon/farch.c const ef4_oword_t *mask) mask 94 drivers/net/ethernet/sfc/falcon/farch.c return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || mask 95 drivers/net/ethernet/sfc/falcon/farch.c ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); mask 104 drivers/net/ethernet/sfc/falcon/farch.c ef4_oword_t mask, imask, original, reg, buf; mask 108 drivers/net/ethernet/sfc/falcon/farch.c mask = imask = regs[i].mask; mask 115 drivers/net/ethernet/sfc/falcon/farch.c if (!EF4_EXTRACT_OWORD32(mask, j, j)) mask 119 drivers/net/ethernet/sfc/falcon/farch.c EF4_AND_OWORD(reg, original, mask); mask 125 drivers/net/ethernet/sfc/falcon/farch.c if (ef4_masked_compare_oword(®, &buf, &mask)) mask 129 drivers/net/ethernet/sfc/falcon/farch.c EF4_OR_OWORD(reg, original, mask); mask 135 drivers/net/ethernet/sfc/falcon/farch.c if (ef4_masked_compare_oword(®, &buf, &mask)) mask 148 drivers/net/ethernet/sfc/falcon/farch.c EF4_OWORD_VAL(buf), address, EF4_OWORD_VAL(mask)); mask 80 drivers/net/ethernet/sfc/falcon/mdio_10g.c int mask = mmd_mask; mask 84 drivers/net/ethernet/sfc/falcon/mdio_10g.c while (mask) { mask 85 drivers/net/ethernet/sfc/falcon/mdio_10g.c if (mask & 1) { mask 96 drivers/net/ethernet/sfc/falcon/mdio_10g.c mask = mask >> 1; mask 100 drivers/net/ethernet/sfc/falcon/mdio_10g.h int mask, bool state) mask 102 drivers/net/ethernet/sfc/falcon/mdio_10g.h mdio_set_flag(&efx->mdio, efx->mdio.prtad, devad, addr, mask, state); mask 447 drivers/net/ethernet/sfc/falcon/nic.c const unsigned long *mask, u8 *names) mask 452 drivers/net/ethernet/sfc/falcon/nic.c for_each_set_bit(index, mask, count) { mask 481 drivers/net/ethernet/sfc/falcon/nic.c const unsigned long *mask, mask 486 drivers/net/ethernet/sfc/falcon/nic.c for_each_set_bit(index, mask, count) { mask 491 drivers/net/ethernet/sfc/falcon/nic.h ef4_oword_t mask; mask 501 drivers/net/ethernet/sfc/falcon/nic.h const unsigned long *mask, u8 *names); mask 503 drivers/net/ethernet/sfc/falcon/nic.h const unsigned long *mask, u64 *stats, mask 94 drivers/net/ethernet/sfc/farch.c const efx_oword_t *mask) mask 96 drivers/net/ethernet/sfc/farch.c return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || mask 97 drivers/net/ethernet/sfc/farch.c ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); mask 106 drivers/net/ethernet/sfc/farch.c efx_oword_t mask, imask, original, reg, buf; mask 110 drivers/net/ethernet/sfc/farch.c mask = imask = regs[i].mask; mask 117 drivers/net/ethernet/sfc/farch.c if (!EFX_EXTRACT_OWORD32(mask, j, j)) mask 121 drivers/net/ethernet/sfc/farch.c EFX_AND_OWORD(reg, original, mask); mask 127 drivers/net/ethernet/sfc/farch.c if (efx_masked_compare_oword(®, &buf, &mask)) mask 131 drivers/net/ethernet/sfc/farch.c EFX_OR_OWORD(reg, original, mask); mask 137 drivers/net/ethernet/sfc/farch.c if (efx_masked_compare_oword(®, &buf, &mask)) mask 150 drivers/net/ethernet/sfc/farch.c EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); mask 312 drivers/net/ethernet/sfc/mcdi_mon.c u32 mask; mask 328 drivers/net/ethernet/sfc/mcdi_mon.c mask = MCDI_DWORD(outbuf, SENSOR_INFO_OUT_MASK); mask 329 drivers/net/ethernet/sfc/mcdi_mon.c n_sensors += hweight32(mask & ~(1 << MC_CMD_SENSOR_PAGE0_NEXT)); mask 331 drivers/net/ethernet/sfc/mcdi_mon.c } while (mask & (1 << MC_CMD_SENSOR_PAGE0_NEXT)); mask 394 drivers/net/ethernet/sfc/mcdi_mon.c mask = (MCDI_DWORD(outbuf, mask 400 drivers/net/ethernet/sfc/mcdi_mon.c MC_CMD_SENSOR_INFO_OUT_LEN(hweight32(mask))) { mask 405 drivers/net/ethernet/sfc/mcdi_mon.c } while (!(mask & (1 << type % 32))); mask 454 drivers/net/ethernet/sfc/nic.c const unsigned long *mask, u8 *names) mask 459 drivers/net/ethernet/sfc/nic.c for_each_set_bit(index, mask, count) { mask 488 drivers/net/ethernet/sfc/nic.c const unsigned long *mask, mask 493 drivers/net/ethernet/sfc/nic.c for_each_set_bit(index, mask, count) { mask 672 drivers/net/ethernet/sfc/nic.h efx_oword_t mask; mask 682 drivers/net/ethernet/sfc/nic.h const unsigned long *mask, u8 *names); mask 684 drivers/net/ethernet/sfc/nic.h const unsigned long *mask, u64 *stats, mask 260 drivers/net/ethernet/smsc/smc911x.c unsigned mask, cfg, cr; mask 298 drivers/net/ethernet/smsc/smc911x.c mask = INT_EN_TDFA_EN_ | INT_EN_TSFL_EN_ | INT_EN_RSFL_EN_ | mask 302 drivers/net/ethernet/smsc/smc911x.c mask|=INT_EN_RDFL_EN_; mask 304 drivers/net/ethernet/smsc/smc911x.c mask|=INT_EN_RDFO_EN_; mask 306 drivers/net/ethernet/smsc/smc911x.c SMC_ENABLE_INT(lp, mask); mask 1002 drivers/net/ethernet/smsc/smc911x.c unsigned int status, mask, timeout; mask 1017 drivers/net/ethernet/smsc/smc911x.c mask = SMC_GET_INT_EN(lp); mask 1028 drivers/net/ethernet/smsc/smc911x.c status, mask, status & ~mask); mask 1030 drivers/net/ethernet/smsc/smc911x.c status &= mask; mask 1037 drivers/net/ethernet/smsc/smc911x.c mask &= ~INT_EN_SW_INT_EN_; mask 1157 drivers/net/ethernet/smsc/smc911x.c SMC_SET_INT_EN(lp, mask); mask 1251 drivers/net/ethernet/smsc/smc911x.c int status, mask; mask 1258 drivers/net/ethernet/smsc/smc911x.c mask = SMC_GET_INT_EN(lp); mask 1261 drivers/net/ethernet/smsc/smc911x.c status, mask); mask 1264 drivers/net/ethernet/smsc/smc911x.c mask = SMC_GET_TX_CFG(lp); mask 1265 drivers/net/ethernet/smsc/smc911x.c SMC_SET_TX_CFG(lp, mask | TX_CFG_TXS_DUMP_ | TX_CFG_TXD_DUMP_); mask 1786 drivers/net/ethernet/smsc/smc911x.c dma_cap_mask_t mask; mask 1960 drivers/net/ethernet/smsc/smc911x.c dma_cap_zero(mask); mask 1961 drivers/net/ethernet/smsc/smc911x.c dma_cap_set(DMA_SLAVE, mask); mask 1962 drivers/net/ethernet/smsc/smc911x.c lp->rxdma = dma_request_channel(mask, NULL, NULL); mask 1963 drivers/net/ethernet/smsc/smc911x.c lp->txdma = dma_request_channel(mask, NULL, NULL); mask 1317 drivers/net/ethernet/smsc/smc9194.c byte mask; mask 1332 drivers/net/ethernet/smsc/smc9194.c mask = inb( ioaddr + INT_MASK ); mask 1340 drivers/net/ethernet/smsc/smc9194.c PRINTK2((KERN_WARNING CARDNAME ": MASK IS %x\n", mask)); mask 1343 drivers/net/ethernet/smsc/smc9194.c status = inb( ioaddr + INTERRUPT ) & mask; mask 1378 drivers/net/ethernet/smsc/smc9194.c mask &= ~IM_TX_EMPTY_INT; mask 1386 drivers/net/ethernet/smsc/smc9194.c mask &= ~IM_ALLOC_INT; mask 1391 drivers/net/ethernet/smsc/smc9194.c mask |= ( IM_TX_EMPTY_INT | IM_TX_INT ); mask 1412 drivers/net/ethernet/smsc/smc9194.c outb( mask, ioaddr + INT_MASK ); mask 1414 drivers/net/ethernet/smsc/smc9194.c PRINTK3((KERN_WARNING CARDNAME ": MASK is now %x\n", mask)); mask 213 drivers/net/ethernet/smsc/smc9194.h unsigned char mask;\ mask 215 drivers/net/ethernet/smsc/smc9194.h mask = inb( ioaddr + INT_MASK );\ mask 216 drivers/net/ethernet/smsc/smc9194.h mask |= (x);\ mask 217 drivers/net/ethernet/smsc/smc9194.h outb( mask, ioaddr + INT_MASK ); \ mask 223 drivers/net/ethernet/smsc/smc9194.h unsigned char mask;\ mask 225 drivers/net/ethernet/smsc/smc9194.h mask = inb( ioaddr + INT_MASK );\ mask 226 drivers/net/ethernet/smsc/smc9194.h mask &= ~(x);\ mask 227 drivers/net/ethernet/smsc/smc9194.h outb( mask, ioaddr + INT_MASK ); \ mask 1346 drivers/net/ethernet/smsc/smc91c92_cs.c u_short saved_bank, saved_pointer, mask, status; mask 1372 drivers/net/ethernet/smsc/smc91c92_cs.c mask = inw(ioaddr + INTERRUPT) >> 8; mask 1379 drivers/net/ethernet/smsc/smc91c92_cs.c status, mask); mask 1380 drivers/net/ethernet/smsc/smc91c92_cs.c if ((status & mask) == 0) { mask 1393 drivers/net/ethernet/smsc/smc91c92_cs.c status &= mask; mask 1396 drivers/net/ethernet/smsc/smc91c92_cs.c mask &= ~IM_TX_EMPTY_INT; mask 1402 drivers/net/ethernet/smsc/smc91c92_cs.c mask &= ~IM_ALLOC_INT; mask 1407 drivers/net/ethernet/smsc/smc91c92_cs.c mask |= (IM_TX_EMPTY_INT | IM_TX_INT); mask 1424 drivers/net/ethernet/smsc/smc91c92_cs.c mask, saved_bank, saved_pointer); mask 1427 drivers/net/ethernet/smsc/smc91c92_cs.c outw((mask<<8), ioaddr + INTERRUPT); mask 195 drivers/net/ethernet/smsc/smc91x.c unsigned char mask; \ mask 198 drivers/net/ethernet/smsc/smc91x.c mask = SMC_GET_INT_MASK(lp); \ mask 199 drivers/net/ethernet/smsc/smc91x.c mask |= (x); \ mask 200 drivers/net/ethernet/smsc/smc91x.c SMC_SET_INT_MASK(lp, mask); \ mask 206 drivers/net/ethernet/smsc/smc91x.c unsigned char mask; \ mask 209 drivers/net/ethernet/smsc/smc91x.c mask = SMC_GET_INT_MASK(lp); \ mask 210 drivers/net/ethernet/smsc/smc91x.c mask &= ~(x); \ mask 211 drivers/net/ethernet/smsc/smc91x.c SMC_SET_INT_MASK(lp, mask); \ mask 336 drivers/net/ethernet/smsc/smc91x.c int mask; mask 349 drivers/net/ethernet/smsc/smc91x.c mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; mask 351 drivers/net/ethernet/smsc/smc91x.c mask |= IM_MDINT; mask 353 drivers/net/ethernet/smsc/smc91x.c SMC_SET_INT_MASK(lp, mask); mask 764 drivers/net/ethernet/smsc/smc91x.c unsigned int mii_reg, mask; mask 769 drivers/net/ethernet/smsc/smc91x.c for (mask = 1 << (bits - 1); mask; mask >>= 1) { mask 770 drivers/net/ethernet/smsc/smc91x.c if (val & mask) mask 786 drivers/net/ethernet/smsc/smc91x.c unsigned int mii_reg, mask, val; mask 791 drivers/net/ethernet/smsc/smc91x.c for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { mask 793 drivers/net/ethernet/smsc/smc91x.c val |= mask; mask 1205 drivers/net/ethernet/smsc/smc91x.c int status, mask, timeout, card_stats; mask 1218 drivers/net/ethernet/smsc/smc91x.c mask = SMC_GET_INT_MASK(lp); mask 1228 drivers/net/ethernet/smsc/smc91x.c status, mask, mask 1234 drivers/net/ethernet/smsc/smc91x.c status &= mask; mask 1251 drivers/net/ethernet/smsc/smc91x.c mask &= ~IM_ALLOC_INT; mask 1254 drivers/net/ethernet/smsc/smc91x.c mask &= ~IM_TX_EMPTY_INT; mask 1288 drivers/net/ethernet/smsc/smc91x.c SMC_SET_INT_MASK(lp, mask); mask 1294 drivers/net/ethernet/smsc/smc91x.c mask); mask 1328 drivers/net/ethernet/smsc/smc91x.c int status, mask, eph_st, meminfo, fifo; mask 1334 drivers/net/ethernet/smsc/smc91x.c mask = SMC_GET_INT_MASK(lp); mask 1342 drivers/net/ethernet/smsc/smc91x.c status, mask, meminfo, fifo, eph_st); mask 2009 drivers/net/ethernet/smsc/smc91x.c dma_cap_mask_t mask; mask 2011 drivers/net/ethernet/smsc/smc91x.c dma_cap_zero(mask); mask 2012 drivers/net/ethernet/smsc/smc91x.c dma_cap_set(DMA_SLAVE, mask); mask 2013 drivers/net/ethernet/smsc/smc91x.c lp->dma_chan = dma_request_channel(mask, NULL, NULL); mask 1866 drivers/net/ethernet/smsc/smsc911x.c unsigned int mask = 0x01 << (bitnum & 0x1F); mask 1869 drivers/net/ethernet/smsc/smsc911x.c hash_high |= mask; mask 1871 drivers/net/ethernet/smsc/smsc911x.c hash_low |= mask; mask 2181 drivers/net/ethernet/smsc/smsc911x.c unsigned int byte_test, mask; mask 2213 drivers/net/ethernet/smsc/smsc911x.c mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_); mask 2214 drivers/net/ethernet/smsc/smsc911x.c while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to) mask 1016 drivers/net/ethernet/smsc/smsc9420.c u32 mask = 1 << (bit_num & 0x1F); mask 1019 drivers/net/ethernet/smsc/smsc9420.c hash_hi |= mask; mask 1021 drivers/net/ethernet/smsc/smsc9420.c hash_lo |= mask; mask 361 drivers/net/ethernet/socionext/netsec.c static int netsec_wait_while_busy(struct netsec_priv *priv, u32 addr, u32 mask) mask 365 drivers/net/ethernet/socionext/netsec.c while (--timeout && netsec_read(priv, addr) & mask) mask 371 drivers/net/ethernet/socionext/netsec.c while (--timeout && netsec_read(priv, addr) & mask) mask 406 drivers/net/ethernet/socionext/netsec.c u32 addr, u32 mask) mask 416 drivers/net/ethernet/socionext/netsec.c } while (--timeout && (data & mask)); mask 429 drivers/net/ethernet/socionext/netsec.c } while (--timeout && (data & mask)); mask 73 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c u32 mask, u32 value) mask 78 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c data &= ~mask; mask 79 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c data |= (value & mask); mask 147 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; mask 107 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c int mask, int val, unsigned int offset) mask 112 drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c temp = (temp & ~(mask)) | val; mask 68 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c #define HIWORD_UPDATE(val, mask, shift) \ mask 69 drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c ((val) << (shift) | (mask) << ((shift) + 16)) mask 25 drivers/net/ethernet/stmicro/stmmac/dwmac5.c unsigned long loc, mask; mask 31 drivers/net/ethernet/stmicro/stmmac/dwmac5.c mask = value; mask 32 drivers/net/ethernet/stmicro/stmmac/dwmac5.c for_each_set_bit(loc, &mask, 32) { mask 612 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c unsigned long loc, mask; mask 618 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c mask = value; mask 619 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c for_each_set_bit(loc, &mask, 32) { mask 367 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause; mask 373 drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c mask &= (ADVERTISED_1000baseT_Half | mask 815 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 834 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c phylink_set(mask, 1000baseT_Full); mask 835 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c phylink_set(mask, 1000baseX_Full); mask 857 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c phylink_set(mask, 10baseT_Half); mask 858 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c phylink_set(mask, 100baseT_Half); mask 859 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c phylink_set(mask, 1000baseT_Half); mask 864 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c bitmap_andnot(supported, supported, mask, mask 868 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c bitmap_andnot(state->advertising, state->advertising, mask, mask 1099 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c sel->keys[0].mask = ~0x0; mask 1295 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c struct flow_dissector_key_ipv4_addrs key, mask; mask 1341 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c rule->match.mask = (void *)&mask; mask 1345 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c mask.src = src_mask; mask 1346 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c mask.dst = dst_mask; mask 1419 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c struct flow_dissector_key_ports mask; mask 1468 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c rule->match.mask = (void *)&masks; mask 1473 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c masks.mask.src = src_mask; mask 1474 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c masks.mask.dst = dst_mask; mask 96 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c u32 off, data, mask, real_off, rem; mask 106 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c mask = sel->keys[0].mask; mask 136 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_en = (mask << (rem * 8)) & mask 143 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c frag->val.match_en = (mask >> (rem * 8)) & mask 152 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c entry->val.match_en = mask; mask 427 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c hw_match = ntohl(match.key->src) & ntohl(match.mask->src); mask 435 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c hw_match = ntohl(match.key->dst) & ntohl(match.mask->dst); mask 475 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c hw_match = ntohs(match.key->src) & ntohs(match.mask->src); mask 483 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c hw_match = ntohs(match.key->dst) & ntohs(match.mask->dst); mask 1169 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); mask 4073 drivers/net/ethernet/sun/cassini.c int mask, pending = 0, reset = 0; mask 4108 drivers/net/ethernet/sun/cassini.c if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { mask 4113 drivers/net/ethernet/sun/cassini.c if ((mask & rmask) == 0) mask 2122 drivers/net/ethernet/sun/cassini.h u16 mask, val; mask 432 drivers/net/ethernet/sun/niu.c u64 uninitialized_var(sig), mask, val; mask 495 drivers/net/ethernet/sun/niu.c mask = val; mask 500 drivers/net/ethernet/sun/niu.c mask = val; mask 509 drivers/net/ethernet/sun/niu.c if ((sig & mask) == val) mask 515 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { mask 517 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); mask 529 drivers/net/ethernet/sun/niu.c u64 uninitialized_var(sig), mask, val; mask 588 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P0_BITS; mask 599 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P1_BITS; mask 615 drivers/net/ethernet/sun/niu.c if ((sig & mask) == val) mask 621 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { mask 623 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); mask 758 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; mask 841 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P0_BITS; mask 852 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P1_BITS; mask 866 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { mask 872 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); mask 911 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; mask 1007 drivers/net/ethernet/sun/niu.c mask = val; mask 1012 drivers/net/ethernet/sun/niu.c mask = val; mask 1019 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { mask 1021 drivers/net/ethernet/sun/niu.c np->port, (int)(sig & mask), (int)val); mask 2106 drivers/net/ethernet/sun/niu.c u64 sig, mask, val; mask 2111 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P0_BITS; mask 2122 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P1_BITS; mask 2136 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) mask 2354 drivers/net/ethernet/sun/niu.c u64 ctrl_val, test_cfg_val, sig, mask, val; mask 2438 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P0_BITS; mask 2449 drivers/net/ethernet/sun/niu.c mask = ESR_INT_SIGNALS_P1_BITS; mask 2463 drivers/net/ethernet/sun/niu.c if ((sig & mask) != val) { mask 2656 drivers/net/ethernet/sun/niu.c u64 val, mask; mask 2663 drivers/net/ethernet/sun/niu.c mask = 1 << index; mask 2666 drivers/net/ethernet/sun/niu.c mask = 1 << (index + 1); mask 2671 drivers/net/ethernet/sun/niu.c val |= mask; mask 2673 drivers/net/ethernet/sun/niu.c val &= ~mask; mask 2799 drivers/net/ethernet/sun/niu.c u64 *key, u64 *mask) mask 2810 drivers/net/ethernet/sun/niu.c mask[0] = nr64(TCAM_KEY_MASK_0); mask 2811 drivers/net/ethernet/sun/niu.c mask[1] = nr64(TCAM_KEY_MASK_1); mask 2812 drivers/net/ethernet/sun/niu.c mask[2] = nr64(TCAM_KEY_MASK_2); mask 2813 drivers/net/ethernet/sun/niu.c mask[3] = nr64(TCAM_KEY_MASK_3); mask 2820 drivers/net/ethernet/sun/niu.c u64 *key, u64 *mask) mask 2826 drivers/net/ethernet/sun/niu.c nw64(TCAM_KEY_MASK_0, mask[0]); mask 2827 drivers/net/ethernet/sun/niu.c nw64(TCAM_KEY_MASK_1, mask[1]); mask 2828 drivers/net/ethernet/sun/niu.c nw64(TCAM_KEY_MASK_2, mask[2]); mask 2829 drivers/net/ethernet/sun/niu.c nw64(TCAM_KEY_MASK_3, mask[3]); mask 3086 drivers/net/ethernet/sun/niu.c u64 mask, u64 base, int enable) mask 3092 drivers/net/ethernet/sun/niu.c (mask & ~(u64)0x1f) != 0 || mask 3100 drivers/net/ethernet/sun/niu.c val |= (mask << FLW_PRT_SEL_MASK_SHIFT); mask 3308 drivers/net/ethernet/sun/niu.c gfp_t mask, int start_index) mask 3314 drivers/net/ethernet/sun/niu.c page = alloc_page(mask); mask 3339 drivers/net/ethernet/sun/niu.c static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) mask 3345 drivers/net/ethernet/sun/niu.c int err = niu_rbr_add_page(np, rp, mask, index); mask 3494 drivers/net/ethernet/sun/niu.c static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) mask 3501 drivers/net/ethernet/sun/niu.c err = niu_rbr_add_page(np, rp, mask, index); mask 4614 drivers/net/ethernet/sun/niu.c u64 val, mask; mask 4618 drivers/net/ethernet/sun/niu.c mask = (u64)1 << np->port; mask 4620 drivers/net/ethernet/sun/niu.c val |= TXC_CONTROL_ENABLE | mask; mask 4622 drivers/net/ethernet/sun/niu.c val &= ~mask; mask 1509 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c unsigned int mask; mask 1557 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c mask = 0; mask 1561 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c mask |= (1 << prio); mask 1568 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c mask |= (1 << prio); mask 1572 drivers/net/ethernet/synopsys/dwc-xlgmac-hw.c regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); mask 1180 drivers/net/ethernet/ti/cpmac.c u32 mask; mask 1210 drivers/net/ethernet/ti/cpmac.c mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE); mask 1211 drivers/net/ethernet/ti/cpmac.c if (mask) mask 1217 drivers/net/ethernet/ti/cpmac.c mask &= 0x7fffffff; mask 1218 drivers/net/ethernet/ti/cpmac.c if (mask & (mask - 1)) { mask 1220 drivers/net/ethernet/ti/cpmac.c mask = 0; mask 1223 drivers/net/ethernet/ti/cpmac.c cpmac_mii->phy_mask = ~(mask | 0x80000000); mask 44 drivers/net/ethernet/ti/cpsw-phy-sel.c u32 mask; mask 76 drivers/net/ethernet/ti/cpsw-phy-sel.c mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); mask 77 drivers/net/ethernet/ti/cpsw-phy-sel.c mask |= BIT(slave + 4); mask 94 drivers/net/ethernet/ti/cpsw-phy-sel.c reg &= ~mask; mask 104 drivers/net/ethernet/ti/cpsw-phy-sel.c u32 mask; mask 133 drivers/net/ethernet/ti/cpsw-phy-sel.c mask = GMII_SEL_MODE_MASK; mask 136 drivers/net/ethernet/ti/cpsw-phy-sel.c mask = GMII_SEL_MODE_MASK << 4; mask 147 drivers/net/ethernet/ti/cpsw-phy-sel.c reg &= ~mask; mask 182 drivers/net/ethernet/ti/cpsw.c int mask, flags, ret; mask 191 drivers/net/ethernet/ti/cpsw.c mask = cpsw->data.dual_emac ? ALE_PORT_HOST : ALE_ALL_PORTS; mask 195 drivers/net/ethernet/ti/cpsw.c ret = cpsw_ale_add_mcast(cpsw->ale, addr, mask, flags, vid, 0); mask 1028 drivers/net/ethernet/ti/cpsw.c u32 shift, mask, val; mask 1034 drivers/net/ethernet/ti/cpsw.c mask = 7 << shift; mask 1035 drivers/net/ethernet/ti/cpsw.c val = val & mask; mask 1044 drivers/net/ethernet/ti/cpsw.c u32 shift, mask, val; mask 1050 drivers/net/ethernet/ti/cpsw.c mask = (1 << --fifo) << shift; mask 1051 drivers/net/ethernet/ti/cpsw.c val = on ? val | mask : val & ~mask; mask 23 drivers/net/ethernet/ti/cpsw_ale.c #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask)) mask 245 drivers/net/ethernet/ti/cpsw_ale.c int mask; mask 247 drivers/net/ethernet/ti/cpsw_ale.c mask = cpsw_ale_get_port_mask(ale_entry, mask 249 drivers/net/ethernet/ti/cpsw_ale.c if ((mask & port_mask) == 0) mask 251 drivers/net/ethernet/ti/cpsw_ale.c mask &= ~port_mask; mask 254 drivers/net/ethernet/ti/cpsw_ale.c if (mask) mask 255 drivers/net/ethernet/ti/cpsw_ale.c cpsw_ale_set_port_mask(ale_entry, mask, mask 352 drivers/net/ethernet/ti/cpsw_ale.c int idx, mask; mask 364 drivers/net/ethernet/ti/cpsw_ale.c mask = cpsw_ale_get_port_mask(ale_entry, mask 366 drivers/net/ethernet/ti/cpsw_ale.c port_mask |= mask; mask 706 drivers/net/ethernet/ti/cpsw_ale.c u32 tmp, mask; mask 718 drivers/net/ethernet/ti/cpsw_ale.c mask = BITMASK(info->bits); mask 719 drivers/net/ethernet/ti/cpsw_ale.c if (value & ~mask) mask 726 drivers/net/ethernet/ti/cpsw_ale.c tmp = (tmp & ~(mask << shift)) | (value << shift); mask 509 drivers/net/ethernet/ti/cpts.c maxsec = cpts->cc.mask; mask 529 drivers/net/ethernet/ti/cpts.c ns = cyclecounter_cyc2ns(&cpts->cc, freq, cpts->cc.mask, &frac); mask 668 drivers/net/ethernet/ti/cpts.c cpts->cc.mask = CLOCKSOURCE_MASK(32); mask 117 drivers/net/ethernet/ti/davinci_cpdma.c u32 mask; mask 130 drivers/net/ethernet/ti/davinci_cpdma.c u32 shift, mask; mask 324 drivers/net/ethernet/ti/davinci_cpdma.c val &= ~(info->mask << info->shift); mask 325 drivers/net/ethernet/ti/davinci_cpdma.c val |= (value & info->mask) << info->shift; mask 348 drivers/net/ethernet/ti/davinci_cpdma.c ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; mask 369 drivers/net/ethernet/ti/davinci_cpdma.c rmask |= chan->mask; mask 390 drivers/net/ethernet/ti/davinci_cpdma.c dma_reg_write(ctlr, chan->int_set, chan->mask); mask 426 drivers/net/ethernet/ti/davinci_cpdma.c new_rmask |= chan->mask; mask 922 drivers/net/ethernet/ti/davinci_cpdma.c chan->mask = BIT(chan_linear(chan)); mask 1327 drivers/net/ethernet/ti/davinci_cpdma.c dma_reg_write(ctlr, chan->int_clear, chan->mask); mask 1385 drivers/net/ethernet/ti/davinci_cpdma.c chan->mask); mask 1224 drivers/net/ethernet/ti/davinci_emac.c unsigned int mask; mask 1234 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; mask 1237 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; mask 1239 drivers/net/ethernet/ti/davinci_emac.c if (status & mask) { mask 1244 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; mask 1247 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; mask 1249 drivers/net/ethernet/ti/davinci_emac.c if (status & mask) { mask 1253 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; mask 1255 drivers/net/ethernet/ti/davinci_emac.c mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; mask 1257 drivers/net/ethernet/ti/davinci_emac.c if (unlikely(status & mask)) { mask 91 drivers/net/ethernet/ti/netcp_sgmii.c unsigned int i, status, mask; mask 138 drivers/net/ethernet/ti/netcp_sgmii.c mask = SGMII_REG_STATUS_LINK; mask 140 drivers/net/ethernet/ti/netcp_sgmii.c mask |= SGMII_REG_STATUS_AUTONEG; mask 145 drivers/net/ethernet/ti/netcp_sgmii.c if ((status & mask) == mask) mask 21 drivers/net/ethernet/ti/netcp_xgbepcsr.c #define reg_rmw(addr, value, mask) \ mask 22 drivers/net/ethernet/ti/netcp_xgbepcsr.c writel(((readl(addr) & (~(mask))) | \ mask 23 drivers/net/ethernet/ti/netcp_xgbepcsr.c (value & (mask))), (addr)) mask 36 drivers/net/ethernet/ti/netcp_xgbepcsr.c u32 mask; mask 135 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_1p25g_156p25mhz_cmu0[i].mask); mask 142 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_156p25mhz_cmu1[i].mask); mask 158 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_16bit_lane[i].mask); mask 177 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_phyb_10p3125g_comlane[i].mask); mask 437 drivers/net/ethernet/ti/netcp_xgbepcsr.c cfg_cm_c1_c2[i].mask); mask 49 drivers/net/ethernet/toshiba/ps3_gelic_net.c int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask) mask 54 drivers/net/ethernet/toshiba/ps3_gelic_net.c mask, 0); mask 255 drivers/net/ethernet/toshiba/ps3_gelic_net.c u64 mask; mask 265 drivers/net/ethernet/toshiba/ps3_gelic_net.c mask = card->irq_mask & (GELIC_CARD_WLAN_EVENT_RECEIVED | mask 267 drivers/net/ethernet/toshiba/ps3_gelic_net.c gelic_card_set_irq_mask(card, mask); mask 354 drivers/net/ethernet/toshiba/ps3_gelic_net.h int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask); mask 610 drivers/net/ethernet/toshiba/tc35815.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 634 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); mask 635 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); mask 637 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask); mask 638 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask); mask 641 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, mask); mask 642 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); mask 644 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, mask); mask 645 drivers/net/ethernet/toshiba/tc35815.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); mask 647 drivers/net/ethernet/toshiba/tc35815.c linkmode_andnot(phydev->supported, phydev->supported, mask); mask 527 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low) mask 533 drivers/net/ethernet/via/via-rhine.c bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); mask 541 drivers/net/ethernet/via/via-rhine.c "count: %04d\n", low ? "low" : "high", reg, mask, i); mask 545 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask) mask 547 drivers/net/ethernet/via/via-rhine.c rhine_wait_bit(rp, reg, mask, false); mask 550 drivers/net/ethernet/via/via-rhine.c static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask) mask 552 drivers/net/ethernet/via/via-rhine.c rhine_wait_bit(rp, reg, mask, true); mask 567 drivers/net/ethernet/via/via-rhine.c static void rhine_ack_events(struct rhine_private *rp, u32 mask) mask 572 drivers/net/ethernet/via/via-rhine.c iowrite8(mask >> 16, ioaddr + IntrStatus2); mask 573 drivers/net/ethernet/via/via-rhine.c iowrite16(mask, ioaddr + IntrStatus); mask 1464 drivers/net/ethernet/via/via-rhine.c static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask) mask 1470 drivers/net/ethernet/via/via-rhine.c iowrite32(mask, ioaddr + CamMask); mask 1483 drivers/net/ethernet/via/via-rhine.c static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask) mask 1489 drivers/net/ethernet/via/via-rhine.c iowrite32(mask, ioaddr + CamMask); mask 103 drivers/net/ethernet/via/via-velocity.c static void mac_get_cam_mask(struct mac_regs __iomem *regs, u8 *mask) mask 114 drivers/net/ethernet/via/via-velocity.c *mask++ = readb(&(regs->MARCAM[i])); mask 130 drivers/net/ethernet/via/via-velocity.c static void mac_set_cam_mask(struct mac_regs __iomem *regs, u8 *mask) mask 139 drivers/net/ethernet/via/via-velocity.c writeb(*mask++, &(regs->MARCAM[i])); mask 148 drivers/net/ethernet/via/via-velocity.c static void mac_set_vlan_cam_mask(struct mac_regs __iomem *regs, u8 *mask) mask 157 drivers/net/ethernet/via/via-velocity.c writeb(*mask++, &(regs->MARCAM[i])); mask 2975 drivers/net/ethernet/via/via-velocity.c u8 mask; mask 2979 drivers/net/ethernet/via/via-velocity.c mask = mask_pattern[i]; mask 2982 drivers/net/ethernet/via/via-velocity.c if (mask == 0x00) mask 2986 drivers/net/ethernet/via/via-velocity.c if ((mask & 0x01) == 0) { mask 2987 drivers/net/ethernet/via/via-velocity.c mask >>= 1; mask 2990 drivers/net/ethernet/via/via-velocity.c mask >>= 1; mask 1152 drivers/net/ethernet/via/via-velocity.h #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); mask 601 drivers/net/ethernet/wiznet/w5100.c static void w5100_socket_intr_mask(struct w5100_priv *priv, u8 mask) mask 610 drivers/net/ethernet/wiznet/w5100.c w5100_write(priv, imr, mask); mask 1380 drivers/net/ethernet/xilinx/xilinx_axienet_main.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 1392 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, Autoneg); mask 1393 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set_port_modes(mask); mask 1395 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, Asym_Pause); mask 1396 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, Pause); mask 1397 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, 1000baseX_Full); mask 1398 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, 10baseT_Full); mask 1399 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, 100baseT_Full); mask 1400 drivers/net/ethernet/xilinx/xilinx_axienet_main.c phylink_set(mask, 1000baseT_Full); mask 1402 drivers/net/ethernet/xilinx/xilinx_axienet_main.c bitmap_and(supported, supported, mask, mask 1404 drivers/net/ethernet/xilinx/xilinx_axienet_main.c bitmap_and(state->advertising, state->advertising, mask, mask 809 drivers/net/fddi/skfp/h/skfbi.h #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) mask 810 drivers/net/fddi/skfp/h/skfbi.h #define SET(io,mask) outpw((io),inpw(io)|(mask)) mask 811 drivers/net/fddi/skfp/h/skfbi.h #define GET(io,mask) (inpw(io)&(mask)) mask 812 drivers/net/fddi/skfp/h/skfbi.h #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) mask 674 drivers/net/fjes/fjes_hw.c enum REG_ICTL_MASK mask) mask 676 drivers/net/fjes/fjes_hw.c u32 ig = mask | dest_epid; mask 693 drivers/net/fjes/fjes_hw.c enum REG_ICTL_MASK intr_mask, bool mask) mask 695 drivers/net/fjes/fjes_hw.c if (mask) mask 206 drivers/net/hamradio/baycom_par.c unsigned int data, mask, mask2, descx; mask 235 drivers/net/hamradio/baycom_par.c for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; mask 236 drivers/net/hamradio/baycom_par.c i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) mask 237 drivers/net/hamradio/baycom_par.c if ((bc->modem.par96.dcd_shreg & mask) == mask2) mask 240 drivers/net/hamradio/baycom_par.c for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; mask 241 drivers/net/hamradio/baycom_par.c i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) mask 242 drivers/net/hamradio/baycom_par.c if (((bc->modem.par96.dcd_shreg & mask) == mask2) && mask 973 drivers/net/hamradio/yam.c if ((yi.cfg.mask & YAM_IOBASE) && netif_running(dev)) mask 975 drivers/net/hamradio/yam.c if ((yi.cfg.mask & YAM_IRQ) && netif_running(dev)) mask 977 drivers/net/hamradio/yam.c if ((yi.cfg.mask & YAM_BITRATE) && netif_running(dev)) mask 979 drivers/net/hamradio/yam.c if ((yi.cfg.mask & YAM_BAUDRATE) && netif_running(dev)) mask 982 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_IOBASE) { mask 986 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_IRQ) { mask 992 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_BITRATE) { mask 997 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_BAUDRATE) { mask 1002 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_MODE) { mask 1007 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_HOLDDLY) { mask 1012 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_TXDELAY) { mask 1017 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_TXTAIL) { mask 1022 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_PERSIST) { mask 1027 drivers/net/hamradio/yam.c if (yi.cfg.mask & YAM_SLOTTIME) { mask 1037 drivers/net/hamradio/yam.c yi.cfg.mask = 0xffffffff; mask 639 drivers/net/hyperv/hyperv_net.h u64 mask; mask 316 drivers/net/ieee802154/adf7242.c unsigned int mask, int line) mask 324 drivers/net/ieee802154/adf7242.c } while (((stat & mask) != status) && (cnt < MAX_POLL_LOOPS)); mask 333 drivers/net/ieee802154/adf7242.c if ((stat & mask) == status) mask 181 drivers/net/ieee802154/at86rf230.c unsigned int addr, unsigned int mask, mask 188 drivers/net/ieee802154/at86rf230.c *data = (*data & mask) >> shift; mask 195 drivers/net/ieee802154/at86rf230.c unsigned int addr, unsigned int mask, mask 205 drivers/net/ieee802154/at86rf230.c ret = regmap_update_bits(lp->regmap, addr, mask, data << shift); mask 150 drivers/net/ieee802154/atusb.c static int atusb_write_subreg(struct atusb *atusb, u8 reg, u8 mask, mask 164 drivers/net/ieee802154/atusb.c tmp = orig & ~mask; mask 165 drivers/net/ieee802154/atusb.c tmp |= (value << shift) & mask; mask 174 drivers/net/ieee802154/atusb.c unsigned int addr, unsigned int mask, mask 180 drivers/net/ieee802154/atusb.c rc = (rc & mask) >> shift; mask 1060 drivers/net/macvlan.c netdev_features_t mask; mask 1064 drivers/net/macvlan.c mask = features; mask 1067 drivers/net/macvlan.c features = netdev_increment_features(lowerdev_features, features, mask); mask 67 drivers/net/mdio.c int prtad, int devad, u16 addr, int mask, mask 76 drivers/net/mdio.c new_val = old_val | mask; mask 78 drivers/net/mdio.c new_val = old_val & ~mask; mask 55 drivers/net/phy/bcm87xx.c u16 mask = be32_to_cpup(paddr++); mask 60 drivers/net/phy/bcm87xx.c if (mask) { mask 66 drivers/net/phy/bcm87xx.c val &= mask; mask 450 drivers/net/phy/dp83867.c u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE; mask 455 drivers/net/phy/dp83867.c mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK; mask 461 drivers/net/phy/dp83867.c mask, val); mask 222 drivers/net/phy/intel-xway.c u16 mask = 0; mask 225 drivers/net/phy/intel-xway.c mask = XWAY_MDIO_INIT_MASK; mask 227 drivers/net/phy/intel-xway.c return phy_write(phydev, XWAY_MDIO_IMASK, mask); mask 397 drivers/net/phy/marvell.c u16 mask = be32_to_cpup(paddr + i + 2); mask 409 drivers/net/phy/marvell.c if (mask) { mask 415 drivers/net/phy/marvell.c val &= mask; mask 260 drivers/net/phy/mdio-mux-meson-g12a.c mux->mask = PLL_CTL0_SEL >> mux->shift; mask 22 drivers/net/phy/mdio-mux-mmioreg.c unsigned int mask; mask 57 drivers/net/phy/mdio-mux-mmioreg.c y = (x & ~s->mask) | desired_child; mask 59 drivers/net/phy/mdio-mux-mmioreg.c iowrite8((x & ~s->mask) | desired_child, p); mask 69 drivers/net/phy/mdio-mux-mmioreg.c y = (x & ~s->mask) | desired_child; mask 71 drivers/net/phy/mdio-mux-mmioreg.c iowrite16((x & ~s->mask) | desired_child, p); mask 81 drivers/net/phy/mdio-mux-mmioreg.c y = (x & ~s->mask) | desired_child; mask 83 drivers/net/phy/mdio-mux-mmioreg.c iowrite32((x & ~s->mask) | desired_child, p); mask 136 drivers/net/phy/mdio-mux-mmioreg.c s->mask = be32_to_cpup(iprop); mask 150 drivers/net/phy/mdio-mux-mmioreg.c if (be32_to_cpup(iprop) & ~s->mask) { mask 161 drivers/net/phy/micrel.c u16 mask; mask 164 drivers/net/phy/micrel.c mask = type->interrupt_level_mask; mask 166 drivers/net/phy/micrel.c mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; mask 172 drivers/net/phy/micrel.c temp &= ~mask; mask 312 drivers/net/phy/micrel.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; mask 319 drivers/net/phy/micrel.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask); mask 320 drivers/net/phy/micrel.c linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask); mask 322 drivers/net/phy/micrel.c linkmode_and(phydev->supported, phydev->supported, mask); mask 325 drivers/net/phy/micrel.c linkmode_and(phydev->advertising, phydev->advertising, mask); mask 508 drivers/net/phy/micrel.c u16 mask; mask 528 drivers/net/phy/micrel.c mask = 0xffff; mask 529 drivers/net/phy/micrel.c mask ^= maxval << (field_sz * i); mask 530 drivers/net/phy/micrel.c newval = (newval & mask) | mask 667 drivers/net/phy/micrel.c u16 mask; mask 698 drivers/net/phy/micrel.c mask = 0xffff; mask 699 drivers/net/phy/micrel.c mask ^= maxval << (field_sz * i); mask 700 drivers/net/phy/micrel.c newval = (newval & mask) | mask 48 drivers/net/phy/microchip_t1.c u16 mask; mask 90 drivers/net/phy/microchip_t1.c u8 bank, u8 offset, u16 val, u16 mask) mask 101 drivers/net/phy/microchip_t1.c new = val | (rc & (mask ^ 0xFFFF)); mask 171 drivers/net/phy/microchip_t1.c init[i].mask); mask 325 drivers/net/phy/mscc.c u16 mask; mask 333 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 338 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 343 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 348 drivers/net/phy/mscc.c .mask = VALID_CRC_CNT_CRC_MASK, mask 353 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 362 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 367 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 372 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 377 drivers/net/phy/mscc.c .mask = VALID_CRC_CNT_CRC_MASK, mask 382 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 387 drivers/net/phy/mscc.c .mask = VALID_CRC_CNT_CRC_MASK, mask 392 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 397 drivers/net/phy/mscc.c .mask = VALID_CRC_CNT_CRC_MASK, mask 402 drivers/net/phy/mscc.c .mask = ERR_CNT_MASK, mask 478 drivers/net/phy/mscc.c val = val & priv->hw_stats[i].mask; mask 61 drivers/net/phy/nxp-tja11xx.c u16 mask; mask 73 drivers/net/phy/nxp-tja11xx.c static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) mask 82 drivers/net/phy/nxp-tja11xx.c if ((ret & mask) == set) mask 92 drivers/net/phy/nxp-tja11xx.c u16 mask, u16 set) mask 96 drivers/net/phy/nxp-tja11xx.c ret = phy_modify(phydev, reg, mask, set); mask 100 drivers/net/phy/nxp-tja11xx.c return tja11xx_check(phydev, reg, mask, set); mask 267 drivers/net/phy/nxp-tja11xx.c data[i] = ret & tja11xx_hw_stats[i].mask; mask 164 drivers/net/phy/phy-core.c phy_lookup_setting(int speed, int duplex, const unsigned long *mask, bool exact) mask 171 drivers/net/phy/phy-core.c test_bit(p->bit, mask)) { mask 196 drivers/net/phy/phy-core.c unsigned long *mask) mask 203 drivers/net/phy/phy-core.c test_bit(settings[i].bit, mask) && mask 495 drivers/net/phy/phy-core.c int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, mask 504 drivers/net/phy/phy-core.c new = (ret & ~mask) | set; mask 527 drivers/net/phy/phy-core.c int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) mask 532 drivers/net/phy/phy-core.c ret = __phy_modify_changed(phydev, regnum, mask, set); mask 550 drivers/net/phy/phy-core.c int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) mask 554 drivers/net/phy/phy-core.c ret = __phy_modify_changed(phydev, regnum, mask, set); mask 571 drivers/net/phy/phy-core.c int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) mask 576 drivers/net/phy/phy-core.c ret = __phy_modify(phydev, regnum, mask, set); mask 597 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 605 drivers/net/phy/phy-core.c new = (ret & ~mask) | set; mask 630 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 635 drivers/net/phy/phy-core.c ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); mask 655 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 659 drivers/net/phy/phy-core.c ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set); mask 678 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 683 drivers/net/phy/phy-core.c ret = __phy_modify_mmd(phydev, devad, regnum, mask, set); mask 835 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 841 drivers/net/phy/phy-core.c ret = __phy_modify_changed(phydev, regnum, mask, set); mask 858 drivers/net/phy/phy-core.c u16 mask, u16 set) mask 860 drivers/net/phy/phy-core.c int ret = phy_modify_paged_changed(phydev, page, regnum, mask, set); mask 116 drivers/net/phy/phylink.c void phylink_set_port_modes(unsigned long *mask) mask 118 drivers/net/phy/phylink.c phylink_set(mask, TP); mask 119 drivers/net/phy/phylink.c phylink_set(mask, AUI); mask 120 drivers/net/phy/phylink.c phylink_set(mask, MII); mask 121 drivers/net/phy/phylink.c phylink_set(mask, FIBRE); mask 122 drivers/net/phy/phylink.c phylink_set(mask, BNC); mask 123 drivers/net/phy/phylink.c phylink_set(mask, Backplane); mask 1095 drivers/net/phy/phylink.c __ETHTOOL_DECLARE_LINK_MODE_MASK(mask); mask 1097 drivers/net/phy/phylink.c linkmode_zero(mask); mask 1098 drivers/net/phy/phylink.c phylink_set_port_modes(mask); mask 1100 drivers/net/phy/phylink.c linkmode_and(dst, dst, mask); mask 532 drivers/net/ppp/ppp_generic.c __poll_t mask; mask 537 drivers/net/ppp/ppp_generic.c mask = EPOLLOUT | EPOLLWRNORM; mask 539 drivers/net/ppp/ppp_generic.c mask |= EPOLLIN | EPOLLRDNORM; mask 541 drivers/net/ppp/ppp_generic.c mask |= EPOLLHUP; mask 549 drivers/net/ppp/ppp_generic.c mask |= EPOLLIN | EPOLLRDNORM; mask 553 drivers/net/ppp/ppp_generic.c return mask; mask 2315 drivers/net/ppp/ppp_generic.c u32 mask, seq; mask 2325 drivers/net/ppp/ppp_generic.c mask = 0xfff; mask 2328 drivers/net/ppp/ppp_generic.c mask = 0xffffff; mask 2345 drivers/net/ppp/ppp_generic.c seq |= ppp->minseq & ~mask; mask 2346 drivers/net/ppp/ppp_generic.c if ((int)(ppp->minseq - seq) > (int)(mask >> 1)) mask 2347 drivers/net/ppp/ppp_generic.c seq += mask + 1; mask 2348 drivers/net/ppp/ppp_generic.c else if ((int)(seq - ppp->minseq) > (int)(mask >> 1)) mask 2349 drivers/net/ppp/ppp_generic.c seq -= mask + 1; /* should never happen */ mask 575 drivers/net/tap.c __poll_t mask = EPOLLERR; mask 580 drivers/net/tap.c mask = 0; mask 584 drivers/net/tap.c mask |= EPOLLIN | EPOLLRDNORM; mask 589 drivers/net/tap.c mask |= EPOLLOUT | EPOLLWRNORM; mask 592 drivers/net/tap.c return mask; mask 2002 drivers/net/team/team.c netdev_features_t mask; mask 2004 drivers/net/team/team.c mask = features; mask 2012 drivers/net/team/team.c mask); mask 2016 drivers/net/team/team.c features = netdev_add_tso_features(features, mask); mask 127 drivers/net/tun.c u32 mask[2]; /* Mask of the hashed addrs */ mask 902 drivers/net/tun.c static void addr_hash_set(u32 *mask, const u8 *addr) mask 905 drivers/net/tun.c mask[n >> 5] |= (1 << (n & 31)); mask 908 drivers/net/tun.c static unsigned int addr_hash_test(const u32 *mask, const u8 *addr) mask 911 drivers/net/tun.c return mask[n >> 5] & (1 << (n & 31)); mask 948 drivers/net/tun.c memset(filter->mask, 0, sizeof(filter->mask)); mask 954 drivers/net/tun.c addr_hash_set(filter->mask, addr[n].u); mask 960 drivers/net/tun.c memset(filter->mask, ~0, sizeof(filter->mask)); mask 988 drivers/net/tun.c return addr_hash_test(filter->mask, eh->h_dest); mask 1431 drivers/net/tun.c __poll_t mask = 0; mask 1443 drivers/net/tun.c mask |= EPOLLIN | EPOLLRDNORM; mask 1453 drivers/net/tun.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1456 drivers/net/tun.c mask = EPOLLERR; mask 1459 drivers/net/tun.c return mask; mask 1059 drivers/net/usb/r8152.c u32 mask = 0xffff; mask 1064 drivers/net/usb/r8152.c data &= mask; mask 1068 drivers/net/usb/r8152.c mask <<= (shift * 8); mask 1097 drivers/net/usb/r8152.c u32 mask = 0xff; mask 1102 drivers/net/usb/r8152.c data &= mask; mask 1106 drivers/net/usb/r8152.c mask <<= (shift * 8); mask 1698 drivers/net/usb/smsc75xx.c static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask) mask 1719 drivers/net/usb/smsc75xx.c ret |= mask; mask 483 drivers/net/usb/smsc95xx.c u32 mask = 0x01 << (bitnum & 0x1F); mask 485 drivers/net/usb/smsc95xx.c pdata->hash_hi |= mask; mask 487 drivers/net/usb/smsc95xx.c pdata->hash_lo |= mask; mask 1341 drivers/net/usb/smsc95xx.c static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask) mask 1358 drivers/net/usb/smsc95xx.c ret |= mask; mask 1934 drivers/net/virtio_net.c cpumask_var_t mask; mask 1941 drivers/net/virtio_net.c if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { mask 1957 drivers/net/virtio_net.c cpumask_set_cpu(cpu, mask); mask 1961 drivers/net/virtio_net.c virtqueue_set_affinity(vi->rq[i].vq, mask); mask 1962 drivers/net/virtio_net.c virtqueue_set_affinity(vi->sq[i].vq, mask); mask 1963 drivers/net/virtio_net.c __netif_set_xps_queue(vi->dev, cpumask_bits(mask), i, false); mask 1964 drivers/net/virtio_net.c cpumask_clear(mask); mask 1968 drivers/net/virtio_net.c free_cpumask_var(mask); mask 598 drivers/net/vmxnet3/vmxnet3_defs.h u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; mask 267 drivers/net/vmxnet3/vmxnet3_drv.c u32 mask = ((1 << size) - 1) << pos; mask 268 drivers/net/vmxnet3/vmxnet3_drv.c temp &= mask; mask 3646 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ mask 3690 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[0] = 0x00; mask 3691 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ mask 3692 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ mask 3693 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[3] = 0x00; mask 3694 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ mask 3695 drivers/net/vmxnet3/vmxnet3_drv.c pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ mask 3662 drivers/net/vxlan.c int attrtype, unsigned long mask, bool changelink, mask 3677 drivers/net/vxlan.c flags = conf->flags | mask; mask 3679 drivers/net/vxlan.c flags = conf->flags | mask; mask 3681 drivers/net/vxlan.c flags = conf->flags & ~mask; mask 584 drivers/net/wan/farsync.c u64 mask; mask 597 drivers/net/wan/farsync.c mask = (u64)1 << card_index; mask 598 drivers/net/wan/farsync.c *queue |= mask; mask 159 drivers/net/wan/hdlc_cisco.c __be32 addr, mask; mask 193 drivers/net/wan/hdlc_cisco.c mask = ~cpu_to_be32(0); /* is the mask correct? */ mask 202 drivers/net/wan/hdlc_cisco.c mask = ifa->ifa_mask; mask 208 drivers/net/wan/hdlc_cisco.c addr, mask); mask 123 drivers/net/wireless/ath/ath10k/ce.c return ((offset << addr_map->lsb) & addr_map->mask); mask 130 drivers/net/wireless/ath/ath10k/ce.c return ((offset & addr_map->mask) >> (addr_map->lsb)); mask 265 drivers/net/wireless/ath/ath10k/ce.c (ctrl1_addr & ~(ctrl_regs->dmax->mask)) | mask 279 drivers/net/wireless/ath/ath10k/ce.c (ctrl1_addr & ~(ctrl_regs->src_ring->mask)) | mask 293 drivers/net/wireless/ath/ath10k/ce.c (ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) | mask 373 drivers/net/wireless/ath/ath10k/ce.c (addr & ~(srcr_wm->wm_high->mask)) | mask 385 drivers/net/wireless/ath/ath10k/ce.c (addr & ~(srcr_wm->wm_low->mask)) | mask 397 drivers/net/wireless/ath/ath10k/ce.c (addr & ~(dstr_wm->wm_high->mask)) | mask 409 drivers/net/wireless/ath/ath10k/ce.c (addr & ~(dstr_wm->wm_low->mask)) | mask 422 drivers/net/wireless/ath/ath10k/ce.c host_ie_addr | host_ie->copy_complete->mask); mask 434 drivers/net/wireless/ath/ath10k/ce.c host_ie_addr & ~(host_ie->copy_complete->mask)); mask 477 drivers/net/wireless/ath/ath10k/ce.c unsigned int mask) mask 481 drivers/net/wireless/ath/ath10k/ce.c ath10k_ce_write32(ar, ce_ctrl_addr + wm_regs->addr, mask); mask 2019 drivers/net/wireless/ath/ath10k/ce.c value |= ar->hw_ce_regs->upd->mask; mask 921 drivers/net/wireless/ath/ath10k/debug.c unsigned long mask; mask 924 drivers/net/wireless/ath/ath10k/debug.c ret = kstrtoul_from_user(user_buf, count, 0, &mask); mask 929 drivers/net/wireless/ath/ath10k/debug.c if (mask > HTT_STATS_BIT_MASK) mask 934 drivers/net/wireless/ath/ath10k/debug.c ar->debug.htt_stats_mask = mask; mask 1040 drivers/net/wireless/ath/ath10k/debug.c u64 mask; mask 1047 drivers/net/wireless/ath/ath10k/debug.c ret = sscanf(buf, "%llx %u", &mask, &log_level); mask 1058 drivers/net/wireless/ath/ath10k/debug.c ar->debug.fw_dbglog_mask = mask; mask 2238 drivers/net/wireless/ath/ath10k/debug.c u32 mask; mask 2245 drivers/net/wireless/ath/ath10k/debug.c if (kstrtoint(buf, 0, &mask)) mask 2248 drivers/net/wireless/ath/ath10k/debug.c ar->sta_tid_stats_mask = mask; mask 2667 drivers/net/wireless/ath/ath10k/debug.c void __ath10k_dbg(struct ath10k *ar, enum ath10k_debug_mask mask, mask 2678 drivers/net/wireless/ath/ath10k/debug.c if (ath10k_debug_mask & mask) mask 2681 drivers/net/wireless/ath/ath10k/debug.c trace_ath10k_log_dbg(ar, mask, &vaf); mask 2688 drivers/net/wireless/ath/ath10k/debug.c enum ath10k_debug_mask mask, mask 2696 drivers/net/wireless/ath/ath10k/debug.c if (ath10k_debug_mask & mask) { mask 2698 drivers/net/wireless/ath/ath10k/debug.c __ath10k_dbg(ar, mask, "%s\n", msg); mask 247 drivers/net/wireless/ath/ath10k/debug.h enum ath10k_debug_mask mask, mask 250 drivers/net/wireless/ath/ath10k/debug.h enum ath10k_debug_mask mask, mask 263 drivers/net/wireless/ath/ath10k/debug.h enum ath10k_debug_mask mask, mask 2260 drivers/net/wireless/ath/ath10k/htt.h int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, mask 583 drivers/net/wireless/ath/ath10k/htt_tx.c int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask, mask 610 drivers/net/wireless/ath/ath10k/htt_tx.c memcpy(req->upload_types, &mask, 3); mask 213 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(17, 17), mask 219 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(18, 18), mask 225 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 236 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(0, 0), mask 267 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(31, 16), mask 273 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 286 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(31, 16), mask 292 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 305 drivers/net/wireless/ath/ath10k/hw.c .mask = 0x00080000, mask 345 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(16, 16), mask 351 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(17, 17), mask 357 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 376 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(3, 3), mask 381 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(0, 0), mask 389 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(0, 0), mask 421 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(31, 16), mask 427 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 440 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(31, 16), mask 446 drivers/net/wireless/ath/ath10k/hw.c .mask = GENMASK(15, 0), mask 288 drivers/net/wireless/ath/ath10k/hw.h u32 mask; mask 306 drivers/net/wireless/ath/ath10k/hw.h u32 mask; mask 343 drivers/net/wireless/ath/ath10k/hw.h u32 mask; mask 3483 drivers/net/wireless/ath/ath10k/mac.c const u32 mask = IEEE80211_TX_INTFL_DONT_ENCRYPT | mask 3489 drivers/net/wireless/ath/ath10k/mac.c if ((info->flags & mask) == mask) mask 7201 drivers/net/wireless/ath/ath10k/mac.c const struct cfg80211_bitrate_mask *mask, mask 7207 drivers/net/wireless/ath/ath10k/mac.c num_rates += hweight32(mask->control[band].legacy); mask 7209 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) mask 7210 drivers/net/wireless/ath/ath10k/mac.c num_rates += hweight8(mask->control[band].ht_mcs[i]); mask 7213 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].vht_mcs); i++) { mask 7214 drivers/net/wireless/ath/ath10k/mac.c tmp = hweight16(mask->control[band].vht_mcs[i]); mask 7225 drivers/net/wireless/ath/ath10k/mac.c const struct cfg80211_bitrate_mask *mask, mask 7234 drivers/net/wireless/ath/ath10k/mac.c if (mask->control[band].legacy) mask 7237 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) { mask 7238 drivers/net/wireless/ath/ath10k/mac.c if (mask->control[band].ht_mcs[i] == 0) mask 7240 drivers/net/wireless/ath/ath10k/mac.c else if (mask->control[band].ht_mcs[i] == mask 7247 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].vht_mcs); i++) { mask 7248 drivers/net/wireless/ath/ath10k/mac.c if (mask->control[band].vht_mcs[i] == 0) mask 7250 drivers/net/wireless/ath/ath10k/mac.c else if (mask->control[band].vht_mcs[i] == mask 7274 drivers/net/wireless/ath/ath10k/mac.c const struct cfg80211_bitrate_mask *mask, mask 7286 drivers/net/wireless/ath/ath10k/mac.c if (hweight32(mask->control[band].legacy) == 1) { mask 7287 drivers/net/wireless/ath/ath10k/mac.c rate_idx = ffs(mask->control[band].legacy) - 1; mask 7308 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) { mask 7309 drivers/net/wireless/ath/ath10k/mac.c if (hweight8(mask->control[band].ht_mcs[i]) == 1) { mask 7313 drivers/net/wireless/ath/ath10k/mac.c (ffs(mask->control[band].ht_mcs[i]) - 1); mask 7320 drivers/net/wireless/ath/ath10k/mac.c for (i = 0; i < ARRAY_SIZE(mask->control[band].vht_mcs); i++) { mask 7321 drivers/net/wireless/ath/ath10k/mac.c if (hweight16(mask->control[band].vht_mcs[i]) == 1) { mask 7325 drivers/net/wireless/ath/ath10k/mac.c (ffs(mask->control[band].vht_mcs[i]) - 1); mask 7381 drivers/net/wireless/ath/ath10k/mac.c const struct cfg80211_bitrate_mask *mask, mask 7392 drivers/net/wireless/ath/ath10k/mac.c vht_mcs = mask->control[band].vht_mcs[i]; mask 7472 drivers/net/wireless/ath/ath10k/mac.c const struct cfg80211_bitrate_mask *mask) mask 7494 drivers/net/wireless/ath/ath10k/mac.c ht_mcs_mask = mask->control[band].ht_mcs; mask 7495 drivers/net/wireless/ath/ath10k/mac.c vht_mcs_mask = mask->control[band].vht_mcs; mask 7498 drivers/net/wireless/ath/ath10k/mac.c sgi = mask->control[band].gi; mask 7512 drivers/net/wireless/ath/ath10k/mac.c if (ath10k_mac_bitrate_mask_has_single_rate(ar, band, mask, mask 7514 drivers/net/wireless/ath/ath10k/mac.c ret = ath10k_mac_bitrate_mask_get_single_rate(ar, band, mask, mask 7522 drivers/net/wireless/ath/ath10k/mac.c } else if (ath10k_mac_bitrate_mask_get_single_nss(ar, band, mask, mask 7532 drivers/net/wireless/ath/ath10k/mac.c if (!ath10k_mac_can_set_bitrate_mask(ar, band, mask, mask 7543 drivers/net/wireless/ath/ath10k/mac.c ath10k_mac_bitrate_mask_get_single_rate(ar, band, mask, mask 7555 drivers/net/wireless/ath/ath10k/mac.c arvif->bitrate_mask = *mask; mask 2206 drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.c mask), mask 654 drivers/net/wireless/ath/ath10k/qmi_wlfw_v01.h u64 mask; mask 177 drivers/net/wireless/ath/ath10k/wmi-ops.h const u8 *mask, mask 1353 drivers/net/wireless/ath/ath10k/wmi-ops.h const u8 *pattern, const u8 *mask, mask 1363 drivers/net/wireless/ath/ath10k/wmi-ops.h pattern, mask, pattern_len, mask 108 drivers/net/wireless/ath/ath10k/wow.c old->mask, ETH_HLEN - old->pkt_offset); mask 154 drivers/net/wireless/ath/ath10k/wow.c memcpy((u8 *)new->mask, mask 163 drivers/net/wireless/ath/ath10k/wow.c memcpy((u8 *)new->mask + new->pattern_len, mask 164 drivers/net/wireless/ath/ath10k/wow.c (void *)old->mask + ETH_HLEN - old->pkt_offset, mask 332 drivers/net/wireless/ath/ath10k/wow.c new_pattern.mask = ath_bitmask; mask 337 drivers/net/wireless/ath/ath10k/wow.c if (patterns[i].mask[j / 8] & BIT(j % 8)) mask 339 drivers/net/wireless/ath/ath10k/wow.c old_pattern.mask = bitmask; mask 356 drivers/net/wireless/ath/ath10k/wow.c new_pattern.mask, mask 1544 drivers/net/wireless/ath/ath5k/ath5k.h void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); mask 486 drivers/net/wireless/ath/ath5k/base.c iter_data->mask[i] &= mask 531 drivers/net/wireless/ath/ath5k/base.c eth_broadcast_addr(iter_data.mask); mask 544 drivers/net/wireless/ath/ath5k/base.c memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); mask 82 drivers/net/wireless/ath/ath5k/base.h u8 mask[ETH_ALEN]; mask 554 drivers/net/wireless/ath/ath5k/eeprom.c u8 mask; mask 561 drivers/net/wireless/ath/ath5k/eeprom.c mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version); mask 564 drivers/net/wireless/ath/ath5k/eeprom.c pcal[0].freq = (val >> 9) & mask; mask 565 drivers/net/wireless/ath/ath5k/eeprom.c pcal[1].freq = (val >> 2) & mask; mask 566 drivers/net/wireless/ath/ath5k/eeprom.c pcal[2].freq = (val << 5) & mask; mask 570 drivers/net/wireless/ath/ath5k/eeprom.c pcal[3].freq = (val >> 4) & mask; mask 571 drivers/net/wireless/ath/ath5k/eeprom.c pcal[4].freq = (val << 3) & mask; mask 575 drivers/net/wireless/ath/ath5k/eeprom.c pcal[5].freq = (val >> 6) & mask; mask 576 drivers/net/wireless/ath/ath5k/eeprom.c pcal[6].freq = (val << 1) & mask; mask 580 drivers/net/wireless/ath/ath5k/eeprom.c pcal[7].freq = (val >> 8) & mask; mask 581 drivers/net/wireless/ath/ath5k/eeprom.c pcal[8].freq = (val >> 1) & mask; mask 582 drivers/net/wireless/ath/ath5k/eeprom.c pcal[9].freq = (val << 6) & mask; mask 447 drivers/net/wireless/ath/ath5k/pcu.c ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) mask 453 drivers/net/wireless/ath/ath5k/pcu.c memcpy(common->bssidmask, mask, ETH_ALEN); mask 199 drivers/net/wireless/ath/ath5k/phy.c u32 mask, data, last_bit, bits_shifted, first_bit; mask 249 drivers/net/wireless/ath/ath5k/phy.c mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << mask 253 drivers/net/wireless/ath/ath5k/phy.c rfb[entry] &= ~mask; mask 254 drivers/net/wireless/ath/ath5k/phy.c rfb[entry] |= ((data << position) << (col * 8)) & mask; mask 257 drivers/net/wireless/ath/ath5k/phy.c data |= (((rfb[entry] & mask) >> (col * 8)) >> position) mask 400 drivers/net/wireless/ath/ath5k/reset.c u32 mask = val ? val : ~0U; mask 416 drivers/net/wireless/ath/ath5k/reset.c mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA mask 420 drivers/net/wireless/ath/ath5k/reset.c mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; mask 423 drivers/net/wireless/ath/ath5k/reset.c ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false); mask 448 drivers/net/wireless/ath/ath5k/reset.c u32 mask = flags ? flags : ~0U; mask 456 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_PCU) mask 458 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_BASEBAND) mask 463 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_PCU) mask 465 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_BASEBAND) mask 469 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_PCU) mask 471 drivers/net/wireless/ath/ath5k/reset.c if (mask & AR5K_RESET_CTL_BASEBAND) mask 1909 drivers/net/wireless/ath/ath6kl/cfg80211.c u8 mask[WOW_PATTERN_SIZE]; mask 1922 drivers/net/wireless/ath/ath6kl/cfg80211.c memset(&mask, 0, sizeof(mask)); mask 1924 drivers/net/wireless/ath/ath6kl/cfg80211.c if (wow->patterns[i].mask[pos / 8] & (0x1 << (pos % 8))) mask 1925 drivers/net/wireless/ath/ath6kl/cfg80211.c mask[pos] = 0xFF; mask 1937 drivers/net/wireless/ath/ath6kl/cfg80211.c wow->patterns[i].pattern, mask); mask 3375 drivers/net/wireless/ath/ath6kl/cfg80211.c const struct cfg80211_bitrate_mask *mask) mask 3381 drivers/net/wireless/ath/ath6kl/cfg80211.c mask); mask 130 drivers/net/wireless/ath/ath6kl/debug.c void ath6kl_dbg(enum ATH6K_DEBUG_MASK mask, const char *fmt, ...) mask 140 drivers/net/wireless/ath/ath6kl/debug.c if (debug_mask & mask) mask 143 drivers/net/wireless/ath/ath6kl/debug.c trace_ath6kl_log_dbg(mask, &vaf); mask 149 drivers/net/wireless/ath/ath6kl/debug.c void ath6kl_dbg_dump(enum ATH6K_DEBUG_MASK mask, mask 153 drivers/net/wireless/ath/ath6kl/debug.c if (debug_mask & mask) { mask 155 drivers/net/wireless/ath/ath6kl/debug.c ath6kl_dbg(mask, "%s\n", msg); mask 67 drivers/net/wireless/ath/ath6kl/debug.h void ath6kl_dbg(enum ATH6K_DEBUG_MASK mask, const char *fmt, ...); mask 68 drivers/net/wireless/ath/ath6kl/debug.h void ath6kl_dbg_dump(enum ATH6K_DEBUG_MASK mask, mask 93 drivers/net/wireless/ath/ath6kl/debug.h static inline void ath6kl_dbg_dump(enum ATH6K_DEBUG_MASK mask, mask 2767 drivers/net/wireless/ath/ath6kl/wmi.c const struct cfg80211_bitrate_mask *mask) mask 2779 drivers/net/wireless/ath/ath6kl/wmi.c ratemask[band] = mask->control[band].legacy; mask 2782 drivers/net/wireless/ath/ath6kl/wmi.c mask->control[band].legacy << 4; mask 2785 drivers/net/wireless/ath/ath6kl/wmi.c mcsrate = mask->control[band].ht_mcs[1]; mask 2787 drivers/net/wireless/ath/ath6kl/wmi.c mcsrate |= mask->control[band].ht_mcs[0]; mask 2819 drivers/net/wireless/ath/ath6kl/wmi.c const struct cfg80211_bitrate_mask *mask) mask 2831 drivers/net/wireless/ath/ath6kl/wmi.c ratemask[band] = mask->control[band].legacy; mask 2834 drivers/net/wireless/ath/ath6kl/wmi.c mask->control[band].legacy << 4; mask 2837 drivers/net/wireless/ath/ath6kl/wmi.c mcsrate = mask->control[band].ht_mcs[0]; mask 2869 drivers/net/wireless/ath/ath6kl/wmi.c const struct cfg80211_bitrate_mask *mask) mask 2875 drivers/net/wireless/ath/ath6kl/wmi.c return ath6kl_set_bitrate_mask64(wmi, if_idx, mask); mask 2877 drivers/net/wireless/ath/ath6kl/wmi.c return ath6kl_set_bitrate_mask32(wmi, if_idx, mask); mask 2955 drivers/net/wireless/ath/ath6kl/wmi.c const u8 *mask) mask 2981 drivers/net/wireless/ath/ath6kl/wmi.c memcpy(filter_mask, mask, filter_size); mask 2642 drivers/net/wireless/ath/ath6kl/wmi.h const struct cfg80211_bitrate_mask *mask); mask 2649 drivers/net/wireless/ath/ath6kl/wmi.h const u8 *mask); mask 91 drivers/net/wireless/ath/ath9k/ar5008_phy.c u32 tmp32, mask, arrayEntry, lastBit; mask 101 drivers/net/wireless/ath/ath9k/ar5008_phy.c mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) << mask 103 drivers/net/wireless/ath/ath9k/ar5008_phy.c rfBuf[arrayEntry] &= ~mask; mask 105 drivers/net/wireless/ath/ath9k/ar5008_phy.c (column * 8)) & mask; mask 656 drivers/net/wireless/ath/ath9k/ath9k.h u8 mask[ETH_ALEN]; /* bssid mask */ mask 103 drivers/net/wireless/ath/ath9k/debug.c unsigned long mask; mask 112 drivers/net/wireless/ath/ath9k/debug.c if (kstrtoul(buf, 0, &mask)) mask 115 drivers/net/wireless/ath/ath9k/debug.c common->debug_mask = mask; mask 28 drivers/net/wireless/ath/ath9k/eeprom.c void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, mask 31 drivers/net/wireless/ath/ath9k/eeprom.c REG_RMW(ah, reg, ((val << shift) & mask), mask); mask 672 drivers/net/wireless/ath/ath9k/eeprom.h void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, mask 1010 drivers/net/wireless/ath/ath9k/eeprom_4k.c u32 pwrctrl, mask, clr; mask 1012 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25); mask 1013 drivers/net/wireless/ath/ath9k/eeprom_4k.c pwrctrl = mask * bb_desired_scale; mask 1014 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; mask 1020 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5)|BIT(15); mask 1021 drivers/net/wireless/ath/ath9k/eeprom_4k.c pwrctrl = mask * bb_desired_scale; mask 1022 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; mask 1025 drivers/net/wireless/ath/ath9k/eeprom_4k.c mask = BIT(0)|BIT(5); mask 1026 drivers/net/wireless/ath/ath9k/eeprom_4k.c pwrctrl = mask * bb_desired_scale; mask 1027 drivers/net/wireless/ath/ath9k/eeprom_4k.c clr = mask * 0x1f; mask 169 drivers/net/wireless/ath/ath9k/htc.h __be32 mask; mask 251 drivers/net/wireless/ath/ath9k/htc.h u8 mask[ETH_ALEN]; mask 377 drivers/net/wireless/ath/ath9k/htc_drv_debug.c unsigned long mask; mask 386 drivers/net/wireless/ath/ath9k/htc_drv_debug.c if (kstrtoul(buf, 0, &mask)) mask 389 drivers/net/wireless/ath/ath9k/htc_drv_debug.c common->debug_mask = mask; mask 134 drivers/net/wireless/ath/ath9k/htc_drv_main.c iter_data->mask[i] &= ~(iter_data->hw_macaddr[i] ^ mac[i]); mask 152 drivers/net/wireless/ath/ath9k/htc_drv_main.c eth_broadcast_addr(iter_data.mask); mask 162 drivers/net/wireless/ath/ath9k/htc_drv_main.c memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); mask 1762 drivers/net/wireless/ath/ath9k/htc_drv_main.c const struct cfg80211_bitrate_mask *mask) mask 1775 drivers/net/wireless/ath/ath9k/htc_drv_main.c tmask.mask = cpu_to_be32(mask->control[NL80211_BAND_2GHZ].legacy); mask 1786 drivers/net/wireless/ath/ath9k/htc_drv_main.c tmask.mask = cpu_to_be32(mask->control[NL80211_BAND_5GHZ].legacy); mask 1797 drivers/net/wireless/ath/ath9k/htc_drv_main.c mask->control[NL80211_BAND_2GHZ].legacy, mask 1798 drivers/net/wireless/ath/ath9k/htc_drv_main.c mask->control[NL80211_BAND_5GHZ].legacy); mask 77 drivers/net/wireless/ath/ath9k/hw.c bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) mask 84 drivers/net/wireless/ath/ath9k/hw.c if ((REG_READ(ah, reg) & mask) == val) mask 92 drivers/net/wireless/ath/ath9k/hw.c timeout, reg, REG_READ(ah, reg), mask, val); mask 1269 drivers/net/wireless/ath/ath9k/hw.c u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; mask 1294 drivers/net/wireless/ath/ath9k/hw.c REG_RMW(ah, AR_STA_ID1, set, mask); mask 1755 drivers/net/wireless/ath/ath9k/hw.c u32 mask; mask 1756 drivers/net/wireless/ath/ath9k/hw.c mask = REG_READ(ah, AR_CFG); mask 1757 drivers/net/wireless/ath/ath9k/hw.c if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { mask 1759 drivers/net/wireless/ath/ath9k/hw.c mask); mask 1761 drivers/net/wireless/ath/ath9k/hw.c mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; mask 1762 drivers/net/wireless/ath/ath9k/hw.c REG_WRITE(ah, AR_CFG, mask); mask 3167 drivers/net/wireless/ath/ath9k/hw.c u32 mask = 0; mask 3196 drivers/net/wireless/ath/ath9k/hw.c mask |= SM(AR_GENTMR_BIT(timer->index), mask 3199 drivers/net/wireless/ath/ath9k/hw.c mask |= SM(AR_GENTMR_BIT(timer->index), mask 3202 drivers/net/wireless/ath/ath9k/hw.c REG_SET_BIT(ah, AR_IMR_S5, mask); mask 1016 drivers/net/wireless/ath/ath9k/hw.h static inline u8 get_streams(int mask) mask 1018 drivers/net/wireless/ath/ath9k/hw.h return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); mask 1041 drivers/net/wireless/ath/ath9k/hw.h bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); mask 911 drivers/net/wireless/ath/ath9k/mac.c u32 mask, mask2; mask 927 drivers/net/wireless/ath/ath9k/mac.c mask = ints & ATH9K_INT_COMMON; mask 934 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; mask 937 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_TXOK; mask 939 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_TXDESC; mask 942 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_TXERR; mask 944 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_TXEOL; mask 949 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; mask 951 drivers/net/wireless/ath/ath9k/mac.c mask &= ~AR_IMR_RXOK_LP; mask 952 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; mask 954 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_RXOK_LP; mask 958 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; mask 960 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_RXOK | AR_IMR_RXDESC; mask 963 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_GENTMR; mask 967 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_GENTMR; mask 970 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_BCNMISC; mask 984 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_BCNMISC; mask 993 drivers/net/wireless/ath/ath9k/mac.c mask |= AR_IMR_BCNMISC; mask 998 drivers/net/wireless/ath/ath9k/mac.c ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); mask 999 drivers/net/wireless/ath/ath9k/mac.c REG_WRITE(ah, AR_IMR, mask); mask 939 drivers/net/wireless/ath/ath9k/main.c iter_data->mask[i] &= mask 1003 drivers/net/wireless/ath/ath9k/main.c iter_data->mask[i] &= mask 1021 drivers/net/wireless/ath/ath9k/main.c eth_broadcast_addr(iter_data->mask); mask 1121 drivers/net/wireless/ath/ath9k/main.c memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); mask 153 drivers/net/wireless/ath/ath9k/wow.c memcpy(wow_mask, patterns[i].mask, mask_len); mask 1612 drivers/net/wireless/ath/ath9k/xmit.c u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA); mask 1613 drivers/net/wireless/ath/ath9k/xmit.c u16 mask_val = mask * val; mask 1616 drivers/net/wireless/ath/ath9k/xmit.c if ((hdr->frame_control & mask) != mask_val) { mask 1617 drivers/net/wireless/ath/ath9k/xmit.c hdr->frame_control = (hdr->frame_control & ~mask) | mask_val; mask 206 drivers/net/wireless/ath/carl9170/fwcmd.h __le32 mask; mask 146 drivers/net/wireless/ath/carl9170/fwdesc.h __le32 mask; mask 3372 drivers/net/wireless/ath/wcn36xx/hal.h u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE]; mask 67 drivers/net/wireless/ath/wcn36xx/wcn36xx.h #define wcn36xx_dbg(mask, fmt, arg...) do { \ mask 68 drivers/net/wireless/ath/wcn36xx/wcn36xx.h if (wcn36xx_dbg_mask & mask) \ mask 72 drivers/net/wireless/ath/wcn36xx/wcn36xx.h #define wcn36xx_dbg_dump(mask, prefix_str, buf, len) do { \ mask 73 drivers/net/wireless/ath/wcn36xx/wcn36xx.h if (wcn36xx_dbg_mask & mask) \ mask 137 drivers/net/wireless/ath/wil6210/fw.h __le32 mask; mask 154 drivers/net/wireless/ath/wil6210/fw.h __le32 mask; /* mask for verification */ mask 386 drivers/net/wireless/ath/wil6210/fw_inc.c u32 m = le32_to_cpu(block[i].mask); mask 580 drivers/net/wireless/atmel/atmel.c static void atmel_set_gcr(struct net_device *dev, u16 mask); mask 581 drivers/net/wireless/atmel/atmel.c static void atmel_clear_gcr(struct net_device *dev, u16 mask); mask 4183 drivers/net/wireless/atmel/atmel.c static void atmel_set_gcr(struct net_device *dev, u16 mask) mask 4185 drivers/net/wireless/atmel/atmel.c outw(inw(dev->base_addr + GCR) | mask, dev->base_addr + GCR); mask 4188 drivers/net/wireless/atmel/atmel.c static void atmel_clear_gcr(struct net_device *dev, u16 mask) mask 4190 drivers/net/wireless/atmel/atmel.c outw(inw(dev->base_addr + GCR) & ~mask, dev->base_addr + GCR); mask 1046 drivers/net/wireless/broadcom/b43/b43.h static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask, mask 1049 drivers/net/wireless/broadcom/b43/b43.h b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set); mask 1062 drivers/net/wireless/broadcom/b43/b43.h static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask, mask 1065 drivers/net/wireless/broadcom/b43/b43.h b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set); mask 112 drivers/net/wireless/broadcom/b43/debugfs.c unsigned int routing, addr, mask, set; mask 117 drivers/net/wireless/broadcom/b43/debugfs.c &routing, &addr, &mask, &set); mask 128 drivers/net/wireless/broadcom/b43/debugfs.c if ((mask > 0xFFFF) || (set > 0xFFFF)) mask 131 drivers/net/wireless/broadcom/b43/debugfs.c if (mask == 0) mask 135 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; mask 188 drivers/net/wireless/broadcom/b43/debugfs.c unsigned int routing, addr, mask, set; mask 193 drivers/net/wireless/broadcom/b43/debugfs.c &routing, &addr, &mask, &set); mask 204 drivers/net/wireless/broadcom/b43/debugfs.c if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF)) mask 207 drivers/net/wireless/broadcom/b43/debugfs.c if (mask == 0) mask 211 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; mask 260 drivers/net/wireless/broadcom/b43/debugfs.c unsigned int addr, mask, set; mask 264 drivers/net/wireless/broadcom/b43/debugfs.c res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set); mask 269 drivers/net/wireless/broadcom/b43/debugfs.c if ((mask > 0xFFFF) || (set > 0xFFFF)) mask 274 drivers/net/wireless/broadcom/b43/debugfs.c if (mask == 0) mask 278 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; mask 324 drivers/net/wireless/broadcom/b43/debugfs.c unsigned int addr, mask, set; mask 328 drivers/net/wireless/broadcom/b43/debugfs.c res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set); mask 333 drivers/net/wireless/broadcom/b43/debugfs.c if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF)) mask 338 drivers/net/wireless/broadcom/b43/debugfs.c if (mask == 0) mask 342 drivers/net/wireless/broadcom/b43/debugfs.c val &= mask; mask 167 drivers/net/wireless/broadcom/b43/lo.c u16 reg, mask; mask 219 drivers/net/wireless/broadcom/b43/lo.c reg = lo_txctl_register_table(dev, &mask, NULL); mask 220 drivers/net/wireless/broadcom/b43/lo.c mask = ~mask; mask 221 drivers/net/wireless/broadcom/b43/lo.c b43_radio_mask(dev, reg, mask); mask 2867 drivers/net/wireless/broadcom/b43/main.c u32 mask, set; mask 2872 drivers/net/wireless/broadcom/b43/main.c mask = 0x0000001F; mask 2875 drivers/net/wireless/broadcom/b43/main.c mask |= 0x0060; mask 2887 drivers/net/wireless/broadcom/b43/main.c mask |= 0x0080; mask 2890 drivers/net/wireless/broadcom/b43/main.c mask |= 0x0100; mask 2898 drivers/net/wireless/broadcom/b43/main.c mask |= 0x0200; mask 2905 drivers/net/wireless/broadcom/b43/main.c bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set); mask 2914 drivers/net/wireless/broadcom/b43/main.c & ~mask) | set); mask 4323 drivers/net/wireless/broadcom/b43/main.c u32 mask; mask 4373 drivers/net/wireless/broadcom/b43/main.c mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); mask 4374 drivers/net/wireless/broadcom/b43/main.c B43_WARN_ON(mask != 0xFFFFFFFF && mask); mask 37 drivers/net/wireless/broadcom/b43/phy_ac.c static void b43_phy_ac_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, mask 42 drivers/net/wireless/broadcom/b43/phy_ac.c (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); mask 233 drivers/net/wireless/broadcom/b43/phy_common.c void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask) mask 236 drivers/net/wireless/broadcom/b43/phy_common.c b43_radio_read16(dev, offset) & mask); mask 245 drivers/net/wireless/broadcom/b43/phy_common.c void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) mask 248 drivers/net/wireless/broadcom/b43/phy_common.c (b43_radio_read16(dev, offset) & mask) | set); mask 251 drivers/net/wireless/broadcom/b43/phy_common.c bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, mask 259 drivers/net/wireless/broadcom/b43/phy_common.c if ((val & mask) == value) mask 299 drivers/net/wireless/broadcom/b43/phy_common.c void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask) mask 303 drivers/net/wireless/broadcom/b43/phy_common.c dev->phy.ops->phy_maskset(dev, offset, mask, 0); mask 306 drivers/net/wireless/broadcom/b43/phy_common.c b43_phy_read(dev, offset) & mask); mask 321 drivers/net/wireless/broadcom/b43/phy_common.c void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) mask 325 drivers/net/wireless/broadcom/b43/phy_common.c dev->phy.ops->phy_maskset(dev, offset, mask, set); mask 328 drivers/net/wireless/broadcom/b43/phy_common.c (b43_phy_read(dev, offset) & mask) | set); mask 163 drivers/net/wireless/broadcom/b43/phy_common.h void (*phy_maskset)(struct b43_wldev *dev, u16 reg, u16 mask, u16 set); mask 320 drivers/net/wireless/broadcom/b43/phy_common.h void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask); mask 330 drivers/net/wireless/broadcom/b43/phy_common.h void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); mask 347 drivers/net/wireless/broadcom/b43/phy_common.h void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask); mask 357 drivers/net/wireless/broadcom/b43/phy_common.h void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); mask 362 drivers/net/wireless/broadcom/b43/phy_common.h bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, mask 220 drivers/net/wireless/broadcom/b43/phy_ht.c static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val) mask 229 drivers/net/wireless/broadcom/b43/phy_ht.c tmp &= ~mask; mask 230 drivers/net/wireless/broadcom/b43/phy_ht.c tmp |= (val & mask); mask 516 drivers/net/wireless/broadcom/b43/phy_ht.c u16 mask; mask 520 drivers/net/wireless/broadcom/b43/phy_ht.c mask = 0x2 << (i * 4); mask 522 drivers/net/wireless/broadcom/b43/phy_ht.c mask = 0; mask 523 drivers/net/wireless/broadcom/b43/phy_ht.c b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); mask 1088 drivers/net/wireless/broadcom/b43/phy_ht.c static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, mask 1093 drivers/net/wireless/broadcom/b43/phy_ht.c (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); mask 813 drivers/net/wireless/broadcom/b43/phy_lcn.c static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, mask 818 drivers/net/wireless/broadcom/b43/phy_lcn.c (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); mask 616 drivers/net/wireless/broadcom/b43/phy_lp.c u16 mask; mask 620 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, }, mask 621 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, }, mask 622 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, }, mask 623 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, }, mask 624 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, }, mask 625 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, }, mask 626 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, }, mask 627 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, }, mask 628 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, }, mask 629 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, }, mask 630 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, }, mask 631 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, }, mask 632 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, }, mask 633 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, }, mask 634 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, }, mask 635 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, }, mask 636 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, }, mask 637 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, }, mask 638 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, }, mask 639 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, }, mask 640 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, }, mask 641 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, }, mask 642 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, }, mask 643 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, }, mask 644 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, }, mask 645 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, }, mask 646 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, }, mask 647 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, }, mask 648 drivers/net/wireless/broadcom/b43/phy_lp.c { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, }, mask 663 drivers/net/wireless/broadcom/b43/phy_lp.c ~(e->mask << e->phy_shift), tmp); mask 1965 drivers/net/wireless/broadcom/b43/phy_lp.c static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, mask 1970 drivers/net/wireless/broadcom/b43/phy_lp.c (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); mask 509 drivers/net/wireless/broadcom/b43/phy_n.c static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) mask 519 drivers/net/wireless/broadcom/b43/phy_n.c tmp &= ~mask; mask 520 drivers/net/wireless/broadcom/b43/phy_n.c tmp |= (val & mask); mask 4480 drivers/net/wireless/broadcom/b43/phy_n.c static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) mask 4495 drivers/net/wireless/broadcom/b43/phy_n.c if (mask == 0) mask 4504 drivers/net/wireless/broadcom/b43/phy_n.c if (i == 0 && (mask & 1)) { mask 4508 drivers/net/wireless/broadcom/b43/phy_n.c } else if (i == 1 && (mask & 2)) { mask 4552 drivers/net/wireless/broadcom/b43/phy_n.c if (i == 0 && (mask & 0x1)) { mask 4560 drivers/net/wireless/broadcom/b43/phy_n.c } else if (i == 1 && (mask & 0x2)) { mask 5838 drivers/net/wireless/broadcom/b43/phy_n.c static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) mask 5844 drivers/net/wireless/broadcom/b43/phy_n.c nphy->phyrxchain = mask; mask 5855 drivers/net/wireless/broadcom/b43/phy_n.c (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); mask 5857 drivers/net/wireless/broadcom/b43/phy_n.c if ((mask & 0x3) != 0x3) { mask 6560 drivers/net/wireless/broadcom/b43/phy_n.c static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, mask 6565 drivers/net/wireless/broadcom/b43/phy_n.c b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); mask 1879 drivers/net/wireless/broadcom/b43legacy/main.c u32 mask; mask 1892 drivers/net/wireless/broadcom/b43legacy/main.c mask = 0x0000001F; mask 1895 drivers/net/wireless/broadcom/b43legacy/main.c mask |= 0x0060; mask 1903 drivers/net/wireless/broadcom/b43legacy/main.c mask |= 0x0200; mask 1907 drivers/net/wireless/broadcom/b43legacy/main.c mask |= 0x0010; /* FIXME: This is redundant. */ mask 1917 drivers/net/wireless/broadcom/b43legacy/main.c & ~mask) | set); mask 2502 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sfu->mask = BIT(NL80211_STA_FLAG_WME) | mask 2645 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c sinfo->sta_flags.mask |= BIT(NL80211_STA_FLAG_TDLS_PEER); mask 3476 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c u8 *pattern, u32 patternsize, u8 *mask, mask 3502 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c if ((mask) && (masksize)) mask 3503 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c memcpy(buf + sizeof(*filter), mask, masksize); mask 3695 drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c (u8 *)wowl->patterns[i].mask, mask 35 drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.h #define BRCMF_FW_ENTRY(chipid, mask, name) \ mask 36 drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.h { chipid, mask, BRCM_ ## name ## _FIRMWARE_BASENAME } mask 543 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) mask 553 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c if (mask || val) mask 554 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c bcma_maskset32(cc, regoff, ~mask, val); mask 175 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val); mask 180 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val); mask 75 drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac.h u32 mask), mask 76 drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac.h TP_ARGS(dev, in_isr, macintstatus, mask), mask 81 drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac.h __field(u32, mask) mask 87 drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac.h __entry->mask = mask; mask 90 drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcms_trace_brcmsmac.h __entry->in_isr, __entry->macintstatus, __entry->mask) mask 348 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c static uint _dma_ctrlflags(struct dma_info *di, uint mask, uint flags) mask 356 drivers/net/wireless/broadcom/brcm80211/brcmsmac/dma.c dmactrlflags &= ~mask; mask 1329 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, mask 1339 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((val & ~mask) || idx >= MHFMAX) mask 1362 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val; mask 1375 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val; mask 1377 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val; mask 1417 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val) mask 1422 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (val & ~mask) mask 1425 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c new_maccontrol = (maccontrol & ~mask) | val; mask 1622 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c u16 mask = PHY_TXC_ANT_MASK; mask 1626 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c phyctl = (phyctl & ~mask) | phytxant; mask 1631 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c phyctl = (phyctl & ~mask) | phytxant; mask 2546 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c u32 macintstatus, mask; mask 2550 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c mask = in_isr ? wlc->macintmask : wlc->defmacintmask; mask 2552 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask); mask 2565 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c macintstatus &= mask; mask 3975 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c u16 mask = PHY_TXC_ANT_MASK; mask 3982 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c phyctl = (phyctl & ~mask) | phytxant; mask 643 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val, mask 646 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.h void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val); mask 250 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask) mask 255 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_radio_reg(pi, addr, (rval ^ mask)); mask 258 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val) mask 263 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c write_radio_reg(pi, addr, (rval & ~mask) | (val & mask)); mask 310 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val) mask 312 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c val &= mask; mask 314 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c bcma_maskset16(pi->d11core, D11REGOFFS(phyregdata), ~mask, val); mask 899 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); mask 904 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val); mask 905 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask); mask 1073 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_int.h u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val); mask 17171 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask = mask 17338 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x7 << 3); mask 17342 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 17346 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 8); mask 17350 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 9); mask 17354 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0xf << 12); mask 17358 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 17362 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 1); mask 17366 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 17370 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 4); mask 17374 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 6); mask 17378 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 8); mask 17382 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 9); mask 17386 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = 0x1fff; mask 17390 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = 0x1fff; mask 17394 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = 0x0; mask 17400 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, addr, mask, (value << shift)); mask 18043 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask; mask 18058 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 10); mask 18061 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 0x92, mask, val); mask 18075 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 6) | (0x1 << 7); mask 18081 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18094 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 6) | mask 18101 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18103 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 18108 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18110 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (core == PHY_CORE_0) ? mask 18114 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x78, mask, val); mask 18122 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 18127 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18132 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 4) | (0x1 << 5); mask 18142 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18151 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 5); mask 18154 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 4); mask 18160 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18167 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 18172 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); mask 18174 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 18178 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, 0); mask 18181 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 18186 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); mask 18188 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 18192 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, 0); mask 18195 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 11); mask 18200 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18204 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 0); mask 18207 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 18213 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18220 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 1); mask 18225 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); mask 18227 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 3); mask 18231 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, 0); mask 18234 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 3); mask 18239 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, val); mask 18241 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 1); mask 18245 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0x92, mask, 0); mask 18248 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 11); mask 18253 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 18257 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 1); mask 18260 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 3); mask 18266 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 21248 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask = 0xfc00; mask 21286 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc, mask, mask); mask 21292 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c bcma_set16(pi->d11core, D11REGOFFS(psm_gpio_oe), mask); mask 21294 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c bcma_mask16(pi->d11core, D11REGOFFS(psm_gpio_out), ~mask); mask 21305 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val) mask 21319 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c new_ctl = (curr_ctl & (~mask)) | (val & mask); mask 21646 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask, val; mask 21666 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2) | mask 21668 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xf9, mask, 0); mask 21669 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xfb, mask, 0); mask 21691 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2) | mask 21697 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, 0); mask 21702 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 2); mask 21705 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 3); mask 21710 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 4); mask 21713 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 5); mask 21719 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask, val); mask 21721 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 5); mask 21724 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c 0xe5 : 0xe6, mask, val); mask 21727 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 8); mask 21732 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21733 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 10); mask 21738 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21741 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 8); mask 21746 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21747 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 10); mask 21752 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21754 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 8); mask 21759 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21760 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 10); mask 21765 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c : 0xa7, mask, val); mask 21790 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = ((0x3 << 12) | (0x3 << 14)); mask 21792 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); mask 21793 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); mask 21805 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x3 << 4); mask 21807 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x7a, mask, val); mask 21808 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x7d, mask, val); mask 23907 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 val, mask; mask 23913 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = ((0x3 << 8) | (0x3 << 10)); mask 23916 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); mask 23917 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); mask 24029 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = ((0x3 << 12) | (0x3 << 14)); mask 24032 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, val); mask 24033 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, val); mask 24064 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask; mask 24128 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = ((0x3 << 12) | (0x3 << 14)); mask 24129 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa6, mask, pi->tx_rx_cal_phy_saveregs[0]); mask 24130 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0xa7, mask, pi->tx_rx_cal_phy_saveregs[1]); mask 27521 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask, val1, val2; mask 27584 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = RADIO_2055_COUPLE_RX_MASK | RADIO_2055_COUPLE_TX_MASK; mask 27594 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, mask, mask 27596 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, mask, mask 27695 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c and_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, ~mask); mask 27696 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c and_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, ~mask); mask 28192 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u16 mask = 0, val = 0, ishw = 0; mask 28267 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask = (0x1 << 14) | (0x1 << 13); mask 28271 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mask |= (0x1 << 15); mask 28275 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c mod_phy_reg(pi, 0x1e7, mask, val); mask 110 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, mask 113 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c brcms_b_mhf(physhim->wlc_hw, idx, mask, val, bands); mask 136 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val) mask 138 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.c brcms_b_mctrl(physhim->wlc_hw, mask, val); mask 145 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.h void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val, mask 151 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy_shim.h void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val); mask 431 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c u16 mask = PHY_TXC_ANT_MASK; mask 436 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c mask = PHY_TXC_HTANT_MASK; mask 438 drivers/net/wireless/broadcom/brcm80211/brcmsmac/stf.c phytxant |= phytxant & mask; mask 134 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define CONF_MSK(config, mask) ((config) & (mask)) mask 147 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define NCONF_MSK(mask) CONF_MSK(NCONF, mask) mask 155 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask) mask 163 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask) mask 273 drivers/net/wireless/broadcom/brcm80211/brcmsmac/types.h #define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val))) mask 172 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h static inline void brcmu_maskset32(u32 *var, u32 mask, u8 shift, u32 value) mask 174 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h value = (value << shift) & mask; mask 175 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h *var = (*var & ~mask) | value; mask 177 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h static inline u32 brcmu_maskget32(u32 var, u32 mask, u8 shift) mask 179 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h return (var & mask) >> shift; mask 181 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h static inline void brcmu_maskset16(u16 *var, u16 mask, u8 shift, u16 value) mask 183 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h value = (value << shift) & mask; mask 184 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h *var = (*var & ~mask) | value; mask 186 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h static inline u16 brcmu_maskget16(u16 var, u16 mask, u8 shift) mask 188 drivers/net/wireless/broadcom/brcm80211/include/brcmu_utils.h return (var & mask) >> shift; mask 2705 drivers/net/wireless/intel/ipw2x00/ipw2100.c stats.mask = 0; mask 2707 drivers/net/wireless/intel/ipw2x00/ipw2100.c stats.mask |= LIBIPW_STATMASK_RSSI; mask 559 drivers/net/wireless/intel/ipw2x00/ipw2200.c static inline void ipw_set_bit(struct ipw_priv *priv, u32 reg, u32 mask) mask 561 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write32(priv, reg, ipw_read32(priv, reg) | mask); mask 565 drivers/net/wireless/intel/ipw2x00/ipw2200.c static inline void ipw_clear_bit(struct ipw_priv *priv, u32 reg, u32 mask) mask 567 drivers/net/wireless/intel/ipw2x00/ipw2200.c ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask); mask 3017 drivers/net/wireless/intel/ipw2x00/ipw2200.c static int ipw_poll_bit(struct ipw_priv *priv, u32 addr, u32 mask, mask 3023 drivers/net/wireless/intel/ipw2x00/ipw2200.c if ((ipw_read32(priv, addr) & mask) == mask) mask 4140 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 mask = priv->rates_mask; mask 4144 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask &= LIBIPW_CCK_RATES_MASK; mask 4149 drivers/net/wireless/intel/ipw2x00/ipw2200.c while (i && !(mask & i)) mask 6072 drivers/net/wireless/intel/ipw2x00/ipw2200.c u16 mask = 0; mask 6115 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= (LIBIPW_OFDM_RATE_6MB_MASK >> 1); mask 6120 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= (LIBIPW_OFDM_RATE_9MB_MASK >> 1); mask 6125 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= (LIBIPW_OFDM_RATE_12MB_MASK >> 1); mask 6129 drivers/net/wireless/intel/ipw2x00/ipw2200.c new_tx_rates |= mask; mask 8306 drivers/net/wireless/intel/ipw2x00/ipw2200.c stats.mask |= LIBIPW_STATMASK_RSSI; mask 8308 drivers/net/wireless/intel/ipw2x00/ipw2200.c stats.mask |= LIBIPW_STATMASK_SIGNAL; mask 8310 drivers/net/wireless/intel/ipw2x00/ipw2200.c stats.mask |= LIBIPW_STATMASK_NOISE; mask 8312 drivers/net/wireless/intel/ipw2x00/ipw2200.c stats.mask |= LIBIPW_STATMASK_RATE; mask 9127 drivers/net/wireless/intel/ipw2x00/ipw2200.c u32 fixed, mask; mask 9135 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask = LIBIPW_DEFAULT_RATES_MASK; mask 9140 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask = 0; mask 9144 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_CCK_RATE_1MB_MASK; mask 9149 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_CCK_RATE_2MB_MASK; mask 9154 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_CCK_RATE_5MB_MASK; mask 9159 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_6MB_MASK; mask 9164 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_9MB_MASK; mask 9169 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_CCK_RATE_11MB_MASK; mask 9174 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_12MB_MASK; mask 9179 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_18MB_MASK; mask 9184 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_24MB_MASK; mask 9189 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_36MB_MASK; mask 9194 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_48MB_MASK; mask 9199 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask |= LIBIPW_OFDM_RATE_54MB_MASK; mask 9208 drivers/net/wireless/intel/ipw2x00/ipw2200.c mask, fixed ? "fixed" : "sub-rates"); mask 9210 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (mask == LIBIPW_DEFAULT_RATES_MASK) { mask 9216 drivers/net/wireless/intel/ipw2x00/ipw2200.c if (priv->rates_mask == mask) { mask 9222 drivers/net/wireless/intel/ipw2x00/ipw2200.c priv->rates_mask = mask; mask 231 drivers/net/wireless/intel/ipw2x00/libipw.h u8 mask; mask 380 drivers/net/wireless/intel/ipw2x00/libipw_rx.c if (rx_stats->mask & LIBIPW_STATMASK_RSSI) { mask 386 drivers/net/wireless/intel/ipw2x00/libipw_rx.c if (rx_stats->mask & LIBIPW_STATMASK_NOISE) { mask 392 drivers/net/wireless/intel/ipw2x00/libipw_rx.c if (rx_stats->mask & LIBIPW_STATMASK_SIGNAL) { mask 146 drivers/net/wireless/intel/ipw2x00/libipw_wx.c if (!(network->stats.mask & LIBIPW_STATMASK_RSSI)) { mask 171 drivers/net/wireless/intel/ipw2x00/libipw_wx.c if (!(network->stats.mask & LIBIPW_STATMASK_NOISE)) { mask 178 drivers/net/wireless/intel/ipw2x00/libipw_wx.c if (!(network->stats.mask & LIBIPW_STATMASK_SIGNAL)) { mask 535 drivers/net/wireless/intel/iwlegacy/3945-rs.c u32 mask; mask 539 drivers/net/wireless/intel/iwlegacy/3945-rs.c for (mask = (1 << i); i >= 0; i--, mask >>= 1) { mask 540 drivers/net/wireless/intel/iwlegacy/3945-rs.c if (rate_mask & mask) { mask 548 drivers/net/wireless/intel/iwlegacy/3945-rs.c for (mask = (1 << i); i < RATE_COUNT_3945; i++, mask <<= 1) { mask 549 drivers/net/wireless/intel/iwlegacy/3945-rs.c if (rate_mask & mask) { mask 592 drivers/net/wireless/intel/iwlegacy/4965-calib.c il4965_find_first_chain(u8 mask) mask 594 drivers/net/wireless/intel/iwlegacy/4965-calib.c if (mask & ANT_A) mask 596 drivers/net/wireless/intel/iwlegacy/4965-calib.c if (mask & ANT_B) mask 6773 drivers/net/wireless/intel/iwlegacy/4965-mac.c il4965_txq_set_sched(struct il_priv *il, u32 mask) mask 6775 drivers/net/wireless/intel/iwlegacy/4965-mac.c il_wr_prph(il, IL49_SCD_TXFACT, mask); mask 408 drivers/net/wireless/intel/iwlegacy/4965-rs.c static const u64 mask = (((u64) 1) << (RATE_MAX_WINDOW - 1)); mask 434 drivers/net/wireless/intel/iwlegacy/4965-rs.c if (win->data & mask) { mask 435 drivers/net/wireless/intel/iwlegacy/4965-rs.c win->data &= ~mask; mask 667 drivers/net/wireless/intel/iwlegacy/4965-rs.c u32 mask; mask 671 drivers/net/wireless/intel/iwlegacy/4965-rs.c for (mask = (1 << i); i >= 0; i--, mask >>= 1) { mask 672 drivers/net/wireless/intel/iwlegacy/4965-rs.c if (rate_mask & mask) { mask 680 drivers/net/wireless/intel/iwlegacy/4965-rs.c for (mask = (1 << i); i < RATE_COUNT; i++, mask <<= 1) { mask 681 drivers/net/wireless/intel/iwlegacy/4965-rs.c if (rate_mask & mask) { mask 76 drivers/net/wireless/intel/iwlegacy/4965.h void il4965_txq_set_sched(struct il_priv *il, u32 mask); mask 27 drivers/net/wireless/intel/iwlegacy/common.c _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout) mask 33 drivers/net/wireless/intel/iwlegacy/common.c if ((_il_rd(il, addr) & mask) == (bits & mask)) mask 108 drivers/net/wireless/intel/iwlegacy/common.c il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout) mask 114 drivers/net/wireless/intel/iwlegacy/common.c if ((il_rd(il, addr) & mask) == mask) mask 1962 drivers/net/wireless/intel/iwlegacy/common.h int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout); mask 1963 drivers/net/wireless/intel/iwlegacy/common.h int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout); mask 2003 drivers/net/wireless/intel/iwlegacy/common.h _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) mask 2005 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, reg, _il_rd(il, reg) & ~mask); mask 2009 drivers/net/wireless/intel/iwlegacy/common.h _il_set_bit(struct il_priv *il, u32 reg, u32 mask) mask 2011 drivers/net/wireless/intel/iwlegacy/common.h _il_wr(il, reg, _il_rd(il, reg) | mask); mask 2062 drivers/net/wireless/intel/iwlegacy/common.h il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) mask 2068 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); mask 2075 drivers/net/wireless/intel/iwlegacy/common.h il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) mask 2081 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); mask 2088 drivers/net/wireless/intel/iwlegacy/common.h il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) mask 2096 drivers/net/wireless/intel/iwlegacy/common.h _il_wr_prph(il, reg, (val & ~mask)); mask 2847 drivers/net/wireless/intel/iwlegacy/common.h il4965_first_antenna(u8 mask) mask 2849 drivers/net/wireless/intel/iwlegacy/common.h if (mask & ANT_A) mask 2851 drivers/net/wireless/intel/iwlegacy/common.h if (mask & ANT_B) mask 755 drivers/net/wireless/intel/iwlwifi/dvm/calib.c static inline u8 find_first_chain(u8 mask) mask 757 drivers/net/wireless/intel/iwlwifi/dvm/calib.c if (mask & ANT_A) mask 759 drivers/net/wireless/intel/iwlwifi/dvm/calib.c if (mask & ANT_B) mask 3757 drivers/net/wireless/intel/iwlwifi/dvm/commands.h u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8]; mask 1023 drivers/net/wireless/intel/iwlwifi/dvm/lib.c memcpy(&pattern_cmd->patterns[i].mask, mask 1024 drivers/net/wireless/intel/iwlwifi/dvm/lib.c wowlan->patterns[i].mask, mask_len); mask 453 drivers/net/wireless/intel/iwlwifi/dvm/rs.c static const u64 mask = (((u64)1) << (IWL_RATE_MAX_WINDOW - 1)); mask 479 drivers/net/wireless/intel/iwlwifi/dvm/rs.c if (window->data & mask) { mask 480 drivers/net/wireless/intel/iwlwifi/dvm/rs.c window->data &= ~mask; mask 724 drivers/net/wireless/intel/iwlwifi/dvm/rs.c u32 mask; mask 729 drivers/net/wireless/intel/iwlwifi/dvm/rs.c mask = BIT(i); mask 731 drivers/net/wireless/intel/iwlwifi/dvm/rs.c for (; i >= 0; i--, mask >>= 1) { mask 732 drivers/net/wireless/intel/iwlwifi/dvm/rs.c if (rate_mask & mask) { mask 740 drivers/net/wireless/intel/iwlwifi/dvm/rs.c for (mask = (1 << i); i < IWL_RATE_COUNT; i++, mask <<= 1) { mask 741 drivers/net/wireless/intel/iwlwifi/dvm/rs.c if (rate_mask & mask) { mask 373 drivers/net/wireless/intel/iwlwifi/dvm/rs.h static inline u8 first_antenna(u8 mask) mask 375 drivers/net/wireless/intel/iwlwifi/dvm/rs.h if (mask & ANT_A) mask 377 drivers/net/wireless/intel/iwlwifi/dvm/rs.h if (mask & ANT_B) mask 153 drivers/net/wireless/intel/iwlwifi/dvm/sta.c __le32 *flags, __le32 *mask) mask 157 drivers/net/wireless/intel/iwlwifi/dvm/sta.c *mask = STA_FLG_RTS_MIMO_PROT_MSK | mask 202 drivers/net/wireless/intel/iwlwifi/dvm/sta.c __le32 flags, mask; mask 208 drivers/net/wireless/intel/iwlwifi/dvm/sta.c iwl_sta_calc_ht_flags(priv, sta, ctx, &flags, &mask); mask 211 drivers/net/wireless/intel/iwlwifi/dvm/sta.c priv->stations[sta_id].sta.station_flags &= ~mask; mask 217 drivers/net/wireless/intel/iwlwifi/dvm/sta.c cmd.station_flags_msk = mask; mask 228 drivers/net/wireless/intel/iwlwifi/dvm/sta.c __le32 flags, mask; mask 230 drivers/net/wireless/intel/iwlwifi/dvm/sta.c iwl_sta_calc_ht_flags(priv, sta, ctx, &flags, &mask); mask 233 drivers/net/wireless/intel/iwlwifi/dvm/sta.c priv->stations[index].sta.station_flags &= ~mask; mask 218 drivers/net/wireless/intel/iwlwifi/fw/api/d3.h u8 mask[IWL_WOWLAN_MAX_PATTERN_LEN / 8]; mask 123 drivers/net/wireless/intel/iwlwifi/fw/api/filter.h __be32 mask; mask 157 drivers/net/wireless/intel/iwlwifi/iwl-config.h static inline u8 num_of_ant(u8 mask) mask 159 drivers/net/wireless/intel/iwlwifi/iwl-config.h return !!((mask) & ANT_A) + mask 160 drivers/net/wireless/intel/iwlwifi/iwl-config.h !!((mask) & ANT_B) + mask 161 drivers/net/wireless/intel/iwlwifi/iwl-config.h !!((mask) & ANT_C); mask 137 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 bits, u32 mask, int timeout) mask 142 drivers/net/wireless/intel/iwlwifi/iwl-io.c if ((iwl_read32(trans, addr) & mask) == (bits & mask)) mask 187 drivers/net/wireless/intel/iwlwifi/iwl-io.c int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, mask 193 drivers/net/wireless/intel/iwlwifi/iwl-io.c if ((iwl_read_direct32(trans, addr) & mask) == mask) mask 251 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 bits, u32 mask, int timeout) mask 256 drivers/net/wireless/intel/iwlwifi/iwl-io.c if ((iwl_read_prph(trans, addr) & mask) == (bits & mask)) mask 265 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask) mask 272 drivers/net/wireless/intel/iwlwifi/iwl-io.c mask); mask 279 drivers/net/wireless/intel/iwlwifi/iwl-io.c u32 bits, u32 mask) mask 286 drivers/net/wireless/intel/iwlwifi/iwl-io.c mask) | bits); mask 292 drivers/net/wireless/intel/iwlwifi/iwl-io.c void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask) mask 299 drivers/net/wireless/intel/iwlwifi/iwl-io.c iwl_write_prph_no_grab(trans, ofs, (val & ~mask)); mask 69 drivers/net/wireless/intel/iwlwifi/iwl-io.h static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) mask 71 drivers/net/wireless/intel/iwlwifi/iwl-io.h iwl_trans_set_bits_mask(trans, reg, mask, mask); mask 74 drivers/net/wireless/intel/iwlwifi/iwl-io.h static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) mask 76 drivers/net/wireless/intel/iwlwifi/iwl-io.h iwl_trans_set_bits_mask(trans, reg, mask, 0); mask 80 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 bits, u32 mask, int timeout); mask 81 drivers/net/wireless/intel/iwlwifi/iwl-io.h int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask, mask 95 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 bits, u32 mask, int timeout); mask 96 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); mask 98 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 bits, u32 mask); mask 99 drivers/net/wireless/intel/iwlwifi/iwl-io.h void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); mask 143 drivers/net/wireless/intel/iwlwifi/iwl-io.h u32 bits, u32 mask, int timeout) mask 147 drivers/net/wireless/intel/iwlwifi/iwl-io.h bits, mask, timeout); mask 604 drivers/net/wireless/intel/iwlwifi/iwl-trans.h void (*set_bits_mask)(struct iwl_trans *trans, u32 reg, u32 mask, mask 1211 drivers/net/wireless/intel/iwlwifi/iwl-trans.h iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value) mask 1213 drivers/net/wireless/intel/iwlwifi/iwl-trans.h trans->ops->set_bits_mask(trans, reg, mask, value); mask 412 drivers/net/wireless/intel/iwlwifi/mvm/d3.c memcpy(&pattern_cmd->patterns[i].mask, mask 413 drivers/net/wireless/intel/iwlwifi/mvm/d3.c wowlan->patterns[i].mask, mask_len); mask 456 drivers/net/wireless/intel/iwlwifi/mvm/d3.c memcpy(&pattern_cmd->patterns[i].u.bitmask.mask, mask 457 drivers/net/wireless/intel/iwlwifi/mvm/d3.c wowlan->patterns[i].mask, mask_len); mask 72 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_pm->mask |= param; mask 311 drivers/net/wireless/intel/iwlwifi/mvm/debugfs-vif.c dbgfs_bf->mask |= param; mask 1410 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c for (i = 0; cmd.filters[i].attrs[0].mask; i++) { mask 1422 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c if (!attr->mask) mask 1429 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c be32_to_cpu(attr->mask), mask 1446 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c u32 filter_id, attr_id, mask, value; mask 1467 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c &mask, &value, &next_pos) != 4) mask 1470 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c attr->mask = cpu_to_be32(mask); mask 1472 drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c if (mask) mask 142 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .mask = cpu_to_be32(0xffffffff), mask 152 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .mask = cpu_to_be32(0xffffffff), mask 168 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .mask = cpu_to_be32(0xffff0000), mask 174 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c .mask = cpu_to_be32(0xffffffff), mask 1796 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c if (!attr->mask) mask 1802 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c attr->mask = 0; mask 1845 drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c for (i = 0; mvm->bcast_filters[i].attrs[0].mask; i++) { mask 219 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h int mask; mask 250 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h int mask; mask 1495 drivers/net/wireless/intel/iwlwifi/mvm/mvm.h u8 first_antenna(u8 mask); mask 467 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_KEEP_ALIVE) mask 470 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_SKIP_OVER_DTIM) { mask 478 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_RX_DATA_TIMEOUT) mask 481 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_TX_DATA_TIMEOUT) mask 484 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_SKIP_DTIM_PERIODS) mask 486 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_LPRX_ENA) { mask 492 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_LPRX_RSSI_THRESHOLD) mask 494 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_SNOOZE_ENABLE) { mask 502 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (mvmvif->dbgfs_pm.mask & MVM_DEBUGFS_PM_UAPSD_MISBEHAVING) { mask 820 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_ENERGY_DELTA) mask 822 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_ROAMING_ENERGY_DELTA) mask 825 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_ROAMING_STATE) mask 827 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_TEMP_THRESHOLD) mask 830 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_TEMP_FAST_FILTER) mask 833 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_TEMP_SLOW_FILTER) mask 836 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_DEBUG_FLAG) mask 838 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BF_ESCAPE_TIMER) mask 840 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BA_ESCAPE_TIMER) mask 842 drivers/net/wireless/intel/iwlwifi/mvm/power.c if (dbgfs_bf->mask & MVM_DEBUGFS_BA_ENABLE_BEACON_ABORT) mask 686 drivers/net/wireless/intel/iwlwifi/mvm/rs.c static const u64 mask = (((u64)1) << (IWL_RATE_MAX_WINDOW - 1)); mask 705 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (window->data & mask) { mask 706 drivers/net/wireless/intel/iwlwifi/mvm/rs.c window->data &= ~mask; mask 1024 drivers/net/wireless/intel/iwlwifi/mvm/rs.c u32 mask; mask 1029 drivers/net/wireless/intel/iwlwifi/mvm/rs.c mask = BIT(i); mask 1030 drivers/net/wireless/intel/iwlwifi/mvm/rs.c for (; i >= 0; i--, mask >>= 1) { mask 1031 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (rate_mask & mask) { mask 1039 drivers/net/wireless/intel/iwlwifi/mvm/rs.c for (mask = (1 << i); i < IWL_RATE_COUNT; i++, mask <<= 1) { mask 1040 drivers/net/wireless/intel/iwlwifi/mvm/rs.c if (rate_mask & mask) { mask 265 drivers/net/wireless/intel/iwlwifi/mvm/utils.c u8 first_antenna(u8 mask) mask 268 drivers/net/wireless/intel/iwlwifi/mvm/utils.c if (WARN_ON_ONCE(!mask)) /* ffs will return 0 if mask is zeroed */ mask 270 drivers/net/wireless/intel/iwlwifi/mvm/utils.c return BIT(ffs(mask) - 1); mask 1024 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask, u32 value) mask 1029 drivers/net/wireless/intel/iwlwifi/pcie/internal.h WARN_ON_ONCE(value & ~mask); mask 1033 drivers/net/wireless/intel/iwlwifi/pcie/internal.h v &= ~mask; mask 1039 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask) mask 1041 drivers/net/wireless/intel/iwlwifi/pcie/internal.h __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); mask 1045 drivers/net/wireless/intel/iwlwifi/pcie/internal.h u32 reg, u32 mask) mask 1047 drivers/net/wireless/intel/iwlwifi/pcie/internal.h __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); mask 1913 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 mask = iwl_trans_pcie_prph_msk(trans); mask 1916 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ((reg & mask) | (3 << 24))); mask 1923 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 mask = iwl_trans_pcie_prph_msk(trans); mask 1926 drivers/net/wireless/intel/iwlwifi/pcie/trans.c ((addr & mask) | (3 << 24))); mask 2432 drivers/net/wireless/intel/iwlwifi/pcie/trans.c u32 mask, u32 value) mask 2438 drivers/net/wireless/intel/iwlwifi/pcie/trans.c __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); mask 850 drivers/net/wireless/intel/iwlwifi/pcie/tx.c u32 mask = 0; mask 860 drivers/net/wireless/intel/iwlwifi/pcie/tx.c mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); mask 864 drivers/net/wireless/intel/iwlwifi/pcie/tx.c ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); mask 551 drivers/net/wireless/intersil/p54/fwio.c led->mask[0] = led->mask[1] = cpu_to_le16(priv->softled_state); mask 395 drivers/net/wireless/intersil/p54/lmac.h __le16 mask[2]; mask 655 drivers/net/wireless/intersil/prism54/isl_ioctl.c int mask; mask 662 drivers/net/wireless/intersil/prism54/isl_ioctl.c mask = 0x1; mask 664 drivers/net/wireless/intersil/prism54/isl_ioctl.c if(bss->rates & mask) { mask 670 drivers/net/wireless/intersil/prism54/isl_ioctl.c mask <<= 1; mask 277 drivers/net/wireless/marvell/mwifiex/cfg80211.c u32 mask; mask 280 drivers/net/wireless/marvell/mwifiex/cfg80211.c mask = priv->mgmt_frame_mask | BIT(frame_type >> 4); mask 282 drivers/net/wireless/marvell/mwifiex/cfg80211.c mask = priv->mgmt_frame_mask & ~BIT(frame_type >> 4); mask 284 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (mask != priv->mgmt_frame_mask) { mask 285 drivers/net/wireless/marvell/mwifiex/cfg80211.c priv->mgmt_frame_mask = mask; mask 1702 drivers/net/wireless/marvell/mwifiex/cfg80211.c const struct cfg80211_bitrate_mask *mask) mask 1721 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[0] = mask->control[band].legacy & 0x000f; mask 1725 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[1] = (mask->control[band].legacy & 0x0ff0) >> 4; mask 1727 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[1] = mask->control[band].legacy; mask 1730 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[2] = mask->control[band].ht_mcs[0]; mask 1732 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[2] |= mask->control[band].ht_mcs[1] << 8; mask 1736 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[10] = mask->control[band].vht_mcs[0]; mask 1738 drivers/net/wireless/marvell/mwifiex/cfg80211.c bitmap_rates[11] = mask->control[band].vht_mcs[1]; mask 2606 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (priv->vs_ie[i].mask != MWIFIEX_VSIE_MASK_CLEAR) mask 2608 drivers/net/wireless/marvell/mwifiex/cfg80211.c priv->vs_ie[i].mask = MWIFIEX_VSIE_MASK_SCAN; mask 2651 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (priv->vs_ie[i].mask == MWIFIEX_VSIE_MASK_SCAN) { mask 2652 drivers/net/wireless/marvell/mwifiex/cfg80211.c priv->vs_ie[i].mask = MWIFIEX_VSIE_MASK_CLEAR; mask 2704 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (priv->vs_ie[i].mask != MWIFIEX_VSIE_MASK_CLEAR) mask 2706 drivers/net/wireless/marvell/mwifiex/cfg80211.c priv->vs_ie[i].mask = MWIFIEX_VSIE_MASK_BGSCAN; mask 3223 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (pat->mask[j] & 1 << k) { mask 2073 drivers/net/wireless/marvell/mwifiex/fw.h __le32 mask; mask 50 drivers/net/wireless/marvell/mwifiex/ie.c u16 mask, len, i; mask 53 drivers/net/wireless/marvell/mwifiex/ie.c mask = le16_to_cpu(priv->mgmt_ie[i].mgmt_subtype_mask); mask 56 drivers/net/wireless/marvell/mwifiex/ie.c if (mask == MWIFIEX_AUTO_IDX_MASK) mask 59 drivers/net/wireless/marvell/mwifiex/ie.c if (mask == subtype_mask) { mask 84 drivers/net/wireless/marvell/mwifiex/ie.c u16 travel_len, index, mask; mask 102 drivers/net/wireless/marvell/mwifiex/ie.c mask = le16_to_cpu(ie->mgmt_subtype_mask); mask 106 drivers/net/wireless/marvell/mwifiex/ie.c if (mwifiex_ie_get_autoidx(priv, mask, ie, &index)) mask 116 drivers/net/wireless/marvell/mwifiex/ie.c cpu_to_le16(mask); mask 120 drivers/net/wireless/marvell/mwifiex/ie.c if (mask != MWIFIEX_DELETE_MASK) mask 226 drivers/net/wireless/marvell/mwifiex/ie.c struct mwifiex_ie **ie_ptr, u16 mask, mask 250 drivers/net/wireless/marvell/mwifiex/ie.c ie->mgmt_subtype_mask = cpu_to_le16(mask); mask 1755 drivers/net/wireless/marvell/mwifiex/main.c void _mwifiex_dbg(const struct mwifiex_adapter *adapter, int mask, mask 1761 drivers/net/wireless/marvell/mwifiex/main.c if (!(adapter->debug_mask & mask)) mask 206 drivers/net/wireless/marvell/mwifiex/main.h void _mwifiex_dbg(const struct mwifiex_adapter *adapter, int mask, mask 208 drivers/net/wireless/marvell/mwifiex/main.h #define mwifiex_dbg(adapter, mask, fmt, ...) \ mask 209 drivers/net/wireless/marvell/mwifiex/main.h _mwifiex_dbg(adapter, MWIFIEX_DBG_##mask, fmt, ##__VA_ARGS__) mask 502 drivers/net/wireless/marvell/mwifiex/main.h u16 mask; mask 97 drivers/net/wireless/marvell/mwifiex/scan.c #define dbg_security_flags(mask, desc, priv, bss_desc) \ mask 98 drivers/net/wireless/marvell/mwifiex/scan.c _dbg_security_flags(MWIFIEX_DBG_##mask, desc, __func__, priv, bss_desc) mask 2880 drivers/net/wireless/marvell/mwifiex/scan.c if (priv->vs_ie[id].mask & vsie_mask) { mask 2063 drivers/net/wireless/marvell/mwifiex/sta_cmd.c cmd_ptr->params.reg_mask.mask = cpu_to_le32( mask 34 drivers/net/wireless/marvell/mwifiex/uap_event.c int mask = IEEE80211_WMM_IE_AP_QOSINFO_PARAM_SET_CNT_MASK; mask 73 drivers/net/wireless/marvell/mwifiex/uap_event.c wmm_param_ie->qos_info_bitmap & mask); mask 916 drivers/net/wireless/marvell/mwifiex/wmm.c int mask = IEEE80211_WMM_IE_AP_QOSINFO_PARAM_SET_CNT_MASK; mask 971 drivers/net/wireless/marvell/mwifiex/wmm.c wmm_param_ie->qos_info_bitmap & mask); mask 2932 drivers/net/wireless/marvell/mwl8k.c mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) mask 2944 drivers/net/wireless/marvell/mwl8k.c cmd->mode = cpu_to_le16(mask); mask 3218 drivers/net/wireless/marvell/mwl8k.c static void legacy_rate_mask_to_array(u8 *rates, u32 mask) mask 3226 drivers/net/wireless/marvell/mwl8k.c mask &= 0x1fef; mask 3229 drivers/net/wireless/marvell/mwl8k.c if (mask & (1 << i)) mask 25 drivers/net/wireless/mediatek/mt76/mmio.c static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val) mask 27 drivers/net/wireless/mediatek/mt76/mmio.c val |= mt76_mmio_rr(dev, offset) & ~mask; mask 40 drivers/net/wireless/mediatek/mt76/mt76.h u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); mask 571 drivers/net/wireless/mediatek/mt76/mt76.h bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, mask 576 drivers/net/wireless/mediatek/mt76/mt76.h bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, mask 432 drivers/net/wireless/mediatek/mt76/mt7603/init.c static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) mask 437 drivers/net/wireless/mediatek/mt76/mt7603/init.c return dev->bus_ops->rmw(mdev, addr, mask, val); mask 11 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt7603_ac_queue_mask0(u32 mask) mask 15 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(3, 0) * !!(mask & BIT(0)); mask 16 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(8, 5) * !!(mask & BIT(1)); mask 17 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(13, 10) * !!(mask & BIT(2)); mask 18 drivers/net/wireless/mediatek/mt76/mt7603/mac.c ret |= GENMASK(19, 16) * !!(mask & BIT(3)); mask 23 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask) mask 25 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask)); mask 29 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask) mask 31 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask)); mask 75 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask) mask 78 drivers/net/wireless/mediatek/mt76/mt7603/mac.c FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); mask 1278 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 mask = dev->mt76.mmio.irqmask; mask 1313 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt7603_irq_disable(dev, mask); mask 1329 drivers/net/wireless/mediatek/mt76/mt7603/mac.c mt7603_irq_enable(dev, mask); mask 184 drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask) mask 186 drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask); mask 189 drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask) mask 191 drivers/net/wireless/mediatek/mt76/mt7603/mt7603.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); mask 35 drivers/net/wireless/mediatek/mt76/mt7615/main.c static int get_omac_idx(enum nl80211_iftype type, u32 mask) mask 43 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(HW_BSSID_0)) mask 47 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(i)) mask 54 drivers/net/wireless/mediatek/mt76/mt7615/main.c if (~mask & BIT(i)) mask 221 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h static inline void mt7615_irq_enable(struct mt7615_dev *dev, u32 mask) mask 223 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask); mask 226 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h static inline void mt7615_irq_disable(struct mt7615_dev *dev, u32 mask) mask 228 drivers/net/wireless/mediatek/mt76/mt7615/mt7615.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); mask 36 drivers/net/wireless/mediatek/mt76/mt76x0/init.c u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; mask 57 drivers/net/wireless/mediatek/mt76/mt76x0/init.c if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) mask 141 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val) mask 149 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c val |= ret & ~mask; mask 162 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask) mask 164 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c return mt76x0_rf_rmw(dev, offset, mask, 0); mask 220 drivers/net/wireless/mediatek/mt76/mt76x02.h static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask) mask 222 drivers/net/wireless/mediatek/mt76/mt76x02.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask); mask 225 drivers/net/wireless/mediatek/mt76/mt76x02.h static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask) mask 227 drivers/net/wireless/mediatek/mt76/mt76x02.h mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); mask 438 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c u32 mask = dev->mt76.mmio.irqmask; mask 462 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c mt76x02_irq_disable(dev, mask); mask 494 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c mt76x02_irq_enable(dev, mask); mask 104 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h TP_PROTO(struct mt76x02_dev *dev, u32 val, u32 mask), mask 106 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h TP_ARGS(dev, val, mask), mask 111 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h __field(u32, mask) mask 117 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h __entry->mask = mask; mask 122 drivers/net/wireless/mediatek/mt76/mt76x02_trace.h DEV_PR_ARG, __entry->val, __entry->mask mask 139 drivers/net/wireless/mediatek/mt76/usb.c u32 mask, u32 val) mask 142 drivers/net/wireless/mediatek/mt76/usb.c val |= __mt76u_rr(dev, addr) & ~mask; mask 9 drivers/net/wireless/mediatek/mt76/util.c bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, mask 16 drivers/net/wireless/mediatek/mt76/util.c cur = dev->bus->rr(dev, offset) & mask; mask 27 drivers/net/wireless/mediatek/mt76/util.c bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, mask 34 drivers/net/wireless/mediatek/mt76/util.c cur = dev->bus->rr(dev, offset) & mask; mask 45 drivers/net/wireless/mediatek/mt76/util.c int mt76_wcid_alloc(unsigned long *mask, int size) mask 50 drivers/net/wireless/mediatek/mt76/util.c idx = ffs(~mask[i]); mask 59 drivers/net/wireless/mediatek/mt76/util.c mask[i] |= BIT(idx); mask 77 drivers/net/wireless/mediatek/mt76/util.c unsigned long mask = dev->wcid_mask[i]; mask 79 drivers/net/wireless/mediatek/mt76/util.c if (!mask) mask 82 drivers/net/wireless/mediatek/mt76/util.c for (j = i * BITS_PER_LONG; mask; j++, mask >>= 1) { mask 83 drivers/net/wireless/mediatek/mt76/util.c if (!(mask & 1)) mask 17 drivers/net/wireless/mediatek/mt76/util.h int mt76_wcid_alloc(unsigned long *mask, int size); mask 20 drivers/net/wireless/mediatek/mt76/util.h mt76_wcid_free(unsigned long *mask, int idx) mask 22 drivers/net/wireless/mediatek/mt76/util.h mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG); mask 28 drivers/net/wireless/mediatek/mt7601u/core.c bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, mask 38 drivers/net/wireless/mediatek/mt7601u/core.c cur = mt7601u_rr(dev, offset) & mask; mask 50 drivers/net/wireless/mediatek/mt7601u/core.c bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, mask 60 drivers/net/wireless/mediatek/mt7601u/core.c cur = mt7601u_rr(dev, offset) & mask; mask 285 drivers/net/wireless/mediatek/mt7601u/mt7601u.h u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); mask 286 drivers/net/wireless/mediatek/mt7601u/mt7601u.h u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); mask 291 drivers/net/wireless/mediatek/mt7601u/mt7601u.h bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, mask 293 drivers/net/wireless/mediatek/mt7601u/mt7601u.h bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, mask 311 drivers/net/wireless/mediatek/mt7601u/mt7601u.h mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) mask 313 drivers/net/wireless/mediatek/mt7601u/mt7601u.h return mt7601u_rmw(dev, offset, mask, val); mask 95 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) mask 102 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; mask 117 drivers/net/wireless/mediatek/mt7601u/phy.c mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) mask 119 drivers/net/wireless/mediatek/mt7601u/phy.c return mt7601u_rf_rmw(dev, bank, offset, mask, 0); mask 182 drivers/net/wireless/mediatek/mt7601u/phy.c static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) mask 189 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; mask 195 drivers/net/wireless/mediatek/mt7601u/phy.c static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) mask 202 drivers/net/wireless/mediatek/mt7601u/phy.c val |= ret & ~mask; mask 187 drivers/net/wireless/mediatek/mt7601u/usb.c u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) mask 190 drivers/net/wireless/mediatek/mt7601u/usb.c val |= __mt7601u_rr(dev, offset) & ~mask; mask 197 drivers/net/wireless/mediatek/mt7601u/usb.c u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) mask 203 drivers/net/wireless/mediatek/mt7601u/usb.c val |= reg & ~mask; mask 504 drivers/net/wireless/quantenna/qtnfmac/commands.c u32 mask, value; mask 506 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask = 0; mask 509 drivers/net/wireless/quantenna/qtnfmac/commands.c mask = le32_to_cpu(src->mask); mask 512 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_AUTHORIZED) { mask 513 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_AUTHORIZED); mask 518 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_SHORT_PREAMBLE) { mask 519 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_SHORT_PREAMBLE); mask 524 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_WME) { mask 525 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_WME); mask 530 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_MFP) { mask 531 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_MFP); mask 536 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_AUTHENTICATED) { mask 537 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_AUTHENTICATED); mask 542 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_TDLS_PEER) { mask 543 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_TDLS_PEER); mask 548 drivers/net/wireless/quantenna/qtnfmac/commands.c if (mask & QLINK_STA_FLAG_ASSOCIATED) { mask 549 drivers/net/wireless/quantenna/qtnfmac/commands.c dst->mask |= BIT(NL80211_STA_FLAG_ASSOCIATED); mask 1985 drivers/net/wireless/quantenna/qtnfmac/commands.c cmd->flag_update.mask = mask 193 drivers/net/wireless/quantenna/qtnfmac/qlink.h __le32 mask; mask 160 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c u8 mask = 1 << (bit - (idx * BITS_PER_BYTE)); mask 165 drivers/net/wireless/quantenna/qtnfmac/qlink_util.c return arr[idx] & mask; mask 960 drivers/net/wireless/ralink/rt2x00/rt2400pci.c int mask = (state == STATE_RADIO_IRQ_OFF); mask 980 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); mask 981 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); mask 982 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); mask 983 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); mask 984 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(®, CSR8_RXDONE, mask); mask 1370 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg, mask; mask 1385 drivers/net/wireless/ralink/rt2x00/rt2400pci.c mask = reg; mask 1403 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); mask 1404 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); mask 1405 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); mask 1415 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg |= mask; mask 1114 drivers/net/wireless/ralink/rt2x00/rt2500pci.c int mask = (state == STATE_RADIO_IRQ_OFF); mask 1134 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); mask 1135 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); mask 1136 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); mask 1137 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); mask 1138 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(®, CSR8_RXDONE, mask); mask 1498 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg, mask; mask 1513 drivers/net/wireless/ralink/rt2x00/rt2500pci.c mask = reg; mask 1531 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); mask 1532 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); mask 1533 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); mask 1543 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg |= mask; mask 323 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u32 mask; mask 343 drivers/net/wireless/ralink/rt2x00/rt2500usb.c mask = TXRX_CSR0_KEY_ID.bit_mask; mask 347 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg &= mask; mask 349 drivers/net/wireless/ralink/rt2x00/rt2500usb.c if (reg && reg == mask) mask 388 drivers/net/wireless/ralink/rt2x00/rt2500usb.c mask = rt2x00_get_field16(reg, TXRX_CSR0_KEY_ID); mask 390 drivers/net/wireless/ralink/rt2x00/rt2500usb.c mask |= 1 << key->hw_key_idx; mask 392 drivers/net/wireless/ralink/rt2x00/rt2500usb.c mask &= ~(1 << key->hw_key_idx); mask 393 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rt2x00_set_field16(®, TXRX_CSR0_KEY_ID, mask); mask 325 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c u32 reg, mask; mask 342 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c mask = ~reg; mask 345 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1); mask 369 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c reg &= mask; mask 327 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 mask; mask 400 drivers/net/wireless/ralink/rt2x00/rt61pci.c mask = 1 << key->hw_key_idx; mask 404 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; mask 406 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg &= ~mask; mask 409 drivers/net/wireless/ralink/rt2x00/rt61pci.c mask = 1 << (key->hw_key_idx - 32); mask 413 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; mask 415 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg &= ~mask; mask 1623 drivers/net/wireless/ralink/rt2x00/rt61pci.c int mask = (state == STATE_RADIO_IRQ_OFF); mask 1646 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); mask 1647 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); mask 1648 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); mask 1649 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); mask 1654 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); mask 1655 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); mask 1656 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); mask 1657 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); mask 1658 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); mask 1659 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); mask 1660 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); mask 1661 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); mask 1662 drivers/net/wireless/ralink/rt2x00/rt61pci.c rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); mask 2232 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg, mask; mask 2270 drivers/net/wireless/ralink/rt2x00/rt61pci.c mask = reg; mask 2280 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg |= mask; mask 262 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 mask; mask 276 drivers/net/wireless/ralink/rt2x00/rt73usb.c mask = (0xf << crypto->bssidx); mask 279 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= mask; mask 281 drivers/net/wireless/ralink/rt2x00/rt73usb.c if (reg && reg == mask) mask 341 drivers/net/wireless/ralink/rt2x00/rt73usb.c mask = 1 << key->hw_key_idx; mask 345 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; mask 347 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; mask 359 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 mask; mask 435 drivers/net/wireless/ralink/rt2x00/rt73usb.c mask = 1 << key->hw_key_idx; mask 439 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; mask 441 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; mask 444 drivers/net/wireless/ralink/rt2x00/rt73usb.c mask = 1 << (key->hw_key_idx - 32); mask 448 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg |= mask; mask 450 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg &= ~mask; mask 50 drivers/net/wireless/realtek/rtlwifi/core.c u32 mask, u32 data) mask 55 drivers/net/wireless/realtek/rtlwifi/core.c rtl_set_rfreg(hw, rfpath, addr, mask, data); mask 425 drivers/net/wireless/realtek/rtlwifi/core.c u8 mask[MAX_WOL_BIT_MASK_SIZE] = {0}; mask 435 drivers/net/wireless/realtek/rtlwifi/core.c memset(mask, 0, MAX_WOL_BIT_MASK_SIZE); mask 444 drivers/net/wireless/realtek/rtlwifi/core.c mask_os = patterns[i].mask; mask 486 drivers/net/wireless/realtek/rtlwifi/core.c mask[j] = mask_os[j] >> 6; mask 487 drivers/net/wireless/realtek/rtlwifi/core.c mask[j] |= (mask_os[j + 1] & 0x3F) << 2; mask 489 drivers/net/wireless/realtek/rtlwifi/core.c mask[j] = (mask_os[j] >> 6) & 0x3F; mask 491 drivers/net/wireless/realtek/rtlwifi/core.c mask[0] &= 0xC0; mask 494 drivers/net/wireless/realtek/rtlwifi/core.c "mask to hw\n", mask, mask_len); mask 496 drivers/net/wireless/realtek/rtlwifi/core.c rtl_pattern.mask[j] = mask[j * 4]; mask 497 drivers/net/wireless/realtek/rtlwifi/core.c rtl_pattern.mask[j] |= (mask[j * 4 + 1] << 8); mask 498 drivers/net/wireless/realtek/rtlwifi/core.c rtl_pattern.mask[j] |= (mask[j * 4 + 2] << 16); mask 499 drivers/net/wireless/realtek/rtlwifi/core.c rtl_pattern.mask[j] |= (mask[j * 4 + 3] << 24); mask 58 drivers/net/wireless/realtek/rtlwifi/core.h u32 mask, u32 data); mask 1198 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; mask 1298 drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c mask, value); mask 2128 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c u32 mask = 0; mask 2257 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); mask 2260 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c mask, ratr_bitmap); mask 2262 drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); mask 193 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c u32 mask = 0; mask 199 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c mask |= 0x000000FF; mask 201 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c mask |= 0x0000FF00; mask 203 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c mask |= 0x00FF0000; mask 205 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c mask |= 0xFF000000; mask 208 drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c if ((cond2 & mask) == (driver2 & mask)) mask 4045 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam = rtl_pattern->mask[addr - 2]; mask 4054 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c cam = rtl_pattern->mask[addr - 2]; mask 791 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u32 mask = 0; mask 797 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c mask |= 0x000000FF; mask 799 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c mask |= 0x0000FF00; mask 801 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c mask |= 0x00FF0000; mask 803 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c mask |= 0xFF000000; mask 806 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if ((cond2 & mask) == (driver2 & mask)) mask 2085 drivers/net/wireless/realtek/rtlwifi/wifi.h u8 mask; mask 2207 drivers/net/wireless/realtek/rtlwifi/wifi.h u32 mask[4]; mask 737 drivers/net/wireless/realtek/rtw88/coex.c u32 mask, u32 val) mask 739 drivers/net/wireless/realtek/rtw88/coex.c u32 shift = __ffs(mask); mask 743 drivers/net/wireless/realtek/rtw88/coex.c tmp = (tmp & (~mask)) | ((val << shift) & mask); mask 351 drivers/net/wireless/realtek/rtw88/coex.h u32 mask, u32 val); mask 128 drivers/net/wireless/realtek/rtw88/debug.c u32 val, addr, mask; mask 133 drivers/net/wireless/realtek/rtw88/debug.c mask = debugfs_priv->rf_mask; mask 135 drivers/net/wireless/realtek/rtw88/debug.c val = rtw_read_rf(rtwdev, path, addr, mask); mask 138 drivers/net/wireless/realtek/rtw88/debug.c path, addr, mask, val); mask 353 drivers/net/wireless/realtek/rtw88/debug.c u32 path, addr, mask, val; mask 358 drivers/net/wireless/realtek/rtw88/debug.c num = sscanf(tmp, "%x %x %x %x", &path, &addr, &mask, &val); mask 365 drivers/net/wireless/realtek/rtw88/debug.c rtw_write_rf(rtwdev, path, addr, mask, val); mask 368 drivers/net/wireless/realtek/rtw88/debug.c path, addr, mask, val); mask 381 drivers/net/wireless/realtek/rtw88/debug.c u32 path, addr, mask; mask 386 drivers/net/wireless/realtek/rtw88/debug.c num = sscanf(tmp, "%x %x %x", &path, &addr, &mask); mask 395 drivers/net/wireless/realtek/rtw88/debug.c debugfs_priv->rf_mask = mask; mask 731 drivers/net/wireless/realtek/rtw88/debug.c void __rtw_dbg(struct rtw_dev *rtwdev, enum rtw_debug_mask mask, mask 742 drivers/net/wireless/realtek/rtw88/debug.c if (rtw_debug_mask & mask) mask 36 drivers/net/wireless/realtek/rtw88/debug.h void __rtw_dbg(struct rtw_dev *rtwdev, enum rtw_debug_mask mask, mask 43 drivers/net/wireless/realtek/rtw88/debug.h static inline void rtw_dbg(struct rtw_dev *rtwdev, enum rtw_debug_mask mask, mask 142 drivers/net/wireless/realtek/rtw88/hci.h u32 addr, u32 mask) mask 148 drivers/net/wireless/realtek/rtw88/hci.h val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); mask 156 drivers/net/wireless/realtek/rtw88/hci.h u32 addr, u32 mask, u32 data) mask 161 drivers/net/wireless/realtek/rtw88/hci.h rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); mask 166 drivers/net/wireless/realtek/rtw88/hci.h rtw_read32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask) mask 168 drivers/net/wireless/realtek/rtw88/hci.h u32 shift = __ffs(mask); mask 173 drivers/net/wireless/realtek/rtw88/hci.h ret = (orig & mask) >> shift; mask 179 drivers/net/wireless/realtek/rtw88/hci.h rtw_write32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) mask 181 drivers/net/wireless/realtek/rtw88/hci.h u32 shift = __ffs(mask); mask 188 drivers/net/wireless/realtek/rtw88/hci.h set = (orig & ~mask) | ((data << shift) & mask); mask 193 drivers/net/wireless/realtek/rtw88/hci.h rtw_write8_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u8 data) mask 198 drivers/net/wireless/realtek/rtw88/hci.h mask &= 0xff; mask 199 drivers/net/wireless/realtek/rtw88/hci.h shift = __ffs(mask); mask 202 drivers/net/wireless/realtek/rtw88/hci.h set = (orig & ~mask) | ((data << shift) & mask); mask 117 drivers/net/wireless/realtek/rtw88/mac.c value &= cmd->mask; mask 118 drivers/net/wireless/realtek/rtw88/mac.c if (value == (cmd->value & cmd->mask)) mask 159 drivers/net/wireless/realtek/rtw88/mac.c value &= ~cur_cmd->mask; mask 160 drivers/net/wireless/realtek/rtw88/mac.c value |= (cur_cmd->value & cur_cmd->mask); mask 87 drivers/net/wireless/realtek/rtw88/mac80211.c .net_type = {.addr = 0x0100, .mask = 0x30000}, mask 88 drivers/net/wireless/realtek/rtw88/mac80211.c .aid = {.addr = 0x06a8, .mask = 0x7ff}, mask 89 drivers/net/wireless/realtek/rtw88/mac80211.c .bcn_ctrl = {.addr = 0x0550, .mask = 0xff}, mask 94 drivers/net/wireless/realtek/rtw88/mac80211.c .net_type = {.addr = 0x0100, .mask = 0xc0000}, mask 95 drivers/net/wireless/realtek/rtw88/mac80211.c .aid = {.addr = 0x0710, .mask = 0x7ff}, mask 96 drivers/net/wireless/realtek/rtw88/mac80211.c .bcn_ctrl = {.addr = 0x0551, .mask = 0xff}, mask 101 drivers/net/wireless/realtek/rtw88/mac80211.c .net_type = {.addr = 0x1100, .mask = 0x3}, mask 102 drivers/net/wireless/realtek/rtw88/mac80211.c .aid = {.addr = 0x1600, .mask = 0x7ff}, mask 103 drivers/net/wireless/realtek/rtw88/mac80211.c .bcn_ctrl = {.addr = 0x0578, .mask = 0xff}, mask 108 drivers/net/wireless/realtek/rtw88/mac80211.c .net_type = {.addr = 0x1100, .mask = 0xc}, mask 109 drivers/net/wireless/realtek/rtw88/mac80211.c .aid = {.addr = 0x1604, .mask = 0x7ff}, mask 110 drivers/net/wireless/realtek/rtw88/mac80211.c .bcn_ctrl = {.addr = 0x0579, .mask = 0xff}, mask 115 drivers/net/wireless/realtek/rtw88/mac80211.c .net_type = {.addr = 0x1100, .mask = 0x30}, mask 116 drivers/net/wireless/realtek/rtw88/mac80211.c .aid = {.addr = 0x1608, .mask = 0x7ff}, mask 117 drivers/net/wireless/realtek/rtw88/mac80211.c .bcn_ctrl = {.addr = 0x057a, .mask = 0xff}, mask 335 drivers/net/wireless/realtek/rtw88/main.c u32 addr, mask; mask 347 drivers/net/wireless/realtek/rtw88/main.c mask = rtwvif->conf->net_type.mask; mask 348 drivers/net/wireless/realtek/rtw88/main.c rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type); mask 352 drivers/net/wireless/realtek/rtw88/main.c mask = rtwvif->conf->aid.mask; mask 353 drivers/net/wireless/realtek/rtw88/main.c rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid); mask 357 drivers/net/wireless/realtek/rtw88/main.c mask = rtwvif->conf->bcn_ctrl.mask; mask 358 drivers/net/wireless/realtek/rtw88/main.c rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl); mask 434 drivers/net/wireless/realtek/rtw88/main.h u32 mask; mask 633 drivers/net/wireless/realtek/rtw88/main.h u32 addr, u32 mask); mask 635 drivers/net/wireless/realtek/rtw88/main.h u32 addr, u32 mask, u32 data); mask 697 drivers/net/wireless/realtek/rtw88/main.h u8 mask; mask 1403 drivers/net/wireless/realtek/rtw88/main.h bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); mask 131 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, mask; mask 143 drivers/net/wireless/realtek/rtw88/phy.c mask = chip->dig[0].mask; mask 144 drivers/net/wireless/realtek/rtw88/phy.c dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); mask 152 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, mask; mask 157 drivers/net/wireless/realtek/rtw88/phy.c mask = chip->dig[path].mask; mask 158 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, addr, mask, igi); mask 669 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask) mask 683 drivers/net/wireless/realtek/rtw88/phy.c mask &= RFREG_MASK; mask 685 drivers/net/wireless/realtek/rtw88/phy.c val = rtw_read32_mask(rtwdev, direct_addr, mask); mask 691 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask, u32 data) mask 706 drivers/net/wireless/realtek/rtw88/phy.c mask &= RFREG_MASK; mask 708 drivers/net/wireless/realtek/rtw88/phy.c if (mask != RFREG_MASK) { mask 716 drivers/net/wireless/realtek/rtw88/phy.c shift = __ffs(mask); mask 717 drivers/net/wireless/realtek/rtw88/phy.c data = ((old_data) & (~mask)) | (data << shift); mask 730 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask, u32 data) mask 744 drivers/net/wireless/realtek/rtw88/phy.c mask &= RFREG_MASK; mask 751 drivers/net/wireless/realtek/rtw88/phy.c rtw_write32_mask(rtwdev, direct_addr, mask, data); mask 764 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask, u32 data) mask 767 drivers/net/wireless/realtek/rtw88/phy.c return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data); mask 769 drivers/net/wireless/realtek/rtw88/phy.c return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data); mask 876 drivers/net/wireless/realtek/rtw88/phy.c u32 addr, u32 mask, u32 val, u8 *rate, mask 908 drivers/net/wireless/realtek/rtw88/phy.c if (mask == 0xffffff00) { mask 916 drivers/net/wireless/realtek/rtw88/phy.c } else if (mask == 0x000000ff) { mask 23 drivers/net/wireless/realtek/rtw88/phy.h u32 addr, u32 mask); mask 25 drivers/net/wireless/realtek/rtw88/phy.h u32 addr, u32 mask, u32 data); mask 27 drivers/net/wireless/realtek/rtw88/phy.h u32 addr, u32 mask, u32 data); mask 29 drivers/net/wireless/realtek/rtw88/phy.h u32 addr, u32 mask, u32 data); mask 1761 drivers/net/wireless/realtek/rtw88/rtw8822b.c [0] = { .addr = 0xc50, .mask = 0x7f }, mask 1762 drivers/net/wireless/realtek/rtw88/rtw8822b.c [1] = { .addr = 0xe50, .mask = 0x7f }, mask 101 drivers/net/wireless/realtek/rtw88/rtw8822b.h _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) mask 104 drivers/net/wireless/realtek/rtw88/rtw8822b.h rtw_write32_mask(rtwdev, addr, mask, data); mask 105 drivers/net/wireless/realtek/rtw88/rtw8822b.h rtw_write32_mask(rtwdev, addr + 0x200, mask, data); mask 108 drivers/net/wireless/realtek/rtw88/rtw8822b.h #define rtw_write32s_mask(rtwdev, addr, mask, data) \ mask 112 drivers/net/wireless/realtek/rtw88/rtw8822b.h _rtw_write32s_mask(rtwdev, addr, mask, data); \ mask 2964 drivers/net/wireless/realtek/rtw88/rtw8822c.c u32 mask = BIT(15) | BIT(14); mask 2974 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); mask 2978 drivers/net/wireless/realtek/rtw88/rtw8822c.c rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); mask 3530 drivers/net/wireless/realtek/rtw88/rtw8822c.c [0] = { .addr = 0x1d70, .mask = 0x7f }, mask 3531 drivers/net/wireless/realtek/rtw88/rtw8822c.c [1] = { .addr = 0x1d70, .mask = 0x7f00 }, mask 9 drivers/net/wireless/realtek/rtw88/util.c bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target) mask 14 drivers/net/wireless/realtek/rtw88/util.c if (rtw_read32_mask(rtwdev, addr, mask) == target) mask 1215 drivers/net/wireless/rsi/rsi_91x_mac80211.c const struct cfg80211_bitrate_mask *mask) mask 1224 drivers/net/wireless/rsi/rsi_91x_mac80211.c if (mask->control[band].legacy == 0xfff) { mask 1226 drivers/net/wireless/rsi/rsi_91x_mac80211.c (mask->control[band].ht_mcs[0] << 12); mask 1229 drivers/net/wireless/rsi/rsi_91x_mac80211.c mask->control[band].legacy; mask 479 drivers/net/wireless/st/cw1200/txrx.c u32 mask = ~BIT(t->txpriv.raw_link_id); mask 481 drivers/net/wireless/st/cw1200/txrx.c priv->sta_asleep_mask &= mask; mask 482 drivers/net/wireless/st/cw1200/txrx.c priv->pspoll_mask &= mask; mask 1387 drivers/net/wireless/st/cw1200/txrx.c u32 mask; mask 1397 drivers/net/wireless/st/cw1200/txrx.c mask = BIT(i + 1); mask 1400 drivers/net/wireless/st/cw1200/txrx.c !(priv->link_id_map & mask))) { mask 1401 drivers/net/wireless/st/cw1200/txrx.c if (priv->link_id_map & mask) { mask 1402 drivers/net/wireless/st/cw1200/txrx.c priv->sta_asleep_mask &= ~mask; mask 1403 drivers/net/wireless/st/cw1200/txrx.c priv->pspoll_mask &= ~mask; mask 1406 drivers/net/wireless/st/cw1200/txrx.c priv->link_id_map |= mask; mask 1426 drivers/net/wireless/st/cw1200/txrx.c priv->link_id_map &= ~mask; mask 1427 drivers/net/wireless/st/cw1200/txrx.c priv->sta_asleep_mask &= ~mask; mask 1428 drivers/net/wireless/st/cw1200/txrx.c priv->pspoll_mask &= ~mask; mask 695 drivers/net/wireless/ti/wl1251/acx.c struct acx_event_mask *mask; mask 700 drivers/net/wireless/ti/wl1251/acx.c mask = kzalloc(sizeof(*mask), GFP_KERNEL); mask 701 drivers/net/wireless/ti/wl1251/acx.c if (!mask) mask 705 drivers/net/wireless/ti/wl1251/acx.c mask->high_event_mask = 0xffffffff; mask 707 drivers/net/wireless/ti/wl1251/acx.c mask->event_mask = event_mask; mask 710 drivers/net/wireless/ti/wl1251/acx.c mask, sizeof(*mask)); mask 717 drivers/net/wireless/ti/wl1251/acx.c kfree(mask); mask 158 drivers/net/wireless/ti/wl1251/event.c int wl1251_event_wait(struct wl1251 *wl, u32 mask, int timeout_ms) mask 174 drivers/net/wireless/ti/wl1251/event.c event = events_vector & mask; mask 177 drivers/net/wireless/ti/wl1251/event.c event |= events_vector & mask; mask 111 drivers/net/wireless/ti/wl1251/event.h int wl1251_event_wait(struct wl1251 *wl, u32 mask, int timeout_ms); mask 208 drivers/net/wireless/ti/wl12xx/scan.c u32 rate, mask; mask 216 drivers/net/wireless/ti/wl12xx/scan.c mask = wlvif->bitrate_masks[band]; mask 218 drivers/net/wireless/ti/wl12xx/scan.c mask &= ~CONF_TX_CCK_RATES; mask 219 drivers/net/wireless/ti/wl12xx/scan.c if (!mask) mask 220 drivers/net/wireless/ti/wl12xx/scan.c mask = CONF_TX_RATE_MASK_BASIC_P2P; mask 222 drivers/net/wireless/ti/wl12xx/scan.c rate = wl1271_tx_min_rate_get(wl, mask); mask 233 drivers/net/wireless/ti/wl12xx/scan.c mask = wlvif->bitrate_masks[band]; mask 235 drivers/net/wireless/ti/wl12xx/scan.c mask &= ~CONF_TX_CCK_RATES; mask 236 drivers/net/wireless/ti/wl12xx/scan.c if (!mask) mask 237 drivers/net/wireless/ti/wl12xx/scan.c mask = CONF_TX_RATE_MASK_BASIC_P2P; mask 239 drivers/net/wireless/ti/wl12xx/scan.c rate = wl1271_tx_min_rate_get(wl, mask); mask 622 drivers/net/wireless/ti/wlcore/acx.c struct acx_event_mask *mask; mask 627 drivers/net/wireless/ti/wlcore/acx.c mask = kzalloc(sizeof(*mask), GFP_KERNEL); mask 628 drivers/net/wireless/ti/wlcore/acx.c if (!mask) { mask 634 drivers/net/wireless/ti/wlcore/acx.c mask->high_event_mask = cpu_to_le32(0xffffffff); mask 635 drivers/net/wireless/ti/wlcore/acx.c mask->event_mask = cpu_to_le32(event_mask); mask 638 drivers/net/wireless/ti/wlcore/acx.c mask, sizeof(*mask)); mask 645 drivers/net/wireless/ti/wlcore/acx.c kfree(mask); mask 165 drivers/net/wireless/ti/wlcore/cmd.c u32 mask, bool *timeout) mask 190 drivers/net/wireless/ti/wlcore/cmd.c (int)mask); mask 207 drivers/net/wireless/ti/wlcore/cmd.c event = *events_vector & mask; mask 214 drivers/net/wireless/ti/wlcore/cmd.c event |= *events_vector & mask; mask 95 drivers/net/wireless/ti/wlcore/cmd.h u32 mask, bool *timeout); mask 1350 drivers/net/wireless/ti/wlcore/main.c if (!p->mask) { mask 1365 drivers/net/wireless/ti/wlcore/main.c if (test_bit(i, (unsigned long *)p->mask)) { mask 1506 drivers/net/wireless/ti/wlcore/main.c if (!test_bit(i, (unsigned long *)p->mask)) { mask 1512 drivers/net/wireless/ti/wlcore/main.c if (!test_bit(j, (unsigned long *)p->mask)) mask 5450 drivers/net/wireless/ti/wlcore/main.c const struct cfg80211_bitrate_mask *mask) mask 5457 drivers/net/wireless/ti/wlcore/main.c mask->control[NL80211_BAND_2GHZ].legacy, mask 5458 drivers/net/wireless/ti/wlcore/main.c mask->control[NL80211_BAND_5GHZ].legacy); mask 5465 drivers/net/wireless/ti/wlcore/main.c mask->control[i].legacy, mask 81 drivers/nfc/port100.c #define PORT100_CMD_TYPE_IS_SUPPORTED(mask, cmd_type) \ mask 82 drivers/nfc/port100.c ((mask) & (0x01 << (cmd_type))) mask 1002 drivers/nfc/port100.c u64 mask; mask 1013 drivers/nfc/port100.c mask = 0; mask 1015 drivers/nfc/port100.c mask = be64_to_cpu(*(__be64 *)resp->data); mask 1019 drivers/nfc/port100.c return mask; mask 1311 drivers/nfc/port100.c u8 mask; mask 1315 drivers/nfc/port100.c mask = PORT100_MDAA_TGT_HAS_BEEN_ACTIVATED_MASK; mask 1318 drivers/nfc/port100.c mask = PORT100_MDAA_TGT_HAS_BEEN_ACTIVATED_MASK | mask 1326 drivers/nfc/port100.c return ((tgt_activated & mask) == mask); mask 268 drivers/ntb/hw/intel/ntb_hw_gen1.c u64 shift, mask; mask 271 drivers/ntb/hw/intel/ntb_hw_gen1.c mask = BIT_ULL(shift) - 1; mask 273 drivers/ntb/hw/intel/ntb_hw_gen1.c return mask << (shift * db_vector); mask 653 drivers/ntb/test/ntb_perf.c u64 mask; mask 671 drivers/ntb/test/ntb_perf.c mask = GENMASK_ULL(perf->pcnt, 0); mask 673 drivers/ntb/test/ntb_perf.c (ntb_db_valid_mask(perf->ntb) & mask) == mask) { mask 691 drivers/ntb/test/ntb_perf.c u64 mask, incmd_bit; mask 694 drivers/ntb/test/ntb_perf.c mask = ntb_db_valid_mask(perf->ntb); mask 695 drivers/ntb/test/ntb_perf.c (void)ntb_db_set_mask(perf->ntb, mask); mask 155 drivers/nubus/nubus.c nubus_move(&p, nubus_expand32(nd->data), nd->mask); mask 170 drivers/nubus/nubus.c *t++ = nubus_get_rom(&p, 1, dirent->mask); mask 183 drivers/nubus/nubus.c unsigned char c = nubus_get_rom(&p, 1, dirent->mask); mask 210 drivers/nubus/nubus.c dirent->mask); mask 216 drivers/nubus/nubus.c seq_putc(m, nubus_get_rom(&p, 1, dirent->mask)); mask 224 drivers/nubus/nubus.c dir->mask = board->lanes; mask 234 drivers/nubus/nubus.c dir->mask = fres->board->lanes; mask 246 drivers/nubus/nubus.c dir->mask = board->lanes; mask 263 drivers/nubus/nubus.c dir->mask = ent->mask; mask 279 drivers/nubus/nubus.c resid = nubus_get_rom(&nd->ptr, 4, nd->mask); mask 292 drivers/nubus/nubus.c ent->mask = nd->mask; mask 126 drivers/nubus/proc.c ent.mask = lanes; mask 232 drivers/nvdimm/bus.c u32 clear_err_unit, mask; mask 262 drivers/nvdimm/bus.c mask = clear_err_unit - 1; mask 263 drivers/nvdimm/bus.c if ((phys | len) & mask) mask 49 drivers/nvdimm/nd.h unsigned int mask = num - 1; mask 51 drivers/nvdimm/nd.h return ndrd->flush_wpq[dimm * num + (hint & mask)]; mask 58 drivers/nvdimm/nd.h unsigned int mask = num - 1; mask 60 drivers/nvdimm/nd.h ndrd->flush_wpq[dimm * num + (hint & mask)] = flush; mask 107 drivers/nvme/host/fabrics.c if (ctrl->opts->mask & NVMF_OPT_TRADDR) mask 109 drivers/nvme/host/fabrics.c if (ctrl->opts->mask & NVMF_OPT_TRSVCID) mask 112 drivers/nvme/host/fabrics.c if (ctrl->opts->mask & NVMF_OPT_HOST_TRADDR) mask 649 drivers/nvme/host/fabrics.c opts->mask |= token; mask 905 drivers/nvme/host/fabrics.c if ((opts->mask & required_opts) != required_opts) { mask 910 drivers/nvme/host/fabrics.c !(opt_tokens[i].token & opts->mask)) { mask 939 drivers/nvme/host/fabrics.c if ((opts->mask & NVMF_OPT_HOST_TRADDR) && mask 940 drivers/nvme/host/fabrics.c (ctrl->opts->mask & NVMF_OPT_HOST_TRADDR)) { mask 943 drivers/nvme/host/fabrics.c } else if ((opts->mask & NVMF_OPT_HOST_TRADDR) || mask 944 drivers/nvme/host/fabrics.c (ctrl->opts->mask & NVMF_OPT_HOST_TRADDR)) { mask 955 drivers/nvme/host/fabrics.c if (opts->mask & ~allowed_opts) { mask 959 drivers/nvme/host/fabrics.c if ((opt_tokens[i].token & opts->mask) && mask 1017 drivers/nvme/host/fabrics.c opts->mask &= ~NVMF_REQUIRED_OPTS; mask 94 drivers/nvme/host/fabrics.h unsigned mask; mask 541 drivers/nvme/host/rdma.c if (ctrl->ctrl.opts->mask & NVMF_OPT_HOST_TRADDR) mask 1986 drivers/nvme/host/rdma.c if (!(opts->mask & NVMF_OPT_TRSVCID)) { mask 1993 drivers/nvme/host/rdma.c opts->mask |= NVMF_OPT_TRSVCID; mask 2004 drivers/nvme/host/rdma.c if (opts->mask & NVMF_OPT_HOST_TRADDR) { mask 1335 drivers/nvme/host/tcp.c if (nctrl->opts->mask & NVMF_OPT_HOST_TRADDR) { mask 2306 drivers/nvme/host/tcp.c if (!(opts->mask & NVMF_OPT_TRSVCID)) { mask 2313 drivers/nvme/host/tcp.c opts->mask |= NVMF_OPT_TRSVCID; mask 2324 drivers/nvme/host/tcp.c if (opts->mask & NVMF_OPT_HOST_TRADDR) { mask 640 drivers/nvme/target/admin-cmd.c u16 nvmet_set_feat_async_event(struct nvmet_req *req, u32 mask) mask 644 drivers/nvme/target/admin-cmd.c if (val32 & ~mask) { mask 27 drivers/nvme/target/fcloop.c int mask; mask 64 drivers/nvme/target/fcloop.c opts->mask |= token; mask 914 drivers/nvme/target/fcloop.c if ((opts->mask & LPORT_OPTS) != LPORT_OPTS) { mask 1025 drivers/nvme/target/fcloop.c if ((opts->mask & opts_mask) != opts_mask) { mask 1037 drivers/nvme/target/fcloop.c if (opts->mask & NVMF_OPT_ROLES) mask 1039 drivers/nvme/target/fcloop.c if (opts->mask & NVMF_OPT_FCADDR) mask 1076 drivers/nvme/target/fcloop.c if (opts->mask & NVMF_OPT_ROLES) mask 1078 drivers/nvme/target/fcloop.c if (opts->mask & NVMF_OPT_FCADDR) mask 558 drivers/nvme/target/loop.c if ((ctrl->opts->mask & NVMF_OPT_TRADDR) && mask 364 drivers/nvme/target/nvmet.h u16 nvmet_set_feat_async_event(struct nvmet_req *req, u32 mask); mask 74 drivers/nvmem/imx-ocotp.c u32 c, mask; mask 76 drivers/nvmem/imx-ocotp.c mask = IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags; mask 80 drivers/nvmem/imx-ocotp.c if (!(c & mask)) mask 52 drivers/nvmem/meson-mx-efuse.c u32 mask, u32 set) mask 57 drivers/nvmem/meson-mx-efuse.c data &= ~mask; mask 58 drivers/nvmem/meson-mx-efuse.c data |= (set & mask); mask 1586 drivers/of/base.c const __be32 *map, *mask, *pass; mask 1640 drivers/of/base.c mask = of_get_property(cur, mask_name, NULL); mask 1641 drivers/of/base.c if (!mask) mask 1642 drivers/of/base.c mask = dummy_mask; mask 1649 drivers/of/base.c match &= !((match_array[i] ^ *map++) & mask[i]); mask 96 drivers/of/device.c u64 mask; mask 151 drivers/of/device.c mask = DMA_BIT_MASK(ilog2(dma_addr + size - 1) + 1); mask 152 drivers/of/device.c dev->coherent_dma_mask &= mask; mask 153 drivers/of/device.c *dev->dma_mask &= mask; mask 156 drivers/of/device.c dev->bus_dma_mask = mask; mask 294 drivers/parisc/ccio-dma.c #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \ mask 300 drivers/parisc/ccio-dma.c if ((0 == (*res_ptr & mask)) && !ret) { \ mask 301 drivers/parisc/ccio-dma.c *res_ptr |= mask; \ mask 308 drivers/parisc/ccio-dma.c #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \ mask 311 drivers/parisc/ccio-dma.c CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \ mask 313 drivers/parisc/ccio-dma.c CCIO_SEARCH_LOOP(ioa, res_idx, mask, size); mask 373 drivers/parisc/ccio-dma.c unsigned long mask = ~(~0UL >> pages_needed); mask 374 drivers/parisc/ccio-dma.c CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8); mask 416 drivers/parisc/ccio-dma.c #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \ mask 418 drivers/parisc/ccio-dma.c BUG_ON((*res_ptr & mask) != mask); \ mask 419 drivers/parisc/ccio-dma.c *res_ptr &= ~(mask); mask 450 drivers/parisc/ccio-dma.c unsigned long mask = ~(~0UL >> pages_mapped); mask 451 drivers/parisc/ccio-dma.c CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8); mask 702 drivers/parisc/ccio-dma.c ccio_dma_supported(struct device *dev, u64 mask) mask 711 drivers/parisc/ccio-dma.c return (int)(mask >= 0xffffffffUL); mask 263 drivers/parisc/dino.c #define DINO_PORT_IN(type, size, mask) \ mask 272 drivers/parisc/dino.c v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ mask 281 drivers/parisc/dino.c #define DINO_PORT_OUT(type, size, mask) \ mask 289 drivers/parisc/dino.c write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ mask 371 drivers/parisc/dino.c u32 mask; mask 378 drivers/parisc/dino.c mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; mask 380 drivers/parisc/dino.c if (mask == 0) mask 385 drivers/parisc/dino.c int local_irq = __ffs(mask); mask 388 drivers/parisc/dino.c __func__, irq, intr_dev, mask); mask 390 drivers/parisc/dino.c mask &= ~DINO_MASK_IRQ(local_irq); mask 391 drivers/parisc/dino.c } while (mask); mask 400 drivers/parisc/dino.c mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; mask 401 drivers/parisc/dino.c if (mask) { mask 405 drivers/parisc/dino.c dino_dev->hba.base_addr, mask); mask 887 drivers/parisc/lba_pci.c #define LBA_PORT_IN(size, mask) \ mask 928 drivers/parisc/lba_pci.c #define LBA_PORT_OUT(size, mask) \ mask 969 drivers/parisc/lba_pci.c #define LBA_PORT_IN(size, mask) \ mask 985 drivers/parisc/lba_pci.c #define LBA_PORT_OUT(size, mask) \ mask 312 drivers/parisc/led.c static unsigned char mask[4] = { LED_HEARTBEAT, LED_DISK_IO, mask 327 drivers/parisc/led.c if ((leds & mask[i]) != (lastleds & mask[i])) mask 332 drivers/parisc/led.c gsc_writeb( leds & mask[i] ? blockp[i]->on : mask 380 drivers/parisc/sba_iommu.c unsigned long mask; mask 386 drivers/parisc/sba_iommu.c mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; mask 391 drivers/parisc/sba_iommu.c DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); mask 392 drivers/parisc/sba_iommu.c WARN_ON(mask == 0); mask 397 drivers/parisc/sba_iommu.c if ((((*res_ptr) & mask) == 0) && !ret) { mask 398 drivers/parisc/sba_iommu.c *res_ptr |= mask; /* mark resources busy! */ mask 402 drivers/parisc/sba_iommu.c mask >>= o; mask 404 drivers/parisc/sba_iommu.c if (mask == 0) { mask 405 drivers/parisc/sba_iommu.c mask = RESMAP_MASK(bits_wanted); mask 671 drivers/parisc/sba_iommu.c static int sba_dma_supported( struct device *dev, u64 mask) mask 689 drivers/parisc/sba_iommu.c return((int)(mask >= (ioc->ibase - 1 + mask 114 drivers/parport/ieee1284.c unsigned char mask, mask 124 drivers/parport/ieee1284.c if ((status & mask) == result) mask 163 drivers/parport/ieee1284.c unsigned char mask, mask 183 drivers/parport/ieee1284.c ret = parport_poll_peripheral (port, mask, result, usec); mask 204 drivers/parport/ieee1284.c if ((status & mask) == result) mask 64 drivers/parport/ieee1284_ops.c unsigned char mask = (PARPORT_STATUS_ERROR mask 72 drivers/parport/ieee1284_ops.c if (!parport_wait_peripheral (port, mask, val)) mask 72 drivers/parport/parport_amiga.c static unsigned char amiga_frob_control( struct parport *p, unsigned char mask, unsigned char val) mask 76 drivers/parport/parport_amiga.c DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); mask 78 drivers/parport/parport_amiga.c amiga_write_control(p, (old & ~mask) ^ val); mask 77 drivers/parport/parport_atari.c parport_atari_frob_control(struct parport *p, unsigned char mask, mask 81 drivers/parport/parport_atari.c parport_atari_write_control(p, (old & ~mask) ^ val); mask 144 drivers/parport/parport_ax88796.c parport_ax88796_frob_control(struct parport *p, unsigned char mask, mask 151 drivers/parport/parport_ax88796.c mask, val, old); mask 153 drivers/parport/parport_ax88796.c parport_ax88796_write_control(p, (old & ~mask) | val); mask 92 drivers/parport/parport_gsc.h unsigned char mask, mask 100 drivers/parport/parport_gsc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); mask 102 drivers/parport/parport_gsc.h ctr = (ctr & ~mask) ^ val; mask 148 drivers/parport/parport_gsc.h unsigned char mask, mask 157 drivers/parport/parport_gsc.h if (mask & 0x20) { mask 168 drivers/parport/parport_gsc.h mask &= wm; mask 171 drivers/parport/parport_gsc.h return __parport_gsc_frob_control (p, mask, val); mask 818 drivers/parport/parport_ip32.c unsigned int mask, mask 822 drivers/parport/parport_ip32.c c = (parport_ip32_read_econtrol(p) & ~mask) ^ val; mask 919 drivers/parport/parport_ip32.c unsigned int mask, mask 923 drivers/parport/parport_ip32.c c = (__parport_ip32_read_control(p) & ~mask) ^ val; mask 968 drivers/parport/parport_ip32.c unsigned char mask, mask 973 drivers/parport/parport_ip32.c CHECK_EXTRA_BITS(p, mask, wm); mask 975 drivers/parport/parport_ip32.c __parport_ip32_frob_control(p, mask & wm, val & wm); mask 141 drivers/parport/parport_mfc3.c static unsigned char mfc3_frob_control( struct parport *p, unsigned char mask, unsigned char val) mask 145 drivers/parport/parport_mfc3.c DPRINTK(KERN_DEBUG "frob_control mask %02x, value %02x\n",mask,val); mask 147 drivers/parport/parport_mfc3.c mfc3_write_control(p, (old & ~mask) ^ val); mask 136 drivers/parport/parport_sunbpp.c unsigned char mask, mask 145 drivers/parport/parport_sunbpp.c if (mask & PARPORT_CONTROL_STROBE) { mask 152 drivers/parport/parport_sunbpp.c if (mask & PARPORT_CONTROL_AUTOFD) { mask 159 drivers/parport/parport_sunbpp.c if (mask & PARPORT_CONTROL_INIT) { mask 166 drivers/parport/parport_sunbpp.c if (mask & PARPORT_CONTROL_SELECT) { mask 143 drivers/pci/access.c u32 mask, tmp; mask 167 drivers/pci/access.c mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); mask 168 drivers/pci/access.c tmp = readl(addr) & mask; mask 652 drivers/pci/controller/dwc/pci-dra7xx.c u32 mask; mask 667 drivers/pci/controller/dwc/pci-dra7xx.c mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN; mask 669 drivers/pci/controller/dwc/pci-dra7xx.c regmap_update_bits(pcie_syscon, pcie_reg, mask, val); mask 608 drivers/pci/controller/dwc/pci-imx6.c unsigned int mask, val; mask 612 drivers/pci/controller/dwc/pci-imx6.c mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; mask 616 drivers/pci/controller/dwc/pci-imx6.c mask = IMX6Q_GPR12_DEVICE_TYPE; mask 621 drivers/pci/controller/dwc/pci-imx6.c regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); mask 190 drivers/pci/controller/dwc/pci-keystone.c const struct cpumask *mask, bool force) mask 1070 drivers/pci/controller/dwc/pci-keystone.c u32 mask; mask 1077 drivers/pci/controller/dwc/pci-keystone.c mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; mask 1080 drivers/pci/controller/dwc/pci-keystone.c ret = regmap_update_bits(syscon, 0, mask, val); mask 1095 drivers/pci/controller/dwc/pci-keystone.c u32 mask; mask 1102 drivers/pci/controller/dwc/pci-keystone.c mask = AM654_PCIE_DEV_TYPE_MASK; mask 1116 drivers/pci/controller/dwc/pci-keystone.c ret = regmap_update_bits(syscon, 0, mask, val); mask 146 drivers/pci/controller/dwc/pcie-armada8k.c u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; mask 150 drivers/pci/controller/dwc/pcie-armada8k.c if ((reg & mask) == mask) mask 142 drivers/pci/controller/dwc/pcie-designware-host.c const struct cpumask *mask, bool force) mask 131 drivers/pci/controller/dwc/pcie-uniphier.c u32 val, mask; mask 134 drivers/pci/controller/dwc/pcie-uniphier.c mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP; mask 136 drivers/pci/controller/dwc/pcie-uniphier.c return (val & mask) == mask; mask 466 drivers/pci/controller/pci-aardvark.c int reg, u32 old, u32 new, u32 mask) mask 680 drivers/pci/controller/pci-aardvark.c const struct cpumask *mask, bool force) mask 732 drivers/pci/controller/pci-aardvark.c u32 mask; mask 734 drivers/pci/controller/pci-aardvark.c mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); mask 735 drivers/pci/controller/pci-aardvark.c mask |= PCIE_ISR1_INTX_ASSERT(hwirq); mask 736 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); mask 743 drivers/pci/controller/pci-aardvark.c u32 mask; mask 745 drivers/pci/controller/pci-aardvark.c mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); mask 746 drivers/pci/controller/pci-aardvark.c mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); mask 747 drivers/pci/controller/pci-aardvark.c advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); mask 210 drivers/pci/controller/pci-mvebu.c u32 cmd, mask; mask 223 drivers/pci/controller/pci-mvebu.c mask = mvebu_readl(port, PCIE_MASK_OFF); mask 224 drivers/pci/controller/pci-mvebu.c mask |= PCIE_MASK_ENABLE_INTS; mask 225 drivers/pci/controller/pci-mvebu.c mvebu_writel(port, mask, PCIE_MASK_OFF); mask 474 drivers/pci/controller/pci-mvebu.c int reg, u32 old, u32 new, u32 mask) mask 523 drivers/pci/controller/pci-mvebu.c int reg, u32 old, u32 new, u32 mask) mask 2162 drivers/pci/controller/pci-tegra.c u32 lanes = 0, mask = 0; mask 2273 drivers/pci/controller/pci-tegra.c mask |= ((1 << value) - 1) << lane; mask 2332 drivers/pci/controller/pci-tegra.c err = tegra_pcie_get_regulators(pcie, mask); mask 211 drivers/pci/controller/pci-thunder-pem.c u32 mask = 0; mask 228 drivers/pci/controller/pci-thunder-pem.c mask = ~(0xff << (8 * (where & 3))); mask 229 drivers/pci/controller/pci-thunder-pem.c read_val &= mask; mask 237 drivers/pci/controller/pci-thunder-pem.c mask = ~(0xffff << (8 * (where & 3))); mask 238 drivers/pci/controller/pci-thunder-pem.c read_val &= mask; mask 252 drivers/pci/controller/pci-thunder-pem.c if (mask) { mask 256 drivers/pci/controller/pci-thunder-pem.c mask &= w1c_bits; mask 257 drivers/pci/controller/pci-thunder-pem.c val &= ~mask; mask 173 drivers/pci/controller/pci-xgene-msi.c const struct cpumask *mask, bool force) mask 175 drivers/pci/controller/pci-xgene-msi.c int target_cpu = cpumask_first(mask); mask 378 drivers/pci/controller/pci-xgene-msi.c cpumask_var_t mask; mask 399 drivers/pci/controller/pci-xgene-msi.c if (alloc_cpumask_var(&mask, GFP_KERNEL)) { mask 400 drivers/pci/controller/pci-xgene-msi.c cpumask_clear(mask); mask 401 drivers/pci/controller/pci-xgene-msi.c cpumask_set_cpu(cpu, mask); mask 402 drivers/pci/controller/pci-xgene-msi.c err = irq_set_affinity(msi_group->gic_irq, mask); mask 405 drivers/pci/controller/pci-xgene-msi.c free_cpumask_var(mask); mask 289 drivers/pci/controller/pci-xgene.c u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; mask 294 drivers/pci/controller/pci-xgene.c val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16); mask 298 drivers/pci/controller/pci-xgene.c val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16); mask 302 drivers/pci/controller/pci-xgene.c val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); mask 306 drivers/pci/controller/pci-xgene.c val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); mask 309 drivers/pci/controller/pci-xgene.c return mask; mask 374 drivers/pci/controller/pci-xgene.c u64 mask = 0; mask 386 drivers/pci/controller/pci-xgene.c mask = ~(size - 1) | flag; mask 393 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask)); mask 394 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); mask 497 drivers/pci/controller/pci-xgene.c u64 mask = ~(size - 1) | EN_REG; mask 522 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask)); mask 528 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask)); mask 529 drivers/pci/controller/pci-xgene.c xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask)); mask 105 drivers/pci/controller/pcie-altera-msi.c const struct cpumask *mask, bool force) mask 121 drivers/pci/controller/pcie-altera-msi.c u32 mask; mask 140 drivers/pci/controller/pcie-altera-msi.c mask = msi_readl(msi, MSI_INTMASK); mask 141 drivers/pci/controller/pcie-altera-msi.c mask |= 1 << bit; mask 142 drivers/pci/controller/pcie-altera-msi.c msi_writel(msi, mask, MSI_INTMASK); mask 152 drivers/pci/controller/pcie-altera-msi.c u32 mask; mask 161 drivers/pci/controller/pcie-altera-msi.c mask = msi_readl(msi, MSI_INTMASK); mask 162 drivers/pci/controller/pcie-altera-msi.c mask &= ~(1 << d->hwirq); mask 163 drivers/pci/controller/pcie-altera-msi.c msi_writel(msi, mask, MSI_INTMASK); mask 207 drivers/pci/controller/pcie-iproc-msi.c const struct cpumask *mask, bool force) mask 210 drivers/pci/controller/pcie-iproc-msi.c int target_cpu = cpumask_first(mask); mask 479 drivers/pci/controller/pcie-iproc-msi.c cpumask_var_t mask; mask 487 drivers/pci/controller/pcie-iproc-msi.c if (alloc_cpumask_var(&mask, GFP_KERNEL)) { mask 488 drivers/pci/controller/pcie-iproc-msi.c cpumask_clear(mask); mask 489 drivers/pci/controller/pcie-iproc-msi.c cpumask_set_cpu(cpu, mask); mask 490 drivers/pci/controller/pcie-iproc-msi.c ret = irq_set_affinity(msi->grps[i].gic_irq, mask); mask 495 drivers/pci/controller/pcie-iproc-msi.c free_cpumask_var(mask); mask 688 drivers/pci/controller/pcie-iproc.c u32 mask, tmp; mask 699 drivers/pci/controller/pcie-iproc.c mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); mask 700 drivers/pci/controller/pcie-iproc.c tmp = readl(addr) & mask; mask 415 drivers/pci/controller/pcie-mediatek.c const struct cpumask *mask, bool force) mask 347 drivers/pci/controller/pcie-mobiveil.c u32 bit, virq, val, mask; mask 358 drivers/pci/controller/pcie-mobiveil.c mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); mask 359 drivers/pci/controller/pcie-mobiveil.c intr_status = val & mask; mask 671 drivers/pci/controller/pcie-mobiveil.c u32 mask, shifted_val; mask 674 drivers/pci/controller/pcie-mobiveil.c mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); mask 677 drivers/pci/controller/pcie-mobiveil.c shifted_val &= ~mask; mask 687 drivers/pci/controller/pcie-mobiveil.c u32 shifted_val, mask; mask 690 drivers/pci/controller/pcie-mobiveil.c mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); mask 693 drivers/pci/controller/pcie-mobiveil.c shifted_val |= mask; mask 747 drivers/pci/controller/pcie-mobiveil.c const struct cpumask *mask, bool force) mask 176 drivers/pci/controller/pcie-rcar.c static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data) mask 181 drivers/pci/controller/pcie-rcar.c val &= ~(mask << shift); mask 343 drivers/pci/controller/pcie-rcar.c u32 mask; mask 352 drivers/pci/controller/pcie-rcar.c mask = (roundup_pow_of_two(size) / SZ_128) - 1; mask 353 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win)); mask 365 drivers/pci/controller/pcie-rcar.c mask = PAR_ENABLE; mask 367 drivers/pci/controller/pcie-rcar.c mask |= IO_SPACE; mask 369 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win)); mask 1030 drivers/pci/controller/pcie-rcar.c u64 mask; mask 1052 drivers/pci/controller/pcie-rcar.c mask = roundup_pow_of_two(size) - 1; mask 1053 drivers/pci/controller/pcie-rcar.c mask &= ~0xf; mask 1063 drivers/pci/controller/pcie-rcar.c rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, mask 134 drivers/pci/controller/pcie-rockchip-host.c u32 mask, tmp, offset; mask 145 drivers/pci/controller/pcie-rockchip-host.c mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); mask 152 drivers/pci/controller/pcie-rockchip-host.c tmp = readl(addr) & mask; mask 21 drivers/pci/controller/pcie-rockchip.h #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) mask 82 drivers/pci/controller/pcie-tango.c static int tango_set_affinity(struct irq_data *d, const struct cpumask *mask, mask 388 drivers/pci/controller/pcie-xilinx-nwl.c u32 mask; mask 392 drivers/pci/controller/pcie-xilinx-nwl.c mask = 1 << (data->hwirq - 1); mask 395 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); mask 404 drivers/pci/controller/pcie-xilinx-nwl.c u32 mask; mask 408 drivers/pci/controller/pcie-xilinx-nwl.c mask = 1 << (data->hwirq - 1); mask 411 drivers/pci/controller/pcie-xilinx-nwl.c nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); mask 465 drivers/pci/controller/pcie-xilinx-nwl.c const struct cpumask *mask, bool force) mask 392 drivers/pci/controller/pcie-xilinx.c u32 val, mask, status; mask 396 drivers/pci/controller/pcie-xilinx.c mask = pcie_read(port, XILINX_PCIE_REG_IMR); mask 398 drivers/pci/controller/pcie-xilinx.c status = val & mask; mask 390 drivers/pci/controller/vmd.c static int vmd_dma_supported(struct device *dev, u64 mask) mask 392 drivers/pci/controller/vmd.c return dma_supported(to_vmd_dev(dev), mask); mask 634 drivers/pci/hotplug/acpiphp_glue.c unsigned int mask = ACPI_STA_DEVICE_ENABLED | ACPI_STA_DEVICE_FUNCTIONING; mask 635 drivers/pci/hotplug/acpiphp_glue.c return (sta & mask) == mask; mask 989 drivers/pci/hotplug/ibmphp_hpc.c u8 mask; mask 996 drivers/pci/hotplug/ibmphp_hpc.c mask = 0x01 << i; mask 997 drivers/pci/hotplug/ibmphp_hpc.c if ((mask & old) != (mask & new)) { mask 138 drivers/pci/hotplug/pciehp_hpc.c u16 mask, bool wait) mask 157 drivers/pci/hotplug/pciehp_hpc.c slot_ctrl &= ~mask; mask 158 drivers/pci/hotplug/pciehp_hpc.c slot_ctrl |= (cmd & mask); mask 193 drivers/pci/hotplug/pciehp_hpc.c static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) mask 195 drivers/pci/hotplug/pciehp_hpc.c pcie_do_write_cmd(ctrl, cmd, mask, true); mask 199 drivers/pci/hotplug/pciehp_hpc.c static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) mask 201 drivers/pci/hotplug/pciehp_hpc.c pcie_do_write_cmd(ctrl, cmd, mask, false); mask 475 drivers/pci/hotplug/pciehp_hpc.c u16 cmd = 0, mask = 0; mask 479 drivers/pci/hotplug/pciehp_hpc.c mask |= PCI_EXP_SLTCTL_PIC; mask 484 drivers/pci/hotplug/pciehp_hpc.c mask |= PCI_EXP_SLTCTL_AIC; mask 488 drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd_nowait(ctrl, cmd, mask); mask 698 drivers/pci/hotplug/pciehp_hpc.c u16 cmd, mask; mask 724 drivers/pci/hotplug/pciehp_hpc.c mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | mask 729 drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd_nowait(ctrl, cmd, mask); mask 736 drivers/pci/hotplug/pciehp_hpc.c u16 mask; mask 738 drivers/pci/hotplug/pciehp_hpc.c mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | mask 742 drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd(ctrl, 0, mask); mask 755 drivers/pci/hotplug/pciehp_hpc.c u16 mask; mask 757 drivers/pci/hotplug/pciehp_hpc.c mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; mask 758 drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd(ctrl, mask, mask); mask 763 drivers/pci/hotplug/pciehp_hpc.c u16 mask; mask 772 drivers/pci/hotplug/pciehp_hpc.c mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; mask 773 drivers/pci/hotplug/pciehp_hpc.c pcie_write_cmd(ctrl, 0, mask); mask 423 drivers/pci/hotplug/pnv_php.c u16 new, mask; mask 429 drivers/pci/hotplug/pnv_php.c mask = PCI_EXP_SLTCTL_AIC; mask 436 drivers/pci/hotplug/pnv_php.c pcie_capability_clear_and_set_word(bridge, PCI_EXP_SLTCTL, mask, new); mask 173 drivers/pci/msi.c u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) mask 180 drivers/pci/msi.c mask_bits &= ~mask; mask 188 drivers/pci/msi.c static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) mask 190 drivers/pci/msi.c desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); mask 628 drivers/pci/msi.c unsigned mask; mask 637 drivers/pci/msi.c mask = msi_mask(entry->msi_attrib.multi_cap); mask 638 drivers/pci/msi.c msi_mask_irq(entry, mask, mask); mask 645 drivers/pci/msi.c msi_mask_irq(entry, mask, ~mask); mask 652 drivers/pci/msi.c msi_mask_irq(entry, mask, ~mask); mask 659 drivers/pci/msi.c msi_mask_irq(entry, mask, ~mask); mask 918 drivers/pci/msi.c u32 mask; mask 931 drivers/pci/msi.c mask = msi_mask(desc->msi_attrib.multi_cap); mask 933 drivers/pci/msi.c __pci_msi_desc_mask_irq(desc, mask, ~mask); mask 1300 drivers/pci/msi.c return &entry->affinity->mask; mask 1312 drivers/pci/msi.c return &entry->affinity[nr].mask; mask 1326 drivers/pci/msi.c const struct cpumask *mask; mask 1328 drivers/pci/msi.c mask = pci_irq_get_affinity(pdev, vec); mask 1329 drivers/pci/msi.c if (mask) mask 1330 drivers/pci/msi.c return local_memory_node(cpu_to_node(cpumask_first(mask))); mask 387 drivers/pci/pci-bridge-emul.c int mask, ret, old, new, shift; mask 389 drivers/pci/pci-bridge-emul.c u32 old, u32 new, u32 mask); mask 402 drivers/pci/pci-bridge-emul.c mask = 0xffffffff; mask 404 drivers/pci/pci-bridge-emul.c mask = 0xffff << shift; mask 406 drivers/pci/pci-bridge-emul.c mask = 0xff << shift; mask 426 drivers/pci/pci-bridge-emul.c new = old & (~mask | ~behavior[reg / 4].rw); mask 429 drivers/pci/pci-bridge-emul.c new |= (value << shift) & (behavior[reg / 4].rw & mask); mask 432 drivers/pci/pci-bridge-emul.c new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); mask 437 drivers/pci/pci-bridge-emul.c write_op(bridge, reg, old, new, mask); mask 100 drivers/pci/pci-bridge-emul.h u32 old, u32 new, u32 mask); mask 107 drivers/pci/pci-bridge-emul.h u32 old, u32 new, u32 mask); mask 81 drivers/pci/pci-sysfs.c const struct cpumask *mask; mask 84 drivers/pci/pci-sysfs.c mask = (dev_to_node(dev) == -1) ? cpu_online_mask : mask 87 drivers/pci/pci-sysfs.c mask = cpumask_of_pcibus(to_pci_dev(dev)->bus); mask 89 drivers/pci/pci-sysfs.c return cpumap_print_to_pagebuf(list, buf, mask); mask 554 drivers/pci/pci.c u8 cap, mask; mask 557 drivers/pci/pci.c mask = HT_3BIT_CAP_MASK; mask 559 drivers/pci/pci.c mask = HT_5BIT_CAP_MASK; mask 568 drivers/pci/pci.c if ((cap & mask) == ht_cap) mask 720 drivers/pci/pci.c int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) mask 731 drivers/pci/pci.c if (!(status & mask)) mask 4341 drivers/pci/pci.c static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) mask 4368 drivers/pci/pci.c if (mask != irq_pending) { mask 4375 drivers/pci/pci.c if (mask) mask 438 drivers/pci/pci.h unsigned int mask; /* COR/UNCOR Error Mask */ mask 685 drivers/pci/pcie/aer.c status = (info->status & ~info->mask); mask 722 drivers/pci/pcie/aer.c status = (info->status & ~info->mask); mask 765 drivers/pci/pcie/aer.c info->status, info->mask); mask 776 drivers/pci/pcie/aer.c trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), mask 810 drivers/pci/pcie/aer.c u32 status, mask; mask 815 drivers/pci/pcie/aer.c mask = aer->cor_mask; mask 818 drivers/pci/pcie/aer.c mask = aer->uncor_mask; mask 828 drivers/pci/pcie/aer.c info.mask = mask; mask 831 drivers/pci/pcie/aer.c pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); mask 843 drivers/pci/pcie/aer.c trace_aer_event(dev_name(&dev->dev), (status & ~mask), mask 871 drivers/pci/pcie/aer.c u32 status, mask; mask 912 drivers/pci/pcie/aer.c pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &mask); mask 915 drivers/pci/pcie/aer.c pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask); mask 917 drivers/pci/pcie/aer.c if (status & ~mask) mask 1104 drivers/pci/pcie/aer.c &info->mask); mask 1105 drivers/pci/pcie/aer.c if (!(info->status & ~info->mask)) mask 1115 drivers/pci/pcie/aer.c &info->mask); mask 1116 drivers/pci/pcie/aer.c if (!(info->status & ~info->mask)) mask 154 drivers/pci/pcie/dpc.c u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix; mask 158 drivers/pci/pcie/dpc.c pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask); mask 160 drivers/pci/pcie/dpc.c status, mask); mask 173 drivers/pci/pcie/dpc.c if ((status & ~mask) & (1 << i)) mask 209 drivers/pci/pcie/dpc.c u32 status, mask, sev; mask 212 drivers/pci/pcie/dpc.c pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask); mask 213 drivers/pci/pcie/dpc.c status &= ~mask; mask 45 drivers/pci/pcie/portdrv_core.c static int pcie_message_numbers(struct pci_dev *dev, int mask, mask 58 drivers/pci/pcie/portdrv_core.c if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | mask 66 drivers/pci/pcie/portdrv_core.c if (mask & PCIE_PORT_SERVICE_AER) { mask 79 drivers/pci/pcie/portdrv_core.c if (mask & PCIE_PORT_SERVICE_DPC) { mask 101 drivers/pci/pcie/portdrv_core.c static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) mask 113 drivers/pci/pcie/portdrv_core.c nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc); mask 140 drivers/pci/pcie/portdrv_core.c if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | mask 148 drivers/pci/pcie/portdrv_core.c if (mask & PCIE_PORT_SERVICE_AER) mask 151 drivers/pci/pcie/portdrv_core.c if (mask & PCIE_PORT_SERVICE_DPC) mask 165 drivers/pci/pcie/portdrv_core.c static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask) mask 177 drivers/pci/pcie/portdrv_core.c if ((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) mask 181 drivers/pci/pcie/portdrv_core.c if (pcie_port_enable_irq_vec(dev, irqs, mask) == 0) mask 109 drivers/pci/probe.c static u64 pci_size(u64 base, u64 maxbase, u64 mask) mask 111 drivers/pci/probe.c u64 size = mask & maxbase; /* Find the significant bits */ mask 125 drivers/pci/probe.c if (base == maxbase && ((base | (size - 1)) & mask) != mask) mask 178 drivers/pci/probe.c u32 l = 0, sz = 0, mask; mask 183 drivers/pci/probe.c mask = type ? PCI_ROM_ADDRESS_MASK : ~0; mask 197 drivers/pci/probe.c pci_write_config_dword(dev, pos, l | mask); mask 664 drivers/pci/quirks.c u32 mask, size, base; mask 669 drivers/pci/quirks.c mask = (devres >> 16) & 15; mask 674 drivers/pci/quirks.c if ((bit & mask) == bit) mask 690 drivers/pci/quirks.c u32 mask, size, base; mask 696 drivers/pci/quirks.c mask = (devres & 0x3f) << 16; mask 700 drivers/pci/quirks.c if ((bit & mask) == bit) mask 861 drivers/pci/quirks.c u32 mask, base; mask 871 drivers/pci/quirks.c mask = (val >> 16) & 0xfc; mask 872 drivers/pci/quirks.c mask |= 3; mask 878 drivers/pci/quirks.c pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); mask 306 drivers/pci/setup-bus.c unsigned long mask = 0; mask 310 drivers/pci/setup-bus.c mask |= fail_res->flags; mask 317 drivers/pci/setup-bus.c return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); mask 320 drivers/pci/setup-bus.c static bool pci_need_to_release(unsigned long mask, struct resource *res) mask 323 drivers/pci/setup-bus.c return !!(mask & IORESOURCE_IO); mask 327 drivers/pci/setup-bus.c if (mask & IORESOURCE_PREFETCH) mask 330 drivers/pci/setup-bus.c else if ((mask & IORESOURCE_MEM) && mask 338 drivers/pci/setup-bus.c return !!(mask & IORESOURCE_MEM); mask 971 drivers/pci/setup-bus.c static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, mask 982 drivers/pci/setup-bus.c mask | IORESOURCE_PREFETCH, type); mask 1002 drivers/pci/setup-bus.c ((r->flags & mask) != type && mask 1003 drivers/pci/setup-bus.c (r->flags & mask) != type2 && mask 1004 drivers/pci/setup-bus.c (r->flags & mask) != type3)) mask 1180 drivers/pci/setup-bus.c unsigned long mask, prefmask, type2 = 0, type3 = 0; mask 1228 drivers/pci/setup-bus.c mask = IORESOURCE_MEM; mask 1243 drivers/pci/setup-bus.c mask = prefmask; mask 1266 drivers/pci/setup-bus.c mask = prefmask; mask 1287 drivers/pci/setup-bus.c pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, mask 1304 drivers/pci/setup-bus.c unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | mask 1311 drivers/pci/setup-bus.c if ((r->flags & mask) == (parent_r->flags & mask) && mask 30 drivers/pci/setup-res.c u32 new, check, mask; mask 60 drivers/pci/setup-res.c mask = (u32)PCI_BASE_ADDRESS_IO_MASK; mask 63 drivers/pci/setup-res.c mask = PCI_ROM_ADDRESS_MASK; mask 65 drivers/pci/setup-res.c mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; mask 101 drivers/pci/setup-res.c if ((new ^ check) & mask) { mask 455 drivers/pci/setup-res.c int pci_enable_resources(struct pci_dev *dev, int mask) mask 465 drivers/pci/setup-res.c if (!(mask & (1 << i))) mask 227 drivers/pcmcia/i82092.c static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) mask 237 drivers/pcmcia/i82092.c val |= mask; mask 244 drivers/pcmcia/i82092.c static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) mask 254 drivers/pcmcia/i82092.c val &= ~mask; mask 243 drivers/pcmcia/i82365.c static void i365_bset(u_short sock, u_short reg, u_char mask) mask 246 drivers/pcmcia/i82365.c d |= mask; mask 250 drivers/pcmcia/i82365.c static void i365_bclr(u_short sock, u_short reg, u_char mask) mask 253 drivers/pcmcia/i82365.c d &= ~mask; mask 257 drivers/pcmcia/i82365.c static void i365_bflip(u_short sock, u_short reg, u_char mask, int b) mask 261 drivers/pcmcia/i82365.c d |= mask; mask 263 drivers/pcmcia/i82365.c d &= ~mask; mask 325 drivers/pcmcia/i82365.c u_int mask = 0xffff; mask 340 drivers/pcmcia/i82365.c mask &= ~0x8000; mask 343 drivers/pcmcia/i82365.c mask &= ~0x1000; mask 347 drivers/pcmcia/i82365.c mask &= ~0x0600; mask 367 drivers/pcmcia/i82365.c return mask; mask 675 drivers/pcmcia/i82365.c u_int mask = 0, i, base; mask 688 drivers/pcmcia/i82365.c mask = irq_mask; mask 690 drivers/pcmcia/i82365.c for (i = mask = 0; i < irq_list_count; i++) mask 691 drivers/pcmcia/i82365.c mask |= (1<<irq_list[i]); mask 692 drivers/pcmcia/i82365.c mask &= I365_MASK & set_bridge_opts(base, ns); mask 694 drivers/pcmcia/i82365.c mask = isa_scan(base, mask); mask 698 drivers/pcmcia/i82365.c u_int tmp = (mask & 0xff20); mask 706 drivers/pcmcia/i82365.c u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); mask 730 drivers/pcmcia/i82365.c t[i].socket.irq_mask = mask; mask 731 drivers/pcmcia/pcmcia_resource.c u32 mask = s->irq_mask; mask 741 drivers/pcmcia/pcmcia_resource.c if (!((mask >> irq) & 1)) mask 113 drivers/pcmcia/pd6729.c unsigned char mask) mask 124 drivers/pcmcia/pd6729.c val |= mask; mask 131 drivers/pcmcia/pd6729.c unsigned char mask) mask 142 drivers/pcmcia/pd6729.c val &= ~mask; mask 594 drivers/pcmcia/pd6729.c u_int mask0, mask = 0; mask 608 drivers/pcmcia/pd6729.c mask |= (1 << i); mask 612 drivers/pcmcia/pd6729.c if (mask & (1<<i)) mask 613 drivers/pcmcia/pd6729.c printk("%s%d", ((mask & ((1<<i)-1)) ? "," : ""), i); mask 615 drivers/pcmcia/pd6729.c if (mask == 0) mask 620 drivers/pcmcia/pd6729.c return mask; mask 627 drivers/pcmcia/pd6729.c u_int mask; mask 674 drivers/pcmcia/pd6729.c mask = pd6729_isa_scan(); mask 675 drivers/pcmcia/pd6729.c if (irq_mode == 0 && mask == 0) { mask 685 drivers/pcmcia/pd6729.c socket[i].socket.irq_mask = mask; mask 22 drivers/pcmcia/rsrc_iodyn.c unsigned long mask; mask 33 drivers/pcmcia/rsrc_iodyn.c start = (res->start & ~data->mask) + data->offset; mask 35 drivers/pcmcia/rsrc_iodyn.c start += data->mask + 1; mask 65 drivers/pcmcia/rsrc_iodyn.c data.mask = align - 1; mask 66 drivers/pcmcia/rsrc_iodyn.c data.offset = base & data.mask; mask 584 drivers/pcmcia/rsrc_nonstatic.c unsigned long mask; mask 596 drivers/pcmcia/rsrc_nonstatic.c ret = (start & ~align_data->mask) + align_data->offset; mask 598 drivers/pcmcia/rsrc_nonstatic.c ret += align_data->mask + 1; mask 693 drivers/pcmcia/rsrc_nonstatic.c data.mask = align - 1; mask 694 drivers/pcmcia/rsrc_nonstatic.c data.offset = base & data.mask; mask 814 drivers/pcmcia/rsrc_nonstatic.c data.mask = align - 1; mask 815 drivers/pcmcia/rsrc_nonstatic.c data.offset = base & data.mask; mask 69 drivers/pcmcia/sa11xx_base.h #define MECR_SET(mecr, sock, shift, mask, bs) \ mask 70 drivers/pcmcia/sa11xx_base.h ((mecr)=((mecr)&~(((mask)<<(shift))<<\ mask 74 drivers/pcmcia/sa11xx_base.h #define MECR_GET(mecr, sock, shift, mask) \ mask 76 drivers/pcmcia/sa11xx_base.h (shift))&(mask)) mask 662 drivers/pcmcia/soc_common.c unsigned int mask; mask 695 drivers/pcmcia/soc_common.c if (val & bits[i].mask) mask 157 drivers/pcmcia/socket_sysfs.c u32 mask; mask 162 drivers/pcmcia/socket_sysfs.c ret = sscanf(buf, "0x%x\n", &mask); mask 166 drivers/pcmcia/socket_sysfs.c s->irq_mask &= mask; mask 364 drivers/pcmcia/tcic.c u_int mask, scan; mask 444 drivers/pcmcia/tcic.c mask = irq_mask; mask 446 drivers/pcmcia/tcic.c for (i = mask = 0; i < irq_list_count; i++) mask 447 drivers/pcmcia/tcic.c mask |= (1<<irq_list[i]); mask 450 drivers/pcmcia/tcic.c mask &= 0x4cf8; mask 452 drivers/pcmcia/tcic.c mask = irq_scan(mask); mask 454 drivers/pcmcia/tcic.c socket_table[i].socket.irq_mask = mask; mask 457 drivers/pcmcia/tcic.c scan = (mask & (mask-1)); mask 463 drivers/pcmcia/tcic.c u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); mask 919 drivers/pcmcia/ti113x.h #define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) { \ mask 924 drivers/pcmcia/ti113x.h .driver_data = ((mask) << 8 | (bits)), \ mask 941 drivers/pcmcia/ti113x.h u8 test_c9, old_c9, mask, bits; mask 951 drivers/pcmcia/ti113x.h mask = (id->driver_data >> 8) & 0xFF; mask 954 drivers/pcmcia/ti113x.h test_c9 = (test_c9 & ~mask) | bits; mask 696 drivers/pcmcia/yenta_socket.c unsigned mask; mask 704 drivers/pcmcia/yenta_socket.c mask = ~0xfff; mask 706 drivers/pcmcia/yenta_socket.c mask = ~3; mask 711 drivers/pcmcia/yenta_socket.c region.start = config_readl(socket, addr_start) & mask; mask 712 drivers/pcmcia/yenta_socket.c region.end = config_readl(socket, addr_end) | ~mask; mask 917 drivers/pcmcia/yenta_socket.c u32 mask; mask 940 drivers/pcmcia/yenta_socket.c mask = probe_irq_mask(val) & 0xffff; mask 942 drivers/pcmcia/yenta_socket.c return mask; mask 132 drivers/perf/arm-cci.c unsigned long *mask); mask 646 drivers/perf/arm-cci.c DECLARE_BITMAP(mask, HW_CNTRS_MAX); mask 648 drivers/perf/arm-cci.c bitmap_zero(mask, cci_pmu->num_cntrs); mask 659 drivers/perf/arm-cci.c set_bit(i, mask); mask 664 drivers/perf/arm-cci.c pmu_write_counters(cci_pmu, mask); mask 764 drivers/perf/arm-cci.c pmu_save_counters(struct cci_pmu *cci_pmu, unsigned long *mask) mask 770 drivers/perf/arm-cci.c set_bit(i, mask); mask 781 drivers/perf/arm-cci.c pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask) mask 785 drivers/perf/arm-cci.c for_each_set_bit(i, mask, cci_pmu->num_cntrs) mask 896 drivers/perf/arm-cci.c static void __pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask) mask 901 drivers/perf/arm-cci.c for_each_set_bit(i, mask, cci_pmu->num_cntrs) { mask 910 drivers/perf/arm-cci.c static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask) mask 913 drivers/perf/arm-cci.c cci_pmu->model->write_counters(cci_pmu, mask); mask 915 drivers/perf/arm-cci.c __pmu_write_counters(cci_pmu, mask); mask 949 drivers/perf/arm-cci.c static void cci5xx_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask) mask 963 drivers/perf/arm-cci.c for_each_set_bit(i, mask, cci_pmu->num_cntrs) { mask 1257 drivers/perf/arm-cci.c unsigned long mask[BITS_TO_LONGS(HW_CNTRS_MAX)]; mask 1263 drivers/perf/arm-cci.c .used_mask = mask, mask 1265 drivers/perf/arm-cci.c memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long)); mask 240 drivers/perf/arm-ccn.c static CCN_FORMAT_ATTR(mask, "config:30-33"); mask 272 drivers/perf/arm-ccn.c int mask; mask 289 drivers/perf/arm-ccn.c .def = _def, .mask = _mask, } mask 294 drivers/perf/arm-ccn.c .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } mask 299 drivers/perf/arm-ccn.c .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, } mask 338 drivers/perf/arm-ccn.c if (event->mask) mask 340 drivers/perf/arm-ccn.c event->mask); mask 477 drivers/perf/arm-ccn.c u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); mask 479 drivers/perf/arm-ccn.c return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL; mask 486 drivers/perf/arm-ccn.c u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name); mask 489 drivers/perf/arm-ccn.c if (mask) mask 490 drivers/perf/arm-ccn.c err = kstrtoull(buf, 0, mask); mask 877 drivers/perf/arm-ccn.c u64 prev_count, new_count, mask; mask 884 drivers/perf/arm-ccn.c mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1; mask 886 drivers/perf/arm-ccn.c local64_add((new_count - prev_count) & mask, &event->count); mask 608 drivers/perf/arm_dsu_pmu.c static int dsu_pmu_dt_get_cpus(struct device_node *dev, cpumask_t *mask) mask 629 drivers/perf/arm_dsu_pmu.c cpumask_set_cpu(cpu, mask); mask 35 drivers/perf/arm_pmu_platform.c if ((cpuid & info->mask) != info->cpuid) mask 1098 drivers/perf/arm_spe_pmu.c cpumask_t *mask = &spe_pmu->supported_cpus; mask 1101 drivers/perf/arm_spe_pmu.c ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1); mask 122 drivers/phy/amlogic/phy-meson8b-usb2.c u32 reg, u32 mask, u32 value) mask 127 drivers/phy/amlogic/phy-meson8b-usb2.c data &= ~mask; mask 128 drivers/phy/amlogic/phy-meson8b-usb2.c data |= (value & mask); mask 261 drivers/phy/broadcom/phy-bcm-ns-usb3.c u32 mask, u32 value, unsigned long timeout) mask 268 drivers/phy/broadcom/phy-bcm-ns-usb3.c if ((val & mask) == value) mask 418 drivers/phy/broadcom/phy-brcm-usb-init.c u32 mask; mask 421 drivers/phy/broadcom/phy-brcm-usb-init.c mask = params->usb_reg_bits_map[field]; mask 423 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(brcmusb_readl(reg) & ~mask, reg); mask 430 drivers/phy/broadcom/phy-brcm-usb-init.c u32 mask; mask 433 drivers/phy/broadcom/phy-brcm-usb-init.c mask = params->usb_reg_bits_map[field]; mask 435 drivers/phy/broadcom/phy-brcm-usb-init.c brcmusb_writel(brcmusb_readl(reg) | mask, reg); mask 369 drivers/phy/cadence/phy-cadence-dp.c u32 mask = 0; mask 389 drivers/phy/cadence/phy-cadence-dp.c mask = 0x0000003f; mask 394 drivers/phy/cadence/phy-cadence-dp.c mask = 0x00003f3f; mask 399 drivers/phy/cadence/phy-cadence-dp.c mask = 0x3f3f3f3f; mask 406 drivers/phy/cadence/phy-cadence-dp.c read_val, (read_val & mask) == write_val1, 0, mask 418 drivers/phy/cadence/phy-cadence-dp.c read_val, (read_val & mask) == write_val2, 0, mask 68 drivers/phy/hisilicon/phy-hi3660-usb3.c u32 val, mask; mask 90 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; mask 91 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL0, mask, val); mask 96 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; mask 97 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL7, mask, val); mask 102 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = USBOTG3CTRL2_POWERDOWN_HSP | USBOTG3CTRL2_POWERDOWN_SSP; mask 103 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL2, mask, 0); mask 121 drivers/phy/hisilicon/phy-hi3660-usb3.c mask = val; mask 122 drivers/phy/hisilicon/phy-hi3660-usb3.c ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL3, mask, val); mask 51 drivers/phy/hisilicon/phy-hi6220-usb.c u32 val, mask; mask 55 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val; mask 56 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val); mask 57 drivers/phy/hisilicon/phy-hi6220-usb.c regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val); mask 63 drivers/phy/hisilicon/phy-hi6220-usb.c u32 val, mask; mask 68 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val | CTRL5_PICOPHY_BC_MODE; mask 69 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val); mask 75 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE; mask 76 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); mask 85 drivers/phy/hisilicon/phy-hi6220-usb.c mask = val; mask 86 drivers/phy/hisilicon/phy-hi6220-usb.c ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val); mask 40 drivers/phy/hisilicon/phy-histb-combphy.c u32 mask; mask 101 drivers/phy/hisilicon/phy-histb-combphy.c return regmap_update_bits(syscon, mode->reg, mode->mask, mask 236 drivers/phy/hisilicon/phy-histb-combphy.c mode->mask = vals[2]; mask 58 drivers/phy/marvell/phy-armada38x-comphy.c unsigned int offset, u32 mask, u32 value) mask 62 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->base + offset) & ~mask; mask 76 drivers/phy/marvell/phy-armada38x-comphy.c unsigned int offset, u32 mask, u32 value) mask 82 drivers/phy/marvell/phy-armada38x-comphy.c (val & mask) == value, mask 66 drivers/phy/marvell/phy-berlin-sata.c u32 phy_base, u32 reg, u32 mask, u32 val) mask 75 drivers/phy/marvell/phy-berlin-sata.c regval &= ~mask; mask 47 drivers/phy/marvell/phy-pxa-28nm-hsic.c static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) mask 51 drivers/phy/marvell/phy-pxa-28nm-hsic.c if ((readl(reg) & mask) == mask) mask 141 drivers/phy/marvell/phy-pxa-28nm-usb2.c static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout) mask 145 drivers/phy/marvell/phy-pxa-28nm-usb2.c if ((readl(reg) & mask) == mask) mask 341 drivers/phy/mscc/phy-ocelot-serdes.c u32 mask; mask 350 drivers/phy/mscc/phy-ocelot-serdes.c .mask = _mask, \ mask 419 drivers/phy/mscc/phy-ocelot-serdes.c ocelot_serdes_muxes[i].mask, mask 75 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c static int read_poll_timeout(void __iomem *addr, u32 mask) mask 80 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c if (readl_relaxed(addr) & mask) mask 86 drivers/phy/qualcomm/phy-qcom-apq8064-sata.c return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; mask 1373 drivers/phy/qualcomm/phy-qcom-qmp.c unsigned int mask, val; mask 1380 drivers/phy/qualcomm/phy-qcom-qmp.c mask = cfg->mask_com_pcs_ready; mask 1382 drivers/phy/qualcomm/phy-qcom-qmp.c ret = readl_poll_timeout(status, val, (val & mask), 10, mask 1452 drivers/phy/qualcomm/phy-qcom-qmp.c unsigned int mask, val, ready; mask 1542 drivers/phy/qualcomm/phy-qcom-qmp.c mask = PCS_READY; mask 1546 drivers/phy/qualcomm/phy-qcom-qmp.c mask = PHYSTATUS; mask 1550 drivers/phy/qualcomm/phy-qcom-qmp.c ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, mask 338 drivers/phy/qualcomm/phy-qcom-qusb2.c u32 val, u32 mask) mask 343 drivers/phy/qualcomm/phy-qcom-qusb2.c reg &= ~mask; mask 344 drivers/phy/qualcomm/phy-qcom-qusb2.c reg |= val & mask; mask 23 drivers/phy/rockchip/phy-rockchip-emmc.c #define HIWORD_UPDATE(val, mask, shift) \ mask 24 drivers/phy/rockchip/phy-rockchip-emmc.c ((val) << (shift) | (mask) << ((shift) + 16)) mask 397 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u8 mask, u8 val) mask 399 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c regmap_update_bits(inno->regmap, reg * 4, mask, val); mask 233 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int val, mask, tmp; mask 236 drivers/phy/rockchip/phy-rockchip-inno-usb2.c mask = GENMASK(reg->bitend, reg->bitstart); mask 237 drivers/phy/rockchip/phy-rockchip-inno-usb2.c val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); mask 247 drivers/phy/rockchip/phy-rockchip-inno-usb2.c unsigned int mask = GENMASK(reg->bitend, reg->bitstart); mask 253 drivers/phy/rockchip/phy-rockchip-inno-usb2.c tmp = (orig & mask) >> reg->bitstart; mask 26 drivers/phy/rockchip/phy-rockchip-pcie.c #define HIWORD_UPDATE(val, mask, shift) \ mask 27 drivers/phy/rockchip/phy-rockchip-pcie.c ((val) << (shift) | (mask) << ((shift) + 16)) mask 563 drivers/phy/rockchip/phy-rockchip-typec.c u32 mask = 1 << reg->write_enable; mask 566 drivers/phy/rockchip/phy-rockchip-typec.c return regmap_write(tcphy->grf_regs, reg->offset, val | mask); mask 28 drivers/phy/rockchip/phy-rockchip-usb.c #define HIWORD_UPDATE(val, mask) \ mask 29 drivers/phy/rockchip/phy-rockchip-usb.c ((val) | (mask) << 16) mask 128 drivers/phy/samsung/phy-exynos4210-usb2.c u32 mask; mask 133 drivers/phy/samsung/phy-exynos4210-usb2.c mask = EXYNOS_4210_USB_ISOL_DEVICE; mask 137 drivers/phy/samsung/phy-exynos4210-usb2.c mask = EXYNOS_4210_USB_ISOL_HOST; mask 143 drivers/phy/samsung/phy-exynos4210-usb2.c regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); mask 169 drivers/phy/samsung/phy-exynos4x12-usb2.c u32 mask; mask 175 drivers/phy/samsung/phy-exynos4x12-usb2.c mask = EXYNOS_4x12_USB_ISOL_OTG; mask 179 drivers/phy/samsung/phy-exynos4x12-usb2.c mask = EXYNOS_4x12_USB_ISOL_HSIC0; mask 183 drivers/phy/samsung/phy-exynos4x12-usb2.c mask = EXYNOS_4x12_USB_ISOL_HSIC1; mask 189 drivers/phy/samsung/phy-exynos4x12-usb2.c regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); mask 179 drivers/phy/samsung/phy-exynos5250-usb2.c u32 mask; mask 184 drivers/phy/samsung/phy-exynos5250-usb2.c mask = EXYNOS_5250_USB_ISOL_OTG; mask 188 drivers/phy/samsung/phy-exynos5250-usb2.c mask = EXYNOS_5250_USB_ISOL_HOST; mask 194 drivers/phy/samsung/phy-exynos5250-usb2.c regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); mask 92 drivers/phy/samsung/phy-s5pv210-usb2.c u32 mask; mask 96 drivers/phy/samsung/phy-s5pv210-usb2.c mask = S5PV210_USB_ISOL_DEVICE; mask 99 drivers/phy/samsung/phy-s5pv210-usb2.c mask = S5PV210_USB_ISOL_HOST; mask 106 drivers/phy/samsung/phy-s5pv210-usb2.c mask, on ? 0 : mask); mask 67 drivers/phy/socionext/phy-uniphier-pcie.c u32 reg, u32 mask, u32 param) mask 78 drivers/phy/socionext/phy-uniphier-pcie.c val &= ~FIELD_PREP(TESTI_DAT_MASK, mask); mask 79 drivers/phy/socionext/phy-uniphier-pcie.c val = FIELD_PREP(TESTI_DAT_MASK, mask & param); mask 809 drivers/phy/st/phy-miphy28lp.c u8 mask = HFC_PLL | HFC_RDY; mask 817 drivers/phy/st/phy-miphy28lp.c mask |= PHY_RDY; mask 821 drivers/phy/st/phy-miphy28lp.c if ((val & mask) != mask) mask 409 drivers/phy/tegra/xusb-tegra124.c .mask = _mask, \ mask 117 drivers/phy/tegra/xusb-tegra186.c .mask = _mask, \ mask 844 drivers/phy/tegra/xusb-tegra210.c .mask = _mask, \ mask 320 drivers/phy/tegra/xusb.c value &= ~(soc->mask << soc->shift); mask 33 drivers/phy/tegra/xusb.h unsigned int mask; mask 124 drivers/phy/ti/phy-dm816x-usb.c unsigned int mask, val; mask 127 drivers/phy/ti/phy-dm816x-usb.c mask = BIT(phy->instance); mask 130 drivers/phy/ti/phy-dm816x-usb.c mask, val); mask 142 drivers/phy/ti/phy-dm816x-usb.c unsigned int mask, val; mask 155 drivers/phy/ti/phy-dm816x-usb.c mask = BIT(phy->instance); mask 158 drivers/phy/ti/phy-dm816x-usb.c mask, val); mask 112 drivers/phy/ti/phy-omap-usb2.c phy->mask, val); mask 208 drivers/phy/ti/phy-omap-usb2.c .mask = OMAP_DEV_PHY_PD, mask 215 drivers/phy/ti/phy-omap-usb2.c .mask = OMAP_DEV_PHY_PD, mask 222 drivers/phy/ti/phy-omap-usb2.c .mask = OMAP_DEV_PHY_PD, mask 229 drivers/phy/ti/phy-omap-usb2.c .mask = OMAP_USB2_PHY_PD, mask 236 drivers/phy/ti/phy-omap-usb2.c .mask = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD | mask 245 drivers/phy/ti/phy-omap-usb2.c .mask = AM654_USB2_OTG_PD | AM654_USB2_VBUS_DET_EN | mask 314 drivers/phy/ti/phy-omap-usb2.c phy->mask = phy_data->mask; mask 339 drivers/phy/ti/phy-ti-pipe3.c u32 mask; mask 356 drivers/phy/ti/phy-ti-pipe3.c mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; mask 359 drivers/phy/ti/phy-ti-pipe3.c mask, val); mask 364 drivers/phy/ti/phy-ti-pipe3.c mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; mask 373 drivers/phy/ti/phy-ti-pipe3.c mask, val); mask 378 drivers/phy/ti/phy-ti-pipe3.c mask, val); mask 54 drivers/pinctrl/actions/pinctrl-owl.c static void owl_update_bits(void __iomem *base, u32 mask, u32 val) mask 60 drivers/pinctrl/actions/pinctrl-owl.c reg_val = (reg_val & ~mask) | (val & mask); mask 68 drivers/pinctrl/actions/pinctrl-owl.c u32 tmp, mask; mask 71 drivers/pinctrl/actions/pinctrl-owl.c mask = (1 << width) - 1; mask 73 drivers/pinctrl/actions/pinctrl-owl.c return (tmp >> bit) & mask; mask 79 drivers/pinctrl/actions/pinctrl-owl.c u32 mask; mask 81 drivers/pinctrl/actions/pinctrl-owl.c mask = (1 << width) - 1; mask 82 drivers/pinctrl/actions/pinctrl-owl.c mask = mask << bit; mask 84 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + reg, mask, (arg << bit)); mask 163 drivers/pinctrl/actions/pinctrl-owl.c u32 *mask, mask 182 drivers/pinctrl/actions/pinctrl-owl.c *mask = (option_mask << g->mfpctl_shift); mask 195 drivers/pinctrl/actions/pinctrl-owl.c u32 val, mask; mask 199 drivers/pinctrl/actions/pinctrl-owl.c if (get_group_mfp_mask_val(g, function, &mask, &val)) mask 204 drivers/pinctrl/actions/pinctrl-owl.c owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val); mask 2554 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c u32 val = (pattern << __ffs(desc->mask)); mask 2574 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c !(desc->mask & (BIT(21) | BIT(22)))) mask 2581 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c desc->mask, val); mask 2722 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c u32 val = (pattern << __ffs(desc->mask)); mask 2748 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c !(desc->mask & (BIT(21) | BIT(22)))) mask 2756 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c u32 value = ~val & desc->mask; mask 2767 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c desc->mask, val); mask 2256 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c u32 val = (pattern << __ffs(desc->mask)); mask 2276 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c u32 clear = ~val & desc->mask; mask 2281 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c w1c, desc->mask, mask 2286 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c desc->mask, val); mask 19 drivers/pinctrl/aspeed/pinmux-aspeed.c desc->mask, enable ? desc->enable : desc->disable, mask 20 drivers/pinctrl/aspeed/pinmux-aspeed.c (rv & desc->mask) >> __ffs(desc->mask), rv); mask 57 drivers/pinctrl/aspeed/pinmux-aspeed.c return ((raw & desc->mask) >> __ffs(desc->mask)) == want; mask 445 drivers/pinctrl/aspeed/pinmux-aspeed.h u32 mask; mask 1105 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *mask) mask 1119 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1130 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, mask 1133 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, mask 1139 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 1, mask 1142 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, mask 1148 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, mask 1151 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 1, mask 1158 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1166 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1181 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, (arg/2)-1, mask 1221 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *mask) mask 1247 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, j+1, mask 1253 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, 0, mask 1260 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1268 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1291 drivers/pinctrl/bcm/pinctrl-bcm281xx.c u32 *mask) mask 1305 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 1313 drivers/pinctrl/bcm/pinctrl-bcm281xx.c bcm281xx_pin_update(val, mask, arg, mask 359 drivers/pinctrl/bcm/pinctrl-bcm2835.c unsigned int bank, u32 mask) mask 366 drivers/pinctrl/bcm/pinctrl-bcm2835.c events &= mask; mask 782 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c u32 val, mask = 0x7; mask 821 drivers/pinctrl/bcm/pinctrl-cygnus-mux.c val &= ~(mask << grp->mux.shift); mask 60 drivers/pinctrl/bcm/pinctrl-ns2-mux.c unsigned int mask; mask 381 drivers/pinctrl/bcm/pinctrl-ns2-mux.c .mask = ma, \ mask 578 drivers/pinctrl/bcm/pinctrl-ns2-mux.c u32 val, mask; mask 609 drivers/pinctrl/bcm/pinctrl-ns2-mux.c mask = mux->mask; mask 628 drivers/pinctrl/bcm/pinctrl-ns2-mux.c val &= ~(mask << grp->mux.shift); mask 55 drivers/pinctrl/bcm/pinctrl-nsp-mux.c unsigned int mask; mask 235 drivers/pinctrl/bcm/pinctrl-nsp-mux.c .mask = ma, \ mask 395 drivers/pinctrl/bcm/pinctrl-nsp-mux.c u32 val, mask; mask 425 drivers/pinctrl/bcm/pinctrl-nsp-mux.c mask = mux->mask; mask 448 drivers/pinctrl/bcm/pinctrl-nsp-mux.c val &= ~(mask << grp->mux.shift); mask 160 drivers/pinctrl/berlin/berlin.c u32 mask, val; mask 165 drivers/pinctrl/berlin/berlin.c mask = GENMASK(group_desc->lsb + group_desc->bit_width - 1, mask 168 drivers/pinctrl/berlin/berlin.c regmap_update_bits(pctrl->regmap, group_desc->offset, mask, val); mask 824 drivers/pinctrl/cirrus/pinctrl-madera-core.c u16 mask[2] = {0, 0}; mask 834 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK; mask 838 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK; mask 842 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK; mask 847 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK; mask 852 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_OP_CFG_MASK; mask 856 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_OP_CFG_MASK; mask 861 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_DRV_STR_MASK; mask 866 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_DB_MASK; mask 880 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_DIR_MASK; mask 888 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_IP_CFG; mask 894 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_DIR_MASK; mask 898 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_IP_CFG; mask 900 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_DIR_MASK; mask 905 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[0] |= MADERA_GP1_LVL_MASK; mask 911 drivers/pinctrl/cirrus/pinctrl-madera-core.c mask[1] |= MADERA_GP1_DIR_MASK; mask 926 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(priv->madera->regmap, reg, mask[0], conf[0]); mask 931 drivers/pinctrl/cirrus/pinctrl-madera-core.c ret = regmap_update_bits(priv->madera->regmap, reg, mask[1], conf[1]); mask 212 drivers/pinctrl/freescale/pinctrl-imx.c u32 mask = ((1 << width) - 1) << shift; mask 218 drivers/pinctrl/freescale/pinctrl-imx.c val &= ~mask; mask 315 drivers/pinctrl/freescale/pinctrl-imx.c & decode->mask; mask 73 drivers/pinctrl/freescale/pinctrl-imx.h u32 mask; mask 119 drivers/pinctrl/freescale/pinctrl-imx.h { .param = p, .mask = m, .shift = o, .invert = false, } mask 122 drivers/pinctrl/freescale/pinctrl-imx.h { .param = p, .mask = m, .shift = o, .invert = true, } mask 90 drivers/pinctrl/freescale/pinctrl-imx1-core.c int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */ mask 103 drivers/pinctrl/freescale/pinctrl-imx1-core.c old_val &= mask; mask 117 drivers/pinctrl/freescale/pinctrl-imx1-core.c int mask = ~BIT_MASK(offset); mask 123 drivers/pinctrl/freescale/pinctrl-imx1-core.c old_val &= mask; mask 190 drivers/pinctrl/freescale/pinctrl-mxs.c static void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift, void __iomem *reg) mask 195 drivers/pinctrl/freescale/pinctrl-mxs.c tmp &= ~(mask << shift); mask 1333 drivers/pinctrl/intel/pinctrl-cherryview.c static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) mask 1348 drivers/pinctrl/intel/pinctrl-cherryview.c if (mask) mask 996 drivers/pinctrl/intel/pinctrl-intel.c static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) mask 1023 drivers/pinctrl/intel/pinctrl-intel.c if (mask) mask 1599 drivers/pinctrl/intel/pinctrl-intel.c intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value) mask 1604 drivers/pinctrl/intel/pinctrl-intel.c updated = (curr & ~mask) | (value & mask); mask 493 drivers/pinctrl/intel/pinctrl-merrifield.c u32 bits, u32 mask) mask 501 drivers/pinctrl/intel/pinctrl-merrifield.c value &= ~mask; mask 502 drivers/pinctrl/intel/pinctrl-merrifield.c value |= bits & mask; mask 595 drivers/pinctrl/intel/pinctrl-merrifield.c u32 mask = BUFCFG_PINMODE_MASK; mask 611 drivers/pinctrl/intel/pinctrl-merrifield.c mrfld_update_bufcfg(mp, grp->pins[i], bits, mask); mask 623 drivers/pinctrl/intel/pinctrl-merrifield.c u32 mask = BUFCFG_PINMODE_MASK; mask 630 drivers/pinctrl/intel/pinctrl-merrifield.c mrfld_update_bufcfg(mp, pin, bits, mask); mask 732 drivers/pinctrl/intel/pinctrl-merrifield.c u32 bits = 0, mask = 0; mask 737 drivers/pinctrl/intel/pinctrl-merrifield.c mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; mask 741 drivers/pinctrl/intel/pinctrl-merrifield.c mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; mask 761 drivers/pinctrl/intel/pinctrl-merrifield.c mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; mask 781 drivers/pinctrl/intel/pinctrl-merrifield.c mask |= BUFCFG_OD_EN; mask 787 drivers/pinctrl/intel/pinctrl-merrifield.c mask |= BUFCFG_SLEWSEL; mask 794 drivers/pinctrl/intel/pinctrl-merrifield.c mrfld_update_bufcfg(mp, pin, bits, mask); mask 32 drivers/pinctrl/mediatek/mtk-eint.c .mask = 0x080, mask 88 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(hwirq & 0x1f); mask 100 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg + reg_offset); mask 112 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); mask 116 drivers/pinctrl/mediatek/mtk-eint.c eint->cur_mask[d->hwirq >> 5] &= ~mask; mask 118 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 124 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); mask 128 drivers/pinctrl/mediatek/mtk-eint.c eint->cur_mask[d->hwirq >> 5] |= mask; mask 130 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 141 drivers/pinctrl/mediatek/mtk-eint.c eint->regs->mask); mask 149 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); mask 153 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 159 drivers/pinctrl/mediatek/mtk-eint.c u32 mask = BIT(d->hwirq & 0x1f); mask 177 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 180 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 185 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 188 drivers/pinctrl/mediatek/mtk-eint.c writel(mask, reg); mask 17 drivers/pinctrl/mediatek/mtk-eint.h unsigned int mask; mask 477 drivers/pinctrl/mediatek/pinctrl-mt2701.c unsigned int i, value, mask; mask 490 drivers/pinctrl/mediatek/pinctrl-mt2701.c mask = BIT(mt2701_spec_pinmux[i].bit); mask 492 drivers/pinctrl/mediatek/pinctrl-mt2701.c value = mask; mask 495 drivers/pinctrl/mediatek/pinctrl-mt2701.c regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value); mask 55 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set) mask 60 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c val &= ~mask; mask 117 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c pfd->mask = (1 << c->x_bits) - 1; mask 143 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c *h = get_count_order(pf->mask) - *l; mask 153 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c mtk_rmw(hw, pf->index, pf->offset, pf->mask << pf->bitpos, mask 154 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c (value & pf->mask) << pf->bitpos); mask 157 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c (value & pf->mask) >> nbits_l); mask 186 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, mask 187 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c (value & pf.mask) << pf.bitpos); mask 206 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c >> pf.bitpos) & pf.mask; mask 99 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h u32 mask; mask 251 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); mask 199 drivers/pinctrl/mediatek/pinctrl-mtk-common.c unsigned int bits, mask, shift; mask 214 drivers/pinctrl/mediatek/pinctrl-mtk-common.c mask = BIT(bits) - 1; mask 216 drivers/pinctrl/mediatek/pinctrl-mtk-common.c mask <<= shift; mask 219 drivers/pinctrl/mediatek/pinctrl-mtk-common.c pin_drv->offset, mask, val); mask 679 drivers/pinctrl/mediatek/pinctrl-mtk-common.c unsigned int mask = (1L << GPIO_MODE_BITS) - 1; mask 689 drivers/pinctrl/mediatek/pinctrl-mtk-common.c mode &= mask; mask 691 drivers/pinctrl/mediatek/pinctrl-mtk-common.c mask <<= (GPIO_MODE_BITS * bit); mask 694 drivers/pinctrl/mediatek/pinctrl-mtk-common.c reg_addr, mask, val); mask 169 drivers/pinctrl/mediatek/pinctrl-mtk-common.h unsigned int mask; mask 345 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask = grp->reg_mask; mask 357 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); mask 387 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask; mask 390 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); mask 392 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return regmap_update_bits(info->regmap, reg, mask, 0); mask 400 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int val, mask; mask 403 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); mask 406 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return !(val & mask); mask 414 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask, val, ret; mask 417 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); mask 419 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c ret = regmap_update_bits(info->regmap, reg, mask, mask); mask 425 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = value ? mask : 0; mask 426 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); mask 435 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int val, mask; mask 438 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); mask 442 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c return (val & mask) != 0; mask 450 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c unsigned int mask, val; mask 453 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = BIT(offset); mask 454 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c val = value ? mask : 0; mask 456 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c regmap_update_bits(info->regmap, reg, mask, val); mask 522 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(d->mask, info->base + reg); mask 536 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val & ~d->mask, info->base + reg); mask 550 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c writel(val | d->mask, info->base + reg); mask 712 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c d->mask = BIT(d->hwirq % GPIO_PER_REG); mask 1063 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c u32 mask, *irq_pol, input_reg, virq, type, level; mask 1066 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = info->pm.irq_en_l; mask 1070 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c mask = info->pm.irq_en_h; mask 1075 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c if (!(mask & irq_bit)) mask 107 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long mask; mask 111 drivers/pinctrl/mvebu/pinctrl-dove.c mask = CAM_GPIO_SEL; mask 114 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SD0_GPIO_SEL; mask 117 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SD1_GPIO_SEL; mask 120 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SPI_GPIO_SEL; mask 123 drivers/pinctrl/mvebu/pinctrl-dove.c mask = UART1_GPIO_SEL; mask 129 drivers/pinctrl/mvebu/pinctrl-dove.c *config = ((mpp4 & mask) != 0); mask 138 drivers/pinctrl/mvebu/pinctrl-dove.c unsigned long mask; mask 142 drivers/pinctrl/mvebu/pinctrl-dove.c mask = CAM_GPIO_SEL; mask 145 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SD0_GPIO_SEL; mask 148 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SD1_GPIO_SEL; mask 151 drivers/pinctrl/mvebu/pinctrl-dove.c mask = SPI_GPIO_SEL; mask 154 drivers/pinctrl/mvebu/pinctrl-dove.c mask = UART1_GPIO_SEL; mask 160 drivers/pinctrl/mvebu/pinctrl-dove.c mpp4 &= ~mask; mask 162 drivers/pinctrl/mvebu/pinctrl-dove.c mpp4 |= mask; mask 437 drivers/pinctrl/nomadik/pinctrl-nomadik.c static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) mask 442 drivers/pinctrl/nomadik/pinctrl-nomadik.c val = ((val & ~mask) | (value & mask)); mask 416 drivers/pinctrl/pinctrl-amd.c u32 pin_reg, pin_reg_irq_en, mask; mask 500 drivers/pinctrl/pinctrl-amd.c mask = BIT(INTERRUPT_ENABLE_OFF); mask 502 drivers/pinctrl/pinctrl-amd.c pin_reg_irq_en |= mask; mask 505 drivers/pinctrl/pinctrl-amd.c while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) mask 545 drivers/pinctrl/pinctrl-amd.c u64 status, mask; mask 557 drivers/pinctrl/pinctrl-amd.c for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { mask 558 drivers/pinctrl/pinctrl-amd.c if (!(status & mask)) mask 560 drivers/pinctrl/pinctrl-amd.c status &= ~mask; mask 713 drivers/pinctrl/pinctrl-at91-pio4.c u32 mask, conf = 0; mask 770 drivers/pinctrl/pinctrl-at91-pio4.c mask = 1 << pin; mask 773 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(mask, atmel_pioctrl->reg_base + mask 777 drivers/pinctrl/pinctrl-at91-pio4.c writel_relaxed(mask, atmel_pioctrl->reg_base + mask 167 drivers/pinctrl/pinctrl-at91.c enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); mask 168 drivers/pinctrl/pinctrl-at91.c void (*mux_A_periph)(void __iomem *pio, unsigned mask); mask 169 drivers/pinctrl/pinctrl-at91.c void (*mux_B_periph)(void __iomem *pio, unsigned mask); mask 170 drivers/pinctrl/pinctrl-at91.c void (*mux_C_periph)(void __iomem *pio, unsigned mask); mask 171 drivers/pinctrl/pinctrl-at91.c void (*mux_D_periph)(void __iomem *pio, unsigned mask); mask 173 drivers/pinctrl/pinctrl-at91.c void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); mask 175 drivers/pinctrl/pinctrl-at91.c void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); mask 177 drivers/pinctrl/pinctrl-at91.c void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); mask 179 drivers/pinctrl/pinctrl-at91.c void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); mask 380 drivers/pinctrl/pinctrl-at91.c static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) mask 382 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IDR); mask 390 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) mask 393 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_PPDDR); mask 395 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); mask 404 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_output(void __iomem *pio, unsigned int mask, mask 407 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); mask 408 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); mask 416 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) mask 418 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); mask 421 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) mask 423 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_ASR); mask 426 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) mask 428 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_BSR); mask 431 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) mask 434 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, mask 436 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, mask 440 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) mask 442 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, mask 444 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, mask 448 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) mask 450 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); mask 451 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); mask 454 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) mask 456 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); mask 457 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); mask 460 drivers/pinctrl/pinctrl-at91.c static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) mask 464 drivers/pinctrl/pinctrl-at91.c if (readl_relaxed(pio + PIO_PSR) & mask) mask 467 drivers/pinctrl/pinctrl-at91.c select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); mask 468 drivers/pinctrl/pinctrl-at91.c select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); mask 473 drivers/pinctrl/pinctrl-at91.c static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) mask 477 drivers/pinctrl/pinctrl-at91.c if (readl_relaxed(pio + PIO_PSR) & mask) mask 480 drivers/pinctrl/pinctrl-at91.c select = readl_relaxed(pio + PIO_ABSR) & mask; mask 490 drivers/pinctrl/pinctrl-at91.c static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) mask 492 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); mask 503 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) mask 506 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IFSCDR); mask 507 drivers/pinctrl/pinctrl-at91.c at91_mux_set_deglitch(pio, mask, is_on); mask 518 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, mask 522 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IFSCER); mask 524 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IFER); mask 526 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IFSCDR); mask 534 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) mask 537 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_PUDR); mask 539 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); mask 542 drivers/pinctrl/pinctrl-at91.c static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) mask 544 drivers/pinctrl/pinctrl-at91.c writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); mask 809 drivers/pinctrl/pinctrl-at91.c static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) mask 811 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_PDR); mask 814 drivers/pinctrl/pinctrl-at91.c static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) mask 816 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_PER); mask 817 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); mask 828 drivers/pinctrl/pinctrl-at91.c unsigned mask; mask 851 drivers/pinctrl/pinctrl-at91.c mask = pin_to_mask(pin->pin); mask 852 drivers/pinctrl/pinctrl-at91.c at91_mux_disable_interrupt(pio, mask); mask 855 drivers/pinctrl/pinctrl-at91.c at91_mux_gpio_enable(pio, mask, 1); mask 858 drivers/pinctrl/pinctrl-at91.c info->ops->mux_A_periph(pio, mask); mask 861 drivers/pinctrl/pinctrl-at91.c info->ops->mux_B_periph(pio, mask); mask 866 drivers/pinctrl/pinctrl-at91.c info->ops->mux_C_periph(pio, mask); mask 871 drivers/pinctrl/pinctrl-at91.c info->ops->mux_D_periph(pio, mask); mask 875 drivers/pinctrl/pinctrl-at91.c at91_mux_gpio_disable(pio, mask); mask 915 drivers/pinctrl/pinctrl-at91.c unsigned mask; mask 930 drivers/pinctrl/pinctrl-at91.c mask = 1 << (offset - chip->base); mask 933 drivers/pinctrl/pinctrl-at91.c offset, 'A' + range->id, offset - chip->base, mask); mask 935 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, at91_chip->regbase + PIO_PER); mask 1007 drivers/pinctrl/pinctrl-at91.c unsigned mask; mask 1025 drivers/pinctrl/pinctrl-at91.c mask = pin_to_mask(pin); mask 1030 drivers/pinctrl/pinctrl-at91.c at91_mux_set_output(pio, mask, config & OUTPUT, mask 1032 drivers/pinctrl/pinctrl-at91.c at91_mux_set_pullup(pio, mask, config & PULL_UP); mask 1033 drivers/pinctrl/pinctrl-at91.c at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); mask 1035 drivers/pinctrl/pinctrl-at91.c info->ops->set_deglitch(pio, mask, config & DEGLITCH); mask 1037 drivers/pinctrl/pinctrl-at91.c info->ops->set_debounce(pio, mask, config & DEBOUNCE, mask 1040 drivers/pinctrl/pinctrl-at91.c info->ops->set_pulldown(pio, mask, config & PULL_DOWN); mask 1042 drivers/pinctrl/pinctrl-at91.c info->ops->disable_schmitt_trig(pio, mask); mask 1065 drivers/pinctrl/pinctrl-at91.c #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \ mask 1066 drivers/pinctrl/pinctrl-at91.c if ((config & mask) == flag) { \ mask 1413 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << offset; mask 1417 drivers/pinctrl/pinctrl-at91.c return !(osr & mask); mask 1424 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << offset; mask 1426 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_ODR); mask 1434 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << offset; mask 1438 drivers/pinctrl/pinctrl-at91.c return (pdsr & mask) != 0; mask 1446 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << offset; mask 1448 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); mask 1452 drivers/pinctrl/pinctrl-at91.c unsigned long *mask, unsigned long *bits) mask 1459 drivers/pinctrl/pinctrl-at91.c uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); mask 1460 drivers/pinctrl/pinctrl-at91.c uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); mask 1471 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << offset; mask 1473 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); mask 1474 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_OER); mask 1488 drivers/pinctrl/pinctrl-at91.c unsigned mask = pin_to_mask(i); mask 1494 drivers/pinctrl/pinctrl-at91.c mode = at91_gpio->ops->get_periph(pio, mask); mask 1500 drivers/pinctrl/pinctrl-at91.c readl_relaxed(pio + PIO_OSR) & mask ? mask 1503 drivers/pinctrl/pinctrl-at91.c readl_relaxed(pio + PIO_PDSR) & mask ? mask 1533 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << d->hwirq; mask 1536 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IDR); mask 1543 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << d->hwirq; mask 1546 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_IER); mask 1565 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << d->hwirq; mask 1570 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_ESR); mask 1571 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_REHLSR); mask 1575 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_ESR); mask 1576 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_FELLSR); mask 1580 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_LSR); mask 1581 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_FELLSR); mask 1585 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_LSR); mask 1586 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_REHLSR); mask 1594 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_AIMDR); mask 1603 drivers/pinctrl/pinctrl-at91.c writel_relaxed(mask, pio + PIO_AIMER); mask 1622 drivers/pinctrl/pinctrl-at91.c unsigned mask = 1 << d->hwirq; mask 1628 drivers/pinctrl/pinctrl-at91.c wakeups[bank] |= mask; mask 1630 drivers/pinctrl/pinctrl-at91.c wakeups[bank] &= ~mask; mask 231 drivers/pinctrl/pinctrl-axp209.c unsigned int mask; mask 239 drivers/pinctrl/pinctrl-axp209.c mask = pctl->desc->ldo_mask; mask 241 drivers/pinctrl/pinctrl-axp209.c mask = pctl->desc->adc_mask; mask 243 drivers/pinctrl/pinctrl-axp209.c if (!(BIT(group) & mask)) mask 315 drivers/pinctrl/pinctrl-axp209.c static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask, mask 320 drivers/pinctrl/pinctrl-axp209.c unsigned long int mask_cpy = mask; mask 322 drivers/pinctrl/pinctrl-axp209.c unsigned int ngroups = hweight8(mask); mask 35 drivers/pinctrl/pinctrl-gemini.c u32 mask; mask 78 drivers/pinctrl/pinctrl-gemini.c u32 mask; mask 714 drivers/pinctrl/pinctrl-gemini.c .mask = DRAM_PADS_POWERDOWN, mask 788 drivers/pinctrl/pinctrl-gemini.c .mask = SSP_PADS_ENABLE, mask 796 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_PADS_ENABLE, mask 804 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE, mask 821 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, mask 828 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 849 drivers/pinctrl/pinctrl-gemini.c .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, mask 857 drivers/pinctrl/pinctrl-gemini.c .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, mask 865 drivers/pinctrl/pinctrl-gemini.c .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, mask 873 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_CLK_PAD_ENABLE, mask 880 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_PADS_ENABLE, mask 899 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, mask 906 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 942 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 965 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 973 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 980 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 988 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, mask 994 drivers/pinctrl/pinctrl-gemini.c .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, mask 1002 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, mask 1009 drivers/pinctrl/pinctrl-gemini.c .mask = PCI_PADS_ENABLE, mask 1658 drivers/pinctrl/pinctrl-gemini.c .mask = DRAM_PADS_POWERDOWN, mask 1714 drivers/pinctrl/pinctrl-gemini.c .mask = GEMINI_GMAC_IOSEL_MASK, mask 1722 drivers/pinctrl/pinctrl-gemini.c .mask = GEMINI_GMAC_IOSEL_MASK, mask 1739 drivers/pinctrl/pinctrl-gemini.c .mask = SSP_PADS_ENABLE, mask 1746 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_PADS_ENABLE, mask 1754 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE, mask 1771 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, mask 1778 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 1799 drivers/pinctrl/pinctrl-gemini.c .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, mask 1807 drivers/pinctrl/pinctrl-gemini.c .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, mask 1815 drivers/pinctrl/pinctrl-gemini.c .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, mask 1823 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_PADS_ENABLE, mask 1836 drivers/pinctrl/pinctrl-gemini.c .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, mask 1849 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 1885 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE, mask 1901 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_CLK_PAD_ENABLE, mask 1908 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 1916 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 1923 drivers/pinctrl/pinctrl-gemini.c .mask = IDE_PADS_ENABLE, mask 1931 drivers/pinctrl/pinctrl-gemini.c .mask = TVC_PADS_ENABLE, mask 1937 drivers/pinctrl/pinctrl-gemini.c .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, mask 1945 drivers/pinctrl/pinctrl-gemini.c .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, mask 1952 drivers/pinctrl/pinctrl-gemini.c .mask = PCI_PADS_ENABLE, mask 2216 drivers/pinctrl/pinctrl-gemini.c grp->mask | grp->value, mask 2223 drivers/pinctrl/pinctrl-gemini.c expected = before &= ~grp->mask; mask 2228 drivers/pinctrl/pinctrl-gemini.c tmp = grp->mask; mask 2306 drivers/pinctrl/pinctrl-gemini.c .mask = GENMASK(_hb, _lb) \ mask 2391 drivers/pinctrl/pinctrl-gemini.c val &= conf->mask; mask 2392 drivers/pinctrl/pinctrl-gemini.c val >>= (ffs(conf->mask) - 1); mask 2426 drivers/pinctrl/pinctrl-gemini.c arg <<= (ffs(conf->mask) - 1); mask 2429 drivers/pinctrl/pinctrl-gemini.c pin, conf->mask, arg); mask 2430 drivers/pinctrl/pinctrl-gemini.c regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); mask 342 drivers/pinctrl/pinctrl-max77620.c int mask, shift; mask 351 drivers/pinctrl/pinctrl-max77620.c mask = MAX77620_FPS_SRC_MASK; mask 360 drivers/pinctrl/pinctrl-max77620.c mask = MAX77620_FPS_PU_PERIOD_MASK; mask 369 drivers/pinctrl/pinctrl-max77620.c mask = MAX77620_FPS_PD_PERIOD_MASK; mask 385 drivers/pinctrl/pinctrl-max77620.c ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift); mask 181 drivers/pinctrl/pinctrl-mcp23s08.c unsigned int mask, bool enabled) mask 185 drivers/pinctrl/pinctrl-mcp23s08.c mask, val); mask 191 drivers/pinctrl/pinctrl-mcp23s08.c u16 mask = BIT(pin); mask 192 drivers/pinctrl/pinctrl-mcp23s08.c return mcp_set_mask(mcp, reg, mask, enabled); mask 418 drivers/pinctrl/pinctrl-mcp23s08.c static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) mask 420 drivers/pinctrl/pinctrl-mcp23s08.c return mcp_set_mask(mcp, MCP_OLAT, mask, value); mask 426 drivers/pinctrl/pinctrl-mcp23s08.c unsigned mask = BIT(offset); mask 429 drivers/pinctrl/pinctrl-mcp23s08.c __mcp23s08_set(mcp, mask, !!value); mask 437 drivers/pinctrl/pinctrl-mcp23s08.c unsigned mask = BIT(offset); mask 441 drivers/pinctrl/pinctrl-mcp23s08.c status = __mcp23s08_set(mcp, mask, value); mask 443 drivers/pinctrl/pinctrl-mcp23s08.c status = mcp_set_mask(mcp, MCP_IODIR, mask, false); mask 595 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pg->pin); mask 602 drivers/pinctrl/pinctrl-oxnas.c functions->fct, mask); mask 608 drivers/pinctrl/pinctrl-oxnas.c mask, mask 610 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 615 drivers/pinctrl/pinctrl-oxnas.c mask, mask 617 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 622 drivers/pinctrl/pinctrl-oxnas.c mask, mask 624 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 646 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pg->pin); mask 653 drivers/pinctrl/pinctrl-oxnas.c functions->fct, mask); mask 657 drivers/pinctrl/pinctrl-oxnas.c mask, mask 659 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 662 drivers/pinctrl/pinctrl-oxnas.c mask, mask 664 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 667 drivers/pinctrl/pinctrl-oxnas.c mask, mask 669 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 672 drivers/pinctrl/pinctrl-oxnas.c mask, mask 674 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 677 drivers/pinctrl/pinctrl-oxnas.c mask, mask 679 drivers/pinctrl/pinctrl-oxnas.c mask : 0)); mask 698 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); mask 701 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); mask 707 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 712 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 717 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 729 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset - bank->gpio_chip.base); mask 732 drivers/pinctrl/pinctrl-oxnas.c offset, bank->gpio_chip.base, bank->id, mask); mask 736 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 739 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 742 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 745 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 748 drivers/pinctrl/pinctrl-oxnas.c mask, 0); mask 757 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 759 drivers/pinctrl/pinctrl-oxnas.c return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask); mask 766 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 768 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR); mask 776 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 778 drivers/pinctrl/pinctrl-oxnas.c return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0; mask 785 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 788 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_SET); mask 790 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR); mask 797 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 800 drivers/pinctrl/pinctrl-oxnas.c writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET); mask 843 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); mask 857 drivers/pinctrl/pinctrl-oxnas.c arg = !!(arg & mask); mask 875 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(pin - bank->gpio_chip.base); mask 887 drivers/pinctrl/pinctrl-oxnas.c arg = !!(arg & mask); mask 907 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 910 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); mask 922 drivers/pinctrl/pinctrl-oxnas.c mask, mask); mask 944 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(offset); mask 947 drivers/pinctrl/pinctrl-oxnas.c pin, bank->gpio_chip.base, mask); mask 957 drivers/pinctrl/pinctrl-oxnas.c mask, mask); mask 985 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); mask 987 drivers/pinctrl/pinctrl-oxnas.c writel(mask, bank->reg_base + IRQ_PENDING); mask 995 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); mask 998 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask, mask 1002 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask, mask 1011 drivers/pinctrl/pinctrl-oxnas.c u32 mask = BIT(data->hwirq); mask 1014 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask, mask 1018 drivers/pinctrl/pinctrl-oxnas.c writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask, mask 867 drivers/pinctrl/pinctrl-palmas.c int base, add, mask; mask 907 drivers/pinctrl/pinctrl-palmas.c mask = opt->pud_info->pullup_dn_mask; mask 933 drivers/pinctrl/pinctrl-palmas.c mask = opt->od_info->od_mask; mask 951 drivers/pinctrl/pinctrl-palmas.c __func__, base, add, mask, rval); mask 952 drivers/pinctrl/pinctrl-palmas.c ret = palmas_update_bits(pci->palmas, base, add, mask, rval); mask 1803 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset - bank->gpio_chip.base); mask 1806 drivers/pinctrl/pinctrl-pic32.c offset, bank->gpio_chip.base, mask); mask 1808 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); mask 1817 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); mask 1819 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(TRIS_REG)); mask 1835 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); mask 1838 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); mask 1840 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); mask 1847 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); mask 1850 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(TRIS_REG)); mask 1884 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin - bank->gpio_chip.base); mask 1889 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPU_REG) & mask); mask 1892 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + CNPD_REG) & mask); mask 1895 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + ANSEL_REG) & mask); mask 1898 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ANSEL_REG) & mask); mask 1901 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + ODCU_REG) & mask); mask 1904 drivers/pinctrl/pinctrl-pic32.c arg = !!(readl(bank->reg_base + TRIS_REG) & mask); mask 1907 drivers/pinctrl/pinctrl-pic32.c arg = !(readl(bank->reg_base + TRIS_REG) & mask); mask 1928 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(offset); mask 1931 drivers/pinctrl/pinctrl-pic32.c pin, bank->gpio_chip.base, mask); mask 1940 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base +PIC32_SET(CNPU_REG)); mask 1944 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNPD_REG)); mask 1948 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(ANSEL_REG)); mask 1952 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ANSEL_REG)); mask 1956 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(ODCU_REG)); mask 2030 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(data->hwirq); mask 2035 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); mask 2037 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNNE_REG)); mask 2043 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_CLR(CNEN_REG)); mask 2045 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); mask 2051 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNEN_REG)); mask 2053 drivers/pinctrl/pinctrl-pic32.c writel(mask, bank->reg_base + PIC32_SET(CNNE_REG)); mask 2077 drivers/pinctrl/pinctrl-pic32.c u32 mask = BIT(pin); mask 2079 drivers/pinctrl/pinctrl-pic32.c if ((mask & cnen_rise) || (mask && cnne_fall)) mask 2080 drivers/pinctrl/pinctrl-pic32.c pending |= mask; mask 299 drivers/pinctrl/pinctrl-rockchip.c u8 mask; mask 567 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 573 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 579 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 585 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 591 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 597 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 603 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 609 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 615 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 621 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 631 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 637 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 643 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 649 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 655 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 665 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 671 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x7 mask 677 drivers/pinctrl/pinctrl-rockchip.c .mask = 0x3 mask 682 drivers/pinctrl/pinctrl-rockchip.c int *reg, u8 *bit, int *mask) mask 700 drivers/pinctrl/pinctrl-rockchip.c *mask = data->mask; mask 1143 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, mask, mux_type; mask 1167 drivers/pinctrl/pinctrl-rockchip.c mask = 0xf; mask 1172 drivers/pinctrl/pinctrl-rockchip.c mask = 0x7; mask 1175 drivers/pinctrl/pinctrl-rockchip.c mask = 0x3; mask 1179 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); mask 1185 drivers/pinctrl/pinctrl-rockchip.c return ((val >> bit) & mask); mask 1231 drivers/pinctrl/pinctrl-rockchip.c int reg, ret, mask, mux_type; mask 1255 drivers/pinctrl/pinctrl-rockchip.c mask = 0xf; mask 1260 drivers/pinctrl/pinctrl-rockchip.c mask = 0x7; mask 1263 drivers/pinctrl/pinctrl-rockchip.c mask = 0x3; mask 1267 drivers/pinctrl/pinctrl-rockchip.c rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); mask 1290 drivers/pinctrl/pinctrl-rockchip.c data = (mask << (bit + 16)); mask 1292 drivers/pinctrl/pinctrl-rockchip.c data |= (mux & mask) << bit; mask 2900 drivers/pinctrl/pinctrl-rockchip.c u32 mask = BIT(d->hwirq); mask 2916 drivers/pinctrl/pinctrl-rockchip.c data &= ~mask; mask 2934 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode |= mask; mask 2935 drivers/pinctrl/pinctrl-rockchip.c level |= mask; mask 2942 drivers/pinctrl/pinctrl-rockchip.c if (data & mask) mask 2943 drivers/pinctrl/pinctrl-rockchip.c polarity &= ~mask; mask 2945 drivers/pinctrl/pinctrl-rockchip.c polarity |= mask; mask 2948 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; mask 2949 drivers/pinctrl/pinctrl-rockchip.c level |= mask; mask 2950 drivers/pinctrl/pinctrl-rockchip.c polarity |= mask; mask 2953 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; mask 2954 drivers/pinctrl/pinctrl-rockchip.c level |= mask; mask 2955 drivers/pinctrl/pinctrl-rockchip.c polarity &= ~mask; mask 2958 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; mask 2959 drivers/pinctrl/pinctrl-rockchip.c level &= ~mask; mask 2960 drivers/pinctrl/pinctrl-rockchip.c polarity |= mask; mask 2963 drivers/pinctrl/pinctrl-rockchip.c bank->toggle_edge_mode &= ~mask; mask 2964 drivers/pinctrl/pinctrl-rockchip.c level &= ~mask; mask 2965 drivers/pinctrl/pinctrl-rockchip.c polarity &= ~mask; mask 3078 drivers/pinctrl/pinctrl-rockchip.c gc->chip_types[0].regs.mask = GPIO_INTMASK; mask 49 drivers/pinctrl/pinctrl-single.c unsigned mask; mask 66 drivers/pinctrl/pinctrl-single.c unsigned mask; mask 358 drivers/pinctrl/pinctrl-single.c unsigned val, mask; mask 365 drivers/pinctrl/pinctrl-single.c mask = vals->mask; mask 367 drivers/pinctrl/pinctrl-single.c mask = pcs->fmask; mask 369 drivers/pinctrl/pinctrl-single.c val &= ~mask; mask 370 drivers/pinctrl/pinctrl-single.c val |= (vals->val & mask); mask 485 drivers/pinctrl/pinctrl-single.c data = pcs->read(pcs->base + offset) & func->conf[i].mask; mask 551 drivers/pinctrl/pinctrl-single.c shift = ffs(func->conf[i].mask) - 1; mask 552 drivers/pinctrl/pinctrl-single.c data &= ~func->conf[i].mask; mask 553 drivers/pinctrl/pinctrl-single.c data |= (arg << shift) & func->conf[i].mask; mask 565 drivers/pinctrl/pinctrl-single.c data &= ~func->conf[i].mask; mask 833 drivers/pinctrl/pinctrl-single.c unsigned mask) mask 839 drivers/pinctrl/pinctrl-single.c (*conf)->mask = mask; mask 1119 drivers/pinctrl/pinctrl-single.c unsigned mask, bit_pos, val_pos, mask_pos, submask; mask 1136 drivers/pinctrl/pinctrl-single.c mask = pinctrl_spec.args[2]; mask 1139 drivers/pinctrl/pinctrl-single.c pinctrl_spec.np, offset, val, mask); mask 1142 drivers/pinctrl/pinctrl-single.c while (mask) { mask 1143 drivers/pinctrl/pinctrl-single.c bit_pos = __ffs(mask); mask 1147 drivers/pinctrl/pinctrl-single.c submask = mask & mask_pos; mask 1149 drivers/pinctrl/pinctrl-single.c if ((mask & mask_pos) == 0) { mask 1156 drivers/pinctrl/pinctrl-single.c mask &= ~mask_pos; mask 1165 drivers/pinctrl/pinctrl-single.c vals[found].mask = submask; mask 1370 drivers/pinctrl/pinctrl-single.c unsigned mask; mask 1383 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); mask 1385 drivers/pinctrl/pinctrl-single.c mask |= soc_mask; mask 1387 drivers/pinctrl/pinctrl-single.c mask &= ~soc_mask; mask 1388 drivers/pinctrl/pinctrl-single.c pcs->write(mask, pcswi->reg); mask 1391 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); mask 1456 drivers/pinctrl/pinctrl-single.c unsigned mask; mask 1460 drivers/pinctrl/pinctrl-single.c mask = pcs->read(pcswi->reg); mask 1462 drivers/pinctrl/pinctrl-single.c if (mask & pcs_soc->irq_status_mask) { mask 390 drivers/pinctrl/pinctrl-st.c unsigned long mask = BIT(pin); mask 394 drivers/pinctrl/pinctrl-st.c oe_value &= ~mask; mask 396 drivers/pinctrl/pinctrl-st.c oe_value |= mask; mask 402 drivers/pinctrl/pinctrl-st.c pu_value &= ~mask; mask 404 drivers/pinctrl/pinctrl-st.c pu_value |= mask; mask 410 drivers/pinctrl/pinctrl-st.c od_value &= ~mask; mask 412 drivers/pinctrl/pinctrl-st.c od_value |= mask; mask 107 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 113 drivers/pinctrl/pinctrl-stmfx.c return ret ? ret : !!(value & mask); mask 120 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 123 drivers/pinctrl/pinctrl-stmfx.c mask, mask); mask 130 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 140 drivers/pinctrl/pinctrl-stmfx.c return ret ? ret : !(val & mask); mask 147 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 149 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, 0); mask 157 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 161 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, mask); mask 168 drivers/pinctrl/pinctrl-stmfx.c u32 pupd, mask = get_mask(offset); mask 175 drivers/pinctrl/pinctrl-stmfx.c return !!(pupd & mask); mask 182 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 184 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0); mask 191 drivers/pinctrl/pinctrl-stmfx.c u32 type, mask = get_mask(offset); mask 198 drivers/pinctrl/pinctrl-stmfx.c return !!(type & mask); mask 205 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 207 drivers/pinctrl/pinctrl-stmfx.c return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0); mask 418 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(data->hwirq); mask 420 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_src[reg] &= ~mask; mask 428 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(data->hwirq); mask 430 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_src[reg] |= mask; mask 438 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(data->hwirq); mask 444 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_evt[reg] |= mask; mask 447 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_evt[reg] &= ~mask; mask 452 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; mask 454 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= ~mask; mask 464 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_toggle_edge[reg] |= mask; mask 466 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_toggle_edge[reg] &= mask; mask 484 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(data->hwirq); mask 491 drivers/pinctrl/pinctrl-stmfx.c if (pctl->irq_toggle_edge[reg] & mask) { mask 493 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= ~mask; mask 495 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; mask 512 drivers/pinctrl/pinctrl-stmfx.c u32 mask = get_mask(offset); mask 515 drivers/pinctrl/pinctrl-stmfx.c if (!(pctl->irq_toggle_edge[reg] & mask)) mask 523 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] &= mask; mask 526 drivers/pinctrl/pinctrl-stmfx.c mask, 0); mask 529 drivers/pinctrl/pinctrl-stmfx.c pctl->irq_gpi_type[reg] |= mask; mask 532 drivers/pinctrl/pinctrl-stmfx.c mask, mask); mask 447 drivers/pinctrl/pinctrl-sx150x.c unsigned long *mask, mask 452 drivers/pinctrl/pinctrl-sx150x.c regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits); mask 512 drivers/pinctrl/pinctrl-sx150x.c const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | mask 515 drivers/pinctrl/pinctrl-sx150x.c pctl->irq.sense &= mask; mask 712 drivers/pinctrl/pinctrl-u300.c u16 mask; mask 886 drivers/pinctrl/pinctrl-u300.c const struct u300_pmx_mask *mask; mask 907 drivers/pinctrl/pinctrl-u300.c .mask = emif0_mask, mask 913 drivers/pinctrl/pinctrl-u300.c .mask = emif1_mask, mask 919 drivers/pinctrl/pinctrl-u300.c .mask = uart0_mask, mask 925 drivers/pinctrl/pinctrl-u300.c .mask = mmc0_mask, mask 931 drivers/pinctrl/pinctrl-u300.c .mask = spi0_mask, mask 938 drivers/pinctrl/pinctrl-u300.c u16 regval, val, mask; mask 942 drivers/pinctrl/pinctrl-u300.c upmx_mask = u300_pmx_functions[selector].mask; mask 949 drivers/pinctrl/pinctrl-u300.c mask = upmx_mask->mask; mask 950 drivers/pinctrl/pinctrl-u300.c if (mask != 0) { mask 952 drivers/pinctrl/pinctrl-u300.c regval &= ~mask; mask 763 drivers/pinctrl/pinctrl-zynq.c #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\ mask 770 drivers/pinctrl/pinctrl-zynq.c .mux_mask = mask, \ mask 164 drivers/pinctrl/qcom/pinctrl-msm.c u32 val, mask; mask 168 drivers/pinctrl/qcom/pinctrl-msm.c mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); mask 181 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~mask; mask 217 drivers/pinctrl/qcom/pinctrl-msm.c unsigned *mask, mask 226 drivers/pinctrl/qcom/pinctrl-msm.c *mask = 3; mask 230 drivers/pinctrl/qcom/pinctrl-msm.c *mask = 7; mask 235 drivers/pinctrl/qcom/pinctrl-msm.c *mask = 1; mask 262 drivers/pinctrl/qcom/pinctrl-msm.c unsigned mask; mask 270 drivers/pinctrl/qcom/pinctrl-msm.c ret = msm_config_reg(pctrl, g, param, &mask, &bit); mask 275 drivers/pinctrl/qcom/pinctrl-msm.c arg = (val >> bit) & mask; mask 340 drivers/pinctrl/qcom/pinctrl-msm.c unsigned mask; mask 353 drivers/pinctrl/qcom/pinctrl-msm.c ret = msm_config_reg(pctrl, g, param, &mask, &bit); mask 409 drivers/pinctrl/qcom/pinctrl-msm.c if (arg & ~mask) { mask 416 drivers/pinctrl/qcom/pinctrl-msm.c val &= ~(mask << bit); mask 56 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long mask; mask 61 drivers/pinctrl/samsung/pinctrl-exynos.c mask = readl(bank->eint_base + reg_mask); mask 62 drivers/pinctrl/samsung/pinctrl-exynos.c mask |= 1 << irqd->hwirq; mask 63 drivers/pinctrl/samsung/pinctrl-exynos.c writel(mask, bank->eint_base + reg_mask); mask 84 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long mask; mask 100 drivers/pinctrl/samsung/pinctrl-exynos.c mask = readl(bank->eint_base + reg_mask); mask 101 drivers/pinctrl/samsung/pinctrl-exynos.c mask &= ~(1 << irqd->hwirq); mask 102 drivers/pinctrl/samsung/pinctrl-exynos.c writel(mask, bank->eint_base + reg_mask); mask 155 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned int shift, mask, con; mask 168 drivers/pinctrl/samsung/pinctrl-exynos.c mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 173 drivers/pinctrl/samsung/pinctrl-exynos.c con &= ~(mask << shift); mask 187 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned int shift, mask, con; mask 191 drivers/pinctrl/samsung/pinctrl-exynos.c mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 196 drivers/pinctrl/samsung/pinctrl-exynos.c con &= ~(mask << shift); mask 448 drivers/pinctrl/samsung/pinctrl-exynos.c unsigned long mask; mask 457 drivers/pinctrl/samsung/pinctrl-exynos.c mask = readl(b->eint_base + b->irq_chip->eint_mask mask 459 drivers/pinctrl/samsung/pinctrl-exynos.c exynos_irq_demux_eint(pend & ~mask, b->irq_domain); mask 145 drivers/pinctrl/samsung/pinctrl-s3c24xx.c u32 mask; mask 151 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 156 drivers/pinctrl/samsung/pinctrl-s3c24xx.c val &= ~(mask << shift); mask 267 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned long mask; mask 269 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = readl(d->virt_base + EINTMASK_REG); mask 270 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask |= (1UL << data->hwirq); mask 271 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(mask, d->virt_base + EINTMASK_REG); mask 278 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned long mask; mask 280 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = readl(d->virt_base + EINTMASK_REG); mask 281 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask &= ~(1UL << data->hwirq); mask 282 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(mask, d->virt_base + EINTMASK_REG); mask 328 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned long mask; mask 330 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = readl(d->virt_base + EINTMASK_REG); mask 331 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask |= (1UL << index); mask 332 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(mask, d->virt_base + EINTMASK_REG); mask 340 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned long mask; mask 342 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = readl(d->virt_base + EINTMASK_REG); mask 343 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask &= ~(1UL << index); mask 344 drivers/pinctrl/samsung/pinctrl-s3c24xx.c writel(mask, d->virt_base + EINTMASK_REG); mask 361 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned int pend, mask; mask 366 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = readl(d->virt_base + EINTMASK_REG); mask 368 drivers/pinctrl/samsung/pinctrl-s3c24xx.c pend &= ~mask; mask 520 drivers/pinctrl/samsung/pinctrl-s3c24xx.c unsigned int mask; mask 546 drivers/pinctrl/samsung/pinctrl-s3c24xx.c mask = bank->eint_mask; mask 547 drivers/pinctrl/samsung/pinctrl-s3c24xx.c for (pin = 0; mask; ++pin, mask >>= 1) { mask 550 drivers/pinctrl/samsung/pinctrl-s3c24xx.c if (!(mask & 1)) mask 274 drivers/pinctrl/samsung/pinctrl-s3c64xx.c u32 mask; mask 287 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 292 drivers/pinctrl/samsung/pinctrl-s3c64xx.c val &= ~(mask << shift); mask 303 drivers/pinctrl/samsung/pinctrl-s3c64xx.c static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask) mask 312 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (mask) mask 468 drivers/pinctrl/samsung/pinctrl-s3c64xx.c unsigned int mask; mask 473 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; mask 474 drivers/pinctrl/samsung/pinctrl-s3c64xx.c nr_eints = fls(mask); mask 510 drivers/pinctrl/samsung/pinctrl-s3c64xx.c static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask) mask 518 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (mask) mask 599 drivers/pinctrl/samsung/pinctrl-s3c64xx.c unsigned int pend, mask; mask 604 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = readl(drvdata->virt_base + EINT0MASK_REG); mask 606 drivers/pinctrl/samsung/pinctrl-s3c64xx.c pend = pend & range & ~mask; mask 733 drivers/pinctrl/samsung/pinctrl-s3c64xx.c unsigned int mask; mask 740 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; mask 741 drivers/pinctrl/samsung/pinctrl-s3c64xx.c nr_eints = fls(mask); mask 757 drivers/pinctrl/samsung/pinctrl-s3c64xx.c mask = bank->eint_mask; mask 758 drivers/pinctrl/samsung/pinctrl-s3c64xx.c for (pin = 0; mask; ++pin, mask >>= 1) { mask 759 drivers/pinctrl/samsung/pinctrl-s3c64xx.c if (!(mask & 1)) mask 383 drivers/pinctrl/samsung/pinctrl-samsung.c u32 mask, shift, data, pin_offset; mask 395 drivers/pinctrl/samsung/pinctrl-samsung.c mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 406 drivers/pinctrl/samsung/pinctrl-samsung.c data &= ~(mask << shift); mask 439 drivers/pinctrl/samsung/pinctrl-samsung.c u32 data, width, pin_offset, mask, shift; mask 456 drivers/pinctrl/samsung/pinctrl-samsung.c mask = (1 << width) - 1; mask 462 drivers/pinctrl/samsung/pinctrl-samsung.c data &= ~(mask << shift); mask 467 drivers/pinctrl/samsung/pinctrl-samsung.c data &= mask; mask 597 drivers/pinctrl/samsung/pinctrl-samsung.c u32 data, mask, shift; mask 605 drivers/pinctrl/samsung/pinctrl-samsung.c mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; mask 614 drivers/pinctrl/samsung/pinctrl-samsung.c data &= ~(mask << shift); mask 214 drivers/pinctrl/sh-pfc/core.c u32 mask, data; mask 216 drivers/pinctrl/sh-pfc/core.c sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); mask 220 drivers/pinctrl/sh-pfc/core.c crp->reg, value, field, crp->reg_width, hweight32(mask)); mask 222 drivers/pinctrl/sh-pfc/core.c mask = ~(mask << pos); mask 226 drivers/pinctrl/sh-pfc/core.c data &= mask; mask 133 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), mask 136 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | mask 157 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | mask 163 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), mask 166 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17), mask 184 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | mask 190 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), mask 193 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | mask 213 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | mask 219 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), mask 222 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(8), mask 240 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(12), mask 243 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(23), mask 246 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5), mask 263 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5), mask 277 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(15) | BIT(17), mask 291 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10) | BIT(14), mask 294 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(18), mask 311 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(18), mask 325 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30) | BIT(31), mask 328 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), mask 345 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(30), mask 348 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(2) | BIT(3), mask 365 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10), mask 382 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(10), mask 399 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19), mask 416 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), mask 431 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4), mask 446 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), mask 463 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), mask 477 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), mask 494 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3), mask 511 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(24) | BIT(25) | BIT(26), mask 528 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(24) | BIT(25) | BIT(26), mask 545 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), mask 562 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), mask 579 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), mask 596 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(20) | BIT(21), mask 609 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(15), mask 612 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), mask 629 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(12) | BIT(13), mask 646 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), mask 649 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(0) | BIT(1), mask 666 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(1), mask 683 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(27) | BIT(28) | BIT(29), mask 700 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(27) | BIT(28), mask 717 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(14), mask 731 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9) mask 751 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) mask 755 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(23) | BIT(24) | BIT(25), mask 773 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(26) | BIT(27), mask 787 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(13) | BIT(15), mask 804 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4), mask 821 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(5), mask 835 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(6), mask 849 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(7), mask 863 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(14), mask 877 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(8), mask 894 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) mask 913 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(28), mask 948 drivers/pinctrl/sirf/pinctrl-atlas6.c .mask = BIT(9) | BIT(10) | BIT(11), mask 4791 drivers/pinctrl/sirf/pinctrl-atlas7.c u8 mask; mask 4914 drivers/pinctrl/sirf/pinctrl-atlas7.c u8 mask; mask 5176 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = pull_info->s2v[sel].data & pull_info->mask; mask 5179 drivers/pinctrl/sirf/pinctrl-atlas7.c writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg)); mask 5197 drivers/pinctrl/sirf/pinctrl-atlas7.c if (sel & (~(ds_info->mask))) mask 5513 drivers/pinctrl/sirf/pinctrl-atlas7.c status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask; mask 5519 drivers/pinctrl/sirf/pinctrl-atlas7.c regv = (regv >> conf->pupd_bit) & pull_info->mask; mask 137 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | mask 143 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), mask 161 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | mask 167 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), mask 170 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(17), mask 188 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | mask 194 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), mask 197 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | mask 217 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | mask 223 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(31), mask 226 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(23), mask 244 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5), mask 247 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(23) | BIT(28), mask 264 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5), mask 278 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(17), mask 292 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27), mask 309 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(16) | BIT(18), mask 323 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(30) | BIT(31), mask 326 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), mask 343 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3), mask 360 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9), mask 374 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(10), mask 391 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(10), mask 408 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19), mask 425 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), mask 440 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(14), mask 455 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14) mask 473 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), mask 490 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), mask 507 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(27) | BIT(28) | BIT(29), mask 521 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26), mask 538 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26), mask 555 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), mask 572 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), mask 589 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23), mask 606 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(20) | BIT(21), mask 620 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28), mask 637 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(25) | BIT(26), mask 651 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(29) | BIT(30) | BIT(31), mask 654 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(0) | BIT(1), mask 671 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(30) | BIT(31), mask 685 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30), mask 711 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(2) | BIT(3), mask 728 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(14), mask 742 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) mask 762 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(26) | BIT(27), mask 776 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(13) | BIT(15), mask 790 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) mask 795 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(12), mask 813 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(4), mask 830 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(5), mask 844 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(6), mask 858 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(7), mask 872 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(8), mask 886 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(22), mask 902 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(27), mask 937 drivers/pinctrl/sirf/pinctrl-prima2.c .mask = BIT(9) | BIT(10) | BIT(11), mask 153 drivers/pinctrl/sirf/pinctrl-sirf.c const struct sirfsoc_muxmask *mask = mux->muxmask; mask 158 drivers/pinctrl/sirf/pinctrl-sirf.c SIRFSOC_GPIO_PAD_EN(mask[i].group)); mask 160 drivers/pinctrl/sirf/pinctrl-sirf.c muxval = muxval & ~mask[i].mask; mask 162 drivers/pinctrl/sirf/pinctrl-sirf.c muxval = muxval | mask[i].mask; mask 164 drivers/pinctrl/sirf/pinctrl-sirf.c SIRFSOC_GPIO_PAD_EN(mask[i].group)); mask 56 drivers/pinctrl/sirf/pinctrl-sirf.h unsigned long mask; mask 658 drivers/pinctrl/spear/pinctrl-plgpio.c u32 mask, tmp; mask 664 drivers/pinctrl/spear/pinctrl-plgpio.c mask = (1 << (plgpio->chip.ngpio - i * mask 668 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_prepare_reg(enb, off, mask, tmp); mask 671 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_prepare_reg(eit, off, mask, tmp); mask 673 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_prepare_reg(wdata, off, mask, tmp); mask 674 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_prepare_reg(dir, off, mask, tmp); mask 675 drivers/pinctrl/spear/pinctrl-plgpio.c plgpio_prepare_reg(ie, off, mask, tmp); mask 41 drivers/pinctrl/spear/pinctrl-spear.c val &= ~muxreg->mask; mask 48 drivers/pinctrl/spear/pinctrl-spear.c val |= muxreg->mask & temp; mask 73 drivers/pinctrl/spear/pinctrl-spear.c val &= ~pmx_mode->mask; mask 36 drivers/pinctrl/spear/pinctrl-spear.h u16 mask; mask 48 drivers/pinctrl/spear/pinctrl-spear.h u32 mask; mask 64 drivers/pinctrl/spear/pinctrl-spear.h .mask = __mask, \ mask 73 drivers/pinctrl/spear/pinctrl-spear.h .mask = __mask, \ mask 77 drivers/pinctrl/spear/pinctrl-spear.h .mask = __mask, \ mask 241 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2C0_MASK, mask 245 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2C0_MASK, mask 277 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_MASK, mask 281 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_MASK, mask 306 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_CS0_MASK, mask 310 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_CS0_MASK, mask 335 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_CS1_2_MASK, mask 339 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SSP0_CS1_2_MASK, mask 372 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK, mask 376 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK, mask 408 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S1_MASK, mask 412 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S1_MASK, mask 446 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 450 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 475 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD2_MASK, mask 479 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD2_MASK, mask 511 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_EGPIO_0_GRP_MASK, mask 515 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_EGPIO_1_GRP_MASK, mask 519 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_EGPIO_0_GRP_MASK, mask 523 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_EGPIO_1_GRP_MASK, mask 555 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 559 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 583 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 587 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, mask 591 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 595 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK, mask 629 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GMII_MASK, mask 633 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GMII_MASK, mask 667 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG0_MASK, mask 671 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG1_MASK, mask 675 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG2_MASK, mask 679 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG0_MASK, mask 683 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG1_MASK, mask 687 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_RGMII_REG2_MASK, mask 721 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMII_0_1_2_MASK, mask 725 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMII_0_1_2_MASK, mask 757 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFCE2_MASK, mask 761 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFCE2_MASK, mask 797 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND8BIT_0_MASK, mask 801 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND8BIT_1_MASK, mask 805 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND8BIT_0_MASK, mask 809 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND8BIT_1_MASK, mask 835 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND16BIT_1_MASK, mask 839 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND16BIT_1_MASK, mask 864 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND_4CHIPS_MASK, mask 868 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NAND_4CHIPS_MASK, mask 902 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK | mask 929 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL68_MASK, mask 933 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL68_MASK, mask 966 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_UART0_MASK, mask 970 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_UART0_MASK, mask 995 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_UART0_MODEM_MASK, mask 999 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_UART0_MODEM_MASK, mask 1031 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT0_TMR0_MASK, mask 1035 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT0_TMR0_MASK, mask 1060 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT0_TMR1_MASK, mask 1064 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT0_TMR1_MASK, mask 1096 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT1_TMR0_MASK, mask 1100 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT1_TMR0_MASK, mask 1125 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT1_TMR1_MASK, mask 1129 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_GPT1_TMR1_MASK, mask 1164 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCI_DATA8_15_MASK, \ mask 1168 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ mask 1173 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIFALL_2_MASK, \ mask 1177 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCI_DATA8_15_MASK, \ mask 1181 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \ mask 1187 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIFALL_2_MASK, \ mask 1196 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = MCIF_SEL_MASK, mask 1228 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = MCIF_SEL_MASK, mask 1260 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = MCIF_SEL_MASK, mask 1292 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_TOUCH_XY_MASK, mask 1296 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_TOUCH_XY_MASK, mask 1329 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2C0_MASK, mask 1333 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2C0_MASK, mask 1358 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA1_MASK | mask 1363 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA1_MASK | mask 1398 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK, mask 1402 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK, mask 1434 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, mask 1438 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK, mask 1470 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1474 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1508 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1512 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1544 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1548 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK, mask 1581 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, mask 1585 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_CLCD1_MASK | PMX_SMI_MASK, mask 1611 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, mask 1615 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK, mask 1649 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 1653 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_SMI_MASK, mask 1679 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA4_MASK, mask 1683 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA5_MASK, mask 1687 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA4_MASK, mask 1691 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA5_MASK, mask 1717 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA6_MASK | mask 1722 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIDATA6_MASK | mask 1758 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK, mask 1762 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK, mask 1788 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIIORDRE_MASK | mask 1793 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIIORDRE_MASK | mask 1820 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIRESETCF_MASK | mask 1825 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIRESETCF_MASK | mask 1861 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFRSTPWDWN2_MASK, mask 1865 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFRSTPWDWN3_MASK, mask 1869 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFRSTPWDWN2_MASK, mask 1873 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_NFRSTPWDWN3_MASK, mask 1899 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, mask 1903 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK, mask 1937 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, mask 1941 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK, mask 1967 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK, mask 1971 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK, mask 2008 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCI_DATA8_15_MASK, mask 2012 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_PCI_REG1_MASK, mask 2016 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_PCI_REG2_MASK, mask 2020 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCI_DATA8_15_MASK, mask 2024 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_PCI_REG1_MASK, mask 2028 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_PCI_REG2_MASK, mask 2059 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PCIE_CFG_VAL(0), mask 2081 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PCIE_CFG_VAL(1), mask 2103 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PCIE_CFG_VAL(2), mask 2133 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = SATA_CFG_VAL(0), mask 2155 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = SATA_CFG_VAL(1), mask 2177 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = SATA_CFG_VAL(2), mask 2208 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | mask 2214 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK | mask 2243 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | mask 2248 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK | mask 2283 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK mask 2288 drivers/pinctrl/spear/pinctrl-spear1310.c .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK mask 219 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REG0_MASK, mask 223 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 227 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 231 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 235 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 239 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 243 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REGS_MASK, mask 247 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PADS_AS_GPIO_REG7_MASK, mask 280 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = FSMC_8BIT_REG7_MASK, mask 305 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = KBD_ROW_COL_MASK, mask 309 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, mask 336 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_MASK, mask 340 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = FSMC_PNOR_AND_MCIF_REG6_MASK, mask 374 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = KBD_ROW_COL_MASK, mask 378 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, mask 403 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = KBD_COL5_MASK, mask 407 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM1_AND_KBD_COL5_REG0_MASK, mask 440 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SPDIF_IN_REG0_MASK, mask 472 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SPDIF_OUT_REG4_MASK, mask 476 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SPDIF_OUT_ENB_MASK, mask 508 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, mask 512 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = UART0_ENH_AND_GPT_REG0_MASK | mask 548 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SSP0_CS1_MASK, mask 552 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM0_AND_SSP0_CS1_REG0_MASK, mask 577 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = KBD_COL5_MASK, mask 581 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM1_AND_KBD_COL5_REG0_MASK, mask 606 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GPT0_TMR0_CPT_MASK, mask 610 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, mask 635 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GPT0_TMR1_CLK_MASK, mask 639 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, mask 672 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_REG1_MASK, mask 698 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM0_MASK, mask 702 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM0_REG2_MASK, mask 728 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM1_MASK, mask 732 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM1_REG1_MASK, mask 736 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM1_REG2_MASK, mask 762 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM2_MASK, mask 766 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM2_REG1_MASK, mask 792 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM3_MASK, mask 796 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM3_REG0_MASK, mask 800 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM3_REG1_MASK, mask 834 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM0_MASK, mask 838 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM0_REG2_MASK, mask 871 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM1_MASK, mask 875 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM1_REG1_MASK, mask 879 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM1_REG2_MASK, mask 912 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM2_MASK, mask 916 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM2_REG1_MASK, mask 949 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CAM3_MASK, mask 953 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM3_REG0_MASK, mask 957 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = VIP_AND_CAM3_REG1_MASK, mask 989 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SMI_REG2_MASK, mask 1021 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SSP0_REG2_MASK, mask 1046 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SSP0_CS1_MASK, mask 1050 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = PWM0_AND_SSP0_CS1_REG0_MASK, mask 1075 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SSP0_CS2_MASK, mask 1079 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = TS_AND_SSP0_CS2_REG2_MASK, mask 1104 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SSP0_CS3_REG4_MASK, mask 1137 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = UART0_REG2_MASK, mask 1162 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GPT_MASK, mask 1166 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = UART0_ENH_AND_GPT_REG0_MASK, mask 1198 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = UART1_REG2_MASK, mask 1230 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = I2S_IN_REG2_MASK, mask 1234 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = I2S_IN_REG3_MASK, mask 1259 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = I2S_OUT_REG3_MASK, mask 1293 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_REG3_MASK, \ mask 1297 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_REG4_MASK, \ mask 1306 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_PHY_IF_SEL_MASK, mask 1331 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_PHY_IF_SEL_MASK, mask 1356 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_PHY_IF_SEL_MASK, mask 1381 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = GMAC_PHY_IF_SEL_MASK, mask 1414 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = I2C0_REG4_MASK, mask 1446 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = I2C1_REG0_MASK, mask 1478 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CEC0_REG4_MASK, mask 1510 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CEC1_REG4_MASK, mask 1545 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_MASK, \ mask 1549 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ mask 1553 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_REG7_MASK, \ mask 1562 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_SEL_MASK, mask 1594 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_SEL_MASK, mask 1626 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MCIF_SEL_MASK, mask 1662 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, mask 1666 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, mask 1670 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG5_MASK, mask 1674 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG6_MASK, mask 1698 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, mask 1702 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, mask 1706 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG5_MASK, mask 1710 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG6_MASK, mask 1745 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = ARM_TRACE_MASK, mask 1749 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG4_MASK, mask 1753 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG5_MASK, mask 1757 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = CLCD_AND_ARM_TRACE_REG6_MASK, mask 1791 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = MIPHY_DBG_MASK, mask 1795 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, mask 1827 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SATA_PCIE_CFG_MASK, mask 1859 drivers/pinctrl/spear/pinctrl-spear1340.c .mask = SATA_PCIE_CFG_MASK, mask 43 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 51 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 59 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 67 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 75 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 83 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 91 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 99 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 107 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 115 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 123 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 131 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 139 drivers/pinctrl/spear/pinctrl-spear300.c .mask = 0x0000000F, mask 164 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_FIRDA_MASK, mask 191 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, mask 226 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 253 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_2_3_MASK, mask 287 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, mask 324 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 360 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_MII_MASK, mask 386 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, mask 419 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_0_1_MASK, mask 453 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_UART0_MODEM_MASK, mask 489 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | mask 521 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | mask 559 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_UART0_MODEM_MASK, mask 586 drivers/pinctrl/spear/pinctrl-spear300.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 28 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 60 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_FIRDA_MASK, mask 92 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_TIMER_0_1_MASK, mask 124 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_UART0_MODEM_MASK, mask 156 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_UART0_MODEM_MASK, mask 188 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_UART0_MODEM_MASK, mask 220 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_SSP_CS_MASK, mask 252 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_MII_MASK, mask 284 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_MII_MASK, mask 316 drivers/pinctrl/spear/pinctrl-spear310.c .mask = PMX_MII_MASK, mask 36 drivers/pinctrl/spear/pinctrl-spear320.c .mask = 0x00000007, mask 44 drivers/pinctrl/spear/pinctrl-spear320.c .mask = 0x00000007, mask 52 drivers/pinctrl/spear/pinctrl-spear320.c .mask = 0x00000007, mask 60 drivers/pinctrl/spear/pinctrl-spear320.c .mask = 0x00000007, mask 68 drivers/pinctrl/spear/pinctrl-spear320.c .mask = 0x00000001, mask 465 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_69_MASK, mask 469 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | mask 477 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | mask 483 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | mask 522 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 530 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, mask 534 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | mask 541 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_69_MASK, mask 545 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | mask 553 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | mask 559 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | mask 565 drivers/pinctrl/spear/pinctrl-spear320.c .mask = EMI_FSMC_DYNAMIC_MUX_MASK, mask 603 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | mask 609 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | mask 615 drivers/pinctrl/spear/pinctrl-spear320.c .mask = EMI_FSMC_DYNAMIC_MUX_MASK, mask 641 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 649 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, mask 653 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, mask 696 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_69_MASK, mask 700 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | mask 708 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_80_TO_85_MASK, mask 741 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK, mask 749 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_34_MASK, mask 781 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 789 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | mask 795 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_50_MASK, mask 799 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_99_MASK, mask 803 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_100_101_MASK, mask 811 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 815 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_12_MASK, mask 819 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SDHCI_CD_PORT_SEL_MASK, mask 827 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_51_MASK, mask 831 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SDHCI_CD_PORT_SEL_MASK, mask 898 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK, mask 902 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 910 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, mask 914 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, mask 951 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, mask 959 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_28_29_MASK, mask 1001 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, mask 1005 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, mask 1010 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART1_ENH_PORT_SEL_MASK, mask 1018 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | mask 1027 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | mask 1034 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART1_ENH_PORT_SEL_MASK, mask 1042 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | mask 1051 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, mask 1056 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, mask 1060 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART1_ENH_PORT_SEL_MASK, mask 1068 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_80_TO_85_MASK, mask 1072 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, mask 1076 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART1_ENH_PORT_SEL_MASK, mask 1163 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_FIRDA_MASK, mask 1171 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_0_1_MASK, mask 1211 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_MASK, mask 1215 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_8_9_MASK, mask 1219 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1227 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 1231 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_15_16_MASK, mask 1235 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1243 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 1247 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_41_42_MASK, mask 1251 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1259 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_52_53_MASK, mask 1263 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1271 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, mask 1275 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1283 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_94_95_MASK, mask 1287 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1295 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, mask 1299 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART3_PORT_SEL_MASK, mask 1420 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_MASK, mask 1424 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_6_7_MASK, mask 1428 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART4_PORT_SEL_MASK, mask 1436 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 1440 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_13_14_MASK, mask 1444 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART4_PORT_SEL_MASK, mask 1452 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 1456 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_39_MASK, mask 1460 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_40_MASK, mask 1464 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART4_PORT_SEL_MASK, mask 1472 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_71_72_MASK, mask 1476 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART4_PORT_SEL_MASK, mask 1484 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_92_93_MASK, mask 1488 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART4_PORT_SEL_MASK, mask 1496 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_100_101_MASK | mask 1606 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C_MASK, mask 1610 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_4_5_MASK, mask 1614 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART5_PORT_SEL_MASK, mask 1622 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 1626 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_37_38_MASK, mask 1630 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART5_PORT_SEL_MASK, mask 1638 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_69_MASK, mask 1642 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_70_MASK, mask 1646 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART5_PORT_SEL_MASK, mask 1654 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_90_91_MASK, mask 1658 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART5_PORT_SEL_MASK, mask 1736 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MASK, mask 1740 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_2_3_MASK, mask 1744 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART6_PORT_SEL_MASK, mask 1752 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_88_89_MASK, mask 1756 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART6_PORT_SEL_MASK, mask 1807 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_77_78_79_MASK, mask 1840 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, mask 1848 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_5_MASK, mask 1852 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_36_MASK, mask 1889 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, mask 1897 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_32_33_MASK, mask 1934 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, mask 1942 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_30_31_MASK, mask 1982 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_MASK, mask 1986 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_8_9_MASK, mask 1994 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2002 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, mask 2010 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, mask 2014 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, mask 2022 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 2030 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_37_38_MASK, mask 2038 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , mask 2042 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, mask 2051 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_59_MASK, mask 2055 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_60_MASK, mask 2063 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_88_89_MASK, mask 2195 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK, mask 2203 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_7_MASK, mask 2211 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2219 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_13_MASK, mask 2227 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN1_MASK, mask 2231 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_29_MASK, mask 2239 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK, mask 2243 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PWM_MASK, mask 2247 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_34_MASK, mask 2255 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 2259 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_41_MASK, mask 2267 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_58_MASK, mask 2275 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_87_MASK, mask 2402 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_MASK, mask 2406 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_6_MASK, mask 2414 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2422 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_12_MASK, mask 2430 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_GPIO_PIN0_MASK, mask 2434 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_28_MASK, mask 2442 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK, mask 2446 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_40_MASK, mask 2454 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_57_MASK, mask 2462 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_86_MASK, mask 2575 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2583 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, mask 2587 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_20_MASK, mask 2591 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP1_PORT_SEL_MASK, mask 2599 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, mask 2603 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, mask 2608 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP1_PORT_SEL_MASK, mask 2616 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 2620 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_48_49_MASK, mask 2624 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_50_51_MASK, mask 2628 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP1_PORT_SEL_MASK, mask 2636 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_65_TO_68_MASK, mask 2640 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP1_PORT_SEL_MASK, mask 2648 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, mask 2652 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP1_PORT_SEL_MASK, mask 2750 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2758 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, mask 2762 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP2_PORT_SEL_MASK, mask 2770 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | mask 2775 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, mask 2780 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP2_PORT_SEL_MASK, mask 2788 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, mask 2792 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, mask 2796 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP2_PORT_SEL_MASK, mask 2804 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_61_TO_64_MASK, mask 2808 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP2_PORT_SEL_MASK, mask 2816 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, mask 2820 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP2_PORT_SEL_MASK, mask 2917 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | mask 2923 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | mask 2929 drivers/pinctrl/spear/pinctrl-spear320.c .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | mask 2968 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 2976 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_10_11_MASK, mask 2980 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_21_TO_27_MASK, mask 2984 drivers/pinctrl/spear/pinctrl-spear320.c .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | mask 2996 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | mask 3003 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, mask 3007 drivers/pinctrl/spear/pinctrl-spear320.c .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | mask 3072 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_SSP_CS_MASK, mask 3076 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_8_9_MASK, mask 3080 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C1_PORT_SEL_MASK, mask 3088 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, mask 3092 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C1_PORT_SEL_MASK, mask 3144 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_FIRDA_MASK, mask 3148 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_0_1_MASK, mask 3152 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C2_PORT_SEL_MASK, mask 3160 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_UART0_MASK, mask 3164 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_2_3_MASK, mask 3168 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C2_PORT_SEL_MASK, mask 3176 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_MII_MASK, mask 3180 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_19_MASK, mask 3184 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_20_MASK, mask 3188 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C2_PORT_SEL_MASK, mask 3196 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_75_76_MASK, mask 3200 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C2_PORT_SEL_MASK, mask 3208 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_PL_96_97_MASK, mask 3212 drivers/pinctrl/spear/pinctrl-spear320.c .mask = PMX_I2C2_PORT_SEL_MASK, mask 26 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_FIRDA_MASK, mask 59 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_I2C_MASK, mask 92 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_SSP_CS_MASK, mask 125 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_SSP_MASK, mask 159 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_MII_MASK, mask 192 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN0_MASK, mask 218 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN1_MASK, mask 244 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN2_MASK, mask 270 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN3_MASK, mask 296 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN4_MASK, mask 322 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_GPIO_PIN5_MASK, mask 357 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_UART0_MODEM_MASK, mask 390 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_UART0_MASK, mask 423 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_TIMER_0_1_MASK, mask 456 drivers/pinctrl/spear/pinctrl-spear3xx.c .mask = PMX_TIMER_2_3_MASK, mask 590 drivers/pinctrl/sprd/pinctrl-sprd.c unsigned int param, arg, shift, mask, val; mask 597 drivers/pinctrl/sprd/pinctrl-sprd.c mask = 0; mask 613 drivers/pinctrl/sprd/pinctrl-sprd.c mask = SLEEP_MODE_MASK; mask 623 drivers/pinctrl/sprd/pinctrl-sprd.c mask = SLEEP_INPUT_MASK; mask 630 drivers/pinctrl/sprd/pinctrl-sprd.c mask = SLEEP_OUTPUT_MASK; mask 639 drivers/pinctrl/sprd/pinctrl-sprd.c mask = DRIVE_STRENGTH_MASK; mask 645 drivers/pinctrl/sprd/pinctrl-sprd.c mask = SLEEP_PULL_DOWN_MASK; mask 649 drivers/pinctrl/sprd/pinctrl-sprd.c mask = PULL_DOWN_MASK; mask 659 drivers/pinctrl/sprd/pinctrl-sprd.c mask = INPUT_SCHMITT_MASK; mask 665 drivers/pinctrl/sprd/pinctrl-sprd.c mask = SLEEP_PULL_UP_MASK; mask 673 drivers/pinctrl/sprd/pinctrl-sprd.c mask = PULL_UP_MASK; mask 695 drivers/pinctrl/sprd/pinctrl-sprd.c reg &= ~(mask << shift); mask 1260 drivers/pinctrl/stm32/pinctrl-stm32.c int mask, mask_width; mask 1272 drivers/pinctrl/stm32/pinctrl-stm32.c ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask); mask 1274 drivers/pinctrl/stm32/pinctrl-stm32.c mask = SYSCFG_IRQMUX_MASK; mask 1276 drivers/pinctrl/stm32/pinctrl-stm32.c mask_width = fls(mask); mask 447 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 *offset, u32 *shift, u32 *mask) mask 453 drivers/pinctrl/sunxi/pinctrl-sunxi.c *mask = DLEVEL_PINS_MASK; mask 461 drivers/pinctrl/sunxi/pinctrl-sunxi.c *mask = PULL_PINS_MASK; mask 476 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 offset, shift, mask, val; mask 482 drivers/pinctrl/sunxi/pinctrl-sunxi.c ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); mask 486 drivers/pinctrl/sunxi/pinctrl-sunxi.c val = (readl(pctl->membase + offset) >> shift) & mask; mask 542 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 offset, shift, mask, reg; mask 549 drivers/pinctrl/sunxi/pinctrl-sunxi.c ret = sunxi_pconf_reg(pin, param, &offset, &shift, &mask); mask 587 drivers/pinctrl/sunxi/pinctrl-sunxi.c reg &= ~(mask << shift); mask 704 drivers/pinctrl/sunxi/pinctrl-sunxi.c u32 val, mask; mask 710 drivers/pinctrl/sunxi/pinctrl-sunxi.c mask = MUX_PINS_MASK << sunxi_mux_offset(pin); mask 711 drivers/pinctrl/sunxi/pinctrl-sunxi.c writel((val & ~mask) | config << sunxi_mux_offset(pin), mask 70 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c unsigned int mask; mask 313 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c value &= ~(lane->mask << lane->shift); mask 832 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c .mask = _mask, \ mask 449 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val, mask; mask 459 drivers/pinctrl/tegra/pinctrl-tegra.c mask = (1 << width) - 1; mask 460 drivers/pinctrl/tegra/pinctrl-tegra.c arg = (val >> bit) & mask; mask 478 drivers/pinctrl/tegra/pinctrl-tegra.c u32 val, mask; mask 506 drivers/pinctrl/tegra/pinctrl-tegra.c mask = (1 << width) - 1; mask 507 drivers/pinctrl/tegra/pinctrl-tegra.c if (arg & ~mask) { mask 515 drivers/pinctrl/tegra/pinctrl-tegra.c val &= ~(mask << bit); mask 165 drivers/pinctrl/ti/pinctrl-ti-iodelay.c static inline u32 ti_iodelay_extract(u32 val, u32 mask) mask 167 drivers/pinctrl/ti/pinctrl-ti-iodelay.c return (val & mask) >> __ffs(mask); mask 150 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int *mask, mask 199 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c *mask = (1U << width) - 1; mask 259 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; mask 264 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c &mask, &strengths); mask 268 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c if (mask) { mask 276 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c *strength = strengths[(val >> shift) & mask]; mask 287 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, mask, val; mask 298 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask = BIT(iectrl % 32); mask 304 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return val & mask ? 0 : -EINVAL; mask 421 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, shift, mask, val; mask 426 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c &mask, &strengths); mask 433 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c for (val = 0; val <= mask; val++) { mask 445 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c if (!mask) mask 451 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask << shift, val << shift); mask 460 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int reg, mask; mask 478 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask = BIT(iectrl % 32); mask 480 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0); mask 582 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask; mask 617 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask = (1U << mux_bits) - 1; mask 625 drivers/pinctrl/uniphier/pinctrl-uniphier-core.c mask << shift, muxval << shift); mask 27 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 mask) mask 32 drivers/pinctrl/vt8500/pinctrl-wmt.c val |= mask; mask 37 drivers/pinctrl/vt8500/pinctrl-wmt.c u32 mask) mask 42 drivers/pinctrl/vt8500/pinctrl-wmt.c val &= ~mask; mask 65 drivers/pinctrl/zte/pinctrl-zx.c u32 mask, offset, bitpos; mask 75 drivers/pinctrl/zte/pinctrl-zx.c mask = (1 << data->width) - 1; mask 118 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(mask << bitpos); mask 119 drivers/pinctrl/zte/pinctrl-zx.c val |= (mval & mask) << bitpos; mask 138 drivers/pinctrl/zte/pinctrl-zx.c val &= ~(mask << bitpos); mask 139 drivers/pinctrl/zte/pinctrl-zx.c val |= (mval & mask) << bitpos; mask 175 drivers/platform/chrome/cros_ec_debugfs.c __poll_t mask = 0; mask 183 drivers/platform/chrome/cros_ec_debugfs.c mask |= EPOLLIN | EPOLLRDNORM; mask 186 drivers/platform/chrome/cros_ec_debugfs.c return mask; mask 177 drivers/platform/chrome/cros_ec_proto.c uint32_t *mask) mask 190 drivers/platform/chrome/cros_ec_proto.c *mask = r->mask; mask 298 drivers/platform/chrome/cros_ec_proto.c u16 cmd, u32 *mask) mask 321 drivers/platform/chrome/cros_ec_proto.c *mask = rver->version_mask; mask 327 drivers/platform/chrome/wilco_ec/event.c __poll_t mask = 0; mask 333 drivers/platform/chrome/wilco_ec/event.c mask |= EPOLLIN | EPOLLRDNORM | EPOLLPRI; mask 334 drivers/platform/chrome/wilco_ec/event.c return mask; mask 507 drivers/platform/goldfish/goldfish_pipe.c __poll_t mask = 0; mask 517 drivers/platform/goldfish/goldfish_pipe.c mask |= EPOLLIN | EPOLLRDNORM; mask 519 drivers/platform/goldfish/goldfish_pipe.c mask |= EPOLLOUT | EPOLLWRNORM; mask 521 drivers/platform/goldfish/goldfish_pipe.c mask |= EPOLLHUP; mask 523 drivers/platform/goldfish/goldfish_pipe.c mask |= EPOLLERR; mask 525 drivers/platform/goldfish/goldfish_pipe.c return mask; mask 94 drivers/platform/mellanox/mlxreg-hotplug.c u32 mask; mask 179 drivers/platform/mellanox/mlxreg-hotplug.c regval &= data->mask; mask 183 drivers/platform/mellanox/mlxreg-hotplug.c regval = !(regval & data->mask); mask 185 drivers/platform/mellanox/mlxreg-hotplug.c regval = !!(regval & data->mask); mask 264 drivers/platform/mellanox/mlxreg-hotplug.c item->reg, item->mask); mask 281 drivers/platform/mellanox/mlxreg-hotplug.c regval &= item->mask; mask 308 drivers/platform/mellanox/mlxreg-hotplug.c item->mask); mask 335 drivers/platform/mellanox/mlxreg-hotplug.c regval &= data->mask; mask 378 drivers/platform/mellanox/mlxreg-hotplug.c MLXREG_HOTPLUG_MASK_OFF, data->mask); mask 440 drivers/platform/mellanox/mlxreg-hotplug.c regval &= pdata->mask; mask 451 drivers/platform/mellanox/mlxreg-hotplug.c aggr_asserted = pdata->mask; mask 488 drivers/platform/mellanox/mlxreg-hotplug.c MLXREG_HOTPLUG_AGGR_MASK_OFF, pdata->mask); mask 528 drivers/platform/mellanox/mlxreg-hotplug.c item->mask &= ~BIT(j); mask 534 drivers/platform/mellanox/mlxreg-hotplug.c item->cache = item->mask; mask 537 drivers/platform/mellanox/mlxreg-hotplug.c item->mask); mask 545 drivers/platform/mellanox/mlxreg-hotplug.c MLXREG_HOTPLUG_AGGR_MASK_OFF, pdata->mask); mask 68 drivers/platform/mellanox/mlxreg-io.c *regval = !!(*regval & ~data->mask); mask 71 drivers/platform/mellanox/mlxreg-io.c *regval &= data->mask; mask 73 drivers/platform/mellanox/mlxreg-io.c *regval |= ~data->mask; mask 75 drivers/platform/mellanox/mlxreg-io.c } else if (data->mask) { mask 79 drivers/platform/mellanox/mlxreg-io.c *regval = ror32(*regval & data->mask, (data->bit - 1)); mask 82 drivers/platform/mellanox/mlxreg-io.c in_val = rol32(in_val, data->bit - 1) & data->mask; mask 84 drivers/platform/mellanox/mlxreg-io.c *regval = (*regval & ~data->mask) | in_val; mask 575 drivers/platform/olpc/olpc-xo175-ec.c static int olpc_xo175_ec_set_event_mask(unsigned int mask) mask 579 drivers/platform/olpc/olpc-xo175-ec.c args[0] = mask >> 0; mask 580 drivers/platform/olpc/olpc-xo175-ec.c args[1] = mask >> 8; mask 969 drivers/platform/x86/asus-laptop.c static int asus_wireless_status(struct asus_laptop *asus, int mask) mask 975 drivers/platform/x86/asus-laptop.c return (asus->wireless_status & mask) ? 1 : 0; mask 983 drivers/platform/x86/asus-laptop.c return !!(status & mask); mask 342 drivers/platform/x86/asus-wmi.c u32 dev_id, u32 mask) mask 354 drivers/platform/x86/asus-wmi.c if (mask == ASUS_WMI_DSTS_STATUS_BIT) { mask 359 drivers/platform/x86/asus-wmi.c return retval & mask; mask 1663 drivers/platform/x86/asus-wmi.c u8 mask = asus->fan_boost_mode_mask; mask 1666 drivers/platform/x86/asus-wmi.c if (mask & ASUS_FAN_BOOST_MODE_OVERBOOST_MASK) mask 1668 drivers/platform/x86/asus-wmi.c else if (mask & ASUS_FAN_BOOST_MODE_SILENT_MASK) mask 1671 drivers/platform/x86/asus-wmi.c if (mask & ASUS_FAN_BOOST_MODE_SILENT_MASK) mask 1697 drivers/platform/x86/asus-wmi.c u8 mask = asus->fan_boost_mode_mask; mask 1706 drivers/platform/x86/asus-wmi.c if (!(mask & ASUS_FAN_BOOST_MODE_OVERBOOST_MASK)) mask 1709 drivers/platform/x86/asus-wmi.c if (!(mask & ASUS_FAN_BOOST_MODE_SILENT_MASK)) mask 280 drivers/platform/x86/hp-wmi.c static int hp_wmi_hw_state(int mask) mask 287 drivers/platform/x86/hp-wmi.c return !!(state & mask); mask 339 drivers/platform/x86/hp-wmi.c int mask = 0x200 << (r * 8); mask 346 drivers/platform/x86/hp-wmi.c return !(wireless & mask); mask 351 drivers/platform/x86/hp-wmi.c int mask = 0x800 << (r * 8); mask 358 drivers/platform/x86/hp-wmi.c return !(wireless & mask); mask 118 drivers/platform/x86/intel_oaktrail.c unsigned long mask) mask 125 drivers/platform/x86/intel_oaktrail.c &oaktrail_rfkill_ops, (void *)mask); mask 130 drivers/platform/x86/intel_oaktrail.c rfkill_init_sw_state(rfkill_dev, (value & mask) != 1); mask 312 drivers/platform/x86/intel_pmc_ipc.c int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) mask 325 drivers/platform/x86/intel_pmc_ipc.c new_val &= ~mask; mask 326 drivers/platform/x86/intel_pmc_ipc.c new_val |= val & mask; mask 333 drivers/platform/x86/intel_pmc_ipc.c if ((new_val & mask) != (val & mask)) { mask 412 drivers/platform/x86/intel_scu_ipc.c int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) mask 414 drivers/platform/x86/intel_scu_ipc.c u8 data[2] = { bits, mask }; mask 34 drivers/platform/x86/intel_scu_ipcutil.c u8 mask; /* Valid for read-modify-write */ mask 60 drivers/platform/x86/intel_scu_ipcutil.c data->data[0], data->mask); mask 193 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, mask 284 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 291 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 301 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 308 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 318 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 325 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 332 drivers/platform/x86/mlx-platform.c .mask = BIT(2), mask 339 drivers/platform/x86/mlx-platform.c .mask = BIT(3), mask 349 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 359 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PSU_MASK, mask 368 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PWR_MASK, mask 377 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_FAN_MASK, mask 386 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 398 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, mask 407 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 413 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 424 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PWR_MASK, mask 433 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 445 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, mask 455 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 462 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 472 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 479 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 489 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 495 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 501 drivers/platform/x86/mlx-platform.c .mask = BIT(2), mask 507 drivers/platform/x86/mlx-platform.c .mask = BIT(3), mask 517 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PSU_MASK, mask 526 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PWR_MASK, mask 535 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_FAN_MASK, mask 544 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 556 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, mask 566 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 572 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 582 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PWR_MASK, mask 591 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 603 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, mask 613 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 620 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 630 drivers/platform/x86/mlx-platform.c .mask = BIT(0), mask 638 drivers/platform/x86/mlx-platform.c .mask = BIT(1), mask 646 drivers/platform/x86/mlx-platform.c .mask = BIT(2), mask 654 drivers/platform/x86/mlx-platform.c .mask = BIT(3), mask 662 drivers/platform/x86/mlx-platform.c .mask = BIT(4), mask 670 drivers/platform/x86/mlx-platform.c .mask = BIT(5), mask 682 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PSU_MASK, mask 691 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_PWR_MASK, mask 700 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_FAN_NG_MASK, mask 709 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 721 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, mask 731 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 736 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK mask 741 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 746 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 751 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 756 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 761 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 766 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 771 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 776 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 781 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 786 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 800 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 805 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK mask 810 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 815 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 820 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 825 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 830 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 835 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 840 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 854 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 859 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK mask 864 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 869 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 874 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 881 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 888 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 895 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 902 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 909 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 916 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 923 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 930 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 937 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 944 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 951 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, mask 958 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, mask 984 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 990 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 996 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1002 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1008 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), mask 1014 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), mask 1020 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1026 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(7), mask 1032 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1038 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1044 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1050 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1056 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1062 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 1090 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1096 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1102 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1108 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1114 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), mask 1120 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), mask 1126 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1132 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1138 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1144 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1150 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1156 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1162 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 1202 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1208 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1214 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1220 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), mask 1226 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), mask 1232 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1238 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(7), mask 1244 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1250 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1256 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1262 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1268 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1274 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(5), mask 1280 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(0), mask 1286 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(1), mask 1292 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(2), mask 1298 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(3), mask 1304 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(4), mask 1310 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_ASIC_MASK, mask 1336 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1343 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1350 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1357 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1364 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1371 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1378 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1385 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1392 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1399 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1406 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1413 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0), mask 1435 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, mask 1441 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, mask 1447 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, mask 1453 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1462 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, mask 1468 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, mask 1474 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, mask 1501 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, mask 1507 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, mask 1513 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, mask 1518 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, mask 1524 drivers/platform/x86/mlx-platform.c .mask = GENMASK(7, 0) & ~BIT(6), mask 1533 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, mask 1539 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, mask 1545 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, mask 1550 drivers/platform/x86/mlx-platform.c .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, mask 203 drivers/platform/x86/msi-laptop.c static ssize_t set_device_state(const char *buf, size_t count, u8 mask) mask 220 drivers/platform/x86/msi-laptop.c if (!!(rdata & mask) != status) { mask 222 drivers/platform/x86/msi-laptop.c if (rdata & mask) mask 223 drivers/platform/x86/msi-laptop.c wdata = rdata & ~mask; mask 225 drivers/platform/x86/msi-laptop.c wdata = rdata | mask; mask 93 drivers/platform/x86/sony-laptop.c static unsigned long mask = 0xffffffff; mask 94 drivers/platform/x86/sony-laptop.c module_param(mask, ulong, 0644); mask 95 drivers/platform/x86/sony-laptop.c MODULE_PARM_DESC(mask, mask 3350 drivers/platform/x86/sony-laptop.c unsigned long mask; mask 4611 drivers/platform/x86/sony-laptop.c for (i = 0; dev->event_types[i].mask; i++) { mask 4617 drivers/platform/x86/sony-laptop.c if (!(mask & dev->event_types[i].mask)) mask 2255 drivers/platform/x86/thinkpad_acpi.c static int hotkey_mask_set(u32 mask) mask 2260 drivers/platform/x86/thinkpad_acpi.c const u32 fwmask = mask & ~hotkey_source_mask; mask 2266 drivers/platform/x86/thinkpad_acpi.c !!(mask & (1 << i)))) { mask 2296 drivers/platform/x86/thinkpad_acpi.c static int hotkey_user_mask_set(const u32 mask) mask 2303 drivers/platform/x86/thinkpad_acpi.c (mask == 0xffff || mask == 0xffffff || mask 2304 drivers/platform/x86/thinkpad_acpi.c mask == 0xffffffff)) { mask 2307 drivers/platform/x86/thinkpad_acpi.c mask); mask 2313 drivers/platform/x86/thinkpad_acpi.c rc = hotkey_mask_set((mask | hotkey_driver_mask) & ~hotkey_source_mask); mask 2316 drivers/platform/x86/thinkpad_acpi.c hotkey_user_mask = mask & (hotkey_acpi_mask | hotkey_source_mask); mask 2326 drivers/platform/x86/thinkpad_acpi.c static int tpacpi_hotkey_driver_mask_set(const u32 mask) mask 2332 drivers/platform/x86/thinkpad_acpi.c hotkey_driver_mask = mask; mask 2339 drivers/platform/x86/thinkpad_acpi.c hotkey_driver_mask = mask; mask 2341 drivers/platform/x86/thinkpad_acpi.c hotkey_source_mask |= (mask & ~hotkey_all_mask); mask 4297 drivers/platform/x86/thinkpad_acpi.c u32 mask; mask 4306 drivers/platform/x86/thinkpad_acpi.c mask = hotkey_user_mask; mask 4316 drivers/platform/x86/thinkpad_acpi.c mask = (hotkey_all_mask | hotkey_source_mask) mask 4318 drivers/platform/x86/thinkpad_acpi.c } else if (sscanf(cmd, "0x%x", &mask) == 1) { mask 4320 drivers/platform/x86/thinkpad_acpi.c } else if (sscanf(cmd, "%x", &mask) == 1) { mask 4330 drivers/platform/x86/thinkpad_acpi.c "set mask to 0x%08x\n", mask); mask 4331 drivers/platform/x86/thinkpad_acpi.c res = hotkey_user_mask_set(mask); mask 289 drivers/platform/x86/toshiba_acpi.c static inline void _set_bit(u32 *word, u32 mask, int value) mask 291 drivers/platform/x86/toshiba_acpi.c *word = (*word & ~mask) | (mask * value); mask 2461 drivers/platform/x86/toshiba_acpi.c int *val, int *val2, long mask) mask 2465 drivers/platform/x86/toshiba_acpi.c switch (mask) { mask 85 drivers/pnp/pnpbios/rsparser.c int io, size, mask, i, flags; mask 144 drivers/pnp/pnpbios/rsparser.c mask = p[1] + p[2] * 256; mask 145 drivers/pnp/pnpbios/rsparser.c for (i = 0; i < 16; i++, mask = mask >> 1) mask 146 drivers/pnp/pnpbios/rsparser.c if (mask & 0x01) mask 160 drivers/pnp/pnpbios/rsparser.c mask = p[1]; mask 161 drivers/pnp/pnpbios/rsparser.c for (i = 0; i < 8; i++, mask = mask >> 1) mask 162 drivers/pnp/pnpbios/rsparser.c if (mask & 0x01) mask 44 drivers/power/avs/smartreflex.c static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask, mask 59 drivers/power/avs/smartreflex.c mask |= ERRCONFIG_STATUS_V1_MASK; mask 61 drivers/power/avs/smartreflex.c mask |= ERRCONFIG_VPBOUNDINTST_V2; mask 64 drivers/power/avs/smartreflex.c reg_val &= ~mask; mask 66 drivers/power/avs/smartreflex.c value &= mask; mask 23 drivers/power/reset/syscon-poweroff.c static u32 mask; mask 28 drivers/power/reset/syscon-poweroff.c regmap_update_bits(map, offset, mask, value); mask 52 drivers/power/reset/syscon-poweroff.c mask_err = of_property_read_u32(pdev->dev.of_node, "mask", &mask); mask 60 drivers/power/reset/syscon-poweroff.c value = mask; mask 61 drivers/power/reset/syscon-poweroff.c mask = 0xFFFFFFFF; mask 64 drivers/power/reset/syscon-poweroff.c mask = 0xFFFFFFFF; mask 20 drivers/power/reset/syscon-reboot-mode.c u32 mask; mask 32 drivers/power/reset/syscon-reboot-mode.c syscon_rbm->mask, magic); mask 50 drivers/power/reset/syscon-reboot-mode.c syscon_rbm->mask = 0xffffffff; mask 60 drivers/power/reset/syscon-reboot-mode.c of_property_read_u32(pdev->dev.of_node, "mask", &syscon_rbm->mask); mask 22 drivers/power/reset/syscon-reboot.c u32 mask; mask 34 drivers/power/reset/syscon-reboot.c regmap_update_bits(ctx->map, ctx->offset, ctx->mask, ctx->value); mask 61 drivers/power/reset/syscon-reboot.c mask_err = of_property_read_u32(pdev->dev.of_node, "mask", &ctx->mask); mask 69 drivers/power/reset/syscon-reboot.c ctx->value = ctx->mask; mask 70 drivers/power/reset/syscon-reboot.c ctx->mask = 0xFFFFFFFF; mask 73 drivers/power/reset/syscon-reboot.c ctx->mask = 0xFFFFFFFF; mask 26 drivers/power/reset/xgene-reboot.c u32 mask; mask 38 drivers/power/reset/xgene-reboot.c writel(ctx->mask, ctx->csr); mask 63 drivers/power/reset/xgene-reboot.c if (of_property_read_u32(dev->of_node, "mask", &ctx->mask)) mask 64 drivers/power/reset/xgene-reboot.c ctx->mask = 0xFFFFFFFF; mask 149 drivers/power/supply/bd70528-charger.c unsigned int mask; mask 191 drivers/power/supply/bd70528-charger.c mask = BD70528_REG_INT_BAT1_MASK | BD70528_REG_INT_BAT2_MASK; mask 193 drivers/power/supply/bd70528-charger.c BD70528_REG_INT_MAIN_MASK, mask, 0); mask 218 drivers/power/supply/bq2415x_charger.c u8 mask, u8 shift) mask 228 drivers/power/supply/bq2415x_charger.c return (ret & mask) >> shift; mask 272 drivers/power/supply/bq2415x_charger.c u8 mask, u8 shift) mask 283 drivers/power/supply/bq2415x_charger.c ret &= ~mask; mask 260 drivers/power/supply/bq24190_charger.c u8 mask, u8 shift, u8 *data) mask 269 drivers/power/supply/bq24190_charger.c v &= mask; mask 277 drivers/power/supply/bq24190_charger.c u8 mask, u8 shift, u8 data) mask 286 drivers/power/supply/bq24190_charger.c v &= ~mask; mask 287 drivers/power/supply/bq24190_charger.c v |= ((data << shift) & mask); mask 293 drivers/power/supply/bq24190_charger.c u8 reg, u8 mask, u8 shift, mask 300 drivers/power/supply/bq24190_charger.c ret = bq24190_read_mask(bdi, reg, mask, shift, &v); mask 311 drivers/power/supply/bq24190_charger.c u8 reg, u8 mask, u8 shift, mask 319 drivers/power/supply/bq24190_charger.c return bq24190_write_mask(bdi, reg, mask, shift, idx); mask 335 drivers/power/supply/bq24190_charger.c .mask = BQ24190_REG_##r##_##f##_MASK, \ mask 354 drivers/power/supply/bq24190_charger.c u8 mask; mask 454 drivers/power/supply/bq24190_charger.c ret = bq24190_read_mask(bdi, info->reg, info->mask, info->shift, &v); mask 487 drivers/power/supply/bq24190_charger.c ret = bq24190_write_mask(bdi, info->reg, info->mask, info->shift, v); mask 93 drivers/power/supply/bq24735-charger.c u16 mask, u16 value) mask 102 drivers/power/supply/bq24735-charger.c tmp = ret & ~mask; mask 103 drivers/power/supply/bq24735-charger.c tmp |= value & mask; mask 713 drivers/power/supply/qcom_smbb.c unsigned int mask; mask 993 drivers/power/supply/qcom_smbb.c r->mask, r->value); mask 114 drivers/powercap/intel_rapl_common.c u64 mask; mask 123 drivers/powercap/intel_rapl_common.c .mask = m, \ mask 520 drivers/powercap/intel_rapl_common.c unsigned int mask = rp->domain_map & (1 << i); mask 522 drivers/powercap/intel_rapl_common.c if (!mask) mask 657 drivers/powercap/intel_rapl_common.c rp->mask = POWER_HIGH_LOCK; mask 666 drivers/powercap/intel_rapl_common.c ra.mask = rp->mask; mask 697 drivers/powercap/intel_rapl_common.c bits &= rp->mask; mask 702 drivers/powercap/intel_rapl_common.c ra.mask = rp->mask; mask 727 drivers/powercap/intel_rapl_common.c ra.mask = ~0; mask 755 drivers/powercap/intel_rapl_common.c ra.mask = ~0; mask 1093 drivers/powercap/intel_rapl_common.c ra.mask = ~0; mask 1099 drivers/powercap/intel_rapl_common.c ra.mask = ~0; mask 1168 drivers/powercap/intel_rapl_common.c ra.mask = ~0; mask 95 drivers/powercap/intel_rapl_msr.c ra->value &= ra->mask; mask 109 drivers/powercap/intel_rapl_msr.c val &= ~ra->mask; mask 365 drivers/ps3/ps3-lpm.c static const u64 mask = 0xFFFFFFFFFFFFFFFFULL; mask 374 drivers/ps3/ps3-lpm.c result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask, mask 1043 drivers/ps3/ps3-lpm.c void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask) mask 1045 drivers/ps3/ps3-lpm.c if (mask) mask 1046 drivers/ps3/ps3-lpm.c ps3_write_pm(cpu, pm_status, mask); mask 249 drivers/ps3/ps3-vuart.c unsigned long mask) mask 254 drivers/ps3/ps3-vuart.c dev_dbg(&dev->core, "%s:%d: %lxh\n", __func__, __LINE__, mask); mask 256 drivers/ps3/ps3-vuart.c priv->interrupt_mask = mask; mask 136 drivers/ps3/ps3av.c static u32 *ps3av_search_cmd_table(u32 cid, u32 mask) mask 143 drivers/ps3/ps3av.c if ((*table & mask) == (cid & mask)) mask 579 drivers/ps3/ps3av.c unsigned mask:19; mask 619 drivers/ps3/ps3av.c if (res_all & ps3av_preferred_modes[i].mask) mask 686 drivers/ps3/ps3av_cmd.c audio->mask = 0x0FFF; /* XXX set all */ mask 130 drivers/ptp/ptp_qoriq.c u32 ack = 0, lo, hi, mask, val, irqs; mask 135 drivers/ptp/ptp_qoriq.c mask = ptp_qoriq->read(®s->ctrl_regs->tmr_temask); mask 139 drivers/ptp/ptp_qoriq.c irqs = val & mask; mask 168 drivers/ptp/ptp_qoriq.c mask = ptp_qoriq->read(®s->ctrl_regs->tmr_temask); mask 169 drivers/ptp/ptp_qoriq.c mask &= ~ALM2EN; mask 170 drivers/ptp/ptp_qoriq.c ptp_qoriq->write(®s->ctrl_regs->tmr_temask, mask); mask 288 drivers/ptp/ptp_qoriq.c u32 bit, mask = 0; mask 316 drivers/ptp/ptp_qoriq.c mask = ptp_qoriq->read(®s->ctrl_regs->tmr_temask); mask 318 drivers/ptp/ptp_qoriq.c mask |= bit; mask 321 drivers/ptp/ptp_qoriq.c mask &= ~bit; mask 324 drivers/ptp/ptp_qoriq.c ptp_qoriq->write(®s->ctrl_regs->tmr_temask, mask); mask 72 drivers/pwm/pwm-hibvt.c u32 mask, u32 data) mask 78 drivers/pwm/pwm-hibvt.c value &= ~mask; mask 79 drivers/pwm/pwm-hibvt.c value |= (data & mask); mask 144 drivers/pwm/pwm-lp3943.c mux[index].mask, mask 514 drivers/pwm/pwm-meson.c channel->mux.mask = MISC_CLK_SEL_MASK; mask 58 drivers/pwm/pwm-mtk-disp.c u32 mask, u32 data) mask 64 drivers/pwm/pwm-mtk-disp.c value &= ~mask; mask 59 drivers/pwm/pwm-rcar.c static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data, mask 65 drivers/pwm/pwm-rcar.c value &= ~mask; mask 66 drivers/pwm/pwm-rcar.c value |= data & mask; mask 40 drivers/pwm/pwm-stm32-lp.c u32 val, mask, cfgr, presc = 0; mask 98 drivers/pwm/pwm-stm32-lp.c mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; mask 106 drivers/pwm/pwm-stm32-lp.c ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, mask 324 drivers/pwm/pwm-stm32.c u32 ccmr, mask, shift; mask 370 drivers/pwm/pwm-stm32.c mask = CCMR_CHANNEL_MASK << shift; mask 373 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); mask 375 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); mask 387 drivers/pwm/pwm-stm32.c u32 mask; mask 389 drivers/pwm/pwm-stm32.c mask = TIM_CCER_CC1P << (ch * 4); mask 391 drivers/pwm/pwm-stm32.c mask |= TIM_CCER_CC1NP << (ch * 4); mask 393 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_CCER, mask, mask 394 drivers/pwm/pwm-stm32.c polarity == PWM_POLARITY_NORMAL ? 0 : mask); mask 401 drivers/pwm/pwm-stm32.c u32 mask; mask 409 drivers/pwm/pwm-stm32.c mask = TIM_CCER_CC1E << (ch * 4); mask 411 drivers/pwm/pwm-stm32.c mask |= TIM_CCER_CC1NE << (ch * 4); mask 413 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); mask 426 drivers/pwm/pwm-stm32.c u32 mask; mask 429 drivers/pwm/pwm-stm32.c mask = TIM_CCER_CC1E << (ch * 4); mask 431 drivers/pwm/pwm-stm32.c mask |= TIM_CCER_CC1NE << (ch * 4); mask 433 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); mask 495 drivers/pwm/pwm-stm32.c u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF mask 508 drivers/pwm/pwm-stm32.c regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); mask 133 drivers/pwm/pwm-tiehrpwm.c static void ehrpwm_modify(void __iomem *base, unsigned int offset, u16 mask, mask 139 drivers/pwm/pwm-tiehrpwm.c val &= ~mask; mask 140 drivers/pwm/pwm-tiehrpwm.c val |= value & mask; mask 157 drivers/pwm/pwm-twl.c u8 val, mask, bits; mask 160 drivers/pwm/pwm-twl.c mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK; mask 163 drivers/pwm/pwm-twl.c mask = TWL4030_GPIO6_PWM0_MUTE_MASK; mask 175 drivers/pwm/pwm-twl.c twl->twl4030_pwm_mux &= ~mask; mask 176 drivers/pwm/pwm-twl.c twl->twl4030_pwm_mux |= (val & mask); mask 179 drivers/pwm/pwm-twl.c val &= ~mask; mask 195 drivers/pwm/pwm-twl.c u8 val, mask; mask 198 drivers/pwm/pwm-twl.c mask = TWL4030_GPIO7_VIBRASYNC_PWM1_MASK; mask 200 drivers/pwm/pwm-twl.c mask = TWL4030_GPIO6_PWM0_MUTE_MASK; mask 210 drivers/pwm/pwm-twl.c val &= ~mask; mask 211 drivers/pwm/pwm-twl.c val |= (twl->twl4030_pwm_mux & mask); mask 62 drivers/pwm/pwm-vt8500.c u32 mask = bitmask << (nr << 8); mask 64 drivers/pwm/pwm-vt8500.c while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) mask 69 drivers/pwm/pwm-vt8500.c mask); mask 54 drivers/pwm/pwm-zx.c unsigned int offset, u32 mask, u32 value) mask 59 drivers/pwm/pwm-zx.c data &= ~mask; mask 60 drivers/pwm/pwm-zx.c data |= value & mask; mask 1512 drivers/rapidio/devices/rio_mport_cdev.c if ((msg->em.comptag & filter->mask) < filter->low || mask 1513 drivers/rapidio/devices/rio_mport_cdev.c (msg->em.comptag & filter->mask) > filter->high) mask 1602 drivers/rapidio/devices/rio_mport_cdev.c if ((a->mask == b->mask) && (a->low == b->low) && (a->high == b->high)) mask 270 drivers/rapidio/rio-scan.c u32 mask = RIO_OPS_READ | RIO_OPS_WRITE | RIO_OPS_ATOMIC_TST_SWP | RIO_OPS_ATOMIC_INC | RIO_OPS_ATOMIC_DEC | RIO_OPS_ATOMIC_SET | RIO_OPS_ATOMIC_CLR; mask 272 drivers/rapidio/rio-scan.c return !!((src_ops | dst_ops) & mask); mask 1834 drivers/rapidio/rio.c dma_cap_mask_t mask; mask 1836 drivers/rapidio/rio.c dma_cap_zero(mask); mask 1837 drivers/rapidio/rio.c dma_cap_set(DMA_SLAVE, mask); mask 1838 drivers/rapidio/rio.c return dma_request_channel(mask, rio_chan_filter, mport); mask 316 drivers/regulator/ab8500.c u8 bank, reg, mask, val; mask 328 drivers/regulator/ab8500.c mask = info->mode_mask; mask 332 drivers/regulator/ab8500.c mask = info->update_mask; mask 374 drivers/regulator/ab8500.c bank, reg, mask, val); mask 385 drivers/regulator/ab8500.c mask, val); mask 1068 drivers/regulator/ab8500.c u8 mask; mask 1075 drivers/regulator/ab8500.c .mask = _mask, \ mask 55 drivers/regulator/as3711-regulator.c low_noise_bit = fast_bit << 4, mask = fast_bit | low_noise_bit; mask 62 drivers/regulator/as3711-regulator.c if ((val & mask) == mask) mask 65 drivers/regulator/as3711-regulator.c if ((val & mask) == low_noise_bit) mask 68 drivers/regulator/as3711-regulator.c if (!(val & mask)) mask 371 drivers/regulator/axp20x-regulator.c u8 reg, mask, enable, cfg = 0xff; mask 381 drivers/regulator/axp20x-regulator.c mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | mask 393 drivers/regulator/axp20x-regulator.c mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | mask 433 drivers/regulator/axp20x-regulator.c return regmap_update_bits(axp20x->regmap, reg, mask, cfg); mask 1102 drivers/regulator/axp20x-regulator.c unsigned int mask; mask 1110 drivers/regulator/axp20x-regulator.c mask = AXP20X_WORKMODE_DCDC2_MASK; mask 1112 drivers/regulator/axp20x-regulator.c mask = AXP20X_WORKMODE_DCDC3_MASK; mask 1114 drivers/regulator/axp20x-regulator.c workmode <<= ffs(mask) - 1; mask 1130 drivers/regulator/axp20x-regulator.c mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1); mask 1138 drivers/regulator/axp20x-regulator.c mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); mask 1146 drivers/regulator/axp20x-regulator.c mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1); mask 1156 drivers/regulator/axp20x-regulator.c return regmap_update_bits(rdev->regmap, reg, mask, workmode); mask 316 drivers/regulator/bd718x7-regulator.c unsigned int mask; mask 339 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO5_VRMON80, mask 347 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO6_VRMON80, mask 503 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 527 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 554 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 581 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 603 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 627 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 653 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 675 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 698 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 721 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 747 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 772 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 799 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 823 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 847 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 871 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 898 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 922 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 944 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 968 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_BUCK_SEL, mask 994 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1016 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1039 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1062 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1087 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1114 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1139 drivers/regulator/bd718x7-regulator.c .mask = BD718XX_LDO_SEL, mask 1258 drivers/regulator/bd718x7-regulator.c r->init.mask, r->init.val); mask 1269 drivers/regulator/bd718x7-regulator.c r->additional_inits[j].mask, mask 104 drivers/regulator/da903x.c uint8_t val, mask; mask 110 drivers/regulator/da903x.c mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; mask 112 drivers/regulator/da903x.c return da903x_update(da9034_dev, info->vol_reg, val, mask); mask 119 drivers/regulator/da903x.c uint8_t val, mask; mask 129 drivers/regulator/da903x.c mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; mask 130 drivers/regulator/da903x.c val = (val & mask) >> info->vol_shift; mask 173 drivers/regulator/da903x.c uint8_t val, mask; mask 177 drivers/regulator/da903x.c mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; mask 179 drivers/regulator/da903x.c mask |= DA9030_LDO_UNLOCK_MASK; mask 182 drivers/regulator/da903x.c ret = da903x_update(da903x_dev, info->vol_reg, val, mask); mask 186 drivers/regulator/da903x.c return da903x_update(da903x_dev, info->vol_reg, val, mask); mask 236 drivers/regulator/da903x.c uint8_t val, mask; mask 240 drivers/regulator/da903x.c mask = ((1 << info->vol_nbits) - 1) << info->vol_shift; mask 242 drivers/regulator/da903x.c ret = da903x_update(da9034_dev, info->vol_reg, val, mask); mask 64 drivers/regulator/da9055-regulator.c int mask; mask 92 drivers/regulator/da9055-regulator.c switch ((ret & info->mode.mask) >> info->mode.shift) { mask 127 drivers/regulator/da9055-regulator.c info->mode.mask, val); mask 395 drivers/regulator/da9055-regulator.c .mask = (mbits),\ mask 53 drivers/regulator/lm363x-regulator.c unsigned int val, addr, mask; mask 58 drivers/regulator/lm363x-regulator.c mask = LM3631_ENTIME_CONT_MASK; mask 62 drivers/regulator/lm363x-regulator.c mask = LM3631_ENTIME_MASK; mask 66 drivers/regulator/lm363x-regulator.c mask = LM3631_ENTIME_MASK; mask 70 drivers/regulator/lm363x-regulator.c mask = LM3631_ENTIME_MASK; mask 79 drivers/regulator/lm363x-regulator.c val = (val & mask) >> LM3631_ENTIME_SHIFT; mask 118 drivers/regulator/lochnagar-regulator.c int mask = LOCHNAGAR2_P1_MICBIAS_SRC_MASK << shift; mask 127 drivers/regulator/lochnagar-regulator.c mask, val << shift); mask 27 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val); mask 110 drivers/regulator/lp3971.c u16 mask = 1 << (1 + ldo); mask 114 drivers/regulator/lp3971.c return (val & mask) != 0; mask 121 drivers/regulator/lp3971.c u16 mask = 1 << (1 + ldo); mask 123 drivers/regulator/lp3971.c return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, mask); mask 130 drivers/regulator/lp3971.c u16 mask = 1 << (1 + ldo); mask 132 drivers/regulator/lp3971.c return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, 0); mask 172 drivers/regulator/lp3971.c u16 mask = 1 << (buck * 2); mask 176 drivers/regulator/lp3971.c return (val & mask) != 0; mask 183 drivers/regulator/lp3971.c u16 mask = 1 << (buck * 2); mask 185 drivers/regulator/lp3971.c return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, mask); mask 192 drivers/regulator/lp3971.c u16 mask = 1 << (buck * 2); mask 194 drivers/regulator/lp3971.c return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, 0); mask 356 drivers/regulator/lp3971.c static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) mask 365 drivers/regulator/lp3971.c tmp = (tmp & ~mask) | val; mask 202 drivers/regulator/lp3972.c static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val) mask 211 drivers/regulator/lp3972.c tmp = (tmp & ~mask) | val; mask 225 drivers/regulator/lp3972.c u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo); mask 229 drivers/regulator/lp3972.c return !!(val & mask); mask 236 drivers/regulator/lp3972.c u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo); mask 239 drivers/regulator/lp3972.c mask, mask); mask 246 drivers/regulator/lp3972.c u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo); mask 249 drivers/regulator/lp3972.c mask, 0); mask 256 drivers/regulator/lp3972.c u16 mask = LP3972_LDO_VOL_MASK(ldo); mask 260 drivers/regulator/lp3972.c val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask; mask 318 drivers/regulator/lp3972.c u16 mask = 1 << (buck * 2); mask 322 drivers/regulator/lp3972.c return !!(val & mask); mask 329 drivers/regulator/lp3972.c u16 mask = 1 << (buck * 2); mask 333 drivers/regulator/lp3972.c mask, mask); mask 341 drivers/regulator/lp3972.c u16 mask = 1 << (buck * 2); mask 345 drivers/regulator/lp3972.c mask, 0); mask 177 drivers/regulator/lp872x.c unsigned int mask, u8 data) mask 179 drivers/regulator/lp872x.c return regmap_update_bits(lp->regmap, addr, mask, data); mask 185 drivers/regulator/lp872x.c u8 val, mask, shift; mask 192 drivers/regulator/lp872x.c mask = LP8720_TIMESTEP_M; mask 198 drivers/regulator/lp872x.c mask = LP8725_TIMESTEP_M; mask 211 drivers/regulator/lp872x.c val = (val & mask) >> shift; mask 321 drivers/regulator/lp872x.c u8 addr, mask = LP872X_VOUT_M; mask 331 drivers/regulator/lp872x.c return lp872x_update_bits(lp, addr, mask, selector); mask 356 drivers/regulator/lp872x.c u8 addr, mask, shift, val; mask 361 drivers/regulator/lp872x.c mask = LP8720_BUCK_FPWM_M; mask 366 drivers/regulator/lp872x.c mask = LP8725_BUCK1_FPWM_M; mask 371 drivers/regulator/lp872x.c mask = LP8725_BUCK2_FPWM_M; mask 385 drivers/regulator/lp872x.c return lp872x_update_bits(lp, addr, mask, val); mask 392 drivers/regulator/lp872x.c u8 addr, mask, val; mask 398 drivers/regulator/lp872x.c mask = LP8720_BUCK_FPWM_M; mask 402 drivers/regulator/lp872x.c mask = LP8725_BUCK1_FPWM_M; mask 406 drivers/regulator/lp872x.c mask = LP8725_BUCK2_FPWM_M; mask 416 drivers/regulator/lp872x.c return val & mask ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL; mask 681 drivers/regulator/lp872x.c u8 mask[] = { LP8720_EXT_DVS_M, LP8725_DVS1_M | LP8725_DVS2_M }; mask 703 drivers/regulator/lp872x.c return lp872x_update_bits(lp, LP872X_GENERAL_CFG, mask[lp->chipid], mask 84 drivers/regulator/lp8755.c unsigned int mask, unsigned int val) mask 86 drivers/regulator/lp8755.c return regmap_update_bits(pchip->regmap, reg, mask, val); mask 166 drivers/regulator/lp8788-buck.c u8 val, mask; mask 170 drivers/regulator/lp8788-buck.c mask = LP8788_BUCK1_DVS_SEL_M; mask 173 drivers/regulator/lp8788-buck.c mask = LP8788_BUCK2_DVS_SEL_M; mask 181 drivers/regulator/lp8788-buck.c return val & mask ? REGISTER : EXTPIN; mask 309 drivers/regulator/lp8788-buck.c u8 mask, val; mask 311 drivers/regulator/lp8788-buck.c mask = BUCK_FPWM_MASK(id); mask 323 drivers/regulator/lp8788-buck.c return lp8788_update_bits(buck->lp, LP8788_BUCK_PWM, mask, val); mask 462 drivers/regulator/lp8788-buck.c u8 mask[] = { LP8788_BUCK1_DVS_SEL_M, LP8788_BUCK2_DVS_SEL_M }; mask 481 drivers/regulator/lp8788-buck.c return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id], mask 485 drivers/regulator/lp8788-buck.c return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id], mask 131 drivers/regulator/ltc3589.c int mask, bit = 0; mask 134 drivers/regulator/ltc3589.c mask = rdev->desc->apply_bit << 1; mask 137 drivers/regulator/ltc3589.c bit = mask; /* Select DTV2 */ mask 139 drivers/regulator/ltc3589.c mask |= rdev->desc->apply_bit; mask 141 drivers/regulator/ltc3589.c return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit); mask 95 drivers/regulator/ltc3676.c int mask, val; mask 100 drivers/regulator/ltc3676.c mask = LTC3676_DVBxA_REF_SELECT; mask 115 drivers/regulator/ltc3676.c mask, val); mask 169 drivers/regulator/max77620-regulator.c unsigned int mask = 0; mask 185 drivers/regulator/max77620-regulator.c mask |= MAX77620_FPS_PU_PERIOD_MASK; mask 191 drivers/regulator/max77620-regulator.c mask |= MAX77620_FPS_PD_PERIOD_MASK; mask 194 drivers/regulator/max77620-regulator.c if (mask) { mask 196 drivers/regulator/max77620-regulator.c mask, val); mask 211 drivers/regulator/max77620-regulator.c u8 mask = rinfo->power_mode_mask; mask 225 drivers/regulator/max77620-regulator.c ret = regmap_update_bits(pmic->rmap, addr, mask, power_mode << shift); mask 241 drivers/regulator/max77620-regulator.c u8 mask = rinfo->power_mode_mask; mask 261 drivers/regulator/max77620-regulator.c return (val & mask) >> shift; mask 320 drivers/regulator/max77620-regulator.c u8 mask; mask 332 drivers/regulator/max77620-regulator.c mask = MAX77620_SD_SR_MASK; mask 338 drivers/regulator/max77620-regulator.c mask = MAX77620_LDO_SLEW_RATE_MASK; mask 341 drivers/regulator/max77620-regulator.c ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val); mask 356 drivers/regulator/max77620-regulator.c u8 val, mask; mask 363 drivers/regulator/max77620-regulator.c mask = MAX20024_SD_CFG1_MPOK_MASK; mask 365 drivers/regulator/max77620-regulator.c mask = MAX20024_LDO_CFG2_MPOK_MASK; mask 367 drivers/regulator/max77620-regulator.c val = rpdata->power_ok ? mask : 0; mask 370 drivers/regulator/max77620-regulator.c mask, val); mask 73 drivers/regulator/max8660.c static int max8660_write(struct max8660 *max8660, u8 reg, u8 mask, u8 val) mask 80 drivers/regulator/max8660.c u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; mask 102 drivers/regulator/max8660.c u8 mask = (rdev_get_id(rdev) == MAX8660_V3) ? 1 : 4; mask 104 drivers/regulator/max8660.c return !!(val & mask); mask 118 drivers/regulator/max8660.c u8 mask = (rdev_get_id(rdev) == MAX8660_V3) ? ~1 : ~4; mask 120 drivers/regulator/max8660.c return max8660_write(max8660, MAX8660_OVER1, mask, 0); mask 200 drivers/regulator/max8660.c u8 mask = (rdev_get_id(rdev) == MAX8660_V6) ? 2 : 4; mask 202 drivers/regulator/max8660.c return !!(val & mask); mask 216 drivers/regulator/max8660.c u8 mask = (rdev_get_id(rdev) == MAX8660_V6) ? ~2 : ~4; mask 218 drivers/regulator/max8660.c return max8660_write(max8660, MAX8660_OVER2, mask, 0); mask 46 drivers/regulator/max8925-regulator.c unsigned char mask = rdev->desc->n_voltages - 1; mask 48 drivers/regulator/max8925-regulator.c return max8925_set_bits(info->i2c, info->vol_reg, mask, selector); mask 54 drivers/regulator/max8925-regulator.c unsigned char data, mask; mask 60 drivers/regulator/max8925-regulator.c mask = rdev->desc->n_voltages - 1; mask 61 drivers/regulator/max8925-regulator.c data = ret & mask; mask 105 drivers/regulator/max8925-regulator.c unsigned char data, mask; mask 112 drivers/regulator/max8925-regulator.c mask = 3 << SD1_DVM_SHIFT; mask 114 drivers/regulator/max8925-regulator.c return max8925_set_bits(info->i2c, info->enable_reg, mask, data); mask 169 drivers/regulator/max8997-regulator.c int *reg, int *mask, int *pattern) mask 176 drivers/regulator/max8997-regulator.c *mask = 0xC0; mask 181 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 186 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 191 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 196 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 201 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 206 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 211 drivers/regulator/max8997-regulator.c *mask = 0x01; mask 216 drivers/regulator/max8997-regulator.c *mask = 0x01 << (rid - MAX8997_EN32KHZ_AP); mask 221 drivers/regulator/max8997-regulator.c *mask = 0x80; mask 226 drivers/regulator/max8997-regulator.c *mask = 0x40 << (rid - MAX8997_ESAFEOUT1); mask 231 drivers/regulator/max8997-regulator.c *mask = 0x40; mask 246 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; mask 249 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); mask 257 drivers/regulator/max8997-regulator.c return (val & mask) == pattern; mask 264 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; mask 266 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); mask 270 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, pattern, mask); mask 277 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; mask 279 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); mask 283 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, ~pattern, mask); mask 291 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask = 0x3f; mask 324 drivers/regulator/max8997-regulator.c mask = 0x3; mask 329 drivers/regulator/max8997-regulator.c mask = 0xf; mask 334 drivers/regulator/max8997-regulator.c mask = 0xf; mask 339 drivers/regulator/max8997-regulator.c mask = 0xf; mask 347 drivers/regulator/max8997-regulator.c *_mask = mask; mask 356 drivers/regulator/max8997-regulator.c int reg, shift, mask, ret; mask 359 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); mask 368 drivers/regulator/max8997-regulator.c val &= mask; mask 403 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask, ret = 0; mask 409 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); mask 439 drivers/regulator/max8997-regulator.c ret = max8997_update_reg(i2c, reg, val << shift, mask); mask 455 drivers/regulator/max8997-regulator.c int i, reg, shift, mask, ret; mask 480 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); mask 484 drivers/regulator/max8997-regulator.c ret = max8997_update_reg(i2c, reg, i << shift, mask << shift); mask 696 drivers/regulator/max8997-regulator.c int reg, shift = 0, mask, ret; mask 701 drivers/regulator/max8997-regulator.c ret = max8997_get_voltage_register(rdev, ®, &shift, &mask); mask 705 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, selector << shift, mask << shift); mask 712 drivers/regulator/max8997-regulator.c int ret, reg, mask, pattern; mask 715 drivers/regulator/max8997-regulator.c ret = max8997_get_enable_register(rdev, ®, &mask, &pattern); mask 726 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, 0x40, mask); mask 730 drivers/regulator/max8997-regulator.c rdev->desc->name, max8997->saved_states[rid] & mask, mask 731 drivers/regulator/max8997-regulator.c (~pattern) & mask); mask 732 drivers/regulator/max8997-regulator.c return max8997_update_reg(i2c, reg, ~pattern, mask); mask 122 drivers/regulator/max8998.c int reg, shift = 0, mask = 0xff; mask 127 drivers/regulator/max8998.c mask = 0xf; mask 138 drivers/regulator/max8998.c mask = 0xf; mask 148 drivers/regulator/max8998.c mask = 0x7; mask 151 drivers/regulator/max8998.c mask = 0x1f; mask 175 drivers/regulator/max8998.c *_mask = mask; mask 184 drivers/regulator/max8998.c int reg, shift = 0, mask, ret; mask 187 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); mask 196 drivers/regulator/max8998.c val &= mask; mask 206 drivers/regulator/max8998.c int reg, shift = 0, mask, ret; mask 208 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); mask 212 drivers/regulator/max8998.c ret = max8998_update_reg(i2c, reg, selector<<shift, mask<<shift); mask 235 drivers/regulator/max8998.c int reg, shift = 0, mask, ret, j; mask 238 drivers/regulator/max8998.c ret = max8998_get_voltage_register(rdev, ®, &shift, &mask); mask 274 drivers/regulator/max8998.c &mask); mask 309 drivers/regulator/max8998.c ®, &shift, &mask); mask 324 drivers/regulator/max8998.c mask<<shift); mask 294 drivers/regulator/mc13783-regulator.c static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask, mask 301 drivers/regulator/mc13783-regulator.c BUG_ON(val & ~mask); mask 310 drivers/regulator/mc13783-regulator.c (priv->powermisc_pwgt_state & ~mask) | val; mask 314 drivers/regulator/mc13783-regulator.c valread = (valread & ~mask) | val; mask 302 drivers/regulator/mc13892-regulator.c static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask, mask 309 drivers/regulator/mc13892-regulator.c BUG_ON(val & ~mask); mask 318 drivers/regulator/mc13892-regulator.c (priv->powermisc_pwgt_state & ~mask) | val; mask 322 drivers/regulator/mc13892-regulator.c valread = (valread & ~mask) | val; mask 338 drivers/regulator/mc13892-regulator.c u32 mask = mc13892_regulators[id].enable_bit; mask 347 drivers/regulator/mc13892-regulator.c mask |= MC13892_POWERMISC_GPO4ADINEN; mask 349 drivers/regulator/mc13892-regulator.c return mc13892_powermisc_rmw(priv, mask, en_val); mask 441 drivers/regulator/mc13892-regulator.c int volt, mask, id = rdev_get_id(rdev); mask 446 drivers/regulator/mc13892-regulator.c mask = mc13892_regulators[id].vsel_mask; mask 464 drivers/regulator/mc13892-regulator.c mask |= MC13892_SWITCHERS0_SWxHI; mask 476 drivers/regulator/mc13892-regulator.c mask, reg_value); mask 248 drivers/regulator/pfuze100-regulator.c #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ mask 259 drivers/regulator/pfuze100-regulator.c .vsel_mask = (mask), \ mask 285 drivers/regulator/pfuze100-regulator.c #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ mask 296 drivers/regulator/pfuze100-regulator.c .vsel_mask = (mask), \ mask 22 drivers/regulator/qcom_rpm-regulator.c unsigned int mask; mask 45 drivers/regulator/qcom_rpm-regulator.c (((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3) mask 193 drivers/regulator/qcom_rpm-regulator.c if (WARN_ON((value << req->shift) & ~req->mask)) mask 196 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] &= ~req->mask; mask 215 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 242 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 274 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 293 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 312 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 331 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 350 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 369 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 394 drivers/regulator/qcom_rpm-regulator.c int max_mA = req->mask >> req->shift; mask 397 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0) mask 644 drivers/regulator/qcom_rpm-regulator.c if (req->mask == 0 || (value << req->shift) & ~req->mask) mask 647 drivers/regulator/qcom_rpm-regulator.c vreg->val[req->word] &= ~req->mask; mask 707 drivers/regulator/qcom_rpm-regulator.c if (vreg->parts->freq.mask) { mask 713 drivers/regulator/qcom_rpm-regulator.c if (vreg->parts->pm.mask) { mask 724 drivers/regulator/qcom_rpm-regulator.c if (vreg->parts->fm.mask) { mask 548 drivers/regulator/qcom_spmi-regulator.c u8 mask) mask 550 drivers/regulator/qcom_spmi-regulator.c return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); mask 958 drivers/regulator/qcom_spmi-regulator.c u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; mask 962 drivers/regulator/qcom_spmi-regulator.c val = mask; mask 964 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); mask 1020 drivers/regulator/qcom_spmi-regulator.c u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; mask 1035 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); mask 1042 drivers/regulator/qcom_spmi-regulator.c u8 mask = SPMI_FTSMPS426_MODE_MASK; mask 1059 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); mask 1079 drivers/regulator/qcom_spmi-regulator.c unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; mask 1082 drivers/regulator/qcom_spmi-regulator.c mask, mask); mask 1088 drivers/regulator/qcom_spmi-regulator.c unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; mask 1091 drivers/regulator/qcom_spmi-regulator.c mask, mask); mask 1100 drivers/regulator/qcom_spmi-regulator.c u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | mask 1115 drivers/regulator/qcom_spmi-regulator.c return spmi_vreg_update_bits(vreg, current_reg, reg, mask); mask 1627 drivers/regulator/qcom_spmi-regulator.c u8 ctrl_reg[8], reg, mask; mask 1688 drivers/regulator/qcom_spmi-regulator.c mask = SPMI_VS_SOFT_START_SEL_MASK; mask 1691 drivers/regulator/qcom_spmi-regulator.c reg, mask); mask 245 drivers/regulator/rk808-regulator.c unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask; mask 251 drivers/regulator/rk808-regulator.c tmp = val & ~mask; mask 252 drivers/regulator/rk808-regulator.c old_sel = val & mask; mask 253 drivers/regulator/rk808-regulator.c old_sel >>= ffs(mask) - 1; mask 263 drivers/regulator/rk808-regulator.c val = old_sel << (ffs(mask) - 1); mask 276 drivers/regulator/rk808-regulator.c sel <<= ffs(mask) - 1; mask 129 drivers/regulator/ti-abb-regulator.c static inline u32 ti_abb_rmw(u32 mask, u32 value, void __iomem *reg) mask 134 drivers/regulator/ti-abb-regulator.c val &= ~mask; mask 135 drivers/regulator/ti-abb-regulator.c val |= (value << __ffs(mask)) & mask; mask 139 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_set_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) mask 152 drivers/regulator/tps6507x-regulator.c data |= mask; mask 162 drivers/regulator/tps6507x-regulator.c static int tps6507x_pmic_clear_bits(struct tps6507x_pmic *tps, u8 reg, u8 mask) mask 175 drivers/regulator/tps6507x-regulator.c data &= ~mask; mask 262 drivers/regulator/tps6507x-regulator.c u8 reg, mask; mask 267 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 274 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 281 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 285 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_REG_LDO_CTRL1_LDO1_MASK; mask 289 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_REG_DEFLDO2_LDO2_MASK; mask 299 drivers/regulator/tps6507x-regulator.c data &= mask; mask 308 drivers/regulator/tps6507x-regulator.c u8 reg, mask; mask 313 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 320 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 327 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_DEFDCDCX_DCDC_MASK; mask 331 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_REG_LDO_CTRL1_LDO1_MASK; mask 335 drivers/regulator/tps6507x-regulator.c mask = TPS6507X_REG_DEFLDO2_LDO2_MASK; mask 345 drivers/regulator/tps6507x-regulator.c data &= ~mask; mask 123 drivers/regulator/tps6524x-regulator.c int mask; mask 237 drivers/regulator/tps6524x-regulator.c static int __rmw_reg(struct tps6524x *hw, int reg, int mask, int val) mask 245 drivers/regulator/tps6524x-regulator.c ret &= ~mask; mask 253 drivers/regulator/tps6524x-regulator.c static int rmw_protect(struct tps6524x *hw, int reg, int mask, int val) mask 265 drivers/regulator/tps6524x-regulator.c ret = __rmw_reg(hw, reg, mask, val); mask 289 drivers/regulator/tps6524x-regulator.c return (tmp >> field->shift) & field->mask; mask 295 drivers/regulator/tps6524x-regulator.c if (val & ~field->mask) mask 299 drivers/regulator/tps6524x-regulator.c field->mask << field->shift, mask 372 drivers/regulator/tps6524x-regulator.c { .reg = (_reg), .mask = (_mask), .shift = (_shift), } mask 162 drivers/regulator/wm831x-ldo.c int mask = 1 << rdev_get_id(rdev); mask 169 drivers/regulator/wm831x-ldo.c if (!(ret & mask)) mask 176 drivers/regulator/wm831x-ldo.c if (ret & mask) mask 385 drivers/regulator/wm831x-ldo.c int mask = 1 << rdev_get_id(rdev); mask 392 drivers/regulator/wm831x-ldo.c if (!(ret & mask)) mask 399 drivers/regulator/wm831x-ldo.c if (ret & mask) mask 544 drivers/regulator/wm831x-ldo.c int mask = 1 << rdev_get_id(rdev); mask 551 drivers/regulator/wm831x-ldo.c if (ret & mask) mask 768 drivers/regulator/wm8350-regulator.c u16 mask, sleep, active, force; mask 789 drivers/regulator/wm8350-regulator.c mask = 1 << (dcdc - WM8350_DCDC_1); mask 790 drivers/regulator/wm8350-regulator.c active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask; mask 792 drivers/regulator/wm8350-regulator.c sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask; mask 795 drivers/regulator/wm8350-regulator.c mask, active, sleep, force); mask 1077 drivers/remoteproc/qcom_q6v5_mss.c unsigned long mask = BIT((unsigned long)segment->priv); mask 1097 drivers/remoteproc/qcom_q6v5_mss.c qproc->dump_segment_mask |= mask; mask 40 drivers/remoteproc/stm32_rproc.c u32 mask; mask 353 drivers/remoteproc/stm32_rproc.c hold_boot.mask, val); mask 394 drivers/remoteproc/stm32_rproc.c ddata->pdds.mask, 0); mask 438 drivers/remoteproc/stm32_rproc.c ddata->pdds.mask, 1); mask 503 drivers/remoteproc/stm32_rproc.c err = of_property_read_u32_index(np, prop, 2, &syscon->mask); mask 556 drivers/remoteproc/stm32_rproc.c ddata->secured_soc = tzen & tz.mask; mask 27 drivers/reset/hisilicon/reset-hi3660.c unsigned int mask = BIT(idx & 0x1f); mask 30 drivers/reset/hisilicon/reset-hi3660.c return regmap_write(rc->map, offset, mask); mask 32 drivers/reset/hisilicon/reset-hi3660.c return regmap_write(rc->map, offset + 4, mask); mask 49 drivers/reset/reset-a10sr.c u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); mask 52 drivers/reset/reset-a10sr.c return regmap_update_bits(a10r->regmap, index, mask, assert ? 0 : mask); mask 73 drivers/reset/reset-a10sr.c u8 mask = ALTR_A10SR_REG_BIT_MASK(offset); mask 81 drivers/reset/reset-a10sr.c return !!(value & mask); mask 41 drivers/reset/reset-berlin.c int mask = BIT(id & 0x1f); mask 43 drivers/reset/reset-berlin.c regmap_write(priv->regmap, offset, mask); mask 67 drivers/reset/reset-pistachio.c u32 mask; mask 74 drivers/reset/reset-pistachio.c mask = BIT(shift); mask 77 drivers/reset/reset-pistachio.c mask, mask); mask 84 drivers/reset/reset-pistachio.c u32 mask; mask 91 drivers/reset/reset-pistachio.c mask = BIT(shift); mask 94 drivers/reset/reset-pistachio.c mask, 0); mask 79 drivers/reset/reset-ti-syscon.c unsigned int mask, value; mask 89 drivers/reset/reset-ti-syscon.c mask = BIT(control->assert_bit); mask 90 drivers/reset/reset-ti-syscon.c value = (control->flags & ASSERT_SET) ? mask : 0x0; mask 92 drivers/reset/reset-ti-syscon.c return regmap_update_bits(data->regmap, control->assert_offset, mask, value); mask 110 drivers/reset/reset-ti-syscon.c unsigned int mask, value; mask 120 drivers/reset/reset-ti-syscon.c mask = BIT(control->deassert_bit); mask 121 drivers/reset/reset-ti-syscon.c value = (control->flags & DEASSERT_SET) ? mask : 0x0; mask 123 drivers/reset/reset-ti-syscon.c return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); mask 260 drivers/reset/reset-uniphier.c unsigned int mask, val; mask 265 drivers/reset/reset-uniphier.c mask = BIT(p->bit); mask 268 drivers/reset/reset-uniphier.c val = mask; mask 270 drivers/reset/reset-uniphier.c val = ~mask; mask 275 drivers/reset/reset-uniphier.c return regmap_write_bits(priv->regmap, p->reg, mask, val); mask 687 drivers/rpmsg/qcom_smd.c unsigned mask = channel->fifo_size - 1; mask 692 drivers/rpmsg/qcom_smd.c return mask - ((head - tail) & mask); mask 982 drivers/rpmsg/qcom_smd.c __poll_t mask = 0; mask 987 drivers/rpmsg/qcom_smd.c mask |= EPOLLOUT | EPOLLWRNORM; mask 989 drivers/rpmsg/qcom_smd.c return mask; mask 261 drivers/rpmsg/rpmsg_char.c __poll_t mask = 0; mask 269 drivers/rpmsg/rpmsg_char.c mask |= EPOLLIN | EPOLLRDNORM; mask 271 drivers/rpmsg/rpmsg_char.c mask |= rpmsg_poll(eptdev->ept, filp, wait); mask 273 drivers/rpmsg/rpmsg_char.c return mask; mask 50 drivers/rtc/rtc-88pm80x.c int mask; mask 52 drivers/rtc/rtc-88pm80x.c mask = PM800_ALARM | PM800_ALARM_WAKEUP; mask 53 drivers/rtc/rtc-88pm80x.c regmap_update_bits(info->map, PM800_RTC_CONTROL, mask | PM800_ALARM1_EN, mask 54 drivers/rtc/rtc-88pm80x.c mask); mask 176 drivers/rtc/rtc-88pm80x.c int mask; mask 207 drivers/rtc/rtc-88pm80x.c mask = PM800_ALARM | PM800_ALARM_WAKEUP | PM800_ALARM1_EN; mask 208 drivers/rtc/rtc-88pm80x.c regmap_update_bits(info->map, PM800_RTC_CONTROL, mask, mask); mask 210 drivers/rtc/rtc-88pm80x.c mask = PM800_ALARM | PM800_ALARM_WAKEUP | PM800_ALARM1_EN; mask 211 drivers/rtc/rtc-88pm80x.c regmap_update_bits(info->map, PM800_RTC_CONTROL, mask, mask 60 drivers/rtc/rtc-88pm860x.c int mask; mask 62 drivers/rtc/rtc-88pm860x.c mask = ALARM | ALARM_WAKEUP; mask 63 drivers/rtc/rtc-88pm860x.c pm860x_set_bits(info->i2c, PM8607_RTC1, mask | ALARM_EN, mask); mask 196 drivers/rtc/rtc-88pm860x.c int mask; mask 226 drivers/rtc/rtc-88pm860x.c mask = ALARM | ALARM_WAKEUP | ALARM_EN; mask 227 drivers/rtc/rtc-88pm860x.c pm860x_set_bits(info->i2c, PM8607_RTC1, mask, mask); mask 229 drivers/rtc/rtc-88pm860x.c mask = ALARM | ALARM_WAKEUP | ALARM_EN; mask 230 drivers/rtc/rtc-88pm860x.c pm860x_set_bits(info->i2c, PM8607_RTC1, mask, mask 136 drivers/rtc/rtc-ab-b5ze-s3.c static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00, mask 148 drivers/rtc/rtc-ab-b5ze-s3.c if (regs[i] & mask[i]) /* check if bits are cleared */ mask 510 drivers/rtc/rtc-ab-b5ze-s3.c u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1; mask 524 drivers/rtc/rtc-ab-b5ze-s3.c mask, ABB5ZES3_REG_TIM_CLK_TAC1); mask 608 drivers/rtc/rtc-ab-b5ze-s3.c u8 mask; mask 619 drivers/rtc/rtc-ab-b5ze-s3.c mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 | mask 623 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask, mask 638 drivers/rtc/rtc-ab-b5ze-s3.c mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE | mask 640 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask); mask 648 drivers/rtc/rtc-ab-b5ze-s3.c mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE | mask 651 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0); mask 662 drivers/rtc/rtc-ab-b5ze-s3.c mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE | mask 666 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0); mask 679 drivers/rtc/rtc-ab-b5ze-s3.c mask = (ABB5ZES3_REG_CTRL3_PM0 | ABB5ZES3_REG_CTRL3_PM1 | mask 682 drivers/rtc/rtc-ab-b5ze-s3.c ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0); mask 57 drivers/rtc/rtc-at91rm9200.c static void at91_rtc_write_ier(u32 mask) mask 62 drivers/rtc/rtc-at91rm9200.c at91_rtc_shadow_imr |= mask; mask 63 drivers/rtc/rtc-at91rm9200.c at91_rtc_write(AT91_RTC_IER, mask); mask 67 drivers/rtc/rtc-at91rm9200.c static void at91_rtc_write_idr(u32 mask) mask 72 drivers/rtc/rtc-at91rm9200.c at91_rtc_write(AT91_RTC_IDR, mask); mask 85 drivers/rtc/rtc-at91rm9200.c at91_rtc_shadow_imr &= ~mask; mask 92 drivers/rtc/rtc-at91rm9200.c u32 mask; mask 96 drivers/rtc/rtc-at91rm9200.c mask = at91_rtc_shadow_imr; mask 99 drivers/rtc/rtc-at91rm9200.c mask = at91_rtc_read(AT91_RTC_IMR); mask 102 drivers/rtc/rtc-at91rm9200.c return mask; mask 133 drivers/rtc/rtc-cmos.c static inline int hpet_mask_rtc_irq_bit(unsigned long mask) mask 138 drivers/rtc/rtc-cmos.c static inline int hpet_set_rtc_irq_bit(unsigned long mask) mask 338 drivers/rtc/rtc-cmos.c static void cmos_irq_enable(struct cmos_rtc *cmos, unsigned char mask) mask 348 drivers/rtc/rtc-cmos.c rtc_control |= mask; mask 351 drivers/rtc/rtc-cmos.c hpet_set_rtc_irq_bit(mask); mask 353 drivers/rtc/rtc-cmos.c if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) { mask 361 drivers/rtc/rtc-cmos.c static void cmos_irq_disable(struct cmos_rtc *cmos, unsigned char mask) mask 366 drivers/rtc/rtc-cmos.c rtc_control &= ~mask; mask 369 drivers/rtc/rtc-cmos.c hpet_mask_rtc_irq_bit(mask); mask 371 drivers/rtc/rtc-cmos.c if ((mask & RTC_AIE) && cmos_use_acpi_alarm()) { mask 986 drivers/rtc/rtc-cmos.c unsigned char mask; mask 989 drivers/rtc/rtc-cmos.c mask = RTC_IRQMASK & ~RTC_AIE; mask 991 drivers/rtc/rtc-cmos.c mask = RTC_IRQMASK; mask 992 drivers/rtc/rtc-cmos.c tmp &= ~mask; mask 995 drivers/rtc/rtc-cmos.c hpet_mask_rtc_irq_bit(mask); mask 1089 drivers/rtc/rtc-cmos.c unsigned char mask; mask 1099 drivers/rtc/rtc-cmos.c mask = CMOS_READ(RTC_INTR_FLAGS); mask 1100 drivers/rtc/rtc-cmos.c mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; mask 1101 drivers/rtc/rtc-cmos.c if (!use_hpet_alarm() || !is_intr(mask)) mask 1107 drivers/rtc/rtc-cmos.c rtc_update_irq(cmos->rtc, 1, mask); mask 1110 drivers/rtc/rtc-cmos.c } while (mask & RTC_AIE); mask 1271 drivers/rtc/rtc-cmos.c unsigned char mask; mask 1274 drivers/rtc/rtc-cmos.c mask = CMOS_READ(RTC_INTR_FLAGS); mask 1275 drivers/rtc/rtc-cmos.c rtc_update_irq(cmos->rtc, 1, mask); mask 1335 drivers/rtc/rtc-ds1307.c static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) mask 1342 drivers/rtc/rtc-ds1307.c mask, value); mask 119 drivers/rtc/rtc-jz4740.c static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask, mask 134 drivers/rtc/rtc-jz4740.c ctrl |= mask; mask 136 drivers/rtc/rtc-jz4740.c ctrl &= ~mask; mask 228 drivers/rtc/rtc-lp8788.c u8 mask, shift; mask 233 drivers/rtc/rtc-lp8788.c mask = mask_alarm_en[rtc->alarm]; mask 236 drivers/rtc/rtc-lp8788.c return lp8788_update_bits(lp, LP8788_INTEN_3, mask, enable << shift); mask 29 drivers/rtc/rtc-m48t59.c #define M48T59_SET_BITS(mask, reg) \ mask 30 drivers/rtc/rtc-m48t59.c M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg)) mask 31 drivers/rtc/rtc-m48t59.c #define M48T59_CLEAR_BITS(mask, reg) \ mask 32 drivers/rtc/rtc-m48t59.c M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg)) mask 68 drivers/rtc/rtc-max77686.c u8 mask; mask 187 drivers/rtc/rtc-max77686.c .mask = 0x7f, mask 198 drivers/rtc/rtc-max77686.c .mask = 0x7f, mask 247 drivers/rtc/rtc-max77686.c .mask = 0xff, mask 259 drivers/rtc/rtc-max77686.c u8 mask = info->drv_data->mask; mask 261 drivers/rtc/rtc-max77686.c tm->tm_sec = data[RTC_SEC] & mask; mask 262 drivers/rtc/rtc-max77686.c tm->tm_min = data[RTC_MIN] & mask; mask 272 drivers/rtc/rtc-max77686.c tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1; mask 275 drivers/rtc/rtc-max77686.c tm->tm_year = data[RTC_YEAR] & mask; mask 548 drivers/rtc/rtc-max77686.c if (data[RTC_YEAR] & info->drv_data->mask) mask 369 drivers/rtc/rtc-max8997.c u8 val, mask; mask 379 drivers/rtc/rtc-max8997.c mask = WTSR_EN_MASK | WTSRT_MASK; mask 384 drivers/rtc/rtc-max8997.c ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask); mask 397 drivers/rtc/rtc-max8997.c u8 val, mask; mask 407 drivers/rtc/rtc-max8997.c mask = SMPL_EN_MASK | SMPLT_MASK; mask 412 drivers/rtc/rtc-max8997.c ret = max8997_update_reg(info->rtc, MAX8997_RTC_WTSR_SMPL, val, mask); mask 96 drivers/rtc/rtc-mcp795.c static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state) mask 105 drivers/rtc/rtc-mcp795.c if ((tmp & mask) != state) { mask 106 drivers/rtc/rtc-mcp795.c tmp = (tmp & ~mask) | state; mask 176 drivers/rtc/rtc-mrst.c static void mrst_irq_enable(struct mrst_rtc *mrst, unsigned char mask) mask 187 drivers/rtc/rtc-mrst.c rtc_control |= mask; mask 193 drivers/rtc/rtc-mrst.c static void mrst_irq_disable(struct mrst_rtc *mrst, unsigned char mask) mask 198 drivers/rtc/rtc-mrst.c rtc_control &= ~mask; mask 404 drivers/rtc/rtc-mrst.c unsigned char mask; mask 407 drivers/rtc/rtc-mrst.c mask = RTC_IRQMASK & ~RTC_AIE; mask 409 drivers/rtc/rtc-mrst.c mask = RTC_IRQMASK; mask 410 drivers/rtc/rtc-mrst.c tmp &= ~mask; mask 444 drivers/rtc/rtc-mrst.c unsigned char mask; mask 455 drivers/rtc/rtc-mrst.c mask = vrtc_cmos_read(RTC_INTR_FLAGS); mask 456 drivers/rtc/rtc-mrst.c mask &= (tmp & RTC_IRQMASK) | RTC_IRQF; mask 457 drivers/rtc/rtc-mrst.c if (!is_intr(mask)) mask 460 drivers/rtc/rtc-mrst.c rtc_update_irq(mrst->rtc, 1, mask); mask 462 drivers/rtc/rtc-mrst.c } while (mask & RTC_AIE); mask 118 drivers/rtc/rtc-mt7622.c static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set) mask 123 drivers/rtc/rtc-mt7622.c val &= ~mask; mask 731 drivers/rtc/rtc-omap.c u8 reg, mask, new_ctrl; mask 799 drivers/rtc/rtc-omap.c mask = OMAP_RTC_STATUS_ALARM; mask 802 drivers/rtc/rtc-omap.c mask |= OMAP_RTC_STATUS_ALARM2; mask 805 drivers/rtc/rtc-omap.c mask |= OMAP_RTC_STATUS_POWER_UP; mask 810 drivers/rtc/rtc-omap.c if (reg & mask) mask 811 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_STATUS_REG, reg & mask); mask 1014 drivers/rtc/rtc-omap.c u8 mask; mask 1021 drivers/rtc/rtc-omap.c mask = rtc_read(rtc, OMAP_RTC_INTERRUPTS_REG); mask 1022 drivers/rtc/rtc-omap.c mask &= OMAP_RTC_INTERRUPTS_IT_ALARM; mask 1023 drivers/rtc/rtc-omap.c rtc_write(rtc, OMAP_RTC_INTERRUPTS_REG, mask); mask 167 drivers/rtc/rtc-pl030.c .mask = 0x000fffff, mask 454 drivers/rtc/rtc-pl031.c .mask = 0x000fffff, mask 460 drivers/rtc/rtc-pl031.c .mask = 0x00ffffff, mask 465 drivers/rtc/rtc-pl031.c .mask = 0x00ffffff, mask 112 drivers/rtc/rtc-pxa.c static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask) mask 118 drivers/rtc/rtc-pxa.c rtsr &= ~mask; mask 122 drivers/rtc/rtc-pxa.c static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask) mask 128 drivers/rtc/rtc-pxa.c rtsr |= mask; mask 82 drivers/rtc/rtc-r7301.c u8 mask, u8 val) mask 86 drivers/rtc/rtc-r7301.c regmap_update_bits(priv->regmap, reg_stride * reg, mask, val); mask 148 drivers/rtc/rtc-rv3029c2.c static int rv3029_update_bits(struct device *dev, u8 reg, u8 mask, u8 set) mask 156 drivers/rtc/rtc-rv3029c2.c buf &= ~mask; mask 157 drivers/rtc/rtc-rv3029c2.c buf |= set & mask; mask 311 drivers/rtc/rtc-rv3029c2.c u8 reg, u8 mask, u8 set) mask 319 drivers/rtc/rtc-rv3029c2.c buf &= ~mask; mask 320 drivers/rtc/rtc-rv3029c2.c buf |= set & mask; mask 59 drivers/rtc/rtc-s3c.c void (*irq_handler) (struct s3c_rtc *info, int mask); mask 630 drivers/rtc/rtc-s3c.c static void s3c24xx_rtc_irq(struct s3c_rtc *info, int mask) mask 635 drivers/rtc/rtc-s3c.c static void s3c6410_rtc_irq(struct s3c_rtc *info, int mask) mask 638 drivers/rtc/rtc-s3c.c writeb(mask, info->base + S3C2410_INTP); mask 551 drivers/rtc/rtc-sun6i.c unsigned int mask, unsigned int ms_timeout) mask 558 drivers/rtc/rtc-sun6i.c reg &= mask; mask 49 drivers/rtc/rtc-sunxi.c #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \ mask 52 drivers/rtc/rtc-sunxi.c #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift)) mask 59 drivers/rtc/rtc-sunxi.c #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16) mask 80 drivers/rtc/rtc-sunxi.c #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16) mask 119 drivers/rtc/rtc-sunxi.c unsigned int mask; /* mask for the year field */ mask 127 drivers/rtc/rtc-sunxi.c .mask = 0x3f, mask 133 drivers/rtc/rtc-sunxi.c .mask = 0xff, mask 203 drivers/rtc/rtc-sunxi.c chip->data_year->mask); mask 241 drivers/rtc/rtc-sunxi.c chip->data_year->mask); mask 311 drivers/rtc/rtc-sunxi.c unsigned int mask, unsigned int ms_timeout) mask 318 drivers/rtc/rtc-sunxi.c reg &= mask; mask 320 drivers/rtc/rtc-sunxi.c if (reg == mask) mask 354 drivers/rtc/rtc-sunxi.c chip->data_year->mask); mask 377 drivers/rtc/rtc-x1205.c unsigned char reg, mask, min, max; mask 477 drivers/rtc/rtc-x1205.c value = bcd2bin(reg & probe_limits_pattern[i].mask); mask 2051 drivers/s390/block/dasd.c int mask = ~(DASD_STOPPED_DC_WAIT | DASD_UNRESUMED_PM | DASD_STOPPED_NOSPC); mask 2062 drivers/s390/block/dasd.c if (device->stopped & mask) { mask 303 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x1; mask 307 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x1; mask 312 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x1; mask 320 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x02; mask 332 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x3; mask 333 drivers/s390/block/dasd_eckd.c data->mask.auth = 0x1; mask 338 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x03; mask 343 drivers/s390/block/dasd_eckd.c data->mask.perm = 0x02; mask 3488 drivers/s390/block/dasd_eckd.c char mask; mask 3493 drivers/s390/block/dasd_eckd.c mask = DEV_STAT_ATTENTION | DEV_STAT_DEV_END | DEV_STAT_UNIT_EXCEP; mask 3494 drivers/s390/block/dasd_eckd.c if ((scsw_dstat(&irb->scsw) & mask) == mask) { mask 4242 drivers/s390/block/dasd_eckd.c dedata->mask.perm = 0x1; mask 4252 drivers/s390/block/dasd_eckd.c dedata->mask.perm = 0x02; mask 4271 drivers/s390/block/dasd_eckd.c dedata->mask.perm = 0x1; mask 6196 drivers/s390/block/dasd_eckd.c unsigned long bitmask = 0, mask = 0; mask 6216 drivers/s390/block/dasd_eckd.c mask = cuir->neq_map[2]; mask 6217 drivers/s390/block/dasd_eckd.c mask |= cuir->neq_map[1] << 8; mask 6218 drivers/s390/block/dasd_eckd.c mask |= cuir->neq_map[0] << 16; mask 6222 drivers/s390/block/dasd_eckd.c bitmask = mask; mask 160 drivers/s390/block/dasd_eckd.h } __attribute__ ((packed)) mask; mask 667 drivers/s390/block/dasd_eer.c __poll_t mask; mask 675 drivers/s390/block/dasd_eer.c mask = EPOLLIN | EPOLLRDNORM ; mask 677 drivers/s390/block/dasd_eer.c mask = 0; mask 679 drivers/s390/block/dasd_eer.c return mask; mask 97 drivers/s390/block/dasd_fba.c (data->mask).perm = 0x0; mask 99 drivers/s390/block/dasd_fba.c (data->mask).perm = 0x1; mask 101 drivers/s390/block/dasd_fba.c data->mask.perm = 0x2; mask 246 drivers/s390/block/dasd_fba.c char mask; mask 249 drivers/s390/block/dasd_fba.c mask = DEV_STAT_ATTENTION | DEV_STAT_DEV_END | DEV_STAT_UNIT_EXCEP; mask 250 drivers/s390/block/dasd_fba.c if ((irb->scsw.cmd.dstat & mask) == mask) mask 24 drivers/s390/block/dasd_fba.h } __attribute__ ((packed)) mask; mask 41 drivers/s390/char/sclp_early_core.c S390_lowcore.external_new_psw.mask = psw_mask; mask 42 drivers/s390/char/sclp_early_core.c psw_wait.mask = psw_mask | PSW_MASK_EXT | PSW_MASK_WAIT; mask 31 drivers/s390/char/sclp_quiesce.c quiesce_psw.mask = mask 30 drivers/s390/cio/ccwreq.c int lpm_adjust(int lpm, int mask) mask 32 drivers/s390/cio/ccwreq.c while (lpm && ((lpm & mask) == 0)) mask 46 drivers/s390/cio/ccwreq.c req->mask = 0; mask 50 drivers/s390/cio/ccwreq.c req->mask = lpm_adjust(req->mask >> 1, req->lpm); mask 52 drivers/s390/cio/ccwreq.c return req->mask; mask 82 drivers/s390/cio/ccwreq.c while (req->mask) { mask 90 drivers/s390/cio/ccwreq.c rc = cio_start(sch, cp, (u8) req->mask); mask 126 drivers/s390/cio/ccwreq.c req->mask = 0x8080; mask 128 drivers/s390/cio/ccwreq.c req->mask = req->lpm; mask 131 drivers/s390/cio/ccwreq.c req->mask = lpm_adjust(req->mask, req->lpm); mask 135 drivers/s390/cio/ccwreq.c if (!req->mask) mask 243 drivers/s390/cio/ccwreq.c data.lpm = (u8) req->mask; mask 606 drivers/s390/cio/chp.c int mask; mask 609 drivers/s390/cio/chp.c mask = 0x80 >> i; mask 610 drivers/s390/cio/chp.c if (!(ssd->path_mask & mask)) mask 614 drivers/s390/cio/chp.c if ((ssd->fla_valid_mask & mask) && mask 617 drivers/s390/cio/chp.c return mask; mask 36 drivers/s390/cio/chp.h int mask = 128 >> (num & 7); mask 38 drivers/s390/cio/chp.h return (bitmap[byte] & mask) ? 1 : 0; mask 104 drivers/s390/cio/chsc.c int mask; mask 141 drivers/s390/cio/chsc.c mask = 0x80 >> i; mask 142 drivers/s390/cio/chsc.c if (ssd_area->path_mask & mask) { mask 146 drivers/s390/cio/chsc.c if (ssd_area->fla_valid_mask & mask) mask 965 drivers/s390/cio/chsc.c int i, mask; mask 968 drivers/s390/cio/chsc.c mask = 0x80 >> (i + 3); mask 969 drivers/s390/cio/chsc.c if (cmcv & mask) mask 276 drivers/s390/cio/css.c int mask; mask 281 drivers/s390/cio/css.c mask = 0x80 >> i; mask 282 drivers/s390/cio/css.c if (pmcw->pim & mask) { mask 292 drivers/s390/cio/css.c int mask; mask 295 drivers/s390/cio/css.c mask = 0x80 >> i; mask 296 drivers/s390/cio/css.c if (ssd->path_mask & mask) mask 402 drivers/s390/cio/css.c int mask; mask 406 drivers/s390/cio/css.c mask = 0x80 >> chp; mask 407 drivers/s390/cio/css.c if (ssd->path_mask & mask) mask 1142 drivers/s390/cio/device.c static void io_subchannel_terminate_path(struct subchannel *sch, u8 mask) mask 1152 drivers/s390/cio/device.c if (scsw_actl(&sch->schib.scsw) == 0 || sch->schib.pmcw.lpum != mask) mask 1173 drivers/s390/cio/device.c int mask; mask 1175 drivers/s390/cio/device.c mask = chp_ssd_get_mask(&sch->ssd_info, link); mask 1176 drivers/s390/cio/device.c if (!mask) mask 1180 drivers/s390/cio/device.c sch->opm &= ~mask; mask 1181 drivers/s390/cio/device.c sch->lpm &= ~mask; mask 1183 drivers/s390/cio/device.c cdev->private->path_gone_mask |= mask; mask 1184 drivers/s390/cio/device.c io_subchannel_terminate_path(sch, mask); mask 1187 drivers/s390/cio/device.c sch->opm |= mask; mask 1188 drivers/s390/cio/device.c sch->lpm |= mask; mask 1190 drivers/s390/cio/device.c cdev->private->path_new_mask |= mask; mask 1197 drivers/s390/cio/device.c cdev->private->path_gone_mask |= mask; mask 1198 drivers/s390/cio/device.c io_subchannel_terminate_path(sch, mask); mask 1203 drivers/s390/cio/device.c sch->lpm |= mask & sch->opm; mask 1205 drivers/s390/cio/device.c cdev->private->path_new_mask |= mask; mask 111 drivers/s390/cio/device.h int lpm_adjust(int lpm, int mask); mask 174 drivers/s390/cio/device_fsm.c int mask, i; mask 179 drivers/s390/cio/device_fsm.c mask = 0x80 >> i; mask 180 drivers/s390/cio/device_fsm.c if (!(sch->lpm & mask)) mask 182 drivers/s390/cio/device_fsm.c if (old_lpm & mask) mask 443 drivers/s390/cio/device_fsm.c int chp, mask; mask 445 drivers/s390/cio/device_fsm.c for (chp = 0, mask = 0x80; chp < 8; chp++, mask >>= 1) { mask 447 drivers/s390/cio/device_fsm.c if (mask & cdev->private->path_gone_mask & ~(sch->vpm)) mask 449 drivers/s390/cio/device_fsm.c if (mask & cdev->private->path_new_mask & sch->vpm) mask 451 drivers/s390/cio/device_fsm.c if (mask & cdev->private->pgid_reset_mask & sch->vpm) mask 640 drivers/s390/cio/device_ops.c int ccw_device_get_mdc(struct ccw_device *cdev, u8 mask) mask 648 drivers/s390/cio/device_ops.c if (mask) mask 649 drivers/s390/cio/device_ops.c mask &= sch->lpm; mask 651 drivers/s390/cio/device_ops.c mask = sch->lpm; mask 655 drivers/s390/cio/device_ops.c if (!(mask & (0x80 >> i))) mask 91 drivers/s390/cio/io_sch.h u16 mask; mask 250 drivers/s390/cio/qdio.h int mask; mask 52 drivers/s390/cio/qdio_main.c static inline int do_siga_input(unsigned long schid, unsigned int mask, mask 57 drivers/s390/cio/qdio_main.c register unsigned long __mask asm ("2") = mask; mask 80 drivers/s390/cio/qdio_main.c static inline int do_siga_output(unsigned long schid, unsigned long mask, mask 86 drivers/s390/cio/qdio_main.c register unsigned long __mask asm("2") = mask; mask 308 drivers/s390/cio/qdio_main.c return qdio_siga_sync(q, 0, q->mask); mask 310 drivers/s390/cio/qdio_main.c return qdio_siga_sync(q, q->mask, 0); mask 332 drivers/s390/cio/qdio_main.c cc = do_siga_output(schid, q->mask, busy_bit, fc, laob); mask 367 drivers/s390/cio/qdio_main.c cc = do_siga_input(schid, q->mask, fc); mask 180 drivers/s390/cio/qdio_setup.c q->mask = 1 << (31 - i); mask 45 drivers/s390/net/qeth_core_mpc.h static inline bool qeth_ipa_caps_supported(struct qeth_ipa_caps *caps, u32 mask) mask 47 drivers/s390/net/qeth_core_mpc.h return (caps->supported & mask) == mask; mask 50 drivers/s390/net/qeth_core_mpc.h static inline bool qeth_ipa_caps_enabled(struct qeth_ipa_caps *caps, u32 mask) mask 52 drivers/s390/net/qeth_core_mpc.h return (caps->enabled & mask) == mask; mask 341 drivers/s390/net/qeth_core_mpc.h __u8 mask[4]; mask 347 drivers/s390/net/qeth_core_mpc.h __u8 mask[16]; mask 41 drivers/s390/net/qeth_l3.h unsigned int mask; mask 89 drivers/s390/net/qeth_l3.h return a1->u.a4.mask == a2->u.a4.mask; mask 445 drivers/s390/net/qeth_l3_main.c memcpy(cmd->data.setdelip6.mask, netmask, mask 450 drivers/s390/net/qeth_l3_main.c memcpy(cmd->data.setdelip4.mask, &addr->u.a4.mask, 4); mask 2563 drivers/s390/net/qeth_l3_main.c addr.u.a4.mask = be32_to_cpu(ifa->ifa_mask); mask 50 drivers/s390/scsi/zfcp_erp.c static void zfcp_erp_adapter_block(struct zfcp_adapter *adapter, int mask) mask 53 drivers/s390/scsi/zfcp_erp.c ZFCP_STATUS_COMMON_UNBLOCKED | mask); mask 527 drivers/s390/scsi/zfcp_erp.c static int zfcp_erp_status_change_set(unsigned long mask, atomic_t *status) mask 529 drivers/s390/scsi/zfcp_erp.c return (atomic_read(status) ^ mask) & mask; mask 1622 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_set_adapter_status(struct zfcp_adapter *adapter, u32 mask) mask 1627 drivers/s390/scsi/zfcp_erp.c u32 common_mask = mask & ZFCP_COMMON_FLAGS; mask 1629 drivers/s390/scsi/zfcp_erp.c atomic_or(mask, &adapter->status); mask 1652 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_clear_adapter_status(struct zfcp_adapter *adapter, u32 mask) mask 1657 drivers/s390/scsi/zfcp_erp.c u32 common_mask = mask & ZFCP_COMMON_FLAGS; mask 1658 drivers/s390/scsi/zfcp_erp.c u32 clear_counter = mask & ZFCP_STATUS_COMMON_ERP_FAILED; mask 1660 drivers/s390/scsi/zfcp_erp.c atomic_andnot(mask, &adapter->status); mask 1692 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_set_port_status(struct zfcp_port *port, u32 mask) mask 1695 drivers/s390/scsi/zfcp_erp.c u32 common_mask = mask & ZFCP_COMMON_FLAGS; mask 1698 drivers/s390/scsi/zfcp_erp.c atomic_or(mask, &port->status); mask 1718 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_clear_port_status(struct zfcp_port *port, u32 mask) mask 1721 drivers/s390/scsi/zfcp_erp.c u32 common_mask = mask & ZFCP_COMMON_FLAGS; mask 1722 drivers/s390/scsi/zfcp_erp.c u32 clear_counter = mask & ZFCP_STATUS_COMMON_ERP_FAILED; mask 1725 drivers/s390/scsi/zfcp_erp.c atomic_andnot(mask, &port->status); mask 1749 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_set_lun_status(struct scsi_device *sdev, u32 mask) mask 1753 drivers/s390/scsi/zfcp_erp.c atomic_or(mask, &zfcp_sdev->status); mask 1761 drivers/s390/scsi/zfcp_erp.c void zfcp_erp_clear_lun_status(struct scsi_device *sdev, u32 mask) mask 1765 drivers/s390/scsi/zfcp_erp.c atomic_andnot(mask, &zfcp_sdev->status); mask 1767 drivers/s390/scsi/zfcp_erp.c if (mask & ZFCP_STATUS_COMMON_ERP_FAILED) mask 804 drivers/s390/scsi/zfcp_scsi.c unsigned int mask = 0; mask 813 drivers/s390/scsi/zfcp_scsi.c mask |= SHOST_DIF_TYPE1_PROTECTION; mask 817 drivers/s390/scsi/zfcp_scsi.c mask |= SHOST_DIX_TYPE1_PROTECTION; mask 824 drivers/s390/scsi/zfcp_scsi.c scsi_host_set_prot(shost, mask); mask 230 drivers/scsi/NCR5380.c unsigned char mask; mask 295 drivers/scsi/NCR5380.c for (i = 0; signals[i].mask; ++i) mask 296 drivers/scsi/NCR5380.c if (status & signals[i].mask) mask 299 drivers/scsi/NCR5380.c for (i = 0; basrs[i].mask; ++i) mask 300 drivers/scsi/NCR5380.c if (basr & basrs[i].mask) mask 303 drivers/scsi/NCR5380.c for (i = 0; icrs[i].mask; ++i) mask 304 drivers/scsi/NCR5380.c if (icr & icrs[i].mask) mask 307 drivers/scsi/NCR5380.c for (i = 0; mrs[i].mask; ++i) mask 308 drivers/scsi/NCR5380.c if (mr & mrs[i].mask) mask 37 drivers/scsi/aacraid/sa.c unsigned short intstat, mask; mask 44 drivers/scsi/aacraid/sa.c mask = ~(sa_readw(dev, SaDbCSR.PRISETIRQMASK)); mask 48 drivers/scsi/aacraid/sa.c if (intstat & mask) { mask 78 drivers/scsi/aha1542.c static inline bool wait_mask(u16 port, u8 mask, u8 allof, u8 noneof, int timeout) mask 88 drivers/scsi/aha1542.c u8 bits = inb(port) & mask; mask 5612 drivers/scsi/aic7xxx/aic79xx_core.c int mask; mask 5621 drivers/scsi/aic7xxx/aic79xx_core.c mask = ~0x23; mask 5629 drivers/scsi/aic7xxx/aic79xx_core.c mask = ~0x03; mask 5637 drivers/scsi/aic7xxx/aic79xx_core.c ahd_inb_scbram(ahd, SCB_CONTROL) & mask); mask 5638 drivers/scsi/aic7xxx/aic79xx_core.c scb->hscb->control &= mask; mask 9573 drivers/scsi/aic7xxx/aic79xx_core.c uint32_t mask; mask 9575 drivers/scsi/aic7xxx/aic79xx_core.c mask = 0x01 << i; mask 9576 drivers/scsi/aic7xxx/aic79xx_core.c if ((instr.integer & mask) != 0) mask 9651 drivers/scsi/aic7xxx/aic79xx_core.c if (((value & table[entry].mask) mask 9653 drivers/scsi/aic7xxx/aic79xx_core.c || ((printed_mask & table[entry].mask) mask 9654 drivers/scsi/aic7xxx/aic79xx_core.c == table[entry].mask)) mask 9660 drivers/scsi/aic7xxx/aic79xx_core.c printed_mask |= table[entry].mask; mask 1562 drivers/scsi/aic7xxx/aic79xx_osm.c uint16_t mask; mask 1603 drivers/scsi/aic7xxx/aic79xx_osm.c mask = SCB_GET_TARGET_MASK(ahd, scb); mask 1605 drivers/scsi/aic7xxx/aic79xx_osm.c if ((ahd->user_discenable & mask) != 0) mask 1611 drivers/scsi/aic7xxx/aic79xx_osm.c if ((tstate->auto_negotiate & mask) != 0) { mask 4078 drivers/scsi/aic7xxx/aic7xxx_core.c int mask; mask 4087 drivers/scsi/aic7xxx/aic7xxx_core.c mask = ~0x23; mask 4095 drivers/scsi/aic7xxx/aic7xxx_core.c mask = ~0x03; mask 4103 drivers/scsi/aic7xxx/aic7xxx_core.c ahc_inb(ahc, SCB_CONTROL) & mask); mask 4104 drivers/scsi/aic7xxx/aic7xxx_core.c scb->hscb->control &= mask; mask 5482 drivers/scsi/aic7xxx/aic7xxx_core.c uint16_t mask; mask 5486 drivers/scsi/aic7xxx/aic7xxx_core.c mask = (0x01 << i); mask 5497 drivers/scsi/aic7xxx/aic7xxx_core.c | (ultraenb & mask) mask 5521 drivers/scsi/aic7xxx/aic7xxx_core.c && (ultraenb & mask) != 0) { mask 5524 drivers/scsi/aic7xxx/aic7xxx_core.c ultraenb &= ~mask; mask 5528 drivers/scsi/aic7xxx/aic7xxx_core.c (ultraenb & mask) mask 7051 drivers/scsi/aic7xxx/aic7xxx_core.c uint32_t mask; mask 7053 drivers/scsi/aic7xxx/aic7xxx_core.c mask = 0x01 << i; mask 7054 drivers/scsi/aic7xxx/aic7xxx_core.c if ((instr.integer & mask) != 0) mask 7109 drivers/scsi/aic7xxx/aic7xxx_core.c if (((value & table[entry].mask) mask 7111 drivers/scsi/aic7xxx/aic7xxx_core.c || ((printed_mask & table[entry].mask) mask 7112 drivers/scsi/aic7xxx/aic7xxx_core.c == table[entry].mask)) mask 7118 drivers/scsi/aic7xxx/aic7xxx_core.c printed_mask |= table[entry].mask; mask 1426 drivers/scsi/aic7xxx/aic7xxx_osm.c uint16_t mask; mask 1479 drivers/scsi/aic7xxx/aic7xxx_osm.c mask = SCB_GET_TARGET_MASK(ahc, scb); mask 1485 drivers/scsi/aic7xxx/aic7xxx_osm.c if ((tstate->ultraenb & mask) != 0) mask 1488 drivers/scsi/aic7xxx/aic7xxx_osm.c if ((ahc->user_discenable & mask) != 0) mask 1491 drivers/scsi/aic7xxx/aic7xxx_osm.c if ((tstate->auto_negotiate & mask) != 0) { mask 87 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y static void process_field(int field_type, symbol_t *sym, int mask); mask 1441 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y sym->info.finfo->mask = value; mask 1443 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y sym->info.finfo->mask = field_symbol->info.finfo->value; mask 1445 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y sym->info.finfo->mask = 0xFF; mask 1463 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y cur_symbol->info.rinfo->valid_bitmask |= sym->info.finfo->mask; mask 1859 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y int8_t value, mask; mask 1875 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y mask = (int8_t)~symbol->info.rinfo->valid_bitmask; mask 1878 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y if (and_op == FALSE && (mask & value) != 0 ) { mask 1881 drivers/scsi/aic7xxx/aicasm/aicasm_gram.y (mask & value), mask 456 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.c curnode->symbol->info.finfo->mask); mask 85 drivers/scsi/aic7xxx/aicasm/aicasm_symbol.h uint8_t mask; mask 1367 drivers/scsi/aic94xx/aic94xx_seq.c u8 mask; mask 1372 drivers/scsi/aic94xx/aic94xx_seq.c for_each_phy(phy_mask, mask, i) mask 1677 drivers/scsi/arcmsr/arcmsr_hba.c u32 mask; mask 1682 drivers/scsi/arcmsr/arcmsr_hba.c mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | mask 1685 drivers/scsi/arcmsr/arcmsr_hba.c writel(mask, ®->outbound_intmask); mask 1686 drivers/scsi/arcmsr/arcmsr_hba.c acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; mask 1692 drivers/scsi/arcmsr/arcmsr_hba.c mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | mask 1696 drivers/scsi/arcmsr/arcmsr_hba.c writel(mask, reg->iop2drv_doorbell_mask); mask 1697 drivers/scsi/arcmsr/arcmsr_hba.c acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; mask 1702 drivers/scsi/arcmsr/arcmsr_hba.c mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); mask 1703 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org & mask, ®->host_int_mask); mask 1704 drivers/scsi/arcmsr/arcmsr_hba.c acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; mask 1710 drivers/scsi/arcmsr/arcmsr_hba.c mask = ARCMSR_ARC1214_ALL_INT_ENABLE; mask 1711 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org | mask, reg->pcief0_int_enable); mask 1717 drivers/scsi/arcmsr/arcmsr_hba.c mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); mask 1718 drivers/scsi/arcmsr/arcmsr_hba.c writel(intmask_org & mask, ®->host_int_mask); mask 196 drivers/scsi/arm/eesox.c register const unsigned long mask = 0xffff; mask 237 drivers/scsi/arm/eesox.c l1 = readl(reg_dmadata) & mask; mask 239 drivers/scsi/arm/eesox.c l2 = readl(reg_dmadata) & mask; mask 252 drivers/scsi/arm/eesox.c l1 = readl(reg_dmadata) & mask; mask 164 drivers/scsi/be2iscsi/be.h static inline void amap_set(void *ptr, u32 dw_offset, u32 mask, mask 168 drivers/scsi/be2iscsi/be.h *dw &= ~(mask << offset); mask 169 drivers/scsi/be2iscsi/be.h *dw |= (mask & value) << offset; mask 179 drivers/scsi/be2iscsi/be.h static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) mask 182 drivers/scsi/be2iscsi/be.h return mask & (*(dw + dw_offset) >> offset); mask 1023 drivers/scsi/be2iscsi/be_main.h #define beiscsi_log(phba, level, mask, fmt, arg...) \ mask 1026 drivers/scsi/be2iscsi/be_main.h if (((mask) & log_value) || (level[1] <= '3')) \ mask 1146 drivers/scsi/bfa/bfad.c int mask, int max_bit) mask 1152 drivers/scsi/bfa/bfad.c if (mask & match) { mask 1204 drivers/scsi/bfa/bfad.c u32 mask = 0, i, num_bit = 0, max_bit = 0; mask 1210 drivers/scsi/bfa/bfad.c bfa_msix_getvecs(&bfad->bfa, &mask, &num_bit, &max_bit); mask 1213 drivers/scsi/bfa/bfad.c bfad_init_msix_entry(bfad, msix_entries, mask, max_bit); mask 283 drivers/scsi/bfa/bfad_drv.h #define BFA_LOG(level, bfad, mask, fmt, arg...) \ mask 285 drivers/scsi/bfa/bfad_drv.h if (((mask) == 4) || (level[1] <= '4')) \ mask 133 drivers/scsi/csiostor/csio_hw.c csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, mask 140 drivers/scsi/csiostor/csio_hw.c if (!!(val & mask) == polarity) { mask 164 drivers/scsi/csiostor/csio_hw.c unsigned int mask, unsigned int val) mask 167 drivers/scsi/csiostor/csio_hw.c val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; mask 172 drivers/scsi/csiostor/csio_hw.c csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, mask 175 drivers/scsi/csiostor/csio_hw.c uint32_t val = csio_rd_reg32(hw, reg) & ~mask; mask 3117 drivers/scsi/csiostor/csio_hw.c unsigned int mask = 0; mask 3120 drivers/scsi/csiostor/csio_hw.c for ( ; acts->mask; ++acts) { mask 3121 drivers/scsi/csiostor/csio_hw.c if (!(status & acts->mask)) mask 3126 drivers/scsi/csiostor/csio_hw.c acts->msg, status & acts->mask); mask 3129 drivers/scsi/csiostor/csio_hw.c acts->msg, status & acts->mask); mask 3130 drivers/scsi/csiostor/csio_hw.c mask |= acts->mask; mask 3132 drivers/scsi/csiostor/csio_hw.c status &= mask; mask 112 drivers/scsi/csiostor/csio_hw_chip.h unsigned int mask; /* bits to check in interrupt status */ mask 1164 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c req->mask = cpu_to_be64(0xF0000000); mask 1200 drivers/scsi/cxgbi/cxgb3i/cxgb3i.c req->mask = cpu_to_be64(0x0F000000); mask 2015 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c req->mask = cpu_to_be64(0x3 << 8); mask 2050 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c req->mask = cpu_to_be64(0x3 << 4); mask 987 drivers/scsi/cxlflash/ocxl_hw.c int mask = 0; mask 993 drivers/scsi/cxlflash/ocxl_hw.c mask |= POLLIN | POLLRDNORM; mask 995 drivers/scsi/cxlflash/ocxl_hw.c mask |= POLLERR; mask 999 drivers/scsi/cxlflash/ocxl_hw.c __func__, ctx->pe, mask); mask 1001 drivers/scsi/cxlflash/ocxl_hw.c return mask; mask 2840 drivers/scsi/esp_scsi.c u8 mask = ~(phase == ESP_MIP ? ESP_INTR_FDONE : ESP_INTR_BSERV); mask 2863 drivers/scsi/esp_scsi.c if (esp->ireg & mask) { mask 54 drivers/scsi/fnic/vnic_intr.h u32 mask; /* 0x20 */ mask 70 drivers/scsi/fnic/vnic_intr.h iowrite32(0, &intr->ctrl->mask); mask 75 drivers/scsi/fnic/vnic_intr.h iowrite32(1, &intr->ctrl->mask); mask 2130 drivers/scsi/hisi_sas/hisi_sas_main.c const struct cpumask *mask = cq->pci_irq_mask; mask 2132 drivers/scsi/hisi_sas/hisi_sas_main.c if (mask && !cpumask_intersects(cpu_online_mask, mask)) mask 2349 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c const struct cpumask *mask; mask 2355 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + mask 2357 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c if (!mask) mask 2359 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c cq->pci_irq_mask = mask; mask 2360 drivers/scsi/hisi_sas/hisi_sas_v3_hw.c for_each_cpu(cpu, mask) mask 7440 drivers/scsi/hpsa.c const struct cpumask *mask; mask 7444 drivers/scsi/hpsa.c mask = pci_irq_get_affinity(h->pdev, queue); mask 7445 drivers/scsi/hpsa.c if (!mask) mask 7448 drivers/scsi/hpsa.c for_each_cpu(cpu, mask) mask 304 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c static struct viosrp_crq *ibmvscsis_cmd_q_dequeue(uint mask, mask 313 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c *current_index = (*current_index + 1) & mask; mask 362 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c crq = ibmvscsis_cmd_q_dequeue(vscsi->cmd_q.mask, &vscsi->cmd_q.index, mask 376 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c crq = ibmvscsis_cmd_q_dequeue(vscsi->cmd_q.mask, mask 1185 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c (vscsi->cmd_q.index + 1) & vscsi->cmd_q.mask; mask 1216 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c vscsi->cmd_q.index = vscsi->cmd_q.mask; mask 3027 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c vscsi->cmd_q.mask = ((uint)pages * CRQ_PER_PAGE) - 1; mask 3375 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c (vscsi->cmd_q.index + 1) & vscsi->cmd_q.mask; mask 3403 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c vscsi->cmd_q.index = vscsi->cmd_q.mask; mask 126 drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.h uint mask; mask 10155 drivers/scsi/ipr.c volatile u32 mask, uproc, interrupts; mask 10347 drivers/scsi/ipr.c mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32); mask 10350 drivers/scsi/ipr.c if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT)) mask 105 drivers/scsi/isci/port.c u32 mask; mask 107 drivers/scsi/isci/port.c mask = 0; mask 110 drivers/scsi/isci/port.c mask |= (1 << index); mask 112 drivers/scsi/isci/port.c return mask; mask 162 drivers/scsi/iscsi_boot_sysfs.c iscsi_boot_rd_attr(eth_subnet, subnet-mask, ISCSI_BOOT_ETH_SUBNET_MASK); mask 663 drivers/scsi/lpfc/lpfc.h uint32_t mask); mask 3025 drivers/scsi/lpfc/lpfc_ct.c uint32_t mask; mask 3106 drivers/scsi/lpfc/lpfc_ct.c mask = new_mask; mask 3108 drivers/scsi/lpfc/lpfc_ct.c mask = vport->fdmi_hba_mask; mask 3111 drivers/scsi/lpfc/lpfc_ct.c while (mask) { mask 3112 drivers/scsi/lpfc/lpfc_ct.c if (mask & 0x1) { mask 3122 drivers/scsi/lpfc/lpfc_ct.c mask = mask >> 1; mask 3151 drivers/scsi/lpfc/lpfc_ct.c mask = new_mask; mask 3153 drivers/scsi/lpfc/lpfc_ct.c mask = vport->fdmi_port_mask; mask 3156 drivers/scsi/lpfc/lpfc_ct.c while (mask) { mask 3157 drivers/scsi/lpfc/lpfc_ct.c if (mask & 0x1) { mask 3167 drivers/scsi/lpfc/lpfc_ct.c mask = mask >> 1; mask 1710 drivers/scsi/lpfc/lpfc_debugfs.c lpfc_debugfs_disc_trc(struct lpfc_vport *vport, int mask, char *fmt, mask 1717 drivers/scsi/lpfc/lpfc_debugfs.c if (!(lpfc_debugfs_mask_disc_trc & mask)) mask 49 drivers/scsi/lpfc/lpfc_logmsg.h #define lpfc_printf_vlog(vport, level, mask, fmt, arg...) \ mask 51 drivers/scsi/lpfc/lpfc_logmsg.h { if (((mask) & (vport)->cfg_log_verbose) || (level[1] <= '3')) \ mask 56 drivers/scsi/lpfc/lpfc_logmsg.h #define lpfc_printf_log(phba, level, mask, fmt, arg...) \ mask 61 drivers/scsi/lpfc/lpfc_logmsg.h if (((mask) & log_verbose) || (level[1] <= '3')) \ mask 3348 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) mask 3504 drivers/scsi/lpfc/lpfc_sli.c if ((rsp_cmpl > 0) && (mask & HA_R0RE_REQ)) { mask 3510 drivers/scsi/lpfc/lpfc_sli.c if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) { mask 3715 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) mask 3717 drivers/scsi/lpfc/lpfc_sli.c phba->lpfc_sli_handle_slow_ring_event(phba, pring, mask); mask 3733 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) mask 3830 drivers/scsi/lpfc/lpfc_sli.c if ((rspiocbp != NULL) && (mask & HA_R0RE_REQ)) { mask 3838 drivers/scsi/lpfc/lpfc_sli.c if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) { mask 3869 drivers/scsi/lpfc/lpfc_sli.c struct lpfc_sli_ring *pring, uint32_t mask) mask 4089 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready_s3(struct lpfc_hba *phba, uint32_t mask) mask 4105 drivers/scsi/lpfc/lpfc_sli.c while (((status & mask) != mask) && mask 4155 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready_s4(struct lpfc_hba *phba, uint32_t mask) mask 4188 drivers/scsi/lpfc/lpfc_sli.c lpfc_sli_brdready(struct lpfc_hba *phba, uint32_t mask) mask 4190 drivers/scsi/lpfc/lpfc_sli.c return phba->lpfc_sli_brdready(phba, mask); mask 459 drivers/scsi/megaraid/megaraid_sas_base.c u32 mask = 0x1f; mask 462 drivers/scsi/megaraid/megaraid_sas_base.c writel(mask, ®s->outbound_intr_mask); mask 638 drivers/scsi/megaraid/megaraid_sas_base.c u32 mask = 0xFFFFFFFF; mask 641 drivers/scsi/megaraid/megaraid_sas_base.c writel(mask, ®s->outbound_intr_mask); mask 765 drivers/scsi/megaraid/megaraid_sas_base.c u32 mask = 0xFFFFFFFF; mask 768 drivers/scsi/megaraid/megaraid_sas_base.c writel(mask, ®s->outbound_intr_mask); mask 911 drivers/scsi/megaraid/megaraid_sas_base.c u32 mask = 0xFFFFFFFF; mask 914 drivers/scsi/megaraid/megaraid_sas_base.c writel(mask, ®s->outbound_intr_mask); mask 5697 drivers/scsi/megaraid/megaraid_sas_base.c const struct cpumask *mask; mask 5703 drivers/scsi/megaraid/megaraid_sas_base.c mask = pci_irq_get_affinity(instance->pdev, queue); mask 5704 drivers/scsi/megaraid/megaraid_sas_base.c if (!mask) mask 5707 drivers/scsi/megaraid/megaraid_sas_base.c for_each_cpu(cpu, mask) mask 7964 drivers/scsi/megaraid/megaraid_sas_base.c __poll_t mask; mask 7970 drivers/scsi/megaraid/megaraid_sas_base.c mask = (EPOLLIN | EPOLLRDNORM); mask 7972 drivers/scsi/megaraid/megaraid_sas_base.c mask = 0; mask 7975 drivers/scsi/megaraid/megaraid_sas_base.c return mask; mask 204 drivers/scsi/megaraid/megaraid_sas_fusion.c u32 mask = 0xFFFFFFFF; mask 209 drivers/scsi/megaraid/megaraid_sas_fusion.c writel(mask, ®s->outbound_intr_mask); mask 2922 drivers/scsi/mpt3sas/mpt3sas_base.c const cpumask_t *mask; mask 2927 drivers/scsi/mpt3sas/mpt3sas_base.c mask = pci_irq_get_affinity(ioc->pdev, mask 2929 drivers/scsi/mpt3sas/mpt3sas_base.c if (!mask) { mask 2935 drivers/scsi/mpt3sas/mpt3sas_base.c for_each_cpu_and(cpu, mask, cpu_online_mask) { mask 1900 drivers/scsi/mvumi.c unsigned int mask; mask 1904 drivers/scsi/mvumi.c mask = ioread32(regs->enpointa_mask_reg); mask 1905 drivers/scsi/mvumi.c mask |= regs->int_dl_cpu2pciea | regs->int_comaout | regs->int_comaerr; mask 1906 drivers/scsi/mvumi.c iowrite32(mask, regs->enpointa_mask_reg); mask 1915 drivers/scsi/mvumi.c unsigned int mask; mask 1919 drivers/scsi/mvumi.c mask = ioread32(regs->enpointa_mask_reg); mask 1920 drivers/scsi/mvumi.c mask &= ~(regs->int_dl_cpu2pciea | regs->int_comaout | mask 1922 drivers/scsi/mvumi.c iowrite32(mask, regs->enpointa_mask_reg); mask 281 drivers/scsi/nsp32.c # define nsp32_dbg(mask, args...) /* */ mask 286 drivers/scsi/nsp32.c # define nsp32_dbg(mask, args...) \ mask 287 drivers/scsi/nsp32.c nsp32_dmessage(__func__, __LINE__, (mask), args) mask 329 drivers/scsi/nsp32.c static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...) mask 338 drivers/scsi/nsp32.c if (mask & NSP32_DEBUG_MASK) { mask 339 drivers/scsi/nsp32.c printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); mask 102 drivers/scsi/pcmcia/nsp_cs.c # define nsp_dbg(mask, args...) /* */ mask 107 drivers/scsi/pcmcia/nsp_cs.c # define nsp_dbg(mask, args...) \ mask 108 drivers/scsi/pcmcia/nsp_cs.c nsp_cs_dmessage(__func__, __LINE__, (mask), args) mask 156 drivers/scsi/pcmcia/nsp_cs.c static void nsp_cs_dmessage(const char *func, int line, int mask, char *fmt, ...) mask 165 drivers/scsi/pcmcia/nsp_cs.c if (mask & NSP_DEBUG_MASK) { mask 166 drivers/scsi/pcmcia/nsp_cs.c printk("nsp_cs-debug: 0x%x %s (%d): %s\n", mask, func, line, buf); mask 516 drivers/scsi/pcmcia/nsp_cs.c static int nsp_negate_signal(struct scsi_cmnd *SCpnt, unsigned char mask, mask 532 drivers/scsi/pcmcia/nsp_cs.c } while ((--time_out != 0) && (reg & mask) != 0); mask 546 drivers/scsi/pcmcia/nsp_cs.c unsigned char mask) mask 566 drivers/scsi/pcmcia/nsp_cs.c if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { mask 317 drivers/scsi/pcmcia/nsp_cs.h unsigned char mask, char *str); mask 320 drivers/scsi/pcmcia/nsp_cs.h unsigned char mask); mask 1372 drivers/scsi/pm8001/pm80xx_hwi.c u32 mask; mask 1373 drivers/scsi/pm8001/pm80xx_hwi.c mask = (u32)(1 << vec); mask 1375 drivers/scsi/pm8001/pm80xx_hwi.c pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); mask 1390 drivers/scsi/pm8001/pm80xx_hwi.c u32 mask; mask 1392 drivers/scsi/pm8001/pm80xx_hwi.c mask = 0xFFFFFFFF; mask 1394 drivers/scsi/pm8001/pm80xx_hwi.c mask = (u32)(1 << vec); mask 1395 drivers/scsi/pm8001/pm80xx_hwi.c pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); mask 516 drivers/scsi/pmcraid.c u32 mask; mask 520 drivers/scsi/pmcraid.c mask = ioread32(pinstance->int_regs.ioa_host_interrupt_mask_reg); mask 524 drivers/scsi/pmcraid.c if ((mask & INTRS_HRRQ_VALID) == 0 || mask 140 drivers/scsi/qla2xxx/qla_nx2.c uint32_t mask) mask 149 drivers/scsi/qla2xxx/qla_nx2.c if ((temp & mask) != 0) mask 163 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr) mask 168 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_poll_wait_for_ready(vha, addr1, mask); mask 175 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_poll_wait_for_ready(vha, addr1, mask); mask 187 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask) mask 195 drivers/scsi/qla2xxx/qla_nx2.c temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2); mask 210 drivers/scsi/qla2xxx/qla_nx2.c uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value) mask 214 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_poll_wait_for_ready(vha, addr1, mask); mask 221 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_poll_wait_for_ready(vha, addr1, mask); mask 3008 drivers/scsi/qla2xxx/qla_nx2.c uint32_t poll, mask, modify_mask; mask 3022 drivers/scsi/qla2xxx/qla_nx2.c mask = rddfe->mask; mask 3033 drivers/scsi/qla2xxx/qla_nx2.c if ((temp & mask) != 0) mask 3054 drivers/scsi/qla2xxx/qla_nx2.c if ((temp & mask) != 0) mask 3069 drivers/scsi/qla2xxx/qla_nx2.c if ((temp & mask) != 0) mask 3105 drivers/scsi/qla2xxx/qla_nx2.c uint32_t mask; mask 3119 drivers/scsi/qla2xxx/qla_nx2.c mask = rdmdio->mask; mask 3126 drivers/scsi/qla2xxx/qla_nx2.c addr3, mask); mask 3131 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4, mask 3137 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5, mask 3143 drivers/scsi/qla2xxx/qla_nx2.c ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, mask 3149 drivers/scsi/qla2xxx/qla_nx2.c addr3, mask); mask 3154 drivers/scsi/qla2xxx/qla_nx2.c data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7); mask 441 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; mask 458 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; mask 471 drivers/scsi/qla2xxx/qla_nx2.h uint32_t mask; mask 265 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; mask 282 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; mask 295 drivers/scsi/qla4xxx/ql4_83xx.h uint32_t mask; mask 48 drivers/scsi/qla4xxx/ql4_nvram.c int mask; mask 60 drivers/scsi/qla4xxx/ql4_nvram.c mask = 1 << (FM93C56A_CMD_BITS - 1); mask 66 drivers/scsi/qla4xxx/ql4_nvram.c (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0; mask 83 drivers/scsi/qla4xxx/ql4_nvram.c mask = 1 << (eeprom_no_addr_bits(ha) - 1); mask 88 drivers/scsi/qla4xxx/ql4_nvram.c dataBit = addr & mask ? AUBURN_EEPROM_DO_1 : mask 1827 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, uint32_t mask) mask 1836 drivers/scsi/qla4xxx/ql4_nx.c if ((temp & mask) != 0) mask 1849 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr3, uint32_t mask, uint32_t addr, mask 1856 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); mask 1863 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); mask 1879 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mask) mask 1887 drivers/scsi/qla4xxx/ql4_nx.c ql4_84xx_ipmdio_rd_reg(ha, addr1, addr3, mask, addr2, &temp); mask 1901 drivers/scsi/qla4xxx/ql4_nx.c uint32_t mask, uint32_t addr, mask 1906 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); mask 1913 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_poll_wait_for_ready(ha, addr1, mask); mask 2648 drivers/scsi/qla4xxx/ql4_nx.c uint32_t poll, mask, data_size, modify_mask; mask 2662 drivers/scsi/qla4xxx/ql4_nx.c mask = le32_to_cpu(rddfe->mask); mask 2674 drivers/scsi/qla4xxx/ql4_nx.c if ((temp & mask) != 0) mask 2695 drivers/scsi/qla4xxx/ql4_nx.c if ((temp & mask) != 0) mask 2712 drivers/scsi/qla4xxx/ql4_nx.c if ((temp & mask) != 0) mask 2745 drivers/scsi/qla4xxx/ql4_nx.c uint32_t poll, mask; mask 2758 drivers/scsi/qla4xxx/ql4_nx.c mask = le32_to_cpu(rdmdio->mask); mask 2765 drivers/scsi/qla4xxx/ql4_nx.c addr3, mask); mask 2770 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr4, mask 2776 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, addr5, mask 2782 drivers/scsi/qla4xxx/ql4_nx.c rval = ql4_84xx_ipmdio_wr_reg(ha, addr1, addr3, mask, mask 2788 drivers/scsi/qla4xxx/ql4_nx.c addr3, mask); mask 2794 drivers/scsi/qla4xxx/ql4_nx.c mask, addr7, &data); mask 2816 drivers/scsi/qla4xxx/ql4_nx.c uint32_t addr1, addr2, value1, value2, poll, mask, r_value; mask 2828 drivers/scsi/qla4xxx/ql4_nx.c mask = le32_to_cpu(pollwr_hdr->mask); mask 1169 drivers/scsi/sd.c unsigned int mask = logical_to_sectors(sdp, 1) - 1; mask 1190 drivers/scsi/sd.c if ((blk_rq_pos(rq) & mask) || (blk_rq_sectors(rq) & mask)) { mask 7392 drivers/scsi/smartpqi/smartpqi_init.c u64 mask; mask 7402 drivers/scsi/smartpqi/smartpqi_init.c mask = DMA_BIT_MASK(64); mask 7404 drivers/scsi/smartpqi/smartpqi_init.c mask = DMA_BIT_MASK(32); mask 7406 drivers/scsi/smartpqi/smartpqi_init.c rc = dma_set_mask_and_coherent(&ctrl_info->pci_dev->dev, mask); mask 39 drivers/scsi/snic/vnic_intr.h u32 mask; /* 0x20 */ mask 56 drivers/scsi/snic/vnic_intr.h iowrite32(0, &intr->ctrl->mask); mask 62 drivers/scsi/snic/vnic_intr.h iowrite32(1, &intr->ctrl->mask); mask 737 drivers/scsi/sr.c cd->cdi.mask = 0; mask 901 drivers/scsi/sr.c cd->cdi.mask |= (CDC_CD_R | CDC_CD_RW | CDC_DVD_R | mask 927 drivers/scsi/sr.c cd->cdi.mask |= CDC_CLOSE_TRAY; mask 930 drivers/scsi/sr.c cd->cdi.mask |= CDC_DVD; mask 933 drivers/scsi/sr.c cd->cdi.mask |= CDC_DVD_RAM; mask 936 drivers/scsi/sr.c cd->cdi.mask |= CDC_DVD_R; mask 939 drivers/scsi/sr.c cd->cdi.mask |= CDC_CD_RW; mask 942 drivers/scsi/sr.c cd->cdi.mask |= CDC_CD_R; mask 945 drivers/scsi/sr.c cd->cdi.mask |= CDC_OPEN_TRAY; mask 953 drivers/scsi/sr.c cd->cdi.mask |= CDC_SELECT_DISC; mask 960 drivers/scsi/sr.c if ((cd->cdi.mask & (CDC_DVD_RAM | CDC_MRW_W | CDC_RAM | CDC_CD_RW)) != mask 97 drivers/scsi/sr_vendor.c cd->cdi.mask |= CDC_MULTI_SESSION; mask 167 drivers/scsi/sr_vendor.c if (cd->cdi.mask & CDC_MULTI_SESSION) mask 321 drivers/scsi/sr_vendor.c cdi->mask |= CDC_MULTI_SESSION; mask 109 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_set_bits(host, mask, reg) \ mask 111 drivers/scsi/ufs/ufs-hisi.h (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) mask 112 drivers/scsi/ufs/ufs-hisi.h #define ufs_sys_ctrl_clr_bits(host, mask, reg) \ mask 114 drivers/scsi/ufs/ufs-hisi.h ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ mask 1430 drivers/scsi/ufs/ufs-qcom.c u32 mask = TEST_BUS_SUB_SEL_MASK; mask 1486 drivers/scsi/ufs/ufs-qcom.c mask = 0xFFF; mask 1494 drivers/scsi/ufs/ufs-qcom.c mask <<= offset; mask 1501 drivers/scsi/ufs/ufs-qcom.c ufshcd_rmwl(host->hba, mask, mask 554 drivers/scsi/ufs/ufshcd.c int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, mask 562 drivers/scsi/ufs/ufshcd.c val = val & mask; mask 564 drivers/scsi/ufs/ufshcd.c while ((ufshcd_readl(hba, reg) & mask) != val) { mask 570 drivers/scsi/ufs/ufshcd.c if ((ufshcd_readl(hba, reg) & mask) != val) mask 2521 drivers/scsi/ufs/ufshcd.c u32 mask = 1 << tag; mask 2534 drivers/scsi/ufs/ufshcd.c mask, ~mask, 1000, 1000, true); mask 4907 drivers/scsi/ufs/ufshcd.c static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) mask 4912 drivers/scsi/ufs/ufshcd.c if (!(hba->ee_ctrl_mask & mask)) mask 4915 drivers/scsi/ufs/ufshcd.c val = hba->ee_ctrl_mask & ~mask; mask 4920 drivers/scsi/ufs/ufshcd.c hba->ee_ctrl_mask &= ~mask; mask 4935 drivers/scsi/ufs/ufshcd.c static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) mask 4940 drivers/scsi/ufs/ufshcd.c if (hba->ee_ctrl_mask & mask) mask 4943 drivers/scsi/ufs/ufshcd.c val = hba->ee_ctrl_mask | mask; mask 4948 drivers/scsi/ufs/ufshcd.c hba->ee_ctrl_mask |= mask; mask 5645 drivers/scsi/ufs/ufshcd.c u32 mask = 1 << tag; mask 5658 drivers/scsi/ufs/ufshcd.c mask, 0, 1000, 1000, true); mask 792 drivers/scsi/ufs/ufshcd.h static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) mask 797 drivers/scsi/ufs/ufshcd.h tmp &= ~mask; mask 798 drivers/scsi/ufs/ufshcd.h tmp |= (val & mask); mask 806 drivers/scsi/ufs/ufshcd.h int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, mask 95 drivers/scsi/ufs/ufshci.h #define UFS_MASK(mask, offset) ((mask) << (offset)) mask 1918 drivers/scsi/wd33c93.c static inline void set_resync ( struct WD33C93_hostdata *hd, int mask ) mask 1922 drivers/scsi/wd33c93.c if (mask & (1 << i)) mask 70 drivers/sh/intc/access.c unsigned int mask = ((1 << width) - 1) << shift; mask 72 drivers/sh/intc/access.c return (value & mask) >> shift; mask 42 drivers/soc/amlogic/meson-ee-pwrc.c unsigned int mask; mask 266 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.mem_pd[i].mask, mask 267 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.mem_pd[i].mask); mask 301 drivers/soc/amlogic/meson-ee-pwrc.c pwrc_domain->desc.mem_pd[i].mask, 0); mask 205 drivers/soc/bcm/brcmstb/pm/pm-arm.c static inline void shimphy_set(u32 value, u32 mask) mask 217 drivers/soc/bcm/brcmstb/pm/pm-arm.c tmp = value | (tmp & mask); mask 296 drivers/soc/dove/pmu.c gc->chip_types[0].regs.mask = PMC_IRQ_MASK; mask 98 drivers/soc/fsl/dpio/dpio-driver.c cpumask_t mask; mask 115 drivers/soc/fsl/dpio/dpio-driver.c cpumask_clear(&mask); mask 116 drivers/soc/fsl/dpio/dpio-driver.c cpumask_set_cpu(cpu, &mask); mask 117 drivers/soc/fsl/dpio/dpio-driver.c if (irq_set_affinity_hint(irq->msi_desc->irq, &mask)) mask 257 drivers/soc/fsl/dpio/qbman-portal.c void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask) mask 259 drivers/soc/fsl/dpio/qbman-portal.c qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask); mask 278 drivers/soc/fsl/dpio/qbman-portal.c void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask) mask 280 drivers/soc/fsl/dpio/qbman-portal.c qbman_write_register(p, QBMAN_CINH_SWP_IER, mask); mask 140 drivers/soc/fsl/dpio/qbman-portal.h void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask); mask 142 drivers/soc/fsl/dpio/qbman-portal.h void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask); mask 25 drivers/soc/fsl/guts.c u32 mask; mask 43 drivers/soc/fsl/guts.c .mask = 0xfff00000, mask 48 drivers/soc/fsl/guts.c .mask = 0xfff00000, mask 53 drivers/soc/fsl/guts.c .mask = 0xfff00000, mask 58 drivers/soc/fsl/guts.c .mask = 0xfff00000, mask 68 drivers/soc/fsl/guts.c .mask = 0xffff0000, mask 73 drivers/soc/fsl/guts.c .mask = 0xff3f0000, mask 78 drivers/soc/fsl/guts.c .mask = 0xff3f0000, mask 83 drivers/soc/fsl/guts.c .mask = 0xffff0000, mask 88 drivers/soc/fsl/guts.c .mask = 0xffff0000, mask 93 drivers/soc/fsl/guts.c .mask = 0xff3f0000, mask 98 drivers/soc/fsl/guts.c .mask = 0xfff70000, mask 103 drivers/soc/fsl/guts.c .mask = 0xff3f0000, mask 108 drivers/soc/fsl/guts.c .mask = 0xff3f0000, mask 117 drivers/soc/fsl/guts.c if (matches->svr == (svr & matches->mask)) mask 62 drivers/soc/fsl/qbman/bman_ccsr.c u32 mask; mask 172 drivers/soc/fsl/qbman/bman_ccsr.c if (bman_hwerr_txts[i].mask & isr_mask) { mask 175 drivers/soc/fsl/qbman/bman_ccsr.c if (bman_hwerr_txts[i].mask & ecsr_val) { mask 179 drivers/soc/fsl/qbman/bman_ccsr.c if (bman_hwerr_txts[i].mask & BMAN_ERRS_TO_DISABLE) { mask 181 drivers/soc/fsl/qbman/bman_ccsr.c bman_hwerr_txts[i].mask); mask 182 drivers/soc/fsl/qbman/bman_ccsr.c ier_val &= ~bman_hwerr_txts[i].mask; mask 962 drivers/soc/fsl/qbman/qman.c static inline void fq_set(struct qman_fq *fq, u32 mask) mask 964 drivers/soc/fsl/qbman/qman.c fq->flags |= mask; mask 967 drivers/soc/fsl/qbman/qman.c static inline void fq_clear(struct qman_fq *fq, u32 mask) mask 969 drivers/soc/fsl/qbman/qman.c fq->flags &= ~mask; mask 972 drivers/soc/fsl/qbman/qman.c static inline int fq_isset(struct qman_fq *fq, u32 mask) mask 974 drivers/soc/fsl/qbman/qman.c return fq->flags & mask; mask 977 drivers/soc/fsl/qbman/qman.c static inline int fq_isclear(struct qman_fq *fq, u32 mask) mask 979 drivers/soc/fsl/qbman/qman.c return !(fq->flags & mask); mask 216 drivers/soc/fsl/qbman/qman_ccsr.c u32 mask; mask 502 drivers/soc/fsl/qbman/qman_ccsr.c u32 i, j, mask = 0xffffffff; mask 508 drivers/soc/fsl/qbman/qman_ccsr.c mask = ~(mask << bit_count % 32); mask 511 drivers/soc/fsl/qbman/qman_ccsr.c dev_warn(dev, " 0x%08x\n", qm_ccsr_in(REG_EDATA(j)) & mask); mask 584 drivers/soc/fsl/qbman/qman_ccsr.c if (qman_hwerr_txts[i].mask & isr_mask) { mask 587 drivers/soc/fsl/qbman/qman_ccsr.c if (qman_hwerr_txts[i].mask & ecsr_val) { mask 593 drivers/soc/fsl/qbman/qman_ccsr.c if (qman_hwerr_txts[i].mask & QMAN_ERRS_TO_DISABLE) { mask 595 drivers/soc/fsl/qbman/qman_ccsr.c qman_hwerr_txts[i].mask); mask 596 drivers/soc/fsl/qbman/qman_ccsr.c ier_val &= ~qman_hwerr_txts[i].mask; mask 83 drivers/soc/fsl/qe/gpio.c unsigned long *mask, unsigned long *bits) mask 94 drivers/soc/fsl/qe/gpio.c if (*mask == 0) mask 96 drivers/soc/fsl/qe/gpio.c if (__test_and_clear_bit(i, mask)) { mask 35 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00008000, mask 41 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00004000, mask 47 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00002000, mask 53 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000040, mask 59 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000020, mask 65 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000010, mask 71 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000008, mask 77 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000004, mask 83 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00000002, mask 89 drivers/soc/fsl/qe/qe_ic.c .mask = 0x10000000, mask 95 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00800000, mask 101 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00400000, mask 107 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00200000, mask 113 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00100000, mask 119 drivers/soc/fsl/qe/qe_ic.c .mask = 0x80000000, mask 125 drivers/soc/fsl/qe/qe_ic.c .mask = 0x40000000, mask 131 drivers/soc/fsl/qe/qe_ic.c .mask = 0x20000000, mask 137 drivers/soc/fsl/qe/qe_ic.c .mask = 0x10000000, mask 143 drivers/soc/fsl/qe/qe_ic.c .mask = 0x08000000, mask 149 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00800000, mask 155 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00400000, mask 161 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00200000, mask 167 drivers/soc/fsl/qe/qe_ic.c .mask = 0x00100000, mask 206 drivers/soc/fsl/qe/qe_ic.c temp | qe_ic_info[src].mask); mask 222 drivers/soc/fsl/qe/qe_ic.c temp & ~qe_ic_info[src].mask); mask 263 drivers/soc/fsl/qe/qe_ic.c if (qe_ic_info[hw].mask == 0) { mask 92 drivers/soc/fsl/qe/qe_ic.h u32 mask; /* location of this source at the QIMR register. */ mask 134 drivers/soc/fsl/qe/qe_tdm.c u32 mask; mask 155 drivers/soc/fsl/qe/qe_tdm.c mask = 0x01 << i; mask 157 drivers/soc/fsl/qe/qe_tdm.c if (utdm->tx_ts_mask & mask) mask 164 drivers/soc/fsl/qe/qe_tdm.c if (utdm->rx_ts_mask & mask) mask 99 drivers/soc/fsl/qe/ucc.c int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask) mask 112 drivers/soc/fsl/qe/ucc.c setbits32(cmxucr, mask << shift); mask 114 drivers/soc/fsl/qe/ucc.c clrbits32(cmxucr, mask << shift); mask 207 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 mask = 1 << (queue & (HALF_QUEUES - 1)); mask 210 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, mask 219 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 mask = 1 << (queue & (HALF_QUEUES - 1)); mask 222 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, mask 224 drivers/soc/ixp4xx/ixp4xx-qmgr.c __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ mask 228 drivers/soc/ixp4xx/ixp4xx-qmgr.c static inline void shift_mask(u32 *mask) mask 230 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[3] = mask[3] << 1 | mask[2] >> 31; mask 231 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[2] = mask[2] << 1 | mask[1] >> 31; mask 232 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[1] = mask[1] << 1 | mask[0] >> 31; mask 233 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[0] <<= 1; mask 247 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ mask 258 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[0] = 0x1; mask 262 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[0] = 0x3; mask 266 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[0] = 0xF; mask 270 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[0] = 0xFF; mask 279 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[1] = mask[2] = mask[3] = 0; mask 291 drivers/soc/ixp4xx/ixp4xx-qmgr.c if (!(used_sram_bitmap[0] & mask[0]) && mask 292 drivers/soc/ixp4xx/ixp4xx-qmgr.c !(used_sram_bitmap[1] & mask[1]) && mask 293 drivers/soc/ixp4xx/ixp4xx-qmgr.c !(used_sram_bitmap[2] & mask[2]) && mask 294 drivers/soc/ixp4xx/ixp4xx-qmgr.c !(used_sram_bitmap[3] & mask[3])) mask 298 drivers/soc/ixp4xx/ixp4xx-qmgr.c shift_mask(mask); mask 307 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[0] |= mask[0]; mask 308 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[1] |= mask[1]; mask 309 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[2] |= mask[2]; mask 310 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[3] |= mask[3]; mask 329 drivers/soc/ixp4xx/ixp4xx-qmgr.c u32 cfg, addr, mask[4]; mask 340 drivers/soc/ixp4xx/ixp4xx-qmgr.c case 0: mask[0] = 0x1; break; mask 341 drivers/soc/ixp4xx/ixp4xx-qmgr.c case 1: mask[0] = 0x3; break; mask 342 drivers/soc/ixp4xx/ixp4xx-qmgr.c case 2: mask[0] = 0xF; break; mask 343 drivers/soc/ixp4xx/ixp4xx-qmgr.c case 3: mask[0] = 0xFF; break; mask 346 drivers/soc/ixp4xx/ixp4xx-qmgr.c mask[1] = mask[2] = mask[3] = 0; mask 349 drivers/soc/ixp4xx/ixp4xx-qmgr.c shift_mask(mask); mask 363 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[0] &= ~mask[0]; mask 364 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[1] &= ~mask[1]; mask 365 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[2] &= ~mask[2]; mask 366 drivers/soc/ixp4xx/ixp4xx-qmgr.c used_sram_bitmap[3] &= ~mask[3]; mask 150 drivers/soc/mediatek/mtk-cmdq-helper.c u16 offset, u32 value, u32 mask) mask 155 drivers/soc/mediatek/mtk-cmdq-helper.c if (mask != 0xffffffff) { mask 156 drivers/soc/mediatek/mtk-cmdq-helper.c err = cmdq_pkt_append_command(pkt, CMDQ_CODE_MASK, 0, ~mask); mask 32 drivers/soc/mediatek/mtk-infracfg.c int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, mask 39 drivers/soc/mediatek/mtk-infracfg.c regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask 40 drivers/soc/mediatek/mtk-infracfg.c mask); mask 42 drivers/soc/mediatek/mtk-infracfg.c regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); mask 45 drivers/soc/mediatek/mtk-infracfg.c val, (val & mask) == mask, mask 63 drivers/soc/mediatek/mtk-infracfg.c int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, mask 70 drivers/soc/mediatek/mtk-infracfg.c regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); mask 72 drivers/soc/mediatek/mtk-infracfg.c regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); mask 75 drivers/soc/mediatek/mtk-infracfg.c val, !(val & mask), mask 134 drivers/soc/qcom/qcom_gsbi.c u32 mask, gsbi_num; mask 199 drivers/soc/qcom/qcom_gsbi.c mask = config->array[i][gsbi_num - 1]; mask 203 drivers/soc/qcom/qcom_gsbi.c TCSR_ADM_CRCI_BASE + 4 * i, mask, 0); mask 206 drivers/soc/qcom/qcom_gsbi.c TCSR_ADM_CRCI_BASE + 4 * i, mask, mask); mask 39 drivers/soc/qcom/rpmh-internal.h u32 mask; mask 197 drivers/soc/qcom/rpmh-rsc.c if (tcs->mask & BIT(tcs_id)) mask 593 drivers/soc/qcom/rpmh-rsc.c st + tcs->num_tcs >= BITS_PER_BYTE * sizeof(tcs->mask)) mask 596 drivers/soc/qcom/rpmh-rsc.c tcs->mask = ((1 << tcs->num_tcs) - 1) << st; mask 667 drivers/soc/qcom/rpmh-rsc.c write_tcs_reg(drv, RSC_DRV_IRQ_ENABLE, 0, drv->tcs[ACTIVE_TCS].mask); mask 46 drivers/soc/qcom/smem_state.c u32 mask, mask 55 drivers/soc/qcom/smem_state.c return state->ops.update_bits(state->priv, mask, value); mask 318 drivers/soc/qcom/smp2p.c static int smp2p_update_bits(void *data, u32 mask, u32 value) mask 326 drivers/soc/qcom/smp2p.c val &= ~mask; mask 139 drivers/soc/qcom/smsm.c static int smsm_update_bits(void *data, u32 mask, u32 value) mask 153 drivers/soc/qcom/smsm.c val &= ~mask; mask 211 drivers/soc/qcom/spm.c cpumask_t mask; mask 257 drivers/soc/qcom/spm.c cpumask_clear(&mask); mask 258 drivers/soc/qcom/spm.c cpumask_set_cpu(cpu, &mask); mask 259 drivers/soc/qcom/spm.c qcom_scm_set_warm_boot_addr(cpu_resume_arm, &mask); mask 51 drivers/soc/renesas/rmobile-sysc.c unsigned int mask = BIT(rmobile_pd->bit_shift); mask 60 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) { mask 62 drivers/soc/renesas/rmobile-sysc.c __raw_writel(mask, rmobile_pd->base + SPDCR); mask 65 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SPDCR) & mask)) mask 71 drivers/soc/renesas/rmobile-sysc.c pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask, mask 79 drivers/soc/renesas/rmobile-sysc.c unsigned int mask = BIT(rmobile_pd->bit_shift); mask 83 drivers/soc/renesas/rmobile-sysc.c if (__raw_readl(rmobile_pd->base + PSTR) & mask) mask 86 drivers/soc/renesas/rmobile-sysc.c __raw_writel(mask, rmobile_pd->base + SWUCR); mask 89 drivers/soc/renesas/rmobile-sysc.c if (!(__raw_readl(rmobile_pd->base + SWUCR) & mask)) mask 100 drivers/soc/renesas/rmobile-sysc.c rmobile_pd->genpd.name, mask, mask 14 drivers/soc/rockchip/grf.c #define HIWORD_UPDATE(val, mask, shift) \ mask 15 drivers/soc/rockchip/grf.c ((val) << (shift) | (mask) << ((shift) + 16)) mask 226 drivers/soc/sunxi/sunxi_sram.c u32 val, mask; mask 250 drivers/soc/sunxi/sunxi_sram.c mask = GENMASK(sram_data->offset + sram_data->width - 1, mask 253 drivers/soc/sunxi/sunxi_sram.c val &= ~mask; mask 254 drivers/soc/sunxi/sunxi_sram.c writel(val | ((device << sram_data->offset) & mask), mask 97 drivers/soc/tegra/fuse/fuse-tegra20.c dma_cap_mask_t mask; mask 99 drivers/soc/tegra/fuse/fuse-tegra20.c dma_cap_zero(mask); mask 100 drivers/soc/tegra/fuse/fuse-tegra20.c dma_cap_set(DMA_SLAVE, mask); mask 102 drivers/soc/tegra/fuse/fuse-tegra20.c fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL); mask 496 drivers/soc/tegra/pmc.c u32 mask; mask 516 drivers/soc/tegra/pmc.c mask = (1 << TEGRA_POWERGATE_PCIE); mask 518 drivers/soc/tegra/pmc.c mask = (1 << TEGRA_POWERGATE_VDEC); mask 520 drivers/soc/tegra/pmc.c mask = (1 << id); mask 522 drivers/soc/tegra/pmc.c tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); mask 1157 drivers/soc/tegra/pmc.c u32 *mask) mask 1170 drivers/soc/tegra/pmc.c *mask = BIT(pad->dpd % 32); mask 1185 drivers/soc/tegra/pmc.c u32 *mask) mask 1190 drivers/soc/tegra/pmc.c err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); mask 1213 drivers/soc/tegra/pmc.c u32 mask, u32 val, unsigned long timeout) mask 1221 drivers/soc/tegra/pmc.c if ((value & mask) == val) mask 1245 drivers/soc/tegra/pmc.c u32 mask; mask 1250 drivers/soc/tegra/pmc.c err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); mask 1256 drivers/soc/tegra/pmc.c tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); mask 1258 drivers/soc/tegra/pmc.c err = tegra_io_pad_poll(pmc, status, mask, 0, 250); mask 1281 drivers/soc/tegra/pmc.c u32 mask; mask 1286 drivers/soc/tegra/pmc.c err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); mask 1292 drivers/soc/tegra/pmc.c tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); mask 1294 drivers/soc/tegra/pmc.c err = tegra_io_pad_poll(pmc, status, mask, mask, 250); mask 1311 drivers/soc/tegra/pmc.c u32 mask, value; mask 1315 drivers/soc/tegra/pmc.c &mask); mask 1321 drivers/soc/tegra/pmc.c return !(value & mask); mask 58 drivers/soc/ti/knav_qmss_acc.c u32 mask, offset; mask 69 drivers/soc/ti/knav_qmss_acc.c mask = BIT(kq->acc->channel % 32); mask 73 drivers/soc/ti/knav_qmss_acc.c writel_relaxed(mask, pdsp->intd + offset); mask 1256 drivers/soc/ti/knav_qmss_queue.c unsigned long mask; mask 1264 drivers/soc/ti/knav_qmss_queue.c mask = (oirq.args[2] & 0x0000ff00) >> 8; mask 1265 drivers/soc/ti/knav_qmss_queue.c for_each_set_bit(bit, &mask, BITS_PER_LONG) mask 269 drivers/soc/xilinx/xlnx_vcu.c u32 field, u32 mask, int shift) mask 273 drivers/soc/xilinx/xlnx_vcu.c val &= ~(mask << shift); mask 274 drivers/soc/xilinx/xlnx_vcu.c val |= (field & mask) << shift; mask 608 drivers/soundwire/bus.c int port, bool enable, int mask) mask 618 drivers/soundwire/bus.c val |= mask; mask 621 drivers/soundwire/bus.c val &= ~(mask); mask 625 drivers/soundwire/bus.c ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val); mask 142 drivers/soundwire/bus.h bool enable, int mask); mask 155 drivers/soundwire/bus.h sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val) mask 163 drivers/soundwire/bus.h tmp = (tmp & ~mask) | val; mask 205 drivers/soundwire/cadence_master.c int offset, u32 mask, u32 val) mask 210 drivers/soundwire/cadence_master.c tmp = (tmp & ~mask) | val; mask 605 drivers/soundwire/cadence_master.c u32 mask; mask 613 drivers/soundwire/cadence_master.c mask = (slave >> (i * CDNS_MCP_SLAVE_STATUS_NUM)) & mask 615 drivers/soundwire/cadence_master.c if (!mask) mask 621 drivers/soundwire/cadence_master.c if (mask & CDNS_MCP_SLAVE_INTSTAT_RESERVED) { mask 626 drivers/soundwire/cadence_master.c if (mask & CDNS_MCP_SLAVE_INTSTAT_ATTACHED) { mask 631 drivers/soundwire/cadence_master.c if (mask & CDNS_MCP_SLAVE_INTSTAT_ALERT) { mask 636 drivers/soundwire/cadence_master.c if (mask & CDNS_MCP_SLAVE_INTSTAT_NPRESENT) { mask 645 drivers/soundwire/cadence_master.c mask); mask 757 drivers/soundwire/cadence_master.c u32 mask; mask 765 drivers/soundwire/cadence_master.c mask = CDNS_MCP_INT_SLAVE_MASK; mask 768 drivers/soundwire/cadence_master.c mask |= CDNS_MCP_INT_CTRL_CLASH | CDNS_MCP_INT_DATA_CLASH | mask 774 drivers/soundwire/cadence_master.c mask |= CDNS_MCP_INT_RX_WL; mask 780 drivers/soundwire/cadence_master.c mask |= CDNS_MCP_INT_IRQ; mask 783 drivers/soundwire/cadence_master.c mask = interrupt_mask; mask 785 drivers/soundwire/cadence_master.c cdns_writel(cdns, CDNS_MCP_INTMASK, mask); mask 136 drivers/soundwire/intel.c static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) mask 144 drivers/soundwire/intel.c if (!(reg_read & mask)) mask 154 drivers/soundwire/intel.c static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) mask 162 drivers/soundwire/intel.c if (reg_read & mask) mask 434 drivers/spi/atmel-quadspi.c u32 status, mask, pending; mask 437 drivers/spi/atmel-quadspi.c mask = readl_relaxed(aq->regs + QSPI_IMR); mask 438 drivers/spi/atmel-quadspi.c pending = status & mask; mask 129 drivers/spi/spi-at91-usart.c dma_cap_mask_t mask; mask 132 drivers/spi/spi-at91-usart.c dma_cap_zero(mask); mask 133 drivers/spi/spi-at91-usart.c dma_cap_set(DMA_SLAVE, mask); mask 525 drivers/spi/spi-atmel.c dma_cap_mask_t mask; mask 526 drivers/spi/spi-atmel.c dma_cap_zero(mask); mask 527 drivers/spi/spi-atmel.c dma_cap_set(DMA_SLAVE, mask); mask 469 drivers/spi/spi-au1550.c #define AU1550_SPI_RX_WORD(size, mask) \ mask 472 drivers/spi/spi-au1550.c u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ mask 481 drivers/spi/spi-au1550.c #define AU1550_SPI_TX_WORD(size, mask) \ mask 486 drivers/spi/spi-au1550.c fifoword = *(u##size *)hw->tx & (u32)(mask); \ mask 505 drivers/spi/spi-au1550.c u32 stat, mask; mask 515 drivers/spi/spi-au1550.c mask = PSC_SPIMSK_SD; mask 524 drivers/spi/spi-au1550.c mask |= PSC_SPIMSK_TR; mask 534 drivers/spi/spi-au1550.c hw->regs->psc_spimsk = mask; mask 186 drivers/spi/spi-axi-spi-engine.c unsigned int mask = 0xff; mask 189 drivers/spi/spi-axi-spi-engine.c mask ^= BIT(spi->chip_select); mask 191 drivers/spi/spi-axi-spi-engine.c spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask)); mask 176 drivers/spi/spi-bcm-qspi.c u32 mask; mask 443 drivers/spi/spi-bcm-qspi.c u32 val, mask; mask 446 drivers/spi/spi-bcm-qspi.c mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; mask 447 drivers/spi/spi-bcm-qspi.c if (val & mask || qspi->s3_strap_override_ctrl & mask) { mask 1025 drivers/spi/spi-bcm-qspi.c u32 status = qspi_dev_id->irqp->mask; mask 1098 drivers/spi/spi-bcm-qspi.c .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK, mask 1103 drivers/spi/spi-bcm-qspi.c .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK, mask 1108 drivers/spi/spi-bcm-qspi.c .mask = INTR_BSPI_LR_IMPATIENT_MASK, mask 1113 drivers/spi/spi-bcm-qspi.c .mask = INTR_BSPI_LR_SESSION_DONE_MASK, mask 1120 drivers/spi/spi-bcm-qspi.c .mask = INTR_BSPI_LR_OVERREAD_MASK, mask 1126 drivers/spi/spi-bcm-qspi.c .mask = INTR_MSPI_DONE_MASK, mask 1131 drivers/spi/spi-bcm-qspi.c .mask = INTR_MSPI_HALTED_MASK, mask 1138 drivers/spi/spi-bcm-qspi.c .mask = QSPI_INTERRUPTS_ALL, mask 43 drivers/spi/spi-dw-mid.c dma_cap_mask_t mask; mask 53 drivers/spi/spi-dw-mid.c dma_cap_zero(mask); mask 54 drivers/spi/spi-dw-mid.c dma_cap_set(DMA_SLAVE, mask); mask 58 drivers/spi/spi-dw-mid.c dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, rx); mask 65 drivers/spi/spi-dw-mid.c dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, tx); mask 204 drivers/spi/spi-dw.h static inline void spi_mask_intr(struct dw_spi *dws, u32 mask) mask 208 drivers/spi/spi-dw.h new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask; mask 213 drivers/spi/spi-dw.h static inline void spi_umask_intr(struct dw_spi *dws, u32 mask) mask 217 drivers/spi/spi-dw.h new_mask = dw_readl(dws, DW_SPI_IMR) | mask; mask 20 drivers/spi/spi-efm32.c #define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) mask 585 drivers/spi/spi-ep93xx.c dma_cap_mask_t mask; mask 592 drivers/spi/spi-ep93xx.c dma_cap_zero(mask); mask 593 drivers/spi/spi-ep93xx.c dma_cap_set(DMA_SLAVE, mask); mask 599 drivers/spi/spi-ep93xx.c espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter, mask 610 drivers/spi/spi-ep93xx.c espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter, mask 149 drivers/spi/spi-fsl-cpm.c mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB); mask 356 drivers/spi/spi-fsl-espi.c u32 mask, spcom; mask 376 drivers/spi/spi-fsl-espi.c mask = SPIM_DON; mask 378 drivers/spi/spi-fsl-espi.c mask |= SPIM_RXT; mask 379 drivers/spi/spi-fsl-espi.c fsl_espi_write_reg(espi, ESPI_SPIM, mask); mask 619 drivers/spi/spi-fsl-qspi.c u32 mask, u32 delay_us, u32 timeout_us) mask 624 drivers/spi/spi-fsl-qspi.c mask = (u32)cpu_to_be32(mask); mask 626 drivers/spi/spi-fsl-qspi.c return readl_poll_timeout(base, reg, !(reg & mask), delay_us, mask 299 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); mask 350 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, 0); mask 657 drivers/spi/spi-fsl-spi.c mpc8xxx_spi_write_reg(®_base->mask, 0); mask 28 drivers/spi/spi-fsl-spi.h __be32 mask; mask 59 drivers/spi/spi-iproc-qspi.c u32 mask = get_qspi_mask(type); mask 63 drivers/spi/spi-iproc-qspi.c if (mask & (1UL << i)) mask 74 drivers/spi/spi-iproc-qspi.c u32 mask = get_qspi_mask(type); mask 83 drivers/spi/spi-iproc-qspi.c val = val | (mask << INTR_BASE_BIT_SHIFT); mask 85 drivers/spi/spi-iproc-qspi.c val = val & ~(mask << INTR_BASE_BIT_SHIFT); mask 117 drivers/spi/spi-meson-spicc.c #define writel_bits_relaxed(mask, val, addr) \ mask 118 drivers/spi/spi-meson-spicc.c writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) mask 125 drivers/spi/spi-mxs.c static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) mask 137 drivers/spi/spi-mxs.c reg &= mask; mask 139 drivers/spi/spi-mxs.c if (reg == mask) mask 73 drivers/spi/spi-npcm-pspi.c static inline void npcm_pspi_irq_enable(struct npcm_pspi *priv, u16 mask) mask 78 drivers/spi/spi-npcm-pspi.c val |= mask; mask 82 drivers/spi/spi-npcm-pspi.c static inline void npcm_pspi_irq_disable(struct npcm_pspi *priv, u16 mask) mask 87 drivers/spi/spi-npcm-pspi.c val &= ~mask; mask 447 drivers/spi/spi-nxp-fspi.c u32 mask, u32 delay_us, mask 453 drivers/spi/spi-nxp-fspi.c mask = (u32)cpu_to_be32(mask); mask 456 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, (reg & mask), mask 459 drivers/spi/spi-nxp-fspi.c return readl_poll_timeout(base, reg, !(reg & mask), mask 141 drivers/spi/spi-omap-uwire.c static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch) mask 149 drivers/spi/spi-omap-uwire.c if ((w & mask) == val) mask 154 drivers/spi/spi-omap-uwire.c __func__, w, mask, val); mask 112 drivers/spi/spi-orion.c orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask) mask 118 drivers/spi/spi-orion.c val |= mask; mask 123 drivers/spi/spi-orion.c orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask) mask 129 drivers/spi/spi-orion.c val &= ~mask; mask 186 drivers/spi/spi-pic32-sqi.c u32 mask = PESQI_DMAERR | PESQI_BDDONE | PESQI_PKTCOMP; mask 188 drivers/spi/spi-pic32-sqi.c writel(mask, sqi->regs + PESQI_INT_ENABLE_REG); mask 190 drivers/spi/spi-pic32-sqi.c writel(mask, sqi->regs + PESQI_INT_SIGEN_REG); mask 612 drivers/spi/spi-pic32.c dma_cap_mask_t mask; mask 614 drivers/spi/spi-pic32.c dma_cap_zero(mask); mask 615 drivers/spi/spi-pic32.c dma_cap_set(DMA_SLAVE, mask); mask 617 drivers/spi/spi-pic32.c master->dma_rx = dma_request_slave_channel_compat(mask, NULL, NULL, mask 624 drivers/spi/spi-pic32.c master->dma_tx = dma_request_slave_channel_compat(mask, NULL, NULL, mask 43 drivers/spi/spi-pl022.c #define SSP_WRITE_BITS(reg, val, mask, sb) \ mask 44 drivers/spi/spi-pl022.c ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask)))) mask 51 drivers/spi/spi-pl022.c #define GEN_MASK_BITS(val, mask, sb) \ mask 52 drivers/spi/spi-pl022.c (((val)<<(sb)) & (mask)) mask 1109 drivers/spi/spi-pl022.c dma_cap_mask_t mask; mask 1112 drivers/spi/spi-pl022.c dma_cap_zero(mask); mask 1113 drivers/spi/spi-pl022.c dma_cap_set(DMA_SLAVE, mask); mask 1118 drivers/spi/spi-pl022.c pl022->dma_rx_channel = dma_request_channel(mask, mask 1126 drivers/spi/spi-pl022.c pl022->dma_tx_channel = dma_request_channel(mask, mask 2452 drivers/spi/spi-pl022.c .mask = 0x000fffff, mask 2461 drivers/spi/spi-pl022.c .mask = 0xffffffff, mask 2473 drivers/spi/spi-pl022.c .mask = 0xffffffff, mask 2482 drivers/spi/spi-pl022.c .mask = 0x000fffff, mask 196 drivers/spi/spi-pxa2xx-dma.c dma_cap_mask_t mask; mask 198 drivers/spi/spi-pxa2xx-dma.c dma_cap_zero(mask); mask 199 drivers/spi/spi-pxa2xx-dma.c dma_cap_set(DMA_SLAVE, mask); mask 201 drivers/spi/spi-pxa2xx-dma.c controller->dma_tx = dma_request_slave_channel_compat(mask, mask 206 drivers/spi/spi-pxa2xx-dma.c controller->dma_rx = dma_request_slave_channel_compat(mask, mask 220 drivers/spi/spi-pxa2xx.c u32 mask; mask 224 drivers/spi/spi-pxa2xx.c mask = QUARK_X1000_SSSR_TFL_MASK; mask 227 drivers/spi/spi-pxa2xx.c mask = CE4100_SSSR_TFL_MASK; mask 230 drivers/spi/spi-pxa2xx.c mask = SSSR_TFL_MASK; mask 234 drivers/spi/spi-pxa2xx.c return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; mask 240 drivers/spi/spi-pxa2xx.c u32 mask; mask 244 drivers/spi/spi-pxa2xx.c mask = QUARK_X1000_SSCR1_RFT; mask 247 drivers/spi/spi-pxa2xx.c mask = CE4100_SSCR1_RFT; mask 250 drivers/spi/spi-pxa2xx.c mask = SSCR1_RFT; mask 253 drivers/spi/spi-pxa2xx.c *sccr1_reg &= ~mask; mask 726 drivers/spi/spi-pxa2xx.c u32 mask = drv_data->mask_sr; mask 752 drivers/spi/spi-pxa2xx.c mask &= ~SSSR_TFS; mask 756 drivers/spi/spi-pxa2xx.c mask &= ~SSSR_TINT; mask 758 drivers/spi/spi-pxa2xx.c if (!(status & mask)) mask 829 drivers/spi/spi-qup.c u32 mask = 0; mask 837 drivers/spi/spi-qup.c mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG; mask 839 drivers/spi/spi-qup.c writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); mask 381 drivers/spi/spi-rspi.c static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg) mask 386 drivers/spi/spi-rspi.c data &= ~mask; mask 387 drivers/spi/spi-rspi.c data |= (val & mask); mask 1030 drivers/spi/spi-rspi.c dma_cap_mask_t mask; mask 1035 drivers/spi/spi-rspi.c dma_cap_zero(mask); mask 1036 drivers/spi/spi-rspi.c dma_cap_set(DMA_SLAVE, mask); mask 1038 drivers/spi/spi-rspi.c chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, mask 56 drivers/spi/spi-sh-hspi.c static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set) mask 60 drivers/spi/spi-sh-hspi.c val &= ~mask; mask 61 drivers/spi/spi-sh-hspi.c val |= set & mask; mask 69 drivers/spi/spi-sh-hspi.c static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) mask 74 drivers/spi/spi-sh-hspi.c if ((mask & hspi_read(hspi, SPSR)) == val) mask 223 drivers/spi/spi-sh-msiof.c u32 mask = clr | set; mask 232 drivers/spi/spi-sh-msiof.c (data & mask) == set, 1, 100); mask 248 drivers/spi/spi-sh-msiof.c u32 mask = CTR_TXRST | CTR_RXRST; mask 252 drivers/spi/spi-sh-msiof.c data |= mask; mask 255 drivers/spi/spi-sh-msiof.c readl_poll_timeout_atomic(p->mapbase + CTR, data, !(data & mask), 1, mask 1170 drivers/spi/spi-sh-msiof.c dma_cap_mask_t mask; mask 1175 drivers/spi/spi-sh-msiof.c dma_cap_zero(mask); mask 1176 drivers/spi/spi-sh-msiof.c dma_cap_set(DMA_SLAVE, mask); mask 1178 drivers/spi/spi-sh-msiof.c chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, mask 186 drivers/spi/spi-stm32.c int mask; mask 643 drivers/spi/spi-stm32.c spi->cfg->regs->en.mask); mask 791 drivers/spi/spi-stm32.c u32 sr, mask = 0; mask 808 drivers/spi/spi-stm32.c mask |= STM32F4_SPI_SR_TXE; mask 814 drivers/spi/spi-stm32.c mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; mask 817 drivers/spi/spi-stm32.c if (!(sr & mask)) { mask 894 drivers/spi/spi-stm32.c u32 sr, ier, mask; mask 903 drivers/spi/spi-stm32.c mask = ier; mask 905 drivers/spi/spi-stm32.c mask |= STM32H7_SPI_SR_SUSP; mask 912 drivers/spi/spi-stm32.c mask |= STM32H7_SPI_SR_RXP; mask 914 drivers/spi/spi-stm32.c if (!(sr & mask)) { mask 964 drivers/spi/spi-stm32.c writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); mask 1017 drivers/spi/spi-stm32.c setb |= spi->cfg->regs->cpol.mask; mask 1019 drivers/spi/spi-stm32.c clrb |= spi->cfg->regs->cpol.mask; mask 1022 drivers/spi/spi-stm32.c setb |= spi->cfg->regs->cpha.mask; mask 1024 drivers/spi/spi-stm32.c clrb |= spi->cfg->regs->cpha.mask; mask 1027 drivers/spi/spi-stm32.c setb |= spi->cfg->regs->lsb_first.mask; mask 1029 drivers/spi/spi-stm32.c clrb |= spi->cfg->regs->lsb_first.mask; mask 1290 drivers/spi/spi-stm32.c spi->cfg->regs->dma_rx_en.mask); mask 1346 drivers/spi/spi-stm32.c spi->cfg->regs->dma_tx_en.mask); mask 1361 drivers/spi/spi-stm32.c spi->cfg->regs->dma_rx_en.mask); mask 1420 drivers/spi/spi-stm32.c clrb |= spi->cfg->regs->br.mask; mask 1422 drivers/spi/spi-stm32.c spi->cfg->regs->br.mask; mask 109 drivers/spi/spi-sun4i.c static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask) mask 113 drivers/spi/spi-sun4i.c reg |= mask; mask 117 drivers/spi/spi-sun4i.c static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask) mask 121 drivers/spi/spi-sun4i.c reg &= ~mask; mask 121 drivers/spi/spi-sun6i.c static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) mask 125 drivers/spi/spi-sun6i.c reg |= mask; mask 129 drivers/spi/spi-sun6i.c static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) mask 133 drivers/spi/spi-sun6i.c reg &= ~mask; mask 673 drivers/spi/spi-ti-qspi.c dma_cap_mask_t mask; mask 767 drivers/spi/spi-ti-qspi.c dma_cap_zero(mask); mask 768 drivers/spi/spi-ti-qspi.c dma_cap_set(DMA_MEMCPY, mask); mask 770 drivers/spi/spi-ti-qspi.c qspi->rx_chan = dma_request_chan_by_mask(&mask); mask 843 drivers/spi/spi-topcliff-pch.c dma_cap_mask_t mask; mask 856 drivers/spi/spi-topcliff-pch.c dma_cap_zero(mask); mask 857 drivers/spi/spi-topcliff-pch.c dma_cap_set(DMA_SLAVE, mask); mask 869 drivers/spi/spi-topcliff-pch.c chan = dma_request_channel(mask, pch_spi_filter, param); mask 884 drivers/spi/spi-topcliff-pch.c chan = dma_request_channel(mask, pch_spi_filter, param); mask 96 drivers/spi/spi-uniphier.c static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask) mask 102 drivers/spi/spi-uniphier.c val |= mask; mask 106 drivers/spi/spi-uniphier.c static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask) mask 112 drivers/spi/spi-uniphier.c val &= ~mask; mask 620 drivers/spi/spi-zynqmp-gqspi.c u32 status, mask, dma_status = 0; mask 624 drivers/spi/spi-zynqmp-gqspi.c mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST))); mask 634 drivers/spi/spi-zynqmp-gqspi.c if (mask & GQSPI_ISR_TXNOT_FULL_MASK) { mask 642 drivers/spi/spi-zynqmp-gqspi.c } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) && mask 643 drivers/spi/spi-zynqmp-gqspi.c (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { mask 666 drivers/spi/spi-zynqmp-gqspi.c u32 mask = 0; mask 670 drivers/spi/spi-zynqmp-gqspi.c mask = GQSPI_GENFIFO_MODE_DUALSPI; mask 673 drivers/spi/spi-zynqmp-gqspi.c mask = GQSPI_GENFIFO_MODE_QUADSPI; mask 676 drivers/spi/spi-zynqmp-gqspi.c mask = GQSPI_GENFIFO_MODE_SPI; mask 682 drivers/spi/spi-zynqmp-gqspi.c return mask; mask 33 drivers/ssb/driver_chipcommon.c u32 mask, u32 value) mask 35 drivers/ssb/driver_chipcommon.c value &= mask; mask 36 drivers/ssb/driver_chipcommon.c value |= chipco_read32(cc, offset) & ~mask; mask 494 drivers/ssb/driver_chipcommon.c void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 496 drivers/ssb/driver_chipcommon.c chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value); mask 499 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) mask 501 drivers/ssb/driver_chipcommon.c return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask; mask 504 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) mask 506 drivers/ssb/driver_chipcommon.c return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; mask 509 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 515 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); mask 521 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 527 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); mask 533 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 539 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); mask 546 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 552 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); mask 558 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 564 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); mask 570 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 579 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value); mask 585 drivers/ssb/driver_chipcommon.c u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value) mask 594 drivers/ssb/driver_chipcommon.c res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value); mask 36 drivers/ssb/driver_chipcommon_pmu.c u32 offset, u32 mask, u32 set) mask 44 drivers/ssb/driver_chipcommon_pmu.c value &= mask; mask 544 drivers/ssb/driver_chipcommon_pmu.c u32 addr, shift, mask; mask 553 drivers/ssb/driver_chipcommon_pmu.c mask = 0xF; mask 558 drivers/ssb/driver_chipcommon_pmu.c mask = 0xF; mask 563 drivers/ssb/driver_chipcommon_pmu.c mask = 0xF; mask 568 drivers/ssb/driver_chipcommon_pmu.c mask = 0x3F; mask 580 drivers/ssb/driver_chipcommon_pmu.c mask = 0x3F; mask 586 drivers/ssb/driver_chipcommon_pmu.c ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift), mask 587 drivers/ssb/driver_chipcommon_pmu.c (voltage & mask) << shift); mask 31 drivers/ssb/driver_extif.c u32 mask, u32 value) mask 33 drivers/ssb/driver_extif.c value &= mask; mask 34 drivers/ssb/driver_extif.c value |= extif_read32(extif, offset) & ~mask; mask 148 drivers/ssb/driver_extif.c u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) mask 150 drivers/ssb/driver_extif.c return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask; mask 153 drivers/ssb/driver_extif.c u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) mask 160 drivers/ssb/driver_extif.c mask, value); mask 166 drivers/ssb/driver_extif.c u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) mask 173 drivers/ssb/driver_extif.c mask, value); mask 179 drivers/ssb/driver_extif.c u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) mask 185 drivers/ssb/driver_extif.c res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); mask 191 drivers/ssb/driver_extif.c u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) mask 197 drivers/ssb/driver_extif.c res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); mask 126 drivers/ssb/driver_gpio.c u32 mask = chipco_read32(chipco, SSB_CHIPCO_GPIOIRQ); mask 128 drivers/ssb/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; mask 323 drivers/ssb/driver_gpio.c u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK); mask 325 drivers/ssb/driver_gpio.c unsigned long irqs = (val ^ pol) & mask; mask 69 drivers/ssb/embedded.c u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask) mask 76 drivers/ssb/embedded.c res = ssb_chipco_gpio_in(&bus->chipco, mask); mask 78 drivers/ssb/embedded.c res = ssb_extif_gpio_in(&bus->extif, mask); mask 87 drivers/ssb/embedded.c u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value) mask 94 drivers/ssb/embedded.c res = ssb_chipco_gpio_out(&bus->chipco, mask, value); mask 96 drivers/ssb/embedded.c res = ssb_extif_gpio_out(&bus->extif, mask, value); mask 105 drivers/ssb/embedded.c u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value) mask 112 drivers/ssb/embedded.c res = ssb_chipco_gpio_outen(&bus->chipco, mask, value); mask 114 drivers/ssb/embedded.c res = ssb_extif_gpio_outen(&bus->extif, mask, value); mask 123 drivers/ssb/embedded.c u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value) mask 130 drivers/ssb/embedded.c res = ssb_chipco_gpio_control(&bus->chipco, mask, value); mask 137 drivers/ssb/embedded.c u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value) mask 144 drivers/ssb/embedded.c res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value); mask 146 drivers/ssb/embedded.c res = ssb_extif_gpio_intmask(&bus->extif, mask, value); mask 155 drivers/ssb/embedded.c u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value) mask 162 drivers/ssb/embedded.c res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value); mask 164 drivers/ssb/embedded.c res = ssb_extif_gpio_polarity(&bus->extif, mask, value); mask 328 drivers/ssb/pci.c u16 mask, u16 shift) mask 334 drivers/ssb/pci.c gain = (v & mask) >> shift; mask 625 drivers/staging/comedi/comedi_fops.c unsigned int mask, mask 631 drivers/staging/comedi/comedi_fops.c __comedi_clear_subdevice_runflags(s, mask); mask 632 drivers/staging/comedi/comedi_fops.c __comedi_set_subdevice_runflags(s, bits & mask); mask 2403 drivers/staging/comedi/comedi_fops.c __poll_t mask = 0; mask 2422 drivers/staging/comedi/comedi_fops.c mask |= EPOLLIN | EPOLLRDNORM; mask 2434 drivers/staging/comedi/comedi_fops.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2439 drivers/staging/comedi/comedi_fops.c return mask; mask 1001 drivers/staging/comedi/comedidev.h unsigned int mask); mask 20 drivers/staging/comedi/comedilib.h unsigned int mask, unsigned int *bits, mask 340 drivers/staging/comedi/drivers.c unsigned int mask) mask 344 drivers/staging/comedi/drivers.c if (!mask) mask 345 drivers/staging/comedi/drivers.c mask = chan_mask; mask 349 drivers/staging/comedi/drivers.c s->io_bits &= ~mask; mask 353 drivers/staging/comedi/drivers.c s->io_bits |= mask; mask 357 drivers/staging/comedi/drivers.c data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT; mask 387 drivers/staging/comedi/drivers.c unsigned int mask = data[0] & chanmask; mask 390 drivers/staging/comedi/drivers.c if (mask) { mask 391 drivers/staging/comedi/drivers.c s->state &= ~mask; mask 392 drivers/staging/comedi/drivers.c s->state |= (bits & mask); mask 395 drivers/staging/comedi/drivers.c return mask; mask 54 drivers/staging/comedi/drivers/addi_apci_16xx.c unsigned int mask; mask 58 drivers/staging/comedi/drivers/addi_apci_16xx.c mask = 0x000000ff; mask 60 drivers/staging/comedi/drivers/addi_apci_16xx.c mask = 0x0000ff00; mask 62 drivers/staging/comedi/drivers/addi_apci_16xx.c mask = 0x00ff0000; mask 64 drivers/staging/comedi/drivers/addi_apci_16xx.c mask = 0xff000000; mask 66 drivers/staging/comedi/drivers/addi_apci_16xx.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 670 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int mask = 0; mask 684 drivers/staging/comedi/drivers/addi_apci_3xxx.c mask = 0xff0000; mask 687 drivers/staging/comedi/drivers/addi_apci_3xxx.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 702 drivers/staging/comedi/drivers/addi_apci_3xxx.c unsigned int mask; mask 705 drivers/staging/comedi/drivers/addi_apci_3xxx.c mask = comedi_dio_update_state(s, data); mask 706 drivers/staging/comedi/drivers/addi_apci_3xxx.c if (mask) { mask 707 drivers/staging/comedi/drivers/addi_apci_3xxx.c if (mask & 0xff) mask 709 drivers/staging/comedi/drivers/addi_apci_3xxx.c if (mask & 0xff0000) mask 157 drivers/staging/comedi/drivers/adq12b.c unsigned int mask; mask 161 drivers/staging/comedi/drivers/adq12b.c mask = comedi_dio_update_state(s, data); mask 162 drivers/staging/comedi/drivers/adq12b.c if (mask) { mask 164 drivers/staging/comedi/drivers/adq12b.c if ((mask >> chan) & 0x01) { mask 102 drivers/staging/comedi/drivers/adv_pci1723.c unsigned int mask = (chan < 8) ? 0x00ff : 0xff00; mask 106 drivers/staging/comedi/drivers/adv_pci1723.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 620 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned int mask; mask 623 drivers/staging/comedi/drivers/amplc_dio200_common.c mask = comedi_dio_update_state(s, data); mask 624 drivers/staging/comedi/drivers/amplc_dio200_common.c if (mask) { mask 625 drivers/staging/comedi/drivers/amplc_dio200_common.c if (mask & 0xff) { mask 629 drivers/staging/comedi/drivers/amplc_dio200_common.c if (mask & 0xff00) { mask 633 drivers/staging/comedi/drivers/amplc_dio200_common.c if (mask & 0xff0000) { mask 654 drivers/staging/comedi/drivers/amplc_dio200_common.c unsigned int mask; mask 658 drivers/staging/comedi/drivers/amplc_dio200_common.c mask = 0x0000ff; mask 660 drivers/staging/comedi/drivers/amplc_dio200_common.c mask = 0x00ff00; mask 662 drivers/staging/comedi/drivers/amplc_dio200_common.c mask = 0x0f0000; mask 664 drivers/staging/comedi/drivers/amplc_dio200_common.c mask = 0xf00000; mask 666 drivers/staging/comedi/drivers/amplc_dio200_common.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 246 drivers/staging/comedi/drivers/amplc_pci224.c #define COMBINE(old, new, mask) (((old) & ~(mask)) | ((new) & (mask))) mask 432 drivers/staging/comedi/drivers/amplc_pci230.c #define COMBINE(old, new, mask) (((old) & ~(mask)) | ((new) & (mask))) mask 264 drivers/staging/comedi/drivers/cb_das16_cs.c unsigned int mask; mask 268 drivers/staging/comedi/drivers/cb_das16_cs.c mask = 0x0f; mask 270 drivers/staging/comedi/drivers/cb_das16_cs.c mask = 0xf0; mask 272 drivers/staging/comedi/drivers/cb_das16_cs.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 69 drivers/staging/comedi/drivers/comedi_8255.c unsigned int mask; mask 72 drivers/staging/comedi/drivers/comedi_8255.c mask = comedi_dio_update_state(s, data); mask 73 drivers/staging/comedi/drivers/comedi_8255.c if (mask) { mask 74 drivers/staging/comedi/drivers/comedi_8255.c if (mask & 0xff) mask 77 drivers/staging/comedi/drivers/comedi_8255.c if (mask & 0xff00) mask 80 drivers/staging/comedi/drivers/comedi_8255.c if (mask & 0xff0000) mask 121 drivers/staging/comedi/drivers/comedi_8255.c unsigned int mask; mask 125 drivers/staging/comedi/drivers/comedi_8255.c mask = 0x0000ff; mask 127 drivers/staging/comedi/drivers/comedi_8255.c mask = 0x00ff00; mask 129 drivers/staging/comedi/drivers/comedi_8255.c mask = 0x0f0000; mask 131 drivers/staging/comedi/drivers/comedi_8255.c mask = 0xf00000; mask 133 drivers/staging/comedi/drivers/comedi_8255.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 40 drivers/staging/comedi/drivers/dt2817.c unsigned int mask; mask 44 drivers/staging/comedi/drivers/dt2817.c mask = 0x000000ff; mask 46 drivers/staging/comedi/drivers/dt2817.c mask = 0x0000ff00; mask 48 drivers/staging/comedi/drivers/dt2817.c mask = 0x00ff0000; mask 50 drivers/staging/comedi/drivers/dt2817.c mask = 0xff000000; mask 52 drivers/staging/comedi/drivers/dt2817.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 76 drivers/staging/comedi/drivers/dt2817.c unsigned int mask; mask 79 drivers/staging/comedi/drivers/dt2817.c mask = comedi_dio_update_state(s, data); mask 80 drivers/staging/comedi/drivers/dt2817.c if (mask) { mask 81 drivers/staging/comedi/drivers/dt2817.c if (mask & 0x000000ff) mask 83 drivers/staging/comedi/drivers/dt2817.c if (mask & 0x0000ff00) mask 85 drivers/staging/comedi/drivers/dt2817.c if (mask & 0x00ff0000) mask 87 drivers/staging/comedi/drivers/dt2817.c if (mask & 0xff000000) mask 981 drivers/staging/comedi/drivers/dt282x.c unsigned int mask; mask 985 drivers/staging/comedi/drivers/dt282x.c mask = 0x00ff; mask 987 drivers/staging/comedi/drivers/dt282x.c mask = 0xff00; mask 989 drivers/staging/comedi/drivers/dt282x.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 560 drivers/staging/comedi/drivers/dt3000.c unsigned int mask; mask 564 drivers/staging/comedi/drivers/dt3000.c mask = 0x0f; mask 566 drivers/staging/comedi/drivers/dt3000.c mask = 0xf0; mask 568 drivers/staging/comedi/drivers/dt3000.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 323 drivers/staging/comedi/drivers/ii_pci20kc.c unsigned int mask; mask 327 drivers/staging/comedi/drivers/ii_pci20kc.c mask = 0x000000ff; mask 329 drivers/staging/comedi/drivers/ii_pci20kc.c mask = 0x0000ff00; mask 331 drivers/staging/comedi/drivers/ii_pci20kc.c mask = 0x00ff0000; mask 333 drivers/staging/comedi/drivers/ii_pci20kc.c mask = 0xff000000; mask 335 drivers/staging/comedi/drivers/ii_pci20kc.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 349 drivers/staging/comedi/drivers/ii_pci20kc.c unsigned int mask; mask 351 drivers/staging/comedi/drivers/ii_pci20kc.c mask = comedi_dio_update_state(s, data); mask 352 drivers/staging/comedi/drivers/ii_pci20kc.c if (mask) { mask 353 drivers/staging/comedi/drivers/ii_pci20kc.c if (mask & 0x000000ff) mask 356 drivers/staging/comedi/drivers/ii_pci20kc.c if (mask & 0x0000ff00) mask 359 drivers/staging/comedi/drivers/ii_pci20kc.c if (mask & 0x00ff0000) mask 362 drivers/staging/comedi/drivers/ii_pci20kc.c if (mask & 0xff000000) mask 1047 drivers/staging/comedi/drivers/me4000.c unsigned int mask; mask 1052 drivers/staging/comedi/drivers/me4000.c mask = 0x000000ff; mask 1054 drivers/staging/comedi/drivers/me4000.c mask = 0x0000ff00; mask 1056 drivers/staging/comedi/drivers/me4000.c mask = 0x00ff0000; mask 1058 drivers/staging/comedi/drivers/me4000.c mask = 0xff000000; mask 1060 drivers/staging/comedi/drivers/me4000.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 156 drivers/staging/comedi/drivers/me_daq.c unsigned int mask; mask 160 drivers/staging/comedi/drivers/me_daq.c mask = 0x0000ffff; mask 162 drivers/staging/comedi/drivers/me_daq.c mask = 0xffff0000; mask 164 drivers/staging/comedi/drivers/me_daq.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 189 drivers/staging/comedi/drivers/me_daq.c unsigned int mask; mask 192 drivers/staging/comedi/drivers/me_daq.c mask = comedi_dio_update_state(s, data); mask 193 drivers/staging/comedi/drivers/me_daq.c if (mask) { mask 194 drivers/staging/comedi/drivers/me_daq.c if (mask & 0x0000ffff) mask 196 drivers/staging/comedi/drivers/me_daq.c if (mask & 0xffff0000) mask 165 drivers/staging/comedi/drivers/ni_6527.c unsigned int mask; mask 167 drivers/staging/comedi/drivers/ni_6527.c mask = comedi_dio_update_state(s, data); mask 168 drivers/staging/comedi/drivers/ni_6527.c if (mask) { mask 172 drivers/staging/comedi/drivers/ni_6527.c if (mask & 0x0000ff) mask 174 drivers/staging/comedi/drivers/ni_6527.c if (mask & 0x00ff00) mask 177 drivers/staging/comedi/drivers/ni_6527.c if (mask & 0xff0000) mask 272 drivers/staging/comedi/drivers/ni_6527.c unsigned int mask, mask 278 drivers/staging/comedi/drivers/ni_6527.c rising &= mask; mask 279 drivers/staging/comedi/drivers/ni_6527.c falling &= mask; mask 281 drivers/staging/comedi/drivers/ni_6527.c if (mask & 0xff) { mask 282 drivers/staging/comedi/drivers/ni_6527.c if (~mask & 0xff) { mask 286 drivers/staging/comedi/drivers/ni_6527.c (~mask & 0xff); mask 290 drivers/staging/comedi/drivers/ni_6527.c (~mask & 0xff); mask 301 drivers/staging/comedi/drivers/ni_6527.c mask >>= 8; mask 310 drivers/staging/comedi/drivers/ni_6527.c unsigned int mask = 0xffffffff; mask 320 drivers/staging/comedi/drivers/ni_6527.c ni6527_set_edge_detection(dev, mask, rising, falling); mask 336 drivers/staging/comedi/drivers/ni_6527.c mask = 0; mask 340 drivers/staging/comedi/drivers/ni_6527.c mask <<= shift; mask 348 drivers/staging/comedi/drivers/ni_6527.c ni6527_set_edge_detection(dev, mask, rising, falling); mask 537 drivers/staging/comedi/drivers/ni_660x.c unsigned int mask = data[0] << shift; mask 546 drivers/staging/comedi/drivers/ni_660x.c if (mask) { mask 547 drivers/staging/comedi/drivers/ni_660x.c s->state &= ~mask; mask 548 drivers/staging/comedi/drivers/ni_660x.c s->state |= (bits & mask); mask 173 drivers/staging/comedi/drivers/ni_at_ao.c unsigned int mask; mask 177 drivers/staging/comedi/drivers/ni_at_ao.c mask = 0x0f; mask 179 drivers/staging/comedi/drivers/ni_at_ao.c mask = 0xf0; mask 181 drivers/staging/comedi/drivers/ni_at_ao.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 558 drivers/staging/comedi/drivers/ni_atmio16d.c unsigned int mask; mask 562 drivers/staging/comedi/drivers/ni_atmio16d.c mask = 0x0f; mask 564 drivers/staging/comedi/drivers/ni_atmio16d.c mask = 0xf0; mask 566 drivers/staging/comedi/drivers/ni_atmio16d.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 79 drivers/staging/comedi/drivers/ni_daq_700.c unsigned int mask; mask 82 drivers/staging/comedi/drivers/ni_daq_700.c mask = comedi_dio_update_state(s, data); mask 83 drivers/staging/comedi/drivers/ni_daq_700.c if (mask) { mask 84 drivers/staging/comedi/drivers/ni_daq_700.c if (mask & 0xff) mask 1828 drivers/staging/comedi/drivers/ni_mio_common.c unsigned int mask = s->maxdata; mask 1915 drivers/staging/comedi/drivers/ni_mio_common.c d &= mask; mask 3805 drivers/staging/comedi/drivers/ni_mio_common.c unsigned char mask, input = 0; mask 3810 drivers/staging/comedi/drivers/ni_mio_common.c for (mask = 0x80; mask; mask >>= 1) { mask 3817 drivers/staging/comedi/drivers/ni_mio_common.c if (data_out & mask) mask 3837 drivers/staging/comedi/drivers/ni_mio_common.c input |= mask; mask 223 drivers/staging/comedi/drivers/ni_tio.c unsigned int mask, unsigned int value, mask 234 drivers/staging/comedi/drivers/ni_tio.c regs[reg] &= ~mask; mask 235 drivers/staging/comedi/drivers/ni_tio.c regs[reg] |= (value & mask); mask 253 drivers/staging/comedi/drivers/ni_tio.c unsigned int mask, unsigned int value) mask 255 drivers/staging/comedi/drivers/ni_tio.c ni_tio_set_bits_transient(counter, reg, mask, value, 0x0); mask 446 drivers/staging/comedi/drivers/ni_tio.c unsigned int mask = 0; mask 461 drivers/staging/comedi/drivers/ni_tio.c mask = GI_M_ALT_SYNC; mask 464 drivers/staging/comedi/drivers/ni_tio.c mask = GI_660X_ALT_SYNC; mask 493 drivers/staging/comedi/drivers/ni_tio.c bits = mask; mask 495 drivers/staging/comedi/drivers/ni_tio.c ni_tio_set_bits(counter, reg, mask, bits); mask 565 drivers/staging/comedi/drivers/ni_tio.c unsigned int mask = 0; mask 574 drivers/staging/comedi/drivers/ni_tio.c mask = GI_M_HW_ARM_SEL_MASK; mask 577 drivers/staging/comedi/drivers/ni_tio.c mask = GI_660X_HW_ARM_SEL_MASK; mask 594 drivers/staging/comedi/drivers/ni_tio.c if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) { mask 596 drivers/staging/comedi/drivers/ni_tio.c (GI_HW_ARM_SEL(start_trigger) & mask); mask 603 drivers/staging/comedi/drivers/ni_tio.c if (mask) mask 605 drivers/staging/comedi/drivers/ni_tio.c GI_HW_ARM_ENA | mask, bits); mask 1125 drivers/staging/comedi/drivers/ni_tio.c unsigned int abz_reg, shift, mask; mask 1146 drivers/staging/comedi/drivers/ni_tio.c mask = 0x1f << shift; mask 1150 drivers/staging/comedi/drivers/ni_tio.c counter_dev->regs[chip][abz_reg] &= ~mask; mask 1151 drivers/staging/comedi/drivers/ni_tio.c counter_dev->regs[chip][abz_reg] |= (source << shift) & mask; mask 1161 drivers/staging/comedi/drivers/ni_tio.c unsigned int abz_reg, shift, mask; mask 1183 drivers/staging/comedi/drivers/ni_tio.c mask = 0x1f; mask 1185 drivers/staging/comedi/drivers/ni_tio.c *source = (ni_tio_get_soft_copy(counter, abz_reg) >> shift) & mask; mask 166 drivers/staging/comedi/drivers/ni_tio_internal.h unsigned int mask, unsigned int value); mask 43 drivers/staging/comedi/drivers/ni_tiocmd.c unsigned int mask; mask 46 drivers/staging/comedi/drivers/ni_tiocmd.c mask = GI_READ_ACKS_IRQ | GI_WRITE_ACKS_IRQ; mask 55 drivers/staging/comedi/drivers/ni_tiocmd.c ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), mask, bits); mask 62 drivers/staging/comedi/drivers/ni_tiocmd.c mask = GI_DMA_ENABLE | GI_DMA_INT_ENA | GI_DMA_WRITE; mask 69 drivers/staging/comedi/drivers/ni_tiocmd.c ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), mask, bits); mask 360 drivers/staging/comedi/drivers/ni_usb6501.c unsigned int mask; mask 365 drivers/staging/comedi/drivers/ni_usb6501.c mask = comedi_dio_update_state(s, data); mask 368 drivers/staging/comedi/drivers/ni_usb6501.c if (mask & (0xFF << port * 8)) { mask 402 drivers/staging/comedi/drivers/pcl711.c unsigned int mask; mask 404 drivers/staging/comedi/drivers/pcl711.c mask = comedi_dio_update_state(s, data); mask 405 drivers/staging/comedi/drivers/pcl711.c if (mask) { mask 406 drivers/staging/comedi/drivers/pcl711.c if (mask & 0x00ff) mask 408 drivers/staging/comedi/drivers/pcl711.c if (mask & 0xff00) mask 286 drivers/staging/comedi/drivers/pcl726.c unsigned int mask; mask 288 drivers/staging/comedi/drivers/pcl726.c mask = comedi_dio_update_state(s, data); mask 289 drivers/staging/comedi/drivers/pcl726.c if (mask) { mask 291 drivers/staging/comedi/drivers/pcl726.c if (mask & 0x00ff) mask 293 drivers/staging/comedi/drivers/pcl726.c if (mask & 0xff00) mask 296 drivers/staging/comedi/drivers/pcl726.c if (mask & 0x00ff) mask 298 drivers/staging/comedi/drivers/pcl726.c if (mask & 0xff00) mask 218 drivers/staging/comedi/drivers/pcl730.c unsigned int mask; mask 220 drivers/staging/comedi/drivers/pcl730.c mask = comedi_dio_update_state(s, data); mask 221 drivers/staging/comedi/drivers/pcl730.c if (mask) { mask 222 drivers/staging/comedi/drivers/pcl730.c if (mask & 0x00ff) mask 224 drivers/staging/comedi/drivers/pcl730.c if ((mask & 0xff00) && (s->n_chan > 8)) mask 226 drivers/staging/comedi/drivers/pcl730.c if ((mask & 0xff0000) && (s->n_chan > 16)) mask 228 drivers/staging/comedi/drivers/pcl730.c if ((mask & 0xff000000) && (s->n_chan > 24)) mask 127 drivers/staging/comedi/drivers/pcm3724.c unsigned int mask; mask 132 drivers/staging/comedi/drivers/pcm3724.c mask = 1 << CR_CHAN(chanspec); mask 134 drivers/staging/comedi/drivers/pcm3724.c priv->dio_1 |= mask; mask 136 drivers/staging/comedi/drivers/pcm3724.c priv->dio_2 |= mask; mask 166 drivers/staging/comedi/drivers/pcm3724.c unsigned int mask; mask 170 drivers/staging/comedi/drivers/pcm3724.c mask = 0x0000ff; mask 172 drivers/staging/comedi/drivers/pcm3724.c mask = 0x00ff00; mask 174 drivers/staging/comedi/drivers/pcm3724.c mask = 0x0f0000; mask 176 drivers/staging/comedi/drivers/pcm3724.c mask = 0xf00000; mask 178 drivers/staging/comedi/drivers/pcm3724.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 250 drivers/staging/comedi/drivers/pcmmio.c unsigned int mask; mask 253 drivers/staging/comedi/drivers/pcmmio.c mask = comedi_dio_update_state(s, data); mask 254 drivers/staging/comedi/drivers/pcmmio.c if (mask) { mask 220 drivers/staging/comedi/drivers/pcmuio.c unsigned int mask; mask 223 drivers/staging/comedi/drivers/pcmuio.c mask = comedi_dio_update_state(s, data); mask 224 drivers/staging/comedi/drivers/pcmuio.c if (mask) { mask 520 drivers/staging/comedi/drivers/s526.c unsigned int mask; mask 528 drivers/staging/comedi/drivers/s526.c mask = 0x0f; mask 530 drivers/staging/comedi/drivers/s526.c mask = 0xf0; mask 532 drivers/staging/comedi/drivers/s526.c ret = comedi_dio_insn_config(dev, s, insn, data, mask); mask 210 drivers/staging/comedi/drivers/s626.c unsigned int mask, unsigned int wdata) mask 220 drivers/staging/comedi/drivers/s626.c val &= mask; mask 885 drivers/staging/comedi/drivers/s626.c unsigned int mask = S626_CRBMSK_INTCTRL; mask 889 drivers/staging/comedi/drivers/s626.c mask |= S626_CRBMSK_CLKENAB_A; mask 892 drivers/staging/comedi/drivers/s626.c mask |= S626_CRBMSK_CLKENAB_B; mask 895 drivers/staging/comedi/drivers/s626.c s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set); mask 907 drivers/staging/comedi/drivers/s626.c u16 mask; mask 912 drivers/staging/comedi/drivers/s626.c mask = S626_CRAMSK_LOADSRC_A; mask 916 drivers/staging/comedi/drivers/s626.c mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL; mask 919 drivers/staging/comedi/drivers/s626.c s626_debi_replace(dev, reg, ~mask, set); mask 1017 drivers/staging/comedi/drivers/s626.c unsigned int mask = 1 << (chan - (16 * group)); mask 1022 drivers/staging/comedi/drivers/s626.c s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status); mask 1026 drivers/staging/comedi/drivers/s626.c s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status); mask 1033 drivers/staging/comedi/drivers/s626.c s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status); mask 1039 drivers/staging/comedi/drivers/s626.c unsigned int mask) mask 1045 drivers/staging/comedi/drivers/s626.c s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask); mask 46 drivers/staging/comedi/drivers/ssv_dnp.c unsigned int mask; mask 55 drivers/staging/comedi/drivers/ssv_dnp.c mask = comedi_dio_update_state(s, data); mask 56 drivers/staging/comedi/drivers/ssv_dnp.c if (mask) { mask 86 drivers/staging/comedi/drivers/ssv_dnp.c unsigned int mask; mask 95 drivers/staging/comedi/drivers/ssv_dnp.c mask = 1 << chan; mask 98 drivers/staging/comedi/drivers/ssv_dnp.c mask = 1 << (chan - 8); mask 110 drivers/staging/comedi/drivers/ssv_dnp.c mask = 1 << ((chan - 16) * 2); mask 116 drivers/staging/comedi/drivers/ssv_dnp.c val |= mask; mask 118 drivers/staging/comedi/drivers/ssv_dnp.c val &= ~mask; mask 166 drivers/staging/comedi/kcomedilib/kcomedilib_main.c unsigned int mask, unsigned int *bits, mask 186 drivers/staging/comedi/kcomedilib/kcomedilib_main.c data[0] = mask; mask 2858 drivers/staging/exfat/exfat_super.c mode_t i_mode, mask, perm; mask 2863 drivers/staging/exfat/exfat_super.c mask = sbi->options.fs_fmask; mask 2865 drivers/staging/exfat/exfat_super.c mask = sbi->options.fs_dmask; mask 2867 drivers/staging/exfat/exfat_super.c perm = *mode_ptr & ~(S_IFMT | mask); mask 2878 drivers/staging/exfat/exfat_super.c if ((perm & 0222) && ((perm & 0222) != (0222 & ~mask))) mask 2885 drivers/staging/exfat/exfat_super.c if ((perm & 0222) != (0222 & ~mask)) mask 154 drivers/staging/fbtft/fb_hx8340bn.c static const unsigned long mask[] = { mask 164 drivers/staging/fbtft/fb_hx8340bn.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 98 drivers/staging/fbtft/fb_hx8347d.c static const unsigned long mask[] = { mask 109 drivers/staging/fbtft/fb_hx8347d.c CURVE(i, j) &= mask[j]; mask 198 drivers/staging/fbtft/fb_ili9163.c static const unsigned long mask[] = { mask 206 drivers/staging/fbtft/fb_ili9163.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 217 drivers/staging/fbtft/fb_ili9320.c static const unsigned long mask[] = { mask 226 drivers/staging/fbtft/fb_ili9320.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 211 drivers/staging/fbtft/fb_ili9325.c static const unsigned long mask[] = { mask 220 drivers/staging/fbtft/fb_ili9325.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 126 drivers/staging/fbtft/fb_s6d1121.c static const unsigned long mask[] = { mask 136 drivers/staging/fbtft/fb_s6d1121.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 132 drivers/staging/fbtft/fb_ssd1289.c static const unsigned long mask[] = { mask 141 drivers/staging/fbtft/fb_ssd1289.c CURVE(i, j) &= mask[i * par->gamma.num_values + j]; mask 218 drivers/staging/fieldbus/dev_core.c __poll_t mask = EPOLLIN | EPOLLRDNORM | EPOLLOUT | EPOLLWRNORM; mask 223 drivers/staging/fieldbus/dev_core.c mask |= EPOLLPRI | EPOLLERR; mask 224 drivers/staging/fieldbus/dev_core.c return mask; mask 135 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h __le32 mask; mask 145 drivers/staging/fsl-dpaa2/ethsw/dpsw-cmd.h __le32 mask; mask 219 drivers/staging/fsl-dpaa2/ethsw/dpsw.c u32 mask) mask 229 drivers/staging/fsl-dpaa2/ethsw/dpsw.c cmd_params->mask = cpu_to_le32(mask); mask 124 drivers/staging/fsl-dpaa2/ethsw/dpsw.h u32 mask); mask 740 drivers/staging/fsl-dpaa2/ethsw/ethsw.c u32 mask = DPSW_IRQ_EVENT_LINK_CHANGED; mask 775 drivers/staging/fsl-dpaa2/ethsw/ethsw.c DPSW_IRQ_INDEX_IF, mask); mask 1187 drivers/staging/fwserial/fwserial.c static int check_msr_delta(struct fwtty_port *port, unsigned long mask, mask 1195 drivers/staging/fwserial/fwserial.c delta = ((mask & TIOCM_RNG && prev->rng != now.rng) || mask 1196 drivers/staging/fwserial/fwserial.c (mask & TIOCM_DSR && prev->dsr != now.dsr) || mask 1197 drivers/staging/fwserial/fwserial.c (mask & TIOCM_CAR && prev->dcd != now.dcd) || mask 1198 drivers/staging/fwserial/fwserial.c (mask & TIOCM_CTS && prev->cts != now.cts)); mask 1205 drivers/staging/fwserial/fwserial.c static int wait_msr_change(struct fwtty_port *port, unsigned long mask) mask 1212 drivers/staging/fwserial/fwserial.c check_msr_delta(port, mask, &prev)); mask 1672 drivers/staging/gasket/gasket_core.c u64 offset, u64 mask, u64 val, mask 1680 drivers/staging/gasket/gasket_core.c if ((tmp & mask) == val) mask 607 drivers/staging/gasket/gasket_core.h u64 mask, tmp; mask 610 drivers/staging/gasket/gasket_core.h mask = ((1ULL << mask_width) - 1) << mask_shift; mask 611 drivers/staging/gasket/gasket_core.h tmp = (tmp & ~mask) | (value << mask_shift); mask 619 drivers/staging/gasket/gasket_core.h u32 mask, tmp; mask 622 drivers/staging/gasket/gasket_core.h mask = ((1 << mask_width) - 1) << mask_shift; mask 623 drivers/staging/gasket/gasket_core.h tmp = (tmp & ~mask) | (value << mask_shift); mask 635 drivers/staging/gasket/gasket_core.h u64 offset, u64 mask, u64 val, mask 79 drivers/staging/gasket/gasket_interrupt.c ulong mask; mask 127 drivers/staging/gasket/gasket_interrupt.c mask = ~(0xFFFF << pack_shift); mask 131 drivers/staging/gasket/gasket_interrupt.c value &= mask; mask 243 drivers/staging/gasket/gasket_interrupt.c u32 mask = mask 247 drivers/staging/gasket/gasket_interrupt.c if (!(mask & 1)) mask 932 drivers/staging/greybus/audio_codec.c int mask; mask 947 drivers/staging/greybus/audio_codec.c mask = GBCODEC_JACK_MASK; mask 949 drivers/staging/greybus/audio_codec.c mask = GBCODEC_JACK_BUTTON_MASK; mask 951 drivers/staging/greybus/audio_codec.c mask = 0; mask 952 drivers/staging/greybus/audio_codec.c if (mask) { mask 955 drivers/staging/greybus/audio_codec.c snd_soc_jack_report(jack, 0, mask); mask 433 drivers/staging/greybus/audio_topology.c unsigned int mask, val; mask 459 drivers/staging/greybus/audio_topology.c mask = (1 << fls(max)) - 1; mask 460 drivers/staging/greybus/audio_topology.c val = ucontrol->value.integer.value[0] & mask; mask 766 drivers/staging/greybus/audio_topology.c unsigned int mask; mask 807 drivers/staging/greybus/audio_topology.c mask = e->mask << e->shift_l; mask 820 drivers/staging/greybus/audio_topology.c mask |= e->mask << e->shift_r; mask 1061 drivers/staging/greybus/camera.c unsigned int mask; mask 1069 drivers/staging/greybus/camera.c .mask = S_IFREG | 0444, mask 1074 drivers/staging/greybus/camera.c .mask = S_IFREG | 0666, mask 1079 drivers/staging/greybus/camera.c .mask = S_IFREG | 0666, mask 1084 drivers/staging/greybus/camera.c .mask = S_IFREG | 0666, mask 1099 drivers/staging/greybus/camera.c if (!(op->mask & 0222)) { mask 1190 drivers/staging/greybus/camera.c debugfs_create_file(entry->name, entry->mask, mask 82 drivers/staging/greybus/tools/loopback_test.c int mask; mask 225 drivers/staging/greybus/tools/loopback_test.c if (!t->mask || (t->mask & (1 << dev_idx))) mask 724 drivers/staging/greybus/tools/loopback_test.c sigset_t mask_old, mask; mask 726 drivers/staging/greybus/tools/loopback_test.c sigemptyset(&mask); mask 728 drivers/staging/greybus/tools/loopback_test.c sigaddset(&mask, SIGINT); mask 729 drivers/staging/greybus/tools/loopback_test.c sigprocmask(SIG_BLOCK, &mask, &mask_old); mask 879 drivers/staging/greybus/tools/loopback_test.c if (t->mask && !strcmp(t->devices[i].name, "")) { mask 917 drivers/staging/greybus/tools/loopback_test.c t.mask = atol(optarg); mask 154 drivers/staging/iio/accel/adis16203.c long mask) mask 166 drivers/staging/iio/accel/adis16203.c long mask) mask 173 drivers/staging/iio/accel/adis16203.c switch (mask) { mask 248 drivers/staging/iio/accel/adis16240.c long mask) mask 255 drivers/staging/iio/accel/adis16240.c switch (mask) { mask 309 drivers/staging/iio/accel/adis16240.c long mask) mask 314 drivers/staging/iio/accel/adis16240.c switch (mask) { mask 603 drivers/staging/iio/adc/ad7192.c long mask) mask 613 drivers/staging/iio/adc/ad7192.c switch (mask) { mask 662 drivers/staging/iio/adc/ad7192.c long mask) mask 664 drivers/staging/iio/adc/ad7192.c switch (mask) { mask 679 drivers/staging/iio/adc/ad7192.c long mask) mask 683 drivers/staging/iio/adc/ad7192.c switch (mask) { mask 1863 drivers/staging/iio/addac/adt7316.c u8 mask; mask 1870 drivers/staging/iio/addac/adt7316.c mask = 0; /* enable vdd int */ mask 1872 drivers/staging/iio/addac/adt7316.c mask = ADT7316_INT_MASK2_VDD; /* disable vdd int */ mask 1874 drivers/staging/iio/addac/adt7316.c ret = chip->bus.write(chip->bus.client, ADT7316_INT_MASK2, mask); mask 1883 drivers/staging/iio/addac/adt7316.c mask = (~data) & ADT7316_TEMP_INT_MASK; mask 1886 drivers/staging/iio/addac/adt7316.c mask = (~data) & ADT7316_TEMP_AIN_INT_MASK; mask 1888 drivers/staging/iio/addac/adt7316.c ret = chip->bus.write(chip->bus.client, ADT7316_INT_MASK1, mask); mask 1890 drivers/staging/iio/addac/adt7316.c chip->int_mask = mask; mask 104 drivers/staging/iio/cdc/ad7150.c long mask) mask 110 drivers/staging/iio/cdc/ad7150.c switch (mask) { mask 424 drivers/staging/iio/cdc/ad7746.c long mask) mask 431 drivers/staging/iio/cdc/ad7746.c switch (mask) { mask 531 drivers/staging/iio/cdc/ad7746.c long mask) mask 539 drivers/staging/iio/cdc/ad7746.c switch (mask) { mask 430 drivers/staging/isdn/gigaset/common.c static void make_valid(struct cardstate *cs, unsigned mask) mask 435 drivers/staging/isdn/gigaset/common.c cs->flags |= mask; mask 439 drivers/staging/isdn/gigaset/common.c static void make_invalid(struct cardstate *cs, unsigned mask) mask 444 drivers/staging/isdn/gigaset/common.c cs->flags &= ~mask; mask 769 drivers/staging/isdn/gigaset/isocdata.c unsigned char mask = (1 << lead1) - 1; mask 770 drivers/staging/isdn/gigaset/isocdata.c c = (c & mask) | ((c & ~mask) >> 1); mask 155 drivers/staging/isdn/gigaset/usb-gigaset.c unsigned mask, val; mask 158 drivers/staging/isdn/gigaset/usb-gigaset.c mask = tiocm_to_gigaset(old_state ^ new_state); mask 161 drivers/staging/isdn/gigaset/usb-gigaset.c gig_dbg(DEBUG_USBREQ, "set flags 0x%02x with mask 0x%02x", val, mask); mask 163 drivers/staging/isdn/gigaset/usb-gigaset.c (val & 0xff) | ((mask & 0xff) << 8), 0, mask 287 drivers/staging/isdn/hysdn/hysdn_proclog.c __poll_t mask = 0; mask 292 drivers/staging/isdn/hysdn/hysdn_proclog.c return (mask); /* no polling for write supported */ mask 297 drivers/staging/isdn/hysdn/hysdn_proclog.c mask |= EPOLLIN | EPOLLRDNORM; mask 299 drivers/staging/isdn/hysdn/hysdn_proclog.c return mask; mask 273 drivers/staging/kpc2000/kpc2000/cell_probe.c u64 mask; mask 276 drivers/staging/kpc2000/kpc2000/cell_probe.c mask = readq(pcard->sysinfo_regs_base + REG_INTERRUPT_MASK); mask 278 drivers/staging/kpc2000/kpc2000/cell_probe.c mask &= ~(BIT_ULL(kudev->cte.irq_base_num)); mask 280 drivers/staging/kpc2000/kpc2000/cell_probe.c mask |= BIT_ULL(kudev->cte.irq_base_num); mask 281 drivers/staging/kpc2000/kpc2000/cell_probe.c writeq(mask, pcard->sysinfo_regs_base + REG_INTERRUPT_MASK); mask 2275 drivers/staging/media/allegro-dvt/allegro-core.c u64 mask; mask 2298 drivers/staging/media/allegro-dvt/allegro-core.c mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B; mask 2302 drivers/staging/media/allegro-dvt/allegro-core.c V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask, mask 286 drivers/staging/media/hantro/hantro.h u32 mask; mask 374 drivers/staging/media/hantro/hantro.h v &= ~(reg->mask << reg->shift); mask 375 drivers/staging/media/hantro/hantro.h v |= ((val & reg->mask) << reg->shift); mask 275 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0x3f; mask 281 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0x3fffff; mask 302 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0xf; mask 339 drivers/staging/media/hantro/hantro_g1_vp8_dec.c reg.mask = 0xf; mask 201 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0x3f mask 207 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0x3fffff mask 213 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0xf mask 219 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0xffffff mask 225 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0x1ff mask 231 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0xff mask 237 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0x7 mask 243 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0x7 mask 249 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0xff mask 255 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 0xff mask 261 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 1 mask 267 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 1 mask 273 drivers/staging/media/hantro/rk3399_vpu_hw_vp8_dec.c .mask = 1 mask 248 drivers/staging/media/imx/imx6-mipi-csi2.c u32 mask, reg; mask 251 drivers/staging/media/imx/imx6-mipi-csi2.c mask = PHY_STOPSTATECLK | (((1 << csi2->bus.num_data_lanes) - 1) << mask 255 drivers/staging/media/imx/imx6-mipi-csi2.c (reg & mask) == mask, 0, 500000); mask 183 drivers/staging/media/imx/imx7-mipi-csis.c u32 mask; mask 371 drivers/staging/media/imx/imx7-mipi-csis.c u32 val, mask; mask 383 drivers/staging/media/imx/imx7-mipi-csis.c mask = (1 << (state->bus.num_data_lanes + 1)) - 1; mask 384 drivers/staging/media/imx/imx7-mipi-csis.c val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE); mask 773 drivers/staging/media/imx/imx7-mipi-csis.c if (!(status & state->events[i].mask)) mask 203 drivers/staging/media/ipu3/ipu3-css.c static int imgu_hw_wait(void __iomem *base, int reg, u32 mask, u32 cmp) mask 207 drivers/staging/media/ipu3/ipu3-css.c return readl_poll_timeout(base + reg, val, (val & mask) == cmp, mask 379 drivers/staging/media/ipu3/ipu3-css.c u32 mask; mask 457 drivers/staging/media/ipu3/ipu3-css.c if (val & stream_monitors[i].mask) { mask 397 drivers/staging/media/omap4iss/iss_csi2.c const u32 mask = CSI2_CTX_IRQ_FE | CSI2_CTX_IRQ_FS; mask 402 drivers/staging/media/omap4iss/iss_csi2.c mask); mask 405 drivers/staging/media/omap4iss/iss_csi2.c CSI2_CTX_IRQENABLE(i), mask); mask 408 drivers/staging/media/omap4iss/iss_csi2.c CSI2_CTX_IRQENABLE(i), mask); mask 72 drivers/staging/media/tegra-vde/vde.c u32 mask, void __iomem *base, u32 offset) mask 76 drivers/staging/media/tegra-vde/vde.c tegra_vde_writel(vde, value | mask, base, offset); mask 291 drivers/staging/most/cdev/cdev.c __poll_t mask = 0; mask 298 drivers/staging/most/cdev/cdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 301 drivers/staging/most/cdev/cdev.c mask |= EPOLLOUT | EPOLLWRNORM; mask 304 drivers/staging/most/cdev/cdev.c return mask; mask 117 drivers/staging/most/dim2/hal.c u32 mask = ~((~(u32)0) << blocks); mask 120 drivers/staging/most/dim2/hal.c if ((g.dbr_map[i] & mask) == 0) { mask 121 drivers/staging/most/dim2/hal.c g.dbr_map[i] |= mask; mask 126 drivers/staging/most/dim2/hal.c mask <<= mask_size - 1; mask 127 drivers/staging/most/dim2/hal.c } while ((mask <<= 1) != 0); mask 137 drivers/staging/most/dim2/hal.c u32 mask = ~((~(u32)0) << blocks); mask 139 drivers/staging/most/dim2/hal.c mask <<= block_idx % 32; mask 140 drivers/staging/most/dim2/hal.c g.dbr_map[block_idx / 32] &= ~mask; mask 177 drivers/staging/most/dim2/hal.c static void dim2_write_ctr_mask(u32 ctr_addr, const u32 *mask, const u32 *value) mask 183 drivers/staging/most/dim2/hal.c if (mask[0] != 0) mask 185 drivers/staging/most/dim2/hal.c if (mask[1] != 0) mask 187 drivers/staging/most/dim2/hal.c if (mask[2] != 0) mask 189 drivers/staging/most/dim2/hal.c if (mask[3] != 0) mask 192 drivers/staging/most/dim2/hal.c writel(mask[0], &g.dim2->MDWE0); mask 193 drivers/staging/most/dim2/hal.c writel(mask[1], &g.dim2->MDWE1); mask 194 drivers/staging/most/dim2/hal.c writel(mask[2], &g.dim2->MDWE2); mask 195 drivers/staging/most/dim2/hal.c writel(mask[3], &g.dim2->MDWE3); mask 202 drivers/staging/most/dim2/hal.c u32 const mask[4] = { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }; mask 204 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ctr_addr, mask, value); mask 230 drivers/staging/most/dim2/hal.c u32 mask[4] = { 0, 0, 0, 0 }; mask 233 drivers/staging/most/dim2/hal.c mask[idx] = (u32)0xFFFF << shift; mask 235 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ctr_addr, mask, value); mask 243 drivers/staging/most/dim2/hal.c u32 mask[4] = { 0, 0, 0, 0 }; mask 246 drivers/staging/most/dim2/hal.c mask[idx] = (u32)0xFFFF << shift; mask 247 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ctr_addr, mask, value); mask 302 drivers/staging/most/dim2/hal.c u32 mask[4] = { 0, 0, 0, 0 }; mask 305 drivers/staging/most/dim2/hal.c mask[1] = mask 314 drivers/staging/most/dim2/hal.c mask[idx + 2] = 0xFFFFFFFF; mask 317 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ADT + ch_addr, mask, adt); mask 325 drivers/staging/most/dim2/hal.c u32 mask[4] = { 0, 0, 0, 0 }; mask 328 drivers/staging/most/dim2/hal.c mask[1] = mask 335 drivers/staging/most/dim2/hal.c mask[idx + 2] = 0xFFFFFFFF; mask 338 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ADT + ch_addr, mask, adt); mask 578 drivers/staging/most/dim2/hal.c u32 mask[4] = { 0, 0, 0, 0 }; mask 584 drivers/staging/most/dim2/hal.c mask[1] = mask 588 drivers/staging/most/dim2/hal.c dim2_write_ctr_mask(ADT + ch_addr, mask, adt_w); mask 206 drivers/staging/most/video/video.c __poll_t mask = 0; mask 212 drivers/staging/most/video/video.c mask |= EPOLLIN | EPOLLRDNORM; mask 214 drivers/staging/most/video/video.c return mask; mask 263 drivers/staging/mt7621-pci/pci-mt7621.c resource_size_t mask; mask 271 drivers/staging/mt7621-pci/pci-mt7621.c mask = ~(mem_resource->end - mem_resource->start); mask 274 drivers/staging/mt7621-pci/pci-mt7621.c write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0); mask 142 drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c mode &= ~(p->groups[group].mask << shift); mask 45 drivers/staging/netlogic/xlr_net.c static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask) mask 50 drivers/staging/netlogic/xlr_net.c xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); mask 357 drivers/staging/nvec/nvec.c static void nvec_event_mask(char *ev, u32 mask) mask 359 drivers/staging/nvec/nvec.c ev[3] = mask >> 16 & 0xff; mask 360 drivers/staging/nvec/nvec.c ev[4] = mask >> 24 & 0xff; mask 361 drivers/staging/nvec/nvec.c ev[5] = mask >> 0 & 0xff; mask 362 drivers/staging/nvec/nvec.c ev[6] = mask >> 8 & 0xff; mask 75 drivers/staging/pi433/rf69.c static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) mask 80 drivers/staging/pi433/rf69.c tmp = tmp | mask; mask 84 drivers/staging/pi433/rf69.c static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) mask 89 drivers/staging/pi433/rf69.c tmp = tmp & ~mask; mask 94 drivers/staging/pi433/rf69.c u8 mask, u8 value) mask 99 drivers/staging/pi433/rf69.c tmp = (tmp & ~mask) | value; mask 544 drivers/staging/pi433/rf69.c u8 mask; mask 551 drivers/staging/pi433/rf69.c mask = MASK_DIO0; mask 556 drivers/staging/pi433/rf69.c mask = MASK_DIO1; mask 561 drivers/staging/pi433/rf69.c mask = MASK_DIO2; mask 566 drivers/staging/pi433/rf69.c mask = MASK_DIO3; mask 571 drivers/staging/pi433/rf69.c mask = MASK_DIO4; mask 576 drivers/staging/pi433/rf69.c mask = MASK_DIO5; mask 588 drivers/staging/pi433/rf69.c dio_value = dio_value & ~mask; mask 1334 drivers/staging/qlge/qlge.h __le16 mask; mask 1692 drivers/staging/qlge/qlge_dbg.c pr_err("ricb->mask = 0x%.04x\n", le16_to_cpu(ricb->mask)); mask 221 drivers/staging/qlge/qlge_main.c u32 mask; mask 248 drivers/staging/qlge/qlge_main.c mask = CFG_Q_MASK | (bit << 16); mask 250 drivers/staging/qlge/qlge_main.c ql_write32(qdev, CFG, (mask | value)); mask 520 drivers/staging/qlge/qlge_main.c static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask, mask 526 drivers/staging/qlge/qlge_main.c switch (mask) { mask 601 drivers/staging/qlge/qlge_main.c "Mask type %d not yet supported.\n", mask); mask 612 drivers/staging/qlge/qlge_main.c ql_write32(qdev, RT_DATA, enable ? mask : 0); mask 3630 drivers/staging/qlge/qlge_main.c ricb->mask = cpu_to_le16((u16)(0x3ff)); mask 3753 drivers/staging/qlge/qlge_main.c u32 value, mask; mask 3761 drivers/staging/qlge/qlge_main.c mask = value << 16; mask 3762 drivers/staging/qlge/qlge_main.c ql_write32(qdev, SYS, mask | value); mask 3766 drivers/staging/qlge/qlge_main.c mask = NIC_RCV_CFG_DFQ_MASK; mask 3769 drivers/staging/qlge/qlge_main.c mask |= (NIC_RCV_CFG_RV << 16); mask 3771 drivers/staging/qlge/qlge_main.c ql_write32(qdev, NIC_RCV_CFG, (mask | value)); mask 3782 drivers/staging/qlge/qlge_main.c mask = FSC_VM_PAGESIZE_MASK | mask 3784 drivers/staging/qlge/qlge_main.c ql_write32(qdev, FSC, mask | value); mask 3800 drivers/staging/qlge/qlge_main.c mask = 0xffff0000; mask 3803 drivers/staging/qlge/qlge_main.c ql_write32(qdev, MGMT_RCV_CFG, mask); mask 3804 drivers/staging/qlge/qlge_main.c ql_write32(qdev, MGMT_RCV_CFG, mask | value); mask 1109 drivers/staging/rtl8188eu/core/rtw_wlan_util.c unsigned int mask = 0; mask 1115 drivers/staging/rtl8188eu/core/rtw_wlan_util.c mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); mask 1117 drivers/staging/rtl8188eu/core/rtw_wlan_util.c return mask; mask 1123 drivers/staging/rtl8188eu/core/rtw_wlan_util.c unsigned int mask = 0; mask 1128 drivers/staging/rtl8188eu/core/rtw_wlan_util.c mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); mask 1129 drivers/staging/rtl8188eu/core/rtw_wlan_util.c return mask; mask 1158 drivers/staging/rtl8188eu/core/rtw_wlan_util.c unsigned char get_highest_rate_idx(u32 mask) mask 1164 drivers/staging/rtl8188eu/core/rtw_wlan_util.c if (mask & BIT(i)) { mask 154 drivers/staging/rtl8188eu/hal/rf_cfg.c static void rtl_rfreg_delay(struct adapter *adapt, enum rf_radio_path rfpath, u32 addr, u32 mask, u32 data) mask 169 drivers/staging/rtl8188eu/hal/rf_cfg.c phy_set_rf_reg(adapt, rfpath, addr, mask, data); mask 1880 drivers/staging/rtl8188eu/hal/usb_halinit.c u32 mask, rate_bitmap; mask 1899 drivers/staging/rtl8188eu/hal/usb_halinit.c mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); mask 1900 drivers/staging/rtl8188eu/hal/usb_halinit.c mask |= (pmlmeinfo->HT_enable) ? update_MSC_rate(&pmlmeinfo->HT_caps) : 0; mask 1911 drivers/staging/rtl8188eu/hal/usb_halinit.c mask = update_basic_rate(cur_network->SupportedRates, supportRateNum); mask 1917 drivers/staging/rtl8188eu/hal/usb_halinit.c mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); mask 1923 drivers/staging/rtl8188eu/hal/usb_halinit.c rate_bitmap = ODM_Get_Rate_Bitmap(odmpriv, mac_id, mask, rssi_level); mask 1925 drivers/staging/rtl8188eu/hal/usb_halinit.c __func__, mac_id, networkType, mask, rssi_level, rate_bitmap); mask 1927 drivers/staging/rtl8188eu/hal/usb_halinit.c mask &= rate_bitmap; mask 1929 drivers/staging/rtl8188eu/hal/usb_halinit.c init_rate = get_highest_rate_idx(mask) & 0x3f; mask 1931 drivers/staging/rtl8188eu/hal/usb_halinit.c ODM_RA_UpdateRateInfo_8188E(odmpriv, mac_id, raid, mask, shortGIrate); mask 525 drivers/staging/rtl8188eu/include/rtw_mlme_ext.h unsigned char get_highest_rate_idx(u32 mask); mask 14 drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c static bool _rtl92e_wait_for_fw(struct net_device *dev, u32 mask, u32 timeout) mask 19 drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c if (rtl92e_readl(dev, CPU_GEN) & mask) mask 663 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c u8 mask = 0xff; mask 696 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c hwkey[i] |= key[4 * i + 0] & mask; mask 698 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c mask = 0x00; mask 700 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c mask = 0x00; mask 701 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c hwkey[i] |= (key[4 * i + 1] & mask) << 8; mask 702 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c hwkey[i] |= (key[4 * i + 2] & mask) << 16; mask 703 drivers/staging/rtl8192e/rtl8192e/rtl_wx.c hwkey[i] |= (key[4 * i + 3] & mask) << 24; mask 575 drivers/staging/rtl8192e/rtllib.h u8 mask; mask 176 drivers/staging/rtl8192e/rtllib_wx.c iwe.u.qual.updated = network->stats.mask & RTLLIB_STATMASK_WEMASK; mask 177 drivers/staging/rtl8192e/rtllib_wx.c if (!(network->stats.mask & RTLLIB_STATMASK_RSSI)) mask 179 drivers/staging/rtl8192e/rtllib_wx.c if (!(network->stats.mask & RTLLIB_STATMASK_NOISE)) mask 181 drivers/staging/rtl8192e/rtllib_wx.c if (!(network->stats.mask & RTLLIB_STATMASK_SIGNAL)) mask 695 drivers/staging/rtl8192u/ieee80211/ieee80211.h u8 mask; mask 166 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c iwe.u.qual.updated = network->stats.mask & IEEE80211_STATMASK_WEMASK; mask 167 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c if (!(network->stats.mask & IEEE80211_STATMASK_RSSI)) mask 169 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c if (!(network->stats.mask & IEEE80211_STATMASK_NOISE)) mask 171 drivers/staging/rtl8192u/ieee80211/ieee80211_wx.c if (!(network->stats.mask & IEEE80211_STATMASK_SIGNAL)) mask 21 drivers/staging/rtl8192u/ieee80211/rtl819x_TS.h u8 mask; mask 27 drivers/staging/rtl8192u/ieee80211/rtl819x_TS.h u8 mask; mask 36 drivers/staging/rtl8192u/ieee80211/rtl819x_TS.h u8 mask; mask 50 drivers/staging/rtl8192u/ieee80211/rtl819x_TS.h u8 mask; mask 62 drivers/staging/rtl8192u/ieee80211/rtl819x_TS.h u8 mask; mask 507 drivers/staging/rtl8192u/r8192U_wx.c u8 mask = 0xff; mask 531 drivers/staging/rtl8192u/r8192U_wx.c hwkey[i] |= key[4*i+0]&mask; mask 533 drivers/staging/rtl8192u/r8192U_wx.c mask = 0x00; mask 535 drivers/staging/rtl8192u/r8192U_wx.c mask = 0x00; mask 536 drivers/staging/rtl8192u/r8192U_wx.c hwkey[i] |= (key[4*i+1]&mask)<<8; mask 537 drivers/staging/rtl8192u/r8192U_wx.c hwkey[i] |= (key[4*i+2]&mask)<<16; mask 538 drivers/staging/rtl8192u/r8192U_wx.c hwkey[i] |= (key[4*i+3]&mask)<<24; mask 287 drivers/staging/rtl8192u/r819xU_cmdpkt.c rx_query_cfg.mask = (pmsg[12] << 24) | (pmsg[13] << 16) | mask 80 drivers/staging/rtl8192u/r819xU_cmdpkt.h u32 mask; mask 392 drivers/staging/rtl8712/ieee80211.h u8 mask; mask 38 drivers/staging/rtl8712/rtl871x_eeprom.c u16 x, mask; mask 42 drivers/staging/rtl8712/rtl871x_eeprom.c mask = 0x01 << (count - 1); mask 47 drivers/staging/rtl8712/rtl871x_eeprom.c if (data & mask) mask 55 drivers/staging/rtl8712/rtl871x_eeprom.c mask >>= 1; mask 56 drivers/staging/rtl8712/rtl871x_eeprom.c } while (mask); mask 35 drivers/staging/rtl8723bs/core/rtw_eeprom.c u16 x, mask; mask 42 drivers/staging/rtl8723bs/core/rtw_eeprom.c mask = 0x01 << (count - 1); mask 49 drivers/staging/rtl8723bs/core/rtw_eeprom.c if (data & mask) mask 59 drivers/staging/rtl8723bs/core/rtw_eeprom.c mask = mask >> 1; mask 60 drivers/staging/rtl8723bs/core/rtw_eeprom.c } while (mask); mask 232 drivers/staging/rtl8723bs/core/rtw_wlan_util.c void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask) mask 234 drivers/staging/rtl8723bs/core/rtw_wlan_util.c u8 mcs_rate_1r = (u8)(mask&0xff); mask 235 drivers/staging/rtl8723bs/core/rtw_wlan_util.c u8 mcs_rate_2r = (u8)((mask>>8)&0xff); mask 236 drivers/staging/rtl8723bs/core/rtw_wlan_util.c u8 mcs_rate_3r = (u8)((mask>>16)&0xff); mask 237 drivers/staging/rtl8723bs/core/rtw_wlan_util.c u8 mcs_rate_4r = (u8)((mask>>24)&0xff); mask 1598 drivers/staging/rtl8723bs/core/rtw_wlan_util.c unsigned char get_highest_rate_idx(u32 mask) mask 1604 drivers/staging/rtl8723bs/core/rtw_wlan_util.c if (mask & BIT(i)) { mask 975 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c void rtl8723b_set_FwMacIdConfig_cmd(struct adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask) mask 979 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x\n", __func__, mac_id, raid, bw, mask); mask 985 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(u1H2CMacIdConfigParm, (u8)(mask & 0x000000ff)); mask 986 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(u1H2CMacIdConfigParm, (u8)((mask & 0x0000ff00) >> 8)); mask 987 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(u1H2CMacIdConfigParm, (u8)((mask & 0x00ff0000) >> 16)); mask 988 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(u1H2CMacIdConfigParm, (u8)((mask & 0xff000000) >> 24)); mask 2045 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c u32 mask = bitmap&0x0FFFFFFF; mask 2054 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c mask = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); mask 2056 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x\n", __func__, mac_id, raid, bw, mask); mask 2057 drivers/staging/rtl8723bs/hal/rtl8723b_cmd.c rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, raid, bw, shortGI, mask); mask 2128 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c u32 mask, rate_bitmap; mask 2147 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c mask = psta->ra_mask; mask 2150 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); mask 2152 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap); mask 2154 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c mask &= rate_bitmap; mask 2157 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c mask &= ~rate_bitmap; mask 2162 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); mask 2163 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c mask &= 0xffffff00; /* disable CCK & <24M OFDM rate for 11G mode for CMCC */ mask 2164 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); mask 2170 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask); mask 2175 drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x init_rate = 0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate); mask 546 drivers/staging/rtl8723bs/include/ieee80211.h u8 mask; mask 173 drivers/staging/rtl8723bs/include/rtl8723b_cmd.h void rtl8723b_set_FwMacIdConfig_cmd(struct adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); mask 550 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); mask 634 drivers/staging/rtl8723bs/include/rtw_mlme_ext.h unsigned char get_highest_rate_idx(u32 mask); mask 887 drivers/staging/rts5208/rtsx_card.c u8 mask, val1, val2; mask 890 drivers/staging/rts5208/rtsx_card.c mask = MS_POWER_MASK; mask 894 drivers/staging/rts5208/rtsx_card.c mask = SD_POWER_MASK; mask 900 drivers/staging/rts5208/rtsx_card.c rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1); mask 909 drivers/staging/rts5208/rtsx_card.c rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2); mask 921 drivers/staging/rts5208/rtsx_card.c u8 mask, val; mask 924 drivers/staging/rts5208/rtsx_card.c mask = MS_POWER_MASK; mask 927 drivers/staging/rts5208/rtsx_card.c mask = SD_POWER_MASK; mask 931 drivers/staging/rts5208/rtsx_card.c retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); mask 980 drivers/staging/rts5208/rtsx_card.c u8 mask, value; mask 983 drivers/staging/rts5208/rtsx_card.c mask = CARD_SHARE_MASK; mask 994 drivers/staging/rts5208/rtsx_card.c mask = 0x03; mask 1008 drivers/staging/rts5208/rtsx_card.c retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value); mask 1297 drivers/staging/rts5208/rtsx_chip.c int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) mask 1303 drivers/staging/rts5208/rtsx_chip.c val |= (u32)mask << 8; mask 1348 drivers/staging/rts5208/rtsx_chip.c int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, mask 1356 drivers/staging/rts5208/rtsx_chip.c if (mask & 0xFF) { mask 1359 drivers/staging/rts5208/rtsx_chip.c (u8)(val & mask & 0xFF)); mask 1364 drivers/staging/rts5208/rtsx_chip.c mask >>= 8; mask 1437 drivers/staging/rts5208/rtsx_chip.c u32 *data, *mask; mask 1457 drivers/staging/rts5208/rtsx_chip.c mask = vzalloc(array_size(dw_len, 4)); mask 1458 drivers/staging/rts5208/rtsx_chip.c if (!mask) { mask 1465 drivers/staging/rts5208/rtsx_chip.c mask[j] |= 0xFF << (offset * 8); mask 1473 drivers/staging/rts5208/rtsx_chip.c print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask, mask 1480 drivers/staging/rts5208/rtsx_chip.c mask[i], data[i]); mask 1483 drivers/staging/rts5208/rtsx_chip.c vfree(mask); mask 1489 drivers/staging/rts5208/rtsx_chip.c vfree(mask); mask 2111 drivers/staging/rts5208/rtsx_chip.c u8 mask = 0; mask 2114 drivers/staging/rts5208/rtsx_chip.c mask |= SSC_POWER_DOWN; mask 2118 drivers/staging/rts5208/rtsx_chip.c mask |= SD_OC_POWER_DOWN; mask 2120 drivers/staging/rts5208/rtsx_chip.c mask |= MS_OC_POWER_DOWN; mask 2124 drivers/staging/rts5208/rtsx_chip.c if (mask) { mask 2125 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_register(chip, FPDCTL, mask, 0); mask 2139 drivers/staging/rts5208/rtsx_chip.c u8 mask = 0, val = 0; mask 2142 drivers/staging/rts5208/rtsx_chip.c mask |= SSC_POWER_DOWN; mask 2146 drivers/staging/rts5208/rtsx_chip.c mask |= SD_OC_POWER_DOWN; mask 2148 drivers/staging/rts5208/rtsx_chip.c mask |= MS_OC_POWER_DOWN; mask 2152 drivers/staging/rts5208/rtsx_chip.c if (mask) { mask 2153 drivers/staging/rts5208/rtsx_chip.c val = mask; mask 2154 drivers/staging/rts5208/rtsx_chip.c retval = rtsx_write_register(chip, FPDCTL, mask, val); mask 960 drivers/staging/rts5208/rtsx_chip.h int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); mask 963 drivers/staging/rts5208/rtsx_chip.h u8 func_no, u16 addr, u32 mask, u32 val); mask 1723 drivers/staging/rts5208/rtsx_scsi.c u8 cmd_type, mask, value, idx; mask 1747 drivers/staging/rts5208/rtsx_scsi.c mask = srb->cmnd[7]; mask 1749 drivers/staging/rts5208/rtsx_scsi.c rtsx_add_cmd(chip, cmd_type, addr, mask, value); mask 196 drivers/staging/rts5208/rtsx_transport.c u8 cmd_type, u16 reg_addr, u8 mask, u8 data) mask 203 drivers/staging/rts5208/rtsx_transport.c val |= (u32)mask << 8; mask 34 drivers/staging/rts5208/rtsx_transport.h void rtsx_add_cmd(struct rtsx_chip *chip, u8 cmd_type, u16 reg_addr, u8 mask, mask 580 drivers/staging/rts5208/sd.c u8 mask = 0, val = 0; mask 582 drivers/staging/rts5208/sd.c mask = 0x60; mask 590 drivers/staging/rts5208/sd.c retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); mask 151 drivers/staging/sm750fb/sm750.c fbcursor->mask); mask 89 drivers/staging/sm750fb/sm750_cursor.c u8 color, mask, opr; mask 108 drivers/staging/sm750fb/sm750_cursor.c mask = *pmsk++; mask 112 drivers/staging/sm750fb/sm750_cursor.c if (mask & (0x80 >> j)) { mask 114 drivers/staging/sm750fb/sm750_cursor.c opr = mask ^ color; mask 116 drivers/staging/sm750fb/sm750_cursor.c opr = mask & color; mask 139 drivers/staging/sm750fb/sm750_cursor.c u8 color, mask; mask 158 drivers/staging/sm750fb/sm750_cursor.c mask = *pmsk++; mask 162 drivers/staging/sm750fb/sm750_cursor.c if (mask & (1 << j)) mask 15 drivers/staging/sm750fb/sm750_cursor.h u16 rop, const u8 *data, const u8 *mask); mask 17 drivers/staging/sm750fb/sm750_cursor.h u16 rop, const u8 *data, const u8 *mask); mask 512 drivers/staging/sm750fb/sm750_hw.c unsigned int mask = DE_STATE2_DE_STATUS_BUSY | DE_STATE2_DE_FIFO_EMPTY | mask 518 drivers/staging/sm750fb/sm750_hw.c if ((val & mask) == mask 529 drivers/staging/sm750fb/sm750_hw.c unsigned int mask = SYSTEM_CTRL_DE_STATUS_BUSY | mask 536 drivers/staging/sm750fb/sm750_hw.c if ((val & mask) == mask 467 drivers/staging/speakup/kobjects.c short mask; mask 486 drivers/staging/speakup/kobjects.c mask = pb->mask; mask 488 drivers/staging/speakup/kobjects.c if (!(spk_chartab[i] & mask)) mask 839 drivers/staging/speakup/main.c spk_punc_mask = spk_punc_info[spk_reading_punc].mask; mask 1322 drivers/staging/speakup/main.c short mask = pb_edit->mask, ch_type = spk_chartab[ch]; mask 1331 drivers/staging/speakup/main.c if (mask < PUNC && !(ch_type & PUNC)) mask 1333 drivers/staging/speakup/main.c spk_chartab[ch] ^= mask; mask 1336 drivers/staging/speakup/main.c (spk_chartab[ch] & mask) ? spk_msg_get(MSG_ON) : mask 2369 drivers/staging/speakup/main.c for (i = 1; spk_punc_info[i].mask != 0; i++) mask 140 drivers/staging/speakup/spk_types.h short mask; mask 280 drivers/staging/speakup/varhandlers.c short mask = spk_punc_info[which].mask; mask 284 drivers/staging/speakup/varhandlers.c spk_chartab[*cp] &= ~mask; mask 293 drivers/staging/speakup/varhandlers.c if (mask < PUNC) { mask 307 drivers/staging/speakup/varhandlers.c spk_chartab[*cp] |= mask; mask 311 drivers/staging/speakup/varhandlers.c spk_chartab[*cp] &= ~mask; mask 99 drivers/staging/uwb/include/whci.h u32 mask, u32 result, mask 62 drivers/staging/uwb/whci.c int whci_wait_for(struct device *dev, u32 __iomem *reg, u32 mask, u32 result, mask 69 drivers/staging/uwb/whci.c if ((val & mask) == result) mask 1253 drivers/staging/vc04_services/bcm2835-camera/controls.c u64 mask = ctrl->min; mask 1263 drivers/staging/vc04_services/bcm2835-camera/controls.c mask = BIT(V4L2_SCENE_MODE_NONE); mask 1267 drivers/staging/vc04_services/bcm2835-camera/controls.c mask |= BIT(scene_configs[i].v4l2_scene); mask 1269 drivers/staging/vc04_services/bcm2835-camera/controls.c mask = ~mask; mask 1276 drivers/staging/vc04_services/bcm2835-camera/controls.c mask, ctrl->def); mask 15 drivers/staging/wusbcore/host/whci/hw.c void whc_write_wusbcmd(struct whc *whc, u32 mask, u32 val) mask 23 drivers/staging/wusbcore/host/whci/hw.c cmd = (cmd & ~mask) | val; mask 134 drivers/staging/wusbcore/host/whci/whcd.h void whc_write_wusbcmd(struct whc *whc, u32 mask, u32 val); mask 430 drivers/staging/wusbcore/wa-hc.h static inline s32 __wa_wait_status(struct wahc *wa, u32 mask, u32 value) mask 437 drivers/staging/wusbcore/wa-hc.h if ((result & mask) == value) mask 1508 drivers/target/iscsi/cxgbit/cxgbit_cm.c req->mask = cpu_to_be64(0x3 << 4); mask 1544 drivers/target/iscsi/cxgbit/cxgbit_cm.c req->mask = cpu_to_be64(0x3 << 8); mask 507 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c ra->value &= ra->mask; mask 519 drivers/thermal/intel/int340x_thermal/processor_thermal_device.c val &= ~ra->mask; mask 160 drivers/thermal/intel/intel_bxt_pmic_thermal.c u8 reg_val, mask, irq_stat; mask 173 drivers/thermal/intel/intel_bxt_pmic_thermal.c mask = td->maps[i].trip_config[j].irq_mask; mask 182 drivers/thermal/intel/intel_bxt_pmic_thermal.c irq_stat = ((u8)ret & mask); mask 201 drivers/thermal/intel/intel_bxt_pmic_thermal.c regmap_write(regmap, reg, reg_val & mask); mask 217 drivers/thermal/intel/intel_bxt_pmic_thermal.c u8 mask; mask 259 drivers/thermal/intel/intel_bxt_pmic_thermal.c mask = thermal_data->maps[i].trip_config[j].irq_en_mask; mask 260 drivers/thermal/intel/intel_bxt_pmic_thermal.c ret = regmap_update_bits(regmap, reg, mask, 0x00); mask 144 drivers/thermal/intel/x86_pkg_temp_thermal.c u32 mask, shift, eax, edx; mask 151 drivers/thermal/intel/x86_pkg_temp_thermal.c mask = THERM_MASK_THRESHOLD1; mask 154 drivers/thermal/intel/x86_pkg_temp_thermal.c mask = THERM_MASK_THRESHOLD0; mask 163 drivers/thermal/intel/x86_pkg_temp_thermal.c thres_reg_value = (eax & mask) >> shift; mask 177 drivers/thermal/intel/x86_pkg_temp_thermal.c u32 l, h, mask, shift, intr; mask 189 drivers/thermal/intel/x86_pkg_temp_thermal.c mask = THERM_MASK_THRESHOLD1; mask 193 drivers/thermal/intel/x86_pkg_temp_thermal.c mask = THERM_MASK_THRESHOLD0; mask 197 drivers/thermal/intel/x86_pkg_temp_thermal.c l &= ~mask; mask 1028 drivers/thermal/of-thermal.c int i, mask = 0; mask 1056 drivers/thermal/of-thermal.c mask |= 1 << i; mask 1063 drivers/thermal/of-thermal.c mask, tz, mask 62 drivers/thermal/qcom/tsens-8960.c unsigned int mask; mask 74 drivers/thermal/qcom/tsens-8960.c mask = SLP_CLK_ENA | EN; mask 76 drivers/thermal/qcom/tsens-8960.c mask = SLP_CLK_ENA_8660 | EN; mask 78 drivers/thermal/qcom/tsens-8960.c ret = regmap_update_bits(map, CNTL_ADDR, mask, 0); mask 118 drivers/thermal/qcom/tsens-8960.c u32 reg, mask; mask 124 drivers/thermal/qcom/tsens-8960.c mask = BIT(id + SENSOR0_SHIFT); mask 130 drivers/thermal/qcom/tsens-8960.c reg |= mask | SLP_CLK_ENA | EN; mask 132 drivers/thermal/qcom/tsens-8960.c reg |= mask | SLP_CLK_ENA_8660 | EN; mask 145 drivers/thermal/qcom/tsens-8960.c u32 mask; mask 147 drivers/thermal/qcom/tsens-8960.c mask = GENMASK(priv->num_sensors - 1, 0); mask 148 drivers/thermal/qcom/tsens-8960.c mask <<= SENSOR0_SHIFT; mask 149 drivers/thermal/qcom/tsens-8960.c mask |= EN; mask 155 drivers/thermal/qcom/tsens-8960.c reg_cntl &= ~mask; mask 91 drivers/thermal/qcom/tsens-common.c u32 last_temp = 0, valid, mask; mask 117 drivers/thermal/qcom/tsens-common.c mask = GENMASK(priv->fields[LAST_TEMP_0].msb, mask 120 drivers/thermal/qcom/tsens-common.c *temp = sign_extend32(last_temp, fls(mask) - 1) * 100; mask 161 drivers/thermal/rcar_thermal.c u32 reg, u32 mask, u32 data) mask 166 drivers/thermal/rcar_thermal.c val &= ~mask; mask 167 drivers/thermal/rcar_thermal.c val |= (data & mask); mask 186 drivers/thermal/rcar_thermal.c u32 mask, u32 data) mask 191 drivers/thermal/rcar_thermal.c val &= ~mask; mask 192 drivers/thermal/rcar_thermal.c val |= (data & mask); mask 380 drivers/thermal/rcar_thermal.c u32 mask = 0x3 << rcar_id_to_shift(priv); /* enable Rising/Falling */ mask 387 drivers/thermal/rcar_thermal.c rcar_thermal_common_bset(common, INTMSK, mask, enable ? 0 : mask); mask 440 drivers/thermal/rcar_thermal.c u32 status, mask; mask 444 drivers/thermal/rcar_thermal.c mask = rcar_thermal_common_read(common, INTMSK); mask 446 drivers/thermal/rcar_thermal.c rcar_thermal_common_write(common, STR, 0x000F0F0F & mask); mask 450 drivers/thermal/rcar_thermal.c status = status & ~mask; mask 51 drivers/thermal/st/st_thermal_memmap.c const unsigned int mask = (THERMAL_PDN | THERMAL_SRSTN); mask 52 drivers/thermal/st/st_thermal_memmap.c const unsigned int val = power_state ? mask : 0; mask 54 drivers/thermal/st/st_thermal_memmap.c return regmap_update_bits(sensor->regmap, STIH416_MPE_CONF, mask, val); mask 1372 drivers/thermal/tegra/soctherm.c u32 mask; mask 1377 drivers/thermal/tegra/soctherm.c mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; mask 1378 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 1383 drivers/thermal/tegra/soctherm.c mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; mask 1384 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 1389 drivers/thermal/tegra/soctherm.c mask = THERMCTL_LVL0_CPU0_EN_MASK; mask 1390 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 1393 drivers/thermal/tegra/soctherm.c mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK; mask 1394 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 1405 drivers/thermal/tegra/soctherm.c mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK; mask 1406 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 1417 drivers/thermal/tegra/soctherm.c mask = THERMCTL_LVL0_CPU0_STATUS_MASK; mask 1418 drivers/thermal/tegra/soctherm.c state = REG_GET_MASK(r, mask); mask 868 drivers/thermal/thermal_core.c static void __bind(struct thermal_zone_device *tz, int mask, mask 876 drivers/thermal/thermal_core.c if (mask & (1 << i)) { mask 1104 drivers/thermal/thermal_core.c static void __unbind(struct thermal_zone_device *tz, int mask, mask 1110 drivers/thermal/thermal_core.c if (mask & (1 << i)) mask 1235 drivers/thermal/thermal_core.c thermal_zone_device_register(const char *type, int trips, int mask, mask 1259 drivers/thermal/thermal_core.c if (trips > THERMAL_MAX_TRIPS || trips < 0 || mask >> trips) { mask 1297 drivers/thermal/thermal_core.c result = thermal_zone_create_device_groups(tz, mask); mask 14 drivers/thermal/thermal_mmio.c u32 mask; mask 29 drivers/thermal/thermal_mmio.c t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; mask 97 drivers/thermal/thermal_mmio.c sensor->mask = 0xff; mask 509 drivers/thermal/thermal_sysfs.c static int create_trip_attrs(struct thermal_zone_device *tz, int mask) mask 572 drivers/thermal/thermal_sysfs.c mask & (1 << indx)) { mask 624 drivers/thermal/thermal_sysfs.c int mask) mask 640 drivers/thermal/thermal_sysfs.c result = create_trip_attrs(tz, mask); mask 68 drivers/thermal/ti-soc-thermal/ti-bandgap.c #define RMW_BITS(bgp, id, reg, mask, val) \ mask 75 drivers/thermal/ti-soc-thermal/ti-bandgap.c r &= ~t->mask; \ mask 76 drivers/thermal/ti-soc-thermal/ti-bandgap.c r |= (val) << __ffs(t->mask); \ mask 213 drivers/thermal/uniphier_thermal.c u32 mask = 0, bits = 0; mask 217 drivers/thermal/uniphier_thermal.c mask |= (PMALERTINTCTL_CLR(i) | PMALERTINTCTL_SET(i)); mask 223 drivers/thermal/uniphier_thermal.c tdev->data->map_base + PMALERTINTCTL, mask, bits); mask 61 drivers/thunderbolt/nhi.c int mask = 1 << bit; mask 96 drivers/thunderbolt/nhi.c new = old | mask; mask 98 drivers/thunderbolt/nhi.c new = old & ~mask; mask 336 drivers/thunderbolt/nhi.c static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) mask 344 drivers/thunderbolt/nhi.c if (mask) mask 592 drivers/tty/hvc/hvsi.c packet.mask = cpu_to_be32(HVSI_TSDTR); mask 307 drivers/tty/hvc/hvsi_lib.c ctrl.mask = cpu_to_be32(HVSI_TSDTR); mask 270 drivers/tty/moxa.c u16 rptr, wptr, mask, len; mask 275 drivers/tty/moxa.c mask = readw(ofsAddr + RX_mask); mask 276 drivers/tty/moxa.c len = (wptr - rptr) & mask; mask 1989 drivers/tty/moxa.c u16 rptr, wptr, mask; mask 1993 drivers/tty/moxa.c mask = readw(ofsAddr + TX_mask); mask 1994 drivers/tty/moxa.c return (wptr - rptr) & mask; mask 2000 drivers/tty/moxa.c u16 rptr, wptr, mask; mask 2004 drivers/tty/moxa.c mask = readw(ofsAddr + TX_mask); mask 2005 drivers/tty/moxa.c return mask - ((wptr - rptr) & mask); mask 2011 drivers/tty/moxa.c u16 rptr, wptr, mask; mask 2015 drivers/tty/moxa.c mask = readw(ofsAddr + RX_mask); mask 2016 drivers/tty/moxa.c return (wptr - rptr) & mask; mask 1690 drivers/tty/mxser.c unsigned char val, mask; mask 1704 drivers/tty/mxser.c mask = ModeMask[p]; mask 1708 drivers/tty/mxser.c val &= mask; mask 2597 drivers/tty/n_gsm.c __poll_t mask = 0; mask 2603 drivers/tty/n_gsm.c mask |= EPOLLHUP; mask 2605 drivers/tty/n_gsm.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2607 drivers/tty/n_gsm.c mask |= EPOLLHUP; mask 2608 drivers/tty/n_gsm.c return mask; mask 804 drivers/tty/n_hdlc.c __poll_t mask = 0; mask 818 drivers/tty/n_hdlc.c mask |= EPOLLIN | EPOLLRDNORM; /* readable */ mask 820 drivers/tty/n_hdlc.c mask |= EPOLLHUP; mask 822 drivers/tty/n_hdlc.c mask |= EPOLLHUP; mask 825 drivers/tty/n_hdlc.c mask |= EPOLLOUT | EPOLLWRNORM; /* writable */ mask 827 drivers/tty/n_hdlc.c return mask; mask 2405 drivers/tty/n_tty.c __poll_t mask = 0; mask 2410 drivers/tty/n_tty.c mask |= EPOLLIN | EPOLLRDNORM; mask 2414 drivers/tty/n_tty.c mask |= EPOLLIN | EPOLLRDNORM; mask 2417 drivers/tty/n_tty.c mask |= EPOLLPRI | EPOLLIN | EPOLLRDNORM; mask 2419 drivers/tty/n_tty.c mask |= EPOLLHUP; mask 2421 drivers/tty/n_tty.c mask |= EPOLLHUP; mask 2425 drivers/tty/n_tty.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2426 drivers/tty/n_tty.c return mask; mask 698 drivers/tty/nozomi.c static const u16 mask[] = {MDM_UL, DIAG_UL, APP1_UL, APP2_UL, CTRL_UL}; mask 701 drivers/tty/nozomi.c dc->last_ier |= mask[port]; mask 711 drivers/tty/nozomi.c static const u16 mask[] = mask 715 drivers/tty/nozomi.c dc->last_ier &= mask[port]; mask 725 drivers/tty/nozomi.c static const u16 mask[] = {MDM_DL, DIAG_DL, APP1_DL, APP2_DL, CTRL_DL}; mask 728 drivers/tty/nozomi.c dc->last_ier |= mask[port]; mask 738 drivers/tty/nozomi.c static const u16 mask[] = mask 742 drivers/tty/nozomi.c dc->last_ier &= mask[port]; mask 153 drivers/tty/serial/8250/8250_dma.c dma_cap_mask_t mask; mask 166 drivers/tty/serial/8250/8250_dma.c dma_cap_zero(mask); mask 167 drivers/tty/serial/8250/8250_dma.c dma_cap_set(DMA_SLAVE, mask); mask 170 drivers/tty/serial/8250/8250_dma.c dma->rxchan = dma_request_slave_channel_compat(mask, mask 189 drivers/tty/serial/8250/8250_dma.c dma->txchan = dma_request_slave_channel_compat(mask, mask 397 drivers/tty/serial/8250/8250_exar.c u8 mask = IOT2040_UART1_MASK; mask 413 drivers/tty/serial/8250/8250_exar.c mask <<= IOT2040_UART2_SHIFT; mask 418 drivers/tty/serial/8250/8250_exar.c value &= ~mask; mask 113 drivers/tty/serial/8250/8250_fintek.c static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask, mask 118 drivers/tty/serial/8250/8250_fintek.c tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data); mask 213 drivers/tty/serial/8250/8250_mtk.c static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask) mask 215 drivers/tty/serial/8250/8250_mtk.c serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask)); mask 218 drivers/tty/serial/8250/8250_mtk.c static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask) mask 220 drivers/tty/serial/8250/8250_mtk.c serial_out(up, UART_IER, serial_in(up, UART_IER) | mask); mask 807 drivers/tty/serial/amba-pl010.c .mask = 0x000fffff, mask 414 drivers/tty/serial/amba-pl011.c dma_cap_mask_t mask; mask 431 drivers/tty/serial/amba-pl011.c dma_cap_zero(mask); mask 432 drivers/tty/serial/amba-pl011.c dma_cap_set(DMA_SLAVE, mask); mask 434 drivers/tty/serial/amba-pl011.c chan = dma_request_channel(mask, plat->dma_filter, mask 452 drivers/tty/serial/amba-pl011.c chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); mask 2785 drivers/tty/serial/amba-pl011.c .mask = 0x000fffff, mask 2790 drivers/tty/serial/amba-pl011.c .mask = 0x00ffffff, mask 2795 drivers/tty/serial/amba-pl011.c .mask = 0x00ffffff, mask 66 drivers/tty/serial/ar933x_uart.c unsigned int mask, mask 72 drivers/tty/serial/ar933x_uart.c t &= ~mask; mask 1015 drivers/tty/serial/atmel_serial.c dma_cap_mask_t mask; mask 1019 drivers/tty/serial/atmel_serial.c dma_cap_zero(mask); mask 1020 drivers/tty/serial/atmel_serial.c dma_cap_set(DMA_SLAVE, mask); mask 1195 drivers/tty/serial/atmel_serial.c dma_cap_mask_t mask; mask 1202 drivers/tty/serial/atmel_serial.c dma_cap_zero(mask); mask 1203 drivers/tty/serial/atmel_serial.c dma_cap_set(DMA_CYCLIC, mask); mask 1408 drivers/tty/serial/atmel_serial.c unsigned int status, pending, mask, pass_counter = 0; mask 1414 drivers/tty/serial/atmel_serial.c mask = atmel_uart_readl(port, ATMEL_US_IMR); mask 1415 drivers/tty/serial/atmel_serial.c pending = status & mask; mask 1422 drivers/tty/serial/atmel_serial.c atmel_uart_writel(port, ATMEL_US_IDR, mask); mask 130 drivers/tty/serial/dz.c u16 tmp, mask = 1 << dport->port.line; mask 133 drivers/tty/serial/dz.c tmp &= ~mask; /* clear the TX flag */ mask 140 drivers/tty/serial/dz.c u16 tmp, mask = 1 << dport->port.line; mask 143 drivers/tty/serial/dz.c tmp |= mask; /* set the TX flag */ mask 481 drivers/tty/serial/dz.c unsigned short tmp, mask = 1 << dport->port.line; mask 484 drivers/tty/serial/dz.c tmp &= mask; mask 497 drivers/tty/serial/dz.c unsigned short tmp, mask = 1 << dport->port.line; mask 502 drivers/tty/serial/dz.c tmp |= mask; mask 504 drivers/tty/serial/dz.c tmp &= ~mask; mask 812 drivers/tty/serial/dz.c unsigned short csr, tcr, trdy, mask; mask 820 drivers/tty/serial/dz.c mask = tcr; mask 821 drivers/tty/serial/dz.c dz_out(dport, DZ_TCR, mask); mask 832 drivers/tty/serial/dz.c mask &= ~(1 << trdy); mask 833 drivers/tty/serial/dz.c dz_out(dport, DZ_TCR, mask); mask 307 drivers/tty/serial/max310x.c static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) mask 311 drivers/tty/serial/max310x.c regmap_update_bits(s->regmap, port->iobase + reg, mask, val); mask 1103 drivers/tty/serial/msm_serial.c unsigned int rxstale, watermark, mask; mask 1125 drivers/tty/serial/msm_serial.c mask = UART_DM_IPR_STALE_TIMEOUT_MSB; mask 1128 drivers/tty/serial/msm_serial.c mask = UART_IPR_STALE_TIMEOUT_MSB; mask 1131 drivers/tty/serial/msm_serial.c watermark |= mask & (rxstale << 2); mask 1175 drivers/tty/serial/msm_serial.c unsigned int data, rfr_level, mask; mask 1192 drivers/tty/serial/msm_serial.c mask = UART_DM_MR1_AUTO_RFR_LEVEL1; mask 1194 drivers/tty/serial/msm_serial.c mask = UART_MR1_AUTO_RFR_LEVEL1; mask 1196 drivers/tty/serial/msm_serial.c data &= ~mask; mask 1198 drivers/tty/serial/msm_serial.c data |= mask & (rfr_level << 2); mask 714 drivers/tty/serial/pch_uart.c dma_cap_mask_t mask; mask 720 drivers/tty/serial/pch_uart.c dma_cap_zero(mask); mask 721 drivers/tty/serial/pch_uart.c dma_cap_set(DMA_SLAVE, mask); mask 733 drivers/tty/serial/pch_uart.c chan = dma_request_channel(mask, filter, param); mask 747 drivers/tty/serial/pch_uart.c chan = dma_request_channel(mask, filter, param); mask 297 drivers/tty/serial/sb1250-duart.c unsigned int mask; mask 300 drivers/tty/serial/sb1250-duart.c mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); mask 301 drivers/tty/serial/sb1250-duart.c mask |= M_DUART_IMR_TX; mask 302 drivers/tty/serial/sb1250-duart.c write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); mask 390 drivers/tty/serial/sb1250-duart.c unsigned int mask; mask 417 drivers/tty/serial/sb1250-duart.c mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); mask 418 drivers/tty/serial/sb1250-duart.c mask &= ~M_DUART_IMR_TX; mask 419 drivers/tty/serial/sb1250-duart.c write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); mask 843 drivers/tty/serial/sb1250-duart.c unsigned int mask; mask 847 drivers/tty/serial/sb1250-duart.c mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); mask 849 drivers/tty/serial/sb1250-duart.c mask & ~M_DUART_IMR_TX); mask 860 drivers/tty/serial/sb1250-duart.c write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); mask 402 drivers/tty/serial/sc16is7xx.c u8 mask, u8 val) mask 408 drivers/tty/serial/sc16is7xx.c mask, val); mask 754 drivers/tty/serial/sc16is7xx.c const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | mask 769 drivers/tty/serial/sc16is7xx.c sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); mask 358 drivers/tty/serial/sccnxp.c static void sccnxp_enable_irq(struct uart_port *port, int mask) mask 362 drivers/tty/serial/sccnxp.c s->imr |= mask << (port->line * 4); mask 366 drivers/tty/serial/sccnxp.c static void sccnxp_disable_irq(struct uart_port *port, int mask) mask 370 drivers/tty/serial/sccnxp.c s->imr &= ~(mask << (port->line * 4)); mask 699 drivers/tty/serial/serial_core.c upstat_t mask = UPSTAT_SYNC_FIFO; mask 707 drivers/tty/serial/serial_core.c mask |= UPSTAT_AUTOXOFF; mask 709 drivers/tty/serial/serial_core.c mask |= UPSTAT_AUTORTS; mask 711 drivers/tty/serial/serial_core.c if (port->status & mask) { mask 713 drivers/tty/serial/serial_core.c mask &= ~port->status; mask 716 drivers/tty/serial/serial_core.c if (mask & UPSTAT_AUTORTS) mask 719 drivers/tty/serial/serial_core.c if (mask & UPSTAT_AUTOXOFF) mask 728 drivers/tty/serial/serial_core.c upstat_t mask = UPSTAT_SYNC_FIFO; mask 736 drivers/tty/serial/serial_core.c mask |= UPSTAT_AUTOXOFF; mask 738 drivers/tty/serial/serial_core.c mask |= UPSTAT_AUTORTS; mask 740 drivers/tty/serial/serial_core.c if (port->status & mask) { mask 742 drivers/tty/serial/serial_core.c mask &= ~port->status; mask 745 drivers/tty/serial/serial_core.c if (mask & UPSTAT_AUTORTS) mask 748 drivers/tty/serial/serial_core.c if (mask & UPSTAT_AUTOXOFF) mask 1524 drivers/tty/serial/serial_core.c unsigned int mask = TIOCM_DTR; mask 1526 drivers/tty/serial/serial_core.c mask |= TIOCM_RTS; mask 1527 drivers/tty/serial/serial_core.c uart_set_mctrl(uport, mask); mask 644 drivers/tty/serial/sh-sci.c static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) mask 648 drivers/tty/serial/sh-sci.c serial_port_out(port, SCxSR, mask); mask 653 drivers/tty/serial/sh-sci.c serial_port_in(port, SCxSR) & mask); mask 656 drivers/tty/serial/sh-sci.c serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); mask 833 drivers/tty/synclink.c static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask); mask 2662 drivers/tty/synclink.c int mask; mask 2666 drivers/tty/synclink.c COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); mask 2673 drivers/tty/synclink.c info->device_name, mask); mask 2680 drivers/tty/synclink.c events = mask & mask 2695 drivers/tty/synclink.c if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { mask 2698 drivers/tty/synclink.c (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) + mask 2699 drivers/tty/synclink.c (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0); mask 2739 drivers/tty/synclink.c events = mask & mask 2760 drivers/tty/synclink.c if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { mask 426 drivers/tty/synclink_gt.c #define slgt_irq_on(info, mask) \ mask 427 drivers/tty/synclink_gt.c wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) mask 428 drivers/tty/synclink_gt.c #define slgt_irq_off(info, mask) \ mask 429 drivers/tty/synclink_gt.c wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) mask 2726 drivers/tty/synclink_gt.c int mask; mask 2730 drivers/tty/synclink_gt.c if (get_user(mask, mask_ptr)) mask 2733 drivers/tty/synclink_gt.c DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); mask 2741 drivers/tty/synclink_gt.c events = mask & mask 2756 drivers/tty/synclink_gt.c if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { mask 2796 drivers/tty/synclink_gt.c events = mask & mask 2818 drivers/tty/synclink_gt.c if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { mask 3004 drivers/tty/synclinkmp.c int mask; mask 3008 drivers/tty/synclinkmp.c COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); mask 3015 drivers/tty/synclinkmp.c __FILE__,__LINE__,info->device_name,mask); mask 3023 drivers/tty/synclinkmp.c events = mask & mask 3038 drivers/tty/synclinkmp.c if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { mask 3041 drivers/tty/synclinkmp.c (mask & MgslEvent_ExitHuntMode ? FLGD:0) + mask 3042 drivers/tty/synclinkmp.c (mask & MgslEvent_IdleReceived ? IDLD:0); mask 3083 drivers/tty/synclinkmp.c events = mask & mask 3105 drivers/tty/synclinkmp.c if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { mask 69 drivers/tty/sysrq.c static bool sysrq_on_mask(int mask) mask 73 drivers/tty/sysrq.c (sysrq_enabled & mask); mask 994 drivers/tty/vt/keyboard.c unsigned int mask; mask 1005 drivers/tty/vt/keyboard.c ledstate & trigger->mask ? mask 1017 drivers/tty/vt/keyboard.c .mask = BIT(_led_bit), \ mask 1049 drivers/tty/vt/keyboard.c if (changed & trigger->mask) mask 1051 drivers/tty/vt/keyboard.c new_state & trigger->mask ? mask 512 drivers/tty/vt/vt.c int x, y, mask; mask 536 drivers/tty/vt/vt.c mask = vc->vc_hi_font_mask | 0xff; mask 540 drivers/tty/vt/vt.c u16 glyph = scr_readw(p++) & mask; mask 581 drivers/tty/vt/vt.c int mask = vc->vc_hi_font_mask | 0xff; mask 584 drivers/tty/vt/vt.c u16 glyph = scr_readw(p++) & mask; mask 595 drivers/tty/vt/vt.c int x, y, mask; mask 607 drivers/tty/vt/vt.c mask = vc->vc_hi_font_mask | 0xff; mask 611 drivers/tty/vt/vt.c u16 glyph = scr_readw(p++) & mask; mask 971 drivers/tty/vt/vt.c int mask = vc->vc_hi_font_mask | 0xff; mask 974 drivers/tty/vt/vt.c scr_writew((scr_readw(p)&mask) | (vc->vc_video_erase_char & ~mask), p); mask 650 drivers/tty/vt/vt_ioctl.c unsigned short state, mask; mask 657 drivers/tty/vt/vt_ioctl.c for (i = 0, mask = 2; i < MAX_NR_CONSOLES && mask; mask 658 drivers/tty/vt/vt_ioctl.c ++i, mask <<= 1) mask 660 drivers/tty/vt/vt_ioctl.c state |= mask; mask 150 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_set_bits(struct c67x00_device *dev, u16 reg, u16 mask) mask 157 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_word_nolock(dev, reg, value | mask); mask 161 drivers/usb/c67x00/c67x00-ll-hpi.c static void hpi_clear_bits(struct c67x00_device *dev, u16 reg, u16 mask) mask 168 drivers/usb/c67x00/c67x00-ll-hpi.c hpi_write_word_nolock(dev, reg, value & ~mask); mask 79 drivers/usb/cdns3/gadget.c void cdns3_set_register_bit(void __iomem *ptr, u32 mask) mask 81 drivers/usb/cdns3/gadget.c mask = readl(ptr) | mask; mask 82 drivers/usb/cdns3/gadget.c writel(mask, ptr); mask 1527 drivers/usb/cdns3/gadget.c u32 mask; mask 1530 drivers/usb/cdns3/gadget.c mask = BIT(priv_ep->num + 16); mask 1532 drivers/usb/cdns3/gadget.c mask = BIT(priv_ep->num); mask 1535 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->tdl_from_trb, mask); mask 1536 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->tdl_beh, mask); mask 1537 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->tdl_beh2, mask); mask 1538 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->dma_adv_td, mask); mask 1542 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->tdl_from_trb, mask); mask 1544 drivers/usb/cdns3/gadget.c cdns3_set_register_bit(®s->dtrans, mask); mask 1303 drivers/usb/cdns3/gadget.h void cdns3_set_register_bit(void __iomem *ptr, u32 mask); mask 313 drivers/usb/chipidea/ci.h static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) mask 315 drivers/usb/chipidea/ci.h return ioread32(ci->hw_bank.abs + offset) & mask; mask 326 drivers/usb/chipidea/ci.h u32 mask, u32 data) mask 328 drivers/usb/chipidea/ci.h if (~mask) mask 329 drivers/usb/chipidea/ci.h data = (ioread32(ci->hw_bank.abs + offset) & ~mask) mask 330 drivers/usb/chipidea/ci.h | (data & mask); mask 343 drivers/usb/chipidea/ci.h static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) mask 345 drivers/usb/chipidea/ci.h return ioread32(ci->hw_bank.regmap[reg]) & mask; mask 376 drivers/usb/chipidea/ci.h u32 mask, u32 data) mask 378 drivers/usb/chipidea/ci.h if (~mask) mask 379 drivers/usb/chipidea/ci.h data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) mask 380 drivers/usb/chipidea/ci.h | (data & mask); mask 394 drivers/usb/chipidea/ci.h u32 mask) mask 396 drivers/usb/chipidea/ci.h u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; mask 412 drivers/usb/chipidea/ci.h u32 mask, u32 data) mask 416 drivers/usb/chipidea/ci.h hw_write(ci, reg, mask, data); mask 417 drivers/usb/chipidea/ci.h return (val & mask) >> __ffs(mask); mask 28 drivers/usb/chipidea/otg.c u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask) mask 31 drivers/usb/chipidea/otg.c u32 val = hw_read(ci, OP_OTGSC, mask); mask 73 drivers/usb/chipidea/otg.c return val & mask; mask 81 drivers/usb/chipidea/otg.c void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data) mask 87 drivers/usb/chipidea/otg.c if (data & mask & OTGSC_BSVIS) mask 91 drivers/usb/chipidea/otg.c if (data & mask & OTGSC_BSVIE) { mask 94 drivers/usb/chipidea/otg.c } else if (mask & OTGSC_BSVIE) { mask 101 drivers/usb/chipidea/otg.c if (data & mask & OTGSC_IDIS) mask 105 drivers/usb/chipidea/otg.c if (data & mask & OTGSC_IDIE) { mask 108 drivers/usb/chipidea/otg.c } else if (mask & OTGSC_IDIE) { mask 113 drivers/usb/chipidea/otg.c hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data); mask 151 drivers/usb/chipidea/otg.c u32 mask = OTGSC_BSV; mask 153 drivers/usb/chipidea/otg.c while (hw_read_otgsc(ci, mask)) { mask 156 drivers/usb/chipidea/otg.c mask); mask 11 drivers/usb/chipidea/otg.h u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask); mask 12 drivers/usb/chipidea/otg.h void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data); mask 137 drivers/usb/chipidea/udc.c u32 mask, data; mask 140 drivers/usb/chipidea/udc.c mask = ENDPTCTRL_TXT; /* type */ mask 141 drivers/usb/chipidea/udc.c data = type << __ffs(mask); mask 143 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_TXS; /* unstall */ mask 144 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_TXR; /* reset data toggle */ mask 146 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_TXE; /* enable */ mask 149 drivers/usb/chipidea/udc.c mask = ENDPTCTRL_RXT; /* type */ mask 150 drivers/usb/chipidea/udc.c data = type << __ffs(mask); mask 152 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_RXS; /* unstall */ mask 153 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_RXR; /* reset data toggle */ mask 155 drivers/usb/chipidea/udc.c mask |= ENDPTCTRL_RXE; /* enable */ mask 158 drivers/usb/chipidea/udc.c hw_write(ci, OP_ENDPTCTRL + num, mask, data); mask 171 drivers/usb/chipidea/udc.c u32 mask = (dir == TX) ? ENDPTCTRL_TXS : ENDPTCTRL_RXS; mask 173 drivers/usb/chipidea/udc.c return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0; mask 19 drivers/usb/chipidea/ulpi.c static int ci_ulpi_wait(struct ci_hdrc *ci, u32 mask) mask 24 drivers/usb/chipidea/ulpi.c if (!hw_read(ci, OP_ULPI_VIEWPORT, mask)) mask 614 drivers/usb/class/cdc-wdm.c __poll_t mask = 0; mask 618 drivers/usb/class/cdc-wdm.c mask = EPOLLHUP | EPOLLERR; mask 623 drivers/usb/class/cdc-wdm.c mask = EPOLLIN | EPOLLRDNORM; mask 625 drivers/usb/class/cdc-wdm.c mask |= EPOLLERR; mask 627 drivers/usb/class/cdc-wdm.c mask |= EPOLLOUT | EPOLLWRNORM; mask 633 drivers/usb/class/cdc-wdm.c return mask; mask 2173 drivers/usb/class/usbtmc.c __poll_t mask; mask 2178 drivers/usb/class/usbtmc.c mask = EPOLLHUP | EPOLLERR; mask 2187 drivers/usb/class/usbtmc.c mask = 0; mask 2189 drivers/usb/class/usbtmc.c mask |= EPOLLPRI; mask 2196 drivers/usb/class/usbtmc.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 2198 drivers/usb/class/usbtmc.c mask |= (EPOLLIN | EPOLLRDNORM); mask 2202 drivers/usb/class/usbtmc.c mask |= EPOLLERR; mask 2205 drivers/usb/class/usbtmc.c dev_dbg(&data->intf->dev, "poll mask = %x\n", mask); mask 2209 drivers/usb/class/usbtmc.c return mask; mask 1519 drivers/usb/core/devio.c unsigned long mask = USBDEVFS_URB_SHORT_NOT_OK | mask 1526 drivers/usb/core/devio.c mask |= USBDEVFS_URB_ISO_ASAP; mask 1528 drivers/usb/core/devio.c if (uurb->flags & ~mask) mask 2727 drivers/usb/core/devio.c __poll_t mask = 0; mask 2731 drivers/usb/core/devio.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2733 drivers/usb/core/devio.c mask |= EPOLLHUP; mask 2735 drivers/usb/core/devio.c mask |= EPOLLERR; mask 2736 drivers/usb/core/devio.c return mask; mask 6032 drivers/usb/core/hub.c u8 mask = 1 << (i%8); mask 6034 drivers/usb/core/hub.c if (!(desc->u.hs.DeviceRemovable[i/8] & mask)) { mask 6036 drivers/usb/core/hub.c desc->u.hs.DeviceRemovable[i/8] |= mask; mask 6048 drivers/usb/core/hub.c u16 mask = 1 << i; mask 6050 drivers/usb/core/hub.c if (!(port_removable & mask)) { mask 6052 drivers/usb/core/hub.c port_removable |= mask; mask 986 drivers/usb/dwc2/core.c int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, mask 992 drivers/usb/dwc2/core.c if (dwc2_readl(hsotg, offset) & mask) mask 1009 drivers/usb/dwc2/core.c int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, mask 1015 drivers/usb/dwc2/core.c if (!(dwc2_readl(hsotg, offset) & mask)) mask 743 drivers/usb/dwc2/gadget.c static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask) mask 751 drivers/usb/dwc2/gadget.c *mask = DEV_DMA_NBYTES_MASK; mask 755 drivers/usb/dwc2/gadget.c *mask = DEV_DMA_ISOC_TX_NBYTES_MASK; mask 758 drivers/usb/dwc2/gadget.c *mask = DEV_DMA_ISOC_RX_NBYTES_MASK; mask 762 drivers/usb/dwc2/gadget.c *mask = DEV_DMA_NBYTES_MASK; mask 781 drivers/usb/dwc2/gadget.c u32 mask = 0; mask 784 drivers/usb/dwc2/gadget.c maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); mask 801 drivers/usb/dwc2/gadget.c maxsize << DEV_DMA_NBYTES_SHIFT & mask; mask 816 drivers/usb/dwc2/gadget.c len << DEV_DMA_NBYTES_SHIFT & mask; mask 886 drivers/usb/dwc2/gadget.c u32 mask = 0; mask 889 drivers/usb/dwc2/gadget.c maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); mask 913 drivers/usb/dwc2/gadget.c ((len << DEV_DMA_NBYTES_SHIFT) & mask)); mask 1370 drivers/usb/dwc2/gadget.c u32 mask = 0; mask 1400 drivers/usb/dwc2/gadget.c maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask); mask 1708 drivers/usb/dwc2/gadget.c u32 mask; mask 1728 drivers/usb/dwc2/gadget.c mask = dwc2_readl(hsotg, epmsk_reg); mask 1729 drivers/usb/dwc2/gadget.c mask |= DOEPMSK_OUTTKNEPDISMSK; mask 1730 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, mask, epmsk_reg); mask 2151 drivers/usb/dwc2/gadget.c u32 mask; mask 2169 drivers/usb/dwc2/gadget.c mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK : mask 2171 drivers/usb/dwc2/gadget.c ureq->actual = ureq->length - ((desc_sts & mask) >> mask 2762 drivers/usb/dwc2/gadget.c u32 mask; mask 2765 drivers/usb/dwc2/gadget.c mask = dwc2_readl(hsotg, epmsk_reg); mask 2767 drivers/usb/dwc2/gadget.c mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; mask 2768 drivers/usb/dwc2/gadget.c mask |= DXEPINT_SETUP_RCVD; mask 2771 drivers/usb/dwc2/gadget.c ints &= mask; mask 3932 drivers/usb/dwc2/gadget.c u32 mask; mask 4031 drivers/usb/dwc2/gadget.c mask = dwc2_readl(hsotg, DIEPMSK); mask 4032 drivers/usb/dwc2/gadget.c mask |= DIEPMSK_NAKMSK; mask 4033 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, mask, DIEPMSK); mask 4035 drivers/usb/dwc2/gadget.c mask = dwc2_readl(hsotg, DOEPMSK); mask 4036 drivers/usb/dwc2/gadget.c mask |= DOEPMSK_OUTTKNEPDISMSK; mask 4037 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, mask, DOEPMSK); mask 475 drivers/usb/dwc2/hcd.h u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum)); mask 477 drivers/usb/dwc2/hcd.h mask &= ~intr; mask 478 drivers/usb/dwc2/hcd.h dwc2_writel(hsotg, mask, HCINTMSK(chnum)); mask 134 drivers/usb/early/xhci-dbc.c static int handshake(void __iomem *ptr, u32 mask, u32 done, int wait, int delay) mask 140 drivers/usb/early/xhci-dbc.c result &= mask; mask 654 drivers/usb/gadget/function/f_fs.c __poll_t mask = EPOLLWRNORM; mask 661 drivers/usb/gadget/function/f_fs.c return mask; mask 666 drivers/usb/gadget/function/f_fs.c mask |= EPOLLOUT; mask 673 drivers/usb/gadget/function/f_fs.c mask |= EPOLLIN; mask 678 drivers/usb/gadget/function/f_fs.c mask |= (EPOLLIN | EPOLLOUT); mask 689 drivers/usb/gadget/function/f_fs.c return mask; mask 1658 drivers/usb/gadget/function/f_mass_storage.c enum data_direction data_dir, unsigned int mask, mask 1768 drivers/usb/gadget/function/f_mass_storage.c if (common->cmnd[i] && !(mask & (1 << i))) { mask 1788 drivers/usb/gadget/function/f_mass_storage.c unsigned int mask, int needs_medium, const char *name) mask 1793 drivers/usb/gadget/function/f_mass_storage.c mask, needs_medium, name); mask 1217 drivers/usb/gadget/legacy/inode.c __poll_t mask = 0; mask 1229 drivers/usb/gadget/legacy/inode.c mask = EPOLLHUP; mask 1235 drivers/usb/gadget/legacy/inode.c mask = EPOLLOUT; mask 1238 drivers/usb/gadget/legacy/inode.c mask = EPOLLIN; mask 1242 drivers/usb/gadget/legacy/inode.c return mask; mask 128 drivers/usb/gadget/udc/aspeed-vhub/core.c u32 mask = VHUB_EP_IRQ(i); mask 129 drivers/usb/gadget/udc/aspeed-vhub/core.c if (ep_acks & mask) { mask 131 drivers/usb/gadget/udc/aspeed-vhub/core.c ep_acks &= ~mask; mask 163 drivers/usb/gadget/udc/at91_udc.c static void proc_irq_show(struct seq_file *s, const char *label, u32 mask) mask 167 drivers/usb/gadget/udc/at91_udc.c seq_printf(s, "%s %04x:%s%s" FOURBITS, label, mask, mask 168 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 13)) ? " wakeup" : "", mask 169 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 12)) ? " endbusres" : "", mask 171 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 11)) ? " sofint" : "", mask 172 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 10)) ? " extrsm" : "", mask 173 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 9)) ? " rxrsm" : "", mask 174 drivers/usb/gadget/udc/at91_udc.c (mask & (1 << 8)) ? " rxsusp" : ""); mask 176 drivers/usb/gadget/udc/at91_udc.c if (mask & (1 << i)) mask 1487 drivers/usb/gadget/udc/at91_udc.c unsigned mask = 1; mask 1490 drivers/usb/gadget/udc/at91_udc.c if (status & mask) mask 1493 drivers/usb/gadget/udc/at91_udc.c mask <<= 1; mask 1494 drivers/usb/gadget/udc/at91_udc.c if (status & mask) mask 362 drivers/usb/gadget/udc/atmel_usba_udc.c static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask) mask 366 drivers/usb/gadget/udc/atmel_usba_udc.c val = udc->int_enb_cache | mask; mask 371 drivers/usb/gadget/udc/atmel_usba_udc.c static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask) mask 375 drivers/usb/gadget/udc/atmel_usba_udc.c val = udc->int_enb_cache & ~mask; mask 1283 drivers/usb/gadget/udc/fusb300_udc.c u32 mask = 0; mask 1287 drivers/usb/gadget/udc/fusb300_udc.c mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON; mask 1289 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~mask; mask 1294 drivers/usb/gadget/udc/fusb300_udc.c mask = val = FUSB300_HSCR_HS_LPM_PERMIT; mask 1296 drivers/usb/gadget/udc/fusb300_udc.c reg &= ~mask; mask 1055 drivers/usb/gadget/udc/goku_udc.c static void dump_intmask(struct seq_file *m, const char *label, u32 mask) mask 1059 drivers/usb/gadget/udc/goku_udc.c label, mask, mask 1060 drivers/usb/gadget/udc/goku_udc.c (mask & INT_PWRDETECT) ? " power" : "", mask 1061 drivers/usb/gadget/udc/goku_udc.c (mask & INT_SYSERROR) ? " sys" : "", mask 1062 drivers/usb/gadget/udc/goku_udc.c (mask & INT_MSTRDEND) ? " in-dma" : "", mask 1063 drivers/usb/gadget/udc/goku_udc.c (mask & INT_MSTWRTMOUT) ? " wrtmo" : "", mask 1065 drivers/usb/gadget/udc/goku_udc.c (mask & INT_MSTWREND) ? " out-dma" : "", mask 1066 drivers/usb/gadget/udc/goku_udc.c (mask & INT_MSTWRSET) ? " wrset" : "", mask 1067 drivers/usb/gadget/udc/goku_udc.c (mask & INT_ERR) ? " err" : "", mask 1068 drivers/usb/gadget/udc/goku_udc.c (mask & INT_SOF) ? " sof" : "", mask 1070 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP3NAK) ? " ep3nak" : "", mask 1071 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP2NAK) ? " ep2nak" : "", mask 1072 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP1NAK) ? " ep1nak" : "", mask 1073 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP3DATASET) ? " ep3" : "", mask 1075 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP2DATASET) ? " ep2" : "", mask 1076 drivers/usb/gadget/udc/goku_udc.c (mask & INT_EP1DATASET) ? " ep1" : "", mask 1077 drivers/usb/gadget/udc/goku_udc.c (mask & INT_STATUSNAK) ? " ep0snak" : "", mask 1078 drivers/usb/gadget/udc/goku_udc.c (mask & INT_STATUS) ? " ep0status" : "", mask 1080 drivers/usb/gadget/udc/goku_udc.c (mask & INT_SETUP) ? " setup" : "", mask 1081 drivers/usb/gadget/udc/goku_udc.c (mask & INT_ENDPOINT0) ? " ep0" : "", mask 1082 drivers/usb/gadget/udc/goku_udc.c (mask & INT_USBRESET) ? " reset" : "", mask 1083 drivers/usb/gadget/udc/goku_udc.c (mask & INT_SUSPEND) ? " suspend" : ""); mask 776 drivers/usb/gadget/udc/lpc32xx_udc.c static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) mask 778 drivers/usb/gadget/udc/lpc32xx_udc.c udc->enabled_devints &= ~mask; mask 783 drivers/usb/gadget/udc/lpc32xx_udc.c static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) mask 785 drivers/usb/gadget/udc/lpc32xx_udc.c writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); mask 1964 drivers/usb/gadget/udc/net2272.c u8 tmp, mask; mask 1968 drivers/usb/gadget/udc/net2272.c mask = (1 << USB_HIGH_SPEED) | (1 << USB_FULL_SPEED); mask 1987 drivers/usb/gadget/udc/net2272.c (net2272_read(dev, USBCTL1) & mask) mask 360 drivers/usb/gadget/udc/net2280.c static int handshake(u32 __iomem *ptr, u32 mask, u32 done, int usec) mask 368 drivers/usb/gadget/udc/net2280.c result &= mask; mask 3314 drivers/usb/gadget/udc/net2280.c u32 mask = (BIT(ENDPOINT_0_INTERRUPT) | mask 3318 drivers/usb/gadget/udc/net2280.c if (stat & mask) { mask 3319 drivers/usb/gadget/udc/net2280.c usb338x_handle_ep_intr(dev, stat & mask); mask 3320 drivers/usb/gadget/udc/net2280.c stat &= ~mask; mask 3358 drivers/usb/gadget/udc/net2280.c u32 tmp, num, mask, scratch; mask 3362 drivers/usb/gadget/udc/net2280.c mask = BIT(SUPER_SPEED) | BIT(HIGH_SPEED) | BIT(FULL_SPEED); mask 3386 drivers/usb/gadget/udc/net2280.c (readl(&dev->usb->usbstat) & mask) mask 807 drivers/usb/gadget/udc/omap_udc.c u16 mask = 0x0f << shift; mask 830 drivers/usb/gadget/udc/omap_udc.c omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, mask 841 drivers/usb/gadget/udc/omap_udc.c while (omap_readw(UDC_TXDMA_CFG) & mask) mask 844 drivers/usb/gadget/udc/omap_udc.c omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, mask 848 drivers/usb/gadget/udc/omap_udc.c while (omap_readw(UDC_RXDMA_CFG) & mask) mask 782 drivers/usb/gadget/udc/pch_udc.c u32 mask) mask 784 drivers/usb/gadget/udc/pch_udc.c pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask); mask 793 drivers/usb/gadget/udc/pch_udc.c u32 mask) mask 795 drivers/usb/gadget/udc/pch_udc.c pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask); mask 804 drivers/usb/gadget/udc/pch_udc.c u32 mask) mask 806 drivers/usb/gadget/udc/pch_udc.c pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask); mask 815 drivers/usb/gadget/udc/pch_udc.c u32 mask) mask 817 drivers/usb/gadget/udc/pch_udc.c pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask); mask 351 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask) mask 355 drivers/usb/gadget/udc/pxa25x_udc.c udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR); mask 358 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask) mask 362 drivers/usb/gadget/udc/pxa25x_udc.c udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR); mask 365 drivers/usb/gadget/udc/pxa25x_udc.c static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask) mask 370 drivers/usb/gadget/udc/pxa25x_udc.c udc_set_reg(dev, udccr | (mask & ~UDCCR_MASK_BITS), UDCCR); mask 366 drivers/usb/gadget/udc/pxa27x_udc.c static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask) mask 370 drivers/usb/gadget/udc/pxa27x_udc.c (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS)); mask 380 drivers/usb/gadget/udc/pxa27x_udc.c static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask) mask 384 drivers/usb/gadget/udc/pxa27x_udc.c (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS)); mask 397 drivers/usb/gadget/udc/pxa27x_udc.c static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask) mask 400 drivers/usb/gadget/udc/pxa27x_udc.c mask |= UDCCSR0_ACM; mask 401 drivers/usb/gadget/udc/pxa27x_udc.c udc_ep_writel(ep, UDCCSR, mask); mask 272 drivers/usb/gadget/udc/r8a66597-udc.c u16 tmp, mask, loop; mask 276 drivers/usb/gadget/udc/r8a66597-udc.c mask = ISEL | CURPIPE; mask 279 drivers/usb/gadget/udc/r8a66597-udc.c mask = CURPIPE; mask 282 drivers/usb/gadget/udc/r8a66597-udc.c r8a66597_mdfy(r8a66597, loop, mask, fifosel); mask 293 drivers/usb/gadget/udc/r8a66597-udc.c } while ((tmp & mask) != loop); mask 422 drivers/usb/gadget/udc/renesas_usb3.c static int usb3_wait(struct renesas_usb3 *usb3, u32 reg, u32 mask, mask 428 drivers/usb/gadget/udc/renesas_usb3.c if ((usb3_read(usb3, reg) & mask) == expected) mask 434 drivers/usb/gadget/udc/renesas_usb3.c __func__, reg, mask, expected); mask 1055 drivers/usb/gadget/udc/renesas_usb3.c static int usb3_wait_pipe_status(struct renesas_usb3_ep *usb3_ep, u32 mask) mask 1060 drivers/usb/gadget/udc/renesas_usb3.c return usb3_wait(usb3, sta_reg, mask, mask); mask 148 drivers/usb/host/ehci-hcd.c u32 mask, u32 done, int usec) mask 156 drivers/usb/host/ehci-hcd.c result &= mask; mask 1138 drivers/usb/host/ehci-hcd.c int mask = INTR_MASK; mask 1147 drivers/usb/host/ehci-hcd.c mask &= ~STS_PCD; mask 1148 drivers/usb/host/ehci-hcd.c ehci_writel(ehci, mask, &ehci->regs->intr_enable); mask 218 drivers/usb/host/ehci-hub.c int mask; mask 356 drivers/usb/host/ehci-hub.c mask = INTR_MASK; mask 358 drivers/usb/host/ehci-hub.c mask &= ~STS_PCD; mask 359 drivers/usb/host/ehci-hub.c ehci_writel(ehci, mask, &ehci->regs->intr_enable); mask 620 drivers/usb/host/ehci-hub.c u32 mask; mask 645 drivers/usb/host/ehci-hub.c mask = PORT_CSC | PORT_PEC | PORT_OCC; mask 647 drivers/usb/host/ehci-hub.c mask = PORT_CSC | PORT_PEC; mask 673 drivers/usb/host/ehci-hub.c if ((temp & mask) != 0 || test_bit(i, &ehci->port_c_suspend) mask 318 drivers/usb/host/ehci-sched.c static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask) mask 320 drivers/usb/host/ehci-sched.c unsigned char smask = hc32_to_cpu(ehci, mask) & QH_SMASK; mask 458 drivers/usb/host/ehci-sched.c u32 mask; mask 460 drivers/usb/host/ehci-sched.c mask = hc32_to_cpu(ehci, mask 463 drivers/usb/host/ehci-sched.c mask |= mask >> 8; mask 464 drivers/usb/host/ehci-sched.c if (mask & uf_mask) mask 472 drivers/usb/host/ehci-sched.c u16 mask; mask 474 drivers/usb/host/ehci-sched.c mask = hc32_to_cpu(ehci, here.sitd mask 477 drivers/usb/host/ehci-sched.c mask |= mask >> 8; mask 478 drivers/usb/host/ehci-sched.c if (mask & uf_mask) mask 791 drivers/usb/host/ehci-sched.c u8 mask = 0; mask 814 drivers/usb/host/ehci-sched.c mask |= 1 << i; mask 818 drivers/usb/host/ehci-sched.c *c_maskp = mask; mask 828 drivers/usb/host/ehci-sched.c mask = 0x03 << (uframe + qh->gap_uf); mask 829 drivers/usb/host/ehci-sched.c *c_maskp = mask; mask 831 drivers/usb/host/ehci-sched.c mask |= 1 << uframe; mask 832 drivers/usb/host/ehci-sched.c if (tt_no_collision(ehci, qh->ps.bw_period, qh->ps.udev, frame, mask)) { mask 1401 drivers/usb/host/ehci-sched.c unsigned mask, tmp; mask 1404 drivers/usb/host/ehci-sched.c mask = stream->ps.cs_mask << (uframe & 7); mask 1411 drivers/usb/host/ehci-sched.c if (mask & ~0xffff) mask 1430 drivers/usb/host/ehci-sched.c stream->ps.udev, frame, mask)) mask 883 drivers/usb/host/ehci.h u32 mask, u32 done, int usec); mask 151 drivers/usb/host/fhci-hub.c u16 mask; mask 161 drivers/usb/host/fhci-hub.c mask = in_be16(&fhci->regs->usb_usbmr); mask 162 drivers/usb/host/fhci-hub.c out_be16(&fhci->regs->usb_usbmr, mask & (~USB_E_IDLE_MASK)); mask 167 drivers/usb/host/fhci-hub.c out_be16(&fhci->regs->usb_usbmr, mask); mask 883 drivers/usb/host/fotg210-hcd.c u32 mask, u32 done, int usec) mask 891 drivers/usb/host/fotg210-hcd.c result &= mask; mask 1398 drivers/usb/host/fotg210-hcd.c u32 mask; mask 1410 drivers/usb/host/fotg210-hcd.c mask = PORT_CSC | PORT_PEC; mask 1427 drivers/usb/host/fotg210-hcd.c if ((temp & mask) != 0 || test_bit(0, &fotg210->port_c_suspend) || mask 3427 drivers/usb/host/fotg210-hcd.c u32 mask; mask 3429 drivers/usb/host/fotg210-hcd.c mask = hc32_to_cpu(fotg210, mask 3432 drivers/usb/host/fotg210-hcd.c mask |= mask >> 8; mask 3433 drivers/usb/host/fotg210-hcd.c if (mask & uf_mask) mask 3718 drivers/usb/host/fotg210-hcd.c u8 mask = 0; mask 3738 drivers/usb/host/fotg210-hcd.c mask = 0x03 << (uframe + qh->gap_uf); mask 3739 drivers/usb/host/fotg210-hcd.c *c_maskp = cpu_to_hc32(fotg210, mask << 8); mask 3741 drivers/usb/host/fotg210-hcd.c mask |= 1 << uframe; mask 3742 drivers/usb/host/fotg210-hcd.c if (tt_no_collision(fotg210, qh->period, qh->dev, frame, mask)) { mask 75 drivers/usb/host/imx21-hcd.c static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask) mask 78 drivers/usb/host/imx21-hcd.c writel(readl(reg) | mask, reg); mask 82 drivers/usb/host/imx21-hcd.c u32 offset, u32 mask) mask 85 drivers/usb/host/imx21-hcd.c writel(readl(reg) & ~mask, reg); mask 88 drivers/usb/host/imx21-hcd.c static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask) mask 92 drivers/usb/host/imx21-hcd.c if (readl(reg) & mask) mask 93 drivers/usb/host/imx21-hcd.c writel(mask, reg); mask 96 drivers/usb/host/imx21-hcd.c static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask) mask 100 drivers/usb/host/imx21-hcd.c if (!(readl(reg) & mask)) mask 101 drivers/usb/host/imx21-hcd.c writel(mask, reg); mask 1149 drivers/usb/host/isp116x-hcd.c static void dump_irq(struct seq_file *s, char *label, u16 mask) mask 1151 drivers/usb/host/isp116x-hcd.c seq_printf(s, "%s %04x%s%s%s%s%s%s\n", label, mask, mask 1152 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_CLKRDY ? " clkrdy" : "", mask 1153 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_SUSP ? " susp" : "", mask 1154 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_OPR ? " opr" : "", mask 1155 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_AIIEOT ? " eot" : "", mask 1156 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_ATL ? " atl" : "", mask 1157 drivers/usb/host/isp116x-hcd.c mask & HCuPINT_SOF ? " sof" : ""); mask 1160 drivers/usb/host/isp116x-hcd.c static void dump_int(struct seq_file *s, char *label, u32 mask) mask 1162 drivers/usb/host/isp116x-hcd.c seq_printf(s, "%s %08x%s%s%s%s%s%s%s\n", label, mask, mask 1163 drivers/usb/host/isp116x-hcd.c mask & HCINT_MIE ? " MIE" : "", mask 1164 drivers/usb/host/isp116x-hcd.c mask & HCINT_RHSC ? " rhsc" : "", mask 1165 drivers/usb/host/isp116x-hcd.c mask & HCINT_FNO ? " fno" : "", mask 1166 drivers/usb/host/isp116x-hcd.c mask & HCINT_UE ? " ue" : "", mask 1167 drivers/usb/host/isp116x-hcd.c mask & HCINT_RD ? " rd" : "", mask 1168 drivers/usb/host/isp116x-hcd.c mask & HCINT_SF ? " sof" : "", mask & HCINT_SO ? " so" : ""); mask 119 drivers/usb/host/isp1362-hcd.c static inline void isp1362_enable_int(struct isp1362_hcd *isp1362_hcd, u16 mask) mask 121 drivers/usb/host/isp1362-hcd.c if ((isp1362_hcd->irqenb | mask) == isp1362_hcd->irqenb) mask 123 drivers/usb/host/isp1362-hcd.c if (mask & ~isp1362_hcd->irqenb) mask 124 drivers/usb/host/isp1362-hcd.c isp1362_write_reg16(isp1362_hcd, HCuPINT, mask & ~isp1362_hcd->irqenb); mask 125 drivers/usb/host/isp1362-hcd.c isp1362_hcd->irqenb |= mask; mask 1917 drivers/usb/host/isp1362-hcd.c static void dump_irq(struct seq_file *s, char *label, u16 mask) mask 1919 drivers/usb/host/isp1362-hcd.c seq_printf(s, "%-15s %04x%s%s%s%s%s%s\n", label, mask, mask 1920 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_CLKRDY ? " clkrdy" : "", mask 1921 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_SUSP ? " susp" : "", mask 1922 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_OPR ? " opr" : "", mask 1923 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_EOT ? " eot" : "", mask 1924 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_ATL ? " atl" : "", mask 1925 drivers/usb/host/isp1362-hcd.c mask & HCuPINT_SOF ? " sof" : ""); mask 1928 drivers/usb/host/isp1362-hcd.c static void dump_int(struct seq_file *s, char *label, u32 mask) mask 1930 drivers/usb/host/isp1362-hcd.c seq_printf(s, "%-15s %08x%s%s%s%s%s%s%s\n", label, mask, mask 1931 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_MIE ? " MIE" : "", mask 1932 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_RHSC ? " rhsc" : "", mask 1933 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_FNO ? " fno" : "", mask 1934 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_UE ? " ue" : "", mask 1935 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_RD ? " rd" : "", mask 1936 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_SF ? " sof" : "", mask 1937 drivers/usb/host/isp1362-hcd.c mask & OHCI_INTR_SO ? " so" : ""); mask 1940 drivers/usb/host/isp1362-hcd.c static void dump_ctrl(struct seq_file *s, char *label, u32 mask) mask 1942 drivers/usb/host/isp1362-hcd.c seq_printf(s, "%-15s %08x%s%s%s\n", label, mask, mask 1943 drivers/usb/host/isp1362-hcd.c mask & OHCI_CTRL_RWC ? " rwc" : "", mask 1944 drivers/usb/host/isp1362-hcd.c mask & OHCI_CTRL_RWE ? " rwe" : "", mask 1947 drivers/usb/host/isp1362-hcd.c switch (mask & OHCI_CTRL_HCFS) { mask 1676 drivers/usb/host/max3421-hcd.c u8 mask, idx; mask 1682 drivers/usb/host/max3421-hcd.c mask = 1u << (pin_number % 4); mask 1686 drivers/usb/host/max3421-hcd.c max3421_hcd->iopins[idx] |= mask; mask 1688 drivers/usb/host/max3421-hcd.c max3421_hcd->iopins[idx] &= ~mask; mask 45 drivers/usb/host/ohci-dbg.c u32 mask, mask 51 drivers/usb/host/ohci-dbg.c mask, mask 52 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_MIE) ? " MIE" : "", mask 53 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_OC) ? " OC" : "", mask 54 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_RHSC) ? " RHSC" : "", mask 55 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_FNO) ? " FNO" : "", mask 56 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_UE) ? " UE" : "", mask 57 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_RD) ? " RD" : "", mask 58 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_SF) ? " SF" : "", mask 59 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_WDH) ? " WDH" : "", mask 60 drivers/usb/host/ohci-dbg.c (mask & OHCI_INTR_SO) ? " SO" : "" mask 547 drivers/usb/host/ohci-hcd.c u32 mask, val; mask 670 drivers/usb/host/ohci-hcd.c mask = OHCI_INTR_INIT; mask 672 drivers/usb/host/ohci-hcd.c ohci_writel (ohci, mask, &ohci->regs->intrenable); mask 709 drivers/usb/host/ohci.h #define read_roothub(hc, register, mask) ({ \ mask 714 drivers/usb/host/ohci.h while (temp & mask) \ mask 748 drivers/usb/host/oxu210hp-hcd.c u32 mask, u32 done, int usec) mask 756 drivers/usb/host/oxu210hp-hcd.c result &= mask; mask 3488 drivers/usb/host/oxu210hp-hcd.c u32 temp, mask, status = 0; mask 3511 drivers/usb/host/oxu210hp-hcd.c mask = PORT_CSC | PORT_PEC | PORT_OCC; mask 3513 drivers/usb/host/oxu210hp-hcd.c mask = PORT_CSC | PORT_PEC; mask 3531 drivers/usb/host/oxu210hp-hcd.c if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 && mask 3858 drivers/usb/host/oxu210hp-hcd.c int mask; mask 3915 drivers/usb/host/oxu210hp-hcd.c mask = INTR_MASK; mask 3917 drivers/usb/host/oxu210hp-hcd.c mask &= ~STS_PCD; mask 3918 drivers/usb/host/oxu210hp-hcd.c writel(mask, &oxu->regs->intr_enable); mask 714 drivers/usb/host/pci-quirks.c static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) mask 717 drivers/usb/host/pci-quirks.c return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); mask 1007 drivers/usb/host/pci-quirks.c static int handshake(void __iomem *ptr, u32 mask, u32 done, mask 1014 drivers/usb/host/pci-quirks.c result &= mask; mask 435 drivers/usb/host/r8a66597-hcd.c u16 mask, u16 loop) mask 448 drivers/usb/host/r8a66597-hcd.c } while ((tmp & mask) != loop); mask 1501 drivers/usb/host/r8a66597-hcd.c u16 mask; mask 1504 drivers/usb/host/r8a66597-hcd.c mask = r8a66597_read(r8a66597, BRDYSTS) mask 1506 drivers/usb/host/r8a66597-hcd.c r8a66597_write(r8a66597, ~mask, BRDYSTS); mask 1507 drivers/usb/host/r8a66597-hcd.c if (mask & BRDY0) { mask 1518 drivers/usb/host/r8a66597-hcd.c if (mask & check) { mask 1536 drivers/usb/host/r8a66597-hcd.c u16 mask; mask 1539 drivers/usb/host/r8a66597-hcd.c mask = r8a66597_read(r8a66597, BEMPSTS) mask 1541 drivers/usb/host/r8a66597-hcd.c r8a66597_write(r8a66597, ~mask, BEMPSTS); mask 1542 drivers/usb/host/r8a66597-hcd.c if (mask & BEMP0) { mask 1552 drivers/usb/host/r8a66597-hcd.c if (mask & check) { mask 1573 drivers/usb/host/r8a66597-hcd.c u16 mask; mask 1576 drivers/usb/host/r8a66597-hcd.c mask = r8a66597_read(r8a66597, NRDYSTS) mask 1578 drivers/usb/host/r8a66597-hcd.c r8a66597_write(r8a66597, ~mask, NRDYSTS); mask 1579 drivers/usb/host/r8a66597-hcd.c if (mask & NRDY0) { mask 1588 drivers/usb/host/r8a66597-hcd.c if (mask & check) { mask 1128 drivers/usb/host/sl811-hcd.c const u32 mask = USB_PORT_STAT_CONNECTION mask 1167 drivers/usb/host/sl811-hcd.c sl811->port1 &= ~mask; mask 1170 drivers/usb/host/sl811-hcd.c sl811->port1 |= mask; mask 1373 drivers/usb/host/sl811-hcd.c static void dump_irq(struct seq_file *s, char *label, u8 mask) mask 1375 drivers/usb/host/sl811-hcd.c seq_printf(s, "%s %02x%s%s%s%s%s%s\n", label, mask, mask 1376 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_DONE_A) ? " done_a" : "", mask 1377 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_DONE_B) ? " done_b" : "", mask 1378 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_SOFINTR) ? " sof" : "", mask 1379 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_INSRMV) ? " ins/rmv" : "", mask 1380 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_RD) ? " rd" : "", mask 1381 drivers/usb/host/sl811-hcd.c (mask & SL11H_INTMASK_DP) ? " dp" : ""); mask 1598 drivers/usb/host/u132-hcd.c int mask = OHCI_INTR_INIT; mask 1729 drivers/usb/host/u132-hcd.c retval = u132_write_pcimem(u132, intrstatus, mask); mask 60 drivers/usb/host/uhci-hub.c int mask = RWC_BITS; mask 69 drivers/usb/host/uhci-hub.c mask &= ~USBPORTSC_OCC; mask 73 drivers/usb/host/uhci-hub.c if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) || mask 1526 drivers/usb/host/xhci-hub.c u32 mask; mask 1550 drivers/usb/host/xhci-hub.c mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; mask 1563 drivers/usb/host/xhci-hub.c if ((temp & mask) != 0 || mask 204 drivers/usb/host/xhci-rcar.c u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK; mask 208 drivers/usb/host/xhci-rcar.c if ((val & mask) == mask) mask 465 drivers/usb/host/xhci-tegra.c unsigned long mask; mask 528 drivers/usb/host/xhci-tegra.c mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, mask 531 drivers/usb/host/xhci-tegra.c for_each_set_bit(port, &mask, 32) { mask 556 drivers/usb/host/xhci-tegra.c mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, mask 559 drivers/usb/host/xhci-tegra.c for_each_set_bit(port, &mask, soc->ports.usb3.count) { mask 69 drivers/usb/host/xhci.c int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) mask 75 drivers/usb/host/xhci.c (result & mask) == done || mask 91 drivers/usb/host/xhci.c u32 mask; mask 93 drivers/usb/host/xhci.c mask = ~(XHCI_IRQS); mask 96 drivers/usb/host/xhci.c mask &= ~CMD_RUN; mask 99 drivers/usb/host/xhci.c cmd &= mask; mask 2055 drivers/usb/host/xhci.h int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); mask 380 drivers/usb/isp1760/isp1760-hcd.c u32 mask, u32 done, int usec) mask 388 drivers/usb/isp1760/isp1760-hcd.c result &= mask; mask 1713 drivers/usb/isp1760/isp1760-hcd.c u32 mask; mask 1723 drivers/usb/isp1760/isp1760-hcd.c mask = PORT_CSC; mask 1743 drivers/usb/isp1760/isp1760-hcd.c if ((temp & mask) != 0 mask 2205 drivers/usb/misc/ftdi-elan.c int mask = OHCI_INTR_INIT; mask 2345 drivers/usb/misc/ftdi-elan.c retval = ftdi_write_pcimem(ftdi, intrstatus, mask); mask 687 drivers/usb/misc/iowarrior.c __poll_t mask = 0; mask 699 drivers/usb/misc/iowarrior.c mask |= EPOLLIN | EPOLLRDNORM; mask 702 drivers/usb/misc/iowarrior.c mask |= EPOLLOUT | EPOLLWRNORM; mask 703 drivers/usb/misc/iowarrior.c return mask; mask 416 drivers/usb/misc/ldusb.c __poll_t mask = 0; mask 427 drivers/usb/misc/ldusb.c mask |= EPOLLIN | EPOLLRDNORM; mask 429 drivers/usb/misc/ldusb.c mask |= EPOLLOUT | EPOLLWRNORM; mask 431 drivers/usb/misc/ldusb.c return mask; mask 501 drivers/usb/misc/legousbtower.c __poll_t mask = 0; mask 513 drivers/usb/misc/legousbtower.c mask |= EPOLLIN | EPOLLRDNORM; mask 516 drivers/usb/misc/legousbtower.c mask |= EPOLLOUT | EPOLLWRNORM; mask 519 drivers/usb/misc/legousbtower.c return mask; mask 1248 drivers/usb/misc/sisusbvga/sisusb.c u32 port, u8 idx, u8 data, u8 mask) mask 1255 drivers/usb/misc/sisusbvga/sisusb.c tmp &= ~(mask); mask 1256 drivers/usb/misc/sisusbvga/sisusb.c tmp |= (data & mask); mask 364 drivers/usb/misc/uss720.c static unsigned char parport_uss720_frob_control(struct parport *pp, unsigned char mask, unsigned char val) mask 369 drivers/usb/misc/uss720.c mask &= 0x0f; mask 371 drivers/usb/misc/uss720.c d = (priv->reg[1] & (~mask)) ^ val; mask 1205 drivers/usb/mon/mon_bin.c __poll_t mask = 0; mask 1213 drivers/usb/mon/mon_bin.c mask |= EPOLLIN | EPOLLRDNORM; /* readable */ mask 1215 drivers/usb/mon/mon_bin.c return mask; mask 87 drivers/usb/musb/da8xx.c u32 mask; mask 90 drivers/usb/musb/da8xx.c mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) | mask 93 drivers/usb/musb/da8xx.c musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); mask 2702 drivers/usb/musb/musb_core.c u8 mask; mask 2717 drivers/usb/musb/musb_core.c mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; mask 2718 drivers/usb/musb/musb_core.c if ((devctl & mask) != (musb->context.devctl & mask)) mask 281 drivers/usb/musb/ux500_dma.c dma_cap_mask_t mask; mask 290 drivers/usb/musb/ux500_dma.c dma_cap_zero(mask); mask 291 drivers/usb/musb/ux500_dma.c dma_cap_set(DMA_SLAVE, mask); mask 317 drivers/usb/musb/ux500_dma.c dma_request_channel(mask, mask 376 drivers/usb/phy/phy-tegra-usb.c static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) mask 380 drivers/usb/phy/phy-tegra-usb.c return readl_poll_timeout(reg, tmp, (tmp & mask) == result, mask 21 drivers/usb/phy/phy-ulpi-viewport.c static int ulpi_viewport_wait(void __iomem *view, u32 mask) mask 26 drivers/usb/phy/phy-ulpi-viewport.c if (!(readl(view) & mask)) mask 72 drivers/usb/renesas_usbhs/common.c void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data) mask 76 drivers/usb/renesas_usbhs/common.c val &= ~mask; mask 77 drivers/usb/renesas_usbhs/common.c val |= data & mask; mask 102 drivers/usb/renesas_usbhs/common.c u16 mask = DCFM | DRPD | DPRPU | HSE | USBE; mask 111 drivers/usb/renesas_usbhs/common.c usbhs_bset(priv, SYSCFG, mask, enable ? val : 0); mask 116 drivers/usb/renesas_usbhs/common.c u16 mask = DCFM | DRPD | DPRPU | HSE | USBE; mask 121 drivers/usb/renesas_usbhs/common.c mask |= CNEN; mask 133 drivers/usb/renesas_usbhs/common.c usbhs_bset(priv, SYSCFG, mask, enable ? val : 0); mask 292 drivers/usb/renesas_usbhs/common.h void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); mask 313 drivers/usb/renesas_usbhs/fifo.c u16 mask = ((1 << 5) | 0xF); /* mask of ISEL | CURPIPE */ mask 332 drivers/usb/renesas_usbhs/fifo.c if (base == (mask & usbhs_read(priv, fifo->sel))) { mask 1251 drivers/usb/renesas_usbhs/fifo.c dma_cap_mask_t mask; mask 1253 drivers/usb/renesas_usbhs/fifo.c dma_cap_zero(mask); mask 1254 drivers/usb/renesas_usbhs/fifo.c dma_cap_set(DMA_SLAVE, mask); mask 1255 drivers/usb/renesas_usbhs/fifo.c fifo->tx_chan = dma_request_channel(mask, usbhsf_dma_filter, mask 1258 drivers/usb/renesas_usbhs/fifo.c dma_cap_zero(mask); mask 1259 drivers/usb/renesas_usbhs/fifo.c dma_cap_set(DMA_SLAVE, mask); mask 1260 drivers/usb/renesas_usbhs/fifo.c fifo->rx_chan = dma_request_channel(mask, usbhsf_dma_filter, mask 50 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipectrl_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 56 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, DCPCTR, mask, val); mask 58 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, PIPEnCTR + offset, mask, val); mask 77 drivers/usb/renesas_usbhs/pipe.c u16 mask, u16 val) mask 82 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, dcp_reg, mask, val); mask 84 drivers/usb/renesas_usbhs/pipe.c usbhs_bset(priv, pipe_reg, mask, val); mask 101 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_cfg_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 103 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, DCPCFG, PIPECFG, mask, val); mask 114 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_trn_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 147 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); mask 150 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_tre_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 184 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, reg, mask, val); mask 190 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_buf_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 195 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, 0, PIPEBUF, mask, val); mask 201 drivers/usb/renesas_usbhs/pipe.c static void usbhsp_pipe_maxp_set(struct usbhs_pipe *pipe, u16 mask, u16 val) mask 203 drivers/usb/renesas_usbhs/pipe.c __usbhsp_pipe_xxx_set(pipe, DCPMAXP, PIPEMAXP, mask, val); mask 235 drivers/usb/renesas_usbhs/pipe.c u16 mask = usbhs_mod_is_host(priv) ? (CSSTS | PID_MASK) : PID_MASK; mask 259 drivers/usb/renesas_usbhs/pipe.c if (!(usbhsp_pipectrl_get(pipe) & mask)) mask 570 drivers/usb/renesas_usbhs/pipe.c u16 mask = (SQCLR | SQSET); mask 590 drivers/usb/renesas_usbhs/pipe.c usbhsp_pipectrl_set(pipe, mask, val); mask 505 drivers/usb/serial/cp210x.c u8 mask; mask 1401 drivers/usb/serial/cp210x.c buf.mask = BIT(gpio); mask 1413 drivers/usb/serial/cp210x.c u16 wIndex = buf.state << 8 | buf.mask; mask 159 drivers/usb/serial/f81232.c u8 mask, u8 val) mask 168 drivers/usb/serial/f81232.c tmp = (tmp & ~mask) | (val & mask); mask 299 drivers/usb/serial/f81534.c u8 mask, u8 data) mask 308 drivers/usb/serial/f81534.c tmp &= ~mask; mask 309 drivers/usb/serial/f81534.c tmp |= (mask & data); mask 1923 drivers/usb/serial/ftdi_sio.c static int ftdi_gpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, mask 1933 drivers/usb/serial/ftdi_sio.c *bits = result & *mask; mask 1938 drivers/usb/serial/ftdi_sio.c static void ftdi_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, mask 1946 drivers/usb/serial/ftdi_sio.c priv->gpio_value &= ~(*mask); mask 1947 drivers/usb/serial/ftdi_sio.c priv->gpio_value |= *bits & *mask; mask 2454 drivers/usb/serial/io_edgeport.c __u8 mask = 0xff; mask 2472 drivers/usb/serial/io_edgeport.c lData = LCR_BITS_5; mask = 0x1f; mask 2476 drivers/usb/serial/io_edgeport.c lData = LCR_BITS_6; mask = 0x3f; mask 2480 drivers/usb/serial/io_edgeport.c lData = LCR_BITS_7; mask = 0x7f; mask 2574 drivers/usb/serial/io_edgeport.c edge_port->validDataMask = mask; mask 303 drivers/usb/serial/io_ti.c static int purge_port(struct usb_serial_port *port, __u16 mask) mask 307 drivers/usb/serial/io_ti.c dev_dbg(&port->dev, "%s - port %d, mask %x\n", __func__, port_number, mask); mask 312 drivers/usb/serial/io_ti.c mask, mask 537 drivers/usb/serial/mos7720.c unsigned char mask, mask 543 drivers/usb/serial/mos7720.c mask &= 0x0f; mask 547 drivers/usb/serial/mos7720.c mos_parport->shadowDCR = (mos_parport->shadowDCR & (~mask)) ^ val; mask 232 drivers/usb/serial/pl2303.c static int pl2303_update_reg(struct usb_serial *serial, u8 reg, u8 mask, u8 val) mask 245 drivers/usb/serial/pl2303.c *buf &= ~mask; mask 246 drivers/usb/serial/pl2303.c *buf |= val & mask; mask 346 drivers/usb/serial/ti_usb_3410_5052.c unsigned long addr, u8 mask, u8 byte); mask 1545 drivers/usb/serial/ti_usb_3410_5052.c u8 mask, u8 byte) mask 1552 drivers/usb/serial/ti_usb_3410_5052.c addr, mask, byte); mask 1564 drivers/usb/serial/ti_usb_3410_5052.c data->bData[0] = mask; mask 481 drivers/usb/storage/usb.c unsigned int mask = (US_FL_SANE_SENSE | US_FL_BAD_SENSE | mask 580 drivers/usb/storage/usb.c *fflags = (*fflags & ~mask) | f; mask 303 drivers/usb/typec/tcpm/fusb302.c u8 mask, u8 value) mask 311 drivers/usb/typec/tcpm/fusb302.c data &= ~mask; mask 454 drivers/vfio/pci/vfio_pci_config.c u64 mask; mask 464 drivers/vfio/pci/vfio_pci_config.c mask = ~(pci_resource_len(pdev, i) - 1); mask 466 drivers/vfio/pci/vfio_pci_config.c *bar &= cpu_to_le32((u32)mask); mask 471 drivers/vfio/pci/vfio_pci_config.c *bar &= cpu_to_le32((u32)(mask >> 32)); mask 484 drivers/vfio/pci/vfio_pci_config.c mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); mask 485 drivers/vfio/pci/vfio_pci_config.c mask |= PCI_ROM_ADDRESS_ENABLE; mask 486 drivers/vfio/pci/vfio_pci_config.c *bar &= cpu_to_le32((u32)mask); mask 489 drivers/vfio/pci/vfio_pci_config.c mask = ~(0x20000 - 1); mask 490 drivers/vfio/pci/vfio_pci_config.c mask |= PCI_ROM_ADDRESS_ENABLE; mask 491 drivers/vfio/pci/vfio_pci_config.c *bar &= cpu_to_le32((u32)mask); mask 588 drivers/vfio/pci/vfio_pci_config.c u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; mask 590 drivers/vfio/pci/vfio_pci_config.c *virt_cmd &= cpu_to_le16(~mask); mask 591 drivers/vfio/pci/vfio_pci_config.c *virt_cmd |= cpu_to_le16(new_cmd & mask); mask 931 drivers/vfio/pci/vfio_pci_config.c u32 mask; mask 944 drivers/vfio/pci/vfio_pci_config.c mask = PCI_ERR_UNC_UND | /* Undefined */ mask 961 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); mask 962 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); mask 963 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); mask 965 drivers/vfio/pci/vfio_pci_config.c mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ mask 973 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); mask 974 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); mask 976 drivers/vfio/pci/vfio_pci_config.c mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ mask 978 drivers/vfio/pci/vfio_pci_config.c p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); mask 229 drivers/vfio/pci/vfio_pci_intrs.c vfio_virqfd_disable(&vdev->ctx[0].mask); mask 382 drivers/vfio/pci/vfio_pci_intrs.c vfio_virqfd_disable(&vdev->ctx[i].mask); mask 441 drivers/vfio/pci/vfio_pci_intrs.c uint8_t mask = *(uint8_t *)data; mask 442 drivers/vfio/pci/vfio_pci_intrs.c if (mask) mask 45 drivers/vfio/pci/vfio_pci_private.h struct virqfd *mask; mask 59 drivers/vfio/platform/vfio_platform_irq.c &vdev->irqs[index].mask, fd); mask 61 drivers/vfio/platform/vfio_platform_irq.c vfio_virqfd_disable(&vdev->irqs[index].mask); mask 69 drivers/vfio/platform/vfio_platform_irq.c uint8_t mask = *(uint8_t *)data; mask 71 drivers/vfio/platform/vfio_platform_irq.c if (mask) mask 31 drivers/vfio/platform/vfio_platform_private.h struct virqfd *mask; mask 874 drivers/vfio/vfio_iommu_type1.c uint64_t mask; mask 879 drivers/vfio/vfio_iommu_type1.c mask = ((uint64_t)1 << __ffs(vfio_pgsize_bitmap(iommu))) - 1; mask 881 drivers/vfio/vfio_iommu_type1.c if (unmap->iova & mask) mask 883 drivers/vfio/vfio_iommu_type1.c if (!unmap->size || unmap->size & mask) mask 889 drivers/vfio/vfio_iommu_type1.c WARN_ON(mask & PAGE_MASK); mask 1078 drivers/vfio/vfio_iommu_type1.c uint64_t mask; mask 1085 drivers/vfio/vfio_iommu_type1.c mask = ((uint64_t)1 << __ffs(vfio_pgsize_bitmap(iommu))) - 1; mask 1087 drivers/vfio/vfio_iommu_type1.c WARN_ON(mask & PAGE_MASK); mask 1095 drivers/vfio/vfio_iommu_type1.c if (!prot || !size || (size | iova | vaddr) & mask) mask 2287 drivers/vfio/vfio_iommu_type1.c uint32_t mask = VFIO_DMA_MAP_FLAG_READ | mask 2295 drivers/vfio/vfio_iommu_type1.c if (map.argsz < minsz || map.flags & ~mask) mask 86 drivers/vfio/vfio_spapr_eeh.c minsz = offsetofend(struct vfio_eeh_pe_op, err.mask); mask 93 drivers/vfio/vfio_spapr_eeh.c op.err.addr, op.err.mask); mask 173 drivers/vhost/vhost.c if (!(key_to_poll(key) & poll->mask)) mask 189 drivers/vhost/vhost.c __poll_t mask, struct vhost_dev *dev) mask 193 drivers/vhost/vhost.c poll->mask = mask; mask 205 drivers/vhost/vhost.c __poll_t mask; mask 210 drivers/vhost/vhost.c mask = vfs_poll(file, &poll->table); mask 211 drivers/vhost/vhost.c if (mask) mask 212 drivers/vhost/vhost.c vhost_poll_wakeup(&poll->wait, 0, 0, poll_to_key(mask)); mask 213 drivers/vhost/vhost.c if (mask & EPOLLERR) { mask 1190 drivers/vhost/vhost.c __poll_t mask = 0; mask 1195 drivers/vhost/vhost.c mask |= EPOLLIN | EPOLLRDNORM; mask 1197 drivers/vhost/vhost.c return mask; mask 33 drivers/vhost/vhost.h __poll_t mask; mask 42 drivers/vhost/vhost.h __poll_t mask, struct vhost_dev *dev); mask 94 drivers/video/backlight/arcxcnn_bl.c static int arcxcnn_update_field(struct arcxcnn *lp, u8 reg, u8 mask, u8 data) mask 106 drivers/video/backlight/arcxcnn_bl.c tmp &= ~mask; mask 107 drivers/video/backlight/arcxcnn_bl.c tmp |= data & mask; mask 93 drivers/video/backlight/lm3533_bl.c u8 mask; mask 101 drivers/video/backlight/lm3533_bl.c mask = 1 << (2 * ctrlbank); mask 102 drivers/video/backlight/lm3533_bl.c enable = val & mask; mask 115 drivers/video/backlight/lm3533_bl.c u8 mask; mask 121 drivers/video/backlight/lm3533_bl.c mask = 1 << (2 * ctrlbank); mask 124 drivers/video/backlight/lm3533_bl.c val = mask; mask 129 drivers/video/backlight/lm3533_bl.c mask); mask 141 drivers/video/backlight/lm3533_bl.c u8 mask; mask 149 drivers/video/backlight/lm3533_bl.c mask = 1 << (2 * lm3533_bl_get_ctrlbank_id(bl) + 1); mask 151 drivers/video/backlight/lm3533_bl.c if (val & mask) mask 165 drivers/video/backlight/lm3533_bl.c u8 mask; mask 172 drivers/video/backlight/lm3533_bl.c mask = 1 << (2 * lm3533_bl_get_ctrlbank_id(bl) + 1); mask 175 drivers/video/backlight/lm3533_bl.c val = mask; mask 180 drivers/video/backlight/lm3533_bl.c mask); mask 74 drivers/video/backlight/lm3630a_bl.c unsigned int reg, unsigned int mask, mask 77 drivers/video/backlight/lm3630a_bl.c return regmap_update_bits(pchip->regmap, reg, mask, data); mask 82 drivers/video/backlight/lp855x_bl.c static int lp855x_update_bit(struct lp855x *lp, u8 reg, u8 mask, u8 data) mask 94 drivers/video/backlight/lp855x_bl.c tmp &= ~mask; mask 95 drivers/video/backlight/lp855x_bl.c tmp |= data & mask; mask 338 drivers/video/fbdev/amba-clcd.c unsigned int mask = (1 << bf->length) - 1; mask 340 drivers/video/fbdev/amba-clcd.c return (val >> (16 - bf->length) & mask) << bf->offset; mask 361 drivers/video/fbdev/amba-clcd.c u32 val, mask, newval; mask 376 drivers/video/fbdev/amba-clcd.c mask = 0x0000ffff; mask 378 drivers/video/fbdev/amba-clcd.c mask = 0xffff0000; mask 381 drivers/video/fbdev/amba-clcd.c val = readl(fb->regs + hw_reg) & mask; mask 955 drivers/video/fbdev/amba-clcd.c .mask = 0x000ffffe, mask 1809 drivers/video/fbdev/amifb.c u_short color, mask; mask 1812 drivers/video/fbdev/amifb.c mask = 0x3333; mask 1815 drivers/video/fbdev/amifb.c custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color; mask 1816 drivers/video/fbdev/amifb.c mask <<= 2; color >>= 2; mask 1818 drivers/video/fbdev/amifb.c custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color; mask 2497 drivers/video/fbdev/amifb.c u_short color, mask; mask 2500 drivers/video/fbdev/amifb.c mask = 0x3333; mask 2504 drivers/video/fbdev/amifb.c custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color; mask 2505 drivers/video/fbdev/amifb.c mask <<= 2; color >>= 2; mask 2508 drivers/video/fbdev/amifb.c custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color; mask 2581 drivers/video/fbdev/amifb.c unsigned long mask) mask 2583 drivers/video/fbdev/amifb.c return ((a ^ b) & mask) ^ b; mask 2588 drivers/video/fbdev/amifb.c unsigned long mask) mask 2590 drivers/video/fbdev/amifb.c return (a & mask) ^ b; mask 106 drivers/video/fbdev/atafb_iplan2p2.c u32 pval[4], v, v1, mask; mask 112 drivers/video/fbdev/atafb_iplan2p2.c mask = 0xff00ff00; mask 127 drivers/video/fbdev/atafb_iplan2p2.c pval[0] = (*src32++ << 8) & mask; mask 129 drivers/video/fbdev/atafb_iplan2p2.c pval[0] = dst32[0] & mask; mask 134 drivers/video/fbdev/atafb_iplan2p2.c v1 = v & mask; mask 140 drivers/video/fbdev/atafb_iplan2p2.c dst32[0] = (dst32[0] & mask) | pval[0]; mask 148 drivers/video/fbdev/atafb_iplan2p2.c u32 pval[4], v, v1, mask; mask 154 drivers/video/fbdev/atafb_iplan2p2.c mask = 0xff00ff; mask 169 drivers/video/fbdev/atafb_iplan2p2.c pval[0] = dst32[-1] & mask; mask 171 drivers/video/fbdev/atafb_iplan2p2.c pval[0] = (*--src32 >> 8) & mask; mask 176 drivers/video/fbdev/atafb_iplan2p2.c v1 = v & mask; mask 182 drivers/video/fbdev/atafb_iplan2p2.c dst32[-1] = (dst32[-1] & mask) | pval[0]; mask 106 drivers/video/fbdev/atafb_iplan2p4.c u32 pval[4], v, v1, mask; mask 112 drivers/video/fbdev/atafb_iplan2p4.c mask = 0xff00ff00; mask 127 drivers/video/fbdev/atafb_iplan2p4.c pval[0] = (*src32++ << 8) & mask; mask 128 drivers/video/fbdev/atafb_iplan2p4.c pval[1] = (*src32++ << 8) & mask; mask 130 drivers/video/fbdev/atafb_iplan2p4.c pval[0] = dst32[0] & mask; mask 131 drivers/video/fbdev/atafb_iplan2p4.c pval[1] = dst32[1] & mask; mask 136 drivers/video/fbdev/atafb_iplan2p4.c v1 = v & mask; mask 140 drivers/video/fbdev/atafb_iplan2p4.c v1 = v & mask; mask 146 drivers/video/fbdev/atafb_iplan2p4.c dst32[0] = (dst32[0] & mask) | pval[0]; mask 147 drivers/video/fbdev/atafb_iplan2p4.c dst32[1] = (dst32[1] & mask) | pval[1]; mask 155 drivers/video/fbdev/atafb_iplan2p4.c u32 pval[4], v, v1, mask; mask 161 drivers/video/fbdev/atafb_iplan2p4.c mask = 0xff00ff; mask 176 drivers/video/fbdev/atafb_iplan2p4.c pval[0] = dst32[-1] & mask; mask 177 drivers/video/fbdev/atafb_iplan2p4.c pval[1] = dst32[-2] & mask; mask 179 drivers/video/fbdev/atafb_iplan2p4.c pval[0] = (*--src32 >> 8) & mask; mask 180 drivers/video/fbdev/atafb_iplan2p4.c pval[1] = (*--src32 >> 8) & mask; mask 185 drivers/video/fbdev/atafb_iplan2p4.c v1 = v & mask; mask 189 drivers/video/fbdev/atafb_iplan2p4.c v1 = v & mask; mask 195 drivers/video/fbdev/atafb_iplan2p4.c dst32[-1] = (dst32[-1] & mask) | pval[0]; mask 196 drivers/video/fbdev/atafb_iplan2p4.c dst32[-2] = (dst32[-2] & mask) | pval[1]; mask 113 drivers/video/fbdev/atafb_iplan2p8.c u32 pval[4], v, v1, mask; mask 119 drivers/video/fbdev/atafb_iplan2p8.c mask = 0xff00ff00; mask 134 drivers/video/fbdev/atafb_iplan2p8.c pval[0] = (*src32++ << 8) & mask; mask 135 drivers/video/fbdev/atafb_iplan2p8.c pval[1] = (*src32++ << 8) & mask; mask 136 drivers/video/fbdev/atafb_iplan2p8.c pval[2] = (*src32++ << 8) & mask; mask 137 drivers/video/fbdev/atafb_iplan2p8.c pval[3] = (*src32++ << 8) & mask; mask 139 drivers/video/fbdev/atafb_iplan2p8.c pval[0] = dst32[0] & mask; mask 140 drivers/video/fbdev/atafb_iplan2p8.c pval[1] = dst32[1] & mask; mask 141 drivers/video/fbdev/atafb_iplan2p8.c pval[2] = dst32[2] & mask; mask 142 drivers/video/fbdev/atafb_iplan2p8.c pval[3] = dst32[3] & mask; mask 147 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 151 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 155 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 159 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 165 drivers/video/fbdev/atafb_iplan2p8.c dst32[0] = (dst32[0] & mask) | pval[0]; mask 166 drivers/video/fbdev/atafb_iplan2p8.c dst32[1] = (dst32[1] & mask) | pval[1]; mask 167 drivers/video/fbdev/atafb_iplan2p8.c dst32[2] = (dst32[2] & mask) | pval[2]; mask 168 drivers/video/fbdev/atafb_iplan2p8.c dst32[3] = (dst32[3] & mask) | pval[3]; mask 176 drivers/video/fbdev/atafb_iplan2p8.c u32 pval[4], v, v1, mask; mask 182 drivers/video/fbdev/atafb_iplan2p8.c mask = 0xff00ff; mask 197 drivers/video/fbdev/atafb_iplan2p8.c pval[0] = dst32[-1] & mask; mask 198 drivers/video/fbdev/atafb_iplan2p8.c pval[1] = dst32[-2] & mask; mask 199 drivers/video/fbdev/atafb_iplan2p8.c pval[2] = dst32[-3] & mask; mask 200 drivers/video/fbdev/atafb_iplan2p8.c pval[3] = dst32[-4] & mask; mask 202 drivers/video/fbdev/atafb_iplan2p8.c pval[0] = (*--src32 >> 8) & mask; mask 203 drivers/video/fbdev/atafb_iplan2p8.c pval[1] = (*--src32 >> 8) & mask; mask 204 drivers/video/fbdev/atafb_iplan2p8.c pval[2] = (*--src32 >> 8) & mask; mask 205 drivers/video/fbdev/atafb_iplan2p8.c pval[3] = (*--src32 >> 8) & mask; mask 210 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 214 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 218 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 222 drivers/video/fbdev/atafb_iplan2p8.c v1 = v & mask; mask 228 drivers/video/fbdev/atafb_iplan2p8.c dst32[-1] = (dst32[-1] & mask) | pval[0]; mask 229 drivers/video/fbdev/atafb_iplan2p8.c dst32[-2] = (dst32[-2] & mask) | pval[1]; mask 230 drivers/video/fbdev/atafb_iplan2p8.c dst32[-3] = (dst32[-3] & mask) | pval[2]; mask 231 drivers/video/fbdev/atafb_iplan2p8.c dst32[-4] = (dst32[-4] & mask) | pval[3]; mask 301 drivers/video/fbdev/atafb_utils.h static inline void fill8_2col(u8 *dst, u8 fg, u8 bg, u32 mask) mask 307 drivers/video/fbdev/atafb_utils.h mask |= mask << 8; mask 309 drivers/video/fbdev/atafb_utils.h mask |= mask << 16; mask 311 drivers/video/fbdev/atafb_utils.h tmp = (mask & fgm[0]) ^ bgm[0]; mask 319 drivers/video/fbdev/atafb_utils.h tmp = (mask & fgm[1]) ^ bgm[1]; mask 375 drivers/video/fbdev/atafb_utils.h static inline void memmove32_col(void *dst, void *src, u32 mask, u32 h, u32 bytes) mask 382 drivers/video/fbdev/atafb_utils.h v = (*s++ & mask) | (*d & ~mask); mask 385 drivers/video/fbdev/atafb_utils.h v = (*s++ & mask) | (*d & ~mask); mask 389 drivers/video/fbdev/atafb_utils.h v = (*s++ & mask) | (*d & ~mask); mask 391 drivers/video/fbdev/atafb_utils.h v = (*s++ & mask) | (*d & ~mask); mask 146 drivers/video/fbdev/aty/mach64_cursor.c u8 *msk = (u8 *)cursor->mask; mask 210 drivers/video/fbdev/aty/mach64_gx.c u32 gModeReg, devSetupRegA, temp, mask; mask 256 drivers/video/fbdev/aty/mach64_gx.c mask = 0x04; mask 258 drivers/video/fbdev/aty/mach64_gx.c mask = 0x08; mask 260 drivers/video/fbdev/aty/mach64_gx.c mask = 0x0C; mask 268 drivers/video/fbdev/aty/mach64_gx.c aty_st_8(DAC_REGS, (devSetupRegA | mask) | (temp & A860_DELAY_L), mask 315 drivers/video/fbdev/aty/radeon_base.c void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) mask 322 drivers/video/fbdev/aty/radeon_base.c tmp &= (mask); mask 348 drivers/video/fbdev/aty/radeon_base.c u32 val, u32 mask) mask 353 drivers/video/fbdev/aty/radeon_base.c tmp &= (mask); mask 383 drivers/video/fbdev/aty/radeonfb.h void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask); mask 385 drivers/video/fbdev/aty/radeonfb.h #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) mask 421 drivers/video/fbdev/aty/radeonfb.h u32 val, u32 mask); mask 425 drivers/video/fbdev/aty/radeonfb.h #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) mask 90 drivers/video/fbdev/au1200fb.c unsigned int mask; mask 1266 drivers/video/fbdev/au1200fb.c lcd->colorkeymsk = pdata->mask; mask 1279 drivers/video/fbdev/au1200fb.c pdata->mask = lcd->colorkeymsk; mask 203 drivers/video/fbdev/bt431.h const char *data, const char *mask, mask 217 drivers/video/fbdev/bt431.h val = mask[i]; mask 21 drivers/video/fbdev/c2p_core.h unsigned int shift, u32 mask) mask 23 drivers/video/fbdev/c2p_core.h u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; mask 62 drivers/video/fbdev/c2p_core.h u32 mask = get_mask(n); mask 67 drivers/video/fbdev/c2p_core.h _transp(d, 0, 1, n, mask); mask 69 drivers/video/fbdev/c2p_core.h _transp(d, 2, 3, n, mask); mask 71 drivers/video/fbdev/c2p_core.h _transp(d, 4, 5, n, mask); mask 73 drivers/video/fbdev/c2p_core.h _transp(d, 6, 7, n, mask); mask 78 drivers/video/fbdev/c2p_core.h _transp(d, 0, 2, n, mask); mask 79 drivers/video/fbdev/c2p_core.h _transp(d, 1, 3, n, mask); mask 81 drivers/video/fbdev/c2p_core.h _transp(d, 4, 6, n, mask); mask 82 drivers/video/fbdev/c2p_core.h _transp(d, 5, 7, n, mask); mask 87 drivers/video/fbdev/c2p_core.h _transp(d, 0, 4, n, mask); mask 88 drivers/video/fbdev/c2p_core.h _transp(d, 1, 5, n, mask); mask 89 drivers/video/fbdev/c2p_core.h _transp(d, 2, 6, n, mask); mask 90 drivers/video/fbdev/c2p_core.h _transp(d, 3, 7, n, mask); mask 104 drivers/video/fbdev/c2p_core.h u32 mask = get_mask(n); mask 109 drivers/video/fbdev/c2p_core.h _transp(d, 0, 1, n, mask); mask 111 drivers/video/fbdev/c2p_core.h _transp(d, 2, 3, n, mask); mask 116 drivers/video/fbdev/c2p_core.h _transp(d, 0, 2, n, mask); mask 117 drivers/video/fbdev/c2p_core.h _transp(d, 1, 3, n, mask); mask 131 drivers/video/fbdev/c2p_core.h u32 mask = get_mask(n); mask 136 drivers/video/fbdev/c2p_core.h _transp(d, 2, 0, n, mask); mask 137 drivers/video/fbdev/c2p_core.h _transp(d, 3, 1, n, mask); mask 150 drivers/video/fbdev/c2p_core.h static inline u32 comp(u32 a, u32 b, u32 mask) mask 152 drivers/video/fbdev/c2p_core.h return ((a ^ b) & mask) ^ b; mask 61 drivers/video/fbdev/c2p_iplan2.c static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask) mask 67 drivers/video/fbdev/c2p_iplan2.c get_unaligned_be32(dst), mask), mask 62 drivers/video/fbdev/c2p_planar.c u32 d[8], u32 mask) mask 68 drivers/video/fbdev/c2p_planar.c get_unaligned_be32(dst), mask), mask 48 drivers/video/fbdev/clps711x-fb.c u32 level, mask, shift; mask 54 drivers/video/fbdev/clps711x-fb.c mask = 0xf << shift; mask 56 drivers/video/fbdev/clps711x-fb.c level = (((red * 77 + green * 151 + blue * 28) >> 20) << shift) & mask; mask 62 drivers/video/fbdev/clps711x-fb.c writel((readl(cfb->base + regno) & ~mask) | level, cfb->base + regno); mask 313 drivers/video/fbdev/core/bitblit.c ops->cursor_state.mask == NULL || mask 315 drivers/video/fbdev/core/bitblit.c char *mask = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC); mask 319 drivers/video/fbdev/core/bitblit.c if (!mask) mask 322 drivers/video/fbdev/core/bitblit.c kfree(ops->cursor_state.mask); mask 323 drivers/video/fbdev/core/bitblit.c ops->cursor_state.mask = mask; mask 351 drivers/video/fbdev/core/bitblit.c mask[i++] = ~msk; mask 354 drivers/video/fbdev/core/bitblit.c mask[i++] = msk; mask 377 drivers/video/fbdev/core/bitblit.c cursor.mask = ops->cursor_state.mask; mask 15 drivers/video/fbdev/core/fb_draw.h comp(unsigned long a, unsigned long b, unsigned long mask) mask 17 drivers/video/fbdev/core/fb_draw.h return ((a ^ b) & mask) ^ b; mask 104 drivers/video/fbdev/core/fb_draw.h u32 mask; mask 107 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_HIGH(p, ~(u32)0, index); mask 109 drivers/video/fbdev/core/fb_draw.h mask = 0xff << FB_LEFT_POS(p, 8); mask 110 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; mask 111 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); mask 116 drivers/video/fbdev/core/fb_draw.h mask |= FB_SHIFT_HIGH(p, ~(u32)0, mask 119 drivers/video/fbdev/core/fb_draw.h return mask; mask 126 drivers/video/fbdev/core/fb_draw.h unsigned long mask; mask 129 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_HIGH(p, ~0UL, index); mask 131 drivers/video/fbdev/core/fb_draw.h mask = 0xff << FB_LEFT_POS(p, 8); mask 132 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; mask 133 drivers/video/fbdev/core/fb_draw.h mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); mask 138 drivers/video/fbdev/core/fb_draw.h mask |= FB_SHIFT_HIGH(p, ~0UL, mask 141 drivers/video/fbdev/core/fb_draw.h return mask; mask 791 drivers/video/fbdev/core/fbcon.c kfree(ops->cursor_state.mask); mask 3673 drivers/video/fbdev/core/fbcon.c kfree(ops->cursor_state.mask); mask 305 drivers/video/fbdev/core/fbcon_ccw.c ops->cursor_state.mask == NULL || mask 307 drivers/video/fbdev/core/fbcon_ccw.c char *tmp, *mask = kmalloc_array(w, vc->vc_font.width, mask 312 drivers/video/fbdev/core/fbcon_ccw.c if (!mask) mask 318 drivers/video/fbdev/core/fbcon_ccw.c kfree(mask); mask 322 drivers/video/fbdev/core/fbcon_ccw.c kfree(ops->cursor_state.mask); mask 323 drivers/video/fbdev/core/fbcon_ccw.c ops->cursor_state.mask = mask; mask 356 drivers/video/fbdev/core/fbcon_ccw.c memset(mask, 0, w * vc->vc_font.width); mask 357 drivers/video/fbdev/core/fbcon_ccw.c rotate_ccw(tmp, mask, vc->vc_font.width, vc->vc_font.height); mask 381 drivers/video/fbdev/core/fbcon_ccw.c cursor.mask = ops->cursor_state.mask; mask 288 drivers/video/fbdev/core/fbcon_cw.c ops->cursor_state.mask == NULL || mask 290 drivers/video/fbdev/core/fbcon_cw.c char *tmp, *mask = kmalloc_array(w, vc->vc_font.width, mask 295 drivers/video/fbdev/core/fbcon_cw.c if (!mask) mask 301 drivers/video/fbdev/core/fbcon_cw.c kfree(mask); mask 305 drivers/video/fbdev/core/fbcon_cw.c kfree(ops->cursor_state.mask); mask 306 drivers/video/fbdev/core/fbcon_cw.c ops->cursor_state.mask = mask; mask 339 drivers/video/fbdev/core/fbcon_cw.c memset(mask, 0, w * vc->vc_font.width); mask 340 drivers/video/fbdev/core/fbcon_cw.c rotate_cw(tmp, mask, vc->vc_font.width, vc->vc_font.height); mask 364 drivers/video/fbdev/core/fbcon_cw.c cursor.mask = ops->cursor_state.mask; mask 336 drivers/video/fbdev/core/fbcon_ud.c ops->cursor_state.mask == NULL || mask 338 drivers/video/fbdev/core/fbcon_ud.c char *mask = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC); mask 342 drivers/video/fbdev/core/fbcon_ud.c if (!mask) mask 345 drivers/video/fbdev/core/fbcon_ud.c kfree(ops->cursor_state.mask); mask 346 drivers/video/fbdev/core/fbcon_ud.c ops->cursor_state.mask = mask; mask 376 drivers/video/fbdev/core/fbcon_ud.c mask[i++] = msk; mask 381 drivers/video/fbdev/core/fbcon_ud.c mask[i++] = ~msk; mask 404 drivers/video/fbdev/core/fbcon_ud.c cursor.mask = ops->cursor_state.mask; mask 122 drivers/video/fbdev/core/fbmem.c u8 mask = (u8) (0xfff << shift_high), tmp; mask 128 drivers/video/fbdev/core/fbmem.c tmp &= mask; mask 136 drivers/video/fbdev/core/fbmem.c tmp &= mask; mask 231 drivers/video/fbdev/core/fbmem.c static const unsigned char mask[] = { 0,0x80,0xc0,0xe0,0xf0,0xf8,0xfc,0xfe,0xff }; mask 242 drivers/video/fbdev/core/fbmem.c redmask = mask[info->var.red.length < 8 ? info->var.red.length : 8]; mask 243 drivers/video/fbdev/core/fbmem.c greenmask = mask[info->var.green.length < 8 ? info->var.green.length : 8]; mask 244 drivers/video/fbdev/core/fbmem.c bluemask = mask[info->var.blue.length < 8 ? info->var.blue.length : 8]; mask 61 drivers/video/fbdev/core/softcursor.c src[i] = image->data[i] ^ cursor->mask[i]; mask 66 drivers/video/fbdev/core/softcursor.c src[i] = image->data[i] & cursor->mask[i]; mask 263 drivers/video/fbdev/cyber2000fb.c u_int mask = (1 << bf->length) - 1; mask 265 drivers/video/fbdev/cyber2000fb.c return (val >> (16 - bf->length) & mask) << bf->offset; mask 1006 drivers/video/fbdev/fsl-diu-fb.c uint32_t mask = 1 << 31; mask 1010 drivers/video/fbdev/fsl-diu-fb.c cursor[w] = (line & mask) ? _fg : _bg; mask 1011 drivers/video/fbdev/fsl-diu-fb.c mask >>= 1; mask 1071 drivers/video/fbdev/fsl-diu-fb.c uint32_t *image, *source, *mask; mask 1091 drivers/video/fbdev/fsl-diu-fb.c mask = (uint32_t *)cursor->mask; mask 1095 drivers/video/fbdev/fsl-diu-fb.c image[i] = source[i] ^ mask[i]; mask 1098 drivers/video/fbdev/fsl-diu-fb.c image[i] = source[i] & mask[i]; mask 66 drivers/video/fbdev/goldfishfb.c unsigned int mask = (1 << bf->length) - 1; mask 68 drivers/video/fbdev/goldfishfb.c return (val >> (16 - bf->length) & mask) << bf->offset; mask 113 drivers/video/fbdev/i740fb.c u8 val, u8 mask) mask 115 drivers/video/fbdev/i740fb.c vga_mm_w_fast(par->regs, port, reg, (val & mask) mask 116 drivers/video/fbdev/i740fb.c | (i740inreg(par, port, reg) & ~mask)); mask 1524 drivers/video/fbdev/i810/i810_main.c data[i] = cursor->image.data[i] ^ cursor->mask[i]; mask 1529 drivers/video/fbdev/i810/i810_main.c data[i] = cursor->image.data[i] & cursor->mask[i]; mask 1219 drivers/video/fbdev/imsttfb.c u8 *msk = (u8 *) cursor->mask; mask 1228 drivers/video/fbdev/imsttfb.c mask[d_idx] = byte_rev[msk[s_idx]]; mask 1239 drivers/video/fbdev/imsttfb.c mask[d_idx] = byte_rev[msk[s_idx]]; mask 1621 drivers/video/fbdev/intelfb/intelfbdrv.c u8 *msk = (u8 *) cursor->mask; mask 51 drivers/video/fbdev/matrox/i2c-matroxfb.c static void matroxfb_set_gpio(struct matrox_fb_info* minfo, int mask, int val) { mask 56 drivers/video/fbdev/matrox/i2c-matroxfb.c v = (matroxfb_DAC_in(minfo, DAC_XGENIOCTRL) & mask) | val; mask 64 drivers/video/fbdev/matrox/i2c-matroxfb.c static inline void matroxfb_i2c_set(struct matrox_fb_info* minfo, int mask, int state) { mask 68 drivers/video/fbdev/matrox/i2c-matroxfb.c state = mask; mask 69 drivers/video/fbdev/matrox/i2c-matroxfb.c matroxfb_set_gpio(minfo, ~mask, state); mask 74 drivers/video/fbdev/matrox/i2c-matroxfb.c matroxfb_i2c_set(b->minfo, b->mask.data, state); mask 79 drivers/video/fbdev/matrox/i2c-matroxfb.c matroxfb_i2c_set(b->minfo, b->mask.clock, state); mask 84 drivers/video/fbdev/matrox/i2c-matroxfb.c return (matroxfb_read_gpio(b->minfo) & b->mask.data) ? 1 : 0; mask 89 drivers/video/fbdev/matrox/i2c-matroxfb.c return (matroxfb_read_gpio(b->minfo) & b->mask.clock) ? 1 : 0; mask 109 drivers/video/fbdev/matrox/i2c-matroxfb.c b->mask.data = data; mask 110 drivers/video/fbdev/matrox/i2c-matroxfb.c b->mask.clock = clock; mask 194 drivers/video/fbdev/matrox/matroxfb_crtc2.c unsigned int mask; mask 199 drivers/video/fbdev/matrox/matroxfb_crtc2.c case 16: mask = 0x1F; mask 201 drivers/video/fbdev/matrox/matroxfb_crtc2.c case 32: mask = 0x0F; mask 210 drivers/video/fbdev/matrox/matroxfb_crtc2.c var->xres_virtual = (var->xres_virtual + mask) & ~mask; mask 18 drivers/video/fbdev/matrox/matroxfb_maven.h } mask; mask 583 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c unsigned long reg_ist, mask; mask 591 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c mask = inreg(ctrl, GC_CTRL_INT_MASK); mask 595 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg_ist &= mask; mask 604 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c mask = inreg(host, GC_IMASK); mask 606 drivers/video/fbdev/mb862xx/mb862xxfbdrv.c reg_ist &= mask; mask 651 drivers/video/fbdev/mbx/mbxfb.c tmp &= ~reg.mask; mask 652 drivers/video/fbdev/mbx/mbxfb.c tmp |= reg.val & reg.mask; mask 160 drivers/video/fbdev/mmp/hw/mmp_ctrl.c u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK : mask 168 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp &= ~mask; mask 339 drivers/video/fbdev/mmp/hw/mmp_ctrl.c u32 dma_ctrl1, mask, tmp, path_config; mask 345 drivers/video/fbdev/mmp/hw/mmp_ctrl.c mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK; mask 347 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp &= ~mask; mask 378 drivers/video/fbdev/mmp/hw/mmp_ctrl.c mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1); mask 380 drivers/video/fbdev/mmp/hw/mmp_ctrl.c tmp |= mask; mask 1558 drivers/video/fbdev/mx3fb.c dma_cap_mask_t mask; mask 1592 drivers/video/fbdev/mx3fb.c dma_cap_zero(mask); mask 1593 drivers/video/fbdev/mx3fb.c dma_cap_set(DMA_SLAVE, mask); mask 1594 drivers/video/fbdev/mx3fb.c dma_cap_set(DMA_PRIVATE, mask); mask 1596 drivers/video/fbdev/mx3fb.c chan = dma_request_channel(mask, chan_filter, &rq); mask 356 drivers/video/fbdev/nvidia/nv_accel.c u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel)); mask 364 drivers/video/fbdev/nvidia/nv_accel.c fg = image->fg_color | mask; mask 365 drivers/video/fbdev/nvidia/nv_accel.c bg = image->bg_color | mask; mask 367 drivers/video/fbdev/nvidia/nv_accel.c fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask; mask 368 drivers/video/fbdev/nvidia/nv_accel.c bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask; mask 18 drivers/video/fbdev/nvidia/nv_type.h #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) mask 19 drivers/video/fbdev/nvidia/nv_type.h #define SetBF(mask,value) ((value) << (0?mask)) mask 20 drivers/video/fbdev/nvidia/nv_type.h #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) mask 566 drivers/video/fbdev/nvidia/nvidia.c u8 *msk = (u8 *) cursor->mask; mask 115 drivers/video/fbdev/offb.c u32 mask = (1 << info->var.transp.length) - 1; mask 116 drivers/video/fbdev/offb.c mask <<= info->var.transp.offset; mask 117 drivers/video/fbdev/offb.c value |= mask; mask 69 drivers/video/fbdev/omap/lcdc.c static inline void enable_irqs(int mask) mask 71 drivers/video/fbdev/omap/lcdc.c lcdc.irq_mask |= mask; mask 74 drivers/video/fbdev/omap/lcdc.c static inline void disable_irqs(int mask) mask 76 drivers/video/fbdev/omap/lcdc.c lcdc.irq_mask &= ~mask; mask 114 drivers/video/fbdev/omap/lcdc.c u32 mask; mask 117 drivers/video/fbdev/omap/lcdc.c mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK; mask 122 drivers/video/fbdev/omap/lcdc.c mask &= ~OMAP_LCDC_IRQ_DONE; mask 123 drivers/video/fbdev/omap/lcdc.c l &= ~mask; mask 839 drivers/video/fbdev/omap2/omapfb/dss/apply.c static void dss_apply_irq_handler(void *data, u32 mask); mask 844 drivers/video/fbdev/omap2/omapfb/dss/apply.c u32 mask; mask 847 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask = 0; mask 849 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask |= dispc_mgr_get_vsync_irq(i); mask 852 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask |= dispc_mgr_get_framedone_irq(i); mask 854 drivers/video/fbdev/omap2/omapfb/dss/apply.c r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask); mask 863 drivers/video/fbdev/omap2/omapfb/dss/apply.c u32 mask; mask 866 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask = 0; mask 868 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask |= dispc_mgr_get_vsync_irq(i); mask 871 drivers/video/fbdev/omap2/omapfb/dss/apply.c mask |= dispc_mgr_get_framedone_irq(i); mask 873 drivers/video/fbdev/omap2/omapfb/dss/apply.c r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask); mask 879 drivers/video/fbdev/omap2/omapfb/dss/apply.c static void dss_apply_irq_handler(void *data, u32 mask) mask 927 drivers/video/fbdev/omap2/omapfb/dss/apply.c if (mask & dispc_mgr_get_framedone_irq(i)) mask 36 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c u32 mask; mask 120 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c u32 mask; mask 124 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c mask = dispc_compat.irq_error_mask; mask 132 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c mask |= isr_data->mask; mask 135 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c dispc_write_irqenable(mask); mask 138 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) mask 154 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c isr_data->mask == mask) { mask 171 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c isr_data->mask = mask; mask 192 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) mask 204 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c isr_data->mask != mask) mask 211 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c isr_data->mask = 0; mask 299 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c if (isr_data->mask & irqstatus) { mask 301 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c handledirqs |= isr_data->mask; mask 451 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c static void dispc_mgr_disable_isr(void *data, u32 mask) mask 501 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c static void dispc_digit_out_enable_isr(void *data, u32 mask) mask 506 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD)) mask 626 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c static inline void dispc_irq_wait_handler(void *data, u32 mask) mask 3231 drivers/video/fbdev/omap2/omapfb/dss/dispc.c u32 mask, val; mask 3233 drivers/video/fbdev/omap2/omapfb/dss/dispc.c mask = (1 << 0) | (1 << 3) | (1 << 6); mask 3236 drivers/video/fbdev/omap2/omapfb/dss/dispc.c mask <<= 16 + shifts[channel]; mask 3240 drivers/video/fbdev/omap2/omapfb/dss/dispc.c mask, val); mask 3794 drivers/video/fbdev/omap2/omapfb/dss/dispc.c void dispc_clear_irqstatus(u32 mask) mask 3796 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_IRQSTATUS, mask); mask 3806 drivers/video/fbdev/omap2/omapfb/dss/dispc.c void dispc_write_irqenable(u32 mask) mask 3811 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_clear_irqstatus((mask ^ old_mask) & mask); mask 3813 drivers/video/fbdev/omap2/omapfb/dss/dispc.c dispc_write_reg(DISPC_IRQENABLE, mask); mask 203 drivers/video/fbdev/omap2/omapfb/dss/dsi.c typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); mask 236 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 mask; mask 486 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static void dsi_completion_handler(void *data, u32 mask) mask 757 drivers/video/fbdev/omap2/omapfb/dss/dsi.c if (isr_data->isr && isr_data->mask & irqstatus) mask 864 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 mask; mask 868 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask = default_mask; mask 876 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask |= isr_data->mask; mask 881 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); mask 882 drivers/video/fbdev/omap2/omapfb/dss/dsi.c dsi_write_reg(dsidev, enable_reg, mask); mask 893 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u32 mask = DSI_IRQ_ERROR_MASK; mask 895 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask |= DSI_IRQ_TE_TRIGGER; mask 898 drivers/video/fbdev/omap2/omapfb/dss/dsi.c ARRAY_SIZE(dsi->isr_tables.isr_table), mask, mask 942 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, mask 957 drivers/video/fbdev/omap2/omapfb/dss/dsi.c isr_data->mask == mask) { mask 971 drivers/video/fbdev/omap2/omapfb/dss/dsi.c isr_data->mask = mask; mask 976 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, mask 985 drivers/video/fbdev/omap2/omapfb/dss/dsi.c isr_data->mask != mask) mask 990 drivers/video/fbdev/omap2/omapfb/dss/dsi.c isr_data->mask = 0; mask 999 drivers/video/fbdev/omap2/omapfb/dss/dsi.c void *arg, u32 mask) mask 1007 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, mask 1019 drivers/video/fbdev/omap2/omapfb/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1027 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, mask 1039 drivers/video/fbdev/omap2/omapfb/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1047 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, mask 1060 drivers/video/fbdev/omap2/omapfb/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1068 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, mask 1081 drivers/video/fbdev/omap2/omapfb/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1089 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, mask 1101 drivers/video/fbdev/omap2/omapfb/dss/dsi.c omap_dsi_isr_t isr, void *arg, u32 mask) mask 1109 drivers/video/fbdev/omap2/omapfb/dss/dsi.c r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, mask 2042 drivers/video/fbdev/omap2/omapfb/dss/dsi.c unsigned mask = 0; mask 2047 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask |= 1 << i; mask 2050 drivers/video/fbdev/omap2/omapfb/dss/dsi.c return mask; mask 2274 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static void dsi_packet_sent_handler_vp(void *data, u32 mask) mask 2325 drivers/video/fbdev/omap2/omapfb/dss/dsi.c static void dsi_packet_sent_handler_l4(void *data, u32 mask) mask 3110 drivers/video/fbdev/omap2/omapfb/dss/dsi.c unsigned mask; mask 3155 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask = 0; mask 3160 drivers/video/fbdev/omap2/omapfb/dss/dsi.c mask |= 1 << i; mask 3164 drivers/video/fbdev/omap2/omapfb/dss/dsi.c REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); mask 416 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dispc_clear_irqstatus(u32 mask); mask 418 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dispc_write_irqenable(u32 mask); mask 282 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); mask 283 drivers/video/fbdev/omap2/omapfb/dss/hdmi.h void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); mask 57 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) mask 59 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); mask 62 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) mask 64 drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); mask 1318 drivers/video/fbdev/pm2fb.c u8 *mask = (u8 *)cursor->mask; mask 1329 drivers/video/fbdev/pm2fb.c u8 data = *bitmap ^ *mask; mask 1332 drivers/video/fbdev/pm2fb.c data = *mask & *bitmap; mask 1336 drivers/video/fbdev/pm2fb.c (cursor_bits_lookup[*mask >> 4] << 1)); mask 1340 drivers/video/fbdev/pm2fb.c (cursor_bits_lookup[*mask & 0xf] << 1)); mask 1342 drivers/video/fbdev/pm2fb.c mask++; mask 1425 drivers/video/fbdev/pm2fb.c u8 *mask = (u8 *)cursor->mask; mask 1437 drivers/video/fbdev/pm2fb.c u8 data = *bitmap ^ *mask; mask 1440 drivers/video/fbdev/pm2fb.c data = *mask & *bitmap; mask 1444 drivers/video/fbdev/pm2fb.c mask++; mask 1456 drivers/video/fbdev/pm2fb.c mask = (u8 *)cursor->mask; mask 1464 drivers/video/fbdev/pm2fb.c pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask); mask 1465 drivers/video/fbdev/pm2fb.c mask++; mask 680 drivers/video/fbdev/pm3fb.c u8 *mask = (u8 *)cursor->mask; mask 689 drivers/video/fbdev/pm3fb.c u8 data = *bitmap ^ *mask; mask 692 drivers/video/fbdev/pm3fb.c data = *mask & *bitmap; mask 696 drivers/video/fbdev/pm3fb.c (cursor_bits_lookup[*mask >> 4] << 1)); mask 700 drivers/video/fbdev/pm3fb.c (cursor_bits_lookup[*mask & 0xf] << 1)); mask 702 drivers/video/fbdev/pm3fb.c mask++; mask 130 drivers/video/fbdev/pmag-aa-fb.c cursor->image.data, cursor->mask, cursor->rop, mask 80 drivers/video/fbdev/ps3fb.c u32 mask; mask 1088 drivers/video/fbdev/ps3fb.c dinfo->irq.mask = (1 << GPU_INTR_STATUS_VSYNC_1) | mask 1218 drivers/video/fbdev/ps3fb.c ps3fb.dinfo->irq.mask = 0; mask 1615 drivers/video/fbdev/riva/fbdev.c u8 *msk = (u8 *) cursor->mask; mask 31 drivers/video/fbdev/riva/nvreg.h #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) mask 34 drivers/video/fbdev/riva/nvreg.h #define SetBF(mask,value) ((value) << (0?mask)) mask 35 drivers/video/fbdev/riva/nvreg.h #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) mask 37 drivers/video/fbdev/riva/nvreg.h #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ mask 38 drivers/video/fbdev/riva/nvreg.h | SetBF(mask,value))) mask 51 drivers/video/fbdev/riva/nvreg.h #define DEVICE_DEF(device,mask,value) \ mask 52 drivers/video/fbdev/riva/nvreg.h SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value) mask 53 drivers/video/fbdev/riva/nvreg.h #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) mask 54 drivers/video/fbdev/riva/nvreg.h #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) mask 59 drivers/video/fbdev/riva/nvreg.h #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) mask 60 drivers/video/fbdev/riva/nvreg.h #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) mask 61 drivers/video/fbdev/riva/nvreg.h #define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) mask 66 drivers/video/fbdev/riva/nvreg.h #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) mask 67 drivers/video/fbdev/riva/nvreg.h #define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value) mask 68 drivers/video/fbdev/riva/nvreg.h #define PFB_Mask(mask) DEVICE_MASK(PFB,mask) mask 73 drivers/video/fbdev/riva/nvreg.h #define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value) mask 74 drivers/video/fbdev/riva/nvreg.h #define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value) mask 75 drivers/video/fbdev/riva/nvreg.h #define PRM_Mask(mask) DEVICE_MASK(PRM,mask) mask 80 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value) mask 81 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value) mask 82 drivers/video/fbdev/riva/nvreg.h #define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask) mask 87 drivers/video/fbdev/riva/nvreg.h #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value) mask 88 drivers/video/fbdev/riva/nvreg.h #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value) mask 89 drivers/video/fbdev/riva/nvreg.h #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) mask 94 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value) mask 95 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value) mask 96 drivers/video/fbdev/riva/nvreg.h #define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask) mask 101 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value) mask 102 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value) mask 103 drivers/video/fbdev/riva/nvreg.h #define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask) mask 108 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value) mask 109 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value) mask 110 drivers/video/fbdev/riva/nvreg.h #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask) mask 115 drivers/video/fbdev/riva/nvreg.h #define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value) mask 116 drivers/video/fbdev/riva/nvreg.h #define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value) mask 117 drivers/video/fbdev/riva/nvreg.h #define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask) mask 122 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value) mask 123 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value) mask 124 drivers/video/fbdev/riva/nvreg.h #define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask) mask 129 drivers/video/fbdev/riva/nvreg.h #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) mask 130 drivers/video/fbdev/riva/nvreg.h #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) mask 131 drivers/video/fbdev/riva/nvreg.h #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) mask 136 drivers/video/fbdev/riva/nvreg.h #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value) mask 137 drivers/video/fbdev/riva/nvreg.h #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value) mask 138 drivers/video/fbdev/riva/nvreg.h #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) mask 144 drivers/video/fbdev/riva/nvreg.h #define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value) mask 145 drivers/video/fbdev/riva/nvreg.h #define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value) mask 146 drivers/video/fbdev/riva/nvreg.h #define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask) mask 152 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value) mask 153 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value) mask 154 drivers/video/fbdev/riva/nvreg.h #define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask) mask 173 drivers/video/fbdev/riva/nvreg.h #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) mask 174 drivers/video/fbdev/riva/nvreg.h #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) mask 175 drivers/video/fbdev/riva/nvreg.h #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) mask 675 drivers/video/fbdev/s3c2410fb.c unsigned long set, unsigned long mask) mask 679 drivers/video/fbdev/s3c2410fb.c tmp = readl(reg) & ~mask; mask 739 drivers/video/fbdev/sa1100fb.c u_int mask = 0; mask 755 drivers/video/fbdev/sa1100fb.c mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; mask 759 drivers/video/fbdev/sa1100fb.c mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12; mask 763 drivers/video/fbdev/sa1100fb.c if (mask) { mask 774 drivers/video/fbdev/sa1100fb.c GPDR |= mask; mask 775 drivers/video/fbdev/sa1100fb.c GAFR |= mask; mask 234 drivers/video/fbdev/sbuslib.c ret |= get_user(addr, &argp->mask); mask 235 drivers/video/fbdev/sbuslib.c ret |= put_user(compat_ptr(addr), &p->mask); mask 331 drivers/video/fbdev/sh_mobile_lcdcfb.c unsigned long mask, unsigned long until) mask 333 drivers/video/fbdev/sh_mobile_lcdcfb.c while ((lcdc_read(priv, reg_offs) & mask) != until) mask 60 drivers/video/fbdev/simplefb.c u32 mask = (1 << info->var.transp.length) - 1; mask 61 drivers/video/fbdev/simplefb.c mask <<= info->var.transp.offset; mask 62 drivers/video/fbdev/simplefb.c value |= mask; mask 3324 drivers/video/fbdev/sis/init.c #define GENBITSMASK(mask) GENMASK(1?mask,0?mask) mask 3325 drivers/video/fbdev/sis/init.c #define GETBITS(var,mask) (((var) & GENBITSMASK(mask)) >> (0?mask)) mask 9434 drivers/video/fbdev/sis/init301.c unsigned char mask, value; mask 9443 drivers/video/fbdev/sis/init301.c mask = 0xf0; mask 9449 drivers/video/fbdev/sis/init301.c mask = 0xff; mask 9459 drivers/video/fbdev/sis/init301.c temp &= mask; mask 496 drivers/video/fbdev/sis/sis_main.c if(emodes & sisfb_ddcsmodes[i].mask) { mask 452 drivers/video/fbdev/sis/sis_main.h u32 mask; mask 1117 drivers/video/fbdev/sm501fb.c const unsigned char *pmsk = cursor->mask; mask 424 drivers/video/fbdev/stifb.c #define NGLE_BINC_SET_DSTMASK(fb, mask) \ mask 425 drivers/video/fbdev/stifb.c WRITE_WORD(mask, fb, REG_22) mask 721 drivers/video/fbdev/stifb.c ngleClearOverlayPlanes(struct stifb_info *fb, int mask, int data) mask 738 drivers/video/fbdev/stifb.c NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, mask); mask 1117 drivers/video/fbdev/tdfxfb.c u8 *mask = (u8 *)cursor->mask; mask 1127 drivers/video/fbdev/tdfxfb.c u8 data = *mask ^ *bitmap; mask 1129 drivers/video/fbdev/tdfxfb.c data = *mask & *bitmap; mask 1131 drivers/video/fbdev/tdfxfb.c fb_writeb(*mask, cursorbase + h); mask 1132 drivers/video/fbdev/tdfxfb.c mask++; mask 710 drivers/video/fbdev/tgafb.c u32 mask = 0; mask 715 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j]) << (j * 8); mask 717 drivers/video/fbdev/tgafb.c __raw_writel(mask << shift, fb_base + pos); mask 741 drivers/video/fbdev/tgafb.c u32 mask = 0; mask 742 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+0]) << (0 * 8); mask 743 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+1]) << (1 * 8); mask 744 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+2]) << (2 * 8); mask 745 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+3]) << (3 * 8); mask 746 drivers/video/fbdev/tgafb.c __raw_writel(mask, fb_base + pos + j*bincr); mask 763 drivers/video/fbdev/tgafb.c u32 mask = 0; mask 765 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j]) << (j * 8); mask 766 drivers/video/fbdev/tgafb.c __raw_writel(mask, fb_base + pos); mask 791 drivers/video/fbdev/tgafb.c u32 mask = 0; mask 792 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+0]) << (0 * 8); mask 793 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[j+1]) << (1 * 8); mask 794 drivers/video/fbdev/tgafb.c mask <<= shift; mask 795 drivers/video/fbdev/tgafb.c __raw_writel(mask, fb_base + pos + j*bincr); mask 812 drivers/video/fbdev/tgafb.c u32 mask = bitrev8(data[0]); mask 814 drivers/video/fbdev/tgafb.c mask |= bitrev8(data[1]) << 8; mask 815 drivers/video/fbdev/tgafb.c mask <<= shift; mask 816 drivers/video/fbdev/tgafb.c __raw_writel(mask, fb_base + pos); mask 137 drivers/video/fbdev/vga16fb.c static inline void setmask(int mask) mask 139 drivers/video/fbdev/vga16fb.c vga_io_w(VGA_GFX_D, mask); mask 507 drivers/video/fbdev/via/accel.c u32 mask; mask 513 drivers/video/fbdev/via/accel.c mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 | mask 522 drivers/video/fbdev/via/accel.c mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY; mask 526 drivers/video/fbdev/via/accel.c while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) { mask 680 drivers/video/fbdev/via/hw.c u8 value, mask = 1 << offset; mask 687 drivers/video/fbdev/via/hw.c value = mask; mask 694 drivers/video/fbdev/via/hw.c via_write_reg_mask(VIACR, index, value, mask); mask 1009 drivers/video/fbdev/via/hw.c RegTable[i].value, RegTable[i].mask); mask 1825 drivers/video/fbdev/via/hw.c u8 value, index, mask; mask 1843 drivers/video/fbdev/via/hw.c mask = res_patch_table[0].io_reg_table[j].mask; mask 1844 drivers/video/fbdev/via/hw.c viafb_write_reg_mask(index, port, value, mask); mask 803 drivers/video/fbdev/via/lcd.c int i, mask, data; mask 809 drivers/video/fbdev/via/lcd.c mask = PowerSequenceOff[0][i]; mask 810 drivers/video/fbdev/via/lcd.c data = PowerSequenceOff[1][i] & mask; mask 811 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask); mask 821 drivers/video/fbdev/via/lcd.c int i, mask, data; mask 830 drivers/video/fbdev/via/lcd.c mask = PowerSequenceOn[0][i]; mask 831 drivers/video/fbdev/via/lcd.c data = PowerSequenceOn[1][i] & mask; mask 832 drivers/video/fbdev/via/lcd.c viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask); mask 314 drivers/video/fbdev/via/share.h u8 mask; mask 94 drivers/video/fbdev/via/via-core.c void viafb_irq_enable(u32 mask) mask 96 drivers/video/fbdev/via/via-core.c viafb_enabled_ints |= mask; mask 101 drivers/video/fbdev/via/via-core.c void viafb_irq_disable(u32 mask) mask 103 drivers/video/fbdev/via/via-core.c viafb_enabled_ints &= ~mask; mask 869 drivers/video/fbdev/via/viafbdev.c cr_data->data[i] = cursor->mask[i]; mask 874 drivers/video/fbdev/via/viafbdev.c cr_data->data[i] = cursor->mask[i]; mask 575 drivers/virt/fsl_hypervisor.c __poll_t mask; mask 580 drivers/virt/fsl_hypervisor.c mask = (dbq->head == dbq->tail) ? 0 : (EPOLLIN | EPOLLRDNORM); mask 584 drivers/virt/fsl_hypervisor.c return mask; mask 514 drivers/virt/vboxguest/vboxguest_core.c tracker->mask &= ~bitmask; mask 520 drivers/virt/vboxguest/vboxguest_core.c tracker->mask |= bitmask; mask 609 drivers/virt/vboxguest/vboxguest_core.c or_mask = gdev->fixed_events | gdev->event_filter_tracker.mask; mask 711 drivers/virt/vboxguest/vboxguest_core.c or_mask = gdev->guest_caps_tracker.mask; mask 48 drivers/virt/vboxguest/vboxguest_core.h u32 mask; mask 428 drivers/virtio/virtio_pci_common.c struct cpumask *mask; mask 435 drivers/virtio/virtio_pci_common.c mask = vp_dev->msix_affinity_masks[info->msix_vector]; mask 440 drivers/virtio/virtio_pci_common.c cpumask_copy(mask, cpu_mask); mask 441 drivers/virtio/virtio_pci_common.c irq_set_affinity_hint(irq, mask); mask 964 drivers/vme/bridges/vme_ca91cx42.c unsigned int mask, unsigned int compare, unsigned int swap, mask 996 drivers/vme/bridges/vme_ca91cx42.c iowrite32(mask, bridge->base + SCYC_EN); mask 811 drivers/vme/bridges/vme_fake.c unsigned int mask, unsigned int compare, unsigned int swap, mask 835 drivers/vme/bridges/vme_fake.c if ((tmp && mask) == (compare && mask)) { mask 836 drivers/vme/bridges/vme_fake.c tmp = tmp | (mask | swap); mask 837 drivers/vme/bridges/vme_fake.c tmp = tmp & (~mask | swap); mask 1364 drivers/vme/bridges/vme_tsi148.c unsigned int mask, unsigned int compare, unsigned int swap, mask 1393 drivers/vme/bridges/vme_tsi148.c iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); mask 765 drivers/vme/vme.c unsigned int vme_master_rmw(struct vme_resource *resource, unsigned int mask, mask 783 drivers/vme/vme.c return bridge->master_rmw(image, mask, compare, swap, offset); mask 93 drivers/w1/masters/omap_hdq.c u8 val, u8 mask) mask 95 drivers/w1/masters/omap_hdq.c u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask) mask 96 drivers/w1/masters/omap_hdq.c | (val & mask); mask 103 drivers/w1/masters/omap_hdq.c u32 mask) mask 108 drivers/w1/masters/omap_hdq.c writel(ie & mask, hdq_data->hdq_base + offset); mask 483 drivers/w1/masters/omap_hdq.c u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR; mask 496 drivers/w1/masters/omap_hdq.c ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); mask 510 drivers/w1/masters/omap_hdq.c ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask); mask 536 drivers/w1/masters/omap_hdq.c hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask); mask 128 drivers/w1/slaves/w1_ds2438.c static int w1_ds2438_change_config_bit(struct w1_slave *sl, u8 mask, u8 value) mask 153 drivers/w1/slaves/w1_ds2438.c value = mask; mask 155 drivers/w1/slaves/w1_ds2438.c if ((status & mask) == value) mask 159 drivers/w1/slaves/w1_ds2438.c status ^= mask; mask 336 drivers/w1/slaves/w1_therm.c uint8_t mask = 0x60; mask 389 drivers/w1/slaves/w1_therm.c rom[4] = (rom[4] & ~mask) | (precision_bits & mask); mask 158 drivers/watchdog/at91sam9_wdt.c u32 mask = wdt->mr_mask; mask 164 drivers/watchdog/at91sam9_wdt.c if ((tmp & mask) != (wdt->mr & mask)) { mask 168 drivers/watchdog/bcm_kona_wdt.c unsigned mask, unsigned newval) mask 180 drivers/watchdog/bcm_kona_wdt.c val &= ~mask; mask 70 drivers/watchdog/kempld_wdt.c u32 mask; mask 111 drivers/watchdog/kempld_wdt.c if (!stage || !stage->mask) mask 151 drivers/watchdog/kempld_wdt.c if (stage_timeout64 > stage->mask) mask 154 drivers/watchdog/kempld_wdt.c stage_timeout = stage_timeout64 & stage->mask; mask 181 drivers/watchdog/kempld_wdt.c if (!stage->mask) mask 188 drivers/watchdog/kempld_wdt.c stage_timeout = (stage_timeout & stage->mask) * prescaler; mask 210 drivers/watchdog/kempld_wdt.c if (pretimeout_stage->mask && wdt_data->pretimeout > 0) mask 236 drivers/watchdog/kempld_wdt.c if (!pretimeout_stage->mask) mask 371 drivers/watchdog/kempld_wdt.c u32 mask; mask 377 drivers/watchdog/kempld_wdt.c pretimeout_stage->mask = 0; mask 378 drivers/watchdog/kempld_wdt.c timeout_stage->mask = 0; mask 382 drivers/watchdog/kempld_wdt.c mask = 0; mask 394 drivers/watchdog/kempld_wdt.c mask |= 0xff << (j * 8); mask 399 drivers/watchdog/kempld_wdt.c if (!timeout_stage->mask) { mask 400 drivers/watchdog/kempld_wdt.c timeout_stage->mask = mask; mask 404 drivers/watchdog/kempld_wdt.c pretimeout_stage->mask = timeout_stage->mask; mask 405 drivers/watchdog/kempld_wdt.c timeout_stage->mask = mask; mask 413 drivers/watchdog/kempld_wdt.c if (!timeout_stage->mask) mask 70 drivers/watchdog/mlx_wdt.c if (regval & ~reg_data->mask) { mask 83 drivers/watchdog/mlx_wdt.c return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, mask 92 drivers/watchdog/mlx_wdt.c return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, mask 102 drivers/watchdog/mlx_wdt.c ~reg_data->mask, BIT(reg_data->bit), mask 120 drivers/watchdog/mlx_wdt.c regval = (regval & reg_data->mask) | hw_timeout; mask 381 drivers/watchdog/octeon-wdt-main.c cpumask_t mask; mask 383 drivers/watchdog/octeon-wdt-main.c cpumask_clear(&mask); mask 384 drivers/watchdog/octeon-wdt-main.c cpumask_set_cpu(cpu, &mask); mask 385 drivers/watchdog/octeon-wdt-main.c irq_set_affinity(irq, &mask); mask 294 drivers/watchdog/orion_wdt.c u32 reg, mask; mask 304 drivers/watchdog/orion_wdt.c mask = dev->data->wdt_enable_bit; mask 306 drivers/watchdog/orion_wdt.c mask |= TIMER1_ENABLE_BIT; mask 307 drivers/watchdog/orion_wdt.c atomic_io_modify(dev->reg + TIMER_CTRL, mask, 0); mask 203 drivers/watchdog/s3c2410_wdt.c static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) mask 213 drivers/watchdog/s3c2410_wdt.c if (mask) mask 343 drivers/watchdog/sp805_wdt.c .mask = 0x00ffffff, mask 131 drivers/watchdog/wdat_wdt.c u32 flags, value, mask, x, y; mask 140 drivers/watchdog/wdat_wdt.c mask = entry->mask; mask 148 drivers/watchdog/wdat_wdt.c x &= mask; mask 158 drivers/watchdog/wdat_wdt.c x &= mask; mask 164 drivers/watchdog/wdat_wdt.c x = value & mask; mask 170 drivers/watchdog/wdat_wdt.c y = y & ~(mask << gas->bit_offset); mask 180 drivers/watchdog/wdat_wdt.c x &= mask; mask 186 drivers/watchdog/wdat_wdt.c y = y & ~(mask << gas->bit_offset); mask 168 drivers/watchdog/zx2967_wdt.c unsigned int offset, mask, config; mask 178 drivers/watchdog/zx2967_wdt.c mask = out_args.args[2]; mask 186 drivers/watchdog/zx2967_wdt.c regmap_update_bits(regmap, offset, mask, config); mask 366 drivers/xen/events/events_2l.c .mask = evtchn_2l_mask, mask 392 drivers/xen/events/events_fifo.c .mask = evtchn_fifo_mask, mask 67 drivers/xen/events/events_internal.h void (*mask)(unsigned port); mask 127 drivers/xen/events/events_internal.h return evtchn_ops->mask(port); mask 626 drivers/xen/evtchn.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; mask 631 drivers/xen/evtchn.c mask |= EPOLLIN | EPOLLRDNORM; mask 633 drivers/xen/evtchn.c mask = EPOLLERR; mask 634 drivers/xen/evtchn.c return mask; mask 960 drivers/xen/pvcalls-front.c __poll_t mask = 0; mask 969 drivers/xen/pvcalls-front.c mask |= EPOLLOUT | EPOLLWRNORM; mask 971 drivers/xen/pvcalls-front.c mask |= EPOLLIN | EPOLLRDNORM; mask 973 drivers/xen/pvcalls-front.c mask |= EPOLLERR; mask 975 drivers/xen/pvcalls-front.c return mask; mask 537 drivers/xen/swiotlb-xen.c xen_swiotlb_dma_supported(struct device *hwdev, u64 mask) mask 539 drivers/xen/swiotlb-xen.c return xen_virt_to_bus(xen_io_tlb_end - 1) <= mask; mask 39 drivers/xen/xen-pciback/conf_space.h unsigned int mask; mask 175 drivers/xen/xen-pciback/conf_space_header.c u32 mask; mask 187 drivers/xen/xen-pciback/conf_space_header.c mask = ~PCI_BASE_ADDRESS_IO_MASK; mask 189 drivers/xen/xen-pciback/conf_space_header.c mask = 0; mask 191 drivers/xen/xen-pciback/conf_space_header.c mask = ~PCI_BASE_ADDRESS_MEM_MASK; mask 192 drivers/xen/xen-pciback/conf_space_header.c if ((value | mask) == ~0U) mask 1046 drivers/xen/xen-pciback/pci_stub.c *slot, int *func, int *reg, int *size, int *mask) mask 1051 drivers/xen/xen-pciback/pci_stub.c reg, size, mask, &parsed); mask 1058 drivers/xen/xen-pciback/pci_stub.c mask, &parsed); mask 1136 drivers/xen/xen-pciback/pci_stub.c unsigned int mask) mask 1143 drivers/xen/xen-pciback/pci_stub.c if (reg > 0xfff || (size < 4 && (mask >> (size * 8)))) mask 1161 drivers/xen/xen-pciback/pci_stub.c field->mask = mask; mask 1309 drivers/xen/xen-pciback/pci_stub.c int domain, bus, slot, func, reg, size, mask; mask 1313 drivers/xen/xen-pciback/pci_stub.c &mask); mask 1317 drivers/xen/xen-pciback/pci_stub.c err = pcistub_reg_add(domain, bus, slot, func, reg, size, mask); mask 1359 drivers/xen/xen-pciback/pci_stub.c field->mask); mask 44 fs/affs/bitmap.c u32 blk, bmap, bit, mask, tmp; mask 69 fs/affs/bitmap.c mask = 1 << (bit & 31); mask 74 fs/affs/bitmap.c if (tmp & mask) mask 76 fs/affs/bitmap.c *data = cpu_to_be32(tmp | mask); mask 80 fs/affs/bitmap.c *(__be32 *)bh->b_data = cpu_to_be32(tmp - mask); mask 122 fs/affs/bitmap.c u32 blk, bmap, bit, mask, mask2, tmp; mask 185 fs/affs/bitmap.c mask = ~0UL << (bit & 31); mask 189 fs/affs/bitmap.c if (tmp & mask) mask 202 fs/affs/bitmap.c mask = ~0; mask 206 fs/affs/bitmap.c bit = ffs(tmp & mask) - 1; mask 208 fs/affs/bitmap.c mask2 = mask = 1 << (bit & 31); mask 216 fs/affs/bitmap.c mask |= mask2; mask 220 fs/affs/bitmap.c *data = cpu_to_be32(tmp & ~mask); mask 224 fs/affs/bitmap.c *(__be32 *)bh->b_data = cpu_to_be32(tmp + mask); mask 249 fs/affs/bitmap.c u32 size, blk, end, offset, mask; mask 316 fs/affs/bitmap.c mask = ~(0xFFFFFFFFU << (offset & 31)); mask 317 fs/affs/bitmap.c pr_debug("last word: %d %d %d\n", offset, offset / 32 + 1, mask); mask 320 fs/affs/bitmap.c if (mask) { mask 325 fs/affs/bitmap.c new = old & mask; mask 26 fs/afs/dir_edit.c u32 mask; mask 39 fs/afs/dir_edit.c mask = (1 << nr_slots) - 1; mask 51 fs/afs/dir_edit.c if ((bitmap & mask) == 0) { mask 71 fs/afs/dir_edit.c u64 mask; mask 73 fs/afs/dir_edit.c mask = (1 << nr_slots) - 1; mask 74 fs/afs/dir_edit.c mask <<= bit; mask 76 fs/afs/dir_edit.c block->hdr.bitmap[0] |= (u8)(mask >> 0 * 8); mask 77 fs/afs/dir_edit.c block->hdr.bitmap[1] |= (u8)(mask >> 1 * 8); mask 78 fs/afs/dir_edit.c block->hdr.bitmap[2] |= (u8)(mask >> 2 * 8); mask 79 fs/afs/dir_edit.c block->hdr.bitmap[3] |= (u8)(mask >> 3 * 8); mask 80 fs/afs/dir_edit.c block->hdr.bitmap[4] |= (u8)(mask >> 4 * 8); mask 81 fs/afs/dir_edit.c block->hdr.bitmap[5] |= (u8)(mask >> 5 * 8); mask 82 fs/afs/dir_edit.c block->hdr.bitmap[6] |= (u8)(mask >> 6 * 8); mask 83 fs/afs/dir_edit.c block->hdr.bitmap[7] |= (u8)(mask >> 7 * 8); mask 92 fs/afs/dir_edit.c u64 mask; mask 94 fs/afs/dir_edit.c mask = (1 << nr_slots) - 1; mask 95 fs/afs/dir_edit.c mask <<= bit; mask 97 fs/afs/dir_edit.c block->hdr.bitmap[0] &= ~(u8)(mask >> 0 * 8); mask 98 fs/afs/dir_edit.c block->hdr.bitmap[1] &= ~(u8)(mask >> 1 * 8); mask 99 fs/afs/dir_edit.c block->hdr.bitmap[2] &= ~(u8)(mask >> 2 * 8); mask 100 fs/afs/dir_edit.c block->hdr.bitmap[3] &= ~(u8)(mask >> 3 * 8); mask 101 fs/afs/dir_edit.c block->hdr.bitmap[4] &= ~(u8)(mask >> 4 * 8); mask 102 fs/afs/dir_edit.c block->hdr.bitmap[5] &= ~(u8)(mask >> 5 * 8); mask 103 fs/afs/dir_edit.c block->hdr.bitmap[6] &= ~(u8)(mask >> 6 * 8); mask 104 fs/afs/dir_edit.c block->hdr.bitmap[7] &= ~(u8)(mask >> 7 * 8); mask 186 fs/afs/fsclient.c u32 mask = 0, mtime = 0, owner = 0, group = 0, mode = 0; mask 188 fs/afs/fsclient.c mask = 0; mask 190 fs/afs/fsclient.c mask |= AFS_SET_MTIME; mask 195 fs/afs/fsclient.c mask |= AFS_SET_OWNER; mask 200 fs/afs/fsclient.c mask |= AFS_SET_GROUP; mask 205 fs/afs/fsclient.c mask |= AFS_SET_MODE; mask 209 fs/afs/fsclient.c *bp++ = htonl(mask); mask 112 fs/afs/protocol_yfs.h __be32 mask; mask 155 fs/afs/protocol_yfs.h __be32 mask; mask 401 fs/afs/security.c int afs_permission(struct inode *inode, int mask) mask 409 fs/afs/security.c vnode->fid.vid, vnode->fid.vnode, vnode->flags, mask); mask 411 fs/afs/security.c if (mask & MAY_NOT_BLOCK) { mask 439 fs/afs/security.c mask, access, S_ISDIR(inode->i_mode) ? "dir" : "file"); mask 443 fs/afs/security.c if (mask & (MAY_EXEC | MAY_READ | MAY_CHDIR)) { mask 447 fs/afs/security.c if (mask & MAY_WRITE) { mask 455 fs/afs/security.c if ((mask & MAY_EXEC) && !(inode->i_mode & S_IXUSR)) mask 457 fs/afs/security.c if (mask & (MAY_EXEC | MAY_READ)) { mask 462 fs/afs/security.c } else if (mask & MAY_WRITE) { mask 92 fs/afs/yfsclient.c x->mask = htonl(AFS_SET_MODE); mask 105 fs/afs/yfsclient.c x->mask = htonl(AFS_SET_MTIME); mask 279 fs/afs/yfsclient.c u32 mask = 0, mode = 0; mask 281 fs/afs/yfsclient.c mask = 0; mask 283 fs/afs/yfsclient.c mask |= AFS_SET_MTIME; mask 288 fs/afs/yfsclient.c mask |= AFS_SET_OWNER; mask 293 fs/afs/yfsclient.c mask |= AFS_SET_GROUP; mask 298 fs/afs/yfsclient.c mask |= AFS_SET_MODE; mask 302 fs/afs/yfsclient.c x->mask = htonl(mask); mask 1635 fs/aio.c __poll_t mask = 0; mask 1638 fs/aio.c mask = vfs_poll(req->file, &pt) & req->events; mask 1648 fs/aio.c if (!mask && !READ_ONCE(req->cancelled)) { mask 1654 fs/aio.c iocb->ki_res.res = mangle_poll(mask); mask 1683 fs/aio.c __poll_t mask = key_to_poll(key); mask 1687 fs/aio.c if (mask && !(mask & req->events)) mask 1692 fs/aio.c if (mask && spin_trylock_irqsave(&iocb->ki_ctx->ctx_lock, flags)) { mask 1702 fs/aio.c iocb->ki_res.res = mangle_poll(mask); mask 1747 fs/aio.c __poll_t mask; mask 1772 fs/aio.c mask = vfs_poll(req->file, &apt.pt) & req->events; mask 1780 fs/aio.c mask = 0; mask 1782 fs/aio.c if (mask || apt.error) { mask 1792 fs/aio.c if (mask) { /* no async, we'd stolen it */ mask 1793 fs/aio.c aiocb->ki_res.res = mangle_poll(mask); mask 1797 fs/aio.c if (mask) mask 88 fs/bad_inode.c static int bad_inode_permission(struct inode *inode, int mask) mask 58 fs/binfmt_misc.c char *mask; /* mask, NULL for exact match */ mask 114 fs/binfmt_misc.c if (e->mask) { mask 116 fs/binfmt_misc.c if ((*s++ ^ e->magic[j]) & e->mask[j]) mask 416 fs/binfmt_misc.c e->mask = p; mask 420 fs/binfmt_misc.c if (!e->mask[0]) { mask 421 fs/binfmt_misc.c e->mask = NULL; mask 426 fs/binfmt_misc.c DUMP_PREFIX_NONE, e->mask, p - e->mask); mask 435 fs/binfmt_misc.c if (e->mask && mask 436 fs/binfmt_misc.c string_unescape_inplace(e->mask, UNESCAPE_HEX) != e->size) mask 447 fs/binfmt_misc.c if (e->mask) { mask 453 fs/binfmt_misc.c DUMP_PREFIX_NONE, e->mask, e->size); mask 457 fs/binfmt_misc.c masked[i] = e->magic[i] & e->mask[i]; mask 581 fs/binfmt_misc.c if (e->mask) { mask 583 fs/binfmt_misc.c dp = bin2hex(dp, e->mask, e->size); mask 292 fs/btrfs/extent_io.c static struct extent_state *alloc_extent_state(gfp_t mask) mask 300 fs/btrfs/extent_io.c mask &= ~(__GFP_DMA32|__GFP_HIGHMEM); mask 301 fs/btrfs/extent_io.c state = kmem_cache_alloc(extent_state_cache, mask); mask 310 fs/btrfs/extent_io.c trace_alloc_extent_state(state, mask, _RET_IP_); mask 671 fs/btrfs/extent_io.c gfp_t mask, struct extent_changeset *changeset) mask 693 fs/btrfs/extent_io.c if (!prealloc && gfpflags_allow_blocking(mask)) { mask 701 fs/btrfs/extent_io.c prealloc = alloc_extent_state(mask); mask 810 fs/btrfs/extent_io.c if (gfpflags_allow_blocking(mask)) mask 940 fs/btrfs/extent_io.c gfp_t mask, struct extent_changeset *changeset) mask 955 fs/btrfs/extent_io.c if (!prealloc && gfpflags_allow_blocking(mask)) { mask 963 fs/btrfs/extent_io.c prealloc = alloc_extent_state(mask); mask 1130 fs/btrfs/extent_io.c if (gfpflags_allow_blocking(mask)) mask 1145 fs/btrfs/extent_io.c struct extent_state **cached_state, gfp_t mask) mask 1148 fs/btrfs/extent_io.c cached_state, mask, NULL); mask 4410 fs/btrfs/extent_io.c struct page *page, gfp_t mask) mask 4425 fs/btrfs/extent_io.c 0, 0, NULL, mask, NULL); mask 4443 fs/btrfs/extent_io.c int try_release_extent_mapping(struct page *page, gfp_t mask) mask 4452 fs/btrfs/extent_io.c if (gfpflags_allow_blocking(mask) && mask 4485 fs/btrfs/extent_io.c return try_release_extent_state(tree, page, mask); mask 266 fs/btrfs/extent_io.h int try_release_extent_mapping(struct page *page, gfp_t mask); mask 297 fs/btrfs/extent_io.h struct extent_state **cached, gfp_t mask, mask 334 fs/btrfs/extent_io.h struct extent_state **cached_state, gfp_t mask); mask 352 fs/btrfs/extent_io.h u64 end, gfp_t mask) mask 355 fs/btrfs/extent_io.h NULL, mask); mask 395 fs/btrfs/extent_io.h u64 end, struct extent_state **cached_state, gfp_t mask) mask 398 fs/btrfs/extent_io.h cached_state, mask); mask 1427 fs/btrfs/file.c gfp_t mask = btrfs_alloc_write_mask(inode->i_mapping); mask 1434 fs/btrfs/file.c mask | __GFP_WRITE); mask 375 fs/btrfs/free-space-cache.c gfp_t mask = btrfs_alloc_write_mask(inode->i_mapping); mask 379 fs/btrfs/free-space-cache.c page = find_or_create_page(inode->i_mapping, i, mask); mask 5054 fs/btrfs/inode.c gfp_t mask = btrfs_alloc_write_mask(mapping); mask 5072 fs/btrfs/inode.c page = find_or_create_page(mapping, index, mask); mask 5300 fs/btrfs/inode.c int mask = attr->ia_valid; mask 5311 fs/btrfs/inode.c if (!(mask & (ATTR_CTIME | ATTR_MTIME))) mask 9204 fs/btrfs/inode.c u64 mask = fs_info->sectorsize - 1; mask 9208 fs/btrfs/inode.c ret = btrfs_wait_ordered_range(inode, inode->i_size & (~mask), mask 10632 fs/btrfs/inode.c static int btrfs_permission(struct inode *inode, int mask) mask 10637 fs/btrfs/inode.c if (mask & MAY_WRITE && mask 10644 fs/btrfs/inode.c return generic_permission(inode, mask); mask 1251 fs/btrfs/ioctl.c gfp_t mask = btrfs_alloc_write_mask(inode->i_mapping); mask 1272 fs/btrfs/ioctl.c start_index + i, mask); mask 14 fs/btrfs/rcu-string.h static inline struct rcu_string *rcu_string_strdup(const char *src, gfp_t mask) mask 18 fs/btrfs/rcu-string.h (len * sizeof(char)), mask); mask 3296 fs/btrfs/relocation.c gfp_t mask = btrfs_alloc_write_mask(inode->i_mapping); mask 3332 fs/btrfs/relocation.c mask); mask 3879 fs/btrfs/volumes.c u64 mask = (extended ? BTRFS_EXTENDED_PROFILE_MASK : mask 3885 fs/btrfs/volumes.c if (flags & ~mask) mask 294 fs/cachefiles/daemon.c __poll_t mask; mask 297 fs/cachefiles/daemon.c mask = 0; mask 300 fs/cachefiles/daemon.c mask |= EPOLLIN; mask 303 fs/cachefiles/daemon.c mask |= EPOLLOUT; mask 305 fs/cachefiles/daemon.c return mask; mask 601 fs/cachefiles/daemon.c unsigned long mask; mask 605 fs/cachefiles/daemon.c mask = simple_strtoul(args, &args, 0); mask 609 fs/cachefiles/daemon.c cachefiles_debug = mask; mask 1410 fs/ceph/addr.c sigset_t mask; mask 1411 fs/ceph/addr.c siginitsetinv(&mask, sigmask(SIGKILL)); mask 1412 fs/ceph/addr.c sigprocmask(SIG_BLOCK, &mask, oldset); mask 865 fs/ceph/caps.c int __ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, int touch) mask 871 fs/ceph/caps.c if ((have & mask) == mask) { mask 875 fs/ceph/caps.c ceph_cap_string(mask)); mask 883 fs/ceph/caps.c if ((cap->issued & mask) == mask) { mask 887 fs/ceph/caps.c ceph_cap_string(mask)); mask 895 fs/ceph/caps.c if ((have & mask) == mask) { mask 899 fs/ceph/caps.c ceph_cap_string(mask)); mask 925 fs/ceph/caps.c struct ceph_cap *ocap, int mask) mask 933 fs/ceph/caps.c (cap->implemented & ~cap->issued & mask)) mask 939 fs/ceph/caps.c int ceph_caps_revoking(struct ceph_inode_info *ci, int mask) mask 945 fs/ceph/caps.c ret = __ceph_caps_revoking_other(ci, NULL, mask); mask 948 fs/ceph/caps.c ceph_cap_string(mask), ret); mask 1614 fs/ceph/caps.c int __ceph_mark_dirty_caps(struct ceph_inode_info *ci, int mask, mask 1626 fs/ceph/caps.c inode, ceph_ino(inode), ceph_cap_string(mask)); mask 1631 fs/ceph/caps.c ceph_cap_string(mask), ceph_cap_string(was), mask 1632 fs/ceph/caps.c ceph_cap_string(was | mask)); mask 1633 fs/ceph/caps.c ci->i_dirty_caps |= mask; mask 1658 fs/ceph/caps.c (mask & CEPH_CAP_FILE_BUFFER)) mask 740 fs/ceph/dir.c int mask; mask 780 fs/ceph/dir.c mask = CEPH_STAT_CAP_INODE | CEPH_CAP_AUTH_SHARED; mask 782 fs/ceph/dir.c mask |= CEPH_CAP_XATTR_SHARED; mask 783 fs/ceph/dir.c req->r_args.getattr.mask = cpu_to_le32(mask); mask 1597 fs/ceph/dir.c u32 mask; mask 1610 fs/ceph/dir.c mask = CEPH_STAT_CAP_INODE | CEPH_CAP_AUTH_SHARED; mask 1612 fs/ceph/dir.c mask |= CEPH_CAP_XATTR_SHARED; mask 1613 fs/ceph/dir.c req->r_args.getattr.mask = cpu_to_le32(mask); mask 135 fs/ceph/export.c int mask; mask 142 fs/ceph/export.c mask = CEPH_STAT_CAP_INODE; mask 144 fs/ceph/export.c mask |= CEPH_CAP_XATTR_SHARED; mask 145 fs/ceph/export.c req->r_args.lookupino.mask = cpu_to_le32(mask); mask 192 fs/ceph/export.c int mask; mask 217 fs/ceph/export.c mask = CEPH_STAT_CAP_INODE; mask 219 fs/ceph/export.c mask |= CEPH_CAP_XATTR_SHARED; mask 220 fs/ceph/export.c req->r_args.lookupino.mask = cpu_to_le32(mask); mask 293 fs/ceph/export.c int mask; mask 311 fs/ceph/export.c mask = CEPH_STAT_CAP_INODE; mask 313 fs/ceph/export.c mask |= CEPH_CAP_XATTR_SHARED; mask 314 fs/ceph/export.c req->r_args.getattr.mask = cpu_to_le32(mask); mask 446 fs/ceph/file.c int mask; mask 487 fs/ceph/file.c mask = CEPH_STAT_CAP_INODE | CEPH_CAP_AUTH_SHARED; mask 489 fs/ceph/file.c mask |= CEPH_CAP_XATTR_SHARED; mask 490 fs/ceph/file.c req->r_args.open.mask = cpu_to_le32(mask); mask 1999 fs/ceph/inode.c int mask = 0; mask 2042 fs/ceph/inode.c mask |= CEPH_SETATTR_UID; mask 2057 fs/ceph/inode.c mask |= CEPH_SETATTR_GID; mask 2071 fs/ceph/inode.c mask |= CEPH_SETATTR_MODE; mask 2093 fs/ceph/inode.c mask |= CEPH_SETATTR_ATIME; mask 2113 fs/ceph/inode.c mask |= CEPH_SETATTR_SIZE; mask 2135 fs/ceph/inode.c mask |= CEPH_SETATTR_MTIME; mask 2162 fs/ceph/inode.c mask |= CEPH_SETATTR_CTIME; mask 2183 fs/ceph/inode.c if (mask) { mask 2187 fs/ceph/inode.c req->r_args.setattr.mask = cpu_to_le32(mask); mask 2193 fs/ceph/inode.c ceph_cap_string(dirtied), mask); mask 2198 fs/ceph/inode.c if (err >= 0 && (mask & CEPH_SETATTR_SIZE)) mask 2241 fs/ceph/inode.c int mask, bool force) mask 2255 fs/ceph/inode.c inode, ceph_cap_string(mask), inode->i_mode); mask 2256 fs/ceph/inode.c if (!force && ceph_caps_issued_mask(ceph_inode(inode), mask, 1)) mask 2259 fs/ceph/inode.c mode = (mask & CEPH_STAT_RSTAT) ? USE_AUTH_MDS : USE_ANY_MDS; mask 2266 fs/ceph/inode.c req->r_args.getattr.mask = cpu_to_le32(mask); mask 2290 fs/ceph/inode.c int ceph_permission(struct inode *inode, int mask) mask 2294 fs/ceph/inode.c if (mask & MAY_NOT_BLOCK) mask 2300 fs/ceph/inode.c err = generic_permission(inode, mask); mask 2307 fs/ceph/inode.c int mask = 0; mask 2310 fs/ceph/inode.c mask |= CEPH_CAP_AUTH_SHARED; mask 2313 fs/ceph/inode.c mask |= CEPH_CAP_LINK_SHARED; mask 2317 fs/ceph/inode.c mask |= CEPH_CAP_FILE_SHARED; mask 2320 fs/ceph/inode.c mask |= CEPH_CAP_XATTR_SHARED; mask 2322 fs/ceph/inode.c return mask; mask 936 fs/ceph/super.c req->r_args.getattr.mask = cpu_to_le32(CEPH_STAT_CAP_INODE); mask 635 fs/ceph/super.h extern int __ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, int t); mask 648 fs/ceph/super.h static inline int ceph_caps_issued_mask(struct ceph_inode_info *ci, int mask, mask 653 fs/ceph/super.h r = __ceph_caps_issued_mask(ci, mask, touch); mask 664 fs/ceph/super.h extern int __ceph_mark_dirty_caps(struct ceph_inode_info *ci, int mask, mask 668 fs/ceph/super.h struct ceph_cap *ocap, int mask); mask 669 fs/ceph/super.h extern int ceph_caps_revoking(struct ceph_inode_info *ci, int mask); mask 917 fs/ceph/super.h extern int ceph_inode_holds_cap(struct inode *inode, int mask); mask 927 fs/ceph/super.h int mask, bool force); mask 928 fs/ceph/super.h static inline int ceph_do_getattr(struct inode *inode, int mask, bool force) mask 930 fs/ceph/super.h return __ceph_do_getattr(inode, NULL, mask, force); mask 932 fs/ceph/super.h extern int ceph_permission(struct inode *inode, int mask); mask 809 fs/ceph/xattr.c int mask = 0; mask 815 fs/ceph/xattr.c mask = le32_to_cpu(req->r_args.getattr.mask); mask 818 fs/ceph/xattr.c mask = le32_to_cpu(req->r_args.open.mask); mask 821 fs/ceph/xattr.c return mask; mask 836 fs/ceph/xattr.c int mask = 0; mask 838 fs/ceph/xattr.c mask |= CEPH_STAT_RSTAT; mask 839 fs/ceph/xattr.c err = ceph_do_getattr(inode, mask, true); mask 296 fs/cifs/cifsfs.c static int cifs_permission(struct inode *inode, int mask) mask 303 fs/cifs/cifsfs.c if ((mask & MAY_EXEC) && !execute_ok(inode)) mask 311 fs/cifs/cifsfs.c return generic_permission(inode, mask); mask 1967 fs/cifs/cifspdu.h __u32 mask; /* which flags bits server understands ie 0x0001 */ mask 2767 fs/cifs/cifspdu.h __le64 mask; /* list of all possible attribute bits */ mask 3861 fs/cifs/cifssmb.c *pMask = le64_to_cpu(pfinfo->mask); mask 324 fs/cifs/transport.c sigset_t mask, oldmask; mask 362 fs/cifs/transport.c sigfillset(&mask); mask 363 fs/cifs/transport.c sigprocmask(SIG_BLOCK, &mask, &oldmask); mask 31 fs/coda/cache.c void coda_cache_enter(struct inode *inode, int mask) mask 39 fs/coda/cache.c cii->c_cached_perm = mask; mask 41 fs/coda/cache.c cii->c_cached_perm |= mask; mask 62 fs/coda/cache.c int coda_cache_check(struct inode *inode, int mask) mask 68 fs/coda/cache.c hit = (mask & cii->c_cached_perm) == mask && mask 15 fs/coda/coda_cache.h void coda_cache_enter(struct inode *inode, int mask); mask 18 fs/coda/coda_cache.h int coda_cache_check(struct inode *inode, int mask); mask 49 fs/coda/coda_linux.h int coda_permission(struct inode *inode, int mask); mask 79 fs/coda/coda_psdev.h int venus_access(struct super_block *sb, struct CodaFid *fid, int mask); mask 76 fs/coda/dir.c int coda_permission(struct inode *inode, int mask) mask 80 fs/coda/dir.c if (mask & MAY_NOT_BLOCK) mask 83 fs/coda/dir.c mask &= MAY_READ | MAY_WRITE | MAY_EXEC; mask 85 fs/coda/dir.c if (!mask) mask 88 fs/coda/dir.c if ((mask & MAY_EXEC) && !execute_ok(inode)) mask 91 fs/coda/dir.c if (coda_cache_check(inode, mask)) mask 94 fs/coda/dir.c error = venus_access(inode->i_sb, coda_i2f(inode), mask); mask 97 fs/coda/dir.c coda_cache_enter(inode, mask); mask 27 fs/coda/pioctl.c static int coda_ioctl_permission(struct inode *inode, int mask); mask 43 fs/coda/pioctl.c static int coda_ioctl_permission(struct inode *inode, int mask) mask 45 fs/coda/pioctl.c return (mask & MAY_EXEC) ? -EACCES : 0; mask 61 fs/coda/psdev.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; mask 66 fs/coda/psdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 69 fs/coda/psdev.c return mask; mask 456 fs/coda/upcall.c int venus_access(struct super_block *sb, struct CodaFid *fid, int mask) mask 466 fs/coda/upcall.c inp->coda_access.flags = mask; mask 196 fs/dcache.c unsigned long a,b,mask; mask 211 fs/dcache.c mask = bytemask_from_count(tcount); mask 212 fs/dcache.c return unlikely(!!((a ^ b) & mask)); mask 70 fs/dlm/lowcomms.c unsigned int mask; mask 80 fs/dlm/lowcomms.c return ((cb->base + cb->len) & cb->mask); mask 86 fs/dlm/lowcomms.c cb->mask = size-1; mask 93 fs/dlm/lowcomms.c cb->base &= cb->mask; mask 465 fs/dlm/plock.c __poll_t mask = 0; mask 471 fs/dlm/plock.c mask = EPOLLIN | EPOLLRDNORM; mask 474 fs/dlm/plock.c return mask; mask 865 fs/ecryptfs/inode.c ecryptfs_permission(struct inode *inode, int mask) mask 867 fs/ecryptfs/inode.c return inode_permission(ecryptfs_inode_to_lower(inode), mask); mask 32 fs/ecryptfs/miscdev.c __poll_t mask = 0; mask 49 fs/ecryptfs/miscdev.c mask |= EPOLLIN | EPOLLRDNORM; mask 53 fs/ecryptfs/miscdev.c return mask; mask 243 fs/ext2/dir.c ext2_validate_entry(char *base, unsigned offset, unsigned mask) mask 246 fs/ext2/dir.c ext2_dirent *p = (ext2_dirent*)(base + (offset&mask)); mask 513 fs/ext2/ext2.h #define EXT2_HAS_COMPAT_FEATURE(sb,mask) \ mask 514 fs/ext2/ext2.h ( EXT2_SB(sb)->s_es->s_feature_compat & cpu_to_le32(mask) ) mask 515 fs/ext2/ext2.h #define EXT2_HAS_RO_COMPAT_FEATURE(sb,mask) \ mask 516 fs/ext2/ext2.h ( EXT2_SB(sb)->s_es->s_feature_ro_compat & cpu_to_le32(mask) ) mask 517 fs/ext2/ext2.h #define EXT2_HAS_INCOMPAT_FEATURE(sb,mask) \ mask 518 fs/ext2/ext2.h ( EXT2_SB(sb)->s_es->s_feature_incompat & cpu_to_le32(mask) ) mask 519 fs/ext2/ext2.h #define EXT2_SET_COMPAT_FEATURE(sb,mask) \ mask 520 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_compat |= cpu_to_le32(mask) mask 521 fs/ext2/ext2.h #define EXT2_SET_RO_COMPAT_FEATURE(sb,mask) \ mask 522 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_ro_compat |= cpu_to_le32(mask) mask 523 fs/ext2/ext2.h #define EXT2_SET_INCOMPAT_FEATURE(sb,mask) \ mask 524 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_incompat |= cpu_to_le32(mask) mask 525 fs/ext2/ext2.h #define EXT2_CLEAR_COMPAT_FEATURE(sb,mask) \ mask 526 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_compat &= ~cpu_to_le32(mask) mask 527 fs/ext2/ext2.h #define EXT2_CLEAR_RO_COMPAT_FEATURE(sb,mask) \ mask 528 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_ro_compat &= ~cpu_to_le32(mask) mask 529 fs/ext2/ext2.h #define EXT2_CLEAR_INCOMPAT_FEATURE(sb,mask) \ mask 530 fs/ext2/ext2.h EXT2_SB(sb)->s_es->s_feature_incompat &= ~cpu_to_le32(mask) mask 302 fs/ext4/ioctl.c unsigned int oldflags, mask, i; mask 384 fs/ext4/ioctl.c for (i = 0, mask = 1; i < 32; i++, mask <<= 1) { mask 385 fs/ext4/ioctl.c if (!(mask & EXT4_FL_USER_MODIFIABLE)) mask 388 fs/ext4/ioctl.c if (mask == EXT4_JOURNAL_DATA_FL || mask == EXT4_EXTENTS_FL) mask 390 fs/ext4/ioctl.c if (mask & flags) mask 858 fs/ext4/xattr.c size_t mask = ~(cluster_size - 1); mask 860 fs/ext4/xattr.c return (length + cluster_size - 1) & mask; mask 160 fs/f2fs/f2fs.h #define __F2FS_HAS_FEATURE(raw_super, mask) \ mask 161 fs/f2fs/f2fs.h ((raw_super->feature & cpu_to_le32(mask)) != 0) mask 162 fs/f2fs/f2fs.h #define F2FS_HAS_FEATURE(sbi, mask) __F2FS_HAS_FEATURE(sbi->raw_super, mask) mask 163 fs/f2fs/f2fs.h #define F2FS_SET_FEATURE(sbi, mask) \ mask 164 fs/f2fs/f2fs.h (sbi->raw_super->feature |= cpu_to_le32(mask)) mask 165 fs/f2fs/f2fs.h #define F2FS_CLEAR_FEATURE(sbi, mask) \ mask 166 fs/f2fs/f2fs.h (sbi->raw_super->feature &= ~cpu_to_le32(mask)) mask 2310 fs/f2fs/f2fs.h int mask; mask 2313 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2314 fs/f2fs/f2fs.h return mask & *addr; mask 2319 fs/f2fs/f2fs.h int mask; mask 2322 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2323 fs/f2fs/f2fs.h *addr |= mask; mask 2328 fs/f2fs/f2fs.h int mask; mask 2331 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2332 fs/f2fs/f2fs.h *addr &= ~mask; mask 2337 fs/f2fs/f2fs.h int mask; mask 2341 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2342 fs/f2fs/f2fs.h ret = mask & *addr; mask 2343 fs/f2fs/f2fs.h *addr |= mask; mask 2349 fs/f2fs/f2fs.h int mask; mask 2353 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2354 fs/f2fs/f2fs.h ret = mask & *addr; mask 2355 fs/f2fs/f2fs.h *addr &= ~mask; mask 2361 fs/f2fs/f2fs.h int mask; mask 2364 fs/f2fs/f2fs.h mask = 1 << (7 - (nr & 0x07)); mask 2365 fs/f2fs/f2fs.h *addr ^= mask; mask 1667 fs/f2fs/file.c static int f2fs_setflags_common(struct inode *inode, u32 iflags, u32 mask) mask 1682 fs/f2fs/file.c fi->i_flags = iflags | (fi->i_flags & ~mask); mask 87 fs/f2fs/node.h unsigned char mask = 0x01 << type; mask 89 fs/f2fs/node.h ne->ni.flag |= mask; mask 91 fs/f2fs/node.h ne->ni.flag &= ~mask; mask 96 fs/f2fs/node.h unsigned char mask = 0x01 << type; mask 97 fs/f2fs/node.h return ne->ni.flag & mask; mask 188 fs/fat/fat.h umode_t mask; mask 193 fs/fat/fat.h mask = ~sbi->options.fs_dmask; mask 195 fs/fat/fat.h mask = ~sbi->options.fs_fmask; mask 197 fs/fat/fat.h if (!(mask & S_IWUGO)) mask 426 fs/fat/file.c umode_t mask, perm; mask 434 fs/fat/file.c mask = sbi->options.fs_fmask; mask 436 fs/fat/file.c mask = sbi->options.fs_dmask; mask 438 fs/fat/file.c perm = *mode_ptr & ~(S_IFMT | mask); mask 449 fs/fat/file.c if ((perm & S_IWUGO) && ((perm & S_IWUGO) != (S_IWUGO & ~mask))) mask 452 fs/fat/file.c if ((perm & S_IWUGO) != (S_IWUGO & ~mask)) mask 709 fs/file.c static struct file *__fget(unsigned int fd, fmode_t mask, unsigned int refs) mask 722 fs/file.c if (file->f_mode & mask) mask 765 fs/file.c static unsigned long __fget_light(unsigned int fd, fmode_t mask) mask 772 fs/file.c if (!file || unlikely(file->f_mode & mask)) mask 776 fs/file.c file = __fget(fd, mask, 1); mask 2022 fs/fuse/dev.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; mask 2034 fs/fuse/dev.c mask = EPOLLERR; mask 2036 fs/fuse/dev.c mask |= EPOLLIN | EPOLLRDNORM; mask 2039 fs/fuse/dev.c return mask; mask 118 fs/fuse/dir.c static void fuse_invalidate_attr_mask(struct inode *inode, u32 mask) mask 120 fs/fuse/dir.c set_mask_bits(&get_fuse_inode(inode)->inval_mask, 0, mask); mask 1103 fs/fuse/dir.c static int fuse_access(struct inode *inode, int mask) mask 1110 fs/fuse/dir.c BUG_ON(mask & MAY_NOT_BLOCK); mask 1116 fs/fuse/dir.c inarg.mask = mask & (MAY_READ | MAY_WRITE | MAY_EXEC); mask 1130 fs/fuse/dir.c static int fuse_perm_getattr(struct inode *inode, int mask) mask 1132 fs/fuse/dir.c if (mask & MAY_NOT_BLOCK) mask 1152 fs/fuse/dir.c static int fuse_permission(struct inode *inode, int mask) mask 1165 fs/fuse/dir.c ((mask & MAY_EXEC) && S_ISREG(inode->i_mode))) { mask 1173 fs/fuse/dir.c err = fuse_perm_getattr(inode, mask); mask 1180 fs/fuse/dir.c err = generic_permission(inode, mask); mask 1186 fs/fuse/dir.c err = fuse_perm_getattr(inode, mask); mask 1188 fs/fuse/dir.c err = generic_permission(inode, mask); mask 1195 fs/fuse/dir.c } else if (mask & (MAY_ACCESS | MAY_CHDIR)) { mask 1196 fs/fuse/dir.c err = fuse_access(inode, mask); mask 1197 fs/fuse/dir.c } else if ((mask & MAY_EXEC) && S_ISREG(inode->i_mode)) { mask 1202 fs/fuse/dir.c err = fuse_perm_getattr(inode, mask); mask 216 fs/gfs2/file.c static int do_gfs2_set_flags(struct file *filp, u32 reqflags, u32 mask, mask 246 fs/gfs2/file.c new_flags = (flags & ~mask) | (reqflags & mask); mask 303 fs/gfs2/file.c u32 mask; mask 318 fs/gfs2/file.c mask = GFS2_FLAGS_USER_SET; mask 320 fs/gfs2/file.c mask &= ~GFS2_DIF_JDATA; mask 325 fs/gfs2/file.c mask &= ~(GFS2_DIF_TOPDIR | GFS2_DIF_INHERIT_JDATA); mask 328 fs/gfs2/file.c return do_gfs2_set_flags(filp, gfsflags, mask, fsflags); mask 1807 fs/gfs2/inode.c int gfs2_permission(struct inode *inode, int mask) mask 1816 fs/gfs2/inode.c if (mask & MAY_NOT_BLOCK) mask 1823 fs/gfs2/inode.c if ((mask & MAY_WRITE) && IS_IMMUTABLE(inode)) mask 1826 fs/gfs2/inode.c error = generic_permission(inode, mask); mask 102 fs/gfs2/inode.h extern int gfs2_permission(struct inode *inode, int mask); mask 171 fs/gfs2/rgrp.c static inline u64 gfs2_bit_search(const __le64 *ptr, u64 mask, u8 state) mask 182 fs/gfs2/rgrp.c tmp &= mask; mask 235 fs/gfs2/rgrp.c u64 mask = 0x5555555555555555ULL; mask 239 fs/gfs2/rgrp.c mask <<= spoint; mask 240 fs/gfs2/rgrp.c tmp = gfs2_bit_search(ptr, mask, state); mask 32 fs/hfs/bitmap.c u32 mask, start, len, n; mask 48 fs/hfs/bitmap.c mask = (1U << 31) >> i; mask 49 fs/hfs/bitmap.c for (; i < 32; mask >>= 1, i++) { mask 50 fs/hfs/bitmap.c if (!(n & mask)) mask 60 fs/hfs/bitmap.c mask = 1 << 31; mask 61 fs/hfs/bitmap.c for (i = 0; i < 32; mask >>= 1, i++) { mask 62 fs/hfs/bitmap.c if (!(n & mask)) mask 76 fs/hfs/bitmap.c n |= mask; mask 79 fs/hfs/bitmap.c mask >>= 1; mask 80 fs/hfs/bitmap.c if (!--len || n & mask) mask 99 fs/hfs/bitmap.c mask = 1U << 31; mask 101 fs/hfs/bitmap.c if (n & mask) mask 103 fs/hfs/bitmap.c n |= mask; mask 104 fs/hfs/bitmap.c mask >>= 1; mask 196 fs/hfs/bitmap.c u32 mask; mask 217 fs/hfs/bitmap.c mask = 0xffffffffU << j; mask 219 fs/hfs/bitmap.c mask |= 0xffffffffU >> (i + count); mask 220 fs/hfs/bitmap.c *curr &= cpu_to_be32(mask); mask 223 fs/hfs/bitmap.c *curr++ &= cpu_to_be32(mask); mask 234 fs/hfs/bitmap.c mask = 0xffffffffU >> count; mask 235 fs/hfs/bitmap.c *curr &= cpu_to_be32(mask); mask 72 fs/hfs/inode.c static int hfs_releasepage(struct page *page, gfp_t mask) mask 26 fs/hfsplus/bitmap.c u32 mask, start, len, n; mask 55 fs/hfsplus/bitmap.c mask = (1U << 31) >> i; mask 56 fs/hfsplus/bitmap.c for (; i < 32; mask >>= 1, i++) { mask 57 fs/hfsplus/bitmap.c if (!(n & mask)) mask 69 fs/hfsplus/bitmap.c mask = 1 << 31; mask 70 fs/hfsplus/bitmap.c for (i = 0; i < 32; mask >>= 1, i++) { mask 71 fs/hfsplus/bitmap.c if (!(n & mask)) mask 106 fs/hfsplus/bitmap.c n |= mask; mask 109 fs/hfsplus/bitmap.c mask >>= 1; mask 110 fs/hfsplus/bitmap.c if (!--len || n & mask) mask 144 fs/hfsplus/bitmap.c mask = 1U << 31; mask 146 fs/hfsplus/bitmap.c if (n & mask) mask 148 fs/hfsplus/bitmap.c n |= mask; mask 149 fs/hfsplus/bitmap.c mask >>= 1; mask 170 fs/hfsplus/bitmap.c u32 mask, len, pnr; mask 197 fs/hfsplus/bitmap.c mask = 0xffffffffU << j; mask 199 fs/hfsplus/bitmap.c mask |= 0xffffffffU >> (i + count); mask 200 fs/hfsplus/bitmap.c *curr++ &= cpu_to_be32(mask); mask 203 fs/hfsplus/bitmap.c *curr++ &= cpu_to_be32(mask); mask 229 fs/hfsplus/bitmap.c mask = 0xffffffffU >> count; mask 230 fs/hfsplus/bitmap.c *curr &= cpu_to_be32(mask); mask 232 fs/hfsplus/extents.c u32 ablock, dblock, mask; mask 281 fs/hfsplus/extents.c mask = (1 << sbi->fs_shift) - 1; mask 283 fs/hfsplus/extents.c sbi->blockoffset + (iblock & mask); mask 66 fs/hfsplus/inode.c static int hfsplus_releasepage(struct page *page, gfp_t mask) mask 1806 fs/inode.c int mask = 0; mask 1812 fs/inode.c mask = should_remove_suid(dentry); mask 1817 fs/inode.c mask |= ATTR_KILL_PRIV; mask 1818 fs/inode.c return mask; mask 2143 fs/inode.c unsigned int mask) mask 2145 fs/inode.c WARN_ON_ONCE(flags & ~mask); mask 2146 fs/inode.c set_mask_bits(&inode->i_flags, mask, flags); mask 1782 fs/io_uring.c __poll_t mask) mask 1785 fs/io_uring.c io_cqring_fill_event(ctx, req->user_data, mangle_poll(mask)); mask 1796 fs/io_uring.c __poll_t mask = 0; mask 1801 fs/io_uring.c mask = vfs_poll(poll->file, &pt) & poll->events; mask 1811 fs/io_uring.c if (!mask && !READ_ONCE(poll->canceled)) { mask 1817 fs/io_uring.c io_poll_complete(ctx, req, mask); mask 1833 fs/io_uring.c __poll_t mask = key_to_poll(key); mask 1837 fs/io_uring.c if (mask && !(mask & poll->events)) mask 1842 fs/io_uring.c if (mask && spin_trylock_irqsave(&ctx->completion_lock, flags)) { mask 1844 fs/io_uring.c io_poll_complete(ctx, req, mask); mask 1883 fs/io_uring.c __poll_t mask; mask 1913 fs/io_uring.c mask = vfs_poll(poll->file, &ipt.pt) & poll->events; mask 1922 fs/io_uring.c mask = 0; mask 1924 fs/io_uring.c if (mask || ipt.error) mask 1932 fs/io_uring.c if (mask) { /* no async, we'd stolen it */ mask 1934 fs/io_uring.c io_poll_complete(ctx, req, mask); mask 1938 fs/io_uring.c if (mask) { mask 3654 fs/io_uring.c __poll_t mask = 0; mask 3664 fs/io_uring.c mask |= EPOLLOUT | EPOLLWRNORM; mask 3666 fs/io_uring.c mask |= EPOLLIN | EPOLLRDNORM; mask 3668 fs/io_uring.c return mask; mask 418 fs/jfs/jfs_dmap.c u32 mask; mask 488 fs/jfs/jfs_dmap.c mask = mask 492 fs/jfs/jfs_dmap.c cpu_to_le32(~mask); mask 495 fs/jfs/jfs_dmap.c cpu_to_le32(mask); mask 1118 fs/jfs/jfs_dmap.c u32 mask; mask 1172 fs/jfs/jfs_dmap.c mask = (ONES << (DBWORD - nb) >> wbitno); mask 1173 fs/jfs/jfs_dmap.c if ((mask & ~le32_to_cpu(dp->wmap[word])) != mask) mask 3020 fs/jfs/jfs_dmap.c u32 mask; mask 3031 fs/jfs/jfs_dmap.c mask = ONES << (DBWORD - nb); mask 3035 fs/jfs/jfs_dmap.c for (bitno = 0; mask != 0; bitno += nb, mask >>= nb) { mask 3036 fs/jfs/jfs_dmap.c if ((mask & word) == mask) mask 3150 fs/jfs/jfs_dmap.c s64 mask; /* meant to be signed */ mask 3152 fs/jfs/jfs_dmap.c mask = (s64) 1 << (64 - 1); mask 3156 fs/jfs/jfs_dmap.c for (l2nb = 0; l2nb < 64; l2nb++, mask >>= 1) { mask 3159 fs/jfs/jfs_dmap.c if (nb & mask) { mask 3166 fs/jfs/jfs_dmap.c if (~mask & nb) mask 851 fs/jfs/jfs_imap.c u32 bitmap, mask; mask 909 fs/jfs/jfs_imap.c mask = HIGHORDER >> bitno; mask 911 fs/jfs/jfs_imap.c if (!(le32_to_cpu(iagp->wmap[extno]) & mask)) { mask 925 fs/jfs/jfs_imap.c bitmap = le32_to_cpu(iagp->wmap[extno]) & ~mask; mask 1193 fs/jfs/jfs_imap.c mask = HIGHORDER >> bitno; mask 1194 fs/jfs/jfs_imap.c iagp->inosmap[sword] |= cpu_to_le32(mask); mask 1195 fs/jfs/jfs_imap.c iagp->extsmap[sword] &= cpu_to_le32(~mask); mask 1325 fs/jfs/jfs_imap.c u32 mask, inosmap, extsmap; mask 1474 fs/jfs/jfs_imap.c mask = (bitno == 0) ? 0 : (ONES << (EXTSPERSUM - bitno)); mask 1475 fs/jfs/jfs_imap.c inosmap = le32_to_cpu(iagp->inosmap[sword]) | mask; mask 1476 fs/jfs/jfs_imap.c extsmap = le32_to_cpu(iagp->extsmap[sword]) | mask; mask 2009 fs/jfs/jfs_imap.c u32 mask; mask 2047 fs/jfs/jfs_imap.c mask = HIGHORDER >> bitno; mask 2051 fs/jfs/jfs_imap.c if (((le32_to_cpu(iagp->pmap[extno]) & mask) != 0) || mask 2052 fs/jfs/jfs_imap.c ((le32_to_cpu(iagp->wmap[extno]) & mask) != 0) || mask 2065 fs/jfs/jfs_imap.c iagp->wmap[extno] |= cpu_to_le32(mask); mask 2158 fs/jfs/jfs_imap.c u32 mask; mask 2346 fs/jfs/jfs_imap.c mask = HIGHORDER >> (extno & (EXTSPERSUM - 1)); mask 2347 fs/jfs/jfs_imap.c iagp->extsmap[sword] |= cpu_to_le32(mask); mask 2348 fs/jfs/jfs_imap.c iagp->inosmap[sword] &= cpu_to_le32(~mask); mask 2725 fs/jfs/jfs_imap.c u32 mask; mask 2752 fs/jfs/jfs_imap.c mask = HIGHORDER >> bitno; mask 2762 fs/jfs/jfs_imap.c if (!(le32_to_cpu(iagp->wmap[extno]) & mask)) { mask 2767 fs/jfs/jfs_imap.c if (!(le32_to_cpu(iagp->pmap[extno]) & mask)) { mask 2773 fs/jfs/jfs_imap.c iagp->pmap[extno] &= cpu_to_le32(~mask); mask 2782 fs/jfs/jfs_imap.c if (!(le32_to_cpu(iagp->wmap[extno]) & mask)) { mask 2788 fs/jfs/jfs_imap.c if ((le32_to_cpu(iagp->pmap[extno]) & mask) != 0) { mask 2795 fs/jfs/jfs_imap.c iagp->pmap[extno] |= cpu_to_le32(mask); mask 273 fs/kernfs/inode.c int kernfs_iop_permission(struct inode *inode, int mask) mask 277 fs/kernfs/inode.c if (mask & MAY_NOT_BLOCK) mask 286 fs/kernfs/inode.c return generic_permission(inode, mask); mask 90 fs/kernfs/kernfs-internal.h int kernfs_iop_permission(struct inode *inode, int mask); mask 74 fs/mbcache.c int mb_cache_entry_create(struct mb_cache *cache, gfp_t mask, u32 key, mask 88 fs/mbcache.c entry = kmem_cache_alloc(mb_entry_cache, mask); mask 262 fs/namei.c static int check_acl(struct inode *inode, int mask) mask 267 fs/namei.c if (mask & MAY_NOT_BLOCK) { mask 274 fs/namei.c return posix_acl_permission(inode, acl, mask & ~MAY_NOT_BLOCK); mask 281 fs/namei.c int error = posix_acl_permission(inode, acl, mask); mask 293 fs/namei.c static int acl_permission_check(struct inode *inode, int mask) mask 301 fs/namei.c int error = check_acl(inode, mask); mask 313 fs/namei.c if ((mask & ~mode & (MAY_READ | MAY_WRITE | MAY_EXEC)) == 0) mask 332 fs/namei.c int generic_permission(struct inode *inode, int mask) mask 339 fs/namei.c ret = acl_permission_check(inode, mask); mask 345 fs/namei.c if (!(mask & MAY_WRITE)) mask 357 fs/namei.c mask &= MAY_READ | MAY_WRITE | MAY_EXEC; mask 358 fs/namei.c if (mask == MAY_READ) mask 366 fs/namei.c if (!(mask & MAY_EXEC) || (inode->i_mode & S_IXUGO)) mask 380 fs/namei.c static inline int do_inode_permission(struct inode *inode, int mask) mask 384 fs/namei.c return inode->i_op->permission(inode, mask); mask 391 fs/namei.c return generic_permission(inode, mask); mask 402 fs/namei.c static int sb_permission(struct super_block *sb, struct inode *inode, int mask) mask 404 fs/namei.c if (unlikely(mask & MAY_WRITE)) { mask 425 fs/namei.c int inode_permission(struct inode *inode, int mask) mask 429 fs/namei.c retval = sb_permission(inode->i_sb, inode, mask); mask 433 fs/namei.c if (unlikely(mask & MAY_WRITE)) { mask 449 fs/namei.c retval = do_inode_permission(inode, mask); mask 453 fs/namei.c retval = devcgroup_inode_permission(inode, mask); mask 457 fs/namei.c return security_inode_permission(inode, mask); mask 1953 fs/namei.c unsigned long adata, mask, len; mask 1967 fs/namei.c mask = create_zero_mask(adata); mask 1968 fs/namei.c x ^= a & zero_bytemask(mask); mask 1970 fs/namei.c return hashlen_create(fold_hash(x, y), len + find_zero(mask)); mask 1981 fs/namei.c unsigned long adata, bdata, mask, len; mask 1997 fs/namei.c mask = create_zero_mask(adata | bdata); mask 1998 fs/namei.c x ^= a & zero_bytemask(mask); mask 2000 fs/namei.c return hashlen_create(fold_hash(x, y), len + find_zero(mask)); mask 601 fs/nfs/callback_proc.c validate_bitmap_values(unsigned int mask) mask 603 fs/nfs/callback_proc.c return (mask & ~RCA4_TYPE_MASK_ALL) == 0; mask 2349 fs/nfs/dir.c res->mask = cache->mask; mask 2384 fs/nfs/dir.c res->mask = cache->mask; mask 2433 fs/nfs/dir.c cache->mask = set->mask; mask 2471 fs/nfs/dir.c int mask = 0; mask 2474 fs/nfs/dir.c mask |= MAY_READ; mask 2477 fs/nfs/dir.c mask |= MAY_WRITE; mask 2479 fs/nfs/dir.c mask |= MAY_EXEC; mask 2482 fs/nfs/dir.c mask |= MAY_WRITE; mask 2484 fs/nfs/dir.c mask |= MAY_EXEC; mask 2486 fs/nfs/dir.c mask |= MAY_WRITE; mask 2487 fs/nfs/dir.c return mask; mask 2492 fs/nfs/dir.c entry->mask = access_result; mask 2496 fs/nfs/dir.c static int nfs_do_access(struct inode *inode, const struct cred *cred, int mask) mask 2499 fs/nfs/dir.c bool may_block = (mask & MAY_NOT_BLOCK) == 0; mask 2518 fs/nfs/dir.c cache.mask = NFS_ACCESS_READ | NFS_ACCESS_MODIFY | NFS_ACCESS_EXTEND; mask 2520 fs/nfs/dir.c cache.mask |= NFS_ACCESS_DELETE | NFS_ACCESS_LOOKUP; mask 2522 fs/nfs/dir.c cache.mask |= NFS_ACCESS_EXECUTE; mask 2535 fs/nfs/dir.c cache_mask = nfs_access_calc_mask(cache.mask, inode->i_mode); mask 2536 fs/nfs/dir.c if ((mask & ~cache_mask & (MAY_READ | MAY_WRITE | MAY_EXEC)) != 0) mask 2545 fs/nfs/dir.c int mask = 0; mask 2549 fs/nfs/dir.c mask = MAY_EXEC; mask 2552 fs/nfs/dir.c mask |= MAY_READ; mask 2554 fs/nfs/dir.c mask |= MAY_WRITE; mask 2557 fs/nfs/dir.c return mask; mask 2566 fs/nfs/dir.c static int nfs_execute_ok(struct inode *inode, int mask) mask 2574 fs/nfs/dir.c if (mask & MAY_NOT_BLOCK) mask 2583 fs/nfs/dir.c int nfs_permission(struct inode *inode, int mask) mask 2590 fs/nfs/dir.c if ((mask & (MAY_READ | MAY_WRITE | MAY_EXEC)) == 0) mask 2593 fs/nfs/dir.c if (mask & (MAY_ACCESS | MAY_CHDIR)) mask 2600 fs/nfs/dir.c if ((mask & MAY_OPEN) && mask 2609 fs/nfs/dir.c if ((mask & MAY_WRITE) && !(mask & MAY_READ)) mask 2619 fs/nfs/dir.c res = nfs_do_access(inode, cred, mask|MAY_NOT_BLOCK); mask 2621 fs/nfs/dir.c if (res == -ECHILD && !(mask & MAY_NOT_BLOCK)) { mask 2623 fs/nfs/dir.c res = nfs_do_access(inode, cred, mask); mask 2626 fs/nfs/dir.c if (!res && (mask & MAY_EXEC)) mask 2627 fs/nfs/dir.c res = nfs_execute_ok(inode, mask); mask 2630 fs/nfs/dir.c inode->i_sb->s_id, inode->i_ino, mask, res); mask 2633 fs/nfs/dir.c if (mask & MAY_NOT_BLOCK) mask 2638 fs/nfs/dir.c res = generic_permission(inode, mask); mask 79 fs/nfs/nfs3acl.c args.mask |= NFS_ACLCNT|NFS_ACL; mask 81 fs/nfs/nfs3acl.c args.mask |= NFS_DFACLCNT|NFS_DFACL; mask 82 fs/nfs/nfs3acl.c if (args.mask == 0) mask 91 fs/nfs/nfs3acl.c if (args.mask & NFS_ACL) mask 93 fs/nfs/nfs3acl.c if (args.mask & NFS_DFACL) mask 117 fs/nfs/nfs3acl.c if ((args.mask & res.mask) != args.mask) { mask 130 fs/nfs/nfs3acl.c if (res.mask & NFS_ACL) mask 135 fs/nfs/nfs3acl.c if (res.mask & NFS_DFACL) mask 166 fs/nfs/nfs3acl.c .mask = NFS_ACL, mask 191 fs/nfs/nfs3acl.c args.mask |= NFS_DFACL; mask 195 fs/nfs/nfs3proc.c .access = entry->mask, mask 1331 fs/nfs/nfs3xdr.c encode_uint32(xdr, args->mask); mask 1332 fs/nfs/nfs3xdr.c if (args->mask & (NFS_ACL | NFS_DFACL)) { mask 1349 fs/nfs/nfs3xdr.c encode_uint32(xdr, args->mask); mask 1358 fs/nfs/nfs3xdr.c (args->mask & NFS_ACL) ? mask 1363 fs/nfs/nfs3xdr.c (args->mask & NFS_DFACL) ? mask 2377 fs/nfs/nfs3xdr.c error = decode_uint32(xdr, &result->mask); mask 2381 fs/nfs/nfs3xdr.c if (result->mask & ~(NFS_ACL|NFS_ACLCNT|NFS_DFACL|NFS_DFACLCNT)) mask 2387 fs/nfs/nfs3xdr.c if (result->mask & NFS_ACL) mask 2390 fs/nfs/nfs3xdr.c if (result->mask & NFS_ACLCNT) mask 2397 fs/nfs/nfs3xdr.c if (result->mask & NFS_DFACL) mask 2400 fs/nfs/nfs3xdr.c if (result->mask & NFS_DFACLCNT) mask 2565 fs/nfs/nfs4proc.c u32 mask, flags; mask 2572 fs/nfs/nfs4proc.c mask = 0; mask 2580 fs/nfs/nfs4proc.c mask = NFS4_ACCESS_LOOKUP; mask 2582 fs/nfs/nfs4proc.c mask = NFS4_ACCESS_EXECUTE; mask 2584 fs/nfs/nfs4proc.c mask = NFS4_ACCESS_READ; mask 2591 fs/nfs/nfs4proc.c if ((mask & ~cache.mask & flags) == 0) mask 4346 fs/nfs/nfs4proc.c .access = entry->mask, mask 993 fs/nfs/nfs4xdr.c static size_t mask_bitmap4(const __u32 *bitmap, const __u32 *mask, mask 999 fs/nfs/nfs4xdr.c while (len > 0 && (bitmap[len-1] == 0 || mask[len-1] == 0)) mask 1002 fs/nfs/nfs4xdr.c tmp = bitmap[i] & mask[i]; mask 1246 fs/nfs/nfs4xdr.c const __u32 *bitmap, const __u32 *mask, size_t len, mask 1252 fs/nfs/nfs4xdr.c if (mask) { mask 1255 fs/nfs/nfs4xdr.c len = mask_bitmap4(bitmap, mask, masked_bitmap, len); mask 222 fs/nfs_common/nfsacl.c *group_obj = NULL, *mask = NULL; mask 239 fs/nfs_common/nfsacl.c mask = pa; mask 245 fs/nfs_common/nfsacl.c if (acl->a_count == 4 && group_obj && mask && mask 246 fs/nfs_common/nfsacl.c mask->e_perm == group_obj->e_perm) { mask 248 fs/nfs_common/nfsacl.c memmove(mask, mask+1, (3 - (mask - acl->a_entries)) * mask 1124 fs/nfsd/export.c static void show_expflags(struct seq_file *m, int flags, int mask) mask 1130 fs/nfsd/export.c if (flg->flag & ~mask) mask 147 fs/nfsd/filecache.c new->nfm_mark.mask = FS_ATTRIB|FS_DELETE_SELF; mask 539 fs/nfsd/filecache.c u32 mask, const void *data, int data_type, mask 543 fs/nfsd/filecache.c trace_nfsd_file_fsnotify_handle_event(inode, mask); mask 552 fs/nfsd/filecache.c if (mask & FS_ATTRIB) { mask 49 fs/nfsd/nfs2acl.c if (argp->mask & ~NFS_ACL_MASK) mask 51 fs/nfsd/nfs2acl.c resp->mask = argp->mask; mask 57 fs/nfsd/nfs2acl.c if (resp->mask & (NFS_ACL|NFS_ACLCNT)) { mask 69 fs/nfsd/nfs2acl.c if (resp->mask & (NFS_DFACL|NFS_DFACLCNT)) { mask 193 fs/nfsd/nfs2acl.c argp->mask = ntohl(*p); p++; mask 209 fs/nfsd/nfs2acl.c argp->mask = ntohl(*p++); mask 210 fs/nfsd/nfs2acl.c if (argp->mask & ~NFS_ACL_MASK || mask 216 fs/nfsd/nfs2acl.c (argp->mask & NFS_ACL) ? mask 220 fs/nfsd/nfs2acl.c (argp->mask & NFS_DFACL) ? mask 281 fs/nfsd/nfs2acl.c *p++ = htonl(resp->mask); mask 287 fs/nfsd/nfs2acl.c (resp->mask & NFS_ACL) ? resp->acl_access : NULL, mask 288 fs/nfsd/nfs2acl.c (resp->mask & NFS_DFACL) ? resp->acl_default : NULL); mask 297 fs/nfsd/nfs2acl.c resp->mask & NFS_ACL, 0); mask 301 fs/nfsd/nfs2acl.c resp->mask & NFS_DFACL, mask 46 fs/nfsd/nfs3acl.c if (argp->mask & ~NFS_ACL_MASK) mask 48 fs/nfsd/nfs3acl.c resp->mask = argp->mask; mask 50 fs/nfsd/nfs3acl.c if (resp->mask & (NFS_ACL|NFS_ACLCNT)) { mask 62 fs/nfsd/nfs3acl.c if (resp->mask & (NFS_DFACL|NFS_DFACLCNT)) { mask 135 fs/nfsd/nfs3acl.c args->mask = ntohl(*p); p++; mask 151 fs/nfsd/nfs3acl.c args->mask = ntohl(*p++); mask 152 fs/nfsd/nfs3acl.c if (args->mask & ~NFS_ACL_MASK || mask 158 fs/nfsd/nfs3acl.c (args->mask & NFS_ACL) ? mask 162 fs/nfsd/nfs3acl.c (args->mask & NFS_DFACL) ? mask 185 fs/nfsd/nfs3acl.c *p++ = htonl(resp->mask); mask 191 fs/nfsd/nfs3acl.c (resp->mask & NFS_ACL) ? resp->acl_access : NULL, mask 192 fs/nfsd/nfs3acl.c (resp->mask & NFS_DFACL) ? resp->acl_default : NULL); mask 201 fs/nfsd/nfs3acl.c resp->mask & NFS_ACL, 0); mask 205 fs/nfsd/nfs3acl.c resp->mask & NFS_DFACL, mask 68 fs/nfsd/nfs4acl.c int mask = NFS4_ANYONE_MODE; mask 71 fs/nfsd/nfs4acl.c mask |= NFS4_OWNER_MODE; mask 73 fs/nfsd/nfs4acl.c mask |= NFS4_READ_MODE; mask 75 fs/nfsd/nfs4acl.c mask |= NFS4_WRITE_MODE; mask 77 fs/nfsd/nfs4acl.c mask |= NFS4_ACE_DELETE_CHILD; mask 79 fs/nfsd/nfs4acl.c mask |= NFS4_EXECUTE_MODE; mask 80 fs/nfsd/nfs4acl.c return mask; mask 86 fs/nfsd/nfs4acl.c u32 mask = 0; mask 89 fs/nfsd/nfs4acl.c mask |= NFS4_READ_MODE; mask 91 fs/nfsd/nfs4acl.c mask |= NFS4_WRITE_MODE; mask 93 fs/nfsd/nfs4acl.c mask |= NFS4_ACE_DELETE_CHILD; mask 95 fs/nfsd/nfs4acl.c mask |= NFS4_EXECUTE_MODE; mask 96 fs/nfsd/nfs4acl.c return mask; mask 185 fs/nfsd/nfs4acl.c unsigned short mask; mask 199 fs/nfsd/nfs4acl.c pas->mask = 07; mask 221 fs/nfsd/nfs4acl.c pas->mask = pa->e_perm; mask 226 fs/nfsd/nfs4acl.c pas->users &= pas->mask; mask 227 fs/nfsd/nfs4acl.c pas->group &= pas->mask; mask 228 fs/nfsd/nfs4acl.c pas->groups &= pas->mask; mask 274 fs/nfsd/nfs4acl.c deny = ~(pa->e_perm & pas.mask); mask 287 fs/nfsd/nfs4acl.c ace->access_mask = mask_from_posix(pa->e_perm & pas.mask, mask 314 fs/nfsd/nfs4acl.c ace->access_mask = mask_from_posix(pa->e_perm & pas.mask, mask 339 fs/nfsd/nfs4acl.c deny = ~(pa->e_perm & pas.mask); mask 449 fs/nfsd/nfs4acl.c struct posix_ace_state mask; /* Deny unused in this case */ mask 487 fs/nfsd/nfs4acl.c state->mask.allow |= astate->allow; mask 549 fs/nfsd/nfs4acl.c low_mode_from_nfs4(state->mask.allow, &pace->e_perm, flags); mask 559 fs/nfsd/nfs4acl.c static inline void allow_bits(struct posix_ace_state *astate, u32 mask) mask 562 fs/nfsd/nfs4acl.c astate->allow |= mask & ~astate->deny; mask 565 fs/nfsd/nfs4acl.c static inline void deny_bits(struct posix_ace_state *astate, u32 mask) mask 568 fs/nfsd/nfs4acl.c astate->deny |= mask & ~astate->allow; mask 605 fs/nfsd/nfs4acl.c static void deny_bits_array(struct posix_ace_state_array *a, u32 mask) mask 610 fs/nfsd/nfs4acl.c deny_bits(&a->aces[i].perms, mask); mask 613 fs/nfsd/nfs4acl.c static void allow_bits_array(struct posix_ace_state_array *a, u32 mask) mask 618 fs/nfsd/nfs4acl.c allow_bits(&a->aces[i].perms, mask); mask 624 fs/nfsd/nfs4acl.c u32 mask = ace->access_mask; mask 632 fs/nfsd/nfs4acl.c allow_bits(&state->owner, mask); mask 634 fs/nfsd/nfs4acl.c deny_bits(&state->owner, mask); mask 640 fs/nfsd/nfs4acl.c allow_bits(&state->users->aces[i].perms, mask); mask 642 fs/nfsd/nfs4acl.c deny_bits(&state->users->aces[i].perms, mask); mask 643 fs/nfsd/nfs4acl.c mask = state->users->aces[i].perms.deny; mask 644 fs/nfsd/nfs4acl.c deny_bits(&state->owner, mask); mask 649 fs/nfsd/nfs4acl.c allow_bits(&state->group, mask); mask 651 fs/nfsd/nfs4acl.c deny_bits(&state->group, mask); mask 652 fs/nfsd/nfs4acl.c mask = state->group.deny; mask 653 fs/nfsd/nfs4acl.c deny_bits(&state->owner, mask); mask 654 fs/nfsd/nfs4acl.c deny_bits(&state->everyone, mask); mask 655 fs/nfsd/nfs4acl.c deny_bits_array(state->users, mask); mask 656 fs/nfsd/nfs4acl.c deny_bits_array(state->groups, mask); mask 662 fs/nfsd/nfs4acl.c allow_bits(&state->groups->aces[i].perms, mask); mask 664 fs/nfsd/nfs4acl.c deny_bits(&state->groups->aces[i].perms, mask); mask 665 fs/nfsd/nfs4acl.c mask = state->groups->aces[i].perms.deny; mask 666 fs/nfsd/nfs4acl.c deny_bits(&state->owner, mask); mask 667 fs/nfsd/nfs4acl.c deny_bits(&state->group, mask); mask 668 fs/nfsd/nfs4acl.c deny_bits(&state->everyone, mask); mask 669 fs/nfsd/nfs4acl.c deny_bits_array(state->users, mask); mask 670 fs/nfsd/nfs4acl.c deny_bits_array(state->groups, mask); mask 675 fs/nfsd/nfs4acl.c allow_bits(&state->owner, mask); mask 676 fs/nfsd/nfs4acl.c allow_bits(&state->group, mask); mask 677 fs/nfsd/nfs4acl.c allow_bits(&state->other, mask); mask 678 fs/nfsd/nfs4acl.c allow_bits(&state->everyone, mask); mask 679 fs/nfsd/nfs4acl.c allow_bits_array(state->users, mask); mask 680 fs/nfsd/nfs4acl.c allow_bits_array(state->groups, mask); mask 682 fs/nfsd/nfs4acl.c deny_bits(&state->owner, mask); mask 683 fs/nfsd/nfs4acl.c deny_bits(&state->group, mask); mask 684 fs/nfsd/nfs4acl.c deny_bits(&state->other, mask); mask 685 fs/nfsd/nfs4acl.c deny_bits(&state->everyone, mask); mask 686 fs/nfsd/nfs4acl.c deny_bits_array(state->users, mask); mask 687 fs/nfsd/nfs4acl.c deny_bits_array(state->groups, mask); mask 1127 fs/nfsd/nfs4state.c unsigned char mask = 1 << access; mask 1130 fs/nfsd/nfs4state.c stp->st_access_bmap |= mask; mask 1137 fs/nfsd/nfs4state.c unsigned char mask = 1 << access; mask 1140 fs/nfsd/nfs4state.c stp->st_access_bmap &= ~mask; mask 1147 fs/nfsd/nfs4state.c unsigned char mask = 1 << access; mask 1149 fs/nfsd/nfs4state.c return (bool)(stp->st_access_bmap & mask); mask 1156 fs/nfsd/nfs4state.c unsigned char mask = 1 << deny; mask 1159 fs/nfsd/nfs4state.c stp->st_deny_bmap |= mask; mask 1166 fs/nfsd/nfs4state.c unsigned char mask = 1 << deny; mask 1169 fs/nfsd/nfs4state.c stp->st_deny_bmap &= ~mask; mask 1176 fs/nfsd/nfs4state.c unsigned char mask = 1 << deny; mask 1178 fs/nfsd/nfs4state.c return (bool)(stp->st_deny_bmap & mask); mask 289 fs/nfsd/trace.h TP_PROTO(struct inode *inode, u32 mask), mask 290 fs/nfsd/trace.h TP_ARGS(inode, mask), mask 295 fs/nfsd/trace.h __field(u32, mask) mask 301 fs/nfsd/trace.h __entry->mask = mask; mask 304 fs/nfsd/trace.h __entry->nlink, __entry->mode, __entry->mask) mask 113 fs/nfsd/xdr3.h int mask; mask 119 fs/nfsd/xdr3.h int mask; mask 231 fs/nfsd/xdr3.h int mask; mask 854 fs/nilfs2/inode.c int nilfs_permission(struct inode *inode, int mask) mask 858 fs/nilfs2/inode.c if ((mask & MAY_WRITE) && root && mask 862 fs/nilfs2/inode.c return generic_permission(inode, mask); mask 272 fs/nilfs2/nilfs.h int nilfs_permission(struct inode *inode, int mask); mask 200 fs/nilfs2/page.c unsigned long mask = NILFS_BUFFER_INHERENT_BITS; mask 209 fs/nilfs2/page.c mask |= BIT(BH_Dirty); mask 215 fs/nilfs2/page.c dbh->b_state = sbh->b_state & mask; mask 220 fs/nilfs2/the_nilfs.h #define nilfs_write_opt(nilfs, mask, opt) \ mask 222 fs/nilfs2/the_nilfs.h (((nilfs)->ns_mount_opt & ~NILFS_MOUNT_##mask) | \ mask 58 fs/notify/dnotify/dnotify.c if (fsn_mark->mask == new_mask) mask 60 fs/notify/dnotify/dnotify.c fsn_mark->mask = new_mask; mask 75 fs/notify/dnotify/dnotify.c u32 mask, const void *data, int data_type, mask 84 fs/notify/dnotify/dnotify.c __u32 test_mask = mask & ~FS_EVENT_ON_CHILD; mask 219 fs/notify/dnotify/dnotify.c fl_owner_t id, int fd, struct file *filp, __u32 mask) mask 228 fs/notify/dnotify/dnotify.c odn->dn_mask |= mask; mask 234 fs/notify/dnotify/dnotify.c dn->dn_mask = mask; mask 258 fs/notify/dnotify/dnotify.c __u32 mask; mask 287 fs/notify/dnotify/dnotify.c mask = convert_arg(arg); mask 289 fs/notify/dnotify/dnotify.c error = security_path_notify(&filp->f_path, mask, mask 311 fs/notify/dnotify/dnotify.c new_fsn_mark->mask = mask; mask 359 fs/notify/dnotify/dnotify.c error = attach_dn(dn, dn_mark, id, fd, filp, mask); mask 45 fs/notify/fanotify/fanotify.c return (old->mask & FS_ISDIR) == (new->mask & FS_ISDIR) && mask 67 fs/notify/fanotify/fanotify.c if (fanotify_is_perm_event(new->mask)) mask 72 fs/notify/fanotify/fanotify.c FANOTIFY_E(test_event)->mask |= new->mask; mask 182 fs/notify/fanotify/fanotify.c if (event_mask & FS_ISDIR && !(mark->mask & FS_ISDIR)) mask 191 fs/notify/fanotify/fanotify.c !(mark->mask & FS_EVENT_ON_CHILD))) mask 194 fs/notify/fanotify/fanotify.c marks_mask |= mark->mask; mask 286 fs/notify/fanotify/fanotify.c struct inode *inode, u32 mask, mask 292 fs/notify/fanotify/fanotify.c struct inode *id = fanotify_fid_inode(inode, mask, data, data_type); mask 308 fs/notify/fanotify/fanotify.c if (fanotify_is_perm_event(mask)) { mask 329 fs/notify/fanotify/fanotify.c event->mask = mask; mask 387 fs/notify/fanotify/fanotify.c u32 mask, const void *data, int data_type, mask 418 fs/notify/fanotify/fanotify.c mask = fanotify_group_event_mask(group, iter_info, mask, data, mask 420 fs/notify/fanotify/fanotify.c if (!mask) mask 424 fs/notify/fanotify/fanotify.c mask); mask 426 fs/notify/fanotify/fanotify.c if (fanotify_is_perm_event(mask)) { mask 442 fs/notify/fanotify/fanotify.c event = fanotify_alloc_event(group, inode, mask, data, data_type, mask 450 fs/notify/fanotify/fanotify.c if (!fanotify_is_perm_event(mask)) mask 459 fs/notify/fanotify/fanotify.c BUG_ON(ret == 1 && mask & FANOTIFY_PERM_EVENTS); mask 464 fs/notify/fanotify/fanotify.c } else if (fanotify_is_perm_event(mask)) { mask 469 fs/notify/fanotify/fanotify.c if (fanotify_is_perm_event(mask)) mask 494 fs/notify/fanotify/fanotify.c if (fanotify_is_perm_event(event->mask)) { mask 63 fs/notify/fanotify/fanotify.h u32 mask; mask 131 fs/notify/fanotify/fanotify.h static inline bool fanotify_is_perm_event(u32 mask) mask 134 fs/notify/fanotify/fanotify.h mask & FANOTIFY_PERM_EVENTS; mask 143 fs/notify/fanotify/fanotify.h struct inode *inode, u32 mask, mask 92 fs/notify/fanotify/fanotify_user.c if (fanotify_is_perm_event(FANOTIFY_E(fsn_event)->mask)) mask 275 fs/notify/fanotify/fanotify_user.c metadata.mask = event->mask & FANOTIFY_OUTGOING_EVENTS; mask 298 fs/notify/fanotify/fanotify_user.c if (fanotify_is_perm_event(event->mask)) mask 387 fs/notify/fanotify/fanotify_user.c if (!fanotify_is_perm_event(FANOTIFY_E(kevent)->mask)) { mask 473 fs/notify/fanotify/fanotify_user.c if (!(FANOTIFY_E(fsn_event)->mask & FANOTIFY_PERM_EVENTS)) { mask 531 fs/notify/fanotify/fanotify_user.c struct path *path, unsigned int flags, __u64 mask, mask 576 fs/notify/fanotify/fanotify_user.c ret = security_path_notify(path, mask, obj_type); mask 585 fs/notify/fanotify/fanotify_user.c __u32 mask, mask 593 fs/notify/fanotify/fanotify_user.c oldmask = fsn_mark->mask; mask 594 fs/notify/fanotify/fanotify_user.c fsn_mark->mask &= ~mask; mask 596 fs/notify/fanotify/fanotify_user.c fsn_mark->ignored_mask &= ~mask; mask 598 fs/notify/fanotify/fanotify_user.c *destroy = !(fsn_mark->mask | fsn_mark->ignored_mask); mask 601 fs/notify/fanotify/fanotify_user.c return mask & oldmask; mask 605 fs/notify/fanotify/fanotify_user.c fsnotify_connp_t *connp, __u32 mask, mask 619 fs/notify/fanotify/fanotify_user.c removed = fanotify_mark_remove_from_mask(fsn_mark, mask, flags, mask 635 fs/notify/fanotify/fanotify_user.c struct vfsmount *mnt, __u32 mask, mask 639 fs/notify/fanotify/fanotify_user.c mask, flags); mask 643 fs/notify/fanotify/fanotify_user.c struct super_block *sb, __u32 mask, mask 646 fs/notify/fanotify/fanotify_user.c return fanotify_remove_mark(group, &sb->s_fsnotify_marks, mask, flags); mask 650 fs/notify/fanotify/fanotify_user.c struct inode *inode, __u32 mask, mask 653 fs/notify/fanotify/fanotify_user.c return fanotify_remove_mark(group, &inode->i_fsnotify_marks, mask, mask 658 fs/notify/fanotify/fanotify_user.c __u32 mask, mask 665 fs/notify/fanotify/fanotify_user.c oldmask = fsn_mark->mask; mask 666 fs/notify/fanotify/fanotify_user.c fsn_mark->mask |= mask; mask 668 fs/notify/fanotify/fanotify_user.c fsn_mark->ignored_mask |= mask; mask 674 fs/notify/fanotify/fanotify_user.c return mask & ~oldmask; mask 705 fs/notify/fanotify/fanotify_user.c __u32 mask, unsigned int flags, mask 720 fs/notify/fanotify/fanotify_user.c added = fanotify_mark_add_to_mask(fsn_mark, mask, flags); mask 730 fs/notify/fanotify/fanotify_user.c struct vfsmount *mnt, __u32 mask, mask 734 fs/notify/fanotify/fanotify_user.c FSNOTIFY_OBJ_TYPE_VFSMOUNT, mask, flags, fsid); mask 738 fs/notify/fanotify/fanotify_user.c struct super_block *sb, __u32 mask, mask 742 fs/notify/fanotify/fanotify_user.c FSNOTIFY_OBJ_TYPE_SB, mask, flags, fsid); mask 746 fs/notify/fanotify/fanotify_user.c struct inode *inode, __u32 mask, mask 762 fs/notify/fanotify/fanotify_user.c FSNOTIFY_OBJ_TYPE_INODE, mask, flags, fsid); mask 931 fs/notify/fanotify/fanotify_user.c static int fanotify_events_supported(struct path *path, __u64 mask) mask 941 fs/notify/fanotify/fanotify_user.c if (mask & FANOTIFY_PERM_EVENTS && mask 947 fs/notify/fanotify/fanotify_user.c static int do_fanotify_mark(int fanotify_fd, unsigned int flags, __u64 mask, mask 962 fs/notify/fanotify/fanotify_user.c __func__, fanotify_fd, flags, dfd, pathname, mask); mask 965 fs/notify/fanotify/fanotify_user.c if (mask & ((__u64)0xffffffff << 32)) mask 988 fs/notify/fanotify/fanotify_user.c if (!mask) mask 1002 fs/notify/fanotify/fanotify_user.c if (mask & ~valid_mask) mask 1020 fs/notify/fanotify/fanotify_user.c if (mask & FANOTIFY_PERM_EVENTS && mask 1031 fs/notify/fanotify/fanotify_user.c if (mask & FANOTIFY_INODE_EVENTS && mask 1048 fs/notify/fanotify/fanotify_user.c (mask & ALL_FSNOTIFY_EVENTS), obj_type); mask 1053 fs/notify/fanotify/fanotify_user.c ret = fanotify_events_supported(&path, mask); mask 1076 fs/notify/fanotify/fanotify_user.c ret = fanotify_add_vfsmount_mark(group, mnt, mask, mask 1079 fs/notify/fanotify/fanotify_user.c ret = fanotify_add_sb_mark(group, mnt->mnt_sb, mask, mask 1082 fs/notify/fanotify/fanotify_user.c ret = fanotify_add_inode_mark(group, inode, mask, mask 1087 fs/notify/fanotify/fanotify_user.c ret = fanotify_remove_vfsmount_mark(group, mnt, mask, mask 1090 fs/notify/fanotify/fanotify_user.c ret = fanotify_remove_sb_mark(group, mnt->mnt_sb, mask, mask 1093 fs/notify/fanotify/fanotify_user.c ret = fanotify_remove_inode_mark(group, inode, mask, mask 1108 fs/notify/fanotify/fanotify_user.c __u64, mask, int, dfd, mask 1111 fs/notify/fanotify/fanotify_user.c return do_fanotify_mark(fanotify_fd, flags, mask, dfd, pathname); mask 93 fs/notify/fdinfo.c u32 mask = mark->mask & IN_ALL_EVENTS; mask 96 fs/notify/fdinfo.c mask, mark->ignored_mask); mask 126 fs/notify/fdinfo.c mflags, mark->mask, mark->ignored_mask); mask 134 fs/notify/fdinfo.c mnt->mnt_id, mflags, mark->mask, mark->ignored_mask); mask 139 fs/notify/fdinfo.c sb->s_dev, mflags, mark->mask, mark->ignored_mask); mask 146 fs/notify/fsnotify.c int __fsnotify_parent(const struct path *path, struct dentry *dentry, __u32 mask) mask 163 fs/notify/fsnotify.c } else if (p_inode->i_fsnotify_mask & mask & ALL_FSNOTIFY_EVENTS) { mask 168 fs/notify/fsnotify.c mask |= FS_EVENT_ON_CHILD; mask 172 fs/notify/fsnotify.c ret = fsnotify(p_inode, mask, path, FSNOTIFY_EVENT_PATH, mask 175 fs/notify/fsnotify.c ret = fsnotify(p_inode, mask, dentry->d_inode, FSNOTIFY_EVENT_INODE, mask 187 fs/notify/fsnotify.c __u32 mask, const void *data, mask 193 fs/notify/fsnotify.c __u32 test_mask = (mask & ALL_FSNOTIFY_EVENTS); mask 203 fs/notify/fsnotify.c if (mask & FS_MODIFY) { mask 221 fs/notify/fsnotify.c marks_mask |= mark->mask; mask 228 fs/notify/fsnotify.c __func__, group, to_tell, mask, marks_mask, marks_ignored_mask, mask 234 fs/notify/fsnotify.c return group->ops->handle_event(group, to_tell, mask, data, data_is, mask 318 fs/notify/fsnotify.c int fsnotify(struct inode *to_tell, __u32 mask, const void *data, int data_is, mask 326 fs/notify/fsnotify.c __u32 test_mask = (mask & ALL_FSNOTIFY_EVENTS); mask 333 fs/notify/fsnotify.c if (mask & FS_EVENT_ON_CHILD) mask 351 fs/notify/fsnotify.c if (!(mask & FS_MODIFY) && mask 372 fs/notify/fsnotify.c ret = send_to_group(to_tell, mask, data, data_is, cookie, mask 375 fs/notify/fsnotify.c if (ret && (mask & ALL_FSNOTIFY_PERM_EVENTS)) mask 8 fs/notify/inotify/inotify.h u32 mask; mask 29 fs/notify/inotify/inotify.h u32 mask, const void *data, int data_type, mask 39 fs/notify/inotify/inotify_fsnotify.c if (old->mask & FS_IN_IGNORED) mask 41 fs/notify/inotify/inotify_fsnotify.c if ((old->mask == new->mask) && mask 60 fs/notify/inotify/inotify_fsnotify.c u32 mask, const void *data, int data_type, mask 75 fs/notify/inotify/inotify_fsnotify.c if ((inode_mark->mask & FS_EXCL_UNLINK) && mask 88 fs/notify/inotify/inotify_fsnotify.c mask); mask 117 fs/notify/inotify/inotify_fsnotify.c if (mask & (IN_MOVE_SELF | IN_DELETE_SELF)) mask 118 fs/notify/inotify/inotify_fsnotify.c mask &= ~IN_ISDIR; mask 122 fs/notify/inotify/inotify_fsnotify.c event->mask = mask; mask 135 fs/notify/inotify/inotify_fsnotify.c if (inode_mark->mask & IN_ONESHOT) mask 80 fs/notify/inotify/inotify_user.c __u32 mask; mask 86 fs/notify/inotify/inotify_user.c mask = (FS_IN_IGNORED | FS_EVENT_ON_CHILD | FS_UNMOUNT); mask 89 fs/notify/inotify/inotify_user.c mask |= (arg & (IN_ALL_EVENTS | IN_ONESHOT | IN_EXCL_UNLINK)); mask 91 fs/notify/inotify/inotify_user.c return mask; mask 94 fs/notify/inotify/inotify_user.c static inline u32 inotify_mask_to_arg(__u32 mask) mask 96 fs/notify/inotify/inotify_user.c return mask & (IN_ALL_EVENTS | IN_ISDIR | IN_UNMOUNT | IN_IGNORED | mask 182 fs/notify/inotify/inotify_user.c inotify_event.mask = inotify_mask_to_arg(event->mask); mask 336 fs/notify/inotify/inotify_user.c unsigned int flags, __u64 mask) mask 349 fs/notify/inotify/inotify_user.c error = security_path_notify(path, mask, mask 510 fs/notify/inotify/inotify_user.c __u32 mask; mask 515 fs/notify/inotify/inotify_user.c mask = inotify_arg_to_mask(arg); mask 528 fs/notify/inotify/inotify_user.c old_mask = fsn_mark->mask; mask 530 fs/notify/inotify/inotify_user.c fsn_mark->mask |= mask; mask 532 fs/notify/inotify/inotify_user.c fsn_mark->mask = mask; mask 533 fs/notify/inotify/inotify_user.c new_mask = fsn_mark->mask; mask 563 fs/notify/inotify/inotify_user.c __u32 mask; mask 568 fs/notify/inotify/inotify_user.c mask = inotify_arg_to_mask(arg); mask 575 fs/notify/inotify/inotify_user.c tmp_i_mark->fsn_mark.mask = mask; mask 639 fs/notify/inotify/inotify_user.c oevent->mask = FS_Q_OVERFLOW; mask 699 fs/notify/inotify/inotify_user.c u32, mask) mask 714 fs/notify/inotify/inotify_user.c if (unlikely(mask & ~ALL_INOTIFY_BITS)) mask 721 fs/notify/inotify/inotify_user.c if (unlikely(!(mask & ALL_INOTIFY_BITS))) mask 729 fs/notify/inotify/inotify_user.c if (unlikely((mask & IN_MASK_ADD) && (mask & IN_MASK_CREATE))) { mask 740 fs/notify/inotify/inotify_user.c if (!(mask & IN_DONT_FOLLOW)) mask 742 fs/notify/inotify/inotify_user.c if (mask & IN_ONLYDIR) mask 746 fs/notify/inotify/inotify_user.c (mask & IN_ALL_EVENTS)); mask 755 fs/notify/inotify/inotify_user.c ret = inotify_update_watch(group, inode, mask); mask 130 fs/notify/mark.c new_mask |= mark->mask; mask 663 fs/notify/mark.c if (mark->mask) mask 1572 fs/ntfs/layout.h /* 4*/ ACCESS_MASK mask; /* Access mask associated with the ACE. */ mask 1593 fs/ntfs/layout.h /* 4*/ ACCESS_MASK mask; /* Access mask associated with the ACE. */ mask 22 fs/ocfs2/cluster/masklog.c static ssize_t mlog_mask_show(u64 mask, char *buf) mask 26 fs/ocfs2/cluster/masklog.c if (__mlog_test_u64(mask, mlog_and_bits)) mask 28 fs/ocfs2/cluster/masklog.c else if (__mlog_test_u64(mask, mlog_not_bits)) mask 36 fs/ocfs2/cluster/masklog.c static ssize_t mlog_mask_store(u64 mask, const char *buf, size_t count) mask 39 fs/ocfs2/cluster/masklog.c __mlog_set_u64(mask, mlog_and_bits); mask 40 fs/ocfs2/cluster/masklog.c __mlog_clear_u64(mask, mlog_not_bits); mask 42 fs/ocfs2/cluster/masklog.c __mlog_set_u64(mask, mlog_not_bits); mask 43 fs/ocfs2/cluster/masklog.c __mlog_clear_u64(mask, mlog_and_bits); mask 45 fs/ocfs2/cluster/masklog.c __mlog_clear_u64(mask, mlog_not_bits); mask 46 fs/ocfs2/cluster/masklog.c __mlog_clear_u64(mask, mlog_and_bits); mask 53 fs/ocfs2/cluster/masklog.c void __mlog_printk(const u64 *mask, const char *func, int line, mask 61 fs/ocfs2/cluster/masklog.c if (!__mlog_test_u64(*mask, mlog_and_bits) || mask 62 fs/ocfs2/cluster/masklog.c __mlog_test_u64(*mask, mlog_not_bits)) mask 65 fs/ocfs2/cluster/masklog.c if (*mask & ML_ERROR) { mask 68 fs/ocfs2/cluster/masklog.c } else if (*mask & ML_NOTICE) { mask 89 fs/ocfs2/cluster/masklog.c u64 mask; mask 99 fs/ocfs2/cluster/masklog.c .mask = ML_##_name, \ mask 132 fs/ocfs2/cluster/masklog.c return mlog_mask_show(mlog_attr->mask, buf); mask 140 fs/ocfs2/cluster/masklog.c return mlog_mask_store(mlog_attr->mask, buf, count); mask 120 fs/ocfs2/cluster/masklog.h #define __mlog_test_u64(mask, bits) \ mask 121 fs/ocfs2/cluster/masklog.h ( (u32)(mask & 0xffffffff) & bits.words[0] || \ mask 122 fs/ocfs2/cluster/masklog.h ((u64)(mask) >> 32) & bits.words[1] ) mask 123 fs/ocfs2/cluster/masklog.h #define __mlog_set_u64(mask, bits) do { \ mask 124 fs/ocfs2/cluster/masklog.h bits.words[0] |= (u32)(mask & 0xffffffff); \ mask 125 fs/ocfs2/cluster/masklog.h bits.words[1] |= (u64)(mask) >> 32; \ mask 127 fs/ocfs2/cluster/masklog.h #define __mlog_clear_u64(mask, bits) do { \ mask 128 fs/ocfs2/cluster/masklog.h bits.words[0] &= ~((u32)(mask & 0xffffffff)); \ mask 129 fs/ocfs2/cluster/masklog.h bits.words[1] &= ~((u64)(mask) >> 32); \ mask 131 fs/ocfs2/cluster/masklog.h #define MLOG_BITS_RHS(mask) { \ mask 133 fs/ocfs2/cluster/masklog.h [0] = (u32)(mask & 0xffffffff), \ mask 134 fs/ocfs2/cluster/masklog.h [1] = (u64)(mask) >> 32, \ mask 140 fs/ocfs2/cluster/masklog.h #define __mlog_test_u64(mask, bits) ((mask) & bits.words[0]) mask 141 fs/ocfs2/cluster/masklog.h #define __mlog_set_u64(mask, bits) do { \ mask 142 fs/ocfs2/cluster/masklog.h bits.words[0] |= (mask); \ mask 144 fs/ocfs2/cluster/masklog.h #define __mlog_clear_u64(mask, bits) do { \ mask 145 fs/ocfs2/cluster/masklog.h bits.words[0] &= ~(mask); \ mask 147 fs/ocfs2/cluster/masklog.h #define MLOG_BITS_RHS(mask) { { (mask) } } mask 159 fs/ocfs2/cluster/masklog.h #define mlog(mask, fmt, ...) \ mask 161 fs/ocfs2/cluster/masklog.h u64 _m = MLOG_MASK_PREFIX | (mask); \ mask 167 fs/ocfs2/cluster/masklog.h #define mlog_ratelimited(mask, fmt, ...) \ mask 173 fs/ocfs2/cluster/masklog.h mlog(mask, fmt, ##__VA_ARGS__); \ mask 1401 fs/ocfs2/dlmglue.c unsigned long mask, mask 1409 fs/ocfs2/dlmglue.c mw->mw_mask = mask; mask 1333 fs/ocfs2/file.c int ocfs2_permission(struct inode *inode, int mask) mask 1338 fs/ocfs2/file.c if (mask & MAY_NOT_BLOCK) mask 1358 fs/ocfs2/file.c ret = generic_permission(inode, mask); mask 57 fs/ocfs2/file.h int ocfs2_permission(struct inode *inode, int mask); mask 81 fs/ocfs2/ioctl.c unsigned mask) mask 106 fs/ocfs2/ioctl.c flags = flags & mask; mask 107 fs/ocfs2/ioctl.c flags |= oldflags & ~mask; mask 60 fs/ocfs2/ocfs2_fs.h #define OCFS2_HAS_COMPAT_FEATURE(sb,mask) \ mask 61 fs/ocfs2/ocfs2_fs.h ( OCFS2_SB(sb)->s_feature_compat & (mask) ) mask 62 fs/ocfs2/ocfs2_fs.h #define OCFS2_HAS_RO_COMPAT_FEATURE(sb,mask) \ mask 63 fs/ocfs2/ocfs2_fs.h ( OCFS2_SB(sb)->s_feature_ro_compat & (mask) ) mask 64 fs/ocfs2/ocfs2_fs.h #define OCFS2_HAS_INCOMPAT_FEATURE(sb,mask) \ mask 65 fs/ocfs2/ocfs2_fs.h ( OCFS2_SB(sb)->s_feature_incompat & (mask) ) mask 66 fs/ocfs2/ocfs2_fs.h #define OCFS2_SET_COMPAT_FEATURE(sb,mask) \ mask 67 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_compat |= (mask) mask 68 fs/ocfs2/ocfs2_fs.h #define OCFS2_SET_RO_COMPAT_FEATURE(sb,mask) \ mask 69 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_ro_compat |= (mask) mask 70 fs/ocfs2/ocfs2_fs.h #define OCFS2_SET_INCOMPAT_FEATURE(sb,mask) \ mask 71 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_incompat |= (mask) mask 72 fs/ocfs2/ocfs2_fs.h #define OCFS2_CLEAR_COMPAT_FEATURE(sb,mask) \ mask 73 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_compat &= ~(mask) mask 74 fs/ocfs2/ocfs2_fs.h #define OCFS2_CLEAR_RO_COMPAT_FEATURE(sb,mask) \ mask 75 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_ro_compat &= ~(mask) mask 76 fs/ocfs2/ocfs2_fs.h #define OCFS2_CLEAR_INCOMPAT_FEATURE(sb,mask) \ mask 77 fs/ocfs2/ocfs2_fs.h OCFS2_SB(sb)->s_feature_incompat &= ~(mask) mask 910 fs/ocfs2/quota_global.c unsigned long mask = (1 << (DQ_LASTSET_B + QIF_ILIMITS_B)) | mask 930 fs/ocfs2/quota_global.c if (dquot->dq_flags & mask) mask 969 fs/orangefs/inode.c int orangefs_permission(struct inode *inode, int mask) mask 973 fs/orangefs/inode.c if (mask & MAY_NOT_BLOCK) mask 983 fs/orangefs/inode.c return generic_permission(inode, mask); mask 686 fs/orangefs/orangefs-debugfs.c static void debug_mask_to_string(void *mask, int type) mask 711 fs/orangefs/orangefs-debugfs.c if (check_amalgam_keyword(mask, type)) mask 717 fs/orangefs/orangefs-debugfs.c do_c_string(mask, i); mask 719 fs/orangefs/orangefs-debugfs.c do_k_string(mask, i); mask 741 fs/orangefs/orangefs-debugfs.c __u64 *mask = (__u64 *) k_mask; mask 746 fs/orangefs/orangefs-debugfs.c if (*mask & s_kmod_keyword_mask_map[index].mask_val) { mask 767 fs/orangefs/orangefs-debugfs.c struct client_debug_mask *mask = (struct client_debug_mask *) c_mask; mask 772 fs/orangefs/orangefs-debugfs.c if ((mask->mask1 & cdm_array[index].mask1) || mask 773 fs/orangefs/orangefs-debugfs.c (mask->mask2 & cdm_array[index].mask2)) { mask 806 fs/orangefs/orangefs-debugfs.c static int check_amalgam_keyword(void *mask, int type) mask 814 fs/orangefs/orangefs-debugfs.c c_mask = (struct client_debug_mask *) mask; mask 831 fs/orangefs/orangefs-debugfs.c k_mask = (__u64 *) mask; mask 849 fs/orangefs/orangefs-debugfs.c static void debug_string_to_mask(char *debug_string, void *mask, int type) mask 862 fs/orangefs/orangefs-debugfs.c c_mask = (struct client_debug_mask *)mask; mask 865 fs/orangefs/orangefs-debugfs.c k_mask = (__u64 *)mask; mask 371 fs/orangefs/orangefs-kernel.h int orangefs_permission(struct inode *inode, int mask); mask 482 fs/orangefs/orangefs-kernel.h sys_attr.mask = ORANGEFS_ATTR_SYS_ALL_SETABLE; \ mask 143 fs/orangefs/orangefs-utils.c attrs->mask = 0; mask 146 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_UID; mask 151 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_GID; mask 156 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_ATIME; mask 159 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_ATIME_SET; mask 163 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_MTIME; mask 166 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_MTIME_SET; mask 170 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_CTIME; mask 180 fs/orangefs/orangefs-utils.c attrs->mask |= ORANGEFS_ATTR_SYS_PERM; mask 270 fs/orangefs/orangefs-utils.c new_op->upcall.req.getattr.mask = ORANGEFS_ATTR_SYS_ALL_NOHINT; mask 272 fs/orangefs/orangefs-utils.c new_op->upcall.req.getattr.mask = mask 397 fs/orangefs/orangefs-utils.c new_op->upcall.req.getattr.mask = ORANGEFS_ATTR_SYS_TYPE | mask 434 fs/orangefs/orangefs-utils.c if (!new_op->upcall.req.setattr.attributes.mask) { mask 261 fs/orangefs/protocol.h __u32 mask; mask 356 fs/orangefs/protocol.h #define gossip_debug(mask, fmt, ...) \ mask 358 fs/orangefs/protocol.h if (orangefs_gossip_debug_mask & (mask)) \ mask 49 fs/orangefs/upcall.h __u32 mask; mask 80 fs/orangefs/upcall.h __u32 mask; mask 271 fs/overlayfs/inode.c int ovl_permission(struct inode *inode, int mask) mask 280 fs/overlayfs/inode.c WARN_ON(!(mask & MAY_NOT_BLOCK)); mask 288 fs/overlayfs/inode.c err = generic_permission(inode, mask); mask 294 fs/overlayfs/inode.c !special_file(realinode->i_mode) && mask & MAY_WRITE) { mask 295 fs/overlayfs/inode.c mask &= ~(MAY_WRITE | MAY_APPEND); mask 297 fs/overlayfs/inode.c mask |= MAY_READ; mask 299 fs/overlayfs/inode.c err = inode_permission(realinode, mask); mask 355 fs/overlayfs/overlayfs.h int ovl_permission(struct inode *inode, int mask); mask 394 fs/overlayfs/overlayfs.h unsigned int mask = S_SYNC | S_IMMUTABLE | S_APPEND | S_NOATIME; mask 396 fs/overlayfs/overlayfs.h inode_set_flags(to, from->i_flags & mask, mask); mask 542 fs/pipe.c __poll_t mask; mask 550 fs/pipe.c mask = 0; mask 552 fs/pipe.c mask = (nrbufs > 0) ? EPOLLIN | EPOLLRDNORM : 0; mask 554 fs/pipe.c mask |= EPOLLHUP; mask 558 fs/pipe.c mask |= (nrbufs < pipe->buffers) ? EPOLLOUT | EPOLLWRNORM : 0; mask 564 fs/pipe.c mask |= EPOLLERR; mask 567 fs/pipe.c return mask; mask 364 fs/posix_acl.c goto mask; mask 370 fs/posix_acl.c goto mask; mask 377 fs/posix_acl.c goto mask; mask 393 fs/posix_acl.c mask: mask 710 fs/proc/base.c static int proc_pid_permission(struct inode *inode, int mask) mask 735 fs/proc/base.c return generic_permission(inode, mask); mask 2727 fs/proc/base.c unsigned long mask; mask 2743 fs/proc/base.c for (i = 0, mask = 1; i < MMF_DUMP_FILTER_BITS; i++, mask <<= 1) { mask 2744 fs/proc/base.c if (val & mask) mask 3371 fs/proc/base.c static int proc_tid_comm_permission(struct inode *inode, int mask) mask 3382 fs/proc/base.c if (likely(is_same_tgroup && !(mask & MAY_EXEC))) { mask 3390 fs/proc/base.c return generic_permission(inode, mask); mask 297 fs/proc/fd.c int proc_fd_permission(struct inode *inode, int mask) mask 302 fs/proc/fd.c rv = generic_permission(inode, mask); mask 13 fs/proc/fd.h extern int proc_fd_permission(struct inode *inode, int mask); mask 807 fs/proc/proc_sysctl.c static int proc_sys_permission(struct inode *inode, int mask) mask 818 fs/proc/proc_sysctl.c if ((mask & MAY_EXEC) && S_ISREG(inode->i_mode)) mask 827 fs/proc/proc_sysctl.c error = mask & MAY_WRITE ? -EACCES : 0; mask 829 fs/proc/proc_sysctl.c error = sysctl_perm(head, table, mask & ~MAY_NOT_BLOCK); mask 34 fs/proc/root.c unsigned int mask; mask 81 fs/proc/root.c ctx->mask |= 1 << opt; mask 92 fs/proc/root.c if (ctx->mask & (1 << Opt_gid)) mask 94 fs/proc/root.c if (ctx->mask & (1 << Opt_hidepid)) mask 123 fs/qnx6/inode.c u32 mask = (1 << ptrbits) - 1; mask 144 fs/qnx6/inode.c levelptr = (no >> bitdelta) & mask; mask 944 fs/reiserfs/xattr.c int reiserfs_permission(struct inode *inode, int mask) mask 953 fs/reiserfs/xattr.c return generic_permission(inode, mask); mask 19 fs/reiserfs/xattr.h int reiserfs_permission(struct inode *inode, int mask); mask 515 fs/select.c __poll_t mask; mask 534 fs/select.c mask = vfs_poll(f.file, wait); mask 537 fs/select.c if ((mask & POLLIN_SET) && (in & bit)) { mask 542 fs/select.c if ((mask & POLLOUT_SET) && (out & bit)) { mask 547 fs/select.c if ((mask & POLLEX_SET) && (ex & bit)) { mask 561 fs/select.c } else if (busy_flag & mask) mask 846 fs/select.c __poll_t mask = 0, filter; mask 851 fs/select.c mask = EPOLLNVAL; mask 859 fs/select.c mask = vfs_poll(f.file, pwait); mask 860 fs/select.c if (mask & busy_flag) mask 862 fs/select.c mask &= filter; /* Mask out unneeded events. */ mask 867 fs/select.c pollfd->revents = mangle_poll(mask); mask 868 fs/select.c return mask; mask 263 fs/signalfd.c static int do_signalfd4(int ufd, sigset_t *mask, int flags) mask 274 fs/signalfd.c sigdelsetmask(mask, sigmask(SIGKILL) | sigmask(SIGSTOP)); mask 275 fs/signalfd.c signotset(mask); mask 282 fs/signalfd.c ctx->sigmask = *mask; mask 302 fs/signalfd.c ctx->sigmask = *mask; mask 315 fs/signalfd.c sigset_t mask; mask 318 fs/signalfd.c copy_from_user(&mask, user_mask, sizeof(mask))) mask 320 fs/signalfd.c return do_signalfd4(ufd, &mask, flags); mask 326 fs/signalfd.c sigset_t mask; mask 329 fs/signalfd.c copy_from_user(&mask, user_mask, sizeof(mask))) mask 331 fs/signalfd.c return do_signalfd4(ufd, &mask, 0); mask 339 fs/signalfd.c sigset_t mask; mask 343 fs/signalfd.c if (get_compat_sigset(&mask, user_mask)) mask 345 fs/signalfd.c return do_signalfd4(ufd, &mask, flags); mask 387 fs/squashfs/file.c int i, mask = (1 << (msblk->block_log - PAGE_SHIFT)) - 1; mask 388 fs/squashfs/file.c int start_index = page->index & ~mask, end_index = start_index | mask; mask 33 fs/squashfs/file_direct.c int mask = (1 << (msblk->block_log - PAGE_SHIFT)) - 1; mask 34 fs/squashfs/file_direct.c int start_index = target_page->index & ~mask; mask 35 fs/squashfs/file_direct.c int end_index = start_index | mask; mask 573 fs/stat.c unsigned int, mask, mask 579 fs/stat.c if (mask & STATX__RESERVED) mask 584 fs/stat.c error = vfs_statx(dfd, filename, flags, &stat, mask); mask 245 fs/ufs/balloc.c const unsigned mask = blks_per_page - 1; mask 263 fs/ufs/balloc.c for (i = beg; i < end; i = (i | mask) + 1) { mask 281 fs/ufs/balloc.c pos = i & mask; mask 287 fs/ufs/balloc.c lblock = end & mask; mask 763 fs/ufs/balloc.c unsigned char *table, unsigned char mask) mask 778 fs/ufs/balloc.c while ((table[*cp++] & mask) == 0 && --rest) mask 811 fs/ufs/balloc.c unsigned pos, want, blockmap, mask, end; mask 852 fs/ufs/balloc.c mask = mask_arr[count]; mask 855 fs/ufs/balloc.c if ((blockmap & mask) == want) { mask 860 fs/ufs/balloc.c mask <<= 1; mask 409 fs/ufs/dir.c unsigned offset, unsigned mask) mask 412 fs/ufs/dir.c struct ufs_dir_entry *p = (struct ufs_dir_entry*)(base + (offset&mask)); mask 129 fs/ufs/inode.c u64 mask = (u64) uspi->s_apbmask>>uspi->s_fpbshift; mask 138 fs/ufs/inode.c (unsigned long long)mask); mask 162 fs/ufs/inode.c ptr = (__fs32 *)bh->b_data + (n & mask); mask 186 fs/ufs/inode.c ptr = (__fs64 *)bh->b_data + (n & mask); mask 472 fs/ufs/util.h u8 mask; mask 477 fs/ufs/util.h mask = 0x0f << ((block & 0x01) << 2); mask 478 fs/ufs/util.h return (*ubh_get_addr (ubh, begin + (block >> 1)) & mask) == mask; mask 480 fs/ufs/util.h mask = 0x03 << ((block & 0x03) << 1); mask 481 fs/ufs/util.h return (*ubh_get_addr (ubh, begin + (block >> 2)) & mask) == mask; mask 483 fs/ufs/util.h mask = 0x01 << (block & 0x07); mask 484 fs/ufs/util.h return (*ubh_get_addr (ubh, begin + (block >> 3)) & mask) == mask; mask 2712 fs/unicode/mkutf8data.c int mask; mask 2728 fs/unicode/mkutf8data.c mask = 1 << (*trie & BITNUM); mask 2729 fs/unicode/mkutf8data.c if (*s & mask) { mask 325 fs/unicode/utf8-norm.c int mask; mask 342 fs/unicode/utf8-norm.c mask = 1 << (*trie & BITNUM); mask 343 fs/unicode/utf8-norm.c if (*s & mask) { mask 86 fs/xattr.c xattr_permission(struct inode *inode, const char *name, int mask) mask 92 fs/xattr.c if (mask & MAY_WRITE) { mask 117 fs/xattr.c return (mask & MAY_WRITE) ? -EPERM : -ENODATA; mask 128 fs/xattr.c return (mask & MAY_WRITE) ? -EPERM : -ENODATA; mask 130 fs/xattr.c (mask & MAY_WRITE) && !inode_owner_or_capable(inode)) mask 134 fs/xattr.c return inode_permission(inode, mask); mask 102 fs/xfs/libxfs/xfs_health.h void xfs_fs_mark_sick(struct xfs_mount *mp, unsigned int mask); mask 103 fs/xfs/libxfs/xfs_health.h void xfs_fs_mark_healthy(struct xfs_mount *mp, unsigned int mask); mask 107 fs/xfs/libxfs/xfs_health.h void xfs_rt_mark_sick(struct xfs_mount *mp, unsigned int mask); mask 108 fs/xfs/libxfs/xfs_health.h void xfs_rt_mark_healthy(struct xfs_mount *mp, unsigned int mask); mask 112 fs/xfs/libxfs/xfs_health.h void xfs_ag_mark_sick(struct xfs_perag *pag, unsigned int mask); mask 113 fs/xfs/libxfs/xfs_health.h void xfs_ag_mark_healthy(struct xfs_perag *pag, unsigned int mask); mask 117 fs/xfs/libxfs/xfs_health.h void xfs_inode_mark_sick(struct xfs_inode *ip, unsigned int mask); mask 118 fs/xfs/libxfs/xfs_health.h void xfs_inode_mark_healthy(struct xfs_inode *ip, unsigned int mask); mask 127 fs/xfs/libxfs/xfs_health.h xfs_fs_has_sickness(struct xfs_mount *mp, unsigned int mask) mask 132 fs/xfs/libxfs/xfs_health.h return sick & mask; mask 136 fs/xfs/libxfs/xfs_health.h xfs_rt_has_sickness(struct xfs_mount *mp, unsigned int mask) mask 141 fs/xfs/libxfs/xfs_health.h return sick & mask; mask 145 fs/xfs/libxfs/xfs_health.h xfs_ag_has_sickness(struct xfs_perag *pag, unsigned int mask) mask 150 fs/xfs/libxfs/xfs_health.h return sick & mask; mask 154 fs/xfs/libxfs/xfs_health.h xfs_inode_has_sickness(struct xfs_inode *ip, unsigned int mask) mask 159 fs/xfs/libxfs/xfs_health.h return sick & mask; mask 110 fs/xfs/libxfs/xfs_rtbitmap.c xfs_rtword_t mask; /* mask of relevant bits for value */ mask 146 fs/xfs/libxfs/xfs_rtbitmap.c mask = (((xfs_rtword_t)1 << (bit - firstbit + 1)) - 1) << mask 152 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ want) & mask)) { mask 241 fs/xfs/libxfs/xfs_rtbitmap.c mask = (((xfs_rtword_t)1 << (len - i)) - 1) << firstbit; mask 245 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ want) & mask)) { mask 285 fs/xfs/libxfs/xfs_rtbitmap.c xfs_rtword_t mask; /* mask of relevant bits for value */ mask 321 fs/xfs/libxfs/xfs_rtbitmap.c mask = (((xfs_rtword_t)1 << (lastbit - bit)) - 1) << bit; mask 326 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ want) & mask)) { mask 411 fs/xfs/libxfs/xfs_rtbitmap.c mask = ((xfs_rtword_t)1 << lastbit) - 1; mask 415 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ want) & mask)) { mask 548 fs/xfs/libxfs/xfs_rtbitmap.c xfs_rtword_t mask; /* mask o frelevant bits for value */ mask 582 fs/xfs/libxfs/xfs_rtbitmap.c mask = (((xfs_rtword_t)1 << (lastbit - bit)) - 1) << bit; mask 587 fs/xfs/libxfs/xfs_rtbitmap.c *b |= mask; mask 589 fs/xfs/libxfs/xfs_rtbitmap.c *b &= ~mask; mask 664 fs/xfs/libxfs/xfs_rtbitmap.c mask = ((xfs_rtword_t)1 << lastbit) - 1; mask 669 fs/xfs/libxfs/xfs_rtbitmap.c *b |= mask; mask 671 fs/xfs/libxfs/xfs_rtbitmap.c *b &= ~mask; mask 781 fs/xfs/libxfs/xfs_rtbitmap.c xfs_rtword_t mask; /* mask of relevant bits for value */ mask 819 fs/xfs/libxfs/xfs_rtbitmap.c mask = (((xfs_rtword_t)1 << (lastbit - bit)) - 1) << bit; mask 823 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ val) & mask)) { mask 910 fs/xfs/libxfs/xfs_rtbitmap.c mask = ((xfs_rtword_t)1 << lastbit) - 1; mask 914 fs/xfs/libxfs/xfs_rtbitmap.c if ((wdiff = (*b ^ val) & mask)) { mask 178 fs/xfs/scrub/health.c unsigned int mask = 0; mask 191 fs/xfs/scrub/health.c mask = XFS_SICK_AG_BNOBT; mask 196 fs/xfs/scrub/health.c mask = XFS_SICK_AG_CNTBT; mask 201 fs/xfs/scrub/health.c mask = XFS_SICK_AG_INOBT; mask 206 fs/xfs/scrub/health.c mask = XFS_SICK_AG_FINOBT; mask 211 fs/xfs/scrub/health.c mask = XFS_SICK_AG_RMAPBT; mask 216 fs/xfs/scrub/health.c mask = XFS_SICK_AG_REFCNTBT; mask 223 fs/xfs/scrub/health.c if (xfs_ag_has_sickness(pag, mask)) { mask 806 fs/xfs/xfs_buf_item.c uint mask; mask 841 fs/xfs/xfs_buf_item.c mask = ((1U << (end_bit - bit)) - 1) << bit; mask 842 fs/xfs/xfs_buf_item.c *wordp |= mask; mask 864 fs/xfs/xfs_buf_item.c mask = (1U << end_bit) - 1; mask 865 fs/xfs/xfs_buf_item.c *wordp |= mask; mask 96 fs/xfs/xfs_health.c unsigned int mask) mask 98 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_FS_PRIMARY)); mask 99 fs/xfs/xfs_health.c trace_xfs_fs_mark_sick(mp, mask); mask 102 fs/xfs/xfs_health.c mp->m_fs_sick |= mask; mask 103 fs/xfs/xfs_health.c mp->m_fs_checked |= mask; mask 111 fs/xfs/xfs_health.c unsigned int mask) mask 113 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_FS_PRIMARY)); mask 114 fs/xfs/xfs_health.c trace_xfs_fs_mark_healthy(mp, mask); mask 117 fs/xfs/xfs_health.c mp->m_fs_sick &= ~mask; mask 118 fs/xfs/xfs_health.c mp->m_fs_checked |= mask; mask 139 fs/xfs/xfs_health.c unsigned int mask) mask 141 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_RT_PRIMARY)); mask 142 fs/xfs/xfs_health.c trace_xfs_rt_mark_sick(mp, mask); mask 145 fs/xfs/xfs_health.c mp->m_rt_sick |= mask; mask 146 fs/xfs/xfs_health.c mp->m_rt_checked |= mask; mask 154 fs/xfs/xfs_health.c unsigned int mask) mask 156 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_RT_PRIMARY)); mask 157 fs/xfs/xfs_health.c trace_xfs_rt_mark_healthy(mp, mask); mask 160 fs/xfs/xfs_health.c mp->m_rt_sick &= ~mask; mask 161 fs/xfs/xfs_health.c mp->m_rt_checked |= mask; mask 182 fs/xfs/xfs_health.c unsigned int mask) mask 184 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_AG_PRIMARY)); mask 185 fs/xfs/xfs_health.c trace_xfs_ag_mark_sick(pag->pag_mount, pag->pag_agno, mask); mask 188 fs/xfs/xfs_health.c pag->pag_sick |= mask; mask 189 fs/xfs/xfs_health.c pag->pag_checked |= mask; mask 197 fs/xfs/xfs_health.c unsigned int mask) mask 199 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_AG_PRIMARY)); mask 200 fs/xfs/xfs_health.c trace_xfs_ag_mark_healthy(pag->pag_mount, pag->pag_agno, mask); mask 203 fs/xfs/xfs_health.c pag->pag_sick &= ~mask; mask 204 fs/xfs/xfs_health.c pag->pag_checked |= mask; mask 225 fs/xfs/xfs_health.c unsigned int mask) mask 227 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_INO_PRIMARY)); mask 228 fs/xfs/xfs_health.c trace_xfs_inode_mark_sick(ip, mask); mask 231 fs/xfs/xfs_health.c ip->i_sick |= mask; mask 232 fs/xfs/xfs_health.c ip->i_checked |= mask; mask 240 fs/xfs/xfs_health.c unsigned int mask) mask 242 fs/xfs/xfs_health.c ASSERT(!(mask & ~XFS_SICK_INO_PRIMARY)); mask 243 fs/xfs/xfs_health.c trace_xfs_inode_mark_healthy(ip, mask); mask 246 fs/xfs/xfs_health.c ip->i_sick &= ~mask; mask 247 fs/xfs/xfs_health.c ip->i_checked |= mask; mask 3470 fs/xfs/xfs_inode.c unsigned long first_index, mask; mask 3486 fs/xfs/xfs_inode.c mask = ~(igeo->inodes_per_cluster - 1); mask 3487 fs/xfs/xfs_inode.c first_index = XFS_INO_TO_AGINO(mp, ip->i_ino) & mask; mask 3518 fs/xfs/xfs_inode.c if ((XFS_INO_TO_AGINO(mp, cip->i_ino) & mask) != first_index) { mask 624 fs/xfs/xfs_iops.c int mask = iattr->ia_valid; mask 632 fs/xfs/xfs_iops.c ASSERT((mask & ATTR_SIZE) == 0); mask 642 fs/xfs/xfs_iops.c if (XFS_IS_QUOTA_ON(mp) && (mask & (ATTR_UID|ATTR_GID))) { mask 645 fs/xfs/xfs_iops.c if ((mask & ATTR_UID) && XFS_IS_UQUOTA_ON(mp)) { mask 651 fs/xfs/xfs_iops.c if ((mask & ATTR_GID) && XFS_IS_GQUOTA_ON(mp)) { mask 683 fs/xfs/xfs_iops.c if (mask & (ATTR_UID|ATTR_GID)) { mask 692 fs/xfs/xfs_iops.c gid = (mask & ATTR_GID) ? iattr->ia_gid : igid; mask 693 fs/xfs/xfs_iops.c uid = (mask & ATTR_UID) ? iattr->ia_uid : iuid; mask 714 fs/xfs/xfs_iops.c if (mask & (ATTR_UID|ATTR_GID)) { mask 731 fs/xfs/xfs_iops.c ASSERT(mask & ATTR_UID); mask 743 fs/xfs/xfs_iops.c ASSERT(mask & ATTR_GID); mask 753 fs/xfs/xfs_iops.c if (mask & ATTR_MODE) mask 755 fs/xfs/xfs_iops.c if (mask & (ATTR_ATIME|ATTR_CTIME|ATTR_MTIME)) mask 786 fs/xfs/xfs_iops.c if ((mask & ATTR_MODE) && !(flags & XFS_ATTR_NOACL)) { mask 104 include/acpi/actbl1.h u64 mask; /* Bitmask required for this register instruction */ mask 172 include/acpi/actbl1.h u8 mask; mask 560 include/acpi/actbl3.h u32 mask; /* Bitmask required for this register instruction */ mask 35 include/asm-generic/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 38 include/asm-generic/bitops/atomic.h if (READ_ONCE(*p) & mask) mask 41 include/asm-generic/bitops/atomic.h old = atomic_long_fetch_or(mask, (atomic_long_t *)p); mask 42 include/asm-generic/bitops/atomic.h return !!(old & mask); mask 48 include/asm-generic/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 51 include/asm-generic/bitops/atomic.h if (!(READ_ONCE(*p) & mask)) mask 54 include/asm-generic/bitops/atomic.h old = atomic_long_fetch_andnot(mask, (atomic_long_t *)p); mask 55 include/asm-generic/bitops/atomic.h return !!(old & mask); mask 61 include/asm-generic/bitops/atomic.h unsigned long mask = BIT_MASK(nr); mask 64 include/asm-generic/bitops/atomic.h old = atomic_long_fetch_xor(mask, (atomic_long_t *)p); mask 65 include/asm-generic/bitops/atomic.h return !!(old & mask); mask 22 include/asm-generic/bitops/lock.h unsigned long mask = BIT_MASK(nr); mask 25 include/asm-generic/bitops/lock.h if (READ_ONCE(*p) & mask) mask 28 include/asm-generic/bitops/lock.h old = atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p); mask 29 include/asm-generic/bitops/lock.h return !!(old & mask); mask 82 include/asm-generic/bitops/lock.h unsigned long mask = BIT_MASK(nr); mask 85 include/asm-generic/bitops/lock.h old = atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p); mask 18 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 21 include/asm-generic/bitops/non-atomic.h *p |= mask; mask 26 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 29 include/asm-generic/bitops/non-atomic.h *p &= ~mask; mask 43 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 46 include/asm-generic/bitops/non-atomic.h *p ^= mask; mask 60 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 64 include/asm-generic/bitops/non-atomic.h *p = old | mask; mask 65 include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 79 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 83 include/asm-generic/bitops/non-atomic.h *p = old & ~mask; mask 84 include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 91 include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 95 include/asm-generic/bitops/non-atomic.h *p = old ^ mask; mask 96 include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 19 include/asm-generic/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; mask 20 include/asm-generic/word-at-a-time.h return ~(mask | rhs); mask 23 include/asm-generic/word-at-a-time.h #define create_zero_mask(mask) (mask) mask 25 include/asm-generic/word-at-a-time.h static inline long find_zero(unsigned long mask) mask 29 include/asm-generic/word-at-a-time.h if (mask >> 32) mask 30 include/asm-generic/word-at-a-time.h mask >>= 32; mask 34 include/asm-generic/word-at-a-time.h if (mask >> 16) mask 35 include/asm-generic/word-at-a-time.h mask >>= 16; mask 38 include/asm-generic/word-at-a-time.h return (mask >> 8) ? byte : byte + 1; mask 49 include/asm-generic/word-at-a-time.h #define zero_bytemask(mask) (~1ul << __fls(mask)) mask 74 include/asm-generic/word-at-a-time.h static inline long count_masked_bytes(unsigned long mask) mask 76 include/asm-generic/word-at-a-time.h return mask*0x0001020304050608ul >> 56; mask 82 include/asm-generic/word-at-a-time.h static inline long count_masked_bytes(long mask) mask 85 include/asm-generic/word-at-a-time.h long a = (0x0ff0001+mask) >> 23; mask 87 include/asm-generic/word-at-a-time.h return a & mask; mask 95 include/asm-generic/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 96 include/asm-generic/word-at-a-time.h *bits = mask; mask 97 include/asm-generic/word-at-a-time.h return mask; mask 112 include/asm-generic/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 114 include/asm-generic/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 116 include/asm-generic/word-at-a-time.h return count_masked_bytes(mask); mask 108 include/crypto/acompress.h u32 mask); mask 156 include/crypto/acompress.h static inline int crypto_has_acomp(const char *alg_name, u32 type, u32 mask) mask 160 include/crypto/acompress.h mask |= CRYPTO_ALG_TYPE_MASK; mask 162 include/crypto/acompress.h return crypto_has_alg(alg_name, type, mask); mask 172 include/crypto/aead.h struct crypto_aead *crypto_alloc_aead(const char *alg_name, u32 type, u32 mask); mask 131 include/crypto/akcipher.h u32 mask); mask 32 include/crypto/algapi.h unsigned int (*ctxsize)(struct crypto_alg *alg, u32 type, u32 mask); mask 34 include/crypto/algapi.h int (*init)(struct crypto_tfm *tfm, u32 type, u32 mask); mask 72 include/crypto/algapi.h u32 mask; mask 151 include/crypto/algapi.h struct crypto_instance *inst, u32 mask); mask 156 include/crypto/algapi.h u32 type, u32 mask); mask 160 include/crypto/algapi.h u32 mask); mask 174 include/crypto/algapi.h u32 type, u32 mask); mask 177 include/crypto/algapi.h u32 type, u32 mask) mask 179 include/crypto/algapi.h return crypto_attr_alg2(rta, NULL, type, mask); mask 293 include/crypto/algapi.h u32 mask = CRYPTO_ALG_TYPE_MASK; mask 295 include/crypto/algapi.h return __crypto_blkcipher_cast(crypto_spawn_tfm(spawn, type, mask)); mask 312 include/crypto/algapi.h u32 mask = CRYPTO_ALG_TYPE_MASK; mask 314 include/crypto/algapi.h return __crypto_cipher_cast(crypto_spawn_tfm(spawn, type, mask)); mask 374 include/crypto/algapi.h u32 type, u32 mask) mask 376 include/crypto/algapi.h return crypto_attr_alg(tb[1], type, mask); mask 379 include/crypto/algapi.h static inline int crypto_requires_off(u32 type, u32 mask, u32 off) mask 381 include/crypto/algapi.h return (type ^ off) & mask & off; mask 388 include/crypto/algapi.h static inline int crypto_requires_sync(u32 type, u32 mask) mask 390 include/crypto/algapi.h return crypto_requires_off(type, mask, CRYPTO_ALG_ASYNC); mask 27 include/crypto/cryptd.h u32 type, u32 mask); mask 45 include/crypto/cryptd.h u32 type, u32 mask); mask 63 include/crypto/cryptd.h u32 type, u32 mask); mask 253 include/crypto/hash.h u32 mask); mask 279 include/crypto/hash.h int crypto_has_ahash(const char *alg_name, u32 type, u32 mask); mask 696 include/crypto/hash.h u32 mask); mask 46 include/crypto/if_alg.h void *(*bind)(const char *name, u32 type, u32 mask); mask 91 include/crypto/internal/aead.h u32 type, u32 mask); mask 89 include/crypto/internal/akcipher.h u32 type, u32 mask); mask 23 include/crypto/internal/geniv.h struct rtattr **tb, u32 type, u32 mask); mask 99 include/crypto/internal/hash.h struct hash_alg_common *ahash_attr_alg(struct rtattr *rta, u32 type, u32 mask); mask 118 include/crypto/internal/hash.h struct shash_alg *shash_attr_alg(struct rtattr *rta, u32 type, u32 mask); mask 98 include/crypto/internal/skcipher.h u32 type, u32 mask); mask 105 include/crypto/kpp.h struct crypto_kpp *crypto_alloc_kpp(const char *alg_name, u32 type, u32 mask); mask 90 include/crypto/rng.h struct crypto_rng *crypto_alloc_rng(const char *alg_name, u32 type, u32 mask); mask 192 include/crypto/skcipher.h u32 type, u32 mask); mask 195 include/crypto/skcipher.h u32 type, u32 mask); mask 228 include/crypto/skcipher.h u32 mask) mask 231 include/crypto/skcipher.h crypto_skcipher_mask(mask)); mask 244 include/crypto/skcipher.h int crypto_has_skcipher2(const char *alg_name, u32 type, u32 mask); mask 540 include/drm/ttm/ttm_bo_driver.h ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) mask 542 include/drm/ttm/ttm_bo_driver.h *old ^= (*old ^ new) & mask; mask 547 include/linux/acpi.h u32 *mask, u32 req); mask 167 include/linux/amba/bus.h #define __AMBA_DEV(busid, data, mask) \ mask 169 include/linux/amba/bus.h .coherent_dma_mask = mask, \ mask 42 include/linux/audit.h u32 mask[AUDIT_BITMASK_SIZE]; mask 570 include/linux/avf/virtchnl.h union virtchnl_flow_spec mask; mask 417 include/linux/bcma/bcma.h static inline void bcma_mask32(struct bcma_device *cc, u16 offset, u32 mask) mask 419 include/linux/bcma/bcma.h bcma_write32(cc, offset, bcma_read32(cc, offset) & mask); mask 426 include/linux/bcma/bcma.h u16 offset, u32 mask, u32 set) mask 428 include/linux/bcma/bcma.h bcma_write32(cc, offset, (bcma_read32(cc, offset) & mask) | set); mask 430 include/linux/bcma/bcma.h static inline void bcma_mask16(struct bcma_device *cc, u16 offset, u16 mask) mask 432 include/linux/bcma/bcma.h bcma_write16(cc, offset, bcma_read16(cc, offset) & mask); mask 439 include/linux/bcma/bcma.h u16 offset, u16 mask, u16 set) mask 441 include/linux/bcma/bcma.h bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); mask 663 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_cc_mask32(cc, offset, mask) \ mask 664 include/linux/bcma/bcma_driver_chipcommon.h bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask)) mask 667 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_cc_maskset32(cc, offset, mask, set) \ mask 668 include/linux/bcma/bcma_driver_chipcommon.h bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) mask 676 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_pmu_mask32(cc, offset, mask) \ mask 677 include/linux/bcma/bcma_driver_chipcommon.h bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask)) mask 680 include/linux/bcma/bcma_driver_chipcommon.h #define bcma_pmu_maskset32(cc, offset, mask, set) \ mask 681 include/linux/bcma/bcma_driver_chipcommon.h bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set)) mask 687 include/linux/bcma/bcma_driver_chipcommon.h void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 689 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); mask 692 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); mask 693 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 694 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 695 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 696 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 697 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 698 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 699 include/linux/bcma/bcma_driver_chipcommon.h u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value); mask 705 include/linux/bcma/bcma_driver_chipcommon.h u32 mask, u32 set); mask 707 include/linux/bcma/bcma_driver_chipcommon.h u32 offset, u32 mask, u32 set); mask 709 include/linux/bcma/bcma_driver_chipcommon.h u32 offset, u32 mask, u32 set); mask 157 include/linux/bcma/bcma_driver_pcie2.h #define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask) mask 484 include/linux/bitmap.h static inline void bitmap_from_u64(unsigned long *dst, u64 mask) mask 486 include/linux/bitmap.h dst[0] = mask & ULONG_MAX; mask 488 include/linux/bitmap.h if (sizeof(mask) > sizeof(unsigned long)) mask 489 include/linux/bitmap.h dst[1] = mask >> 32; mask 246 include/linux/bitops.h #define set_mask_bits(ptr, mask, bits) \ mask 248 include/linux/bitops.h const typeof(*(ptr)) mask__ = (mask), bits__ = (bits); \ mask 58 include/linux/can/core.h canid_t can_id, canid_t mask, mask 63 include/linux/can/core.h canid_t can_id, canid_t mask, mask 113 include/linux/can/dev/peak_canfd.h __le32 mask; /* CAN-ID bitmask in idx range */ mask 124 include/linux/can/dev/peak_canfd.h __le32 mask; /* CAN-ID bitmask in idx range */ mask 436 include/linux/ccp.h struct scatterlist *mask; mask 465 include/linux/ccp.h dma_addr_t mask; mask 46 include/linux/cdrom.h int mask; /* mask of capability: disables them */ mask 389 include/linux/ceph/ceph_fs.h __le32 mask; /* CEPH_CAP_* */ mask 398 include/linux/ceph/ceph_fs.h __le32 mask; /* CEPH_SETATTR_* */ mask 421 include/linux/ceph/ceph_fs.h __le32 mask; /* CEPH_CAP_* */ mask 440 include/linux/ceph/ceph_fs.h __le32 mask; /* CEPH_CAP_* */ mask 528 include/linux/ceph/ceph_fs.h __le16 mask; /* lease type(s) */ mask 747 include/linux/ceph/ceph_fs.h __le16 mask; /* which lease */ mask 540 include/linux/clk-provider.h u32 mask; mask 572 include/linux/clk-provider.h void __iomem *reg, u8 shift, u32 mask, mask 577 include/linux/clk-provider.h void __iomem *reg, u8 shift, u32 mask, mask 233 include/linux/clk/ti.h void (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg); mask 119 include/linux/clockchips.h void (*broadcast)(const struct cpumask *mask); mask 203 include/linux/clockchips.h extern void tick_broadcast(const struct cpumask *mask); mask 82 include/linux/clocksource.h u64 mask; mask 202 include/linux/clocksource.h clocks_calc_max_nsecs(u32 mult, u32 shift, u32 maxadj, u64 mask, u64 *max_cycles); mask 417 include/linux/compat.h long compat_get_bitmap(unsigned long *mask, const compat_ulong_t __user *umask, mask 419 include/linux/compat.h long compat_put_bitmap(compat_ulong_t __user *umask, unsigned long *mask, mask 711 include/linux/cpufreq.h ssize_t cpufreq_show_cpus(const struct cpumask *mask, char *buf); mask 178 include/linux/cpumask.h static inline unsigned int cpumask_next_wrap(int n, const struct cpumask *mask, mask 186 include/linux/cpumask.h static inline unsigned int cpumask_any_but(const struct cpumask *mask, mask 197 include/linux/cpumask.h #define for_each_cpu(cpu, mask) \ mask 198 include/linux/cpumask.h for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask) mask 199 include/linux/cpumask.h #define for_each_cpu_not(cpu, mask) \ mask 200 include/linux/cpumask.h for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask) mask 201 include/linux/cpumask.h #define for_each_cpu_wrap(cpu, mask, start) \ mask 202 include/linux/cpumask.h for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)(start)) mask 246 include/linux/cpumask.h int cpumask_any_but(const struct cpumask *mask, unsigned int cpu); mask 256 include/linux/cpumask.h #define for_each_cpu(cpu, mask) \ mask 258 include/linux/cpumask.h (cpu) = cpumask_next((cpu), (mask)), \ mask 268 include/linux/cpumask.h #define for_each_cpu_not(cpu, mask) \ mask 270 include/linux/cpumask.h (cpu) = cpumask_next_zero((cpu), (mask)), \ mask 273 include/linux/cpumask.h extern int cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap); mask 285 include/linux/cpumask.h #define for_each_cpu_wrap(cpu, mask, start) \ mask 286 include/linux/cpumask.h for ((cpu) = cpumask_next_wrap((start)-1, (mask), (start), false); \ mask 288 include/linux/cpumask.h (cpu) = cpumask_next_wrap((cpu), (mask), (start), true)) mask 737 include/linux/cpumask.h bool alloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node); mask 738 include/linux/cpumask.h bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags); mask 739 include/linux/cpumask.h bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node); mask 740 include/linux/cpumask.h bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags); mask 741 include/linux/cpumask.h void alloc_bootmem_cpumask_var(cpumask_var_t *mask); mask 742 include/linux/cpumask.h void free_cpumask_var(cpumask_var_t mask); mask 743 include/linux/cpumask.h void free_bootmem_cpumask_var(cpumask_var_t mask); mask 745 include/linux/cpumask.h static inline bool cpumask_available(cpumask_var_t mask) mask 747 include/linux/cpumask.h return mask != NULL; mask 756 include/linux/cpumask.h static inline bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) mask 761 include/linux/cpumask.h static inline bool alloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, mask 767 include/linux/cpumask.h static inline bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) mask 769 include/linux/cpumask.h cpumask_clear(*mask); mask 773 include/linux/cpumask.h static inline bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, mask 776 include/linux/cpumask.h cpumask_clear(*mask); mask 780 include/linux/cpumask.h static inline void alloc_bootmem_cpumask_var(cpumask_var_t *mask) mask 784 include/linux/cpumask.h static inline void free_cpumask_var(cpumask_var_t mask) mask 788 include/linux/cpumask.h static inline void free_bootmem_cpumask_var(cpumask_var_t mask) mask 792 include/linux/cpumask.h static inline bool cpumask_available(cpumask_var_t mask) mask 914 include/linux/cpumask.h cpumap_print_to_pagebuf(bool list, char *buf, const struct cpumask *mask) mask 916 include/linux/cpumask.h return bitmap_print_to_pagebuf(list, buf, cpumask_bits(mask), mask 60 include/linux/cpuset.h extern void cpuset_cpus_allowed(struct task_struct *p, struct cpumask *mask); mask 185 include/linux/cpuset.h struct cpumask *mask) mask 187 include/linux/cpuset.h cpumask_copy(mask, cpu_possible_mask); mask 89 include/linux/crush/crush.h struct crush_rule_mask mask; mask 710 include/linux/crypto.h int crypto_has_alg(const char *name, u32 type, u32 mask); mask 814 include/linux/crypto.h u32 mask; mask 825 include/linux/crypto.h struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask); mask 833 include/linux/crypto.h int alg_test(const char *driver, const char *alg, u32 type, u32 mask); mask 910 include/linux/crypto.h static inline u32 crypto_skcipher_mask(u32 mask) mask 912 include/linux/crypto.h mask &= ~CRYPTO_ALG_TYPE_MASK; mask 913 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_BLKCIPHER_MASK; mask 914 include/linux/crypto.h return mask; mask 973 include/linux/crypto.h u32 mask) mask 976 include/linux/crypto.h crypto_skcipher_mask(mask)); mask 1324 include/linux/crypto.h const char *alg_name, u32 type, u32 mask) mask 1328 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1330 include/linux/crypto.h return __crypto_blkcipher_cast(crypto_alloc_base(alg_name, type, mask)); mask 1358 include/linux/crypto.h static inline int crypto_has_blkcipher(const char *alg_name, u32 type, u32 mask) mask 1362 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1364 include/linux/crypto.h return crypto_has_alg(alg_name, type, mask); mask 1644 include/linux/crypto.h u32 type, u32 mask) mask 1648 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1650 include/linux/crypto.h return __crypto_cipher_cast(crypto_alloc_base(alg_name, type, mask)); mask 1677 include/linux/crypto.h static inline int crypto_has_cipher(const char *alg_name, u32 type, u32 mask) mask 1681 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1683 include/linux/crypto.h return crypto_has_alg(alg_name, type, mask); mask 1796 include/linux/crypto.h u32 type, u32 mask) mask 1800 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1802 include/linux/crypto.h return __crypto_comp_cast(crypto_alloc_base(alg_name, type, mask)); mask 1815 include/linux/crypto.h static inline int crypto_has_comp(const char *alg_name, u32 type, u32 mask) mask 1819 include/linux/crypto.h mask |= CRYPTO_ALG_TYPE_MASK; mask 1821 include/linux/crypto.h return crypto_has_alg(alg_name, type, mask); mask 35 include/linux/device_cgroup.h static inline int devcgroup_inode_permission(struct inode *inode, int mask) mask 49 include/linux/device_cgroup.h if (mask & MAY_WRITE) mask 51 include/linux/device_cgroup.h if (mask & MAY_READ) mask 75 include/linux/device_cgroup.h static inline int devcgroup_inode_permission(struct inode *inode, int mask) mask 80 include/linux/dma-direct.h int dma_direct_supported(struct device *dev, u64 mask); mask 131 include/linux/dma-mapping.h int (*dma_supported)(struct device *dev, u64 mask); mask 462 include/linux/dma-mapping.h int dma_supported(struct device *dev, u64 mask); mask 463 include/linux/dma-mapping.h int dma_set_mask(struct device *dev, u64 mask); mask 464 include/linux/dma-mapping.h int dma_set_coherent_mask(struct device *dev, u64 mask); mask 557 include/linux/dma-mapping.h static inline int dma_supported(struct device *dev, u64 mask) mask 561 include/linux/dma-mapping.h static inline int dma_set_mask(struct device *dev, u64 mask) mask 565 include/linux/dma-mapping.h static inline int dma_set_coherent_mask(struct device *dev, u64 mask) mask 672 include/linux/dma-mapping.h static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask) mask 674 include/linux/dma-mapping.h int rc = dma_set_mask(dev, mask); mask 676 include/linux/dma-mapping.h dma_set_coherent_mask(dev, mask); mask 684 include/linux/dma-mapping.h static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask) mask 687 include/linux/dma-mapping.h return dma_set_mask_and_coherent(dev, mask); mask 745 include/linux/dma-mapping.h static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask) mask 748 include/linux/dma-mapping.h dev->dma_parms->segment_boundary_mask = mask; mask 25 include/linux/dma/qcom_bam_dma.h __le32 mask; mask 53 include/linux/dma/qcom_bam_dma.h bam_ce->mask = cpu_to_le32(0xffffffff); mask 1034 include/linux/dmaengine.h size_t mask; mask 1038 include/linux/dmaengine.h mask = (1 << align) - 1; mask 1039 include/linux/dmaengine.h if (mask & (off1 | off2 | len)) mask 1083 include/linux/dmaengine.h enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; mask 1085 include/linux/dmaengine.h return (flags & mask) == mask; mask 1202 include/linux/dmaengine.h #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) mask 1209 include/linux/dmaengine.h #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) mask 1216 include/linux/dmaengine.h #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) mask 1222 include/linux/dmaengine.h #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) mask 1229 include/linux/dmaengine.h #define for_each_dma_cap_mask(cap, mask) \ mask 1230 include/linux/dmaengine.h for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) mask 1306 include/linux/dmaengine.h struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, mask 1312 include/linux/dmaengine.h struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); mask 1332 include/linux/dmaengine.h static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, mask 1350 include/linux/dmaengine.h const dma_cap_mask_t *mask) mask 1410 include/linux/dmaengine.h #define dma_request_channel(mask, x, y) \ mask 1411 include/linux/dmaengine.h __dma_request_channel(&(mask), x, y, NULL) mask 1412 include/linux/dmaengine.h #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ mask 1413 include/linux/dmaengine.h __dma_request_slave_channel_compat(&(mask), x, y, dev, name) mask 1416 include/linux/dmaengine.h *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, mask 1429 include/linux/dmaengine.h return __dma_request_channel(mask, fn, fn_param, NULL); mask 389 include/linux/etherdevice.h const u8 *mask) mask 394 include/linux/etherdevice.h if ((addr1[i] ^ addr2[i]) & mask[i]) mask 118 include/linux/fb.h const char __user *mask; /* cursor mask bits */ mask 22 include/linux/firmware/imx/sci.h int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable); mask 3210 include/linux/fs.h unsigned int mask); mask 27 include/linux/fsnotify.h __u32 mask) mask 29 include/linux/fsnotify.h return fsnotify(dir, mask, d_inode(dentry), FSNOTIFY_EVENT_INODE, mask 35 include/linux/fsnotify.h struct dentry *dentry, __u32 mask) mask 40 include/linux/fsnotify.h return __fsnotify_parent(path, dentry, mask); mask 48 include/linux/fsnotify.h __u32 mask) mask 50 include/linux/fsnotify.h int ret = fsnotify_parent(path, NULL, mask); mask 54 include/linux/fsnotify.h return fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); mask 58 include/linux/fsnotify.h static inline int fsnotify_perm(struct file *file, int mask) mask 67 include/linux/fsnotify.h if (!(mask & (MAY_READ | MAY_OPEN))) mask 69 include/linux/fsnotify.h if (mask & MAY_OPEN) { mask 78 include/linux/fsnotify.h } else if (mask & MAY_READ) { mask 93 include/linux/fsnotify.h __u32 mask = FS_ATTRIB; mask 96 include/linux/fsnotify.h mask |= FS_ISDIR; mask 98 include/linux/fsnotify.h fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); mask 113 include/linux/fsnotify.h __u32 mask = FS_MOVE_SELF; mask 122 include/linux/fsnotify.h mask |= FS_ISDIR; mask 134 include/linux/fsnotify.h fsnotify(source, mask, source, FSNOTIFY_EVENT_INODE, NULL, 0); mask 159 include/linux/fsnotify.h __u32 mask = FS_DELETE_SELF; mask 162 include/linux/fsnotify.h mask |= FS_ISDIR; mask 164 include/linux/fsnotify.h fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); mask 234 include/linux/fsnotify.h __u32 mask = FS_ACCESS; mask 237 include/linux/fsnotify.h mask |= FS_ISDIR; mask 240 include/linux/fsnotify.h fsnotify_path(inode, path, mask); mask 250 include/linux/fsnotify.h __u32 mask = FS_MODIFY; mask 253 include/linux/fsnotify.h mask |= FS_ISDIR; mask 256 include/linux/fsnotify.h fsnotify_path(inode, path, mask); mask 266 include/linux/fsnotify.h __u32 mask = FS_OPEN; mask 269 include/linux/fsnotify.h mask |= FS_ISDIR; mask 271 include/linux/fsnotify.h mask |= FS_OPEN_EXEC; mask 273 include/linux/fsnotify.h fsnotify_path(inode, path, mask); mask 284 include/linux/fsnotify.h __u32 mask = (mode & FMODE_WRITE) ? FS_CLOSE_WRITE : FS_CLOSE_NOWRITE; mask 287 include/linux/fsnotify.h mask |= FS_ISDIR; mask 290 include/linux/fsnotify.h fsnotify_path(inode, path, mask); mask 299 include/linux/fsnotify.h __u32 mask = FS_ATTRIB; mask 302 include/linux/fsnotify.h mask |= FS_ISDIR; mask 304 include/linux/fsnotify.h fsnotify_parent(NULL, dentry, mask); mask 305 include/linux/fsnotify.h fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); mask 315 include/linux/fsnotify.h __u32 mask = 0; mask 318 include/linux/fsnotify.h mask |= FS_ATTRIB; mask 320 include/linux/fsnotify.h mask |= FS_ATTRIB; mask 322 include/linux/fsnotify.h mask |= FS_MODIFY; mask 326 include/linux/fsnotify.h mask |= FS_ATTRIB; mask 328 include/linux/fsnotify.h mask |= FS_ACCESS; mask 330 include/linux/fsnotify.h mask |= FS_MODIFY; mask 333 include/linux/fsnotify.h mask |= FS_ATTRIB; mask 335 include/linux/fsnotify.h if (mask) { mask 337 include/linux/fsnotify.h mask |= FS_ISDIR; mask 339 include/linux/fsnotify.h fsnotify_parent(NULL, dentry, mask); mask 340 include/linux/fsnotify.h fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); mask 119 include/linux/fsnotify_backend.h u32 mask, const void *data, int data_type, mask 323 include/linux/fsnotify_backend.h __u32 mask; mask 353 include/linux/fsnotify_backend.h extern int fsnotify(struct inode *to_tell, __u32 mask, const void *data, int data_is, mask 355 include/linux/fsnotify_backend.h extern int __fsnotify_parent(const struct path *path, struct dentry *dentry, __u32 mask); mask 510 include/linux/fsnotify_backend.h static inline int fsnotify(struct inode *to_tell, __u32 mask, const void *data, int data_is, mask 516 include/linux/fsnotify_backend.h static inline int __fsnotify_parent(const struct path *path, struct dentry *dentry, __u32 mask) mask 451 include/linux/genhd.h extern void disk_flush_events(struct gendisk *disk, unsigned int mask); mask 452 include/linux/genhd.h extern unsigned int disk_clear_events(struct gendisk *disk, unsigned int mask); mask 359 include/linux/gpio/driver.h unsigned long *mask, mask 364 include/linux/gpio/driver.h unsigned long *mask, mask 336 include/linux/hugetlb.h unsigned long mask; mask 418 include/linux/hugetlb.h return h->mask; mask 1261 include/linux/ide.h u8 mask; /* mask to isolate the enable-bit */ mask 3275 include/linux/ieee80211.h u8 mask; mask 3283 include/linux/ieee80211.h mask = 1 << (aid & 7); mask 3293 include/linux/ieee80211.h return !!(tim->virtual_map[index] & mask); mask 45 include/linux/iio/buffer.h const unsigned long *mask); mask 158 include/linux/iio/common/cros_ec_sensors_core.h int *val, int *val2, long mask); mask 176 include/linux/iio/common/cros_ec_sensors_core.h long mask); mask 190 include/linux/iio/common/cros_ec_sensors_core.h int val, int val2, long mask); mask 49 include/linux/iio/common/st_sensors.h #define ST_SENSORS_LSM_CHANNELS(device_type, mask, index, mod, \ mask 54 include/linux/iio/common/st_sensors.h .info_mask_separate = mask, \ mask 83 include/linux/iio/common/st_sensors.h u8 mask; mask 89 include/linux/iio/common/st_sensors.h u8 mask; mask 96 include/linux/iio/common/st_sensors.h u8 mask; mask 108 include/linux/iio/common/st_sensors.h u8 mask; mask 124 include/linux/iio/common/st_sensors.h u8 mask; mask 134 include/linux/iio/common/st_sensors.h u8 mask; mask 146 include/linux/iio/common/st_sensors.h u8 mask; mask 169 include/linux/iio/common/st_sensors.h u8 mask; mask 401 include/linux/iio/iio.h long mask); mask 408 include/linux/iio/iio.h long mask); mask 415 include/linux/iio/iio.h long mask); mask 421 include/linux/iio/iio.h long mask); mask 425 include/linux/iio/iio.h long mask); mask 17 include/linux/ima.h extern int ima_file_check(struct file *file, int mask); mask 53 include/linux/ima.h static inline int ima_file_check(struct file *file, int mask) mask 187 include/linux/inetdevice.h __be32 mask); mask 198 include/linux/inetdevice.h static __inline__ bool bad_mask(__be32 mask, __be32 addr) mask 201 include/linux/inetdevice.h if (addr & (mask = ~mask)) mask 203 include/linux/inetdevice.h hmask = ntohl(mask); mask 280 include/linux/inetdevice.h static __inline__ int inet_mask_len(__be32 mask) mask 282 include/linux/inetdevice.h __u32 hmask = ntohl(mask); mask 215 include/linux/intel-iommu.h #define DMA_ID_TLB_ADDR_MASK(mask) (mask) mask 649 include/linux/intel-iommu.h u16 qdep, u64 addr, unsigned mask); mask 94 include/linux/intel_rapl.h u64 mask; mask 259 include/linux/interrupt.h void (*notify)(struct irq_affinity_notify *, const cpumask_t *mask); mask 294 include/linux/interrupt.h struct cpumask mask; mask 15 include/linux/ioprio.h #define IOPRIO_PRIO_CLASS(mask) ((mask) >> IOPRIO_CLASS_SHIFT) mask 16 include/linux/ioprio.h #define IOPRIO_PRIO_DATA(mask) ((mask) & IOPRIO_PRIO_MASK) mask 19 include/linux/ioprio.h #define ioprio_valid(mask) (IOPRIO_PRIO_CLASS((mask)) != IOPRIO_CLASS_NONE) mask 174 include/linux/irq.h u32 mask; mask 945 include/linux/irq.h unsigned long mask; mask 15 include/linux/irqchip/irq-partition-percpu.h cpumask_t mask; mask 274 include/linux/jbd2.h #define JBD2_HAS_COMPAT_FEATURE(j,mask) \ mask 276 include/linux/jbd2.h ((j)->j_superblock->s_feature_compat & cpu_to_be32((mask)))) mask 277 include/linux/jbd2.h #define JBD2_HAS_RO_COMPAT_FEATURE(j,mask) \ mask 279 include/linux/jbd2.h ((j)->j_superblock->s_feature_ro_compat & cpu_to_be32((mask)))) mask 280 include/linux/jbd2.h #define JBD2_HAS_INCOMPAT_FEATURE(j,mask) \ mask 282 include/linux/jbd2.h ((j)->j_superblock->s_feature_incompat & cpu_to_be32((mask)))) mask 17 include/linux/jz4740-adc.h int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val); mask 35 include/linux/kernel.h #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) mask 47 include/linux/kfifo.h unsigned int mask; mask 130 include/linux/kfifo.h __kfifo->mask = __is_kfifo_ptr(__tmp) ? 0 : ARRAY_SIZE(__tmp->buf) - 1;\ mask 150 include/linux/kfifo.h .mask = __is_kfifo_ptr(&(fifo)) ? \ mask 181 include/linux/kfifo.h #define kfifo_initialized(fifo) ((fifo)->kfifo.mask) mask 199 include/linux/kfifo.h #define kfifo_size(fifo) ((fifo)->kfifo.mask + 1) mask 256 include/linux/kfifo.h kfifo_len(__tmpq) > __tmpq->kfifo.mask; \ mask 390 include/linux/kfifo.h )[__kfifo->in & __tmp->kfifo.mask] = \ mask 429 include/linux/kfifo.h )[__kfifo->out & __tmp->kfifo.mask]; \ mask 468 include/linux/kfifo.h )[__kfifo->out & __tmp->kfifo.mask]; \ mask 54 include/linux/kthread.h void kthread_bind_mask(struct task_struct *k, const struct cpumask *mask); mask 819 include/linux/kvm_host.h unsigned long mask); mask 1147 include/linux/libata.h extern u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, mask 1218 include/linux/libata.h unsigned long mask; mask 1747 include/linux/libata.h unsigned int mask = ac_err_mask(status); mask 1748 include/linux/libata.h if (mask == 0) mask 1750 include/linux/libata.h return mask; mask 1547 include/linux/lsm_hooks.h int (*path_notify)(const struct path *path, u64 mask, mask 1573 include/linux/lsm_hooks.h int (*inode_permission)(struct inode *inode, int mask); mask 1600 include/linux/lsm_hooks.h int (*file_permission)(struct file *file, int mask); mask 30 include/linux/mbcache.h int mb_cache_entry_create(struct mb_cache *cache, gfp_t mask, u32 key, mask 142 include/linux/mdio.h int prtad, int devad, u16 addr, int mask, mask 152 include/linux/mempolicy.h extern bool init_nodemask_of_mempolicy(nodemask_t *mask); mask 154 include/linux/mempolicy.h const nodemask_t *mask); mask 135 include/linux/mfd/aat2870.h int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val); mask 14 include/linux/mfd/abx500/ab8500-sysctrl.h int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value); mask 23 include/linux/mfd/abx500/ab8500-sysctrl.h static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) mask 358 include/linux/mfd/abx500/ab8500.h int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data); mask 364 include/linux/mfd/abx500/ab8500.h u8 *mask; mask 507 include/linux/mfd/abx500/ab8500.h void ab8500_override_turn_on_stat(u8 mask, u8 set); mask 409 include/linux/mfd/as3722.h u32 mask, u8 val) mask 411 include/linux/mfd/as3722.h return regmap_update_bits(as3722->regmap, reg, mask, val); mask 245 include/linux/mfd/da903x.h extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask); mask 76 include/linux/mfd/da9150/core.h void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val); mask 545 include/linux/mfd/db8500-prcmu.h void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); mask 761 include/linux/mfd/db8500-prcmu.h static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask, mask 258 include/linux/mfd/dbx500-prcmu.h int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); mask 373 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) mask 375 include/linux/mfd/dbx500-prcmu.h db8500_prcmu_write_masked(reg, mask, value); mask 431 include/linux/mfd/dbx500-prcmu.h static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, mask 567 include/linux/mfd/dbx500-prcmu.h static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} mask 39 include/linux/mfd/htc-pasic3.h unsigned int mask; mask 435 include/linux/mfd/intel_msic.h extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); mask 30 include/linux/mfd/intel_soc_pmic.h u32 value, u32 mask); mask 98 include/linux/mfd/lm3533.h extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask); mask 83 include/linux/mfd/lp3943.h u8 mask; mask 109 include/linux/mfd/lp3943.h int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); mask 329 include/linux/mfd/lp8788.h int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data); mask 470 include/linux/mfd/max14577-private.h static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, mask 473 include/linux/mfd/max14577-private.h return regmap_update_bits(map, reg, mask, val); mask 409 include/linux/mfd/max8997-private.h extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); mask 167 include/linux/mfd/max8998-private.h extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); mask 19 include/linux/mfd/mc13xxx.h u32 mask, u32 val); mask 3790 include/linux/mfd/palmas.h unsigned int reg, unsigned int mask, unsigned int val) mask 3795 include/linux/mfd/palmas.h return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val); mask 68 include/linux/mfd/pcf50633/core.h int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); mask 358 include/linux/mfd/rc5t583.h unsigned int val, unsigned int mask) mask 361 include/linux/mfd/rc5t583.h return regmap_update_bits(rc5t583->regmap, reg, mask, val); mask 196 include/linux/mfd/sta2x11-mfd.h sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) mask 198 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apbreg); mask 229 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) mask 231 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_sctl); mask 368 include/linux/mfd/sta2x11-mfd.h u32 sta2x11_apb_soc_regs_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val) mask 370 include/linux/mfd/sta2x11-mfd.h return __sta2x11_mfd_mask(pdev, reg, mask, val, sta2x11_apb_soc_regs); mask 154 include/linux/mfd/stmpe.h extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val); mask 131 include/linux/mfd/tc3589x.h extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val); mask 285 include/linux/mfd/tps65217.h unsigned int mask, unsigned int val, unsigned int level); mask 287 include/linux/mfd/tps65217.h unsigned int mask, unsigned int level); mask 277 include/linux/mfd/tps65218.h unsigned int mask, unsigned int val, unsigned int level); mask 279 include/linux/mfd/tps65218.h unsigned int mask, unsigned int level); mask 108 include/linux/mfd/tps6586x.h uint8_t mask); mask 929 include/linux/mfd/tps65910.h u8 mask) mask 931 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, mask); mask 935 include/linux/mfd/tps65910.h u8 mask) mask 937 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, 0); mask 941 include/linux/mfd/tps65910.h u8 mask, u8 val) mask 943 include/linux/mfd/tps65910.h return regmap_update_bits(tps65910->regmap, reg, mask, val); mask 606 include/linux/mfd/tps80031.h int reg, uint8_t val, uint8_t mask) mask 610 include/linux/mfd/tps80031.h return regmap_update_bits(tps80031->regmap[sid], reg, mask, val); mask 239 include/linux/mfd/twl6040.h u8 mask); mask 241 include/linux/mfd/twl6040.h u8 mask); mask 411 include/linux/mfd/wm831x/core.h unsigned short mask, unsigned short val); mask 645 include/linux/mfd/wm8350/core.h int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask); mask 646 include/linux/mfd/wm8350/core.h int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask); mask 114 include/linux/mfd/wm8994/core.h unsigned short mask, unsigned short val) mask 116 include/linux/mfd/wm8994/core.h return regmap_update_bits(wm8994->regmap, reg, mask, val); mask 1108 include/linux/mlx5/driver.h u64 mask; mask 18 include/linux/mlx5/eq.h u64 mask[4]; mask 2006 include/linux/mm.h unsigned long mask = ~(PTRS_PER_PMD * sizeof(pmd_t) - 1); mask 2007 include/linux/mm.h return virt_to_page((void *)((unsigned long) pmd & mask)); mask 476 include/linux/mmc/host.h int mmc_of_parse_voltage(struct device_node *np, u32 *mask); mask 101 include/linux/mmc/sh_mmcif.h static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) mask 108 include/linux/mmc/sh_mmcif.h if (tmp & mask) { mask 109 include/linux/mmc/sh_mmcif.h sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); mask 640 include/linux/mod_devicetable.h unsigned int mask; mask 191 include/linux/msi.h u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag); mask 324 include/linux/msi.h int msi_domain_set_affinity(struct irq_data *data, const struct cpumask *mask, mask 342 include/linux/mtd/spi-nor.h u32 mask; mask 458 include/linux/mtd/spinand.h int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); mask 687 include/linux/netdevice.h unsigned int mask; mask 705 include/linux/netdevice.h u32 mask; mask 720 include/linux/netdevice.h unsigned int index = hash & table->mask; mask 2622 include/linux/netdevice.h unsigned short mask); mask 3432 include/linux/netdevice.h int netif_set_xps_queue(struct net_device *dev, const struct cpumask *mask, mask 3434 include/linux/netdevice.h int __netif_set_xps_queue(struct net_device *dev, const unsigned long *mask, mask 3446 include/linux/netdevice.h const unsigned long *mask, mask 3450 include/linux/netdevice.h return test_bit(j, mask); mask 3522 include/linux/netdevice.h const struct cpumask *mask, mask 3529 include/linux/netdevice.h const unsigned long *mask, mask 4480 include/linux/netdevice.h netdev_features_t one, netdev_features_t mask); mask 4487 include/linux/netdevice.h netdev_features_t mask) mask 4489 include/linux/netdevice.h return netdev_increment_features(features, NETIF_F_ALL_TSO, mask); mask 41 include/linux/netfilter.h const union nf_inet_addr *mask) mask 46 include/linux/netfilter.h const unsigned long *um = (const unsigned long *)mask; mask 51 include/linux/netfilter.h result->all[0] = a1->all[0] & mask->all[0]; mask 52 include/linux/netfilter.h result->all[1] = a1->all[1] & mask->all[1]; mask 53 include/linux/netfilter.h result->all[2] = a1->all[2] & mask->all[2]; mask 54 include/linux/netfilter.h result->all[3] = a1->all[3] & mask->all[3]; mask 20 include/linux/netfilter/ipset/ip_set_bitmap.h u32 mask = 0xFFFFFFFE; mask 23 include/linux/netfilter/ipset/ip_set_bitmap.h while (--(*bits) > 0 && mask && (to & mask) != from) mask 24 include/linux/netfilter/ipset/ip_set_bitmap.h mask <<= 1; mask 26 include/linux/netfilter/ipset/ip_set_bitmap.h return mask; mask 408 include/linux/netfilter/x_tables.h const unsigned long *mask = (const unsigned long *)_mask; mask 411 include/linux/netfilter/x_tables.h ret = (a[0] ^ b[0]) & mask[0]; mask 413 include/linux/netfilter/x_tables.h ret |= (a[1] ^ b[1]) & mask[1]; mask 415 include/linux/netfilter/x_tables.h ret |= (a[2] ^ b[2]) & mask[2]; mask 417 include/linux/netfilter/x_tables.h ret |= (a[3] ^ b[3]) & mask[3]; mask 55 include/linux/nfs_fs.h __u32 mask; mask 842 include/linux/nfs_xdr.h int mask; mask 848 include/linux/nfs_xdr.h int mask; mask 967 include/linux/nfs_xdr.h int mask; mask 156 include/linux/nmi.h static inline bool trigger_cpumask_backtrace(struct cpumask *mask) mask 158 include/linux/nmi.h arch_trigger_cpumask_backtrace(mask, false); mask 169 include/linux/nmi.h void nmi_trigger_cpumask_backtrace(const cpumask_t *mask, mask 171 include/linux/nmi.h void (*raise)(cpumask_t *mask)); mask 183 include/linux/nmi.h static inline bool trigger_cpumask_backtrace(struct cpumask *mask) mask 281 include/linux/nodemask.h static inline void init_nodemask_of_node(nodemask_t *mask, int node) mask 283 include/linux/nodemask.h nodes_clear(*mask); mask 284 include/linux/nodemask.h node_set(node, *mask); mask 298 include/linux/nodemask.h #define first_unset_node(mask) __first_unset_node(&(mask)) mask 378 include/linux/nodemask.h #define for_each_node_mask(node, mask) \ mask 379 include/linux/nodemask.h for ((node) = first_node(mask); \ mask 381 include/linux/nodemask.h (node) = next_node((node), (mask))) mask 383 include/linux/nodemask.h #define for_each_node_mask(node, mask) \ mask 384 include/linux/nodemask.h if (!nodes_empty(mask)) \ mask 499 include/linux/nodemask.h static inline int node_random(const nodemask_t *mask) mask 25 include/linux/nsc_gpio.h u32 (*gpio_config) (unsigned iminor, u32 mask, u32 bits); mask 24 include/linux/nubus.h int mask; mask 32 include/linux/nubus.h int mask; mask 60 include/linux/pageblock-flags.h unsigned long mask); mask 66 include/linux/pageblock-flags.h unsigned long mask); mask 116 include/linux/pagemap.h static inline void mapping_set_gfp_mask(struct address_space *m, gfp_t mask) mask 118 include/linux/pagemap.h m->gfp_mask = mask; mask 72 include/linux/parport.h unsigned char (*frob_control)(struct parport *, unsigned char mask, mask 433 include/linux/parport.h unsigned char mask, mask 436 include/linux/parport.h unsigned char mask, mask 129 include/linux/parport_pc.h unsigned char mask, mask 137 include/linux/parport_pc.h mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable); mask 139 include/linux/parport_pc.h ctr = (ctr & ~mask) ^ val; mask 185 include/linux/parport_pc.h unsigned char mask, mask 194 include/linux/parport_pc.h if (mask & 0x20) { mask 205 include/linux/parport_pc.h mask &= wm; mask 208 include/linux/parport_pc.h return __parport_pc_frob_control (p, mask, val); mask 113 include/linux/pci-dma-compat.h static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) mask 115 include/linux/pci-dma-compat.h return dma_set_mask(&dev->dev, mask); mask 118 include/linux/pci-dma-compat.h static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) mask 120 include/linux/pci-dma-compat.h return dma_set_coherent_mask(&dev->dev, mask); mask 123 include/linux/pci-dma-compat.h static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) mask 125 include/linux/pci-dma-compat.h static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) mask 965 include/linux/pci.h int __must_check pcibios_enable_device(struct pci_dev *, int mask); mask 1176 include/linux/pci.h int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); mask 1280 include/linux/pci.h int pci_enable_resources(struct pci_dev *, int mask); mask 1990 include/linux/pci.h int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); mask 1991 include/linux/pci.h int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, mask 1993 include/linux/pci.h void pcim_iounmap_regions(struct pci_dev *pdev, int mask); mask 133 include/linux/perf/arm_pmu.h unsigned int mask; mask 140 include/linux/perf/arm_pmu.h .mask = (_mask), \ mask 20 include/linux/perf_regs.h int perf_reg_validate(u64 mask); mask 34 include/linux/perf_regs.h static inline int perf_reg_validate(u64 mask) mask 36 include/linux/perf_regs.h return mask ? -ENOSYS : 0; mask 667 include/linux/phy.h phy_lookup_setting(int speed, int duplex, const unsigned long *mask, mask 670 include/linux/phy.h unsigned long *mask); mask 788 include/linux/phy.h int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, mask 790 include/linux/phy.h int phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask, mask 792 include/linux/phy.h int __phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); mask 793 include/linux/phy.h int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set); mask 796 include/linux/phy.h u16 mask, u16 set); mask 798 include/linux/phy.h u16 mask, u16 set); mask 800 include/linux/phy.h u16 mask, u16 set); mask 802 include/linux/phy.h u16 mask, u16 set); mask 995 include/linux/phy.h u16 mask, u16 set); mask 997 include/linux/phy.h u16 mask, u16 set); mask 42 include/linux/phy/omap_usb.h u32 mask; mask 50 include/linux/phy/omap_usb.h u32 mask; mask 1560 include/linux/platform_data/cros_ec_commands.h uint32_t mask; mask 3532 include/linux/platform_data/cros_ec_commands.h uint32_t mask; mask 3536 include/linux/platform_data/cros_ec_commands.h uint32_t mask; mask 25 include/linux/platform_data/dmtimer-omap.h int (*set_int_disable)(struct omap_dm_timer *timer, u32 mask); mask 85 include/linux/platform_data/emif_plat.h u32 mask; mask 87 include/linux/platform_data/mlxreg.h u32 mask; mask 114 include/linux/platform_data/mlxreg.h u32 mask; mask 161 include/linux/platform_data/mlxreg.h u32 mask; mask 68 include/linux/platform_data/pwm_omap_dmtimer.h int (*set_int_disable)(pwm_omap_dmtimer *timer, u32 mask); mask 134 include/linux/pm_qos.h enum pm_qos_flags_status __dev_pm_qos_flags(struct device *dev, s32 mask); mask 135 include/linux/pm_qos.h enum pm_qos_flags_status dev_pm_qos_flags(struct device *dev, s32 mask); mask 157 include/linux/pm_qos.h int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set); mask 181 include/linux/pm_qos.h s32 mask) mask 184 include/linux/pm_qos.h s32 mask) mask 67 include/linux/radix-tree.h #define RADIX_TREE_INIT(name, mask) XARRAY_INIT(name, mask) mask 69 include/linux/radix-tree.h #define RADIX_TREE(name, mask) \ mask 70 include/linux/radix-tree.h struct radix_tree_root name = RADIX_TREE_INIT(name, mask) mask 72 include/linux/radix-tree.h #define INIT_RADIX_TREE(root, mask) xa_init_flags(root, mask) mask 74 include/linux/regmap.h #define regmap_update_bits(map, reg, mask, val) \ mask 75 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, false) mask 76 include/linux/regmap.h #define regmap_update_bits_async(map, reg, mask, val)\ mask 77 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, true, false) mask 78 include/linux/regmap.h #define regmap_update_bits_check(map, reg, mask, val, change)\ mask 79 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, false, false) mask 80 include/linux/regmap.h #define regmap_update_bits_check_async(map, reg, mask, val, change)\ mask 81 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, change, true, false) mask 83 include/linux/regmap.h #define regmap_write_bits(map, reg, mask, val) \ mask 84 include/linux/regmap.h regmap_update_bits_base(map, reg, mask, val, NULL, false, true) mask 90 include/linux/regmap.h #define regmap_field_update_bits(field, mask, val)\ mask 91 include/linux/regmap.h regmap_field_update_bits_base(field, mask, val, NULL, false, false) mask 92 include/linux/regmap.h #define regmap_field_force_update_bits(field, mask, val) \ mask 93 include/linux/regmap.h regmap_field_update_bits_base(field, mask, val, NULL, false, true) mask 99 include/linux/regmap.h #define regmap_fields_update_bits(field, id, mask, val)\ mask 100 include/linux/regmap.h regmap_fields_update_bits_base(field, id, mask, val, NULL, false, false) mask 101 include/linux/regmap.h #define regmap_fields_force_update_bits(field, id, mask, val) \ mask 102 include/linux/regmap.h regmap_fields_update_bits_base(field, id, mask, val, NULL, false, true) mask 465 include/linux/regmap.h unsigned int mask, unsigned int val); mask 1032 include/linux/regmap.h unsigned int mask, unsigned int val, mask 1102 include/linux/regmap.h unsigned int mask, unsigned int val, mask 1107 include/linux/regmap.h unsigned int mask, unsigned int val, mask 1138 include/linux/regmap.h unsigned int mask; mask 1143 include/linux/regmap.h [_irq] = { .reg_offset = (_off), .mask = (_mask) } mask 1147 include/linux/regmap.h .mask = BIT((_id) % (_reg_bits)), \ mask 1361 include/linux/regmap.h unsigned int mask, unsigned int val, mask 1369 include/linux/regmap.h unsigned int mask, unsigned int val, mask 1378 include/linux/regmap.h unsigned int mask, unsigned int val, mask 51 include/linux/regulator/ab8500.h u8 mask; mask 58 include/linux/regulator/ab8500.h .mask = _mask, \ mask 303 include/linux/rmi.h int (*clear_irq_bits)(struct rmi_device *rmi_dev, unsigned long *mask); mask 304 include/linux/rmi.h int (*set_irq_bits)(struct rmi_device *rmi_dev, unsigned long *mask); mask 132 include/linux/rtnetlink.h u32 flags, u32 mask, int nlflags, mask 1287 include/linux/rtsx_pci.h int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); mask 1293 include/linux/rtsx_pci.h u8 cmd_type, u16 reg_addr, u8 mask, u8 data); mask 1323 include/linux/rtsx_pci.h u8 mask, u8 append) mask 1331 include/linux/rtsx_pci.h return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); mask 1343 include/linux/rtsx_pci.h u16 mask, u16 append) mask 1352 include/linux/rtsx_pci.h return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append); mask 71 include/linux/rtsx_usb.h extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask, mask 74 include/linux/rtsx_usb.h extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask, mask 80 include/linux/rtsx_usb.h u16 reg_addr, u8 mask, u8 data); mask 1854 include/linux/sched.h extern long sched_getaffinity(pid_t pid, struct cpumask *mask); mask 35 include/linux/sched/jobctl.h extern bool task_set_jobctl_pending(struct task_struct *task, unsigned long mask); mask 37 include/linux/sched/jobctl.h extern void task_clear_jobctl_pending(struct task_struct *task, unsigned long mask); mask 267 include/linux/sched/signal.h sigset_t *mask, kernel_siginfo_t *info); mask 179 include/linux/sched/topology.h sched_domain_mask_f mask; mask 314 include/linux/security.h int security_path_notify(const struct path *path, u64 mask, mask 339 include/linux/security.h int security_inode_permission(struct inode *inode, int mask); mask 359 include/linux/security.h int security_file_permission(struct file *file, int mask); mask 682 include/linux/security.h static inline int security_path_notify(const struct path *path, u64 mask, mask 800 include/linux/security.h static inline int security_inode_permission(struct inode *inode, int mask) mask 889 include/linux/security.h static inline int security_file_permission(struct file *file, int mask) mask 446 include/linux/serial_core.h upstat_t mask = UPSTAT_CTS_ENABLE | UPSTAT_AUTOCTS; mask 448 include/linux/serial_core.h return ((uport->status & mask) == UPSTAT_CTS_ENABLE); mask 210 include/linux/signal.h static inline void sigaddsetmask(sigset_t *set, unsigned long mask) mask 212 include/linux/signal.h set->sig[0] |= mask; mask 215 include/linux/signal.h static inline void sigdelsetmask(sigset_t *set, unsigned long mask) mask 217 include/linux/signal.h set->sig[0] &= ~mask; mask 220 include/linux/signal.h static inline int sigtestsetmask(sigset_t *set, unsigned long mask) mask 222 include/linux/signal.h return (set->sig[0] & mask) != 0; mask 225 include/linux/signal.h static inline void siginitset(sigset_t *set, unsigned long mask) mask 227 include/linux/signal.h set->sig[0] = mask; mask 237 include/linux/signal.h static inline void siginitsetinv(sigset_t *set, unsigned long mask) mask 239 include/linux/signal.h set->sig[0] = ~mask; mask 269 include/linux/signal.h extern int next_signal(struct sigpending *pending, sigset_t *mask); mask 403 include/linux/signal.h #define siginmask(sig, mask) \ mask 404 include/linux/signal.h ((sig) > 0 && (sig) < SIGRTMIN && (rt_sigmask(sig) & (mask))) mask 100 include/linux/sm501.h unsigned long mask; mask 44 include/linux/smp.h void on_each_cpu_mask(const struct cpumask *mask, smp_call_func_t func, mask 58 include/linux/smp.h gfp_t gfp_flags, const struct cpumask *mask); mask 105 include/linux/smp.h void smp_call_function_many(const struct cpumask *mask, mask 108 include/linux/smp.h int smp_call_function_any(const struct cpumask *mask, mask 155 include/linux/smp.h #define smp_call_function_many(mask, func, info, wait) \ mask 160 include/linux/smp.h smp_call_function_any(const struct cpumask *mask, smp_call_func_t func, mask 35 include/linux/soc/mediatek/infracfg.h int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, mask 37 include/linux/soc/mediatek/infracfg.h int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, mask 82 include/linux/soc/mediatek/mtk-cmdq.h u16 offset, u32 value, u32 mask); mask 19 include/linux/soc/qcom/smem_state.h int qcom_smem_state_update_bits(struct qcom_smem_state *state, u32 mask, u32 value); mask 37 include/linux/soc/qcom/smem_state.h u32 mask, u32 value) mask 608 include/linux/ssb/ssb_driver_chipcommon.h #define chipco_mask32(cc, offset, mask) \ mask 609 include/linux/ssb/ssb_driver_chipcommon.h chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask)) mask 612 include/linux/ssb/ssb_driver_chipcommon.h #define chipco_maskset32(cc, offset, mask, set) \ mask 613 include/linux/ssb/ssb_driver_chipcommon.h chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set)) mask 638 include/linux/ssb/ssb_driver_chipcommon.h void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 640 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask); mask 643 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask); mask 644 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 645 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 646 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 647 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 648 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 649 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 650 include/linux/ssb/ssb_driver_chipcommon.h u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value); mask 180 include/linux/ssb/ssb_driver_extif.h u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask); mask 181 include/linux/ssb/ssb_driver_extif.h u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value); mask 182 include/linux/ssb/ssb_driver_extif.h u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value); mask 183 include/linux/ssb/ssb_driver_extif.h u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value); mask 184 include/linux/ssb/ssb_driver_extif.h u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value); mask 220 include/linux/ssb/ssb_driver_extif.h static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) mask 225 include/linux/ssb/ssb_driver_extif.h static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, mask 231 include/linux/ssb/ssb_driver_extif.h static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, mask 237 include/linux/ssb/ssb_driver_extif.h static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, mask 243 include/linux/ssb/ssb_driver_extif.h static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, mask 12 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask); mask 13 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value); mask 14 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value); mask 15 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value); mask 16 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value); mask 17 include/linux/ssb/ssb_embedded.h u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value); mask 301 include/linux/sunrpc/xdr.h const size_t mask = sizeof(__u32) - 1; mask 303 include/linux/sunrpc/xdr.h return (n + mask) & ~mask; mask 80 include/linux/svga.h static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) mask 82 include/linux/svga.h vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & ~mask)); mask 87 include/linux/svga.h static inline void svga_wcrt_mask(void __iomem *regbase, u8 index, u8 data, u8 mask) mask 89 include/linux/svga.h vga_wcrt(regbase, index, (data & mask) | (vga_rcrt(regbase, index) & ~mask)); mask 353 include/linux/swap.h gfp_t gfp_mask, nodemask_t *mask); mask 272 include/linux/switchtec.h u8 mask; mask 379 include/linux/syscalls.h u32 mask); mask 729 include/linux/syscalls.h asmlinkage long sys_umask(int mask); mask 920 include/linux/syscalls.h u64 mask, int fd, mask 988 include/linux/syscalls.h unsigned mask, struct statx __user *buffer); mask 1127 include/linux/syscalls.h asmlinkage long sys_sigsuspend(old_sigset_t mask); mask 1131 include/linux/syscalls.h asmlinkage long sys_sigsuspend(int unused1, int unused2, old_sigset_t mask); mask 480 include/linux/thermal.h const char *type, int trips, int mask, void *devdata, mask 191 include/linux/tick.h static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) mask 194 include/linux/tick.h cpumask_or(mask, mask, tick_nohz_full_mask); mask 269 include/linux/tick.h static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) { } mask 32 include/linux/timecounter.h u64 mask; mask 59 include/linux/timecounter.h u64 mask; mask 71 include/linux/timecounter.h u64 cycles, u64 mask, u64 *frac) mask 76 include/linux/timecounter.h *frac = ns & mask; mask 36 include/linux/timekeeper_internal.h u64 mask; mask 16 include/linux/tnum.h u64 mask; mask 56 include/linux/tnum.h return !a.mask; mask 68 include/linux/tnum.h return !~a.mask; mask 15 include/linux/tracepoint-defs.h unsigned long mask; mask 20 include/linux/tracepoint-defs.h unsigned long long mask; mask 33 include/linux/udp.h static inline u32 udp_hashfn(const struct net *net, u32 num, u32 mask) mask 35 include/linux/udp.h return (num + net_hash_mix(net)) & mask; mask 101 include/linux/via-core.h void viafb_irq_enable(u32 mask); mask 102 include/linux/via-core.h void viafb_irq_disable(u32 mask); mask 202 include/linux/via-core.h static inline void via_write_reg_mask(u16 port, u8 index, u8 data, u8 mask) mask 208 include/linux/via-core.h outb((data & mask) | (old & ~mask), port + 1); mask 214 include/linux/via-core.h static inline void via_write_misc_reg_mask(u8 data, u8 mask) mask 217 include/linux/via-core.h outb((data & mask) | (old & ~mask), VIA_MISC_REG_WRITE); mask 45 include/linux/yam.h unsigned int mask; /* Mask of commands */ mask 33 include/media/drv-intf/saa7146.h #define _DBG(mask, fmt, ...) \ mask 35 include/media/drv-intf/saa7146.h if (DEBUG_VARIABLE & mask) \ mask 40 include/media/rc-core.h u32 mask; mask 215 include/media/rc-core.h int (*s_tx_mask)(struct rc_dev *dev, u32 mask); mask 338 include/media/rc-core.h static inline u32 ir_extract_bits(u32 data, u32 mask) mask 343 include/media/rc-core.h if (mask & 1) { mask 349 include/media/rc-core.h } while (mask >>= 1); mask 620 include/media/v4l2-ctrls.h u32 id, u8 max, u64 mask, u8 def); mask 646 include/media/v4l2-ctrls.h u64 mask, u8 def, mask 306 include/misc/ocxl.h enum ocxl_endian endian, u32 mask); mask 319 include/misc/ocxl.h enum ocxl_endian endian, u64 mask); mask 332 include/misc/ocxl.h enum ocxl_endian endian, u32 mask); mask 345 include/misc/ocxl.h enum ocxl_endian endian, u64 mask); mask 1347 include/net/bluetooth/hci.h __u8 mask[8]; mask 490 include/net/bluetooth/l2cap.h __u16 mask; mask 1960 include/net/cfg80211.h static inline void get_random_mask_addr(u8 *buf, const u8 *addr, const u8 *mask) mask 1966 include/net/cfg80211.h buf[i] &= ~mask[i]; mask 1967 include/net/cfg80211.h buf[i] |= addr[i] & mask[i]; mask 2646 include/net/cfg80211.h const u8 *mask, *pattern; mask 3705 include/net/cfg80211.h struct net_device *dev, u32 mask, mask 3781 include/net/cfg80211.h const struct cfg80211_bitrate_mask *mask); mask 5699 include/net/cfg80211.h u64 mask = GENMASK_ULL(max_bssid - 1, 0); mask 5702 include/net/cfg80211.h new_bssid_u64 = bssid_u64 & ~mask; mask 5704 include/net/cfg80211.h new_bssid_u64 |= ((bssid_u64 & mask) + mbssid_index) & mask; mask 180 include/net/devlink.h void *mask; mask 310 include/net/dsa.h u32 mask = 0; mask 315 include/net/dsa.h mask |= BIT(p); mask 317 include/net/dsa.h return mask; mask 28 include/net/dsfield.h static inline void ipv4_change_dsfield(struct iphdr *iph,__u8 mask, mask 34 include/net/dsfield.h dsfield = (iph->tos & mask) | value; mask 44 include/net/dsfield.h static inline void ipv6_change_dsfield(struct ipv6hdr *ipv6h,__u8 mask, mask 49 include/net/dsfield.h *p = (*p & htons((((u16)mask << 4) | 0xf00f))) | htons((u16)value << 4); mask 11 include/net/flow_offload.h void *mask; mask 16 include/net/flow_offload.h struct flow_dissector_key_meta *key, *mask; mask 20 include/net/flow_offload.h struct flow_dissector_key_basic *key, *mask; mask 24 include/net/flow_offload.h struct flow_dissector_key_control *key, *mask; mask 28 include/net/flow_offload.h struct flow_dissector_key_eth_addrs *key, *mask; mask 32 include/net/flow_offload.h struct flow_dissector_key_vlan *key, *mask; mask 36 include/net/flow_offload.h struct flow_dissector_key_ipv4_addrs *key, *mask; mask 40 include/net/flow_offload.h struct flow_dissector_key_ipv6_addrs *key, *mask; mask 44 include/net/flow_offload.h struct flow_dissector_key_ip *key, *mask; mask 48 include/net/flow_offload.h struct flow_dissector_key_ports *key, *mask; mask 52 include/net/flow_offload.h struct flow_dissector_key_icmp *key, *mask; mask 56 include/net/flow_offload.h struct flow_dissector_key_tcp *key, *mask; mask 60 include/net/flow_offload.h struct flow_dissector_key_mpls *key, *mask; mask 64 include/net/flow_offload.h struct flow_dissector_key_keyid *key, *mask; mask 68 include/net/flow_offload.h struct flow_dissector_key_enc_opts *key, *mask; mask 174 include/net/flow_offload.h u32 mask; mask 3936 include/net/mac80211.h const struct cfg80211_bitrate_mask *mask); mask 27 include/net/netfilter/nf_conntrack_expect.h struct nf_conntrack_tuple_mask mask; mask 44 include/net/netfilter/nf_conntrack_labels.h const u32 *data, const u32 *mask, unsigned int words); mask 158 include/net/netfilter/nf_conntrack_tuple.h const struct nf_conntrack_tuple_mask *mask) mask 164 include/net/netfilter/nf_conntrack_tuple.h mask->src.u3.all[count]) mask 168 include/net/netfilter/nf_conntrack_tuple.h if ((t1->src.u.all ^ t2->src.u.all) & mask->src.u.all) mask 181 include/net/netfilter/nf_conntrack_tuple.h const struct nf_conntrack_tuple_mask *mask) mask 183 include/net/netfilter/nf_conntrack_tuple.h return nf_ct_tuple_src_mask_cmp(t, tuple, mask) && mask 13 include/net/netfilter/nf_tables_offload.h struct nft_data mask; mask 53 include/net/netfilter/nf_tables_offload.h struct nft_flow_key mask; mask 76 include/net/netfilter/nf_tables_offload.h memset(&(__reg)->mask, 0xff, (__reg)->len); mask 406 include/net/netlabel.h const void *mask, mask 411 include/net/netlabel.h const void *mask, mask 416 include/net/netlabel.h const void *mask, mask 423 include/net/netlabel.h const void *mask, mask 432 include/net/netlabel.h const struct in_addr *mask, mask 440 include/net/netlabel.h const struct in6_addr *mask, mask 508 include/net/netlabel.h const void *mask, mask 516 include/net/netlabel.h void *mask, mask 524 include/net/netlabel.h const void *mask, mask 534 include/net/netlabel.h const void *mask, mask 553 include/net/netlabel.h const struct in_addr *mask, mask 571 include/net/netlabel.h const struct in6_addr *mask, mask 540 include/net/pkt_cls.h u32 mask; mask 111 include/net/rose.h unsigned short mask; mask 593 include/net/sch_generic.h static inline unsigned int qdisc_class_hash(u32 id, u32 mask) mask 597 include/net/sch_generic.h return id & mask; mask 13 include/net/tc_act/tc_nat.h __be32 mask; mask 55 include/net/tc_act/tc_pedit.h return to_pedit(a)->tcfp_keys[index].mask; mask 18 include/net/tc_act/tc_skbedit.h u32 mask; mask 74 include/net/udp.h unsigned int mask; mask 82 include/net/udp.h return &table->hash[udp_hashfn(net, num, table->mask)]; mask 91 include/net/udp.h return &table->hash2[hash & table->mask]; mask 823 include/net/xfrm.h __be32 mask; mask 825 include/net/xfrm.h mask = htonl((0xffffffff) << (32 - pbi)); mask 827 include/net/xfrm.h if ((a1[pdw] ^ a2[pdw]) & mask) mask 1870 include/rdma/ib_verbs.h struct ib_flow_eth_filter mask; mask 1884 include/rdma/ib_verbs.h struct ib_flow_ib_filter mask; mask 1909 include/rdma/ib_verbs.h struct ib_flow_ipv4_filter mask; mask 1927 include/rdma/ib_verbs.h struct ib_flow_ipv6_filter mask; mask 1941 include/rdma/ib_verbs.h struct ib_flow_tcp_udp_filter mask; mask 1956 include/rdma/ib_verbs.h struct ib_flow_tunnel_filter mask; mask 1970 include/rdma/ib_verbs.h struct ib_flow_esp_filter mask; mask 1985 include/rdma/ib_verbs.h struct ib_flow_gre_filter mask; mask 1998 include/rdma/ib_verbs.h struct ib_flow_mpls_filter mask; mask 2899 include/rdma/ib_verbs.h enum ib_qp_type type, enum ib_qp_attr_mask mask); mask 4167 include/rdma/ib_verbs.h const u32 mask = 0x000000ff; mask 4168 include/rdma/ib_verbs.h return ((rkey + 1) & mask) | (rkey & ~mask); mask 24 include/rdma/rdma_counter.h enum rdma_nl_counter_mask mask; mask 49 include/rdma/rdma_counter.h bool on, enum rdma_nl_counter_mask mask); mask 63 include/rdma/rdma_counter.h enum rdma_nl_counter_mask *mask); mask 809 include/scsi/scsi_host.h static inline void scsi_host_set_prot(struct Scsi_Host *shost, unsigned int mask) mask 811 include/scsi/scsi_host.h shost->prot_capabilities = mask; mask 45 include/soc/fsl/qe/ucc.h int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask); mask 416 include/soc/tegra/bpmp-abi.h uint32_t mask; mask 32 include/soc/tegra/mc.h unsigned int mask; mask 15 include/sound/ac97/codec.h .mask = (((mask_id1) & 0xffff) << 16) | ((mask_id2) & 0xffff), \ mask 31 include/sound/ac97/codec.h unsigned int mask; mask 324 include/sound/ac97_codec.h int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value); mask 358 include/sound/ac97_codec.h unsigned short mask; /* device id bit mask, 0 = accept all */ mask 304 include/sound/ak4113.h unsigned char mask, unsigned char val); mask 185 include/sound/ak4114.h void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); mask 172 include/sound/ak4117.h void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val); mask 76 include/sound/control.h unsigned int mask; mask 107 include/sound/control.h void snd_ctl_notify(struct snd_card * card, unsigned int mask, struct snd_ctl_elem_id * id); mask 397 include/sound/core.h #define _SND_PCI_QUIRK_ID_MASK(vend, mask, dev) \ mask 398 include/sound/core.h .subvendor = (vend), .subdevice = (dev), .subdevice_mask = (mask) mask 407 include/sound/core.h #define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ mask 408 include/sound/core.h {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), \ mask 414 include/sound/core.h #define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ mask 415 include/sound/core.h {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), .value = (val)} mask 26 include/sound/hda_regmap.h unsigned int mask, unsigned int val); mask 28 include/sound/hda_regmap.h unsigned int mask, unsigned int val); mask 98 include/sound/hda_regmap.h unsigned int verb, unsigned int mask, mask 103 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); mask 161 include/sound/hda_regmap.h int ch, int dir, int idx, int mask, int val) mask 165 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); mask 206 include/sound/hda_regmap.h int dir, int idx, int mask, int val) mask 210 include/sound/hda_regmap.h return snd_hdac_regmap_update_raw(codec, cmd, mask, val); mask 408 include/sound/hdaudio.h unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); mask 410 include/sound/hdaudio.h unsigned int mask); mask 414 include/sound/hdaudio.h #define snd_hdac_aligned_read(addr, mask) 0 mask 415 include/sound/hdaudio.h #define snd_hdac_aligned_write(val, addr, mask) do {} while (0) mask 482 include/sound/hdaudio.h #define snd_hdac_chip_updatel(chip, reg, mask, val) \ mask 484 include/sound/hdaudio.h (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) mask 485 include/sound/hdaudio.h #define snd_hdac_chip_updatew(chip, reg, mask, val) \ mask 487 include/sound/hdaudio.h (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) mask 488 include/sound/hdaudio.h #define snd_hdac_chip_updateb(chip, reg, mask, val) \ mask 490 include/sound/hdaudio.h (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) mask 586 include/sound/hdaudio.h #define snd_hdac_stream_updatel(dev, reg, mask, val) \ mask 589 include/sound/hdaudio.h ~(mask)) | (val)) mask 590 include/sound/hdaudio.h #define snd_hdac_stream_updatew(dev, reg, mask, val) \ mask 593 include/sound/hdaudio.h ~(mask)) | (val)) mask 594 include/sound/hdaudio.h #define snd_hdac_stream_updateb(dev, reg, mask, val) \ mask 597 include/sound/hdaudio.h ~(mask)) | (val)) mask 135 include/sound/hdaudio_ext.h #define snd_hdac_updatel(addr, reg, mask, val) \ mask 136 include/sound/hdaudio_ext.h writel(((readl(addr + reg) & ~(mask)) | (val)), \ mask 139 include/sound/hdaudio_ext.h #define snd_hdac_updatew(addr, reg, mask, val) \ mask 140 include/sound/hdaudio_ext.h writew(((readw(addr + reg) & ~(mask)) | (val)), \ mask 78 include/sound/jack.h int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask); mask 93 include/sound/jack.h static inline int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask) mask 281 include/sound/pcm.h unsigned int mask; mask 287 include/sound/pcm.h unsigned int mask; mask 960 include/sound/pcm.h const unsigned int *list, unsigned int mask); mask 962 include/sound/pcm.h const struct snd_interval *list, unsigned int mask); mask 973 include/sound/pcm.h u_int64_t mask); mask 31 include/sound/pcm_params.h static inline void snd_mask_none(struct snd_mask *mask) mask 33 include/sound/pcm_params.h memset(mask, 0, sizeof(*mask)); mask 36 include/sound/pcm_params.h static inline void snd_mask_any(struct snd_mask *mask) mask 38 include/sound/pcm_params.h memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t)); mask 41 include/sound/pcm_params.h static inline int snd_mask_empty(const struct snd_mask *mask) mask 45 include/sound/pcm_params.h if (mask->bits[i]) mask 50 include/sound/pcm_params.h static inline unsigned int snd_mask_min(const struct snd_mask *mask) mask 54 include/sound/pcm_params.h if (mask->bits[i]) mask 55 include/sound/pcm_params.h return __ffs(mask->bits[i]) + (i << 5); mask 60 include/sound/pcm_params.h static inline unsigned int snd_mask_max(const struct snd_mask *mask) mask 64 include/sound/pcm_params.h if (mask->bits[i]) mask 65 include/sound/pcm_params.h return __fls(mask->bits[i]) + (i << 5); mask 70 include/sound/pcm_params.h static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) mask 72 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] |= MASK_BIT(val); mask 76 include/sound/pcm_params.h static inline void snd_mask_set_format(struct snd_mask *mask, mask 79 include/sound/pcm_params.h snd_mask_set(mask, (__force unsigned int)format); mask 82 include/sound/pcm_params.h static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) mask 84 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); mask 87 include/sound/pcm_params.h static inline void snd_mask_set_range(struct snd_mask *mask, mask 92 include/sound/pcm_params.h mask->bits[MASK_OFS(i)] |= MASK_BIT(i); mask 95 include/sound/pcm_params.h static inline void snd_mask_reset_range(struct snd_mask *mask, mask 100 include/sound/pcm_params.h mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i); mask 103 include/sound/pcm_params.h static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) mask 106 include/sound/pcm_params.h v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); mask 107 include/sound/pcm_params.h snd_mask_none(mask); mask 108 include/sound/pcm_params.h mask->bits[MASK_OFS(val)] = v; mask 111 include/sound/pcm_params.h static inline void snd_mask_intersect(struct snd_mask *mask, mask 116 include/sound/pcm_params.h mask->bits[i] &= v->bits[i]; mask 119 include/sound/pcm_params.h static inline int snd_mask_eq(const struct snd_mask *mask, mask 122 include/sound/pcm_params.h return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t)); mask 125 include/sound/pcm_params.h static inline void snd_mask_copy(struct snd_mask *mask, mask 128 include/sound/pcm_params.h *mask = *v; mask 131 include/sound/pcm_params.h static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) mask 133 include/sound/pcm_params.h return mask->bits[MASK_OFS(val)] & MASK_BIT(val); mask 136 include/sound/pcm_params.h static inline int snd_mask_single(const struct snd_mask *mask) mask 140 include/sound/pcm_params.h if (! mask->bits[i]) mask 142 include/sound/pcm_params.h if (mask->bits[i] & (mask->bits[i] - 1)) mask 151 include/sound/pcm_params.h static inline int snd_mask_refine(struct snd_mask *mask, mask 155 include/sound/pcm_params.h snd_mask_copy(&old, mask); mask 156 include/sound/pcm_params.h snd_mask_intersect(mask, v); mask 157 include/sound/pcm_params.h if (snd_mask_empty(mask)) mask 159 include/sound/pcm_params.h return !snd_mask_eq(mask, &old); mask 162 include/sound/pcm_params.h static inline int snd_mask_refine_first(struct snd_mask *mask) mask 164 include/sound/pcm_params.h if (snd_mask_single(mask)) mask 166 include/sound/pcm_params.h snd_mask_leave(mask, snd_mask_min(mask)); mask 170 include/sound/pcm_params.h static inline int snd_mask_refine_last(struct snd_mask *mask) mask 172 include/sound/pcm_params.h if (snd_mask_single(mask)) mask 174 include/sound/pcm_params.h snd_mask_leave(mask, snd_mask_max(mask)); mask 178 include/sound/pcm_params.h static inline int snd_mask_refine_min(struct snd_mask *mask, unsigned int val) mask 180 include/sound/pcm_params.h if (snd_mask_min(mask) >= val) mask 182 include/sound/pcm_params.h snd_mask_reset_range(mask, 0, val - 1); mask 183 include/sound/pcm_params.h if (snd_mask_empty(mask)) mask 188 include/sound/pcm_params.h static inline int snd_mask_refine_max(struct snd_mask *mask, unsigned int val) mask 190 include/sound/pcm_params.h if (snd_mask_max(mask) <= val) mask 192 include/sound/pcm_params.h snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS); mask 193 include/sound/pcm_params.h if (snd_mask_empty(mask)) mask 198 include/sound/pcm_params.h static inline int snd_mask_refine_set(struct snd_mask *mask, unsigned int val) mask 201 include/sound/pcm_params.h changed = !snd_mask_single(mask); mask 202 include/sound/pcm_params.h snd_mask_leave(mask, val); mask 203 include/sound/pcm_params.h if (snd_mask_empty(mask)) mask 208 include/sound/pcm_params.h static inline int snd_mask_value(const struct snd_mask *mask) mask 210 include/sound/pcm_params.h return snd_mask_min(mask); mask 324 include/sound/sb.h #define SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) \ mask 325 include/sound/sb.h ((left_reg) | ((right_reg) << 8) | ((left_shift) << 16) | ((right_shift) << 19) | ((mask) << 24)) mask 326 include/sound/sb.h #define SB_MIXVAL_SINGLE(reg, shift, mask) \ mask 327 include/sound/sb.h ((reg) | ((shift) << 16) | ((mask) << 24)) mask 340 include/sound/sb.h #define SB_SINGLE(xname, reg, shift, mask) \ mask 343 include/sound/sb.h .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) } mask 345 include/sound/sb.h #define SB_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask) \ mask 348 include/sound/sb.h .private_value = SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) } mask 264 include/sound/soc-component.h unsigned int reg, unsigned int mask, mask 267 include/sound/soc-component.h unsigned int reg, unsigned int mask, mask 271 include/sound/soc-component.h unsigned int reg, unsigned int mask, mask 76 include/sound/soc-dapm.h .reg = wreg, .mask = 1, .shift = wshift, \ mask 258 include/sound/soc-dapm.h .reg = wreg, .shift = wshift, .mask = wmask, \ mask 608 include/sound/soc-dapm.h unsigned int mask; /* non-shifted mask */ mask 652 include/sound/soc-dapm.h int mask; mask 201 include/sound/soc.h .mask = xitems ? roundup_pow_of_two(xitems) - 1 : 0} mask 208 include/sound/soc.h .mask = xmask, .items = xitems, .texts = xtexts, .values = xvalues} mask 213 include/sound/soc.h .mask = xmask, .items = xitems, .texts = xtexts, \ mask 309 include/sound/soc.h .mask = xmask }) } mask 498 include/sound/soc.h void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask); mask 636 include/sound/soc.h int mask; mask 1178 include/sound/soc.h u32 mask; mask 1204 include/sound/soc.h unsigned int mask; mask 1285 include/sound/soc.h unsigned int *mask); mask 266 include/sound/vx_core.h int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); mask 267 include/sound/vx_core.h #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) mask 162 include/sound/wss.h #define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 169 include/sound/wss.h .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 178 include/sound/wss.h #define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 186 include/sound/wss.h (shift_right << 19) | (mask << 24) | (invert << 22) } mask 188 include/sound/wss.h #define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ mask 196 include/sound/wss.h .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ mask 200 include/sound/wss.h shift_left, shift_right, mask, invert, xtlv) \ mask 209 include/sound/wss.h (shift_right << 19) | (mask << 24) | (invert << 22), \ mask 229 include/trace/events/asoc.h TP_PROTO(struct snd_soc_jack *jack, int mask, int val), mask 231 include/trace/events/asoc.h TP_ARGS(jack, mask, val), mask 235 include/trace/events/asoc.h __field( int, mask ) mask 241 include/trace/events/asoc.h __entry->mask = mask; mask 246 include/trace/events/asoc.h (int)__entry->mask) mask 1321 include/trace/events/btrfs.h gfp_t mask, unsigned long IP), mask 1323 include/trace/events/btrfs.h TP_ARGS(state, mask, IP), mask 1327 include/trace/events/btrfs.h __field(gfp_t, mask) mask 1333 include/trace/events/btrfs.h __entry->mask = mask, mask 1338 include/trace/events/btrfs.h show_gfp_flags(__entry->mask), (const void *)__entry->ip) mask 23 include/trace/events/hswadsp.h TP_PROTO(uint32_t status, uint32_t mask), mask 25 include/trace/events/hswadsp.h TP_ARGS(status, mask), mask 29 include/trace/events/hswadsp.h __field( unsigned int, mask ) mask 34 include/trace/events/hswadsp.h __entry->mask = mask; mask 38 include/trace/events/hswadsp.h (unsigned int)__entry->status, (unsigned int)__entry->mask) mask 43 include/trace/events/hswadsp.h TP_PROTO(unsigned int status, unsigned int mask), mask 45 include/trace/events/hswadsp.h TP_ARGS(status, mask) mask 51 include/trace/events/hswadsp.h TP_PROTO(unsigned int status, unsigned int mask), mask 53 include/trace/events/hswadsp.h TP_ARGS(status, mask) mask 21 include/trace/events/ipi.h TP_PROTO(const struct cpumask *mask, const char *reason), mask 23 include/trace/events/ipi.h TP_ARGS(mask, reason), mask 31 include/trace/events/ipi.h __assign_bitmask(target_cpus, cpumask_bits(mask), nr_cpumask_bits); mask 363 include/trace/events/rcu.h unsigned long mask, unsigned long qsmask, mask 366 include/trace/events/rcu.h TP_ARGS(rcuname, gp_seq, mask, qsmask, level, grplo, grphi, gp_tasks), mask 371 include/trace/events/rcu.h __field(unsigned long, mask) mask 382 include/trace/events/rcu.h __entry->mask = mask; mask 392 include/trace/events/rcu.h __entry->mask, __entry->qsmask, __entry->level, mask 301 include/uapi/drm/r128_drm.h unsigned char __user *mask; mask 305 include/uapi/drm/r128_drm.h unsigned int __user *mask; mask 686 include/uapi/drm/radeon_drm.h unsigned int __user *mask; mask 211 include/uapi/drm/savage_drm.h unsigned int mask; mask 358 include/uapi/drm/vmwgfx_drm.h __u32 mask; mask 454 include/uapi/linux/audit.h __u32 mask; /* Bit mask for valid entries */ mask 472 include/uapi/linux/audit.h __u32 mask; /* which bits we are dealing with */ mask 500 include/uapi/linux/audit.h __u32 mask[AUDIT_BITMASK_SIZE]; /* syscall(s) affected */ mask 91 include/uapi/linux/can/netlink.h __u32 mask; mask 151 include/uapi/linux/dvb/dmx.h __u8 mask[DMX_FILTER_SIZE]; mask 113 include/uapi/linux/fanotify.h __aligned_u64 mask; mask 391 include/uapi/linux/fb.h const char *mask; /* cursor mask bits */ mask 22 include/uapi/linux/fsi.h __u64 mask; /* Data mask for writes */ mask 678 include/uapi/linux/fuse.h uint32_t mask; mask 382 include/uapi/linux/if_link.h __u32 mask; mask 1028 include/uapi/linux/if_link.h __u32 mask; mask 29 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_TYPE(mask) ((mask >> 56) & 0xFF) mask 31 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_DIR(mask) ((mask >> 48) & 0x7F) mask 33 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_CHAN_TYPE(mask) ((mask >> 32) & 0xFF) mask 37 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_CHAN(mask) ((__s16)(mask & 0xFFFF)) mask 38 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_CHAN2(mask) ((__s16)(((mask) >> 16) & 0xFFFF)) mask 40 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_MODIFIER(mask) ((mask >> 40) & 0xFF) mask 41 include/uapi/linux/iio/events.h #define IIO_EVENT_CODE_EXTRACT_DIFF(mask) (((mask) >> 55) & 0x1) mask 108 include/uapi/linux/inet_diag.h __u32 mask; mask 23 include/uapi/linux/inotify.h __u32 mask; /* watch mask */ mask 304 include/uapi/linux/ip_vs.h __u32 mask; mask 11 include/uapi/linux/kernel.h #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) mask 183 include/uapi/linux/kvm.h __u64 mask; mask 544 include/uapi/linux/kvm.h __u64 mask; mask 54 include/uapi/linux/netfilter/nf_conntrack_tcp.h __u8 mask; mask 17 include/uapi/linux/netfilter/xt_connlimit.h union nf_inet_addr mask; mask 38 include/uapi/linux/netfilter/xt_connmark.h __u32 mark, mask; mask 8 include/uapi/linux/netfilter/xt_mark.h __u32 mark, mask; mask 12 include/uapi/linux/netfilter/xt_mark.h __u32 mark, mask; mask 9 include/uapi/linux/netfilter/xt_realm.h __u32 mask; mask 44 include/uapi/linux/netfilter/xt_recent.h union nf_inet_addr mask; mask 40 include/uapi/linux/netfilter_arp/arp_tables.h char mask[ARPT_DEV_ADDR_LEN_MAX]; mask 11 include/uapi/linux/netfilter_bridge/ebt_mark_m.h unsigned long mark, mask; mask 3011 include/uapi/linux/nl80211.h __u32 mask; mask 25 include/uapi/linux/phantom.h __u32 mask; mask 208 include/uapi/linux/pkt_cls.h __be32 mask; mask 230 include/uapi/linux/pkt_cls.h __u32 mask; mask 267 include/uapi/linux/pkt_cls.h __u32 mask; mask 35 include/uapi/linux/ppdev.h unsigned char mask; mask 115 include/uapi/linux/rio_mport_cdev.h __u32 mask; mask 68 include/uapi/linux/rose.h unsigned short mask; mask 23 include/uapi/linux/tc_act/tc_nat.h __be32 mask; mask 53 include/uapi/linux/tc_act/tc_pedit.h __u32 mask; /* AND */ mask 10 include/uapi/linux/tc_ematch/tc_em_cmp.h __u32 mask; mask 854 include/uapi/linux/vfio.h __u64 mask; mask 928 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_eth_filter mask; mask 950 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_ipv4_filter mask; mask 968 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_tcp_udp_filter mask; mask 991 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_ipv6_filter mask; mask 1058 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_tunnel_filter mask; mask 1076 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_spec_esp_filter mask; mask 1103 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_gre_filter mask; mask 1126 include/uapi/rdma/ib_user_verbs.h struct ib_uverbs_flow_mpls_filter mask; mask 448 include/uapi/rdma/mlx5-abi.h __aligned_u64 mask; mask 139 include/uapi/rdma/rdma_user_rxe.h __u32 mask; mask 418 include/uapi/sound/asoc.h __le32 mask; mask 439 include/uapi/sound/asoc.h __le32 mask; mask 486 include/uapi/sound/asoc.h __le32 mask; /* non-shifted mask */ mask 1013 include/uapi/sound/asound.h unsigned int mask; mask 64 include/vdso/datapage.h u64 mask; mask 89 include/video/mbxfb.h __u32 mask; /* which bits to touch (for write) */ mask 743 include/video/omapfb_dss.h typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); mask 798 include/video/omapfb_dss.h int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); mask 799 include/video/omapfb_dss.h int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); mask 836 include/video/omapfb_dss.h void *arg, u32 mask) mask 840 include/video/omapfb_dss.h void *arg, u32 mask) mask 2008 ipc/sem.c unsigned long mask = 1ULL << ((sop->sem_num) % BITS_PER_LONG); mask 2014 ipc/sem.c if (dup & mask) { mask 2025 ipc/sem.c dup |= mask; mask 158 kernel/audit.c .mask = -1, mask 1116 kernel/audit.c if (!(feature & uaf->mask)) mask 1137 kernel/audit.c if (!(feature & uaf->mask)) mask 1214 kernel/audit.c if (s.mask & AUDIT_STATUS_ENABLED) { mask 1219 kernel/audit.c if (s.mask & AUDIT_STATUS_FAILURE) { mask 1224 kernel/audit.c if (s.mask & AUDIT_STATUS_PID) { mask 1284 kernel/audit.c if (s.mask & AUDIT_STATUS_RATE_LIMIT) { mask 1289 kernel/audit.c if (s.mask & AUDIT_STATUS_BACKLOG_LIMIT) { mask 1294 kernel/audit.c if (s.mask & AUDIT_STATUS_BACKLOG_WAIT_TIME) { mask 1303 kernel/audit.c if (s.mask == AUDIT_STATUS_LOST) { mask 98 kernel/audit_fsnotify.c audit_mark->mark.mask = AUDIT_FS_EVENTS; mask 157 kernel/audit_fsnotify.c u32 mask, const void *data, int data_type, mask 181 kernel/audit_fsnotify.c if (mask & (FS_CREATE|FS_MOVED_TO|FS_DELETE|FS_MOVED_FROM)) { mask 185 kernel/audit_fsnotify.c } else if (mask & (FS_DELETE_SELF|FS_UNMOUNT|FS_MOVE_SELF)) mask 184 kernel/audit_tree.c amark->mark.mask = FS_IN_IGNORED; mask 1042 kernel/audit_tree.c u32 mask, const void *data, int data_type, mask 149 kernel/audit_watch.c parent->mark.mask = AUDIT_FS_WATCH; mask 471 kernel/audit_watch.c u32 mask, const void *data, int data_type, mask 496 kernel/audit_watch.c if (mask & (FS_CREATE|FS_MOVED_TO) && inode) mask 498 kernel/audit_watch.c else if (mask & (FS_DELETE|FS_MOVED_FROM)) mask 500 kernel/audit_watch.c else if (mask & (FS_DELETE_SELF|FS_UNMOUNT|FS_MOVE_SELF)) mask 196 kernel/auditfilter.c static inline int audit_match_class_bits(int class, u32 *mask) mask 202 kernel/auditfilter.c if (mask[i] & classes[class][i]) mask 216 kernel/auditfilter.c entry->rule.mask) && mask 218 kernel/auditfilter.c entry->rule.mask)); mask 224 kernel/auditfilter.c entry->rule.mask)); mask 227 kernel/auditfilter.c entry->rule.mask)); mask 278 kernel/auditfilter.c entry->rule.mask[i] = rule->mask[i]; mask 282 kernel/auditfilter.c __u32 *p = &entry->rule.mask[AUDIT_WORD(bit)]; mask 292 kernel/auditfilter.c entry->rule.mask[j] |= class[j]; mask 689 kernel/auditfilter.c for (i = 0; i < AUDIT_BITMASK_SIZE; i++) data->mask[i] = krule->mask[i]; mask 771 kernel/auditfilter.c if (a->mask[i] != b->mask[i]) mask 829 kernel/auditfilter.c new->mask[i] = old->mask[i]; mask 133 kernel/auditsc.c static int audit_match_perm(struct audit_context *ctx, int mask) mask 142 kernel/auditsc.c if ((mask & AUDIT_PERM_WRITE) && mask 145 kernel/auditsc.c if ((mask & AUDIT_PERM_READ) && mask 148 kernel/auditsc.c if ((mask & AUDIT_PERM_ATTR) && mask 153 kernel/auditsc.c if ((mask & AUDIT_PERM_WRITE) && mask 156 kernel/auditsc.c if ((mask & AUDIT_PERM_READ) && mask 159 kernel/auditsc.c if ((mask & AUDIT_PERM_ATTR) && mask 164 kernel/auditsc.c return mask & ACC_MODE(ctx->argv[1]); mask 166 kernel/auditsc.c return mask & ACC_MODE(ctx->argv[2]); mask 168 kernel/auditsc.c return ((mask & AUDIT_PERM_WRITE) && ctx->argv[0] == SYS_BIND); mask 170 kernel/auditsc.c return mask & AUDIT_PERM_EXEC; mask 772 kernel/auditsc.c return rule->mask[word] & bit; mask 12 kernel/bpf/tnum.c #define TNUM(_v, _m) (struct tnum){.value = _v, .mask = _m} mask 14 kernel/bpf/tnum.c const struct tnum tnum_unknown = { .value = 0, .mask = -1 }; mask 39 kernel/bpf/tnum.c return TNUM(a.value << shift, a.mask << shift); mask 44 kernel/bpf/tnum.c return TNUM(a.value >> shift, a.mask >> shift); mask 56 kernel/bpf/tnum.c (u32)(((s32)a.mask) >> min_shift)); mask 59 kernel/bpf/tnum.c (s64)a.mask >> min_shift); mask 66 kernel/bpf/tnum.c sm = a.mask + b.mask; mask 70 kernel/bpf/tnum.c mu = chi | a.mask | b.mask; mask 79 kernel/bpf/tnum.c alpha = dv + a.mask; mask 80 kernel/bpf/tnum.c beta = dv - b.mask; mask 82 kernel/bpf/tnum.c mu = chi | a.mask | b.mask; mask 90 kernel/bpf/tnum.c alpha = a.value | a.mask; mask 91 kernel/bpf/tnum.c beta = b.value | b.mask; mask 101 kernel/bpf/tnum.c mu = a.mask | b.mask; mask 110 kernel/bpf/tnum.c mu = a.mask | b.mask; mask 117 kernel/bpf/tnum.c static struct tnum hma(struct tnum acc, u64 value, u64 mask) mask 119 kernel/bpf/tnum.c while (mask) { mask 120 kernel/bpf/tnum.c if (mask & 1) mask 122 kernel/bpf/tnum.c mask >>= 1; mask 134 kernel/bpf/tnum.c acc = hma(TNUM(pi, 0), a.mask, b.mask | b.value); mask 135 kernel/bpf/tnum.c return hma(acc, b.mask, a.value); mask 146 kernel/bpf/tnum.c mu = a.mask & b.mask; mask 153 kernel/bpf/tnum.c a.mask &= (1ULL << (size * 8)) - 1; mask 161 kernel/bpf/tnum.c return !((a.value | a.mask) & (size - 1)); mask 166 kernel/bpf/tnum.c if (b.mask & ~a.mask) mask 168 kernel/bpf/tnum.c b.value &= ~a.mask; mask 174 kernel/bpf/tnum.c return snprintf(str, size, "(%#llx; %#llx)", a.value, a.mask); mask 184 kernel/bpf/tnum.c if (a.mask & 1) mask 191 kernel/bpf/tnum.c a.mask >>= 1; mask 929 kernel/bpf/verifier.c reg->var_off.value | (reg->var_off.mask & S64_MIN)); mask 932 kernel/bpf/verifier.c reg->var_off.value | (reg->var_off.mask & S64_MAX)); mask 935 kernel/bpf/verifier.c reg->var_off.value | reg->var_off.mask); mask 1715 kernel/bpf/verifier.c DECLARE_BITMAP(mask, 64); mask 1760 kernel/bpf/verifier.c bitmap_from_u64(mask, reg_mask); mask 1761 kernel/bpf/verifier.c for_each_set_bit(i, mask, 32) { mask 1772 kernel/bpf/verifier.c bitmap_from_u64(mask, stack_mask); mask 1773 kernel/bpf/verifier.c for_each_set_bit(i, mask, 64) { mask 2734 kernel/bpf/verifier.c u64 mask; mask 2740 kernel/bpf/verifier.c mask = ((u64)1 << (size * 8)) - 1; mask 2741 kernel/bpf/verifier.c if ((reg->umin_value & ~mask) == (reg->umax_value & ~mask)) { mask 2742 kernel/bpf/verifier.c reg->umin_value &= mask; mask 2743 kernel/bpf/verifier.c reg->umax_value &= mask; mask 2746 kernel/bpf/verifier.c reg->umax_value = mask; mask 4765 kernel/bpf/verifier.c dst_reg->var_off.mask; mask 5280 kernel/bpf/verifier.c if ((~reg->var_off.mask & reg->var_off.value) & val) mask 5282 kernel/bpf/verifier.c if (!((reg->var_off.mask | reg->var_off.value) & val)) mask 5347 kernel/bpf/verifier.c return (var.value | var.mask) & ~0xffffffffULL; mask 5384 kernel/bpf/verifier.c t.mask |= ~0xffffffffULL; /* upper half is unknown */ mask 5416 kernel/bpf/verifier.c t.mask |= ~0xffffffffULL; /* upper half is unknown */ mask 5464 kernel/bpf/verifier.c reg->var_off.mask &= hi_mask; mask 5562 kernel/bpf/verifier.c reg->var_off.mask &= hi_mask; mask 990 kernel/cgroup/cgroup-v1.c u16 mask = U16_MAX; mask 996 kernel/cgroup/cgroup-v1.c mask = ~((u16)1 << cpuset_cgrp_id); mask 1031 kernel/cgroup/cgroup-v1.c if ((ctx->flags & CGRP_ROOT_NOPREFIX) && (ctx->subsys_mask & mask)) mask 3341 kernel/cgroup/cpuset.c nodemask_t mask; mask 3346 kernel/cgroup/cpuset.c guarantee_online_mems(task_cs(tsk), &mask); mask 3350 kernel/cgroup/cpuset.c return mask; mask 237 kernel/cgroup/debug.c u16 mask) mask 245 kernel/cgroup/debug.c if (!(mask & (1 << ssid))) mask 236 kernel/compat.c cpumask_var_t mask; mask 243 kernel/compat.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 246 kernel/compat.c ret = sched_getaffinity(pid, mask); mask 250 kernel/compat.c if (compat_put_bitmap(user_mask_ptr, cpumask_bits(mask), retlen * 8)) mask 255 kernel/compat.c free_cpumask_var(mask); mask 281 kernel/compat.c long compat_get_bitmap(unsigned long *mask, const compat_ulong_t __user *umask, mask 297 kernel/compat.c *mask++ = ((unsigned long)l2 << BITS_PER_COMPAT_LONG) | l1; mask 301 kernel/compat.c unsafe_get_user(*mask, umask++, Efault); mask 310 kernel/compat.c long compat_put_bitmap(compat_ulong_t __user *umask, unsigned long *mask, mask 323 kernel/compat.c unsigned long m = *mask++; mask 329 kernel/compat.c unsafe_put_user((compat_ulong_t)*mask, umask++, Efault); mask 81 kernel/debug/kdb/kdb_bt.c kdb_bt1(struct task_struct *p, unsigned long mask, mask 88 kernel/debug/kdb/kdb_bt.c if (!kdb_task_state(p, mask)) mask 121 kernel/debug/kdb/kdb_bt.c unsigned long mask = kdb_task_state_string(argc ? argv[1] : mask 128 kernel/debug/kdb/kdb_bt.c if (kdb_bt1(p, mask, argcount, btaprompt)) mask 137 kernel/debug/kdb/kdb_bt.c if (kdb_bt1(p, mask, argcount, btaprompt)) mask 2350 kernel/debug/kdb/kdb_main.c unsigned long mask, cpu; mask 2357 kernel/debug/kdb/kdb_main.c mask = kdb_task_state_string(argc ? argv[1] : NULL); mask 2363 kernel/debug/kdb/kdb_main.c if (kdb_task_state(p, mask)) mask 2371 kernel/debug/kdb/kdb_main.c if (kdb_task_state(p, mask)) mask 207 kernel/debug/kdb/kdb_private.h unsigned long mask); mask 661 kernel/debug/kdb/kdb_support.c unsigned long kdb_task_state(const struct task_struct *p, unsigned long mask) mask 664 kernel/debug/kdb/kdb_support.c return (mask & kdb_task_state_string(state)) != 0; mask 302 kernel/dma/contiguous.c phys_addr_t mask = align - 1; mask 311 kernel/dma/contiguous.c if ((rmem->base & mask) || (rmem->size & mask)) { mask 394 kernel/dma/direct.c int dma_direct_supported(struct device *dev, u64 mask) mask 410 kernel/dma/direct.c return mask >= __phys_to_dma(dev, min_mask); mask 28 kernel/dma/dummy.c static int dma_dummy_supported(struct device *hwdev, u64 mask) mask 350 kernel/dma/mapping.c int dma_supported(struct device *dev, u64 mask) mask 355 kernel/dma/mapping.c return dma_direct_supported(dev, mask); mask 358 kernel/dma/mapping.c return ops->dma_supported(dev, mask); mask 363 kernel/dma/mapping.c void arch_dma_set_mask(struct device *dev, u64 mask); mask 365 kernel/dma/mapping.c #define arch_dma_set_mask(dev, mask) do { } while (0) mask 368 kernel/dma/mapping.c int dma_set_mask(struct device *dev, u64 mask) mask 374 kernel/dma/mapping.c mask = (dma_addr_t)mask; mask 376 kernel/dma/mapping.c if (!dev->dma_mask || !dma_supported(dev, mask)) mask 379 kernel/dma/mapping.c arch_dma_set_mask(dev, mask); mask 380 kernel/dma/mapping.c *dev->dma_mask = mask; mask 386 kernel/dma/mapping.c int dma_set_coherent_mask(struct device *dev, u64 mask) mask 392 kernel/dma/mapping.c mask = (dma_addr_t)mask; mask 394 kernel/dma/mapping.c if (!dma_supported(dev, mask)) mask 397 kernel/dma/mapping.c dev->coherent_dma_mask = mask; mask 457 kernel/dma/swiotlb.c unsigned long mask; mask 474 kernel/dma/swiotlb.c mask = dma_get_seg_boundary(hwdev); mask 476 kernel/dma/swiotlb.c tbl_dma_addr &= mask; mask 483 kernel/dma/swiotlb.c max_slots = mask + 1 mask 484 kernel/dma/swiotlb.c ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT mask 6054 kernel/events/core.c struct pt_regs *regs, u64 mask) mask 6059 kernel/events/core.c bitmap_from_u64(_mask, mask); mask 6060 kernel/events/core.c for_each_set_bit(bit, _mask, sizeof(mask) * BITS_PER_BYTE) { mask 6467 kernel/events/core.c u64 mask = event->attr.sample_regs_user; mask 6470 kernel/events/core.c mask); mask 6498 kernel/events/core.c u64 mask = event->attr.sample_regs_intr; mask 6502 kernel/events/core.c mask); mask 6651 kernel/events/core.c u64 mask = event->attr.sample_regs_user; mask 6652 kernel/events/core.c size += hweight64(mask) * sizeof(u64); mask 6690 kernel/events/core.c u64 mask = event->attr.sample_regs_intr; mask 6692 kernel/events/core.c size += hweight64(mask) * sizeof(u64); mask 10678 kernel/events/core.c u64 mask = attr->branch_sample_type; mask 10681 kernel/events/core.c if (mask & ~(PERF_SAMPLE_BRANCH_MAX-1)) mask 10685 kernel/events/core.c if (!(mask & ~PERF_SAMPLE_BRANCH_PLM_ALL)) mask 10689 kernel/events/core.c if (!(mask & PERF_SAMPLE_BRANCH_PLM_ALL)) { mask 10693 kernel/events/core.c mask |= PERF_SAMPLE_BRANCH_KERNEL; mask 10696 kernel/events/core.c mask |= PERF_SAMPLE_BRANCH_USER; mask 10699 kernel/events/core.c mask |= PERF_SAMPLE_BRANCH_HV; mask 10703 kernel/events/core.c attr->branch_sample_type = mask; mask 10706 kernel/events/core.c if ((mask & PERF_SAMPLE_BRANCH_PERM_PLM) mask 84 kernel/irq/affinity.c const struct cpumask *mask, nodemask_t *nodemsk) mask 90 kernel/irq/affinity.c if (cpumask_intersects(mask, node_to_cpumask[n])) { mask 272 kernel/irq/affinity.c cpumask_or(&masks[curvec].mask, &masks[curvec].mask, mask 324 kernel/irq/affinity.c irq_spread_init_one(&masks[curvec].mask, nmsk, mask 455 kernel/irq/affinity.c cpumask_copy(&masks[curvec].mask, irq_default_affinity); mask 481 kernel/irq/affinity.c cpumask_copy(&masks[curvec].mask, irq_default_affinity); mask 33 kernel/irq/autoprobe.c unsigned long mask = 0; mask 96 kernel/irq/autoprobe.c mask |= 1 << i; mask 101 kernel/irq/autoprobe.c return mask; mask 119 kernel/irq/autoprobe.c unsigned int mask = 0; mask 127 kernel/irq/autoprobe.c mask |= 1 << i; mask 136 kernel/irq/autoprobe.c return mask & val; mask 302 kernel/irq/chip.c static void __irq_disable(struct irq_desc *desc, bool mask); mask 347 kernel/irq/chip.c static void __irq_disable(struct irq_desc *desc, bool mask) mask 350 kernel/irq/chip.c if (mask) mask 357 kernel/irq/chip.c } else if (mask) { mask 504 kernel/irq/chip.c unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED; mask 510 kernel/irq/chip.c if (!irqd_has_set(&desc->irq_data, mask)) mask 13 kernel/irq/debugfs.c unsigned int mask; mask 16 kernel/irq/debugfs.c #define BIT_MASK_DESCR(m) { .mask = m, .name = #m } mask 24 kernel/irq/debugfs.c if (state & sd->mask) mask 40 kernel/irq/generic-chip.c u32 mask = d->mask; mask 43 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.disable); mask 44 kernel/irq/generic-chip.c *ct->mask_cache &= ~mask; mask 59 kernel/irq/generic-chip.c u32 mask = d->mask; mask 62 kernel/irq/generic-chip.c *ct->mask_cache |= mask; mask 63 kernel/irq/generic-chip.c irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); mask 79 kernel/irq/generic-chip.c u32 mask = d->mask; mask 82 kernel/irq/generic-chip.c *ct->mask_cache &= ~mask; mask 83 kernel/irq/generic-chip.c irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); mask 99 kernel/irq/generic-chip.c u32 mask = d->mask; mask 102 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.enable); mask 103 kernel/irq/generic-chip.c *ct->mask_cache |= mask; mask 115 kernel/irq/generic-chip.c u32 mask = d->mask; mask 118 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.ack); mask 131 kernel/irq/generic-chip.c u32 mask = ~d->mask; mask 134 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.ack); mask 154 kernel/irq/generic-chip.c u32 mask = d->mask; mask 157 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.disable); mask 158 kernel/irq/generic-chip.c *ct->mask_cache &= ~mask; mask 159 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.ack); mask 171 kernel/irq/generic-chip.c u32 mask = d->mask; mask 174 kernel/irq/generic-chip.c irq_reg_writel(gc, mask, ct->regs.eoi); mask 190 kernel/irq/generic-chip.c u32 mask = d->mask; mask 192 kernel/irq/generic-chip.c if (!(mask & gc->wake_enabled)) mask 197 kernel/irq/generic-chip.c gc->wake_active |= mask; mask 199 kernel/irq/generic-chip.c gc->wake_active &= ~mask; mask 257 kernel/irq/generic-chip.c u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; mask 263 kernel/irq/generic-chip.c mskreg = ct[i].regs.mask; mask 420 kernel/irq/generic-chip.c data->mask = 1 << idx; mask 494 kernel/irq/generic-chip.c d->mask = 1 << (i - gc->irq_base); mask 223 kernel/irq/internals.h static inline void irqd_clear(struct irq_data *d, unsigned int mask) mask 225 kernel/irq/internals.h __irqd_to_state(d) &= ~mask; mask 228 kernel/irq/internals.h static inline void irqd_set(struct irq_data *d, unsigned int mask) mask 230 kernel/irq/internals.h __irqd_to_state(d) |= mask; mask 233 kernel/irq/internals.h static inline bool irqd_has_set(struct irq_data *d, unsigned int mask) mask 235 kernel/irq/internals.h return __irqd_to_state(d) & mask; mask 415 kernel/irq/internals.h irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) mask 417 kernel/irq/internals.h cpumask_copy(desc->pending_mask, mask); mask 420 kernel/irq/internals.h irq_get_pending(struct cpumask *mask, struct irq_desc *desc) mask 422 kernel/irq/internals.h cpumask_copy(mask, desc->pending_mask); mask 439 kernel/irq/internals.h irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) mask 443 kernel/irq/internals.h irq_get_pending(struct cpumask *mask, struct irq_desc *desc) mask 476 kernel/irq/irqdesc.c if (cpumask_empty(&affinity[i].mask)) mask 482 kernel/irq/irqdesc.c const struct cpumask *mask = NULL; mask 490 kernel/irq/irqdesc.c mask = &affinity->mask; mask 491 kernel/irq/irqdesc.c node = cpu_to_node(cpumask_first(mask)); mask 495 kernel/irq/irqdesc.c desc = alloc_desc(start + i, node, flags, mask, owner); mask 1452 kernel/irq/irqdomain.c root_irq_data->mask = 0; mask 210 kernel/irq/manage.c int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, mask 220 kernel/irq/manage.c ret = chip->irq_set_affinity(data, mask, force); mask 224 kernel/irq/manage.c cpumask_copy(desc->irq_common_data.affinity, mask); mask 268 kernel/irq/manage.c int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, mask 279 kernel/irq/manage.c ret = irq_try_set_affinity(data, mask, force); mask 282 kernel/irq/manage.c irq_copy_pending(desc, mask); mask 298 kernel/irq/manage.c int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) mask 308 kernel/irq/manage.c ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); mask 411 kernel/irq/manage.c static struct cpumask mask; mask 431 kernel/irq/manage.c cpumask_and(&mask, cpu_online_mask, set); mask 432 kernel/irq/manage.c if (cpumask_empty(&mask)) mask 433 kernel/irq/manage.c cpumask_copy(&mask, cpu_online_mask); mask 439 kernel/irq/manage.c if (cpumask_intersects(&mask, nodemask)) mask 440 kernel/irq/manage.c cpumask_and(&mask, &mask, nodemask); mask 442 kernel/irq/manage.c ret = irq_do_set_affinity(&desc->irq_data, &mask, false); mask 941 kernel/irq/manage.c cpumask_var_t mask; mask 951 kernel/irq/manage.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { mask 965 kernel/irq/manage.c cpumask_copy(mask, m); mask 972 kernel/irq/manage.c set_cpus_allowed_ptr(current, mask); mask 973 kernel/irq/manage.c free_cpumask_var(mask); mask 102 kernel/irq/msi.c const struct cpumask *mask, bool force) mask 108 kernel/irq/msi.c ret = parent->chip->irq_set_affinity(parent, mask, force); mask 49 kernel/irq/proc.c const struct cpumask *mask; mask 54 kernel/irq/proc.c mask = desc->irq_common_data.affinity; mask 57 kernel/irq/proc.c mask = desc->pending_mask; mask 63 kernel/irq/proc.c mask = irq_data_get_effective_affinity_mask(&desc->irq_data); mask 73 kernel/irq/proc.c seq_printf(m, "%*pbl\n", cpumask_pr_args(mask)); mask 77 kernel/irq/proc.c seq_printf(m, "%*pb\n", cpumask_pr_args(mask)); mask 87 kernel/irq/proc.c cpumask_var_t mask; mask 89 kernel/irq/proc.c if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) mask 94 kernel/irq/proc.c cpumask_copy(mask, desc->affinity_hint); mask 97 kernel/irq/proc.c seq_printf(m, "%*pb\n", cpumask_pr_args(mask)); mask 98 kernel/irq/proc.c free_cpumask_var(mask); mask 75 kernel/irq/settings.h irq_settings_set_trigger_mask(struct irq_desc *desc, u32 mask) mask 78 kernel/irq/settings.h desc->status_use_accessors |= mask & IRQ_TYPE_SENSE_MASK; mask 395 kernel/kthread.c static void __kthread_bind_mask(struct task_struct *p, const struct cpumask *mask, long state) mask 406 kernel/kthread.c do_set_cpus_allowed(p, mask); mask 416 kernel/kthread.c void kthread_bind_mask(struct task_struct *p, const struct cpumask *mask) mask 418 kernel/kthread.c __kthread_bind_mask(p, mask, TASK_UNINTERRUPTIBLE); mask 1852 kernel/locking/lockdep.c static inline int usage_accumulate(struct lock_list *entry, void *mask) mask 1854 kernel/locking/lockdep.c *(unsigned long *)mask |= entry->class->usage_mask; mask 1865 kernel/locking/lockdep.c static inline int usage_match(struct lock_list *entry, void *mask) mask 1867 kernel/locking/lockdep.c return entry->class->usage_mask & *(unsigned long *)mask; mask 2155 kernel/locking/lockdep.c static unsigned long invert_dir_mask(unsigned long mask) mask 2160 kernel/locking/lockdep.c excl |= (mask & LOCKF_ENABLED_IRQ_ALL) >> LOCK_USAGE_DIR_MASK; mask 2161 kernel/locking/lockdep.c excl |= (mask & LOCKF_USED_IN_IRQ_ALL) << LOCK_USAGE_DIR_MASK; mask 2171 kernel/locking/lockdep.c static unsigned long exclusive_mask(unsigned long mask) mask 2173 kernel/locking/lockdep.c unsigned long excl = invert_dir_mask(mask); mask 2189 kernel/locking/lockdep.c static unsigned long original_mask(unsigned long mask) mask 2191 kernel/locking/lockdep.c unsigned long excl = invert_dir_mask(mask); mask 2203 kernel/locking/lockdep.c static int find_exclusive_match(unsigned long mask, mask 2210 kernel/locking/lockdep.c for_each_set_bit(bit, &mask, LOCK_USED) { mask 750 kernel/padata.c int padata_remove_cpu(struct padata_instance *pinst, int cpu, int mask) mask 754 kernel/padata.c if (!(mask & (PADATA_CPU_SERIAL | PADATA_CPU_PARALLEL))) mask 760 kernel/padata.c if (mask & PADATA_CPU_SERIAL) mask 762 kernel/padata.c if (mask & PADATA_CPU_PARALLEL) mask 1521 kernel/power/snapshot.c static unsigned long preallocate_image_pages(unsigned long nr_pages, gfp_t mask) mask 1528 kernel/power/snapshot.c page = alloc_image_page(mask); mask 1047 kernel/ptrace.c sigset_t *mask; mask 1055 kernel/ptrace.c mask = &child->saved_sigmask; mask 1057 kernel/ptrace.c mask = &child->blocked; mask 1059 kernel/ptrace.c if (copy_to_user(datavp, mask, sizeof(sigset_t))) mask 360 kernel/rcu/rcu.h #define rcu_find_next_bit(rnp, cpu, mask) \ mask 361 kernel/rcu/rcu.h ((rnp)->grplo + find_next_bit(&(mask), BITS_PER_LONG, (cpu))) mask 362 kernel/rcu/rcu.h #define for_each_leaf_node_cpu_mask(rnp, cpu, mask) \ mask 363 kernel/rcu/rcu.h for ((cpu) = rcu_find_next_bit((rnp), 0, (mask)); \ mask 365 kernel/rcu/rcu.h (cpu) = rcu_find_next_bit((rnp), (cpu) + 1 - (rnp->grplo), (mask))) mask 1200 kernel/rcu/rcutorture.c int mask; mask 1203 kernel/rcu/rcutorture.c mask = extendables & RCUTORTURE_MAX_EXTEND & cur_ops->extendables; mask 1204 kernel/rcu/rcutorture.c mask = mask | RCUTORTURE_RDR_RCU; mask 1205 kernel/rcu/rcutorture.c return mask; mask 1212 kernel/rcu/rcutorture.c int mask = rcutorture_extend_mask_max(); mask 1216 kernel/rcu/rcutorture.c WARN_ON_ONCE(mask >> RCUTORTURE_RDR_SHIFT); mask 1219 kernel/rcu/rcutorture.c mask = mask & randmask2; mask 1221 kernel/rcu/rcutorture.c mask = mask & (1 << (randmask2 % RCUTORTURE_RDR_NBITS)); mask 1223 kernel/rcu/rcutorture.c if ((mask & RCUTORTURE_RDR_IRQ) && mask 1224 kernel/rcu/rcutorture.c ((!(mask & RCUTORTURE_RDR_BH) && (oldmask & RCUTORTURE_RDR_BH)) || mask 1225 kernel/rcu/rcutorture.c (!(mask & RCUTORTURE_RDR_RBH) && (oldmask & RCUTORTURE_RDR_RBH)))) mask 1226 kernel/rcu/rcutorture.c mask |= RCUTORTURE_RDR_BH | RCUTORTURE_RDR_RBH; mask 1227 kernel/rcu/rcutorture.c return mask ?: RCUTORTURE_RDR_RCU; mask 1240 kernel/rcu/rcutorture.c int mask = rcutorture_extend_mask_max(); mask 1243 kernel/rcu/rcutorture.c if (!((mask - 1) & mask)) mask 1249 kernel/rcu/rcutorture.c mask = rcutorture_extend_mask(*readstate, trsp); mask 1250 kernel/rcu/rcutorture.c rcutorture_one_extend(readstate, mask, trsp, &rtrsp[j]); mask 492 kernel/rcu/srcutree.c unsigned long mask, unsigned long delay) mask 497 kernel/rcu/srcutree.c if (!(mask & (1 << (cpu - snp->grplo)))) mask 521 kernel/rcu/srcutree.c unsigned long mask; mask 554 kernel/rcu/srcutree.c mask = snp->srcu_data_have_cbs[idx]; mask 558 kernel/rcu/srcutree.c srcu_schedule_cbs_snp(ssp, snp, mask, cbdelay); mask 145 kernel/rcu/tree.c static void rcu_report_qs_rnp(unsigned long mask, struct rcu_node *rnp, mask 1448 kernel/rcu/tree.c unsigned long mask; mask 1558 kernel/rcu/tree.c mask = rnp->qsmask & ~rnp->qsmaskinitnext; mask 1559 kernel/rcu/tree.c rnp->rcu_gp_init_mask = mask; mask 1560 kernel/rcu/tree.c if ((mask || rnp->wait_blkd_tasks) && rcu_is_leaf_node(rnp)) mask 1561 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags); mask 1843 kernel/rcu/tree.c static void rcu_report_qs_rnp(unsigned long mask, struct rcu_node *rnp, mask 1854 kernel/rcu/tree.c if ((!(rnp->qsmask & mask) && mask) || rnp->gp_seq != gps) { mask 1866 kernel/rcu/tree.c rnp->qsmask &= ~mask; mask 1868 kernel/rcu/tree.c mask, rnp->qsmask, rnp->level, mask 1878 kernel/rcu/tree.c mask = rnp->grpmask; mask 1912 kernel/rcu/tree.c unsigned long mask; mask 1936 kernel/rcu/tree.c mask = rnp->grpmask; mask 1939 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp_p, gps, flags); mask 1950 kernel/rcu/tree.c unsigned long mask; mask 1971 kernel/rcu/tree.c mask = rdp->grpmask; mask 1973 kernel/rcu/tree.c if ((rnp->qsmask & mask) == 0) { mask 1983 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags); mask 2061 kernel/rcu/tree.c long mask; mask 2070 kernel/rcu/tree.c mask = rnp->grpmask; mask 2075 kernel/rcu/tree.c rnp->qsmaskinit &= ~mask; mask 2262 kernel/rcu/tree.c unsigned long mask; mask 2267 kernel/rcu/tree.c mask = 0; mask 2288 kernel/rcu/tree.c mask |= bit; mask 2291 kernel/rcu/tree.c if (mask != 0) { mask 2293 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags); mask 2968 kernel/rcu/tree.c long mask; mask 2975 kernel/rcu/tree.c mask = rnp->grpmask; mask 2981 kernel/rcu/tree.c rnp->qsmaskinit |= mask; mask 3126 kernel/rcu/tree.c unsigned long mask; mask 3139 kernel/rcu/tree.c mask = rdp->grpmask; mask 3141 kernel/rcu/tree.c rnp->qsmaskinitnext |= mask; mask 3143 kernel/rcu/tree.c rnp->expmaskinitnext |= mask; mask 3151 kernel/rcu/tree.c if (rnp->qsmask & mask) { /* RCU waiting on incoming CPU? */ mask 3153 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags); mask 3172 kernel/rcu/tree.c unsigned long mask; mask 3183 kernel/rcu/tree.c mask = rdp->grpmask; mask 3188 kernel/rcu/tree.c if (rnp->qsmask & mask) { /* RCU waiting on outgoing CPU? */ mask 3190 kernel/rcu/tree.c rcu_report_qs_rnp(mask, rnp, rnp->gp_seq, flags); mask 3193 kernel/rcu/tree.c rnp->qsmaskinitnext &= ~mask; mask 75 kernel/rcu/tree_exp.h unsigned long mask; mask 107 kernel/rcu/tree_exp.h mask = rnp->grpmask; mask 114 kernel/rcu/tree_exp.h rnp_up->expmaskinit |= mask; mask 118 kernel/rcu/tree_exp.h mask = rnp_up->grpmask; mask 191 kernel/rcu/tree_exp.h unsigned long mask; mask 209 kernel/rcu/tree_exp.h mask = rnp->grpmask; mask 213 kernel/rcu/tree_exp.h WARN_ON_ONCE(!(rnp->expmask & mask)); mask 214 kernel/rcu/tree_exp.h WRITE_ONCE(rnp->expmask, rnp->expmask & ~mask); mask 235 kernel/rcu/tree_exp.h unsigned long mask, bool wake) mask 240 kernel/rcu/tree_exp.h if (!(rnp->expmask & mask)) { mask 244 kernel/rcu/tree_exp.h WRITE_ONCE(rnp->expmask, rnp->expmask & ~mask); mask 348 kernel/rcu/tree_exp.h unsigned long mask = leaf_node_cpu_bit(rnp, cpu); mask 353 kernel/rcu/tree_exp.h !(rnp->qsmaskinitnext & mask)) { mask 354 kernel/rcu/tree_exp.h mask_ofl_test |= mask; mask 358 kernel/rcu/tree_exp.h mask_ofl_test |= mask; mask 376 kernel/rcu/tree_exp.h unsigned long mask = leaf_node_cpu_bit(rnp, cpu); mask 381 kernel/rcu/tree_exp.h mask_ofl_test |= mask; mask 391 kernel/rcu/tree_exp.h mask_ofl_ipi &= ~mask; mask 396 kernel/rcu/tree_exp.h if ((rnp->qsmaskinitnext & mask) && mask 397 kernel/rcu/tree_exp.h (rnp->expmask & mask)) { mask 405 kernel/rcu/tree_exp.h if (!(rnp->expmask & mask)) mask 406 kernel/rcu/tree_exp.h mask_ofl_ipi &= ~mask; mask 462 kernel/rcu/tree_exp.h unsigned long mask; mask 491 kernel/rcu/tree_exp.h mask = leaf_node_cpu_bit(rnp, cpu); mask 492 kernel/rcu/tree_exp.h if (!(READ_ONCE(rnp->expmask) & mask)) mask 522 kernel/rcu/tree_exp.h mask = leaf_node_cpu_bit(rnp, cpu); mask 523 kernel/rcu/tree_exp.h if (!(READ_ONCE(rnp->expmask) & mask)) mask 1157 kernel/rcu/tree_plugin.h unsigned long mask = rcu_rnp_online_cpus(rnp); mask 1166 kernel/rcu/tree_plugin.h if ((mask & leaf_node_cpu_bit(rnp, cpu)) && mask 931 kernel/relay.c __poll_t mask = 0; mask 940 kernel/relay.c mask |= EPOLLIN | EPOLLRDNORM; mask 943 kernel/relay.c return mask; mask 347 kernel/sched/core.c #define fetch_or(ptr, mask) \ mask 350 kernel/sched/core.c typeof(mask) _mask = (mask); \ mask 5508 kernel/sched/core.c long sched_getaffinity(pid_t pid, struct cpumask *mask) mask 5526 kernel/sched/core.c cpumask_and(mask, &p->cpus_mask, cpu_active_mask); mask 5548 kernel/sched/core.c cpumask_var_t mask; mask 5555 kernel/sched/core.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 5558 kernel/sched/core.c ret = sched_getaffinity(pid, mask); mask 5562 kernel/sched/core.c if (copy_to_user(user_mask_ptr, mask, retlen)) mask 5567 kernel/sched/core.c free_cpumask_var(mask); mask 97 kernel/sched/cpupri.c if (cpumask_any_and(p->cpus_ptr, vec->mask) >= nr_cpu_ids) mask 101 kernel/sched/cpupri.c cpumask_and(lowest_mask, p->cpus_ptr, vec->mask); mask 153 kernel/sched/cpupri.c cpumask_set_cpu(cpu, vec->mask); mask 187 kernel/sched/cpupri.c cpumask_clear_cpu(cpu, vec->mask); mask 207 kernel/sched/cpupri.c if (!zalloc_cpumask_var(&vec->mask, GFP_KERNEL)) mask 222 kernel/sched/cpupri.c free_cpumask_var(cp->pri_to_cpu[i].mask); mask 236 kernel/sched/cpupri.c free_cpumask_var(cp->pri_to_cpu[i].mask); mask 12 kernel/sched/cpupri.h cpumask_var_t mask; mask 840 kernel/sched/topology.c build_balance_mask(struct sched_domain *sd, struct sched_group *sg, struct cpumask *mask) mask 847 kernel/sched/topology.c cpumask_clear(mask); mask 864 kernel/sched/topology.c cpumask_set_cpu(i, mask); mask 868 kernel/sched/topology.c WARN_ON_ONCE(cpumask_empty(mask)); mask 901 kernel/sched/topology.c struct cpumask *mask = sched_domains_tmpmask2; mask 906 kernel/sched/topology.c build_balance_mask(sd, sg, mask); mask 907 kernel/sched/topology.c cpu = cpumask_first_and(sched_group_span(sg), mask); mask 911 kernel/sched/topology.c cpumask_copy(group_balance_mask(sg), mask); mask 913 kernel/sched/topology.c WARN_ON_ONCE(!cpumask_equal(group_balance_mask(sg), mask)); mask 1330 kernel/sched/topology.c sd_weight = cpumask_weight(tl->mask(cpu)); mask 1373 kernel/sched/topology.c cpumask_and(sched_domain_span(sd), cpu_map, tl->mask(cpu)); mask 1450 kernel/sched/topology.c for (tl = sched_domain_topology; tl->mask; tl++) mask 1646 kernel/sched/topology.c struct cpumask *mask = kzalloc(cpumask_size(), GFP_KERNEL); mask 1647 kernel/sched/topology.c if (!mask) mask 1650 kernel/sched/topology.c sched_domains_numa_masks[i][j] = mask; mask 1656 kernel/sched/topology.c cpumask_or(mask, mask, cpumask_of_node(k)); mask 1662 kernel/sched/topology.c for (i = 0; sched_domain_topology[i].mask; i++); mask 1672 kernel/sched/topology.c for (i = 0; sched_domain_topology[i].mask; i++) mask 1679 kernel/sched/topology.c .mask = sd_numa_mask, mask 1689 kernel/sched/topology.c .mask = sd_numa_mask, mask 1913 kernel/sched/topology.c if (!cpumask_equal(tl->mask(cpu), tl->mask(i)) && mask 1914 kernel/sched/topology.c cpumask_intersects(tl->mask(cpu), tl->mask(i))) mask 1959 kernel/sched/topology.c for_each_cpu_and(j, tl->mask(i), cpu_map) { mask 208 kernel/signal.c int next_signal(struct sigpending *pending, sigset_t *mask) mask 214 kernel/signal.c m = mask->sig; mask 285 kernel/signal.c bool task_set_jobctl_pending(struct task_struct *task, unsigned long mask) mask 287 kernel/signal.c BUG_ON(mask & ~(JOBCTL_PENDING_MASK | JOBCTL_STOP_CONSUME | mask 289 kernel/signal.c BUG_ON((mask & JOBCTL_TRAPPING) && !(mask & JOBCTL_PENDING_MASK)); mask 294 kernel/signal.c if (mask & JOBCTL_STOP_SIGMASK) mask 297 kernel/signal.c task->jobctl |= mask; mask 337 kernel/signal.c void task_clear_jobctl_pending(struct task_struct *task, unsigned long mask) mask 339 kernel/signal.c BUG_ON(mask & ~JOBCTL_PENDING_MASK); mask 341 kernel/signal.c if (mask & JOBCTL_STOP_PENDING) mask 342 kernel/signal.c mask |= JOBCTL_STOP_CONSUME | JOBCTL_STOP_DEQUEUED; mask 344 kernel/signal.c task->jobctl &= ~mask; mask 612 kernel/signal.c static int __dequeue_signal(struct sigpending *pending, sigset_t *mask, mask 615 kernel/signal.c int sig = next_signal(pending, mask); mask 628 kernel/signal.c int dequeue_signal(struct task_struct *tsk, sigset_t *mask, kernel_siginfo_t *info) mask 636 kernel/signal.c signr = __dequeue_signal(&tsk->pending, mask, info, &resched_timer); mask 639 kernel/signal.c mask, info, &resched_timer); mask 779 kernel/signal.c static void flush_sigqueue_mask(sigset_t *mask, struct sigpending *s) mask 784 kernel/signal.c sigandsets(&m, mask, &s->signal); mask 788 kernel/signal.c sigandnsets(&s->signal, &s->signal, mask); mask 790 kernel/signal.c if (sigismember(mask, q->info.si_signo)) { mask 3446 kernel/signal.c sigset_t mask = *which; mask 3459 kernel/signal.c sigdelsetmask(&mask, sigmask(SIGKILL) | sigmask(SIGSTOP)); mask 3460 kernel/signal.c signotset(&mask); mask 3463 kernel/signal.c sig = dequeue_signal(tsk, &mask, info); mask 3472 kernel/signal.c sigandsets(&tsk->blocked, &tsk->blocked, &mask); mask 3482 kernel/signal.c sig = dequeue_signal(tsk, &mask, info); mask 3940 kernel/signal.c sigset_t mask; mask 3942 kernel/signal.c sigemptyset(&mask); mask 3943 kernel/signal.c sigaddset(&mask, sig); mask 3945 kernel/signal.c flush_sigqueue_mask(&mask, ¤t->signal->shared_pending); mask 3946 kernel/signal.c flush_sigqueue_mask(&mask, ¤t->pending); mask 3962 kernel/signal.c sigset_t mask; mask 3991 kernel/signal.c sigemptyset(&mask); mask 3992 kernel/signal.c sigaddset(&mask, sig); mask 3993 kernel/signal.c flush_sigqueue_mask(&mask, &p->signal->shared_pending); mask 3995 kernel/signal.c flush_sigqueue_mask(&mask, &t->pending); mask 4317 kernel/signal.c old_sigset_t mask; mask 4322 kernel/signal.c __get_user(mask, &act->sa_mask)) mask 4327 kernel/signal.c siginitset(&new_ka.sa.sa_mask, mask); mask 4351 kernel/signal.c compat_old_sigset_t mask; mask 4359 kernel/signal.c __get_user(mask, &act->sa_mask)) mask 4367 kernel/signal.c siginitset(&new_ka.sa.sa_mask, mask); mask 4489 kernel/signal.c SYSCALL_DEFINE1(sigsuspend, old_sigset_t, mask) mask 4492 kernel/signal.c siginitset(&blocked, mask); mask 4497 kernel/signal.c SYSCALL_DEFINE3(sigsuspend, int, unused1, int, unused2, old_sigset_t, mask) mask 4500 kernel/signal.c siginitset(&blocked, mask); mask 369 kernel/smp.c int smp_call_function_any(const struct cpumask *mask, mask 378 kernel/smp.c if (cpumask_test_cpu(cpu, mask)) mask 383 kernel/smp.c for (cpu = cpumask_first_and(nodemask, mask); cpu < nr_cpu_ids; mask 384 kernel/smp.c cpu = cpumask_next_and(cpu, nodemask, mask)) { mask 390 kernel/smp.c cpu = cpumask_any_and(mask, cpu_online_mask); mask 412 kernel/smp.c void smp_call_function_many(const struct cpumask *mask, mask 436 kernel/smp.c cpu = cpumask_first_and(mask, cpu_online_mask); mask 438 kernel/smp.c cpu = cpumask_next_and(cpu, mask, cpu_online_mask); mask 445 kernel/smp.c next_cpu = cpumask_next_and(cpu, mask, cpu_online_mask); mask 447 kernel/smp.c next_cpu = cpumask_next_and(next_cpu, mask, cpu_online_mask); mask 457 kernel/smp.c cpumask_and(cfd->cpumask, mask, cpu_online_mask); mask 640 kernel/smp.c void on_each_cpu_mask(const struct cpumask *mask, smp_call_func_t func, mask 645 kernel/smp.c smp_call_function_many(mask, func, info, wait); mask 646 kernel/smp.c if (cpumask_test_cpu(cpu, mask)) { mask 685 kernel/smp.c gfp_t gfp_flags, const struct cpumask *mask) mask 694 kernel/smp.c for_each_cpu(cpu, mask) mask 706 kernel/smp.c for_each_cpu(cpu, mask) mask 1806 kernel/sys.c SYSCALL_DEFINE1(umask, int, mask) mask 1808 kernel/sys.c mask = xchg(¤t->fs->umask, mask & S_IRWXUGO); mask 1809 kernel/sys.c return mask; mask 278 kernel/taskstats.c static int add_del_listener(pid_t pid, const struct cpumask *mask, int isadd) mask 285 kernel/taskstats.c if (!cpumask_subset(mask, cpu_possible_mask)) mask 295 kernel/taskstats.c for_each_cpu(cpu, mask) { mask 322 kernel/taskstats.c for_each_cpu(cpu, mask) { mask 337 kernel/taskstats.c static int parse(struct nlattr *na, struct cpumask *mask) mask 354 kernel/taskstats.c ret = cpulist_parse(data, mask); mask 441 kernel/taskstats.c cpumask_var_t mask; mask 444 kernel/taskstats.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 446 kernel/taskstats.c rc = parse(info->attrs[TASKSTATS_CMD_ATTR_REGISTER_CPUMASK], mask); mask 449 kernel/taskstats.c rc = add_del_listener(info->snd_portid, mask, REGISTER); mask 451 kernel/taskstats.c free_cpumask_var(mask); mask 457 kernel/taskstats.c cpumask_var_t mask; mask 460 kernel/taskstats.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 462 kernel/taskstats.c rc = parse(info->attrs[TASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK], mask); mask 465 kernel/taskstats.c rc = add_del_listener(info->snd_portid, mask, DEREGISTER); mask 467 kernel/taskstats.c free_cpumask_var(mask); mask 223 kernel/time/clocksource.c delta = clocksource_delta(wdnow, cs->wd_last, watchdog->mask); mask 227 kernel/time/clocksource.c delta = clocksource_delta(csnow, cs->cs_last, cs->mask); mask 242 kernel/time/clocksource.c watchdog->name, wdnow, wdlast, watchdog->mask); mask 244 kernel/time/clocksource.c cs->name, csnow, cslast, cs->mask); mask 582 kernel/time/clocksource.c suspend_clocksource->mask); mask 666 kernel/time/clocksource.c u64 clocks_calc_max_nsecs(u32 mult, u32 shift, u32 maxadj, u64 mask, u64 *max_cyc) mask 683 kernel/time/clocksource.c max_cycles = min(max_cycles, mask); mask 704 kernel/time/clocksource.c cs->maxadj, cs->mask, mask 876 kernel/time/clocksource.c sec = cs->mask; mask 881 kernel/time/clocksource.c else if (sec > 600 && cs->mask > UINT_MAX) mask 910 kernel/time/clocksource.c cs->name, cs->mask, cs->max_cycles, cs->max_idle_ns); mask 55 kernel/time/jiffies.c .mask = CLOCKSOURCE_MASK(32), mask 143 kernel/time/tick-broadcast.c static void err_broadcast(const struct cpumask *mask) mask 264 kernel/time/tick-broadcast.c static bool tick_do_broadcast(struct cpumask *mask) mask 273 kernel/time/tick-broadcast.c if (cpumask_test_cpu(cpu, mask)) { mask 276 kernel/time/tick-broadcast.c cpumask_clear_cpu(cpu, mask); mask 292 kernel/time/tick-broadcast.c if (!cpumask_empty(mask)) { mask 299 kernel/time/tick-broadcast.c td = &per_cpu(tick_cpu_device, cpumask_first(mask)); mask 300 kernel/time/tick-broadcast.c td->evtdev->broadcast(mask); mask 867 kernel/time/tick-broadcast.c static void tick_broadcast_init_next_event(struct cpumask *mask, mask 873 kernel/time/tick-broadcast.c for_each_cpu(cpu, mask) { mask 15 kernel/time/timecounter.c tc->mask = (1ULL << cc->shift) - 1; mask 40 kernel/time/timecounter.c cycle_delta = (cycle_now - tc->cycle_last) & tc->cc->mask; mask 44 kernel/time/timecounter.c tc->mask, &tc->frac); mask 70 kernel/time/timecounter.c u64 cycles, u64 mask, u64 frac) mask 82 kernel/time/timecounter.c u64 delta = (cycle_tstamp - tc->cycle_last) & tc->cc->mask; mask 90 kernel/time/timecounter.c if (delta > tc->cc->mask / 2) { mask 91 kernel/time/timecounter.c delta = (tc->cycle_last - cycle_tstamp) & tc->cc->mask; mask 92 kernel/time/timecounter.c nsec -= cc_cyc2ns_backwards(tc->cc, delta, tc->mask, frac); mask 94 kernel/time/timecounter.c nsec += cyclecounter_cyc2ns(tc->cc, delta, tc->mask, &frac); mask 221 kernel/time/timekeeping.c u64 now, last, mask, max, delta; mask 235 kernel/time/timekeeping.c mask = tkr->mask; mask 239 kernel/time/timekeeping.c delta = clocksource_delta(now, last, mask); mask 245 kernel/time/timekeeping.c if (unlikely((~delta & mask) < (mask >> 3))) { mask 270 kernel/time/timekeeping.c delta = clocksource_delta(cycle_now, tkr->cycle_last, tkr->mask); mask 296 kernel/time/timekeeping.c tk->tkr_mono.mask = clock->mask; mask 300 kernel/time/timekeeping.c tk->tkr_raw.mask = clock->mask; mask 383 kernel/time/timekeeping.c delta = clocksource_delta(cycles, tkr->cycle_last, tkr->mask); mask 466 kernel/time/timekeeping.c tkr->mask)); mask 532 kernel/time/timekeeping.c tkr->mask)); mask 702 kernel/time/timekeeping.c delta = clocksource_delta(cycle_now, tk->tkr_mono.cycle_last, tk->tkr_mono.mask); mask 2070 kernel/time/timekeeping.c tk->tkr_mono.cycle_last, tk->tkr_mono.mask); mask 17 kernel/time/timekeeping_internal.h static inline u64 clocksource_delta(u64 now, u64 last, u64 mask) mask 19 kernel/time/timekeeping_internal.h u64 ret = (now - last) & mask; mask 25 kernel/time/timekeeping_internal.h return ret & ~(mask >> 1) ? 0 : ret; mask 28 kernel/time/timekeeping_internal.h static inline u64 clocksource_delta(u64 now, u64 last, u64 mask) mask 30 kernel/time/timekeeping_internal.h return (now - last) & mask; mask 23 kernel/time/vsyscall.c vdata[CS_HRES_COARSE].mask = tk->tkr_mono.mask; mask 27 kernel/time/vsyscall.c vdata[CS_RAW].mask = tk->tkr_raw.mask; mask 1712 kernel/trace/blktrace.c int mask; mask 1736 kernel/trace/blktrace.c int mask = 0; mask 1754 kernel/trace/blktrace.c mask |= mask_maps[i].mask; mask 1759 kernel/trace/blktrace.c mask = -EINVAL; mask 1765 kernel/trace/blktrace.c return mask; mask 1768 kernel/trace/blktrace.c static ssize_t blk_trace_mask2str(char *buf, int mask) mask 1774 kernel/trace/blktrace.c if (mask & mask_maps[i].mask) { mask 4591 kernel/trace/trace.c int trace_keep_overwrite(struct tracer *tracer, u32 mask, int set) mask 4593 kernel/trace/trace.c if (tracer->enabled && (mask & TRACE_ITER_OVERWRITE) && !set) mask 4599 kernel/trace/trace.c int set_tracer_flag(struct trace_array *tr, unsigned int mask, int enabled) mask 4601 kernel/trace/trace.c if ((mask == TRACE_ITER_RECORD_TGID) || mask 4602 kernel/trace/trace.c (mask == TRACE_ITER_RECORD_CMD)) mask 4606 kernel/trace/trace.c if (!!(tr->trace_flags & mask) == !!enabled) mask 4611 kernel/trace/trace.c if (tr->current_trace->flag_changed(tr, mask, !!enabled)) mask 4615 kernel/trace/trace.c tr->trace_flags |= mask; mask 4617 kernel/trace/trace.c tr->trace_flags &= ~mask; mask 4619 kernel/trace/trace.c if (mask == TRACE_ITER_RECORD_CMD) mask 4622 kernel/trace/trace.c if (mask == TRACE_ITER_RECORD_TGID) { mask 4635 kernel/trace/trace.c if (mask == TRACE_ITER_EVENT_FORK) mask 4638 kernel/trace/trace.c if (mask == TRACE_ITER_FUNC_FORK) mask 4641 kernel/trace/trace.c if (mask == TRACE_ITER_OVERWRITE) { mask 4648 kernel/trace/trace.c if (mask == TRACE_ITER_PRINTK) { mask 497 kernel/trace/trace.h u32 mask, int set); mask 1894 kernel/trace/trace.h int trace_keep_overwrite(struct tracer *tracer, u32 mask, int set); mask 1895 kernel/trace/trace.h int set_tracer_flag(struct trace_array *tr, unsigned int mask, int enabled); mask 494 kernel/trace/trace_irqsoff.c static int irqsoff_function_set(struct trace_array *tr, u32 mask, int set) mask 496 kernel/trace/trace_irqsoff.c if (!(mask & TRACE_ITER_FUNCTION)) mask 511 kernel/trace/trace_irqsoff.c static inline int irqsoff_function_set(struct trace_array *tr, u32 mask, int set) mask 517 kernel/trace/trace_irqsoff.c static int irqsoff_flag_changed(struct trace_array *tr, u32 mask, int set) mask 521 kernel/trace/trace_irqsoff.c if (irqsoff_function_set(tr, mask, set)) mask 525 kernel/trace/trace_irqsoff.c if (mask & TRACE_ITER_DISPLAY_GRAPH) mask 529 kernel/trace/trace_irqsoff.c return trace_keep_overwrite(tracer, mask, set); mask 69 kernel/trace/trace_output.c unsigned long mask; mask 76 kernel/trace/trace_output.c mask = flag_array[i].mask; mask 77 kernel/trace/trace_output.c if ((flags & mask) != mask) mask 81 kernel/trace/trace_output.c flags &= ~mask; mask 111 kernel/trace/trace_output.c if (val != symbol_array[i].mask) mask 133 kernel/trace/trace_output.c unsigned long long mask; mask 140 kernel/trace/trace_output.c mask = flag_array[i].mask; mask 141 kernel/trace/trace_output.c if ((flags & mask) != mask) mask 145 kernel/trace/trace_output.c flags &= ~mask; mask 175 kernel/trace/trace_output.c if (val != symbol_array[i].mask) mask 265 kernel/trace/trace_sched_wakeup.c static int wakeup_function_set(struct trace_array *tr, u32 mask, int set) mask 267 kernel/trace/trace_sched_wakeup.c if (!(mask & TRACE_ITER_FUNCTION)) mask 282 kernel/trace/trace_sched_wakeup.c static int wakeup_function_set(struct trace_array *tr, u32 mask, int set) mask 314 kernel/trace/trace_sched_wakeup.c static int wakeup_flag_changed(struct trace_array *tr, u32 mask, int set) mask 318 kernel/trace/trace_sched_wakeup.c if (wakeup_function_set(tr, mask, set)) mask 322 kernel/trace/trace_sched_wakeup.c if (mask & TRACE_ITER_DISPLAY_GRAPH) mask 326 kernel/trace/trace_sched_wakeup.c return trace_keep_overwrite(tracer, mask, set); mask 54 kernel/up.c void on_each_cpu_mask(const struct cpumask *mask, mask 59 kernel/up.c if (cpumask_test_cpu(0, mask)) { mask 73 kernel/up.c gfp_t gfp_flags, const struct cpumask *mask) mask 446 lib/bch.c unsigned int tmp, mask; mask 450 lib/bch.c mask = 1 << m; mask 458 lib/bch.c if (rows[r] & mask) { mask 472 lib/bch.c if (rows[r] & mask) mask 479 lib/bch.c mask >>= 1; mask 506 lib/bch.c mask = rows[r] & (tmp|1); mask 507 lib/bch.c tmp |= parity(mask) << (m-r); mask 524 lib/bch.c unsigned int mask = 0xff, t, rows[16] = {0,}; mask 542 lib/bch.c for (j = 8; j != 0; j >>= 1, mask ^= (mask << j)) { mask 544 lib/bch.c t = ((rows[k] >> j)^rows[k+j]) & mask; mask 106 lib/bitmap.c unsigned long mask = BITMAP_LAST_WORD_MASK(nbits); mask 119 lib/bitmap.c upper &= mask; mask 124 lib/bitmap.c lower &= mask; mask 1039 lib/bitmap.c unsigned long mask; /* bitmask for one long of region */ mask 1057 lib/bitmap.c mask = (1UL << (nbitsinlong - 1)); mask 1058 lib/bitmap.c mask += mask - 1; mask 1059 lib/bitmap.c mask <<= offset; mask 1064 lib/bitmap.c if (bitmap[index + i] & mask) mask 1072 lib/bitmap.c bitmap[index + i] |= mask; mask 1077 lib/bitmap.c bitmap[index + i] &= ~mask; mask 95 lib/cpu_rmap.c const struct cpumask *mask, u16 dist) mask 99 lib/cpu_rmap.c for_each_cpu(neigh, mask) { mask 250 lib/cpu_rmap.c irq_cpu_rmap_notify(struct irq_affinity_notify *notify, const cpumask_t *mask) mask 256 lib/cpu_rmap.c rc = cpu_rmap_update(glue->rmap, glue->index, mask); mask 53 lib/cpumask.c int cpumask_any_but(const struct cpumask *mask, unsigned int cpu) mask 58 lib/cpumask.c for_each_cpu(i, mask) mask 77 lib/cpumask.c int cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap) mask 82 lib/cpumask.c next = cpumask_next(n, mask); mask 113 lib/cpumask.c bool alloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node) mask 115 lib/cpumask.c *mask = kmalloc_node(cpumask_size(), flags, node); mask 118 lib/cpumask.c if (!*mask) { mask 124 lib/cpumask.c return *mask != NULL; mask 128 lib/cpumask.c bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node) mask 130 lib/cpumask.c return alloc_cpumask_var_node(mask, flags | __GFP_ZERO, node); mask 144 lib/cpumask.c bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) mask 146 lib/cpumask.c return alloc_cpumask_var_node(mask, flags, NUMA_NO_NODE); mask 150 lib/cpumask.c bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) mask 152 lib/cpumask.c return alloc_cpumask_var(mask, flags | __GFP_ZERO); mask 165 lib/cpumask.c void __init alloc_bootmem_cpumask_var(cpumask_var_t *mask) mask 167 lib/cpumask.c *mask = memblock_alloc(cpumask_size(), SMP_CACHE_BYTES); mask 168 lib/cpumask.c if (!*mask) mask 179 lib/cpumask.c void free_cpumask_var(cpumask_var_t mask) mask 181 lib/cpumask.c kfree(mask); mask 189 lib/cpumask.c void __init free_bootmem_cpumask_var(cpumask_var_t mask) mask 191 lib/cpumask.c memblock_free_early(__pa(mask), cpumask_size()); mask 388 lib/devres.c int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name) mask 400 lib/devres.c if (!(mask & (1 << i))) mask 423 lib/devres.c if (!(mask & (1 << i))) mask 441 lib/devres.c int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, mask 444 lib/devres.c int request_mask = ((1 << 6) - 1) & ~mask; mask 451 lib/devres.c rc = pcim_iomap_regions(pdev, mask, name); mask 465 lib/devres.c void pcim_iounmap_regions(struct pci_dev *pdev, int mask) mask 475 lib/devres.c if (!(mask & (1 << i))) mask 141 lib/dynamic_debug.c unsigned int flags, unsigned int mask) mask 190 lib/dynamic_debug.c newflags = (dp->flags & mask) | flags; mask 448 lib/dynamic_debug.c unsigned int flags = 0, mask = 0; mask 460 lib/dynamic_debug.c if (ddebug_parse_flags(words[nwords-1], &flags, &mask)) { mask 469 lib/dynamic_debug.c nfound = ddebug_change(&query, flags, mask); mask 21 lib/kfifo.c return (fifo->mask + 1) - (fifo->in - fifo->out); mask 39 lib/kfifo.c fifo->mask = 0; mask 46 lib/kfifo.c fifo->mask = 0; mask 49 lib/kfifo.c fifo->mask = size - 1; mask 62 lib/kfifo.c fifo->mask = 0; mask 80 lib/kfifo.c fifo->mask = 0; mask 83 lib/kfifo.c fifo->mask = size - 1; mask 92 lib/kfifo.c unsigned int size = fifo->mask + 1; mask 96 lib/kfifo.c off &= fifo->mask; mask 131 lib/kfifo.c unsigned int size = fifo->mask + 1; mask 135 lib/kfifo.c off &= fifo->mask; mask 179 lib/kfifo.c unsigned int size = fifo->mask + 1; mask 184 lib/kfifo.c off &= fifo->mask; mask 241 lib/kfifo.c unsigned int size = fifo->mask + 1; mask 244 lib/kfifo.c off &= fifo->mask; mask 337 lib/kfifo.c unsigned int size = fifo->mask + 1; mask 342 lib/kfifo.c off &= fifo->mask; mask 392 lib/kfifo.c #define __KFIFO_PEEK(data, out, mask) \ mask 393 lib/kfifo.c ((data)[(out) & (mask)]) mask 401 lib/kfifo.c unsigned int mask = fifo->mask; mask 404 lib/kfifo.c l = __KFIFO_PEEK(data, fifo->out, mask); mask 407 lib/kfifo.c l |= __KFIFO_PEEK(data, fifo->out + 1, mask) << 8; mask 412 lib/kfifo.c #define __KFIFO_POKE(data, in, mask, val) \ mask 414 lib/kfifo.c (data)[(in) & (mask)] = (unsigned char)(val) \ mask 423 lib/kfifo.c unsigned int mask = fifo->mask; mask 426 lib/kfifo.c __KFIFO_POKE(data, fifo->in, mask, n); mask 429 lib/kfifo.c __KFIFO_POKE(data, fifo->in + 1, mask, n >> 8); mask 36 lib/nmi_backtrace.c void nmi_trigger_cpumask_backtrace(const cpumask_t *mask, mask 38 lib/nmi_backtrace.c void (*raise)(cpumask_t *mask)) mask 51 lib/nmi_backtrace.c cpumask_copy(to_cpumask(backtrace_mask), mask); mask 17 lib/sbitmap.c unsigned long mask, val; mask 29 lib/sbitmap.c mask = xchg(&sb->map[index].cleared, 0); mask 36 lib/sbitmap.c } while (cmpxchg(&sb->map[index].word, val, val & ~mask) != val); mask 245 lib/sbitmap.c unsigned long mask = word->word & ~word->cleared; mask 248 lib/sbitmap.c ret = find_first_zero_bit(&mask, word->depth); mask 26 lib/stmp_device.c static int stmp_clear_poll_bit(void __iomem *addr, u32 mask) mask 30 lib/stmp_device.c writel(mask, addr + STMP_OFFSET_REG_CLR); mask 32 lib/stmp_device.c while ((readl(addr) & mask) && --timeout) mask 102 lib/test_bitfield.c #define CHECK(tp, mask) do { \ mask 105 lib/test_bitfield.c for (v = 0; v < 1 << hweight32(mask); v++) \ mask 106 lib/test_bitfield.c if (tp##_encode_bits(v, mask) != v << __ffs64(mask)) \ mask 35 lib/vdso/gettimeofday.c u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) mask 37 lib/vdso/gettimeofday.c return ((cycles - last) & mask) * mult; mask 56 lib/vdso/gettimeofday.c ns += vdso_calc_delta(cycles, last, vd->mask, vd->mult); mask 460 lib/vsprintf.c int mask = spec.base - 1; mask 466 lib/vsprintf.c tmp[i++] = (hex_asc_upper[((unsigned char)num) & mask] | locase); mask 1827 lib/vsprintf.c unsigned long mask; mask 1830 lib/vsprintf.c mask = names->mask; mask 1831 lib/vsprintf.c if ((flags & mask) != mask) mask 1836 lib/vsprintf.c flags &= ~mask; mask 415 lib/xarray.c unsigned long mask = xas_size(xas) - 1; mask 416 lib/xarray.c max |= mask; mask 417 lib/xarray.c if (mask == max) mask 1839 lib/xarray.c unsigned long mask; mask 1843 lib/xarray.c mask = (XA_CHUNK_SIZE << node->shift) - 1; mask 1844 lib/xarray.c return (xas->xa_index & mask) > mask 214 lib/xz/xz_dec_bcj.c uint32_t mask; mask 223 lib/xz/xz_dec_bcj.c mask = branch_table[buf[i] & 0x1F]; mask 225 lib/xz/xz_dec_bcj.c if (((mask >> slot) & 1) == 0) mask 555 lib/xz/xz_dec_lzma2.c uint32_t mask; mask 561 lib/xz/xz_dec_lzma2.c mask = (uint32_t)0 - (rc->code >> 31); mask 562 lib/xz/xz_dec_lzma2.c rc->code += rc->range & mask; mask 563 lib/xz/xz_dec_lzma2.c *dest = (*dest << 1) + (mask + 1); mask 38 lib/zlib_inflate/inftrees.c unsigned mask; /* mask for low root bits */ mask 195 lib/zlib_inflate/inftrees.c mask = used - 1; /* mask for comparing low */ mask 246 lib/zlib_inflate/inftrees.c if (len > root && (huff & mask) != low) { mask 270 lib/zlib_inflate/inftrees.c low = huff & mask; mask 289 lib/zlib_inflate/inftrees.c if (drop != 0 && (huff & mask) != low) { mask 1791 lib/zstd/compress.c #define NEXT_IN_CHAIN(d, mask) chainTable[(d)&mask] mask 420 mm/cma.c unsigned long mask, offset; mask 437 mm/cma.c mask = cma_bitmap_aligned_mask(cma, align); mask 448 mm/cma.c bitmap_maxno, start, bitmap_count, mask, mask 479 mm/cma.c start = bitmap_no + mask + 1; mask 2705 mm/compaction.c const struct cpumask *mask; mask 2707 mm/compaction.c mask = cpumask_of_node(pgdat->node_id); mask 2709 mm/compaction.c if (cpumask_any_and(cpu_online_mask, mask) < nr_cpu_ids) mask 2711 mm/compaction.c set_cpus_allowed_ptr(pgdat->kcompactd, mask); mask 1037 mm/hugetlb.c #define for_each_node_mask_to_alloc(hs, nr_nodes, node, mask) \ mask 1038 mm/hugetlb.c for (nr_nodes = nodes_weight(*mask); \ mask 1040 mm/hugetlb.c ((node = hstate_next_node_to_alloc(hs, mask)) || 1); \ mask 1043 mm/hugetlb.c #define for_each_node_mask_to_free(hs, nr_nodes, node, mask) \ mask 1044 mm/hugetlb.c for (nr_nodes = nodes_weight(*mask); \ mask 1046 mm/hugetlb.c ((node = hstate_next_node_to_free(hs, mask)) || 1); \ mask 3010 mm/hugetlb.c h->mask = ~((1ULL << (order + PAGE_SHIFT)) - 1); mask 479 mm/internal.h static inline int node_reclaim(struct pglist_data *pgdat, gfp_t mask, mask 1891 mm/memcontrol.c static enum oom_status mem_cgroup_oom(struct mem_cgroup *memcg, gfp_t mask, int order) mask 1924 mm/memcontrol.c current->memcg_oom_gfp_mask = mask; mask 1938 mm/memcontrol.c if (mem_cgroup_out_of_memory(memcg, mask, order)) mask 836 mm/memory-failure.c unsigned long mask; mask 1072 mm/memory-failure.c if ((p->flags & ps->mask) == ps->res) mask 1077 mm/memory-failure.c if (!ps->mask) mask 1079 mm/memory-failure.c if ((page_flags & ps->mask) == ps->res) mask 3436 mm/memory.c unsigned long address = vmf->address, nr_pages, mask; mask 3443 mm/memory.c mask = ~(nr_pages * PAGE_SIZE - 1) & PAGE_MASK; mask 3445 mm/memory.c vmf->address = max(address & mask, vmf->vma->vm_start); mask 1388 mm/mempolicy.c static int copy_nodes_to_user(unsigned long __user *mask, unsigned long maxnode, mask 1397 mm/mempolicy.c if (clear_user((char __user *)mask + nbytes, copy - nbytes)) mask 1401 mm/mempolicy.c return copy_to_user(mask, nodes_addr(*nodes), copy) ? -EFAULT : 0; mask 1977 mm/mempolicy.c bool init_nodemask_of_mempolicy(nodemask_t *mask) mask 1982 mm/mempolicy.c if (!(mask && current->mempolicy)) mask 1993 mm/mempolicy.c init_nodemask_of_node(mask, nid); mask 1999 mm/mempolicy.c *mask = mempolicy->v.nodes; mask 2022 mm/mempolicy.c const nodemask_t *mask) mask 2027 mm/mempolicy.c if (!mask) mask 2045 mm/mempolicy.c ret = nodes_intersects(mempolicy->v.nodes, *mask); mask 90 mm/oom_kill.c const nodemask_t *mask = oc->nodemask; mask 97 mm/oom_kill.c if (mask) { mask 104 mm/oom_kill.c ret = mempolicy_nodemask_intersects(tsk, mask); mask 482 mm/page_alloc.c unsigned long mask) mask 495 mm/page_alloc.c return (word >> (BITS_PER_LONG - bitidx - 1)) & mask; mask 500 mm/page_alloc.c unsigned long mask) mask 502 mm/page_alloc.c return __get_pfnblock_flags_mask(page, pfn, end_bitidx, mask); mask 521 mm/page_alloc.c unsigned long mask) mask 538 mm/page_alloc.c mask <<= (BITS_PER_LONG - bitidx - 1); mask 543 mm/page_alloc.c old_word = cmpxchg(&bitmap[word_bitidx], word, (word & ~mask) | flags); mask 7021 mm/page_alloc.c unsigned long start, end, mask; mask 7037 mm/page_alloc.c mask = ~((1 << __ffs(start)) - 1); mask 7038 mm/page_alloc.c while (mask && last_end <= (start & (mask << 1))) mask 7039 mm/page_alloc.c mask <<= 1; mask 7042 mm/page_alloc.c accl_mask |= mask; mask 945 mm/slab.c const struct cpumask *mask = cpumask_of_node(node); mask 967 mm/slab.c if (!cpumask_empty(mask)) { mask 546 mm/swap_state.c unsigned long mask; mask 553 mm/swap_state.c mask = swapin_nr_pages(offset) - 1; mask 554 mm/swap_state.c if (!mask) mask 566 mm/swap_state.c start_offset = offset & ~mask; mask 567 mm/swap_state.c end_offset = offset | mask; mask 4067 mm/vmscan.c const struct cpumask *mask; mask 4069 mm/vmscan.c mask = cpumask_of_node(pgdat->node_id); mask 4071 mm/vmscan.c if (cpumask_any_and(cpu_online_mask, mask) < nr_cpu_ids) mask 4073 mm/vmscan.c set_cpus_allowed_ptr(pgdat->kswapd, mask); mask 120 net/8021q/vlan.h int vlan_dev_change_flags(const struct net_device *dev, u32 flag, u32 mask); mask 215 net/8021q/vlan_dev.c int vlan_dev_change_flags(const struct net_device *dev, u32 flags, u32 mask) mask 220 net/8021q/vlan_dev.c if (mask & ~(VLAN_FLAG_REORDER_HDR | VLAN_FLAG_GVRP | mask 225 net/8021q/vlan_dev.c vlan->flags = (old_flags & ~mask) | (flags & mask); mask 82 net/8021q/vlan_netlink.c if ((flags->flags & flags->mask) & mask 115 net/8021q/vlan_netlink.c err = vlan_dev_change_flags(dev, flags->flags, flags->mask); mask 227 net/8021q/vlan_netlink.c f.mask = ~0; mask 655 net/atm/common.c __poll_t mask; mask 658 net/atm/common.c mask = 0; mask 664 net/atm/common.c mask = EPOLLERR; mask 668 net/atm/common.c mask |= EPOLLHUP; mask 672 net/atm/common.c mask |= EPOLLIN | EPOLLRDNORM; mask 677 net/atm/common.c return mask; mask 681 net/atm/common.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 683 net/atm/common.c return mask; mask 1209 net/atm/mpc.c __be32 mask = msg->ip_mask; mask 1210 net/atm/mpc.c in_cache_entry *entry = mpc->in_ops->get_with_mask(dst_ip, mpc, mask); mask 1225 net/atm/mpc.c entry = mpc->in_ops->get_with_mask(dst_ip, mpc, mask); mask 57 net/atm/mpoa_caches.c __be32 mask) mask 64 net/atm/mpoa_caches.c if ((entry->ctrl_info.in_dst_ip & mask) == (dst_ip & mask)) { mask 40 net/atm/mpoa_caches.h __be32 mask); mask 689 net/batman-adv/sysfs.c u32 mark, mask; mask 697 net/batman-adv/sysfs.c mask = 0xFFFFFFFF; mask 706 net/batman-adv/sysfs.c if (kstrtou32(mask_ptr, 16, &mask) < 0) mask 714 net/batman-adv/sysfs.c bat_priv->isolation_mark_mask = mask; mask 454 net/bluetooth/af_bluetooth.c __poll_t mask = 0; mask 464 net/bluetooth/af_bluetooth.c mask |= EPOLLERR | mask 468 net/bluetooth/af_bluetooth.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 471 net/bluetooth/af_bluetooth.c mask |= EPOLLHUP; mask 474 net/bluetooth/af_bluetooth.c mask |= EPOLLIN | EPOLLRDNORM; mask 477 net/bluetooth/af_bluetooth.c mask |= EPOLLHUP; mask 482 net/bluetooth/af_bluetooth.c return mask; mask 485 net/bluetooth/af_bluetooth.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 489 net/bluetooth/af_bluetooth.c return mask; mask 2571 net/bluetooth/hci_event.c int mask = hdev->link_mode; mask 2579 net/bluetooth/hci_event.c mask |= hci_proto_connect_ind(hdev, &ev->bdaddr, ev->link_type, mask 2582 net/bluetooth/hci_event.c if (!(mask & HCI_LM_ACCEPT)) { mask 2636 net/bluetooth/hci_event.c if (lmp_rswitch_capable(hdev) && (mask & HCI_LM_MASTER)) mask 1378 net/bluetooth/hci_sock.c __u32 mask = hci_pi(sk)->cmsg_mask; mask 1380 net/bluetooth/hci_sock.c if (mask & HCI_CMSG_DIR) { mask 1386 net/bluetooth/hci_sock.c if (mask & HCI_CMSG_TSTAMP) { mask 343 net/bluetooth/l2cap_core.c seq_list->mask = alloc_size - 1; mask 361 net/bluetooth/l2cap_core.c return seq_list->list[seq & seq_list->mask] != L2CAP_SEQ_LIST_CLEAR; mask 367 net/bluetooth/l2cap_core.c u16 mask = seq_list->mask; mask 369 net/bluetooth/l2cap_core.c seq_list->head = seq_list->list[seq & mask]; mask 370 net/bluetooth/l2cap_core.c seq_list->list[seq & mask] = L2CAP_SEQ_LIST_CLEAR; mask 387 net/bluetooth/l2cap_core.c for (i = 0; i <= seq_list->mask; i++) mask 396 net/bluetooth/l2cap_core.c u16 mask = seq_list->mask; mask 400 net/bluetooth/l2cap_core.c if (seq_list->list[seq & mask] != L2CAP_SEQ_LIST_CLEAR) mask 406 net/bluetooth/l2cap_core.c seq_list->list[seq_list->tail & mask] = seq; mask 409 net/bluetooth/l2cap_core.c seq_list->list[seq & mask] = L2CAP_SEQ_LIST_TAIL; mask 538 net/bridge/br_if.c netdev_features_t mask; mask 543 net/bridge/br_if.c mask = features; mask 548 net/bridge/br_if.c p->dev->features, mask); mask 550 net/bridge/br_if.c features = netdev_add_tso_features(features, mask); mask 738 net/bridge/br_if.c void br_port_flags_change(struct net_bridge_port *p, unsigned long mask) mask 742 net/bridge/br_if.c if (mask & BR_AUTO_MASK) mask 745 net/bridge/br_if.c if (mask & BR_NEIGH_SUPPRESS) mask 704 net/bridge/br_netlink.c int attrtype, unsigned long mask) mask 713 net/bridge/br_netlink.c flags = p->flags | mask; mask 715 net/bridge/br_netlink.c flags = p->flags & ~mask; mask 717 net/bridge/br_netlink.c err = br_switchdev_set_port_flag(p, flags, mask); mask 623 net/bridge/br_private.h void br_port_flags_change(struct net_bridge_port *port, unsigned long mask); mask 1195 net/bridge/br_private.h unsigned long mask); mask 1225 net/bridge/br_private.h unsigned long mask) mask 63 net/bridge/br_switchdev.c unsigned long mask) mask 68 net/bridge/br_switchdev.c .u.brport_flags = mask, mask 75 net/bridge/br_switchdev.c if (mask & ~BR_PORT_FLAGS_HW_OFFLOAD) mask 56 net/bridge/br_sysfs_if.c unsigned long mask) mask 63 net/bridge/br_sysfs_if.c flags |= mask; mask 65 net/bridge/br_sysfs_if.c flags &= ~mask; mask 69 net/bridge/br_sysfs_if.c br_port_flags_change(p, mask); mask 22 net/bridge/netfilter/ebt_mark_m.c return !!(skb->mark & info->mask) ^ info->invert; mask 23 net/bridge/netfilter/ebt_mark_m.c return ((skb->mark & info->mask) == info->mark) ^ info->invert; mask 42 net/bridge/netfilter/ebt_mark_m.c compat_ulong_t mark, mask; mask 52 net/bridge/netfilter/ebt_mark_m.c kern->mask = user->mask; mask 63 net/bridge/netfilter/ebt_mark_m.c put_user(kern->mask, &user->mask) || mask 941 net/caif/caif_socket.c __poll_t mask; mask 945 net/caif/caif_socket.c mask = 0; mask 949 net/caif/caif_socket.c mask |= EPOLLERR; mask 951 net/caif/caif_socket.c mask |= EPOLLHUP; mask 953 net/caif/caif_socket.c mask |= EPOLLRDHUP; mask 958 net/caif/caif_socket.c mask |= EPOLLIN | EPOLLRDNORM; mask 965 net/caif/caif_socket.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 967 net/caif/caif_socket.c return mask; mask 364 net/can/af_can.c static struct hlist_head *can_rcv_list_find(canid_t *can_id, canid_t *mask, mask 370 net/can/af_can.c if (*mask & CAN_ERR_FLAG) { mask 372 net/can/af_can.c *mask &= CAN_ERR_MASK; mask 381 net/can/af_can.c if ((*mask & CAN_EFF_FLAG) && !(*can_id & CAN_EFF_FLAG)) mask 382 net/can/af_can.c *mask &= (CAN_SFF_MASK | CAN_EFF_RTR_FLAGS); mask 385 net/can/af_can.c *can_id &= *mask; mask 392 net/can/af_can.c if (!(*mask)) mask 396 net/can/af_can.c if (((*mask & CAN_EFF_RTR_FLAGS) == CAN_EFF_RTR_FLAGS) && mask 399 net/can/af_can.c if (*mask == (CAN_EFF_MASK | CAN_EFF_RTR_FLAGS)) mask 402 net/can/af_can.c if (*mask == (CAN_SFF_MASK | CAN_EFF_RTR_FLAGS)) mask 442 net/can/af_can.c canid_t mask, void (*func)(struct sk_buff *, void *), mask 466 net/can/af_can.c rcv_list = can_rcv_list_find(&can_id, &mask, dev_rcv_lists); mask 469 net/can/af_can.c rcv->mask = mask; mask 511 net/can/af_can.c canid_t mask, void (*func)(struct sk_buff *, void *), mask 528 net/can/af_can.c rcv_list = can_rcv_list_find(&can_id, &mask, dev_rcv_lists); mask 535 net/can/af_can.c if (rcv->can_id == can_id && rcv->mask == mask && mask 545 net/can/af_can.c DNAME(dev), can_id, mask); mask 586 net/can/af_can.c if (can_id & rcv->mask) { mask 602 net/can/af_can.c if ((can_id & rcv->mask) == rcv->can_id) { mask 610 net/can/af_can.c if ((can_id & rcv->mask) != rcv->can_id) { mask 54 net/can/af_can.h canid_t mask; mask 198 net/can/proc.c seq_printf(m, fmt, DNAME(dev), r->can_id, r->mask, mask 48 net/ceph/crush/mapper.c map->rules[i]->mask.ruleset == ruleset && mask 49 net/ceph/crush/mapper.c map->rules[i]->mask.type == type && mask 50 net/ceph/crush/mapper.c map->rules[i]->mask.min_size <= size && mask 51 net/ceph/crush/mapper.c map->rules[i]->mask.max_size >= size) mask 504 net/ceph/osdmap.c ceph_decode_copy_safe(p, end, &r->mask, 4, bad); /* 4 u8's */ mask 772 net/core/datagram.c __poll_t mask; mask 775 net/core/datagram.c mask = 0; mask 779 net/core/datagram.c mask |= EPOLLERR | mask 783 net/core/datagram.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 785 net/core/datagram.c mask |= EPOLLHUP; mask 789 net/core/datagram.c mask |= EPOLLIN | EPOLLRDNORM; mask 794 net/core/datagram.c mask |= EPOLLHUP; mask 797 net/core/datagram.c return mask; mask 802 net/core/datagram.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 806 net/core/datagram.c return mask; mask 917 net/core/dev.c unsigned short mask) mask 925 net/core/dev.c if (((dev->flags ^ if_flags) & mask) == 0) { mask 2134 net/core/dev.c static void clean_xps_maps(struct net_device *dev, const unsigned long *mask, mask 2141 net/core/dev.c for (j = -1; j = netif_attrmask_next(j, mask, nr_ids), mask 2240 net/core/dev.c int __netif_set_xps_queue(struct net_device *dev, const unsigned long *mask, mask 2284 net/core/dev.c for (j = -1; j = netif_attrmask_next_and(j, online_mask, mask, nr_ids), mask 2328 net/core/dev.c if (netif_attr_test_mask(j, mask, nr_ids) && mask 2402 net/core/dev.c if (!netif_attr_test_mask(j, mask, nr_ids) || mask 2438 net/core/dev.c int netif_set_xps_queue(struct net_device *dev, const struct cpumask *mask, mask 2444 net/core/dev.c ret = __netif_set_xps_queue(dev, cpumask_bits(mask), index, false); mask 3922 net/core/dev.c flow_id = skb_get_hash(skb) & flow_table->mask; mask 3990 net/core/dev.c ident = sock_flow_table->ents[hash & sock_flow_table->mask]; mask 3999 net/core/dev.c rflow = &flow_table->flows[hash & flow_table->mask]; mask 4066 net/core/dev.c if (flow_table && flow_id <= flow_table->mask) { mask 4072 net/core/dev.c (int)(10 * flow_table->mask))) mask 9901 net/core/dev.c netdev_features_t one, netdev_features_t mask) mask 9903 net/core/dev.c if (mask & NETIF_F_HW_CSUM) mask 9904 net/core/dev.c mask |= NETIF_F_CSUM_MASK; mask 9905 net/core/dev.c mask |= NETIF_F_VLAN_CHALLENGED; mask 9907 net/core/dev.c all |= one & (NETIF_F_ONE_FOR_ALL | NETIF_F_CSUM_MASK) & mask; mask 1938 net/core/devlink.c if (value->mask) mask 1940 net/core/devlink.c value->value_size, value->mask)) mask 2149 net/core/devlink.c kfree(value[value_index].mask); mask 2156 net/core/devlink.c kfree(value[value_index].mask); mask 297 net/core/ethtool.c netdev_features_t mask = ethtool_get_feature_mask(ethcmd); mask 300 net/core/ethtool.c .data = !!(dev->features & mask), mask 312 net/core/ethtool.c netdev_features_t mask; mask 317 net/core/ethtool.c mask = ethtool_get_feature_mask(ethcmd); mask 318 net/core/ethtool.c mask &= dev->hw_features; mask 319 net/core/ethtool.c if (!mask) mask 323 net/core/ethtool.c dev->wanted_features |= mask; mask 325 net/core/ethtool.c dev->wanted_features &= ~mask; mask 2862 net/core/ethtool.c struct ethtool_rx_flow_key mask; mask 2888 net/core/ethtool.c flow->rule->match.mask = &match->mask; mask 2891 net/core/ethtool.c match->mask.basic.n_proto = htons(0xffff); mask 2903 net/core/ethtool.c ether_addr_copy(match->mask.eth_addrs.src, mask 2909 net/core/ethtool.c ether_addr_copy(match->mask.eth_addrs.dst, mask 2914 net/core/ethtool.c match->mask.basic.n_proto = ether_m_spec->h_proto; mask 2929 net/core/ethtool.c match->mask.ipv4.src = v4_m_spec->ip4src; mask 2933 net/core/ethtool.c match->mask.ipv4.dst = v4_m_spec->ip4dst; mask 2944 net/core/ethtool.c match->mask.tp.src = v4_m_spec->psrc; mask 2948 net/core/ethtool.c match->mask.tp.dst = v4_m_spec->pdst; mask 2959 net/core/ethtool.c match->mask.ip.tos = v4_m_spec->tos; mask 2978 net/core/ethtool.c memcpy(&match->mask.ipv6.src, v6_m_spec->ip6src, mask 2979 net/core/ethtool.c sizeof(match->mask.ipv6.src)); mask 2984 net/core/ethtool.c memcpy(&match->mask.ipv6.dst, v6_m_spec->ip6dst, mask 2985 net/core/ethtool.c sizeof(match->mask.ipv6.dst)); mask 2996 net/core/ethtool.c match->mask.tp.src = v6_m_spec->psrc; mask 3000 net/core/ethtool.c match->mask.tp.dst = v6_m_spec->pdst; mask 3011 net/core/ethtool.c match->mask.ip.tos = v6_m_spec->tclass; mask 3034 net/core/ethtool.c match->mask.basic.ip_proto = 0xff; mask 3046 net/core/ethtool.c match->mask.vlan.vlan_tpid = ext_m_spec->vlan_etype; mask 3052 net/core/ethtool.c match->mask.vlan.vlan_id = mask 3057 net/core/ethtool.c match->mask.vlan.vlan_dei = mask 3062 net/core/ethtool.c match->mask.vlan.vlan_priority = mask 3080 net/core/ethtool.c memcpy(match->mask.eth_addrs.dst, ext_m_spec->h_dest, mask 28 net/core/flow_offload.c (__out)->mask = skb_flow_dissector_target(__d, __type, (__m)->mask); \ mask 689 net/core/net-sysfs.c cpumask_var_t mask; mask 692 net/core/net-sysfs.c if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) mask 699 net/core/net-sysfs.c cpumask_set_cpu(map->cpus[i], mask); mask 701 net/core/net-sysfs.c len = snprintf(buf, PAGE_SIZE, "%*pb\n", cpumask_pr_args(mask)); mask 703 net/core/net-sysfs.c free_cpumask_var(mask); mask 712 net/core/net-sysfs.c cpumask_var_t mask; mask 719 net/core/net-sysfs.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 722 net/core/net-sysfs.c err = bitmap_parse(buf, len, cpumask_bits(mask), nr_cpumask_bits); mask 724 net/core/net-sysfs.c free_cpumask_var(mask); mask 729 net/core/net-sysfs.c RPS_MAP_SIZE(cpumask_weight(mask)), L1_CACHE_BYTES), mask 732 net/core/net-sysfs.c free_cpumask_var(mask); mask 737 net/core/net-sysfs.c for_each_cpu_and(cpu, mask, cpu_online_mask) mask 762 net/core/net-sysfs.c free_cpumask_var(mask); mask 775 net/core/net-sysfs.c val = (unsigned long)flow_table->mask + 1; mask 791 net/core/net-sysfs.c unsigned long mask, count; mask 804 net/core/net-sysfs.c mask = count - 1; mask 808 net/core/net-sysfs.c while ((mask | (mask >> 1)) != mask) mask 809 net/core/net-sysfs.c mask |= (mask >> 1); mask 815 net/core/net-sysfs.c if (mask > (unsigned long)(u32)mask) mask 818 net/core/net-sysfs.c if (mask > (ULONG_MAX - RPS_DEV_FLOW_TABLE_SIZE(1)) mask 824 net/core/net-sysfs.c table = vmalloc(RPS_DEV_FLOW_TABLE_SIZE(mask + 1)); mask 828 net/core/net-sysfs.c table->mask = mask; mask 829 net/core/net-sysfs.c for (count = 0; count <= mask; count++) mask 1241 net/core/net-sysfs.c cpumask_var_t mask; mask 1263 net/core/net-sysfs.c if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) mask 1279 net/core/net-sysfs.c cpumask_set_cpu(cpu, mask); mask 1287 net/core/net-sysfs.c len = snprintf(buf, PAGE_SIZE, "%*pb\n", cpumask_pr_args(mask)); mask 1288 net/core/net-sysfs.c free_cpumask_var(mask); mask 1297 net/core/net-sysfs.c cpumask_var_t mask; mask 1306 net/core/net-sysfs.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 1311 net/core/net-sysfs.c err = bitmap_parse(buf, len, cpumask_bits(mask), nr_cpumask_bits); mask 1313 net/core/net-sysfs.c free_cpumask_var(mask); mask 1317 net/core/net-sysfs.c err = netif_set_xps_queue(dev, mask, index); mask 1319 net/core/net-sysfs.c free_cpumask_var(mask); mask 1331 net/core/net-sysfs.c unsigned long *mask, index; mask 1342 net/core/net-sysfs.c mask = bitmap_zalloc(dev->num_rx_queues, GFP_KERNEL); mask 1343 net/core/net-sysfs.c if (!mask) mask 1362 net/core/net-sysfs.c set_bit(j, mask); mask 1370 net/core/net-sysfs.c len = bitmap_print_to_pagebuf(false, buf, mask, dev->num_rx_queues); mask 1371 net/core/net-sysfs.c bitmap_free(mask); mask 1381 net/core/net-sysfs.c unsigned long *mask, index; mask 1387 net/core/net-sysfs.c mask = bitmap_zalloc(dev->num_rx_queues, GFP_KERNEL); mask 1388 net/core/net-sysfs.c if (!mask) mask 1393 net/core/net-sysfs.c err = bitmap_parse(buf, len, mask, dev->num_rx_queues); mask 1395 net/core/net-sysfs.c bitmap_free(mask); mask 1400 net/core/net-sysfs.c err = __netif_set_xps_queue(dev, mask, index, true); mask 1403 net/core/net-sysfs.c bitmap_free(mask); mask 4282 net/core/rtnetlink.c static int brport_nla_put_flag(struct sk_buff *skb, u32 flags, u32 mask, mask 4285 net/core/rtnetlink.c if (mask & flag) mask 4292 net/core/rtnetlink.c u32 flags, u32 mask, int nlflags, mask 4358 net/core/rtnetlink.c if (brport_nla_put_flag(skb, flags, mask, mask 4360 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4362 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4365 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4367 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4369 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4371 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4373 net/core/rtnetlink.c brport_nla_put_flag(skb, flags, mask, mask 4703 net/core/rtnetlink.c static bool stats_attr_valid(unsigned int mask, int attrid, int idxattr) mask 4705 net/core/rtnetlink.c return (mask & IFLA_STATS_FILTER_BIT(attrid)) && mask 64 net/core/sysctl_net_core.c size = orig_size = orig_sock_table ? orig_sock_table->mask + 1 : 0; mask 84 net/core/sysctl_net_core.c sock_table->mask = size - 1; mask 123 net/core/sysctl_net_core.c cpumask_var_t mask; mask 126 net/core/sysctl_net_core.c if (!alloc_cpumask_var(&mask, GFP_KERNEL)) mask 130 net/core/sysctl_net_core.c ret = cpumask_parse_user(buffer, *lenp, mask); mask 140 net/core/sysctl_net_core.c if (cur && !cpumask_test_cpu(i, mask)) { mask 144 net/core/sysctl_net_core.c } else if (!cur && cpumask_test_cpu(i, mask)) { mask 166 net/core/sysctl_net_core.c cpumask_clear(mask); mask 171 net/core/sysctl_net_core.c cpumask_set_cpu(i, mask); mask 176 net/core/sysctl_net_core.c len = scnprintf(kbuf, len, "%*pb", cpumask_pr_args(mask)); mask 192 net/core/sysctl_net_core.c free_cpumask_var(mask); mask 2040 net/dcb/dcbnl.c u8 mask = 0; mask 2048 net/dcb/dcbnl.c mask |= 1 << itr->app.priority; mask 2052 net/dcb/dcbnl.c return mask; mask 321 net/dccp/proto.c __poll_t mask; mask 333 net/dccp/proto.c mask = 0; mask 335 net/dccp/proto.c mask = EPOLLERR; mask 338 net/dccp/proto.c mask |= EPOLLHUP; mask 340 net/dccp/proto.c mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; mask 345 net/dccp/proto.c mask |= EPOLLIN | EPOLLRDNORM; mask 349 net/dccp/proto.c mask |= EPOLLOUT | EPOLLWRNORM; mask 359 net/dccp/proto.c mask |= EPOLLOUT | EPOLLWRNORM; mask 363 net/dccp/proto.c return mask; mask 1206 net/decnet/af_decnet.c __poll_t mask = datagram_poll(file, sock, wait); mask 1209 net/decnet/af_decnet.c mask |= EPOLLRDBAND; mask 1211 net/decnet/af_decnet.c return mask; mask 943 net/decnet/dn_route.c __le16 mask = dnet_make_mask(res->prefixlen); mask 944 net/decnet/dn_route.c return (daddr&~mask)|res->fi->fib_nh->nh_gw; mask 195 net/hsr/hsr_device.c netdev_features_t mask; mask 198 net/hsr/hsr_device.c mask = features; mask 211 net/hsr/hsr_device.c mask); mask 309 net/ieee802154/nl802154.c nl802154_put_flags(struct sk_buff *msg, int attr, u32 mask) mask 318 net/ieee802154/nl802154.c while (mask) { mask 319 net/ieee802154/nl802154.c if ((mask & 1) && nla_put_flag(msg, i)) mask 322 net/ieee802154/nl802154.c mask >>= 1; mask 999 net/ipv4/arp.c __be32 mask = ((struct sockaddr_in *)&r->arp_netmask)->sin_addr.s_addr; mask 1001 net/ipv4/arp.c if (mask && mask != htonl(0xFFFFFFFF)) mask 1009 net/ipv4/arp.c if (mask) { mask 1137 net/ipv4/arp.c __be32 mask = ((struct sockaddr_in *)&r->arp_netmask)->sin_addr.s_addr; mask 1139 net/ipv4/arp.c if (mask == htonl(0xFFFFFFFF)) mask 1142 net/ipv4/arp.c if (mask) mask 605 net/ipv4/devinet.c __be32 mask) mask 612 net/ipv4/devinet.c if (ifa->ifa_mask == mask && inet_ifa_match(prefix, ifa)) mask 498 net/ipv4/fib_frontend.c __be32 mask = sk_extract_addr(&rt->rt_genmask); mask 501 net/ipv4/fib_frontend.c if (mask || rt->rt_genmask.sa_family) mask 505 net/ipv4/fib_frontend.c if (bad_mask(mask, addr)) mask 508 net/ipv4/fib_frontend.c plen = inet_mask_len(mask); mask 1104 net/ipv4/fib_frontend.c __be32 mask = ifa->ifa_mask; mask 1106 net/ipv4/fib_frontend.c __be32 prefix = ifa->ifa_address & mask; mask 1109 net/ipv4/fib_frontend.c prim = inet_ifa_byprefix(in_dev, prefix, mask); mask 1138 net/ipv4/fib_frontend.c fib_magic(RTM_NEWROUTE, RTN_BROADCAST, prefix | ~mask, mask 321 net/ipv4/fib_semantics.c unsigned int mask = DEVINDEX_HASHSIZE - 1; mask 325 net/ipv4/fib_semantics.c (val >> (DEVINDEX_HASHBITS * 2))) & mask; mask 342 net/ipv4/fib_semantics.c unsigned int mask = (fib_info_hash_size - 1); mask 344 net/ipv4/fib_semantics.c return (val ^ (val >> 7) ^ (val >> 12)) & mask; mask 1200 net/ipv4/fib_semantics.c unsigned int mask = (fib_info_hash_size - 1); mask 1204 net/ipv4/fib_semantics.c ((__force u32)val >> 14)) & mask; mask 2754 net/ipv4/fib_trie.c static unsigned int fib_flag_trans(int type, __be32 mask, struct fib_info *fi) mask 2766 net/ipv4/fib_trie.c if (mask == htonl(0xFFFFFFFF)) mask 2797 net/ipv4/fib_trie.c __be32 mask = inet_make_mask(KEYLENGTH - fa->fa_slen); mask 2798 net/ipv4/fib_trie.c unsigned int flags = fib_flag_trans(fa->fa_type, mask, fi); mask 2822 net/ipv4/fib_trie.c mask, mask 2832 net/ipv4/fib_trie.c mask, 0, 0, 0); mask 536 net/ipv4/inet_diag.c __be32 mask; mask 541 net/ipv4/inet_diag.c mask = htonl((0xffffffff) << (32 - bits)); mask 543 net/ipv4/inet_diag.c if ((w1 ^ w2) & mask) mask 640 net/ipv4/inet_diag.c if ((entry->mark & cond->mask) != cond->mark) mask 54 net/ipv4/netfilter/arp_tables.c ret |= (hdr_addr[i] ^ ap->addr[i]) & ap->mask[i]; mask 72 net/ipv4/netfilter/arp_tables.c const u16 *mask = (const u16 *)_mask; mask 76 net/ipv4/netfilter/arp_tables.c ret |= (a[i] ^ b[i]) & mask[i]; mask 41 net/ipv4/nexthop.c unsigned int mask = NH_DEV_HASHSIZE - 1; mask 45 net/ipv4/nexthop.c (val >> (NH_DEV_HASHBITS * 2))) & mask; mask 62 net/ipv4/ping.c static inline u32 ping_hashfn(const struct net *net, u32 num, u32 mask) mask 64 net/ipv4/ping.c u32 res = (num + net_hash_mix(net)) & mask; mask 502 net/ipv4/tcp.c __poll_t mask; mask 518 net/ipv4/tcp.c mask = 0; mask 548 net/ipv4/tcp.c mask |= EPOLLHUP; mask 550 net/ipv4/tcp.c mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; mask 563 net/ipv4/tcp.c mask |= EPOLLIN | EPOLLRDNORM; mask 567 net/ipv4/tcp.c mask |= EPOLLOUT | EPOLLWRNORM; mask 579 net/ipv4/tcp.c mask |= EPOLLOUT | EPOLLWRNORM; mask 582 net/ipv4/tcp.c mask |= EPOLLOUT | EPOLLWRNORM; mask 585 net/ipv4/tcp.c mask |= EPOLLPRI; mask 591 net/ipv4/tcp.c mask |= EPOLLOUT | EPOLLWRNORM; mask 596 net/ipv4/tcp.c mask |= EPOLLERR; mask 598 net/ipv4/tcp.c return mask; mask 995 net/ipv4/tcp_ipv4.c __be32 mask; mask 1010 net/ipv4/tcp_ipv4.c mask = inet_make_mask(key->prefixlen); mask 1011 net/ipv4/tcp_ipv4.c match = (key->addr.a4.s_addr & mask) == mask 1012 net/ipv4/tcp_ipv4.c (addr->a4.s_addr & mask); mask 248 net/ipv4/udp.c rand = (rand | 1) * (udptable->mask + 1); mask 249 net/ipv4/udp.c last = first + udptable->mask + 1; mask 281 net/ipv4/udp.c slot2 &= udptable->mask; mask 282 net/ipv4/udp.c hash2_nulladdr &= udptable->mask; mask 455 net/ipv4/udp.c slot2 = hash2 & udptable->mask; mask 463 net/ipv4/udp.c slot2 = hash2 & udptable->mask; mask 2161 net/ipv4/udp.c udptable->mask; mask 2162 net/ipv4/udp.c hash2 = ipv4_portaddr_hash(net, daddr, hnum) & udptable->mask; mask 2387 net/ipv4/udp.c unsigned int slot = udp_hashfn(net, hnum, udp_table.mask); mask 2418 net/ipv4/udp.c unsigned int slot2 = hash2 & udp_table.mask; mask 2745 net/ipv4/udp.c __poll_t mask = datagram_poll(file, sock, wait); mask 2749 net/ipv4/udp.c mask |= EPOLLIN | EPOLLRDNORM; mask 2752 net/ipv4/udp.c if ((mask & EPOLLRDNORM) && !(file->f_flags & O_NONBLOCK) && mask 2754 net/ipv4/udp.c mask &= ~(EPOLLIN | EPOLLRDNORM); mask 2756 net/ipv4/udp.c return mask; mask 2819 net/ipv4/udp.c for (state->bucket = start; state->bucket <= afinfo->udp_table->mask; mask 2851 net/ipv4/udp.c if (state->bucket <= afinfo->udp_table->mask) mask 2896 net/ipv4/udp.c if (state->bucket <= afinfo->udp_table->mask) mask 3009 net/ipv4/udp.c &table->mask, mask 3013 net/ipv4/udp.c table->hash2 = table->hash + (table->mask + 1); mask 3014 net/ipv4/udp.c for (i = 0; i <= table->mask; i++) { mask 3019 net/ipv4/udp.c for (i = 0; i <= table->mask; i++) { mask 106 net/ipv4/udp_diag.c for (slot = s_slot; slot <= table->mask; s_num = 0, slot++) { mask 44 net/ipv6/netfilter/ip6t_NPT.c __be32 mask; mask 50 net/ipv6/netfilter/ip6t_NPT.c mask = 0; mask 52 net/ipv6/netfilter/ip6t_NPT.c mask = htonl((1 << (i - pfx_len + 32)) - 1); mask 55 net/ipv6/netfilter/ip6t_NPT.c addr->s6_addr32[idx] &= mask; mask 56 net/ipv6/netfilter/ip6t_NPT.c addr->s6_addr32[idx] |= ~mask & npt->dst_pfx.in6.s6_addr32[idx]; mask 191 net/ipv6/udp.c slot2 = hash2 & udptable->mask; mask 199 net/ipv6/udp.c slot2 = hash2 & udptable->mask; mask 760 net/ipv6/udp.c udptable->mask; mask 761 net/ipv6/udp.c hash2 = ipv6_portaddr_hash(net, daddr, hnum) & udptable->mask; mask 957 net/ipv6/udp.c unsigned int slot2 = hash2 & udp_table.mask; mask 1518 net/iucv/af_iucv.c __poll_t mask = 0; mask 1526 net/iucv/af_iucv.c mask |= EPOLLERR | mask 1530 net/iucv/af_iucv.c mask |= EPOLLRDHUP; mask 1533 net/iucv/af_iucv.c mask |= EPOLLHUP; mask 1537 net/iucv/af_iucv.c mask |= EPOLLIN | EPOLLRDNORM; mask 1540 net/iucv/af_iucv.c mask |= EPOLLHUP; mask 1543 net/iucv/af_iucv.c mask |= EPOLLIN; mask 1546 net/iucv/af_iucv.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 1550 net/iucv/af_iucv.c return mask; mask 68 net/mac80211/cfg.c u32 mask = MONITOR_FLAG_COOK_FRAMES | MONITOR_FLAG_ACTIVE; mask 79 net/mac80211/cfg.c if ((params->flags & mask) != (sdata->u.mntr.flags & mask)) mask 1206 net/mac80211/cfg.c u32 mask, u32 set) mask 1210 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED) && mask 1218 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_ASSOCIATED) && mask 1234 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHORIZED)) { mask 1245 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_ASSOCIATED) && mask 1253 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED) && mask 1336 net/mac80211/cfg.c u32 mask, set; mask 1342 net/mac80211/cfg.c mask = params->sta_flags_mask; mask 1350 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_AUTHENTICATED)) mask 1351 net/mac80211/cfg.c mask |= BIT(NL80211_STA_FLAG_ASSOCIATED); mask 1363 net/mac80211/cfg.c mask |= BIT(NL80211_STA_FLAG_AUTHENTICATED) | mask 1368 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_WME) && mask 1375 net/mac80211/cfg.c !((mask & BIT(NL80211_STA_FLAG_ASSOCIATED)) && mask 1377 net/mac80211/cfg.c ret = sta_apply_auth_flags(local, sta, mask, set); mask 1382 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_SHORT_PREAMBLE)) { mask 1389 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_MFP)) { mask 1397 net/mac80211/cfg.c if (mask & BIT(NL80211_STA_FLAG_TDLS_PEER)) { mask 1519 net/mac80211/cfg.c ret = sta_apply_auth_flags(local, sta, mask, set); mask 1940 net/mac80211/cfg.c static inline bool _chg_mesh_attr(enum nl80211_meshconf_params parm, u32 mask) mask 1942 net/mac80211/cfg.c return (mask >> (parm-1)) & 0x1; mask 1994 net/mac80211/cfg.c struct net_device *dev, u32 mask, mask 2006 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask)) mask 2008 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask)) mask 2010 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask)) mask 2012 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask)) mask 2014 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask)) mask 2016 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_TTL, mask)) mask 2018 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask)) mask 2020 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask)) { mask 2025 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask)) mask 2028 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask)) mask 2031 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask)) mask 2033 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask)) mask 2035 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask)) mask 2038 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask)) mask 2041 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask)) mask 2045 net/mac80211/cfg.c mask)) mask 2048 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask)) { mask 2052 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask)) { mask 2064 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask)) mask 2067 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_FORWARDING, mask)) mask 2069 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask)) { mask 2077 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask)) { mask 2082 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask)) mask 2085 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask)) mask 2088 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask)) mask 2091 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask)) { mask 2095 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask)) mask 2098 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask)) mask 2100 net/mac80211/cfg.c if (_chg_mesh_attr(NL80211_MESHCONF_CONNECTED_TO_GATE, mask)) mask 2860 net/mac80211/cfg.c const struct cfg80211_bitrate_mask *mask) mask 2880 net/mac80211/cfg.c if (!(mask->control[band].legacy & basic_rates)) mask 2885 net/mac80211/cfg.c ret = drv_set_bitrate_mask(local, sdata, mask); mask 2894 net/mac80211/cfg.c sdata->rc_rateidx_mask[i] = mask->control[i].legacy; mask 2895 net/mac80211/cfg.c memcpy(sdata->rc_rateidx_mcs_mask[i], mask->control[i].ht_mcs, mask 2896 net/mac80211/cfg.c sizeof(mask->control[i].ht_mcs)); mask 2898 net/mac80211/cfg.c mask->control[i].vht_mcs, mask 2899 net/mac80211/cfg.c sizeof(mask->control[i].vht_mcs)); mask 183 net/mac80211/debugfs_netdev.c const u16 *mask = sdata->rc_rateidx_vht_mcs_mask[NL80211_BAND_2GHZ]; mask 186 net/mac80211/debugfs_netdev.c len += scnprintf(buf + len, buflen - len, "%04x ", mask[i]); mask 199 net/mac80211/debugfs_netdev.c const u16 *mask = sdata->rc_rateidx_vht_mcs_mask[NL80211_BAND_5GHZ]; mask 202 net/mac80211/debugfs_netdev.c len += scnprintf(buf + len, buflen - len, "%04x ", mask[i]); mask 752 net/mac80211/driver-ops.h const struct cfg80211_bitrate_mask *mask) mask 761 net/mac80211/driver-ops.h trace_drv_set_bitrate_mask(local, sdata, mask); mask 764 net/mac80211/driver-ops.h &sdata->vif, mask); mask 157 net/mac80211/iface.c u64 new, mask, tmp; mask 170 net/mac80211/iface.c mask = ((u64)m[0] << 5*8) | ((u64)m[1] << 4*8) | mask 191 net/mac80211/iface.c if ((new & ~mask) != (tmp & ~mask)) { mask 1594 net/mac80211/iface.c u64 mask, start, addr, val, inc; mask 1662 net/mac80211/iface.c mask = ((u64)m[0] << 5*8) | ((u64)m[1] << 4*8) | mask 1666 net/mac80211/iface.c if (__ffs64(mask) + hweight64(mask) != fls64(mask)) { mask 1687 net/mac80211/iface.c inc = 1ULL<<__ffs64(mask); mask 1688 net/mac80211/iface.c val = (start & mask); mask 1689 net/mac80211/iface.c addr = (start & ~mask) | (val & mask); mask 1713 net/mac80211/iface.c addr = (start & ~mask) | (val & mask); mask 536 net/mac80211/mlme.c u32 mask, ap_bf_sts, our_bf_sts; mask 595 net/mac80211/mlme.c mask = IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK; mask 597 net/mac80211/mlme.c ap_bf_sts = le32_to_cpu(ap_vht_cap->vht_cap_info) & mask; mask 598 net/mac80211/mlme.c our_bf_sts = cap & mask; mask 601 net/mac80211/mlme.c cap &= ~mask; mask 400 net/mac80211/rate.c static bool rate_idx_match_legacy_mask(s8 *rate_idx, int n_bitrates, u32 mask) mask 406 net/mac80211/rate.c if (mask & (1 << j)) { mask 415 net/mac80211/rate.c if (mask & (1 << j)) { mask 502 net/mac80211/rate.c u32 mask, mask 528 net/mac80211/rate.c mask)) mask 542 net/mac80211/rate.c mask)) mask 547 net/mac80211/rate.c mask)) mask 727 net/mac80211/rate.c struct ieee80211_sta *sta, u32 *mask, mask 733 net/mac80211/rate.c *mask = sdata->rc_rateidx_mask[sband->band]; mask 737 net/mac80211/rate.c *mask &= ~BIT(i); mask 740 net/mac80211/rate.c if (*mask == (1 << sband->n_bitrates) - 1 && mask 762 net/mac80211/rate.c *mask &= sta->supp_rates[sband->band]; mask 781 net/mac80211/rate.c u32 mask; mask 786 net/mac80211/rate.c if (!rate_control_cap_mask(sta->sdata, sband, &sta->sta, &mask, mask 796 net/mac80211/rate.c sband, chan_width, mask, mcs_mask, mask 809 net/mac80211/rate.c u32 mask; mask 818 net/mac80211/rate.c if (!rate_control_cap_mask(sdata, sband, sta, &mask, mcs_mask, mask 835 net/mac80211/rate.c chan_width, mask, mcs_mask, vht_mask); mask 251 net/mac80211/rc80211_minstrel_ht.c u16 mask = 0; mask 255 net/mac80211/rc80211_minstrel_ht.c mask = BIT(9); mask 258 net/mac80211/rc80211_minstrel_ht.c mask = BIT(6); mask 260 net/mac80211/rc80211_minstrel_ht.c mask = BIT(9); mask 267 net/mac80211/rc80211_minstrel_ht.c mask |= 0x300; mask 270 net/mac80211/rc80211_minstrel_ht.c mask |= 0x200; mask 275 net/mac80211/rc80211_minstrel_ht.c mask = 0x3ff; mask 278 net/mac80211/rc80211_minstrel_ht.c return 0x3ff & ~mask; mask 2392 net/mac80211/sta_info.c sinfo->sta_flags.mask = BIT(NL80211_STA_FLAG_AUTHORIZED) | mask 1316 net/mac80211/trace.h const struct cfg80211_bitrate_mask *mask), mask 1318 net/mac80211/trace.h TP_ARGS(local, sdata, mask), mask 1330 net/mac80211/trace.h __entry->legacy_2g = mask->control[NL80211_BAND_2GHZ].legacy; mask 1331 net/mac80211/trace.h __entry->legacy_5g = mask->control[NL80211_BAND_5GHZ].legacy; mask 610 net/mac80211/vht.c u16 mask, cap = le16_to_cpu(vht_cap); mask 613 net/mac80211/vht.c mask = (cap >> i * 2) & IEEE80211_VHT_MCS_NOT_SUPPORTED; mask 614 net/mac80211/vht.c switch (mask) { mask 290 net/netfilter/ipset/ip_set_bitmap_ip.c u32 mask; mask 292 net/netfilter/ipset/ip_set_bitmap_ip.c mask = range_to_mask(first_ip, last_ip, &mask_bits); mask 294 net/netfilter/ipset/ip_set_bitmap_ip.c if ((!mask && (first_ip || last_ip != 0xFFFFFFFF)) || mask 3036 net/netfilter/ipvs/ip_vs_ctl.c .mask = ~0 }; mask 3223 net/netfilter/ipvs/ip_vs_ctl.c usvc->flags = (usvc->flags & ~flags.mask) | mask 3224 net/netfilter/ipvs/ip_vs_ctl.c (flags.flags & flags.mask); mask 28 net/netfilter/nf_conntrack_broadcast.c __be32 mask = 0; mask 47 net/netfilter/nf_conntrack_broadcast.c mask = ifa->ifa_mask; mask 53 net/netfilter/nf_conntrack_broadcast.c if (mask == 0) mask 63 net/netfilter/nf_conntrack_broadcast.c exp->mask.src.u3.ip = mask; mask 64 net/netfilter/nf_conntrack_broadcast.c exp->mask.src.u.udp.port = htons(0xFFFF); mask 100 net/netfilter/nf_conntrack_expect.c return nf_ct_tuple_mask_cmp(tuple, &i->tuple, &i->mask) && mask 239 net/netfilter/nf_conntrack_expect.c intersect_mask.src.u.all = a->mask.src.u.all & b->mask.src.u.all; mask 243 net/netfilter/nf_conntrack_expect.c a->mask.src.u3.all[count] & b->mask.src.u3.all[count]; mask 255 net/netfilter/nf_conntrack_expect.c nf_ct_tuple_mask_equal(&a->mask, &b->mask) && mask 322 net/netfilter/nf_conntrack_expect.c memset(&exp->mask.src.u3, 0xFF, len); mask 323 net/netfilter/nf_conntrack_expect.c if (sizeof(exp->mask.src.u3) > len) mask 324 net/netfilter/nf_conntrack_expect.c memset((void *)&exp->mask.src.u3 + len, 0x00, mask 325 net/netfilter/nf_conntrack_expect.c sizeof(exp->mask.src.u3) - len); mask 328 net/netfilter/nf_conntrack_expect.c memset(&exp->mask.src.u3, 0x00, sizeof(exp->mask.src.u3)); mask 333 net/netfilter/nf_conntrack_expect.c exp->mask.src.u.all = htons(0xFFFF); mask 336 net/netfilter/nf_conntrack_expect.c exp->mask.src.u.all = 0; mask 58 net/netfilter/nf_conntrack_helper.c struct nf_conntrack_tuple_mask mask = { .src.u.all = htons(0xFFFF) }; mask 66 net/netfilter/nf_conntrack_helper.c if (nf_ct_tuple_src_mask_cmp(tuple, &helper->tuple, &mask)) mask 398 net/netfilter/nf_conntrack_helper.c struct nf_conntrack_tuple_mask mask = { .src.u.all = htons(0xFFFF) }; mask 427 net/netfilter/nf_conntrack_helper.c &mask)) { mask 16 net/netfilter/nf_conntrack_labels.c static int replace_u32(u32 *address, u32 mask, u32 new) mask 22 net/netfilter/nf_conntrack_labels.c tmp = (old & mask) ^ new; mask 32 net/netfilter/nf_conntrack_labels.c const u32 *mask, unsigned int words32) mask 49 net/netfilter/nf_conntrack_labels.c changed |= replace_u32(&dst[i], mask ? ~mask[i] : 0, data[i]); mask 831 net/netfilter/nf_conntrack_netlink.c u_int32_t mask; mask 854 net/netfilter/nf_conntrack_netlink.c filter->mark.mask = ntohl(nla_get_be32(cda[CTA_MARK_MASK])); mask 892 net/netfilter/nf_conntrack_netlink.c if ((ct->mark & filter->mark.mask) != filter->mark.val) mask 1704 net/netfilter/nf_conntrack_netlink.c u32 mark, newmark, mask = 0; mask 1707 net/netfilter/nf_conntrack_netlink.c mask = ~ntohl(nla_get_be32(cda[CTA_MARK_MASK])); mask 1710 net/netfilter/nf_conntrack_netlink.c newmark = (ct->mark & mask) ^ mark; mask 1855 net/netfilter/nf_conntrack_netlink.c const void *mask = cda[CTA_LABELS_MASK]; mask 1860 net/netfilter/nf_conntrack_netlink.c if (mask) { mask 1864 net/netfilter/nf_conntrack_netlink.c mask = nla_data(cda[CTA_LABELS_MASK]); mask 1869 net/netfilter/nf_conntrack_netlink.c return nf_connlabels_replace(ct, nla_data(cda[CTA_LABELS]), mask, len); mask 2367 net/netfilter/nf_conntrack_netlink.c struct nf_conntrack_tuple *mask); mask 2575 net/netfilter/nf_conntrack_netlink.c struct nf_conntrack_tuple *mask) mask 2584 net/netfilter/nf_conntrack_netlink.c return ctnetlink_parse_tuple(cda, mask, CTA_EXPECT_MASK, mask 2593 net/netfilter/nf_conntrack_netlink.c struct nf_conntrack_tuple tuple, mask; mask 2604 net/netfilter/nf_conntrack_netlink.c ct, &tuple, &mask); mask 2618 net/netfilter/nf_conntrack_netlink.c helper, &tuple, &mask); mask 2671 net/netfilter/nf_conntrack_netlink.c const struct nf_conntrack_tuple_mask *mask) mask 2679 net/netfilter/nf_conntrack_netlink.c memcpy(&m.src.u3, &mask->src.u3, sizeof(m.src.u3)); mask 2680 net/netfilter/nf_conntrack_netlink.c m.src.u.all = mask->src.u.all; mask 2745 net/netfilter/nf_conntrack_netlink.c if (ctnetlink_exp_dump_mask(skb, &exp->tuple, &exp->mask) < 0) mask 3249 net/netfilter/nf_conntrack_netlink.c struct nf_conntrack_tuple *mask) mask 3292 net/netfilter/nf_conntrack_netlink.c exp->mask.src.u3 = mask->src.u3; mask 3293 net/netfilter/nf_conntrack_netlink.c exp->mask.src.u.all = mask->src.u.all; mask 3313 net/netfilter/nf_conntrack_netlink.c struct nf_conntrack_tuple tuple, mask, master_tuple; mask 3325 net/netfilter/nf_conntrack_netlink.c err = ctnetlink_parse_tuple(cda, &mask, CTA_EXPECT_MASK, mask 3367 net/netfilter/nf_conntrack_netlink.c exp = ctnetlink_alloc_expect(cda, ct, helper, &tuple, &mask); mask 1266 net/netfilter/nf_conntrack_proto_tcp.c ct->proto.tcp.seen[0].flags &= ~attr->mask; mask 1267 net/netfilter/nf_conntrack_proto_tcp.c ct->proto.tcp.seen[0].flags |= attr->flags & attr->mask; mask 1273 net/netfilter/nf_conntrack_proto_tcp.c ct->proto.tcp.seen[1].flags &= ~attr->mask; mask 1274 net/netfilter/nf_conntrack_proto_tcp.c ct->proto.tcp.seen[1].flags |= attr->flags & attr->mask; mask 54 net/netfilter/nf_tables_core.c u32 mask = nft_cmp_fast_mask(priv->len); mask 56 net/netfilter/nf_tables_core.c if ((regs->data[priv->sreg] & mask) == priv->data) mask 25 net/netfilter/nf_tables_offload.c flow->rule->match.mask = &flow->match.mask; mask 41 net/netfilter/nfnetlink_acct.c u32 mask; mask 210 net/netfilter/nfnetlink_acct.c if (filter && (cur->flags & filter->mask) != filter->value) mask 260 net/netfilter/nfnetlink_acct.c filter->mask = ntohl(nla_get_be32(tb[NFACCT_FILTER_MASK])); mask 1264 net/netfilter/nfnetlink_queue.c __u32 flags = 0, mask = 0; mask 1289 net/netfilter/nfnetlink_queue.c mask = ntohl(nla_get_be32(nfqa[NFQA_CFG_MASK])); mask 1295 net/netfilter/nfnetlink_queue.c if (flags & mask & NFQA_CFG_F_SECCTX) mask 1298 net/netfilter/nfnetlink_queue.c if ((flags & mask & NFQA_CFG_F_CONNTRACK) && mask 1371 net/netfilter/nfnetlink_queue.c queue->flags &= ~mask; mask 1372 net/netfilter/nfnetlink_queue.c queue->flags |= flags & mask; mask 22 net/netfilter/nft_bitwise.c struct nft_data mask; mask 35 net/netfilter/nft_bitwise.c dst[i] = (src[i] & priv->mask.data[i]) ^ priv->xor.data[i]; mask 79 net/netfilter/nft_bitwise.c err = nft_data_init(NULL, &priv->mask, sizeof(priv->mask), &d1, mask 101 net/netfilter/nft_bitwise.c nft_data_release(&priv->mask, d1.type); mask 116 net/netfilter/nft_bitwise.c if (nft_data_dump(skb, NFTA_BITWISE_MASK, &priv->mask, mask 143 net/netfilter/nft_bitwise.c memcpy(®->mask, &priv->mask, sizeof(priv->mask)); mask 122 net/netfilter/nft_cmp.c u8 *mask = (u8 *)&flow->match.mask; mask 129 net/netfilter/nft_cmp.c memcpy(mask + reg->offset, ®->mask, priv->len); mask 164 net/netfilter/nft_cmp.c u32 mask; mask 178 net/netfilter/nft_cmp.c mask = nft_cmp_fast_mask(desc.len); mask 180 net/netfilter/nft_cmp.c priv->data = data.data[0] & mask; mask 395 net/netfilter/x_tables.c textify_hooks(char *buf, size_t size, unsigned int mask, uint8_t nfproto) mask 415 net/netfilter/x_tables.c if (!(mask & (1 << i))) mask 40 net/netfilter/xt_HMARK.c static inline __be32 hmark_addr6_mask(const __be32 *addr32, const __be32 *mask) mask 42 net/netfilter/xt_HMARK.c return (addr32[0] & mask[0]) ^ mask 43 net/netfilter/xt_HMARK.c (addr32[1] & mask[1]) ^ mask 44 net/netfilter/xt_HMARK.c (addr32[2] & mask[2]) ^ mask 45 net/netfilter/xt_HMARK.c (addr32[3] & mask[3]); mask 49 net/netfilter/xt_HMARK.c hmark_addr_mask(int l3num, const __be32 *addr32, const __be32 *mask) mask 53 net/netfilter/xt_HMARK.c return *addr32 & *mask; mask 55 net/netfilter/xt_HMARK.c return hmark_addr6_mask(addr32, mask); mask 34 net/netfilter/xt_addrtype.c const struct in6_addr *addr, u16 mask) mask 46 net/netfilter/xt_addrtype.c if (dev && (mask & XT_ADDRTYPE_LOCAL)) { mask 69 net/netfilter/xt_addrtype.c const struct in6_addr *addr, u16 mask) mask 73 net/netfilter/xt_addrtype.c if ((mask & XT_ADDRTYPE_MULTICAST) && mask 76 net/netfilter/xt_addrtype.c if ((mask & XT_ADDRTYPE_UNICAST) && !(addr_type & IPV6_ADDR_UNICAST)) mask 78 net/netfilter/xt_addrtype.c if ((mask & XT_ADDRTYPE_UNSPEC) && addr_type != IPV6_ADDR_ANY) mask 82 net/netfilter/xt_addrtype.c XT_ADDRTYPE_UNREACHABLE) & mask) mask 83 net/netfilter/xt_addrtype.c return !!(mask & match_lookup_rt6(net, dev, addr, mask)); mask 105 net/netfilter/xt_addrtype.c __be32 addr, u_int16_t mask) mask 107 net/netfilter/xt_addrtype.c return !!(mask & (1 << inet_dev_addr_type(net, dev, addr))); mask 60 net/netfilter/xt_connlimit.c addr.ip6[i] &= info->mask.ip6[i]; mask 68 net/netfilter/xt_connlimit.c key[0] &= info->mask.ip; mask 129 net/netfilter/xt_connmark.c return ((ct->mark & info->mask) == info->mark) ^ info->invert; mask 30 net/netfilter/xt_mark.c skb->mark = (skb->mark & ~info->mask) ^ info->mark; mask 39 net/netfilter/xt_mark.c return ((skb->mark & info->mask) == info->mark) ^ info->invert; mask 27 net/netfilter/xt_realm.c return (info->id == (dst->tclassid & info->mask)) ^ info->invert; mask 80 net/netfilter/xt_recent.c union nf_inet_addr mask; mask 272 net/netfilter/xt_recent.c nf_inet_addr_mask(&addr, &addr_mask, &t->mask); mask 394 net/netfilter/xt_recent.c memcpy(&t->mask, &info->mask, sizeof(t->mask)); mask 433 net/netfilter/xt_recent.c memset(info_v1.mask.all, 0xFF, sizeof(info_v1.mask.all)); mask 52 net/netlabel/netlabel_addrlist.c if (iter->valid && (addr & iter->mask) == iter->addr) mask 71 net/netlabel/netlabel_addrlist.c __be32 mask, mask 77 net/netlabel/netlabel_addrlist.c if (iter->valid && iter->addr == addr && iter->mask == mask) mask 103 net/netlabel/netlabel_addrlist.c ipv6_masked_addr_cmp(&iter->addr, &iter->mask, addr) == 0) mask 122 net/netlabel/netlabel_addrlist.c const struct in6_addr *mask, mask 130 net/netlabel/netlabel_addrlist.c ipv6_addr_equal(&iter->mask, mask)) mask 154 net/netlabel/netlabel_addrlist.c iter->addr == entry->addr && iter->mask == entry->mask) mask 163 net/netlabel/netlabel_addrlist.c ntohl(entry->mask) > ntohl(iter->mask)) { mask 192 net/netlabel/netlabel_addrlist.c ipv6_addr_equal(&iter->mask, &entry->mask)) mask 201 net/netlabel/netlabel_addrlist.c ipv6_addr_cmp(&entry->mask, &iter->mask) > 0) { mask 239 net/netlabel/netlabel_addrlist.c struct netlbl_af4list *netlbl_af4list_remove(__be32 addr, __be32 mask, mask 244 net/netlabel/netlabel_addrlist.c entry = netlbl_af4list_search_exact(addr, mask, head); mask 280 net/netlabel/netlabel_addrlist.c const struct in6_addr *mask, mask 285 net/netlabel/netlabel_addrlist.c entry = netlbl_af6list_search_exact(addr, mask, head); mask 312 net/netlabel/netlabel_addrlist.c __be32 addr, __be32 mask) mask 314 net/netlabel/netlabel_addrlist.c u32 mask_val = ntohl(mask); mask 347 net/netlabel/netlabel_addrlist.c const struct in6_addr *mask) mask 354 net/netlabel/netlabel_addrlist.c if (ntohl(mask->s6_addr32[3]) != 0xffffffff) { mask 358 net/netlabel/netlabel_addrlist.c while (ntohl(mask->s6_addr32[++iter]) == 0xffffffff) mask 360 net/netlabel/netlabel_addrlist.c mask_val = ntohl(mask->s6_addr32[iter]); mask 35 net/netlabel/netlabel_addrlist.h __be32 mask; mask 50 net/netlabel/netlabel_addrlist.h struct in6_addr mask; mask 100 net/netlabel/netlabel_addrlist.h struct netlbl_af4list *netlbl_af4list_remove(__be32 addr, __be32 mask, mask 106 net/netlabel/netlabel_addrlist.h __be32 mask, mask 112 net/netlabel/netlabel_addrlist.h __be32 addr, __be32 mask); mask 116 net/netlabel/netlabel_addrlist.h __be32 addr, __be32 mask) mask 168 net/netlabel/netlabel_addrlist.h const struct in6_addr *mask, mask 174 net/netlabel/netlabel_addrlist.h const struct in6_addr *mask, mask 182 net/netlabel/netlabel_addrlist.h const struct in6_addr *mask); mask 188 net/netlabel/netlabel_addrlist.h const struct in6_addr *mask) mask 227 net/netlabel/netlabel_domainhash.c addr4->addr, addr4->mask); mask 235 net/netlabel/netlabel_domainhash.c &addr6->addr, &addr6->mask); mask 502 net/netlabel/netlabel_domainhash.c iter4->mask, mask 510 net/netlabel/netlabel_domainhash.c &iter6->mask, mask 661 net/netlabel/netlabel_domainhash.c const struct in_addr *mask, mask 683 net/netlabel/netlabel_domainhash.c entry_addr = netlbl_af4list_remove(addr->s_addr, mask->s_addr, mask 730 net/netlabel/netlabel_domainhash.c const struct in6_addr *mask, mask 750 net/netlabel/netlabel_domainhash.c entry_addr = netlbl_af6list_remove(addr, mask, mask 80 net/netlabel/netlabel_domainhash.h const struct in_addr *mask, mask 84 net/netlabel/netlabel_domainhash.h const struct in6_addr *mask, mask 97 net/netlabel/netlabel_domainhash.h const struct in6_addr *mask, mask 59 net/netlabel/netlabel_kapi.c const void *mask, mask 62 net/netlabel/netlabel_kapi.c if (addr == NULL && mask == NULL) { mask 64 net/netlabel/netlabel_kapi.c } else if (addr != NULL && mask != NULL) { mask 67 net/netlabel/netlabel_kapi.c return netlbl_domhsh_remove_af4(domain, addr, mask, mask 71 net/netlabel/netlabel_kapi.c return netlbl_domhsh_remove_af6(domain, addr, mask, mask 98 net/netlabel/netlabel_kapi.c const void *mask, mask 117 net/netlabel/netlabel_kapi.c if (addr == NULL && mask == NULL) mask 119 net/netlabel/netlabel_kapi.c else if (addr != NULL && mask != NULL) { mask 129 net/netlabel/netlabel_kapi.c const struct in_addr *mask4 = mask; mask 135 net/netlabel/netlabel_kapi.c map4->list.mask = mask4->s_addr; mask 146 net/netlabel/netlabel_kapi.c const struct in6_addr *mask6 = mask; mask 156 net/netlabel/netlabel_kapi.c map6->list.mask = *mask6; mask 211 net/netlabel/netlabel_kapi.c const void *mask, mask 232 net/netlabel/netlabel_kapi.c dev_name, addr, mask, addr_len, mask 254 net/netlabel/netlabel_kapi.c const void *mask, mask 274 net/netlabel/netlabel_kapi.c dev_name, addr, mask, addr_len, mask 326 net/netlabel/netlabel_kapi.c const struct in_addr *mask, mask 349 net/netlabel/netlabel_kapi.c if (addr == NULL && mask == NULL) { mask 352 net/netlabel/netlabel_kapi.c } else if (addr != NULL && mask != NULL) { mask 364 net/netlabel/netlabel_kapi.c addrinfo->list.addr = addr->s_addr & mask->s_addr; mask 365 net/netlabel/netlabel_kapi.c addrinfo->list.mask = mask->s_addr; mask 451 net/netlabel/netlabel_kapi.c const struct in6_addr *mask, mask 475 net/netlabel/netlabel_kapi.c if (addr == NULL && mask == NULL) { mask 478 net/netlabel/netlabel_kapi.c } else if (addr != NULL && mask != NULL) { mask 491 net/netlabel/netlabel_kapi.c addrinfo->list.addr.s6_addr32[0] &= mask->s6_addr32[0]; mask 492 net/netlabel/netlabel_kapi.c addrinfo->list.addr.s6_addr32[1] &= mask->s6_addr32[1]; mask 493 net/netlabel/netlabel_kapi.c addrinfo->list.addr.s6_addr32[2] &= mask->s6_addr32[2]; mask 494 net/netlabel/netlabel_kapi.c addrinfo->list.addr.s6_addr32[3] &= mask->s6_addr32[3]; mask 495 net/netlabel/netlabel_kapi.c addrinfo->list.mask = *mask; mask 149 net/netlabel/netlabel_mgmt.c struct in_addr *mask; mask 171 net/netlabel/netlabel_mgmt.c mask = nla_data(info->attrs[NLBL_MGMT_A_IPV4MASK]); mask 178 net/netlabel/netlabel_mgmt.c map->list.addr = addr->s_addr & mask->s_addr; mask 179 net/netlabel/netlabel_mgmt.c map->list.mask = mask->s_addr; mask 197 net/netlabel/netlabel_mgmt.c struct in6_addr *mask; mask 219 net/netlabel/netlabel_mgmt.c mask = nla_data(info->attrs[NLBL_MGMT_A_IPV6MASK]); mask 227 net/netlabel/netlabel_mgmt.c map->list.addr.s6_addr32[0] &= mask->s6_addr32[0]; mask 228 net/netlabel/netlabel_mgmt.c map->list.addr.s6_addr32[1] &= mask->s6_addr32[1]; mask 229 net/netlabel/netlabel_mgmt.c map->list.addr.s6_addr32[2] &= mask->s6_addr32[2]; mask 230 net/netlabel/netlabel_mgmt.c map->list.addr.s6_addr32[3] &= mask->s6_addr32[3]; mask 231 net/netlabel/netlabel_mgmt.c map->list.mask = *mask; mask 322 net/netlabel/netlabel_mgmt.c addr_struct.s_addr = iter4->mask; mask 357 net/netlabel/netlabel_mgmt.c &iter6->mask); mask 232 net/netlabel/netlabel_unlabeled.c const struct in_addr *mask, mask 242 net/netlabel/netlabel_unlabeled.c entry->list.addr = addr->s_addr & mask->s_addr; mask 243 net/netlabel/netlabel_unlabeled.c entry->list.mask = mask->s_addr; mask 272 net/netlabel/netlabel_unlabeled.c const struct in6_addr *mask, mask 283 net/netlabel/netlabel_unlabeled.c entry->list.addr.s6_addr32[0] &= mask->s6_addr32[0]; mask 284 net/netlabel/netlabel_unlabeled.c entry->list.addr.s6_addr32[1] &= mask->s6_addr32[1]; mask 285 net/netlabel/netlabel_unlabeled.c entry->list.addr.s6_addr32[2] &= mask->s6_addr32[2]; mask 286 net/netlabel/netlabel_unlabeled.c entry->list.addr.s6_addr32[3] &= mask->s6_addr32[3]; mask 287 net/netlabel/netlabel_unlabeled.c entry->list.mask = *mask; mask 366 net/netlabel/netlabel_unlabeled.c const void *mask, mask 408 net/netlabel/netlabel_unlabeled.c const struct in_addr *mask4 = mask; mask 421 net/netlabel/netlabel_unlabeled.c const struct in6_addr *mask6 = mask; mask 468 net/netlabel/netlabel_unlabeled.c const struct in_addr *mask, mask 479 net/netlabel/netlabel_unlabeled.c list_entry = netlbl_af4list_remove(addr->s_addr, mask->s_addr, mask 493 net/netlabel/netlabel_unlabeled.c addr->s_addr, mask->s_addr); mask 530 net/netlabel/netlabel_unlabeled.c const struct in6_addr *mask, mask 541 net/netlabel/netlabel_unlabeled.c list_entry = netlbl_af6list_remove(addr, mask, &iface->addr6_list); mask 554 net/netlabel/netlabel_unlabeled.c addr, mask); mask 630 net/netlabel/netlabel_unlabeled.c const void *mask, mask 659 net/netlabel/netlabel_unlabeled.c iface, addr, mask, mask 665 net/netlabel/netlabel_unlabeled.c iface, addr, mask, mask 765 net/netlabel/netlabel_unlabeled.c void **mask, mask 778 net/netlabel/netlabel_unlabeled.c *mask = nla_data(info->attrs[NLBL_UNLABEL_A_IPV4MASK]); mask 787 net/netlabel/netlabel_unlabeled.c *mask = nla_data(info->attrs[NLBL_UNLABEL_A_IPV6MASK]); mask 882 net/netlabel/netlabel_unlabeled.c void *mask; mask 901 net/netlabel/netlabel_unlabeled.c ret_val = netlbl_unlabel_addrinfo_get(info, &addr, &mask, &addr_len); mask 913 net/netlabel/netlabel_unlabeled.c dev_name, addr, mask, addr_len, secid, mask 933 net/netlabel/netlabel_unlabeled.c void *mask; mask 951 net/netlabel/netlabel_unlabeled.c ret_val = netlbl_unlabel_addrinfo_get(info, &addr, &mask, &addr_len); mask 962 net/netlabel/netlabel_unlabeled.c NULL, addr, mask, addr_len, secid, mask 983 net/netlabel/netlabel_unlabeled.c void *mask; mask 998 net/netlabel/netlabel_unlabeled.c ret_val = netlbl_unlabel_addrinfo_get(info, &addr, &mask, &addr_len); mask 1004 net/netlabel/netlabel_unlabeled.c dev_name, addr, mask, addr_len, mask 1024 net/netlabel/netlabel_unlabeled.c void *mask; mask 1038 net/netlabel/netlabel_unlabeled.c ret_val = netlbl_unlabel_addrinfo_get(info, &addr, &mask, &addr_len); mask 1043 net/netlabel/netlabel_unlabeled.c NULL, addr, mask, addr_len, mask 1107 net/netlabel/netlabel_unlabeled.c addr_struct.s_addr = addr4->list.mask; mask 1124 net/netlabel/netlabel_unlabeled.c &addr6->list.mask); mask 212 net/netlabel/netlabel_unlabeled.h const void *mask, mask 219 net/netlabel/netlabel_unlabeled.h const void *mask, mask 537 net/netlink/af_netlink.c unsigned long mask; mask 546 net/netlink/af_netlink.c mask = 0; mask 549 net/netlink/af_netlink.c mask |= nlk_sk(sk)->groups[i]; mask 551 net/netlink/af_netlink.c listeners->masks[i] = mask; mask 155 net/nfc/digital_technology.c u64 mask; mask 903 net/nfc/digital_technology.c skb_put(skb, sizeof(*req) - sizeof(req->mask)); /* No mask */ mask 548 net/nfc/llcp_sock.c __poll_t mask = 0; mask 558 net/nfc/llcp_sock.c mask |= EPOLLERR | mask 562 net/nfc/llcp_sock.c mask |= EPOLLIN | EPOLLRDNORM; mask 565 net/nfc/llcp_sock.c mask |= EPOLLHUP; mask 568 net/nfc/llcp_sock.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 571 net/nfc/llcp_sock.c mask |= EPOLLHUP; mask 574 net/nfc/llcp_sock.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 578 net/nfc/llcp_sock.c pr_debug("mask 0x%x\n", mask); mask 580 net/nfc/llcp_sock.c return mask; mask 193 net/openvswitch/actions.c const __be32 *mpls_lse, const __be32 *mask) mask 200 net/openvswitch/actions.c lse = OVS_MASKED(stack->label_stack_entry, *mpls_lse, *mask); mask 241 net/openvswitch/actions.c const u16 *mask = (const u16 *)mask_; mask 243 net/openvswitch/actions.c OVS_SET_MASKED(dst[0], src[0], mask[0]); mask 244 net/openvswitch/actions.c OVS_SET_MASKED(dst[1], src[1], mask[1]); mask 245 net/openvswitch/actions.c OVS_SET_MASKED(dst[2], src[2], mask[2]); mask 250 net/openvswitch/actions.c const struct ovs_key_ethernet *mask) mask 261 net/openvswitch/actions.c mask->eth_src); mask 263 net/openvswitch/actions.c mask->eth_dst); mask 408 net/openvswitch/actions.c const __be32 mask[4], __be32 masked[4]) mask 410 net/openvswitch/actions.c masked[0] = OVS_MASKED(old[0], addr[0], mask[0]); mask 411 net/openvswitch/actions.c masked[1] = OVS_MASKED(old[1], addr[1], mask[1]); mask 412 net/openvswitch/actions.c masked[2] = OVS_MASKED(old[2], addr[2], mask[2]); mask 413 net/openvswitch/actions.c masked[3] = OVS_MASKED(old[3], addr[3], mask[3]); mask 427 net/openvswitch/actions.c static void set_ipv6_fl(struct ipv6hdr *nh, u32 fl, u32 mask) mask 430 net/openvswitch/actions.c OVS_SET_MASKED(nh->flow_lbl[0], (u8)(fl >> 16), (u8)(mask >> 16)); mask 431 net/openvswitch/actions.c OVS_SET_MASKED(nh->flow_lbl[1], (u8)(fl >> 8), (u8)(mask >> 8)); mask 432 net/openvswitch/actions.c OVS_SET_MASKED(nh->flow_lbl[2], (u8)fl, (u8)mask); mask 436 net/openvswitch/actions.c u8 mask) mask 438 net/openvswitch/actions.c new_ttl = OVS_MASKED(nh->ttl, new_ttl, mask); mask 446 net/openvswitch/actions.c const struct ovs_key_ipv4 *mask) mask 463 net/openvswitch/actions.c if (mask->ipv4_src) { mask 464 net/openvswitch/actions.c new_addr = OVS_MASKED(nh->saddr, key->ipv4_src, mask->ipv4_src); mask 471 net/openvswitch/actions.c if (mask->ipv4_dst) { mask 472 net/openvswitch/actions.c new_addr = OVS_MASKED(nh->daddr, key->ipv4_dst, mask->ipv4_dst); mask 479 net/openvswitch/actions.c if (mask->ipv4_tos) { mask 480 net/openvswitch/actions.c ipv4_change_dsfield(nh, ~mask->ipv4_tos, key->ipv4_tos); mask 483 net/openvswitch/actions.c if (mask->ipv4_ttl) { mask 484 net/openvswitch/actions.c set_ip_ttl(skb, nh, key->ipv4_ttl, mask->ipv4_ttl); mask 498 net/openvswitch/actions.c const struct ovs_key_ipv6 *mask) mask 514 net/openvswitch/actions.c if (is_ipv6_mask_nonzero(mask->ipv6_src)) { mask 518 net/openvswitch/actions.c mask_ipv6_addr(saddr, key->ipv6_src, mask->ipv6_src, masked); mask 527 net/openvswitch/actions.c if (is_ipv6_mask_nonzero(mask->ipv6_dst)) { mask 534 net/openvswitch/actions.c mask_ipv6_addr(daddr, key->ipv6_dst, mask->ipv6_dst, masked); mask 549 net/openvswitch/actions.c if (mask->ipv6_tclass) { mask 550 net/openvswitch/actions.c ipv6_change_dsfield(nh, ~mask->ipv6_tclass, key->ipv6_tclass); mask 553 net/openvswitch/actions.c if (mask->ipv6_label) { mask 555 net/openvswitch/actions.c ntohl(mask->ipv6_label)); mask 559 net/openvswitch/actions.c if (mask->ipv6_hlimit) { mask 561 net/openvswitch/actions.c mask->ipv6_hlimit); mask 578 net/openvswitch/actions.c struct ovs_key_nsh mask; mask 580 net/openvswitch/actions.c err = nsh_key_from_nlattr(a, &key, &mask); mask 600 net/openvswitch/actions.c flags = OVS_MASKED(flags, key.base.flags, mask.base.flags); mask 603 net/openvswitch/actions.c ttl = OVS_MASKED(ttl, key.base.ttl, mask.base.ttl); mask 607 net/openvswitch/actions.c mask.base.path_hdr); mask 614 net/openvswitch/actions.c mask.context[i]); mask 640 net/openvswitch/actions.c const struct ovs_key_udp *mask) mask 653 net/openvswitch/actions.c src = OVS_MASKED(uh->source, key->udp_src, mask->udp_src); mask 654 net/openvswitch/actions.c dst = OVS_MASKED(uh->dest, key->udp_dst, mask->udp_dst); mask 682 net/openvswitch/actions.c const struct ovs_key_tcp *mask) mask 694 net/openvswitch/actions.c src = OVS_MASKED(th->source, key->tcp_src, mask->tcp_src); mask 699 net/openvswitch/actions.c dst = OVS_MASKED(th->dest, key->tcp_dst, mask->tcp_dst); mask 711 net/openvswitch/actions.c const struct ovs_key_sctp *mask) mask 726 net/openvswitch/actions.c sh->source = OVS_MASKED(sh->source, key->sctp_src, mask->sctp_src); mask 727 net/openvswitch/actions.c sh->dest = OVS_MASKED(sh->dest, key->sctp_dst, mask->sctp_dst); mask 41 net/openvswitch/conntrack.c u32 mask; mask 47 net/openvswitch/conntrack.c struct ovs_key_ct_labels mask; mask 332 net/openvswitch/conntrack.c u32 ct_mark, u32 mask) mask 337 net/openvswitch/conntrack.c new_mark = ct_mark | (ct->mark & ~(mask)); mask 370 net/openvswitch/conntrack.c const struct ovs_key_ct_labels *mask) mask 373 net/openvswitch/conntrack.c bool have_mask = labels_nonzero(mask); mask 394 net/openvswitch/conntrack.c dst[i] = (dst[i] & ~mask->ct_labels_32[i]) | mask 396 net/openvswitch/conntrack.c & mask->ct_labels_32[i]); mask 411 net/openvswitch/conntrack.c const struct ovs_key_ct_labels *mask) mask 421 net/openvswitch/conntrack.c mask->ct_labels_32, mask 1218 net/openvswitch/conntrack.c if (info->mark.mask) { mask 1220 net/openvswitch/conntrack.c info->mark.mask); mask 1226 net/openvswitch/conntrack.c &info->labels.mask); mask 1230 net/openvswitch/conntrack.c labels_nonzero(&info->labels.mask)) { mask 1232 net/openvswitch/conntrack.c &info->labels.mask); mask 1549 net/openvswitch/conntrack.c if (!mark->mask) { mask 1561 net/openvswitch/conntrack.c if (!labels_nonzero(&labels->mask)) { mask 1607 net/openvswitch/conntrack.c if (!info->commit && info->mark.mask) { mask 1614 net/openvswitch/conntrack.c if (!info->commit && labels_nonzero(&info->labels.mask)) { mask 1794 net/openvswitch/conntrack.c if (IS_ENABLED(CONFIG_NF_CONNTRACK_MARK) && ct_info->mark.mask && mask 1799 net/openvswitch/conntrack.c labels_nonzero(&ct_info->labels.mask) && mask 902 net/openvswitch/datapath.c struct sw_flow_mask mask; mask 932 net/openvswitch/datapath.c ovs_match_init(&match, &new_flow->key, false, &mask); mask 948 net/openvswitch/datapath.c ovs_flow_mask_key(&new_flow->key, &new_flow->key, true, &mask); mask 981 net/openvswitch/datapath.c error = ovs_flow_tbl_insert(&dp->table, new_flow, &mask); mask 1063 net/openvswitch/datapath.c const struct sw_flow_mask *mask, mask 1070 net/openvswitch/datapath.c ovs_flow_mask_key(&masked_key, key, true, mask); mask 1102 net/openvswitch/datapath.c struct sw_flow_mask mask; mask 1106 net/openvswitch/datapath.c ovs_match_init(match, key, true, &mask); mask 1122 net/openvswitch/datapath.c &mask, log); mask 1131 net/openvswitch/datapath.c match->mask = NULL; mask 177 net/openvswitch/flow.h struct sw_flow_mask *mask; mask 217 net/openvswitch/flow.h struct sw_flow_mask *mask; mask 99 net/openvswitch/flow_netlink.c range = &match->mask->range; mask 119 net/openvswitch/flow_netlink.c (match)->mask->key.field = value; \ mask 128 net/openvswitch/flow_netlink.c memcpy((u8 *)&(match)->mask->key + offset, value_p, \ mask 143 net/openvswitch/flow_netlink.c memset((u8 *)&(match)->mask->key.field, value, \ mask 144 net/openvswitch/flow_netlink.c sizeof((match)->mask->key.field)); \ mask 182 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.eth.type == htons(0xffff))) mask 188 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.eth.type == htons(0xffff))) mask 194 net/openvswitch/flow_netlink.c if (match->mask && match->mask->key.eth.type == htons(0xffff)) { mask 202 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 208 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 215 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) { mask 223 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 231 net/openvswitch/flow_netlink.c if (match->mask && match->mask->key.eth.type == htons(0xffff)) { mask 239 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 245 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 252 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) { mask 260 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.ip.proto == 0xff)) mask 273 net/openvswitch/flow_netlink.c if (match->mask && (match->mask->key.tp.src == htons(0xff))) mask 282 net/openvswitch/flow_netlink.c if (match->mask && mask 283 net/openvswitch/flow_netlink.c match->mask->key.eth.type == htons(0xffff)) { mask 1781 net/openvswitch/flow_netlink.c if (match->mask) { mask 2249 net/openvswitch/flow_netlink.c return ovs_nla_put_key(&flow->key, &flow->mask->key, mask 2513 net/openvswitch/flow_netlink.c struct sw_flow_mask *mask) mask 2517 net/openvswitch/flow_netlink.c match->mask = mask; mask 2522 net/openvswitch/flow_netlink.c if (mask) { mask 2523 net/openvswitch/flow_netlink.c memset(&mask->key, 0, sizeof(mask->key)); mask 2524 net/openvswitch/flow_netlink.c mask->range.start = mask->range.end = 0; mask 2655 net/openvswitch/flow_netlink.c u8 *mask = data + len; mask 2658 net/openvswitch/flow_netlink.c if (*data++ & ~*mask++) mask 2721 net/openvswitch/flow_netlink.c const struct ovs_key_ipv4 *mask = ipv4_key + 1; mask 2724 net/openvswitch/flow_netlink.c if (mask->ipv4_proto || mask->ipv4_frag) mask 2742 net/openvswitch/flow_netlink.c const struct ovs_key_ipv6 *mask = ipv6_key + 1; mask 2745 net/openvswitch/flow_netlink.c if (mask->ipv6_proto || mask->ipv6_frag) mask 2749 net/openvswitch/flow_netlink.c if (ntohl(mask->ipv6_label) & 0xFFF00000) mask 2824 net/openvswitch/flow_netlink.c struct ovs_key_ipv6 *mask = nla_data(at) + key_len; mask 2826 net/openvswitch/flow_netlink.c mask->ipv6_label &= htonl(0x000FFFFF); mask 31 net/openvswitch/flow_netlink.h struct sw_flow_mask *mask); mask 46 net/openvswitch/flow_netlink.h const struct nlattr *key, const struct nlattr *mask, mask 48 net/openvswitch/flow_table.c bool full, const struct sw_flow_mask *mask) mask 50 net/openvswitch/flow_table.c int start = full ? 0 : mask->range.start; mask 51 net/openvswitch/flow_table.c int len = full ? sizeof *dst : range_n_bytes(&mask->range); mask 52 net/openvswitch/flow_table.c const long *m = (const long *)((const u8 *)&mask->key + start); mask 428 net/openvswitch/flow_table.c const struct sw_flow_mask *mask) mask 435 net/openvswitch/flow_table.c ovs_flow_mask_key(&masked_key, unmasked, false, mask); mask 436 net/openvswitch/flow_table.c hash = flow_hash(&masked_key, &mask->range); mask 439 net/openvswitch/flow_table.c if (flow->mask == mask && flow->flow_table.hash == hash && mask 440 net/openvswitch/flow_table.c flow_cmp_masked_key(flow, &masked_key, &mask->range)) mask 451 net/openvswitch/flow_table.c struct sw_flow_mask *mask; mask 455 net/openvswitch/flow_table.c list_for_each_entry_rcu(mask, &tbl->mask_list, list) { mask 457 net/openvswitch/flow_table.c flow = masked_flow_lookup(ti, key, mask); mask 476 net/openvswitch/flow_table.c struct sw_flow_mask *mask; mask 480 net/openvswitch/flow_table.c list_for_each_entry(mask, &tbl->mask_list, list) { mask 481 net/openvswitch/flow_table.c flow = masked_flow_lookup(ti, match->key, mask); mask 531 net/openvswitch/flow_table.c struct sw_flow_mask *mask; mask 534 net/openvswitch/flow_table.c list_for_each_entry(mask, &table->mask_list, list) mask 547 net/openvswitch/flow_table.c static void flow_mask_remove(struct flow_table *tbl, struct sw_flow_mask *mask) mask 549 net/openvswitch/flow_table.c if (mask) { mask 554 net/openvswitch/flow_table.c BUG_ON(!mask->ref_count); mask 555 net/openvswitch/flow_table.c mask->ref_count--; mask 557 net/openvswitch/flow_table.c if (!mask->ref_count) { mask 558 net/openvswitch/flow_table.c list_del_rcu(&mask->list); mask 559 net/openvswitch/flow_table.c kfree_rcu(mask, rcu); mask 581 net/openvswitch/flow_table.c flow_mask_remove(table, flow->mask); mask 586 net/openvswitch/flow_table.c struct sw_flow_mask *mask; mask 588 net/openvswitch/flow_table.c mask = kmalloc(sizeof(*mask), GFP_KERNEL); mask 589 net/openvswitch/flow_table.c if (mask) mask 590 net/openvswitch/flow_table.c mask->ref_count = 1; mask 592 net/openvswitch/flow_table.c return mask; mask 607 net/openvswitch/flow_table.c const struct sw_flow_mask *mask) mask 614 net/openvswitch/flow_table.c if (mask_equal(mask, m)) mask 625 net/openvswitch/flow_table.c struct sw_flow_mask *mask; mask 626 net/openvswitch/flow_table.c mask = flow_mask_find(tbl, new); mask 627 net/openvswitch/flow_table.c if (!mask) { mask 629 net/openvswitch/flow_table.c mask = mask_alloc(); mask 630 net/openvswitch/flow_table.c if (!mask) mask 632 net/openvswitch/flow_table.c mask->key = new->key; mask 633 net/openvswitch/flow_table.c mask->range = new->range; mask 634 net/openvswitch/flow_table.c list_add_rcu(&mask->list, &tbl->mask_list); mask 636 net/openvswitch/flow_table.c BUG_ON(!mask->ref_count); mask 637 net/openvswitch/flow_table.c mask->ref_count++; mask 640 net/openvswitch/flow_table.c flow->mask = mask; mask 650 net/openvswitch/flow_table.c flow->flow_table.hash = flow_hash(&flow->key, &flow->mask->range); mask 692 net/openvswitch/flow_table.c const struct sw_flow_mask *mask) mask 696 net/openvswitch/flow_table.c err = flow_mask_insert(table, flow, mask); mask 57 net/openvswitch/flow_table.h const struct sw_flow_mask *mask); mask 75 net/openvswitch/flow_table.h bool full, const struct sw_flow_mask *mask); mask 4168 net/packet/af_packet.c __poll_t mask = datagram_poll(file, sock, wait); mask 4174 net/packet/af_packet.c mask |= EPOLLIN | EPOLLRDNORM; mask 4181 net/packet/af_packet.c mask |= EPOLLOUT | EPOLLWRNORM; mask 4184 net/packet/af_packet.c return mask; mask 335 net/phonet/socket.c __poll_t mask = 0; mask 342 net/phonet/socket.c mask |= EPOLLIN | EPOLLRDNORM; mask 344 net/phonet/socket.c mask |= EPOLLPRI; mask 345 net/phonet/socket.c if (!mask && sk->sk_state == TCP_CLOSE_WAIT) mask 351 net/phonet/socket.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 353 net/phonet/socket.c return mask; mask 101 net/qrtr/tun.c __poll_t mask = 0; mask 106 net/qrtr/tun.c mask |= EPOLLIN | EPOLLRDNORM; mask 108 net/qrtr/tun.c return mask; mask 217 net/rds/af_rds.c __poll_t mask = 0; mask 231 net/rds/af_rds.c mask |= (EPOLLIN | EPOLLRDNORM | EPOLLWRBAND); mask 235 net/rds/af_rds.c mask |= (EPOLLIN | EPOLLRDNORM); mask 241 net/rds/af_rds.c mask |= (EPOLLIN | EPOLLRDNORM); mask 243 net/rds/af_rds.c mask |= (EPOLLOUT | EPOLLWRNORM); mask 245 net/rds/af_rds.c mask |= POLLERR; mask 249 net/rds/af_rds.c if (mask) mask 252 net/rds/af_rds.c return mask; mask 637 net/rds/ib_cm.c __be16 mask; mask 661 net/rds/ib_cm.c mask = dp->ricp_v6.dp_protocol_minor_mask; mask 666 net/rds/ib_cm.c mask = dp->ricp_v4.dp_protocol_minor_mask; mask 673 net/rds/ib_cm.c common = be16_to_cpu(mask) & RDS_IB_SUPPORTED_PROTOCOLS; mask 104 net/rose/af_rose.c int rosecmpm(rose_address *addr1, rose_address *addr2, unsigned short mask) mask 108 net/rose/af_rose.c if (mask > 10) mask 111 net/rose/af_rose.c for (i = 0; i < mask; i++) { mask 63 net/rose/rose_route.c if ((rose_node->mask == rose_route->mask) && mask 65 net/rose/rose_route.c rose_route->mask) == 0)) mask 142 net/rose/rose_route.c if (rose_tmpn->mask > rose_route->mask) { mask 158 net/rose/rose_route.c rose_node->mask = rose_route->mask; mask 304 net/rose/rose_route.c if ((rose_node->mask == rose_route->mask) && mask 306 net/rose/rose_route.c rose_route->mask) == 0)) mask 412 net/rose/rose_route.c if ((rose_node->mask == 10) && mask 428 net/rose/rose_route.c rose_node->mask = 10; mask 456 net/rose/rose_route.c if ((rose_node->mask == 10) && mask 684 net/rose/rose_route.c if (rosecmpm(addr, &node->address, node->mask) == 0) { mask 695 net/rose/rose_route.c if (rosecmpm(addr, &node->address, node->mask) == 0) { mask 738 net/rose/rose_route.c if (rose_route.mask > 10) /* Mask can't be more than 10 digits */ mask 1135 net/rose/rose_route.c rose_node->mask, mask 709 net/rxrpc/af_rxrpc.c __poll_t mask; mask 712 net/rxrpc/af_rxrpc.c mask = 0; mask 717 net/rxrpc/af_rxrpc.c mask |= EPOLLIN | EPOLLRDNORM; mask 723 net/rxrpc/af_rxrpc.c mask |= EPOLLOUT | EPOLLWRNORM; mask 725 net/rxrpc/af_rxrpc.c return mask; mask 601 net/rxrpc/conn_client.c u8 avail, mask; mask 605 net/rxrpc/conn_client.c mask = RXRPC_ACTIVE_CHANS_MASK; mask 608 net/rxrpc/conn_client.c mask = 0x01; mask 616 net/rxrpc/conn_client.c avail &= mask, mask 307 net/rxrpc/peer_event.c const u8 mask = ARRAY_SIZE(rxnet->peer_keepalive) - 1; mask 340 net/rxrpc/peer_event.c slot &= mask; mask 343 net/rxrpc/peer_event.c &rxnet->peer_keepalive[slot & mask]); mask 359 net/rxrpc/peer_event.c const u8 mask = ARRAY_SIZE(rxnet->peer_keepalive) - 1; mask 384 net/rxrpc/peer_event.c list_splice_tail_init(&rxnet->peer_keepalive[cursor & mask], mask 402 net/rxrpc/peer_event.c if (!list_empty(&rxnet->peer_keepalive[cursor & mask])) mask 293 net/sched/act_ct.c static void tcf_ct_act_set_mark(struct nf_conn *ct, u32 mark, u32 mask) mask 298 net/sched/act_ct.c if (!mask) mask 301 net/sched/act_ct.c new_mark = mark | (ct->mark & ~(mask)); mask 571 net/sched/act_ct.c void *mask, int mask_type, mask 578 net/sched/act_ct.c if (!mask) mask 582 net/sched/act_ct.c memset(mask, 0xff, len); mask 584 net/sched/act_ct.c nla_memcpy(mask, tb[mask_type], len); mask 768 net/sched/act_ct.c void *mask, int mask_type, mask 773 net/sched/act_ct.c if (mask && !memchr_inv(mask, 0, len)) mask 781 net/sched/act_ct.c err = nla_put(skb, mask_type, len, mask); mask 88 net/sched/act_nat.c p->mask = parm->mask; mask 112 net/sched/act_nat.c __be32 mask; mask 124 net/sched/act_nat.c mask = p->mask; mask 146 net/sched/act_nat.c if (!((old_addr ^ addr) & mask)) { mask 150 net/sched/act_nat.c new_addr &= mask; mask 151 net/sched/act_nat.c new_addr |= addr & ~mask; mask 225 net/sched/act_nat.c if ((old_addr ^ addr) & mask) mask 235 net/sched/act_nat.c new_addr &= mask; mask 236 net/sched/act_nat.c new_addr |= addr & ~mask; mask 277 net/sched/act_nat.c opt.mask = p->mask; mask 385 net/sched/act_pedit.c val = (*ptr + tkey->val) & ~tkey->mask; mask 393 net/sched/act_pedit.c *ptr = ((*ptr & tkey->mask) ^ val); mask 64 net/sched/act_skbedit.c skb->mark &= ~params->mask; mask 65 net/sched/act_skbedit.c skb->mark |= params->mark & params->mask; mask 98 net/sched/act_skbedit.c u32 flags = 0, *priority = NULL, *mark = NULL, *mask = NULL; mask 139 net/sched/act_skbedit.c mask = nla_data(tb[TCA_SKBEDIT_MASK]); mask 203 net/sched/act_skbedit.c params_new->mask = 0xffffffff; mask 205 net/sched/act_skbedit.c params_new->mask = *mask; mask 262 net/sched/act_skbedit.c nla_put_u32(skb, TCA_SKBEDIT_MASK, params->mask)) mask 3515 net/sched/cls_api.c entry->mangle.mask = tcf_pedit_mask(act, k); mask 49 net/sched/cls_flow.c u32 mask; mask 326 net/sched/cls_flow.c classid = (classid & f->mask) ^ f->xor; mask 462 net/sched/cls_flow.c fnew->mask = fold->mask; mask 511 net/sched/cls_flow.c fnew->mask = ~0U; mask 528 net/sched/cls_flow.c fnew->mask = nla_get_u32(tb[TCA_FLOW_MASK]); mask 637 net/sched/cls_flow.c if (f->mask != ~0 || f->xor != 0) { mask 638 net/sched/cls_flow.c if (nla_put_u32(skb, TCA_FLOW_MASK, f->mask) || mask 88 net/sched/cls_flower.c struct fl_flow_key mask; mask 103 net/sched/cls_flower.c struct fl_flow_mask *mask; mask 131 net/sched/cls_flower.c static unsigned short int fl_mask_range(const struct fl_flow_mask *mask) mask 133 net/sched/cls_flower.c return mask->range.end - mask->range.start; mask 136 net/sched/cls_flower.c static void fl_mask_update_range(struct fl_flow_mask *mask) mask 138 net/sched/cls_flower.c const u8 *bytes = (const u8 *) &mask->key; mask 139 net/sched/cls_flower.c size_t size = sizeof(mask->key); mask 155 net/sched/cls_flower.c mask->range.start = rounddown(first, sizeof(long)); mask 156 net/sched/cls_flower.c mask->range.end = roundup(last + 1, sizeof(long)); mask 160 net/sched/cls_flower.c const struct fl_flow_mask *mask) mask 162 net/sched/cls_flower.c return (u8 *) key + mask->range.start; mask 166 net/sched/cls_flower.c struct fl_flow_mask *mask) mask 168 net/sched/cls_flower.c const long *lkey = fl_key_get_start(key, mask); mask 169 net/sched/cls_flower.c const long *lmask = fl_key_get_start(&mask->key, mask); mask 170 net/sched/cls_flower.c long *lmkey = fl_key_get_start(mkey, mask); mask 173 net/sched/cls_flower.c for (i = 0; i < fl_mask_range(mask); i += sizeof(long)) mask 178 net/sched/cls_flower.c struct fl_flow_mask *mask) mask 180 net/sched/cls_flower.c const long *lmask = fl_key_get_start(&mask->key, mask); mask 186 net/sched/cls_flower.c ltmplt = fl_key_get_start(&tmplt->mask, mask); mask 187 net/sched/cls_flower.c for (i = 0; i < fl_mask_range(mask); i += sizeof(long)) { mask 195 net/sched/cls_flower.c struct fl_flow_mask *mask) mask 197 net/sched/cls_flower.c memset(fl_key_get_start(key, mask), 0, fl_mask_range(mask)); mask 206 net/sched/cls_flower.c min_mask = htons(filter->mask->key.tp_range.tp_min.dst); mask 207 net/sched/cls_flower.c max_mask = htons(filter->mask->key.tp_range.tp_max.dst); mask 229 net/sched/cls_flower.c min_mask = htons(filter->mask->key.tp_range.tp_min.src); mask 230 net/sched/cls_flower.c max_mask = htons(filter->mask->key.tp_range.tp_max.src); mask 246 net/sched/cls_flower.c static struct cls_fl_filter *__fl_lookup(struct fl_flow_mask *mask, mask 249 net/sched/cls_flower.c return rhashtable_lookup_fast(&mask->ht, fl_key_get_start(mkey, mask), mask 250 net/sched/cls_flower.c mask->filter_ht_params); mask 253 net/sched/cls_flower.c static struct cls_fl_filter *fl_lookup_range(struct fl_flow_mask *mask, mask 259 net/sched/cls_flower.c list_for_each_entry_rcu(filter, &mask->filters, list) { mask 266 net/sched/cls_flower.c f = __fl_lookup(mask, mkey); mask 273 net/sched/cls_flower.c static struct cls_fl_filter *fl_lookup(struct fl_flow_mask *mask, mask 277 net/sched/cls_flower.c if ((mask->flags & TCA_FLOWER_MASK_FLAGS_RANGE)) mask 278 net/sched/cls_flower.c return fl_lookup_range(mask, mkey, key); mask 280 net/sched/cls_flower.c return __fl_lookup(mask, mkey); mask 302 net/sched/cls_flower.c struct fl_flow_mask *mask; mask 305 net/sched/cls_flower.c list_for_each_entry_rcu(mask, &head->masks, list) { mask 307 net/sched/cls_flower.c fl_clear_masked_range(&skb_key, mask); mask 309 net/sched/cls_flower.c skb_flow_dissect_meta(skb, &mask->dissector, &skb_key); mask 314 net/sched/cls_flower.c skb_flow_dissect_tunnel_info(skb, &mask->dissector, &skb_key); mask 315 net/sched/cls_flower.c skb_flow_dissect_ct(skb, &mask->dissector, &skb_key, mask 318 net/sched/cls_flower.c skb_flow_dissect(skb, &mask->dissector, &skb_key, 0); mask 320 net/sched/cls_flower.c fl_set_masked_key(&skb_mkey, &skb_key, mask); mask 322 net/sched/cls_flower.c f = fl_lookup(mask, &skb_mkey, &skb_key); mask 348 net/sched/cls_flower.c static void fl_mask_free(struct fl_flow_mask *mask, bool mask_init_done) mask 352 net/sched/cls_flower.c WARN_ON(!list_empty(&mask->filters)); mask 353 net/sched/cls_flower.c rhashtable_destroy(&mask->ht); mask 355 net/sched/cls_flower.c kfree(mask); mask 360 net/sched/cls_flower.c struct fl_flow_mask *mask = container_of(to_rcu_work(work), mask 363 net/sched/cls_flower.c fl_mask_free(mask, true); mask 368 net/sched/cls_flower.c struct fl_flow_mask *mask = container_of(to_rcu_work(work), mask 371 net/sched/cls_flower.c fl_mask_free(mask, false); mask 374 net/sched/cls_flower.c static bool fl_mask_put(struct cls_fl_head *head, struct fl_flow_mask *mask) mask 376 net/sched/cls_flower.c if (!refcount_dec_and_test(&mask->refcnt)) mask 379 net/sched/cls_flower.c rhashtable_remove_fast(&head->ht, &mask->ht_node, mask_ht_params); mask 382 net/sched/cls_flower.c list_del_rcu(&mask->list); mask 385 net/sched/cls_flower.c tcf_queue_work(&mask->rwork, fl_mask_free_work); mask 446 net/sched/cls_flower.c cls_flower.rule->match.dissector = &f->mask->dissector; mask 447 net/sched/cls_flower.c cls_flower.rule->match.mask = &f->mask->key; mask 536 net/sched/cls_flower.c rhashtable_remove_fast(&f->mask->ht, &f->ht_node, mask 537 net/sched/cls_flower.c f->mask->filter_ht_params); mask 542 net/sched/cls_flower.c *last = fl_mask_put(head, f->mask); mask 566 net/sched/cls_flower.c struct fl_flow_mask *mask, *next_mask; mask 570 net/sched/cls_flower.c list_for_each_entry_safe(mask, next_mask, &head->masks, list) { mask 571 net/sched/cls_flower.c list_for_each_entry_safe(f, next, &mask->filters, list) { mask 711 net/sched/cls_flower.c void *mask, int mask_type, int len) mask 717 net/sched/cls_flower.c memset(mask, 0xff, len); mask 719 net/sched/cls_flower.c nla_memcpy(mask, tb[mask_type], len); mask 723 net/sched/cls_flower.c struct fl_flow_key *mask) mask 726 net/sched/cls_flower.c TCA_FLOWER_KEY_PORT_DST_MIN, &mask->tp_range.tp_min.dst, mask 729 net/sched/cls_flower.c TCA_FLOWER_KEY_PORT_DST_MAX, &mask->tp_range.tp_max.dst, mask 732 net/sched/cls_flower.c TCA_FLOWER_KEY_PORT_SRC_MIN, &mask->tp_range.tp_min.src, mask 735 net/sched/cls_flower.c TCA_FLOWER_KEY_PORT_SRC_MAX, &mask->tp_range.tp_max.src, mask 738 net/sched/cls_flower.c if ((mask->tp_range.tp_min.dst && mask->tp_range.tp_max.dst && mask 741 net/sched/cls_flower.c (mask->tp_range.tp_min.src && mask->tp_range.tp_max.src && mask 821 net/sched/cls_flower.c u32 key, mask; mask 828 net/sched/cls_flower.c mask = be32_to_cpu(nla_get_u32(tb[TCA_FLOWER_KEY_FLAGS_MASK])); mask 833 net/sched/cls_flower.c fl_set_key_flag(key, mask, flags_key, flags_mask, mask 835 net/sched/cls_flower.c fl_set_key_flag(key, mask, flags_key, flags_mask, mask 844 net/sched/cls_flower.c struct flow_dissector_key_ip *mask) mask 851 net/sched/cls_flower.c fl_set_key_val(tb, &key->tos, tos_key, &mask->tos, tos_mask, sizeof(key->tos)); mask 852 net/sched/cls_flower.c fl_set_key_val(tb, &key->ttl, ttl_key, &mask->ttl, ttl_mask, sizeof(key->ttl)); mask 941 net/sched/cls_flower.c struct fl_flow_key *mask, mask 982 net/sched/cls_flower.c mask->enc_opts.dst_opt_type = TUNNEL_GENEVE_OPT; mask 983 net/sched/cls_flower.c option_len = fl_set_geneve_opt(nla_opt_msk, mask, mask 989 net/sched/cls_flower.c mask->enc_opts.len += option_len; mask 990 net/sched/cls_flower.c if (key->enc_opts.len != mask->enc_opts.len) { mask 1009 net/sched/cls_flower.c struct flow_dissector_key_ct *mask, mask 1018 net/sched/cls_flower.c &mask->ct_state, TCA_FLOWER_KEY_CT_STATE_MASK, mask 1027 net/sched/cls_flower.c &mask->ct_zone, TCA_FLOWER_KEY_CT_ZONE_MASK, mask 1036 net/sched/cls_flower.c &mask->ct_mark, TCA_FLOWER_KEY_CT_MARK_MASK, mask 1045 net/sched/cls_flower.c mask->ct_labels, TCA_FLOWER_KEY_CT_LABELS_MASK, mask 1053 net/sched/cls_flower.c struct fl_flow_key *key, struct fl_flow_key *mask, mask 1064 net/sched/cls_flower.c mask->meta.ingress_ifindex = 0xffffffff; mask 1068 net/sched/cls_flower.c mask->eth.dst, TCA_FLOWER_KEY_ETH_DST_MASK, mask 1071 net/sched/cls_flower.c mask->eth.src, TCA_FLOWER_KEY_ETH_SRC_MASK, mask 1080 net/sched/cls_flower.c &mask->vlan); mask 1088 net/sched/cls_flower.c &key->cvlan, &mask->cvlan); mask 1091 net/sched/cls_flower.c &mask->basic.n_proto, mask 1096 net/sched/cls_flower.c mask->basic.n_proto = cpu_to_be16(~0); mask 1101 net/sched/cls_flower.c mask->basic.n_proto = cpu_to_be16(~0); mask 1108 net/sched/cls_flower.c &mask->basic.ip_proto, TCA_FLOWER_UNSPEC, mask 1110 net/sched/cls_flower.c fl_set_key_ip(tb, false, &key->ip, &mask->ip); mask 1115 net/sched/cls_flower.c mask->control.addr_type = ~0; mask 1117 net/sched/cls_flower.c &mask->ipv4.src, TCA_FLOWER_KEY_IPV4_SRC_MASK, mask 1120 net/sched/cls_flower.c &mask->ipv4.dst, TCA_FLOWER_KEY_IPV4_DST_MASK, mask 1124 net/sched/cls_flower.c mask->control.addr_type = ~0; mask 1126 net/sched/cls_flower.c &mask->ipv6.src, TCA_FLOWER_KEY_IPV6_SRC_MASK, mask 1129 net/sched/cls_flower.c &mask->ipv6.dst, TCA_FLOWER_KEY_IPV6_DST_MASK, mask 1135 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_TCP_SRC_MASK, mask 1138 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_TCP_DST_MASK, mask 1141 net/sched/cls_flower.c &mask->tcp.flags, TCA_FLOWER_KEY_TCP_FLAGS_MASK, mask 1145 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_UDP_SRC_MASK, mask 1148 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_UDP_DST_MASK, mask 1152 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_SCTP_SRC_MASK, mask 1155 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_SCTP_DST_MASK, mask 1160 net/sched/cls_flower.c &mask->icmp.type, mask 1164 net/sched/cls_flower.c &mask->icmp.code, mask 1170 net/sched/cls_flower.c &mask->icmp.type, mask 1174 net/sched/cls_flower.c &mask->icmp.code, mask 1179 net/sched/cls_flower.c ret = fl_set_key_mpls(tb, &key->mpls, &mask->mpls); mask 1185 net/sched/cls_flower.c &mask->arp.sip, TCA_FLOWER_KEY_ARP_SIP_MASK, mask 1188 net/sched/cls_flower.c &mask->arp.tip, TCA_FLOWER_KEY_ARP_TIP_MASK, mask 1191 net/sched/cls_flower.c &mask->arp.op, TCA_FLOWER_KEY_ARP_OP_MASK, mask 1194 net/sched/cls_flower.c mask->arp.sha, TCA_FLOWER_KEY_ARP_SHA_MASK, mask 1197 net/sched/cls_flower.c mask->arp.tha, TCA_FLOWER_KEY_ARP_THA_MASK, mask 1204 net/sched/cls_flower.c ret = fl_set_key_port_range(tb, key, mask); mask 1212 net/sched/cls_flower.c mask->enc_control.addr_type = ~0; mask 1215 net/sched/cls_flower.c &mask->enc_ipv4.src, mask 1220 net/sched/cls_flower.c &mask->enc_ipv4.dst, mask 1228 net/sched/cls_flower.c mask->enc_control.addr_type = ~0; mask 1231 net/sched/cls_flower.c &mask->enc_ipv6.src, mask 1236 net/sched/cls_flower.c &mask->enc_ipv6.dst, mask 1242 net/sched/cls_flower.c &mask->enc_key_id.keyid, TCA_FLOWER_UNSPEC, mask 1246 net/sched/cls_flower.c &mask->enc_tp.src, TCA_FLOWER_KEY_ENC_UDP_SRC_PORT_MASK, mask 1250 net/sched/cls_flower.c &mask->enc_tp.dst, TCA_FLOWER_KEY_ENC_UDP_DST_PORT_MASK, mask 1253 net/sched/cls_flower.c fl_set_key_ip(tb, true, &key->enc_ip, &mask->enc_ip); mask 1256 net/sched/cls_flower.c ret = fl_set_enc_opt(tb, key, mask, extack); mask 1261 net/sched/cls_flower.c ret = fl_set_key_ct(tb, &key->ct, &mask->ct, extack); mask 1266 net/sched/cls_flower.c ret = fl_set_key_flags(tb, &key->control.flags, &mask->control.flags); mask 1287 net/sched/cls_flower.c static int fl_init_mask_hashtable(struct fl_flow_mask *mask) mask 1289 net/sched/cls_flower.c mask->filter_ht_params = fl_ht_params; mask 1290 net/sched/cls_flower.c mask->filter_ht_params.key_len = fl_mask_range(mask); mask 1291 net/sched/cls_flower.c mask->filter_ht_params.key_offset += mask->range.start; mask 1293 net/sched/cls_flower.c return rhashtable_init(&mask->ht, &mask->filter_ht_params); mask 1299 net/sched/cls_flower.c #define FL_KEY_IS_MASKED(mask, member) \ mask 1300 net/sched/cls_flower.c memchr_inv(((char *)mask) + FL_KEY_MEMBER_OFFSET(member), \ mask 1310 net/sched/cls_flower.c #define FL_KEY_SET_IF_MASKED(mask, keys, cnt, id, member) \ mask 1312 net/sched/cls_flower.c if (FL_KEY_IS_MASKED(mask, member)) \ mask 1317 net/sched/cls_flower.c struct fl_flow_key *mask) mask 1322 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1326 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1328 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1330 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1332 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1334 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1336 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1338 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1340 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1342 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1344 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1346 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1348 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1350 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1352 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1354 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1356 net/sched/cls_flower.c if (FL_KEY_IS_MASKED(mask, enc_ipv4) || mask 1357 net/sched/cls_flower.c FL_KEY_IS_MASKED(mask, enc_ipv6)) mask 1360 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1362 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1364 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1366 net/sched/cls_flower.c FL_KEY_SET_IF_MASKED(mask, keys, cnt, mask 1373 net/sched/cls_flower.c struct fl_flow_mask *mask) mask 1382 net/sched/cls_flower.c fl_mask_copy(newmask, mask); mask 1399 net/sched/cls_flower.c err = rhashtable_replace_fast(&head->ht, &mask->ht_node, mask 1421 net/sched/cls_flower.c struct fl_flow_mask *mask) mask 1432 net/sched/cls_flower.c fnew->mask = rhashtable_lookup_get_insert_fast(&head->ht, mask 1433 net/sched/cls_flower.c &mask->ht_node, mask 1435 net/sched/cls_flower.c if (!fnew->mask) { mask 1443 net/sched/cls_flower.c newmask = fl_create_new_mask(head, mask); mask 1449 net/sched/cls_flower.c fnew->mask = newmask; mask 1451 net/sched/cls_flower.c } else if (IS_ERR(fnew->mask)) { mask 1452 net/sched/cls_flower.c ret = PTR_ERR(fnew->mask); mask 1453 net/sched/cls_flower.c } else if (fold && fold->mask != fnew->mask) { mask 1455 net/sched/cls_flower.c } else if (!refcount_inc_not_zero(&fnew->mask->refcnt)) { mask 1463 net/sched/cls_flower.c rhashtable_remove_fast(&head->ht, &mask->ht_node, mask 1469 net/sched/cls_flower.c struct cls_fl_filter *f, struct fl_flow_mask *mask, mask 1491 net/sched/cls_flower.c err = fl_set_key(net, tb, &f->key, &mask->key, extack); mask 1495 net/sched/cls_flower.c fl_mask_update_range(mask); mask 1496 net/sched/cls_flower.c fl_set_masked_key(&f->mkey, &f->key, mask); mask 1498 net/sched/cls_flower.c if (!fl_mask_fits_tmplt(tmplt, mask)) { mask 1510 net/sched/cls_flower.c struct fl_flow_mask *mask = fnew->mask; mask 1513 net/sched/cls_flower.c err = rhashtable_lookup_insert_fast(&mask->ht, mask 1515 net/sched/cls_flower.c mask->filter_ht_params); mask 1537 net/sched/cls_flower.c struct fl_flow_mask *mask; mask 1547 net/sched/cls_flower.c mask = kzalloc(sizeof(struct fl_flow_mask), GFP_KERNEL); mask 1548 net/sched/cls_flower.c if (!mask) { mask 1590 net/sched/cls_flower.c err = fl_set_parms(net, tp, fnew, mask, base, tb, tca[TCA_RATE], ovr, mask 1595 net/sched/cls_flower.c err = fl_check_assign_mask(head, fnew, fold, mask); mask 1633 net/sched/cls_flower.c fnew->mask->filter_ht_params; mask 1635 net/sched/cls_flower.c err = rhashtable_insert_fast(&fnew->mask->ht, mask 1644 net/sched/cls_flower.c rhashtable_remove_fast(&fold->mask->ht, mask 1646 net/sched/cls_flower.c fold->mask->filter_ht_params); mask 1653 net/sched/cls_flower.c fl_mask_put(head, fold->mask); mask 1686 net/sched/cls_flower.c list_add_tail_rcu(&fnew->list, &fnew->mask->filters); mask 1693 net/sched/cls_flower.c tcf_queue_work(&mask->rwork, fl_uninit_mask_free_work); mask 1704 net/sched/cls_flower.c rhashtable_remove_fast(&fnew->mask->ht, &fnew->ht_node, mask 1705 net/sched/cls_flower.c fnew->mask->filter_ht_params); mask 1707 net/sched/cls_flower.c fl_mask_put(head, fnew->mask); mask 1713 net/sched/cls_flower.c tcf_queue_work(&mask->rwork, fl_uninit_mask_free_work); mask 1811 net/sched/cls_flower.c cls_flower.rule->match.dissector = &f->mask->dissector; mask 1812 net/sched/cls_flower.c cls_flower.rule->match.mask = &f->mask->key; mask 1885 net/sched/cls_flower.c cls_flower.rule->match.mask = &tmplt->mask; mask 1935 net/sched/cls_flower.c err = fl_set_key(net, tb, &tmplt->dummy_key, &tmplt->mask, extack); mask 1939 net/sched/cls_flower.c fl_init_dissector(&tmplt->dissector, &tmplt->mask); mask 1965 net/sched/cls_flower.c void *mask, int mask_type, int len) mask 1969 net/sched/cls_flower.c if (!memchr_inv(mask, 0, len)) mask 1975 net/sched/cls_flower.c err = nla_put(skb, mask_type, len, mask); mask 1983 net/sched/cls_flower.c struct fl_flow_key *mask) mask 1987 net/sched/cls_flower.c &mask->tp_range.tp_min.dst, TCA_FLOWER_UNSPEC, mask 1991 net/sched/cls_flower.c &mask->tp_range.tp_max.dst, TCA_FLOWER_UNSPEC, mask 1995 net/sched/cls_flower.c &mask->tp_range.tp_min.src, TCA_FLOWER_UNSPEC, mask 1999 net/sched/cls_flower.c &mask->tp_range.tp_max.src, TCA_FLOWER_UNSPEC, mask 2043 net/sched/cls_flower.c struct flow_dissector_key_ip *mask) mask 2050 net/sched/cls_flower.c if (fl_dump_key_val(skb, &key->tos, tos_key, &mask->tos, tos_mask, sizeof(key->tos)) || mask 2051 net/sched/cls_flower.c fl_dump_key_val(skb, &key->ttl, ttl_key, &mask->ttl, ttl_mask, sizeof(key->ttl))) mask 2094 net/sched/cls_flower.c u32 key, mask; mask 2102 net/sched/cls_flower.c mask = 0; mask 2104 net/sched/cls_flower.c fl_get_key_flag(flags_key, flags_mask, &key, &mask, mask 2106 net/sched/cls_flower.c fl_get_key_flag(flags_key, flags_mask, &key, &mask, mask 2111 net/sched/cls_flower.c _mask = cpu_to_be32(mask); mask 2156 net/sched/cls_flower.c struct flow_dissector_key_ct *mask) mask 2160 net/sched/cls_flower.c &mask->ct_state, TCA_FLOWER_KEY_CT_STATE_MASK, mask 2166 net/sched/cls_flower.c &mask->ct_zone, TCA_FLOWER_KEY_CT_ZONE_MASK, mask 2172 net/sched/cls_flower.c &mask->ct_mark, TCA_FLOWER_KEY_CT_MARK_MASK, mask 2178 net/sched/cls_flower.c &mask->ct_labels, TCA_FLOWER_KEY_CT_LABELS_MASK, mask 2232 net/sched/cls_flower.c struct fl_flow_key *key, struct fl_flow_key *mask) mask 2234 net/sched/cls_flower.c if (mask->meta.ingress_ifindex) { mask 2243 net/sched/cls_flower.c mask->eth.dst, TCA_FLOWER_KEY_ETH_DST_MASK, mask 2246 net/sched/cls_flower.c mask->eth.src, TCA_FLOWER_KEY_ETH_SRC_MASK, mask 2249 net/sched/cls_flower.c &mask->basic.n_proto, TCA_FLOWER_UNSPEC, mask 2253 net/sched/cls_flower.c if (fl_dump_key_mpls(skb, &key->mpls, &mask->mpls)) mask 2257 net/sched/cls_flower.c TCA_FLOWER_KEY_VLAN_PRIO, &key->vlan, &mask->vlan)) mask 2262 net/sched/cls_flower.c &key->cvlan, &mask->cvlan) || mask 2263 net/sched/cls_flower.c (mask->cvlan.vlan_tpid && mask 2268 net/sched/cls_flower.c if (mask->basic.n_proto) { mask 2269 net/sched/cls_flower.c if (mask->cvlan.vlan_tpid) { mask 2273 net/sched/cls_flower.c } else if (mask->vlan.vlan_tpid) { mask 2283 net/sched/cls_flower.c &mask->basic.ip_proto, TCA_FLOWER_UNSPEC, mask 2285 net/sched/cls_flower.c fl_dump_key_ip(skb, false, &key->ip, &mask->ip))) mask 2290 net/sched/cls_flower.c &mask->ipv4.src, TCA_FLOWER_KEY_IPV4_SRC_MASK, mask 2293 net/sched/cls_flower.c &mask->ipv4.dst, TCA_FLOWER_KEY_IPV4_DST_MASK, mask 2298 net/sched/cls_flower.c &mask->ipv6.src, TCA_FLOWER_KEY_IPV6_SRC_MASK, mask 2301 net/sched/cls_flower.c &mask->ipv6.dst, TCA_FLOWER_KEY_IPV6_DST_MASK, mask 2307 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_TCP_SRC_MASK, mask 2310 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_TCP_DST_MASK, mask 2313 net/sched/cls_flower.c &mask->tcp.flags, TCA_FLOWER_KEY_TCP_FLAGS_MASK, mask 2318 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_UDP_SRC_MASK, mask 2321 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_UDP_DST_MASK, mask 2326 net/sched/cls_flower.c &mask->tp.src, TCA_FLOWER_KEY_SCTP_SRC_MASK, mask 2329 net/sched/cls_flower.c &mask->tp.dst, TCA_FLOWER_KEY_SCTP_DST_MASK, mask 2335 net/sched/cls_flower.c TCA_FLOWER_KEY_ICMPV4_TYPE, &mask->icmp.type, mask 2339 net/sched/cls_flower.c TCA_FLOWER_KEY_ICMPV4_CODE, &mask->icmp.code, mask 2346 net/sched/cls_flower.c TCA_FLOWER_KEY_ICMPV6_TYPE, &mask->icmp.type, mask 2350 net/sched/cls_flower.c TCA_FLOWER_KEY_ICMPV6_CODE, &mask->icmp.code, mask 2357 net/sched/cls_flower.c TCA_FLOWER_KEY_ARP_SIP, &mask->arp.sip, mask 2361 net/sched/cls_flower.c TCA_FLOWER_KEY_ARP_TIP, &mask->arp.tip, mask 2365 net/sched/cls_flower.c TCA_FLOWER_KEY_ARP_OP, &mask->arp.op, mask 2369 net/sched/cls_flower.c mask->arp.sha, TCA_FLOWER_KEY_ARP_SHA_MASK, mask 2372 net/sched/cls_flower.c mask->arp.tha, TCA_FLOWER_KEY_ARP_THA_MASK, mask 2379 net/sched/cls_flower.c fl_dump_key_port_range(skb, key, mask)) mask 2384 net/sched/cls_flower.c TCA_FLOWER_KEY_ENC_IPV4_SRC, &mask->enc_ipv4.src, mask 2388 net/sched/cls_flower.c TCA_FLOWER_KEY_ENC_IPV4_DST, &mask->enc_ipv4.dst, mask 2394 net/sched/cls_flower.c TCA_FLOWER_KEY_ENC_IPV6_SRC, &mask->enc_ipv6.src, mask 2399 net/sched/cls_flower.c &mask->enc_ipv6.dst, mask 2405 net/sched/cls_flower.c &mask->enc_key_id, TCA_FLOWER_UNSPEC, mask 2409 net/sched/cls_flower.c &mask->enc_tp.src, mask 2414 net/sched/cls_flower.c &mask->enc_tp.dst, mask 2417 net/sched/cls_flower.c fl_dump_key_ip(skb, true, &key->enc_ip, &mask->enc_ip) || mask 2418 net/sched/cls_flower.c fl_dump_key_enc_opt(skb, &key->enc_opts, &mask->enc_opts)) mask 2421 net/sched/cls_flower.c if (fl_dump_key_ct(skb, &key->ct, &mask->ct)) mask 2424 net/sched/cls_flower.c if (fl_dump_key_flags(skb, key->control.flags, mask->control.flags)) mask 2438 net/sched/cls_flower.c struct fl_flow_key *key, *mask; mask 2457 net/sched/cls_flower.c mask = &f->mask->key; mask 2460 net/sched/cls_flower.c if (fl_dump_key(skb, net, key, mask)) mask 2494 net/sched/cls_flower.c struct fl_flow_key *key, *mask; mask 2502 net/sched/cls_flower.c mask = &tmplt->mask; mask 2504 net/sched/cls_flower.c if (fl_dump_key(skb, net, key, mask)) mask 28 net/sched/cls_fw.c u32 mask; mask 59 net/sched/cls_fw.c id &= head->mask; mask 205 net/sched/cls_fw.c u32 mask; mask 228 net/sched/cls_fw.c mask = nla_get_u32(tb[TCA_FW_MASK]); mask 229 net/sched/cls_fw.c if (mask != head->mask) mask 231 net/sched/cls_fw.c } else if (head->mask != 0xFFFFFFFF) mask 307 net/sched/cls_fw.c u32 mask = 0xFFFFFFFF; mask 309 net/sched/cls_fw.c mask = nla_get_u32(tb[TCA_FW_MASK]); mask 314 net/sched/cls_fw.c head->mask = mask; mask 403 net/sched/cls_fw.c if (head->mask != 0xFFFFFFFF && mask 404 net/sched/cls_fw.c nla_put_u32(skb, TCA_FW_MASK, head->mask)) mask 174 net/sched/cls_rsvp.h !(s->dpi.mask & mask 186 net/sched/cls_rsvp.h !(f->spi.mask & (*(u32 *)(xprt + f->spi.offset) ^ f->spi.key)) mask 611 net/sched/cls_rsvp.h __u32 mask = nfp->spi.mask & f->spi.mask; mask 613 net/sched/cls_rsvp.h if (mask != f->spi.mask) mask 640 net/sched/cls_rsvp.h if ((nsp->dpi.mask & s->dpi.mask) != s->dpi.mask) mask 51 net/sched/cls_tcindex.c u16 mask; /* AND key with mask */ mask 107 net/sched/cls_tcindex.c int key = (skb->tc_index & p->mask) >> p->shift; mask 151 net/sched/cls_tcindex.c p->mask = 0xffff; mask 260 net/sched/cls_tcindex.c return p->hash > (p->mask >> p->shift); mask 355 net/sched/cls_tcindex.c cp->mask = p->mask; mask 367 net/sched/cls_tcindex.c cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]); mask 376 net/sched/cls_tcindex.c if ((cp->mask >> cp->shift) < PERFECT_HASH_THRESHOLD) mask 377 net/sched/cls_tcindex.c cp->hash = (cp->mask >> cp->shift) + 1; mask 648 net/sched/cls_tcindex.c nla_put_u16(skb, TCA_TCINDEX_MASK, p->mask) || mask 59 net/sched/cls_u32.c u32 mask; mask 140 net/sched/cls_u32.c if ((skb->mark & n->mask) != n->val) { mask 158 net/sched/cls_u32.c if ((*data ^ key->val) & key->mask) { mask 544 net/sched/cls_u32.c cls_u32.knode.mask = n->mask; mask 547 net/sched/cls_u32.c cls_u32.knode.mask = 0; mask 829 net/sched/cls_u32.c new->mask = n->mask; mask 1064 net/sched/cls_u32.c n->mask = mark->mask; mask 1190 net/sched/cls_u32.c cls_u32.knode.mask = n->mask; mask 1193 net/sched/cls_u32.c cls_u32.knode.mask = 0; mask 1323 net/sched/cls_u32.c if ((n->val || n->mask)) { mask 1325 net/sched/cls_u32.c .mask = n->mask, mask 57 net/sched/em_cmp.c if (cmp->mask) mask 58 net/sched/em_cmp.c val &= cmp->mask; mask 34 net/sched/em_u32.c return !(((*(__be32 *) ptr) ^ key->val) & key->mask); mask 947 net/sched/sch_cbq.c static void cbq_change_defmap(struct cbq_class *cl, u32 splitid, u32 def, u32 mask) mask 971 net/sched/sch_cbq.c cl->defmap = def & mask; mask 973 net/sched/sch_cbq.c cl->defmap = (cl->defmap & ~mask) | (def & mask); mask 352 net/sched/sch_choke.c unsigned int mask; mask 377 net/sched/sch_choke.c mask = roundup_pow_of_two(ctl->limit + 1) - 1; mask 378 net/sched/sch_choke.c if (mask != q->tab_mask) { mask 381 net/sched/sch_choke.c ntab = kvmalloc_array((mask + 1), sizeof(struct sk_buff *), GFP_KERNEL | __GFP_ZERO); mask 397 net/sched/sch_choke.c if (tail < mask) { mask 411 net/sched/sch_choke.c q->tab_mask = mask; mask 41 net/sched/sch_dsmark.c u8 mask; mask 145 net/sched/sch_dsmark.c p->mv[*arg - 1].mask = nla_get_u8(tb[TCA_DSMARK_MASK]); mask 160 net/sched/sch_dsmark.c p->mv[arg - 1].mask = 0xff; mask 178 net/sched/sch_dsmark.c if (p->mv[i].mask == 0xff && !p->mv[i].value) mask 308 net/sched/sch_dsmark.c ipv4_change_dsfield(ip_hdr(skb), p->mv[index].mask, mask 312 net/sched/sch_dsmark.c ipv6_change_dsfield(ipv6_hdr(skb), p->mv[index].mask, mask 321 net/sched/sch_dsmark.c if (p->mv[index].mask != 0xff || p->mv[index].value) mask 383 net/sched/sch_dsmark.c p->mv[i].mask = 0xff; mask 443 net/sched/sch_dsmark.c if (nla_put_u8(skb, TCA_DSMARK_MASK, p->mv[cl - 1].mask) || mask 344 net/sched/sch_htb.c struct htb_class *cl, int mask) mask 346 net/sched/sch_htb.c q->row_mask[cl->level] |= mask; mask 347 net/sched/sch_htb.c while (mask) { mask 348 net/sched/sch_htb.c int prio = ffz(~mask); mask 349 net/sched/sch_htb.c mask &= ~(1 << prio); mask 373 net/sched/sch_htb.c struct htb_class *cl, int mask) mask 378 net/sched/sch_htb.c while (mask) { mask 379 net/sched/sch_htb.c int prio = ffz(~mask); mask 382 net/sched/sch_htb.c mask &= ~(1 << prio); mask 403 net/sched/sch_htb.c long m, mask = cl->prio_activity; mask 405 net/sched/sch_htb.c while (cl->cmode == HTB_MAY_BORROW && p && mask) { mask 406 net/sched/sch_htb.c m = mask; mask 415 net/sched/sch_htb.c mask &= ~(1 << prio); mask 419 net/sched/sch_htb.c p->prio_activity |= mask; mask 424 net/sched/sch_htb.c if (cl->cmode == HTB_CAN_SEND && mask) mask 425 net/sched/sch_htb.c htb_add_class_to_row(q, cl, mask); mask 438 net/sched/sch_htb.c long m, mask = cl->prio_activity; mask 440 net/sched/sch_htb.c while (cl->cmode == HTB_MAY_BORROW && p && mask) { mask 441 net/sched/sch_htb.c m = mask; mask 442 net/sched/sch_htb.c mask = 0; mask 460 net/sched/sch_htb.c mask |= 1 << prio; mask 463 net/sched/sch_htb.c p->prio_activity &= ~mask; mask 468 net/sched/sch_htb.c if (cl->cmode == HTB_CAN_SEND && mask) mask 469 net/sched/sch_htb.c htb_remove_class_from_row(q, cl, mask); mask 750 net/sched/sch_qfq.c unsigned long mask = mask_from(q->bitmaps[ER], grp->index); mask 753 net/sched/sch_qfq.c if (mask) { mask 754 net/sched/sch_qfq.c next = qfq_ffs(q, mask); mask 769 net/sched/sch_qfq.c static inline void qfq_move_groups(struct qfq_sched *q, unsigned long mask, mask 772 net/sched/sch_qfq.c q->bitmaps[dst] |= q->bitmaps[src] & mask; mask 773 net/sched/sch_qfq.c q->bitmaps[src] &= ~mask; mask 778 net/sched/sch_qfq.c unsigned long mask = mask_from(q->bitmaps[ER], index + 1); mask 781 net/sched/sch_qfq.c if (mask) { mask 782 net/sched/sch_qfq.c next = qfq_ffs(q, mask); mask 787 net/sched/sch_qfq.c mask = (1UL << index) - 1; mask 788 net/sched/sch_qfq.c qfq_move_groups(q, mask, EB, ER); mask 789 net/sched/sch_qfq.c qfq_move_groups(q, mask, IB, IR); mask 808 net/sched/sch_qfq.c unsigned long mask; mask 812 net/sched/sch_qfq.c mask = ~0UL; /* make all groups eligible */ mask 814 net/sched/sch_qfq.c mask = (1UL << last_flip_pos) - 1; mask 816 net/sched/sch_qfq.c qfq_move_groups(q, mask, IR, ER); mask 817 net/sched/sch_qfq.c qfq_move_groups(q, mask, IB, EB); mask 1033 net/sched/sch_qfq.c unsigned long mask; mask 1042 net/sched/sch_qfq.c mask = mask_from(q->bitmaps[ER], agg->grp->index); mask 1043 net/sched/sch_qfq.c if (mask) { mask 1044 net/sched/sch_qfq.c struct qfq_group *next = qfq_ffs(q, mask); mask 1357 net/sched/sch_qfq.c unsigned long mask; mask 1377 net/sched/sch_qfq.c mask = q->bitmaps[ER] & ((1UL << grp->index) - 1); mask 1378 net/sched/sch_qfq.c if (mask) mask 1379 net/sched/sch_qfq.c mask = ~((1UL << __fls(mask)) - 1); mask 1381 net/sched/sch_qfq.c mask = ~0UL; mask 1382 net/sched/sch_qfq.c qfq_move_groups(q, mask, EB, ER); mask 1383 net/sched/sch_qfq.c qfq_move_groups(q, mask, IB, IR); mask 5215 net/sctp/socket.c int mask; mask 5250 net/sctp/socket.c mask = asoc->peer.ecn_capable << 1; mask 5251 net/sctp/socket.c mask = (mask | asoc->peer.ipv4_address) << 1; mask 5252 net/sctp/socket.c mask = (mask | asoc->peer.ipv6_address) << 1; mask 5253 net/sctp/socket.c mask = (mask | asoc->peer.hostname_address) << 1; mask 5254 net/sctp/socket.c mask = (mask | asoc->peer.asconf_capable) << 1; mask 5255 net/sctp/socket.c mask = (mask | asoc->peer.prsctp_capable) << 1; mask 5256 net/sctp/socket.c mask = (mask | asoc->peer.auth_capable); mask 5257 net/sctp/socket.c info->sctpi_peer_capable = mask; mask 5258 net/sctp/socket.c mask = asoc->peer.sack_needed << 1; mask 5259 net/sctp/socket.c mask = (mask | asoc->peer.sack_generation) << 1; mask 5260 net/sctp/socket.c mask = (mask | asoc->peer.zero_window_announced); mask 5261 net/sctp/socket.c info->sctpi_peer_sack = mask; mask 8478 net/sctp/socket.c __poll_t mask; mask 8491 net/sctp/socket.c mask = 0; mask 8495 net/sctp/socket.c mask |= EPOLLERR | mask 8498 net/sctp/socket.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 8500 net/sctp/socket.c mask |= EPOLLHUP; mask 8504 net/sctp/socket.c mask |= EPOLLIN | EPOLLRDNORM; mask 8508 net/sctp/socket.c return mask; mask 8512 net/sctp/socket.c mask |= EPOLLOUT | EPOLLWRNORM; mask 8524 net/sctp/socket.c mask |= EPOLLOUT | EPOLLWRNORM; mask 8526 net/sctp/socket.c return mask; mask 286 net/smc/af_smc.c unsigned long mask) mask 300 net/smc/af_smc.c nsk->sk_flags &= ~mask; mask 301 net/smc/af_smc.c nsk->sk_flags |= osk->sk_flags & mask; mask 1591 net/smc/af_smc.c __poll_t mask = 0; mask 1595 net/smc/af_smc.c mask = EPOLLIN | EPOLLRDNORM; mask 1598 net/smc/af_smc.c return mask; mask 1606 net/smc/af_smc.c __poll_t mask = 0; mask 1614 net/smc/af_smc.c mask = smc->clcsock->ops->poll(file, smc->clcsock, wait); mask 1620 net/smc/af_smc.c mask |= EPOLLERR; mask 1623 net/smc/af_smc.c mask |= EPOLLHUP; mask 1626 net/smc/af_smc.c mask |= smc_accept_poll(sk); mask 1628 net/smc/af_smc.c mask |= smc->clcsock->ops->poll(file, smc->clcsock, mask 1635 net/smc/af_smc.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1641 net/smc/af_smc.c mask |= EPOLLIN | EPOLLRDNORM; mask 1643 net/smc/af_smc.c mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; mask 1645 net/smc/af_smc.c mask |= EPOLLIN; mask 1647 net/smc/af_smc.c mask |= EPOLLPRI; mask 1651 net/smc/af_smc.c return mask; mask 957 net/sunrpc/cache.c __poll_t mask; mask 964 net/sunrpc/cache.c mask = EPOLLOUT | EPOLLWRNORM; mask 967 net/sunrpc/cache.c return mask; mask 974 net/sunrpc/cache.c mask |= EPOLLIN | EPOLLRDNORM; mask 978 net/sunrpc/cache.c return mask; mask 343 net/sunrpc/rpc_pipe.c __poll_t mask = EPOLLOUT | EPOLLWRNORM; mask 349 net/sunrpc/rpc_pipe.c mask |= EPOLLERR | EPOLLHUP; mask 351 net/sunrpc/rpc_pipe.c mask |= EPOLLIN | EPOLLRDNORM; mask 353 net/sunrpc/rpc_pipe.c return mask; mask 168 net/tipc/msg.h static inline u32 msg_bits(struct tipc_msg *m, u32 w, u32 pos, u32 mask) mask 170 net/tipc/msg.h return (msg_word(m, w) >> pos) & mask; mask 174 net/tipc/msg.h u32 pos, u32 mask, u32 val) mask 176 net/tipc/msg.h val = (val & mask) << pos; mask 177 net/tipc/msg.h mask = mask << pos; mask 178 net/tipc/msg.h m->hdr[w] &= ~htonl(mask); mask 2607 net/unix/af_unix.c __poll_t mask; mask 2610 net/unix/af_unix.c mask = 0; mask 2614 net/unix/af_unix.c mask |= EPOLLERR; mask 2616 net/unix/af_unix.c mask |= EPOLLHUP; mask 2618 net/unix/af_unix.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 2622 net/unix/af_unix.c mask |= EPOLLIN | EPOLLRDNORM; mask 2627 net/unix/af_unix.c mask |= EPOLLHUP; mask 2634 net/unix/af_unix.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 2636 net/unix/af_unix.c return mask; mask 2644 net/unix/af_unix.c __poll_t mask; mask 2647 net/unix/af_unix.c mask = 0; mask 2651 net/unix/af_unix.c mask |= EPOLLERR | mask 2655 net/unix/af_unix.c mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; mask 2657 net/unix/af_unix.c mask |= EPOLLHUP; mask 2661 net/unix/af_unix.c mask |= EPOLLIN | EPOLLRDNORM; mask 2666 net/unix/af_unix.c mask |= EPOLLHUP; mask 2669 net/unix/af_unix.c return mask; mask 2674 net/unix/af_unix.c return mask; mask 2690 net/unix/af_unix.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 2694 net/unix/af_unix.c return mask; mask 841 net/vmw_vsock/af_vsock.c __poll_t mask; mask 848 net/vmw_vsock/af_vsock.c mask = 0; mask 852 net/vmw_vsock/af_vsock.c mask |= EPOLLERR; mask 860 net/vmw_vsock/af_vsock.c mask |= EPOLLHUP; mask 865 net/vmw_vsock/af_vsock.c mask |= EPOLLRDHUP; mask 875 net/vmw_vsock/af_vsock.c mask |= EPOLLIN | EPOLLRDNORM; mask 879 net/vmw_vsock/af_vsock.c mask |= EPOLLOUT | EPOLLWRNORM | EPOLLWRBAND; mask 889 net/vmw_vsock/af_vsock.c mask |= EPOLLIN | EPOLLRDNORM; mask 898 net/vmw_vsock/af_vsock.c mask |= EPOLLERR; mask 901 net/vmw_vsock/af_vsock.c mask |= EPOLLIN | EPOLLRDNORM; mask 912 net/vmw_vsock/af_vsock.c mask |= EPOLLIN | EPOLLRDNORM; mask 922 net/vmw_vsock/af_vsock.c mask |= EPOLLERR; mask 928 net/vmw_vsock/af_vsock.c mask |= EPOLLOUT | EPOLLWRNORM; mask 940 net/vmw_vsock/af_vsock.c mask |= EPOLLOUT | EPOLLWRNORM; mask 947 net/vmw_vsock/af_vsock.c return mask; mask 127 net/wireless/core.h kfree(rdev->wiphy.wowlan_config->patterns[i].mask); mask 517 net/wireless/core.h u32 *mask); mask 4115 net/wireless/nl80211.c u32 mask = 0; mask 4125 net/wireless/nl80211.c mask |= 1 << ridx; mask 4133 net/wireless/nl80211.c return mask; mask 4238 net/wireless/nl80211.c struct cfg80211_bitrate_mask *mask) mask 4247 net/wireless/nl80211.c memset(mask, 0, sizeof(*mask)); mask 4255 net/wireless/nl80211.c mask->control[i].legacy = (1 << sband->n_bitrates) - 1; mask 4256 net/wireless/nl80211.c memcpy(mask->control[i].ht_mcs, mask 4258 net/wireless/nl80211.c sizeof(mask->control[i].ht_mcs)); mask 4264 net/wireless/nl80211.c vht_build_mcs_mask(vht_tx_mcs_map, mask->control[i].vht_mcs); mask 4291 net/wireless/nl80211.c mask->control[band].legacy = rateset_to_mask( mask 4295 net/wireless/nl80211.c if ((mask->control[band].legacy == 0) && mask 4304 net/wireless/nl80211.c mask->control[band].ht_mcs)) mask 4311 net/wireless/nl80211.c mask->control[band].vht_mcs)) mask 4315 net/wireless/nl80211.c mask->control[band].gi = mask 4317 net/wireless/nl80211.c if (mask->control[band].gi > NL80211_TXRATE_FORCE_LGI) mask 4321 net/wireless/nl80211.c if (mask->control[band].legacy == 0) { mask 4330 net/wireless/nl80211.c if (mask->control[band].ht_mcs[i]) mask 4334 net/wireless/nl80211.c if (mask->control[band].vht_mcs[i]) mask 4892 net/wireless/nl80211.c params->sta_flags_mask = sta_flags->mask; mask 5037 net/wireless/nl80211.c static bool nl80211_put_signal(struct sk_buff *msg, u8 mask, s8 *signal, mask 5043 net/wireless/nl80211.c if (!mask) mask 5051 net/wireless/nl80211.c if (!(mask & BIT(i))) mask 6711 net/wireless/nl80211.c u32 mask = 0; mask 6714 net/wireless/nl80211.c #define FILL_IN_MESH_PARAM_IF_SET(tb, cfg, param, mask, attr, fn) \ mask 6718 net/wireless/nl80211.c mask |= BIT((attr) - 1); \ mask 6732 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshRetryTimeout, mask, mask 6734 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshConfirmTimeout, mask, mask 6737 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHoldingTimeout, mask, mask 6740 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshMaxPeerLinks, mask, mask 6743 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshMaxRetries, mask, mask 6745 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshTTL, mask, mask 6747 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, element_ttl, mask, mask 6749 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, auto_open_plinks, mask, mask 6753 net/wireless/nl80211.c mask, mask 6756 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMPmaxPREQretries, mask, mask 6759 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, path_refresh_time, mask, mask 6762 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_PATH_REFRESH_TIME) && mask 6765 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, min_discovery_timeout, mask, mask 6769 net/wireless/nl80211.c mask, mask 6772 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT) && mask 6776 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMPpreqMinInterval, mask, mask 6779 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMPperrMinInterval, mask, mask 6783 net/wireless/nl80211.c dot11MeshHWMPnetDiameterTraversalTime, mask, mask 6786 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMPRootMode, mask, mask 6788 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMPRannInterval, mask, mask 6792 net/wireless/nl80211.c mask, NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask 6794 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshForwarding, mask, mask 6796 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, rssi_threshold, mask, mask 6799 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshConnectedToMeshGate, mask, mask 6818 net/wireless/nl80211.c mask |= (1 << (NL80211_MESHCONF_HT_OPMODE - 1)); mask 6821 net/wireless/nl80211.c dot11MeshHWMPactivePathToRootTimeout, mask, mask 6824 net/wireless/nl80211.c if (mask & BIT(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT) && mask 6828 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshHWMProotInterval, mask, mask 6832 net/wireless/nl80211.c mask, mask 6835 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, power_mode, mask, mask 6837 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, dot11MeshAwakeWindowDuration, mask, mask 6839 net/wireless/nl80211.c FILL_IN_MESH_PARAM_IF_SET(tb, cfg, plink_timeout, mask, mask 6842 net/wireless/nl80211.c *mask_out = mask; mask 6910 net/wireless/nl80211.c u32 mask; mask 6919 net/wireless/nl80211.c err = nl80211_parse_mesh_config(info, &cfg, &mask); mask 6928 net/wireless/nl80211.c err = rdev_update_mesh_config(rdev, dev, mask, &cfg); mask 10489 net/wireless/nl80211.c struct cfg80211_bitrate_mask mask; mask 10497 net/wireless/nl80211.c err = nl80211_parse_tx_bitrate_mask(info, &mask); mask 10501 net/wireless/nl80211.c return rdev_set_bitrate_mask(rdev, dev, NULL, &mask); mask 11156 net/wireless/nl80211.c wowlan->patterns[i].mask) || mask 11692 net/wireless/nl80211.c new_triggers.patterns[i].mask = mask_pat; mask 11750 net/wireless/nl80211.c kfree(new_triggers.patterns[i].mask); mask 11800 net/wireless/nl80211.c rule->patterns[j].mask) || mask 11857 net/wireless/nl80211.c kfree(rule->patterns[j].mask); mask 11941 net/wireless/nl80211.c new_rule->patterns[i].mask = mask_pat; mask 12016 net/wireless/nl80211.c kfree(tmp_rule->patterns[j].mask); mask 320 net/wireless/rdev-ops.h struct net_device *dev, u32 mask, mask 324 net/wireless/rdev-ops.h trace_rdev_update_mesh_config(&rdev->wiphy, dev, mask, nconf); mask 325 net/wireless/rdev-ops.h ret = rdev->ops->update_mesh_config(&rdev->wiphy, dev, mask, nconf); mask 642 net/wireless/rdev-ops.h const struct cfg80211_bitrate_mask *mask) mask 645 net/wireless/rdev-ops.h trace_rdev_set_bitrate_mask(&rdev->wiphy, dev, peer, mask); mask 646 net/wireless/rdev-ops.h ret = rdev->ops->set_bitrate_mask(&rdev->wiphy, dev, peer, mask); mask 871 net/wireless/scan.c u16 mask, val; mask 877 net/wireless/scan.c mask = WLAN_CAPABILITY_DMG_TYPE_MASK; mask 892 net/wireless/scan.c mask = WLAN_CAPABILITY_ESS | WLAN_CAPABILITY_IBSS; mask 908 net/wireless/scan.c ret = ((capability & mask) == val); mask 1018 net/wireless/trace.h TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, u32 mask, mask 1020 net/wireless/trace.h TP_ARGS(wiphy, netdev, mask, conf), mask 1025 net/wireless/trace.h __field(u32, mask) mask 1031 net/wireless/trace.h __entry->mask = mask; mask 1034 net/wireless/trace.h WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->mask) mask 1552 net/wireless/trace.h const u8 *peer, const struct cfg80211_bitrate_mask *mask), mask 1553 net/wireless/trace.h TP_ARGS(wiphy, netdev, peer, mask), mask 1852 net/wireless/util.c u32 *mask) mask 1862 net/wireless/util.c *mask = 0; mask 1871 net/wireless/util.c *mask |= BIT(j); mask 1204 net/wireless/wext-compat.c struct cfg80211_bitrate_mask mask; mask 1213 net/wireless/wext-compat.c memset(&mask, 0, sizeof(mask)); mask 1232 net/wireless/wext-compat.c mask.control[band].legacy = 1 << ridx; mask 1237 net/wireless/wext-compat.c mask.control[band].legacy |= 1 << ridx; mask 1246 net/wireless/wext-compat.c return rdev_set_bitrate_mask(rdev, dev, NULL, &mask); mask 434 net/xdp/xsk.c unsigned int mask = datagram_poll(file, sock, wait); mask 440 net/xdp/xsk.c return mask; mask 453 net/xdp/xsk.c mask |= POLLIN | POLLRDNORM; mask 455 net/xdp/xsk.c mask |= POLLOUT | POLLWRNORM; mask 457 net/xdp/xsk.c return mask; mask 609 net/xfrm/xfrm_algo.c u32 mask; mask 616 net/xfrm/xfrm_algo.c .mask = CRYPTO_ALG_TYPE_MASK, mask 623 net/xfrm/xfrm_algo.c .mask = CRYPTO_ALG_TYPE_HASH_MASK, mask 630 net/xfrm/xfrm_algo.c .mask = CRYPTO_ALG_TYPE_BLKCIPHER_MASK, mask 637 net/xfrm/xfrm_algo.c .mask = CRYPTO_ALG_TYPE_MASK, mask 659 net/xfrm/xfrm_algo.c algo_list->mask); mask 65 net/xfrm/xfrm_hash.h __be32 mask; mask 67 net/xfrm/xfrm_hash.h mask = htonl((0xffffffff) << (32 - pbi)); mask 69 net/xfrm/xfrm_hash.h initval = (__force u32)(addr->a6[pdw] & mask); mask 812 net/xfrm/xfrm_policy.c u32 mask = ~0u << (32 - pbi); mask 814 net/xfrm/xfrm_policy.c delta = (ntohl(a->a6[pdw]) & mask) - mask 815 net/xfrm/xfrm_policy.c (ntohl(b->a6[pdw]) & mask); mask 93 samples/seccomp/bpf-direct.c sigset_t mask; mask 95 samples/seccomp/bpf-direct.c sigemptyset(&mask); mask 96 samples/seccomp/bpf-direct.c sigaddset(&mask, SIGSYS); mask 104 samples/seccomp/bpf-direct.c if (sigprocmask(SIG_UNBLOCK, &mask, NULL)) { mask 232 samples/trace_events/trace-events-sample.h const char *string, const struct cpumask *mask), mask 234 samples/trace_events/trace-events-sample.h TP_ARGS(foo, bar, lst, string, mask), mask 250 samples/trace_events/trace-events-sample.h __assign_bitmask(cpus, cpumask_bits(mask), num_possible_cpus()); mask 65 samples/vfio-mdev/mdpy-fb.c u32 value, mask; mask 74 samples/vfio-mdev/mdpy-fb.c mask = (1 << info->var.transp.length) - 1; mask 75 samples/vfio-mdev/mdpy-fb.c mask <<= info->var.transp.offset; mask 76 samples/vfio-mdev/mdpy-fb.c value |= mask; mask 41 samples/vfs/test-statx.c unsigned int mask, struct statx *buffer) mask 43 samples/vfs/test-statx.c return syscall(__NR_statx, dfd, filename, flags, mask, buffer); mask 219 samples/vfs/test-statx.c unsigned int mask = STATX_ALL; mask 237 samples/vfs/test-statx.c mask &= ~STATX_BASIC_STATS; mask 250 samples/vfs/test-statx.c ret = statx(AT_FDCWD, *argv, atflag, mask, &stx); mask 381 scripts/dtc/dtc-parser.y uint64_t mask = (1ULL << $1.bits) - 1; mask 390 scripts/dtc/dtc-parser.y if (($2 > mask) && (($2 | mask) != -1ULL)) mask 16 scripts/gcc-plugins/arm_ssp_per_task_plugin.c rtx mask, masked_sp; mask 36 scripts/gcc-plugins/arm_ssp_per_task_plugin.c mask = GEN_INT(sext_hwi(sp_mask, GET_MODE_PRECISION(Pmode))); mask 42 scripts/gcc-plugins/arm_ssp_per_task_plugin.c mask)), mask 112 scripts/gcc-plugins/latent_entropy_plugin.c unsigned long long mask; mask 114 scripts/gcc-plugins/latent_entropy_plugin.c mask = 1ULL << (TREE_INT_CST_LOW(TYPE_SIZE(type)) - 1); mask 115 scripts/gcc-plugins/latent_entropy_plugin.c mask = 2 * (mask - 1) + 1; mask 118 scripts/gcc-plugins/latent_entropy_plugin.c return build_int_cstu(type, mask & get_random_const()); mask 119 scripts/gcc-plugins/latent_entropy_plugin.c return build_int_cst(type, mask & get_random_const()); mask 114 scripts/kconfig/gconf.c GdkBitmap *mask; mask 118 scripts/kconfig/gconf.c pixmap = gdk_pixmap_create_from_xpm_d(window, &mask, mask 123 scripts/kconfig/gconf.c image = gtk_image_new_from_pixmap(pixmap, mask); mask 16 scripts/kconfig/parser.y #define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt) mask 175 scripts/mod/devicetable-offsets.c DEVID_FIELD(amba_id, mask); mask 1065 scripts/mod/file2alias.c unsigned int nibble, unsigned int mask) mask 1070 scripts/mod/file2alias.c switch (mask) { mask 1088 scripts/mod/file2alias.c if ((i & mask) == nibble) mask 1112 scripts/mod/file2alias.c DEF_FIELD(symval, amba_id, mask); mask 1114 scripts/mod/file2alias.c if ((id & mask) != id) mask 1117 scripts/mod/file2alias.c filename, id, mask); mask 1123 scripts/mod/file2alias.c (mask >> (4 * (7 - digit))) & 0xf); mask 413 security/apparmor/apparmorfs.c static ssize_t policy_update(u32 mask, const char __user *buf, size_t size, mask 425 security/apparmor/apparmorfs.c error = aa_may_manage_policy(label, ns, mask); mask 432 security/apparmor/apparmorfs.c error = aa_replace_profiles(ns, label, mask, data); mask 582 security/apparmor/apparmorfs.c __poll_t mask = 0; mask 588 security/apparmor/apparmorfs.c mask |= EPOLLIN | EPOLLRDNORM; mask 592 security/apparmor/apparmorfs.c return mask; mask 25 security/apparmor/file.c static u32 map_mask_to_chr_mask(u32 mask) mask 27 security/apparmor/file.c u32 m = mask & PERMS_CHRS_MASK; mask 29 security/apparmor/file.c if (mask & AA_MAY_GETATTR) mask 31 security/apparmor/file.c if (mask & (AA_MAY_SETATTR | AA_MAY_CHMOD | AA_MAY_CHOWN)) mask 42 security/apparmor/file.c static void audit_file_mask(struct audit_buffer *ab, u32 mask) mask 47 security/apparmor/file.c map_mask_to_chr_mask(mask)); mask 120 security/apparmor/file.c u32 mask = perms->audit; mask 123 security/apparmor/file.c mask = 0xffff; mask 126 security/apparmor/file.c aad(&sa)->request &= mask; mask 114 security/apparmor/include/file.h static inline u16 dfa_map_xindex(u16 mask) mask 116 security/apparmor/include/file.h u16 old_index = (mask >> 10) & 0xf; mask 119 security/apparmor/include/file.h if (mask & 0x100) mask 121 security/apparmor/include/file.h if (mask & 0x200) mask 123 security/apparmor/include/file.h if (mask & 0x80) mask 137 security/apparmor/include/perms.h u32 mask); mask 139 security/apparmor/include/perms.h u32 mask); mask 140 security/apparmor/include/perms.h void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, mask 193 security/apparmor/include/policy.h u32 mask, struct aa_loaddata *udata); mask 307 security/apparmor/include/policy.h u32 mask); mask 29 security/apparmor/include/resource.h unsigned int mask; mask 26 security/apparmor/ipc.c static void audit_ptrace_mask(struct audit_buffer *ab, u32 mask) mask 28 security/apparmor/ipc.c switch (mask) { mask 149 security/apparmor/ipc.c static void audit_signal_mask(struct audit_buffer *ab, u32 mask) mask 151 security/apparmor/ipc.c if (mask & MAY_READ) mask 153 security/apparmor/ipc.c if (mask & MAY_WRITE) mask 203 security/apparmor/lib.c void aa_perm_mask_to_str(char *str, size_t str_size, const char *chrs, u32 mask) mask 209 security/apparmor/lib.c if (mask & perm) { mask 222 security/apparmor/lib.c u32 mask) mask 229 security/apparmor/lib.c if (mask & perm) { mask 239 security/apparmor/lib.c void aa_audit_perm_mask(struct audit_buffer *ab, u32 mask, const char *chrs, mask 245 security/apparmor/lib.c if ((mask & chrsmask) && chrs) { mask 246 security/apparmor/lib.c aa_perm_mask_to_str(str, sizeof(str), chrs, mask & chrsmask); mask 247 security/apparmor/lib.c mask &= ~chrsmask; mask 249 security/apparmor/lib.c if (mask & namesmask) mask 252 security/apparmor/lib.c if ((mask & namesmask) && names) mask 253 security/apparmor/lib.c aa_audit_perm_names(ab, names, mask & namesmask); mask 193 security/apparmor/lsm.c static int common_perm(const char *op, const struct path *path, u32 mask, mask 201 security/apparmor/lsm.c error = aa_path_perm(op, label, path, 0, mask, cond); mask 215 security/apparmor/lsm.c static int common_perm_cond(const char *op, const struct path *path, u32 mask) mask 224 security/apparmor/lsm.c return common_perm(op, path, mask, &cond); mask 238 security/apparmor/lsm.c struct dentry *dentry, u32 mask, mask 243 security/apparmor/lsm.c return common_perm(op, &path, mask, cond); mask 256 security/apparmor/lsm.c struct dentry *dentry, u32 mask) mask 267 security/apparmor/lsm.c return common_perm_dir_dentry(op, dir, dentry, mask, &cond); mask 281 security/apparmor/lsm.c struct dentry *dentry, u32 mask, umode_t mode) mask 288 security/apparmor/lsm.c return common_perm_dir_dentry(op, dir, dentry, mask, &cond); mask 445 security/apparmor/lsm.c static int common_file_perm(const char *op, struct file *file, u32 mask) mask 455 security/apparmor/lsm.c error = aa_file_perm(op, label, file, mask); mask 466 security/apparmor/lsm.c static int apparmor_file_permission(struct file *file, int mask) mask 468 security/apparmor/lsm.c return common_file_perm(OP_FPERM, file, mask); mask 473 security/apparmor/lsm.c u32 mask = AA_MAY_LOCK; mask 476 security/apparmor/lsm.c mask |= MAY_WRITE; mask 478 security/apparmor/lsm.c return common_file_perm(OP_FLOCK, file, mask); mask 484 security/apparmor/lsm.c int mask = 0; mask 490 security/apparmor/lsm.c mask |= MAY_READ; mask 496 security/apparmor/lsm.c mask |= MAY_WRITE; mask 498 security/apparmor/lsm.c mask |= AA_EXEC_MMAP; mask 500 security/apparmor/lsm.c return common_file_perm(op, file, mask); mask 140 security/apparmor/mount.c u32 mask = perms->audit; mask 143 security/apparmor/mount.c mask = 0xffff; mask 146 security/apparmor/mount.c request &= mask; mask 680 security/apparmor/policy.c int aa_may_manage_policy(struct aa_label *label, struct aa_ns *ns, u32 mask) mask 684 security/apparmor/policy.c if (mask & AA_MAY_REMOVE_POLICY) mask 686 security/apparmor/policy.c else if (mask & AA_MAY_REPLACE_POLICY) mask 857 security/apparmor/policy.c u32 mask, struct aa_loaddata *udata) mask 867 security/apparmor/policy.c op = mask & AA_MAY_REPLACE_POLICY ? OP_PROF_REPL : OP_PROF_LOAD; mask 933 security/apparmor/policy.c !(mask & AA_MAY_REPLACE_POLICY), mask 940 security/apparmor/policy.c !(mask & AA_MAY_REPLACE_POLICY), mask 626 security/apparmor/policy_unpack.c profile->rlimits.mask = tmp; mask 86 security/apparmor/resource.c if (profile->rlimits.mask & (1 << resource) && new_rlim->rlim_max > mask 143 security/apparmor/resource.c unsigned int mask = 0; mask 155 security/apparmor/resource.c if (old->rlimits.mask) { mask 158 security/apparmor/resource.c for (j = 0, mask = 1; j < RLIM_NLIMITS; j++, mask 159 security/apparmor/resource.c mask <<= 1) { mask 160 security/apparmor/resource.c if (old->rlimits.mask & mask) { mask 174 security/apparmor/resource.c if (!new->rlimits.mask) mask 176 security/apparmor/resource.c for (j = 0, mask = 1; j < RLIM_NLIMITS; j++, mask <<= 1) { mask 177 security/apparmor/resource.c if (!(new->rlimits.mask & mask)) mask 209 security/integrity/ima/ima.h int mask, enum ima_hooks func, int *pcr, mask 211 security/integrity/ima/ima.h int ima_must_measure(struct inode *inode, int mask, enum ima_hooks func); mask 233 security/integrity/ima/ima.h enum ima_hooks func, int mask, int flags, int *pcr, mask 261 security/integrity/ima/ima.h int ima_must_appraise(struct inode *inode, int mask, enum ima_hooks func); mask 282 security/integrity/ima/ima.h static inline int ima_must_appraise(struct inode *inode, int mask, mask 185 security/integrity/ima/ima_api.c int mask, enum ima_hooks func, int *pcr, mask 192 security/integrity/ima/ima_api.c return ima_match_policy(inode, cred, secid, func, mask, flags, pcr, mask 48 security/integrity/ima/ima_appraise.c int ima_must_appraise(struct inode *inode, int mask, enum ima_hooks func) mask 56 security/integrity/ima/ima_appraise.c return ima_match_policy(inode, current_cred(), secid, func, mask, mask 193 security/integrity/ima/ima_main.c u32 secid, char *buf, loff_t size, int mask, mask 217 security/integrity/ima/ima_main.c action = ima_get_action(inode, cred, secid, mask, func, &pcr, mask 352 security/integrity/ima/ima_main.c if ((mask & MAY_WRITE) && test_bit(IMA_DIGSIG, &iint->atomic_flags) && mask 433 security/integrity/ima/ima_main.c int ima_file_check(struct file *file, int mask) mask 439 security/integrity/ima/ima_main.c mask & (MAY_READ | MAY_WRITE | MAY_EXEC | mask 68 security/integrity/ima/ima_policy.c int mask; mask 115 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, mask 117 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, mask 119 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, mask 127 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = MMAP_CHECK, .mask = MAY_EXEC, mask 129 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = BPRM_CHECK, .mask = MAY_EXEC, mask 131 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, mask 134 security/integrity/ima/ima_policy.c {.action = MEASURE, .func = FILE_CHECK, .mask = MAY_READ, mask 371 security/integrity/ima/ima_policy.c enum ima_hooks func, int mask) mask 384 security/integrity/ima/ima_policy.c (rule->mask != mask && func != POST_SETATTR)) mask 387 security/integrity/ima/ima_policy.c (!(rule->mask & mask) && func != POST_SETATTR)) mask 493 security/integrity/ima/ima_policy.c enum ima_hooks func, int mask, int flags, int *pcr, mask 508 security/integrity/ima/ima_policy.c if (!ima_match_rules(entry, inode, cred, secid, func, mask)) mask 1015 security/integrity/ima/ima_policy.c if (entry->mask) mask 1023 security/integrity/ima/ima_policy.c entry->mask = MAY_EXEC; mask 1025 security/integrity/ima/ima_policy.c entry->mask = MAY_WRITE; mask 1027 security/integrity/ima/ima_policy.c entry->mask = MAY_READ; mask 1029 security/integrity/ima/ima_policy.c entry->mask = MAY_APPEND; mask 1406 security/integrity/ima/ima_policy.c if (entry->mask & MAY_EXEC) mask 1408 security/integrity/ima/ima_policy.c if (entry->mask & MAY_WRITE) mask 1410 security/integrity/ima/ima_policy.c if (entry->mask & MAY_READ) mask 1412 security/integrity/ima/ima_policy.c if (entry->mask & MAY_APPEND) mask 907 security/security.c int security_path_notify(const struct path *path, u64 mask, mask 910 security/security.c return call_int_hook(path_notify, 0, path, mask, obj_type); mask 1198 security/security.c int security_inode_permission(struct inode *inode, int mask) mask 1202 security/security.c return call_int_hook(inode_permission, 0, inode, mask); mask 1371 security/security.c int security_file_permission(struct file *file, int mask) mask 1375 security/security.c ret = call_int_hook(file_permission, 0, file, mask); mask 1379 security/security.c return fsnotify_perm(file, mask); mask 1977 security/selinux/hooks.c static inline u32 file_mask_to_av(int mode, int mask) mask 1982 security/selinux/hooks.c if (mask & MAY_EXEC) mask 1984 security/selinux/hooks.c if (mask & MAY_READ) mask 1987 security/selinux/hooks.c if (mask & MAY_APPEND) mask 1989 security/selinux/hooks.c else if (mask & MAY_WRITE) mask 1993 security/selinux/hooks.c if (mask & MAY_EXEC) mask 1995 security/selinux/hooks.c if (mask & MAY_WRITE) mask 1997 security/selinux/hooks.c if (mask & MAY_READ) mask 2974 security/selinux/hooks.c static int selinux_inode_mkdir(struct inode *dir, struct dentry *dentry, umode_t mask) mask 3043 security/selinux/hooks.c static int selinux_inode_permission(struct inode *inode, int mask) mask 3048 security/selinux/hooks.c unsigned flags = mask & MAY_NOT_BLOCK; mask 3055 security/selinux/hooks.c from_access = mask & MAY_ACCESS; mask 3056 security/selinux/hooks.c mask &= (MAY_READ|MAY_WRITE|MAY_EXEC|MAY_APPEND); mask 3059 security/selinux/hooks.c if (!mask) mask 3067 security/selinux/hooks.c perms = file_mask_to_av(inode->i_mode, mask); mask 3292 security/selinux/hooks.c static int selinux_path_notify(const struct path *path, u64 mask, mask 3326 security/selinux/hooks.c if (mask & (ALL_FSNOTIFY_PERM_EVENTS)) mask 3330 security/selinux/hooks.c if (mask & (FS_ACCESS | FS_ACCESS_PERM | FS_CLOSE_NOWRITE)) mask 3522 security/selinux/hooks.c static int selinux_revalidate_file_permission(struct file *file, int mask) mask 3528 security/selinux/hooks.c if ((file->f_flags & O_APPEND) && (mask & MAY_WRITE)) mask 3529 security/selinux/hooks.c mask |= MAY_APPEND; mask 3532 security/selinux/hooks.c file_mask_to_av(inode->i_mode, mask)); mask 3535 security/selinux/hooks.c static int selinux_file_permission(struct file *file, int mask) mask 3542 security/selinux/hooks.c if (!mask) mask 3552 security/selinux/hooks.c return selinux_revalidate_file_permission(file, mask); mask 32 security/selinux/ss/avtab.c static inline int avtab_hash(struct avtab_key *keyp, u32 mask) mask 65 security/selinux/ss/avtab.c return hash & mask; mask 115 security/selinux/ss/avtab.c hvalue = avtab_hash(key, h->mask); mask 159 security/selinux/ss/avtab.c hvalue = avtab_hash(key, h->mask); mask 190 security/selinux/ss/avtab.c hvalue = avtab_hash(key, h->mask); mask 226 security/selinux/ss/avtab.c hvalue = avtab_hash(key, h->mask); mask 299 security/selinux/ss/avtab.c h->mask = 0; mask 312 security/selinux/ss/avtab.c u32 mask = 0; mask 329 security/selinux/ss/avtab.c mask = nslot - 1; mask 338 security/selinux/ss/avtab.c h->mask = mask; mask 87 security/selinux/ss/avtab.h u32 mask; /* mask to compute hash func */ mask 2141 security/selinux/ss/policydb.c c->u.node.mask = nodebuf[1]; /* network order */ mask 2177 security/selinux/ss/policydb.c c->u.node6.mask[k] = nodebuf[k+4]; mask 3133 security/selinux/ss/policydb.c nodebuf[1] = c->u.node.mask; /* network order */ mask 3159 security/selinux/ss/policydb.c nodebuf[j + 4] = c->u.node6.mask[j]; /* network order */ mask 180 security/selinux/ss/policydb.h u32 mask; mask 184 security/selinux/ss/policydb.h u32 mask[4]; mask 508 security/selinux/ss/services.c u32 mask = (1 << index); mask 510 security/selinux/ss/services.c if ((mask & permissions) == 0) mask 2439 security/selinux/ss/services.c static int match_ipv6_addrmask(u32 *input, u32 *addr, u32 *mask) mask 2444 security/selinux/ss/services.c if (addr[i] != (input[i] & mask[i])) { mask 2487 security/selinux/ss/services.c if (c->u.node.addr == (addr & c->u.node.mask)) mask 2501 security/selinux/ss/services.c c->u.node6.mask)) mask 1168 security/smack/smack_lsm.c static int smack_inode_permission(struct inode *inode, int mask) mask 1172 security/smack/smack_lsm.c int no_block = mask & MAY_NOT_BLOCK; mask 1175 security/smack/smack_lsm.c mask &= (MAY_READ|MAY_WRITE|MAY_EXEC|MAY_APPEND); mask 1179 security/smack/smack_lsm.c if (mask == 0) mask 1192 security/smack/smack_lsm.c rc = smk_curacc(smk_of_inode(inode), mask, &ad); mask 1193 security/smack/smack_lsm.c rc = smk_bu_inode(inode, mask, rc); mask 1143 security/smack/smackfs.c struct in_addr mask; mask 1215 security/smack/smackfs.c mask.s_addr = cpu_to_be32(temp_mask); mask 1217 security/smack/smackfs.c newname.sin_addr.s_addr &= mask.s_addr; mask 1242 security/smack/smackfs.c snp->smk_mask.s_addr = mask.s_addr; mask 1409 security/smack/smackfs.c unsigned int mask = 128; mask 1438 security/smack/smackfs.c &mask, smack); mask 1449 security/smack/smackfs.c if (mask > 128) { mask 1480 security/smack/smackfs.c for (i = 0, m = mask; i < 8; i++) { mask 1501 security/smack/smackfs.c if (mask != snp->smk_masks) mask 1520 security/smack/smackfs.c snp->smk_masks = mask; mask 10 sound/ac97/ac97_core.h unsigned int mask) mask 12 sound/ac97/ac97_core.h return (id1 & mask) == (id2 & mask); mask 484 sound/ac97/bus.c if (ac97_ids_match(id[i].id, adev->vendor_id, id[i].mask)) mask 373 sound/aoa/codecs/onyx.c u8 mask = pv & 0xff; mask 379 sound/aoa/codecs/onyx.c ucontrol->value.integer.value[0] = !!(c & mask) ^ polarity; mask 394 sound/aoa/codecs/onyx.c u8 mask = pv & 0xff; mask 404 sound/aoa/codecs/onyx.c c &= ~(mask); mask 406 sound/aoa/codecs/onyx.c c |= mask; mask 415 sound/aoa/codecs/onyx.c #define SINGLE_BIT(n, type, description, address, mask, flags) \ mask 423 sound/aoa/codecs/onyx.c .private_value = (flags << 16) | (address << 8) | mask \ mask 180 sound/arm/aaci.c aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) mask 188 sound/arm/aaci.c } while (val & mask && timeout--); mask 196 sound/arm/aaci.c static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) mask 198 sound/arm/aaci.c if (mask & ISR_ORINTR) { mask 203 sound/arm/aaci.c if (mask & ISR_RXTOINTR) { mask 208 sound/arm/aaci.c if (mask & ISR_RXINTR) { mask 263 sound/arm/aaci.c if (mask & ISR_URINTR) { mask 268 sound/arm/aaci.c if (mask & ISR_TXINTR) { mask 327 sound/arm/aaci.c u32 mask; mask 330 sound/arm/aaci.c mask = readl(aaci->base + AACI_ALLINTS); mask 331 sound/arm/aaci.c if (mask) { mask 332 sound/arm/aaci.c u32 m = mask; mask 340 sound/arm/aaci.c return mask ? IRQ_HANDLED : IRQ_NONE; mask 385 sound/arm/aaci.c unsigned int mask = 1 << 0, slots; mask 390 sound/arm/aaci.c mask |= 1 << 1; mask 392 sound/arm/aaci.c mask |= 1 << 2; mask 396 sound/arm/aaci.c ARRAY_SIZE(channel_list), channel_list, mask); mask 1088 sound/arm/aaci.c .mask = 0x000fffff, mask 141 sound/core/control.c void snd_ctl_notify(struct snd_card *card, unsigned int mask, mask 162 sound/core/control.c ev->mask |= mask; mask 169 sound/core/control.c ev->mask = mask; mask 1095 sound/core/control.c unsigned int mask = 0; mask 1118 sound/core/control.c mask = SNDRV_CTL_EVENT_MASK_INFO; mask 1125 sound/core/control.c mask |= SNDRV_CTL_EVENT_MASK_TLV; mask 1128 sound/core/control.c snd_ctl_notify(ue->card, mask, &id); mask 1623 sound/core/control.c ev.data.elem.mask = kev->mask; mask 1645 sound/core/control.c __poll_t mask; mask 1653 sound/core/control.c mask = 0; mask 1655 sound/core/control.c mask |= EPOLLIN | EPOLLRDNORM; mask 1657 sound/core/control.c return mask; mask 195 sound/core/info.c __poll_t mask = 0; mask 202 sound/core/info.c mask |= EPOLLIN | EPOLLRDNORM; mask 204 sound/core/info.c mask |= EPOLLOUT | EPOLLWRNORM; mask 205 sound/core/info.c return mask; mask 96 sound/core/init.c static int get_slot_from_bitmask(int mask, int (*check)(struct module *, int), mask 102 sound/core/init.c if (slot < 32 && !(mask & (1U << slot))) mask 109 sound/core/init.c return mask; /* unchanged */ mask 128 sound/core/jack.c static struct snd_jack_kctl * snd_jack_kctl_new(struct snd_card *card, const char *name, unsigned int mask) mask 148 sound/core/jack.c jack_kctl->mask_bits = mask; mask 170 sound/core/jack.c int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask) mask 174 sound/core/jack.c jack_kctl = snd_jack_kctl_new(jack->card, name, mask); mask 85 sound/core/oss/mulaw.c int mask; mask 92 sound/core/oss/mulaw.c mask = 0x7F; mask 95 sound/core/oss/mulaw.c mask = 0xFF; mask 108 sound/core/oss/mulaw.c return uval ^ mask; mask 841 sound/core/oss/pcm_oss.c struct snd_mask mask; mask 861 sound/core/oss/pcm_oss.c snd_mask_none(&mask); mask 863 sound/core/oss/pcm_oss.c snd_mask_set(&mask, (__force int)SNDRV_PCM_ACCESS_MMAP_INTERLEAVED); mask 865 sound/core/oss/pcm_oss.c snd_mask_set(&mask, (__force int)SNDRV_PCM_ACCESS_RW_INTERLEAVED); mask 867 sound/core/oss/pcm_oss.c snd_mask_set(&mask, (__force int)SNDRV_PCM_ACCESS_RW_NONINTERLEAVED); mask 869 sound/core/oss/pcm_oss.c err = snd_pcm_hw_param_mask(substream, sparams, SNDRV_PCM_HW_PARAM_ACCESS, &mask); mask 2793 sound/core/oss/pcm_oss.c __poll_t mask; mask 2801 sound/core/oss/pcm_oss.c mask = 0; mask 2809 sound/core/oss/pcm_oss.c mask |= EPOLLOUT | EPOLLWRNORM; mask 2819 sound/core/oss/pcm_oss.c mask |= EPOLLIN | EPOLLRDNORM; mask 2830 sound/core/oss/pcm_oss.c return mask; mask 297 sound/core/oss/pcm_plugin.c static int snd_pcm_plug_formats(const struct snd_mask *mask, mask 300 sound/core/oss/pcm_plugin.c struct snd_mask formats = *mask; mask 271 sound/core/pcm_dmaengine.c dma_cap_mask_t mask; mask 273 sound/core/pcm_dmaengine.c dma_cap_zero(mask); mask 274 sound/core/pcm_dmaengine.c dma_cap_set(DMA_SLAVE, mask); mask 275 sound/core/pcm_dmaengine.c dma_cap_set(DMA_CYCLIC, mask); mask 277 sound/core/pcm_dmaengine.c return dma_request_channel(mask, filter_fn, filter_data); mask 130 sound/core/pcm_lib.c #define xrun_debug(substream, mask) \ mask 131 sound/core/pcm_lib.c ((substream)->pstr->xrun_debug & (mask)) mask 133 sound/core/pcm_lib.c #define xrun_debug(substream, mask) 0 mask 995 sound/core/pcm_lib.c const unsigned int *list, unsigned int mask) mask 1008 sound/core/pcm_lib.c if (mask && !(mask & (1 << k))) mask 1034 sound/core/pcm_lib.c const struct snd_interval *ranges, unsigned int mask) mask 1048 sound/core/pcm_lib.c if (mask && !(mask & (1 << k))) mask 1164 sound/core/pcm_lib.c u_int32_t mask) mask 1168 sound/core/pcm_lib.c *maskp->bits &= mask; mask 1186 sound/core/pcm_lib.c u_int64_t mask) mask 1190 sound/core/pcm_lib.c maskp->bits[0] &= (u_int32_t)mask; mask 1191 sound/core/pcm_lib.c maskp->bits[1] &= (u_int32_t)(mask >> 32); mask 1245 sound/core/pcm_lib.c return snd_interval_list(hw_param_interval(params, rule->var), list->count, list->list, list->mask); mask 1276 sound/core/pcm_lib.c r->count, r->ranges, r->mask); mask 1545 sound/core/pcm_lib.c const struct snd_mask *mask = hw_param_mask_c(params, var); mask 1546 sound/core/pcm_lib.c if (!snd_mask_single(mask)) mask 1550 sound/core/pcm_lib.c return snd_mask_value(mask); mask 27 sound/core/pcm_local.h snd_pcm_hw_param_t var, u_int32_t mask); mask 2147 sound/core/pcm_native.c struct snd_mask *mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); mask 2151 sound/core/pcm_native.c if (! snd_mask_test(mask, k)) mask 2159 sound/core/pcm_native.c return snd_mask_refine(mask, &m); mask 2352 sound/core/pcm_native.c unsigned int mask = 0; mask 2355 sound/core/pcm_native.c mask |= 1 << SNDRV_PCM_ACCESS_RW_INTERLEAVED; mask 2357 sound/core/pcm_native.c mask |= 1 << SNDRV_PCM_ACCESS_RW_NONINTERLEAVED; mask 2360 sound/core/pcm_native.c mask |= 1 << SNDRV_PCM_ACCESS_MMAP_INTERLEAVED; mask 2362 sound/core/pcm_native.c mask |= 1 << SNDRV_PCM_ACCESS_MMAP_NONINTERLEAVED; mask 2364 sound/core/pcm_native.c mask |= 1 << SNDRV_PCM_ACCESS_MMAP_COMPLEX; mask 2366 sound/core/pcm_native.c err = snd_pcm_hw_constraint_mask(runtime, SNDRV_PCM_HW_PARAM_ACCESS, mask); mask 3186 sound/core/pcm_native.c __poll_t mask, ok; mask 3202 sound/core/pcm_native.c mask = 0; mask 3210 sound/core/pcm_native.c mask = ok; mask 3214 sound/core/pcm_native.c mask = ok; mask 3216 sound/core/pcm_native.c mask |= EPOLLERR; mask 3220 sound/core/pcm_native.c mask = ok | EPOLLERR; mask 3224 sound/core/pcm_native.c return mask; mask 1414 sound/core/rawmidi.c __poll_t mask; mask 1426 sound/core/rawmidi.c mask = 0; mask 1429 sound/core/rawmidi.c mask |= EPOLLIN | EPOLLRDNORM; mask 1433 sound/core/rawmidi.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1435 sound/core/rawmidi.c return mask; mask 186 sound/core/seq/oss/seq_oss_rw.c __poll_t mask = 0; mask 191 sound/core/seq/oss/seq_oss_rw.c mask |= EPOLLIN | EPOLLRDNORM; mask 197 sound/core/seq/oss/seq_oss_rw.c mask |= EPOLLOUT | EPOLLWRNORM; mask 199 sound/core/seq/oss/seq_oss_rw.c return mask; mask 1125 sound/core/seq/seq_clientmgr.c __poll_t mask = 0; mask 1136 sound/core/seq/seq_clientmgr.c mask |= EPOLLIN | EPOLLRDNORM; mask 1144 sound/core/seq/seq_clientmgr.c mask |= EPOLLOUT | EPOLLWRNORM; mask 1147 sound/core/seq/seq_clientmgr.c return mask; mask 2128 sound/core/timer.c __poll_t mask; mask 2135 sound/core/timer.c mask = 0; mask 2138 sound/core/timer.c mask |= EPOLLIN | EPOLLRDNORM; mask 2140 sound/core/timer.c mask |= EPOLLERR; mask 2143 sound/core/timer.c return mask; mask 39 sound/drivers/vx/vx_core.c int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time) mask 51 sound/drivers/vx/vx_core.c if ((snd_vx_inb(chip, reg) & mask) == bit) mask 55 sound/drivers/vx/vx_core.c snd_printd(KERN_DEBUG "vx_check_reg_bit: timeout, reg=%s, mask=0x%x, val=0x%x\n", reg_names[reg], mask, snd_vx_inb(chip, reg)); mask 323 sound/firewire/fcp.c unsigned int mask, i; mask 327 sound/firewire/fcp.c mask = transaction->response_match_bytes; mask 330 sound/firewire/fcp.c if ((mask & 1) && p1[i] != p2[i]) mask 332 sound/firewire/fcp.c mask >>= 1; mask 333 sound/firewire/fcp.c if (!mask) mask 22 sound/firewire/fireface/ff-protocol-former.c u32 mask; mask 36 sound/firewire/fireface/ff-protocol-former.c u32 mask; mask 48 sound/firewire/fireface/ff-protocol-former.c if ((data & 0x0000001e) == rate_entry->mask) { mask 61 sound/firewire/fireface/ff-protocol-former.c if ((data & 0x00001c00) == clk_entry->mask) { mask 175 sound/firewire/fireface/ff-protocol-former.c u32 mask; mask 185 sound/firewire/fireface/ff-protocol-former.c u32 mask; mask 237 sound/firewire/fireface/ff-protocol-former.c if ((data[0] & 0x1e0000) == referred_entry->mask) { mask 247 sound/firewire/fireface/ff-protocol-former.c if ((data[0] & 0x1e000000) == rate_entry->mask) { mask 225 sound/firewire/motu/motu-protocol-v2.c u32 data, u32 mask, u32 shift) mask 234 sound/firewire/motu/motu-protocol-v2.c data = (data & mask) >> shift; mask 146 sound/firewire/tascam/amdtp-tascam.c __be32 mask; mask 149 sound/firewire/tascam/amdtp-tascam.c mask = cpu_to_be32(~0x0000ffff); mask 151 sound/firewire/tascam/amdtp-tascam.c mask = cpu_to_be32(~0x0000ffff); mask 153 sound/firewire/tascam/amdtp-tascam.c mask = cpu_to_be32(~0x000f0f00); mask 155 sound/firewire/tascam/amdtp-tascam.c mask = cpu_to_be32(~0x00000000); mask 157 sound/firewire/tascam/amdtp-tascam.c if ((before ^ after) & mask) { mask 167 sound/hda/ext/hdac_ext_controller.c int mask = (1 << AZX_MLCTL_CPA_SHIFT); mask 175 sound/hda/ext/hdac_ext_controller.c if (((val & mask) >> AZX_MLCTL_CPA_SHIFT)) mask 178 sound/hda/ext/hdac_ext_controller.c if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT)) mask 120 sound/hda/ext/hdac_ext_stream.c int mask = AZX_PPCTL_PROCEN(hstream->index); mask 123 sound/hda/ext/hdac_ext_stream.c val = readw(bus->ppcap + AZX_REG_PP_PPCTL) & mask; mask 126 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL, mask, mask); mask 128 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->ppcap, AZX_REG_PP_PPCTL, mask, 0); mask 411 sound/hda/ext/hdac_ext_stream.c u32 mask = 0; mask 418 sound/hda/ext/hdac_ext_stream.c mask |= (1 << index); mask 421 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); mask 423 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); mask 494 sound/hda/ext/hdac_ext_stream.c u32 mask = 0; mask 501 sound/hda/ext/hdac_ext_stream.c mask |= (1 << index); mask 504 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); mask 506 sound/hda/ext/hdac_ext_stream.c snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); mask 222 sound/hda/hdac_bus.c unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask) mask 230 sound/hda/hdac_bus.c return (v >> shift) & mask; mask 235 sound/hda/hdac_bus.c unsigned int mask) mask 243 sound/hda/hdac_bus.c v &= ~(mask << shift); mask 463 sound/hda/hdac_device.c unsigned int shift, num_elems, mask; mask 481 sound/hda/hdac_device.c mask = (1 << (shift-1)) - 1; mask 493 sound/hda/hdac_device.c conn_list[0] = parm & mask; mask 512 sound/hda/hdac_device.c val = parm & mask; mask 513 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) mask 521 sound/hda/hdac_regmap.c err = regmap_update_bits_check(codec->regmap, reg, mask, val, mask 528 sound/hda/hdac_regmap.c val &= mask; mask 529 sound/hda/hdac_regmap.c val |= orig & ~mask; mask 551 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) mask 553 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update(codec, reg, mask, val)); mask 558 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) mask 564 sound/hda/hdac_regmap.c return reg_raw_update(codec, reg, mask, val); mask 571 sound/hda/hdac_regmap.c err = regmap_update_bits(codec->regmap, reg, mask, val); mask 588 sound/hda/hdac_regmap.c unsigned int mask, unsigned int val) mask 590 sound/hda/hdac_regmap.c return CALL_RAW_FUNC(codec, reg_raw_update_once(codec, reg, mask, val)); mask 528 sound/hda/hdac_stream.c cc->mask = CLOCKSOURCE_MASK(32); mask 432 sound/hda/hdmi_chmap.c int mask = snd_hdac_chmap_to_spk_mask(pos); mask 441 sound/hda/hdmi_chmap.c if (mask) { mask 443 sound/hda/hdmi_chmap.c if (channel_allocations[ordered_ca].speakers[7 - i] == mask) mask 467 sound/hda/hdmi_chmap.c int mask; mask 475 sound/hda/hdmi_chmap.c mask = channel_allocations[ordered_ca].speakers[7 - slot]; mask 477 sound/hda/hdmi_chmap.c return snd_hdac_spk_to_chmap(mask); mask 486 sound/hda/hdmi_chmap.c int mask = snd_hdac_chmap_to_spk_mask(map[i]); mask 488 sound/hda/hdmi_chmap.c if (mask) { mask 489 sound/hda/hdmi_chmap.c spk_mask |= mask; mask 102 sound/i2c/other/ak4113.c unsigned char mask, unsigned char val) mask 106 sound/i2c/other/ak4113.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); mask 113 sound/i2c/other/ak4114.c void snd_ak4114_reg_write(struct ak4114 *chip, unsigned char reg, unsigned char mask, unsigned char val) mask 116 sound/i2c/other/ak4114.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); mask 119 sound/i2c/other/ak4114.c (chip->txcsb[reg-AK4114_REG_TXCSB0] & ~mask) | val); mask 101 sound/i2c/other/ak4117.c void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val) mask 105 sound/i2c/other/ak4117.c reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val); mask 349 sound/i2c/other/ak4xxx-adda.c #define AK_COMPOSE(chip,addr,shift,mask) \ mask 350 sound/i2c/other/ak4xxx-adda.c (((chip) << 8) | (addr) | ((shift) << 16) | ((mask) << 24)) mask 355 sound/i2c/other/ak4xxx-adda.c unsigned int mask = AK_GET_MASK(kcontrol->private_value); mask 360 sound/i2c/other/ak4xxx-adda.c uinfo->value.integer.max = mask; mask 379 sound/i2c/other/ak4xxx-adda.c unsigned int mask = AK_GET_MASK(kcontrol->private_value); mask 391 sound/i2c/other/ak4xxx-adda.c nval = mask - nval; mask 403 sound/i2c/other/ak4xxx-adda.c unsigned int mask = AK_GET_MASK(kcontrol->private_value); mask 405 sound/i2c/other/ak4xxx-adda.c if (val > mask) mask 413 sound/i2c/other/ak4xxx-adda.c unsigned int mask = AK_GET_MASK(kcontrol->private_value); mask 418 sound/i2c/other/ak4xxx-adda.c uinfo->value.integer.max = mask; mask 438 sound/i2c/other/ak4xxx-adda.c unsigned int mask = AK_GET_MASK(kcontrol->private_value); mask 444 sound/i2c/other/ak4xxx-adda.c if (val[0] > mask || val[1] > mask) mask 567 sound/i2c/other/ak4xxx-adda.c int mask = AK_GET_MASK(kcontrol->private_value); mask 570 sound/i2c/other/ak4xxx-adda.c val = snd_akm4xxx_get(ak, chip, addr) & mask; mask 582 sound/i2c/other/ak4xxx-adda.c int mask = AK_GET_MASK(kcontrol->private_value); mask 590 sound/i2c/other/ak4xxx-adda.c val = oval & ~mask; mask 591 sound/i2c/other/ak4xxx-adda.c val |= ucontrol->value.enumerated.item[0] & mask; mask 46 sound/isa/ad1816a/ad1816a_lib.c unsigned char mask, unsigned char value) mask 49 sound/isa/ad1816a/ad1816a_lib.c (value & mask) | (snd_ad1816a_in(chip, reg) & ~mask)); mask 68 sound/isa/ad1816a/ad1816a_lib.c unsigned short mask, unsigned short value) mask 71 sound/isa/ad1816a/ad1816a_lib.c (value & mask) | (snd_ad1816a_read(chip, reg) & ~mask)); mask 758 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_SINGLE_TLV(xname, reg, shift, mask, invert, xtlv) \ mask 763 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ mask 765 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_SINGLE(xname, reg, shift, mask, invert) \ mask 768 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 772 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 774 sound/isa/ad1816a/ad1816a_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 777 sound/isa/ad1816a/ad1816a_lib.c uinfo->value.integer.max = mask; mask 787 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 791 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = (snd_ad1816a_read(chip, reg) >> shift) & mask; mask 794 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 804 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 809 sound/isa/ad1816a/ad1816a_lib.c val = (ucontrol->value.integer.value[0] & mask); mask 811 sound/isa/ad1816a/ad1816a_lib.c val = mask - val; mask 815 sound/isa/ad1816a/ad1816a_lib.c val = (old_val & ~(mask << shift)) | val; mask 822 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \ mask 827 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \ mask 830 sound/isa/ad1816a/ad1816a_lib.c #define AD1816A_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ mask 833 sound/isa/ad1816a/ad1816a_lib.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) } mask 837 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 839 sound/isa/ad1816a/ad1816a_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 842 sound/isa/ad1816a/ad1816a_lib.c uinfo->value.integer.max = mask; mask 853 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 859 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = (val >> shift_left) & mask; mask 860 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[1] = (val >> shift_right) & mask; mask 863 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 864 sound/isa/ad1816a/ad1816a_lib.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 876 sound/isa/ad1816a/ad1816a_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 881 sound/isa/ad1816a/ad1816a_lib.c val1 = ucontrol->value.integer.value[0] & mask; mask 882 sound/isa/ad1816a/ad1816a_lib.c val2 = ucontrol->value.integer.value[1] & mask; mask 884 sound/isa/ad1816a/ad1816a_lib.c val1 = mask - val1; mask 885 sound/isa/ad1816a/ad1816a_lib.c val2 = mask - val2; mask 891 sound/isa/ad1816a/ad1816a_lib.c val1 = (old_val & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2; mask 380 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 384 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 386 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ mask 391 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ mask 396 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 398 sound/isa/cs423x/cs4236_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 401 sound/isa/cs423x/cs4236_lib.c uinfo->value.integer.max = mask; mask 411 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 415 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->eimage[CS4236_REG(reg)] >> shift) & mask; mask 418 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 428 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 433 sound/isa/cs423x/cs4236_lib.c val = (ucontrol->value.integer.value[0] & mask); mask 435 sound/isa/cs423x/cs4236_lib.c val = mask - val; mask 438 sound/isa/cs423x/cs4236_lib.c val = (chip->eimage[CS4236_REG(reg)] & ~(mask << shift)) | val; mask 445 sound/isa/cs423x/cs4236_lib.c #define CS4236_SINGLEC(xname, xindex, reg, shift, mask, invert) \ mask 449 sound/isa/cs423x/cs4236_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 457 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 461 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->cimage[reg] >> shift) & mask; mask 464 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 474 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 479 sound/isa/cs423x/cs4236_lib.c val = (ucontrol->value.integer.value[0] & mask); mask 481 sound/isa/cs423x/cs4236_lib.c val = mask - val; mask 484 sound/isa/cs423x/cs4236_lib.c val = (chip->cimage[reg] & ~(mask << shift)) | val; mask 491 sound/isa/cs423x/cs4236_lib.c #define CS4236_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 495 sound/isa/cs423x/cs4236_lib.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 498 sound/isa/cs423x/cs4236_lib.c shift_right, mask, invert, xtlv) \ mask 504 sound/isa/cs423x/cs4236_lib.c (shift_right << 19) | (mask << 24) | (invert << 22), \ mask 509 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 511 sound/isa/cs423x/cs4236_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 514 sound/isa/cs423x/cs4236_lib.c uinfo->value.integer.max = mask; mask 526 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 530 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->eimage[CS4236_REG(left_reg)] >> shift_left) & mask; mask 531 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[1] = (chip->eimage[CS4236_REG(right_reg)] >> shift_right) & mask; mask 534 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 535 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 548 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 553 sound/isa/cs423x/cs4236_lib.c val1 = ucontrol->value.integer.value[0] & mask; mask 554 sound/isa/cs423x/cs4236_lib.c val2 = ucontrol->value.integer.value[1] & mask; mask 556 sound/isa/cs423x/cs4236_lib.c val1 = mask - val1; mask 557 sound/isa/cs423x/cs4236_lib.c val2 = mask - val2; mask 563 sound/isa/cs423x/cs4236_lib.c val1 = (chip->eimage[CS4236_REG(left_reg)] & ~(mask << shift_left)) | val1; mask 564 sound/isa/cs423x/cs4236_lib.c val2 = (chip->eimage[CS4236_REG(right_reg)] & ~(mask << shift_right)) | val2; mask 569 sound/isa/cs423x/cs4236_lib.c val1 = (chip->eimage[CS4236_REG(left_reg)] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2; mask 578 sound/isa/cs423x/cs4236_lib.c shift_right, mask, invert) \ mask 582 sound/isa/cs423x/cs4236_lib.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 585 sound/isa/cs423x/cs4236_lib.c shift_right, mask, invert, xtlv) \ mask 591 sound/isa/cs423x/cs4236_lib.c (shift_right << 19) | (mask << 24) | (invert << 22), \ mask 602 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 606 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; mask 607 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[1] = (chip->eimage[CS4236_REG(right_reg)] >> shift_right) & mask; mask 610 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 611 sound/isa/cs423x/cs4236_lib.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 624 sound/isa/cs423x/cs4236_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 629 sound/isa/cs423x/cs4236_lib.c val1 = ucontrol->value.integer.value[0] & mask; mask 630 sound/isa/cs423x/cs4236_lib.c val2 = ucontrol->value.integer.value[1] & mask; mask 632 sound/isa/cs423x/cs4236_lib.c val1 = mask - val1; mask 633 sound/isa/cs423x/cs4236_lib.c val2 = mask - val2; mask 638 sound/isa/cs423x/cs4236_lib.c val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; mask 639 sound/isa/cs423x/cs4236_lib.c val2 = (chip->eimage[CS4236_REG(right_reg)] & ~(mask << shift_right)) | val2; mask 777 sound/isa/es1688/es1688_lib.c #define ES1688_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 781 sound/isa/es1688/es1688_lib.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 785 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 787 sound/isa/es1688/es1688_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 790 sound/isa/es1688/es1688_lib.c uinfo->value.integer.max = mask; mask 800 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 804 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[0] = (snd_es1688_mixer_read(chip, reg) >> shift) & mask; mask 807 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 817 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 822 sound/isa/es1688/es1688_lib.c nval = (ucontrol->value.integer.value[0] & mask); mask 824 sound/isa/es1688/es1688_lib.c nval = mask - nval; mask 828 sound/isa/es1688/es1688_lib.c nval = (oval & ~(mask << shift)) | nval; mask 836 sound/isa/es1688/es1688_lib.c #define ES1688_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 840 sound/isa/es1688/es1688_lib.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 844 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 846 sound/isa/es1688/es1688_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 849 sound/isa/es1688/es1688_lib.c uinfo->value.integer.max = mask; mask 861 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 878 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[0] = (left >> shift_left) & mask; mask 879 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[1] = (right >> shift_right) & mask; mask 881 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 882 sound/isa/es1688/es1688_lib.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 895 sound/isa/es1688/es1688_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 900 sound/isa/es1688/es1688_lib.c val1 = ucontrol->value.integer.value[0] & mask; mask 901 sound/isa/es1688/es1688_lib.c val2 = ucontrol->value.integer.value[1] & mask; mask 903 sound/isa/es1688/es1688_lib.c val1 = mask - val1; mask 904 sound/isa/es1688/es1688_lib.c val2 = mask - val2; mask 918 sound/isa/es1688/es1688_lib.c val1 = (oval1 & ~(mask << shift_left)) | val1; mask 919 sound/isa/es1688/es1688_lib.c val2 = (oval2 & ~(mask << shift_right)) | val2; mask 936 sound/isa/es1688/es1688_lib.c val1 = (oval1 & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2; mask 231 sound/isa/es18xx.c unsigned char mask, unsigned char val) mask 248 sound/isa/es18xx.c oval = old & mask; mask 253 sound/isa/es18xx.c new = (old & ~mask) | (val & mask); mask 297 sound/isa/es18xx.c unsigned char mask, unsigned char val) mask 304 sound/isa/es18xx.c oval = old & mask; mask 306 sound/isa/es18xx.c new = (old & ~mask) | (val & mask); mask 318 sound/isa/es18xx.c unsigned char mask) mask 325 sound/isa/es18xx.c expected = old ^ mask; mask 1094 sound/isa/es18xx.c unsigned char mask, unsigned char val) mask 1097 sound/isa/es18xx.c return snd_es18xx_mixer_bits(chip, reg, mask, val); mask 1099 sound/isa/es18xx.c return snd_es18xx_bits(chip, reg, mask, val); mask 1110 sound/isa/es18xx.c #define ES18XX_SINGLE(xname, xindex, reg, shift, mask, flags) \ mask 1114 sound/isa/es18xx.c .private_value = reg | (shift << 8) | (mask << 16) | (flags << 24) } mask 1121 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1123 sound/isa/es18xx.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 1126 sound/isa/es18xx.c uinfo->value.integer.max = mask; mask 1135 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1144 sound/isa/es18xx.c ucontrol->value.integer.value[0] = (val >> shift) & mask; mask 1146 sound/isa/es18xx.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 1155 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1160 sound/isa/es18xx.c val = (ucontrol->value.integer.value[0] & mask); mask 1162 sound/isa/es18xx.c val = mask - val; mask 1163 sound/isa/es18xx.c mask <<= shift; mask 1168 sound/isa/es18xx.c if ((cur & mask) == val) mask 1170 sound/isa/es18xx.c outb((cur & ~mask) | val, chip->port + ES18XX_PM); mask 1174 sound/isa/es18xx.c return snd_es18xx_reg_bits(chip, reg, mask, val) != val; mask 1177 sound/isa/es18xx.c #define ES18XX_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 1181 sound/isa/es18xx.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 1185 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1187 sound/isa/es18xx.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 1190 sound/isa/es18xx.c uinfo->value.integer.max = mask; mask 1201 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1210 sound/isa/es18xx.c ucontrol->value.integer.value[0] = (left >> shift_left) & mask; mask 1211 sound/isa/es18xx.c ucontrol->value.integer.value[1] = (right >> shift_right) & mask; mask 1213 sound/isa/es18xx.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 1214 sound/isa/es18xx.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 1226 sound/isa/es18xx.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1231 sound/isa/es18xx.c val1 = ucontrol->value.integer.value[0] & mask; mask 1232 sound/isa/es18xx.c val2 = ucontrol->value.integer.value[1] & mask; mask 1234 sound/isa/es18xx.c val1 = mask - val1; mask 1235 sound/isa/es18xx.c val2 = mask - val2; mask 1239 sound/isa/es18xx.c mask1 = mask << shift_left; mask 1240 sound/isa/es18xx.c mask2 = mask << shift_right; mask 1384 sound/isa/es18xx.c int mask = 0; mask 1530 sound/isa/es18xx.c mask = 0x10; mask 1532 sound/isa/es18xx.c snd_es18xx_mixer_write(chip, 0x1c, 0x05 | mask); mask 1534 sound/isa/es18xx.c snd_es18xx_mixer_write(chip, 0x1c, 0x00 | mask); mask 326 sound/isa/opl3sa2.c #define OPL3SA2_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 330 sound/isa/opl3sa2.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 331 sound/isa/opl3sa2.c #define OPL3SA2_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ mask 337 sound/isa/opl3sa2.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ mask 346 sound/isa/opl3sa2.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 350 sound/isa/opl3sa2.c ucontrol->value.integer.value[0] = (chip->ctlregs[reg] >> shift) & mask; mask 353 sound/isa/opl3sa2.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 363 sound/isa/opl3sa2.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 368 sound/isa/opl3sa2.c val = (ucontrol->value.integer.value[0] & mask); mask 370 sound/isa/opl3sa2.c val = mask - val; mask 374 sound/isa/opl3sa2.c val = (oval & ~(mask << shift)) | val; mask 381 sound/isa/opl3sa2.c #define OPL3SA2_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 385 sound/isa/opl3sa2.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 386 sound/isa/opl3sa2.c #define OPL3SA2_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \ mask 392 sound/isa/opl3sa2.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \ mask 403 sound/isa/opl3sa2.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 407 sound/isa/opl3sa2.c ucontrol->value.integer.value[0] = (chip->ctlregs[left_reg] >> shift_left) & mask; mask 408 sound/isa/opl3sa2.c ucontrol->value.integer.value[1] = (chip->ctlregs[right_reg] >> shift_right) & mask; mask 411 sound/isa/opl3sa2.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 412 sound/isa/opl3sa2.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 425 sound/isa/opl3sa2.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 430 sound/isa/opl3sa2.c val1 = ucontrol->value.integer.value[0] & mask; mask 431 sound/isa/opl3sa2.c val2 = ucontrol->value.integer.value[1] & mask; mask 433 sound/isa/opl3sa2.c val1 = mask - val1; mask 434 sound/isa/opl3sa2.c val2 = mask - val2; mask 442 sound/isa/opl3sa2.c val1 = (oval1 & ~(mask << shift_left)) | val1; mask 443 sound/isa/opl3sa2.c val2 = (oval2 & ~(mask << shift_right)) | val2; mask 449 sound/isa/opl3sa2.c val1 = (oval1 & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2; mask 871 sound/isa/opti9xx/miro.c unsigned char reg, unsigned char value, unsigned char mask) mask 875 sound/isa/opti9xx/miro.c snd_miro_write(chip, reg, (oldval & ~mask) | (value & mask)); mask 321 sound/isa/opti9xx/opti92x-ad1848.c unsigned char reg, unsigned char value, unsigned char mask) mask 325 sound/isa/opti9xx/opti92x-ad1848.c snd_opti9xx_write(chip, reg, (oldval & ~mask) | (value & mask)); mask 47 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 49 sound/isa/sb/sb_mixer.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 52 sound/isa/sb/sb_mixer.c uinfo->value.integer.max = mask; mask 62 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 66 sound/isa/sb/sb_mixer.c val = (snd_sbmixer_read(sb, reg) >> shift) & mask; mask 78 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 82 sound/isa/sb/sb_mixer.c val = (ucontrol->value.integer.value[0] & mask) << shift; mask 85 sound/isa/sb/sb_mixer.c val = (oval & ~(mask << shift)) | val; mask 99 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 101 sound/isa/sb/sb_mixer.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 104 sound/isa/sb/sb_mixer.c uinfo->value.integer.max = mask; mask 116 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 120 sound/isa/sb/sb_mixer.c left = (snd_sbmixer_read(sb, left_reg) >> left_shift) & mask; mask 121 sound/isa/sb/sb_mixer.c right = (snd_sbmixer_read(sb, right_reg) >> right_shift) & mask; mask 136 sound/isa/sb/sb_mixer.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 140 sound/isa/sb/sb_mixer.c left = (ucontrol->value.integer.value[0] & mask) << left_shift; mask 141 sound/isa/sb/sb_mixer.c right = (ucontrol->value.integer.value[1] & mask) << right_shift; mask 145 sound/isa/sb/sb_mixer.c left = (oleft & ~((mask << left_shift) | (mask << right_shift))) | left | right; mask 152 sound/isa/sb/sb_mixer.c left = (oleft & ~(mask << left_shift)) | left; mask 153 sound/isa/sb/sb_mixer.c right = (oright & ~(mask << right_shift)) | right; mask 118 sound/isa/wavefront/wavefront_midi.c int max = 256, mask = 1; mask 190 sound/isa/wavefront/wavefront_midi.c mask = 0; mask 191 sound/isa/wavefront/wavefront_midi.c mpu = midi->output_mpu ^ mask; mask 192 sound/isa/wavefront/wavefront_midi.c mask = 0; /* don't invert the value from now */ mask 276 sound/isa/wavefront/wavefront_synth.c wavefront_wait (snd_wavefront_t *dev, int mask) mask 286 sound/isa/wavefront/wavefront_synth.c if (wavefront_status (dev) & mask) { mask 294 sound/isa/wavefront/wavefront_synth.c if (wavefront_status (dev) & mask) { mask 66 sound/isa/wss/wss_lib.c .mask = 0, mask 2043 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2045 sound/isa/wss/wss_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 2048 sound/isa/wss/wss_lib.c uinfo->value.integer.max = mask; mask 2060 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2064 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; mask 2067 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 2079 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2084 sound/isa/wss/wss_lib.c val = (ucontrol->value.integer.value[0] & mask); mask 2086 sound/isa/wss/wss_lib.c val = mask - val; mask 2089 sound/isa/wss/wss_lib.c val = (chip->image[reg] & ~(mask << shift)) | val; mask 2100 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 2102 sound/isa/wss/wss_lib.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 2105 sound/isa/wss/wss_lib.c uinfo->value.integer.max = mask; mask 2119 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 2123 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; mask 2124 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask; mask 2127 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 2128 sound/isa/wss/wss_lib.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 2143 sound/isa/wss/wss_lib.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 2148 sound/isa/wss/wss_lib.c val1 = ucontrol->value.integer.value[0] & mask; mask 2149 sound/isa/wss/wss_lib.c val2 = ucontrol->value.integer.value[1] & mask; mask 2151 sound/isa/wss/wss_lib.c val1 = mask - val1; mask 2152 sound/isa/wss/wss_lib.c val2 = mask - val2; mask 2158 sound/isa/wss/wss_lib.c val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; mask 2159 sound/isa/wss/wss_lib.c val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; mask 2165 sound/isa/wss/wss_lib.c mask = (mask << shift_left) | (mask << shift_right); mask 2166 sound/isa/wss/wss_lib.c val1 = (chip->image[left_reg] & ~mask) | val1 | val2; mask 189 sound/mips/ad1843.c int w, mask, oldval, newbits; mask 192 sound/mips/ad1843.c mask = ((1 << field->nbits) - 1) << field->lo_bit; mask 193 sound/mips/ad1843.c oldval = (w & mask) >> field->lo_bit; mask 194 sound/mips/ad1843.c newbits = (newval << field->lo_bit) & mask; mask 195 sound/mips/ad1843.c w = (w & ~mask) | newbits; mask 218 sound/mips/ad1843.c int w = 0, mask, *value, reg = -1; mask 229 sound/mips/ad1843.c mask = (1 << fp->nbits) - 1; mask 230 sound/mips/ad1843.c *value = w >> fp->lo_bit & mask; mask 252 sound/mips/ad1843.c int w, m, mask, bits; mask 254 sound/mips/ad1843.c mask = 0; mask 267 sound/mips/ad1843.c mask |= m; mask 272 sound/mips/ad1843.c if (~mask & 0xFFFF) mask 276 sound/mips/ad1843.c w = (w & ~mask) | bits; mask 300 sound/mips/ad1843.c unsigned short mask = (1 << gp->lfield->nbits) - 1; mask 304 sound/mips/ad1843.c lg = mask - lg; mask 305 sound/mips/ad1843.c rg = mask - rg; mask 326 sound/mips/ad1843.c unsigned short mask = (1 << gp->lfield->nbits) - 1; mask 328 sound/mips/ad1843.c int lg = (newval >> 0) & mask; mask 329 sound/mips/ad1843.c int rg = (newval >> 8) & mask; mask 334 sound/mips/ad1843.c lg = mask - lg; mask 335 sound/mips/ad1843.c rg = mask - rg; mask 675 sound/oss/dmasound/dmasound_core.c __poll_t mask = 0; mask 687 sound/oss/dmasound/dmasound_core.c mask |= EPOLLOUT | EPOLLWRNORM; mask 688 sound/oss/dmasound/dmasound_core.c return mask; mask 91 sound/parisc/harmony.c .mask = 0, mask 679 sound/parisc/harmony.c int mask = (kc->private_value >> 16) & 0xff; mask 683 sound/parisc/harmony.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : mask 687 sound/parisc/harmony.c uinfo->value.integer.max = mask; mask 699 sound/parisc/harmony.c int mask = (kc->private_value >> 16) & 0xff; mask 705 sound/parisc/harmony.c left = (h->st.gain >> shift_left) & mask; mask 706 sound/parisc/harmony.c right = (h->st.gain >> shift_right) & mask; mask 708 sound/parisc/harmony.c left = mask - left; mask 709 sound/parisc/harmony.c right = mask - right; mask 728 sound/parisc/harmony.c int mask = (kc->private_value >> 16) & 0xff; mask 735 sound/parisc/harmony.c left = ucontrol->value.integer.value[0] & mask; mask 737 sound/parisc/harmony.c left = mask - left; mask 738 sound/parisc/harmony.c h->st.gain &= ~( (mask << shift_left ) ); mask 742 sound/parisc/harmony.c right = ucontrol->value.integer.value[1] & mask; mask 744 sound/parisc/harmony.c right = mask - right; mask 745 sound/parisc/harmony.c h->st.gain &= ~( (mask << shift_right) ); mask 805 sound/parisc/harmony.c #define HARMONY_VOLUME(xname, left_shift, right_shift, mask, invert) \ mask 810 sound/parisc/harmony.c ((mask) << 16) | ((invert) << 24)) } mask 47 sound/pci/ac97/ac97_codec.c unsigned int mask; mask 383 sound/pci/ac97/ac97_codec.c int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value) mask 390 sound/pci/ac97/ac97_codec.c change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); mask 399 sound/pci/ac97/ac97_codec.c unsigned short mask, unsigned short value) mask 405 sound/pci/ac97/ac97_codec.c new = (old & ~mask) | (value & mask); mask 415 sound/pci/ac97/ac97_codec.c static int snd_ac97_ad18xx_update_pcm_bits(struct snd_ac97 *ac97, int codec, unsigned short mask, unsigned short value) mask 422 sound/pci/ac97/ac97_codec.c new = (old & ~mask) | (value & mask); mask 453 sound/pci/ac97/ac97_codec.c e->mask, e->texts); mask 463 sound/pci/ac97/ac97_codec.c for (bitmask = 1; bitmask < e->mask; bitmask <<= 1) mask 479 sound/pci/ac97/ac97_codec.c unsigned short mask, bitmask; mask 481 sound/pci/ac97/ac97_codec.c for (bitmask = 1; bitmask < e->mask; bitmask <<= 1) mask 483 sound/pci/ac97/ac97_codec.c if (ucontrol->value.enumerated.item[0] > e->mask - 1) mask 486 sound/pci/ac97/ac97_codec.c mask = (bitmask - 1) << e->shift_l; mask 488 sound/pci/ac97/ac97_codec.c if (ucontrol->value.enumerated.item[1] > e->mask - 1) mask 491 sound/pci/ac97/ac97_codec.c mask |= (bitmask - 1) << e->shift_r; mask 493 sound/pci/ac97/ac97_codec.c return snd_ac97_update_bits(ac97, e->reg, mask, val); mask 523 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 527 sound/pci/ac97/ac97_codec.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 530 sound/pci/ac97/ac97_codec.c uinfo->value.integer.max = mask; mask 541 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 546 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[0] = (snd_ac97_read_cache(ac97, reg) >> shift) & mask; mask 548 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[1] = (snd_ac97_read_cache(ac97, reg) >> rshift) & mask; mask 550 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 552 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 565 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 571 sound/pci/ac97/ac97_codec.c val = (ucontrol->value.integer.value[0] & mask); mask 573 sound/pci/ac97/ac97_codec.c val = mask - val; mask 574 sound/pci/ac97/ac97_codec.c val_mask = mask << shift; mask 577 sound/pci/ac97/ac97_codec.c val2 = (ucontrol->value.integer.value[1] & mask); mask 579 sound/pci/ac97/ac97_codec.c val2 = mask - val2; mask 580 sound/pci/ac97/ac97_codec.c val_mask |= mask << rshift; mask 808 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 813 sound/pci/ac97/ac97_codec.c value = (ucontrol->value.integer.value[0] & mask); mask 816 sound/pci/ac97/ac97_codec.c mask <<= shift; mask 819 sound/pci/ac97/ac97_codec.c new = (old & ~mask) | value; mask 825 sound/pci/ac97/ac97_codec.c change = snd_ac97_update_bits_nolock(ac97, reg, mask, value); mask 867 sound/pci/ac97/ac97_codec.c #define AD18XX_PCM_BITS(xname, codec, lshift, rshift, mask) \ mask 870 sound/pci/ac97/ac97_codec.c .private_value = (codec) | ((lshift) << 8) | ((rshift) << 12) | ((mask) << 16) } mask 875 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0x0f; mask 879 sound/pci/ac97/ac97_codec.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 885 sound/pci/ac97/ac97_codec.c uinfo->value.integer.max = mask; mask 895 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 897 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[0] = mask - ((ac97->spec.ad18xx.pcmreg[codec] >> lshift) & mask); mask 899 sound/pci/ac97/ac97_codec.c ucontrol->value.integer.value[1] = mask - ((ac97->spec.ad18xx.pcmreg[codec] >> rshift) & mask); mask 909 sound/pci/ac97/ac97_codec.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 912 sound/pci/ac97/ac97_codec.c val = (mask - (ucontrol->value.integer.value[0] & mask)) << lshift; mask 913 sound/pci/ac97/ac97_codec.c valmask = mask << lshift; mask 915 sound/pci/ac97/ac97_codec.c val |= (mask - (ucontrol->value.integer.value[1] & mask)) << rshift; mask 916 sound/pci/ac97/ac97_codec.c valmask |= mask << rshift; mask 1027 sound/pci/ac97/ac97_codec.c unsigned short val, mask = AC97_MUTE_MASK_MONO; mask 1054 sound/pci/ac97/ac97_codec.c mask = 0x0080; mask 1063 sound/pci/ac97/ac97_codec.c if (!(val & mask)) { mask 1066 sound/pci/ac97/ac97_codec.c snd_ac97_write_cache(ac97, reg, val | mask); mask 1069 sound/pci/ac97/ac97_codec.c if (!(val & mask)) mask 1117 sound/pci/ac97/ac97_codec.c unsigned short mask, val, orig, res; mask 1119 sound/pci/ac97/ac97_codec.c mask = 1 << bit; mask 1121 sound/pci/ac97/ac97_codec.c val = orig ^ mask; mask 1778 sound/pci/ac97/ac97_codec.c if (pid->id == (id & pid->mask)) mask 1806 sound/pci/ac97/ac97_codec.c if (pid->mask != 0xffffffff) mask 1807 sound/pci/ac97/ac97_codec.c sprintf(name + strlen(name), " rev %d", id & ~pid->mask); mask 1828 sound/pci/ac97/ac97_codec.c if (pid->id == (ac97->id & pid->mask)) mask 2343 sound/pci/ac97/ac97_codec.c unsigned short mask; mask 2439 sound/pci/ac97/ac97_codec.c bits = power_regs[i].mask; mask 2441 sound/pci/ac97/ac97_codec.c power_regs[i].mask, bits); mask 2760 sound/pci/ac97/ac97_codec.c unsigned short mask; mask 2762 sound/pci/ac97/ac97_codec.c mask = AC97_MUTE_MASK_STEREO; mask 2764 sound/pci/ac97/ac97_codec.c mask = AC97_MUTE_MASK_MONO; mask 2766 sound/pci/ac97/ac97_codec.c (ac97->regs[AC97_MASTER] & mask) == mask ? mask 2796 sound/pci/ac97/ac97_codec.c unsigned short mask; mask 2798 sound/pci/ac97/ac97_codec.c mask = AC97_MUTE_MASK_STEREO; mask 2800 sound/pci/ac97/ac97_codec.c mask = AC97_MUTE_MASK_MONO; mask 2802 sound/pci/ac97/ac97_codec.c (ac97->regs[AC97_MASTER] & mask) == mask ? mask 2905 sound/pci/ac97/ac97_codec.c if ((! quirk->mask && quirk->subdevice == ac97->subsystem_device) || mask 2906 sound/pci/ac97/ac97_codec.c quirk->subdevice == (quirk->mask & ac97->subsystem_device)) { mask 13 sound/pci/ac97/ac97_local.h unsigned short mask, unsigned short value); mask 53 sound/pci/ac97/ac97_patch.c static int ac97_update_bits_page(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value, unsigned short page) mask 61 sound/pci/ac97/ac97_patch.c ret = snd_ac97_update_bits(ac97, reg, mask, value); mask 1455 sound/pci/ac97/ac97_patch.c static unsigned short patch_ad1881_unchained(struct snd_ac97 * ac97, int idx, unsigned short mask) mask 1460 sound/pci/ac97/ac97_patch.c snd_ac97_update_bits(ac97, AC97_AD_SERIAL_CFG, 0x7000, mask); mask 1465 sound/pci/ac97/ac97_patch.c ac97->spec.ad18xx.unchained[idx] = mask; mask 1468 sound/pci/ac97/ac97_patch.c return mask; mask 3631 sound/pci/ac97/ac97_patch.c unsigned short mask; mask 3641 sound/pci/ac97/ac97_patch.c .mask = 0x03, mask 3649 sound/pci/ac97/ac97_patch.c .mask = 0x0c, mask 3657 sound/pci/ac97/ac97_patch.c .mask = 0x30, mask 3688 sound/pci/ac97/ac97_patch.c vt1618_uaj[kcontrol->private_value].mask; mask 3703 sound/pci/ac97/ac97_patch.c vt1618_uaj[kcontrol->private_value].mask, mask 10 sound/pci/ac97/ac97_patch.h #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \ mask 11 sound/pci/ac97/ac97_patch.h ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \ mask 13 sound/pci/ac97/ac97_patch.h #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \ mask 14 sound/pci/ac97/ac97_patch.h (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26)) mask 15 sound/pci/ac97/ac97_patch.h #define AC97_SINGLE(xname, reg, shift, mask, invert) \ mask 19 sound/pci/ac97/ac97_patch.h .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) } mask 20 sound/pci/ac97/ac97_patch.h #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \ mask 24 sound/pci/ac97/ac97_patch.h .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) } mask 25 sound/pci/ac97/ac97_patch.h #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ mask 29 sound/pci/ac97/ac97_patch.h .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) | ((mask) << 16) | ((invert) << 24) } mask 36 sound/pci/ac97/ac97_patch.h unsigned short mask; mask 42 sound/pci/ac97/ac97_patch.h .mask = xmask, .texts = xtexts } mask 161 sound/pci/ac97/ac97_pcm.c unsigned short old, bits, reg, mask; mask 177 sound/pci/ac97/ac97_pcm.c mask = 1 << AC97_SC_SPSR_SHIFT; mask 192 sound/pci/ac97/ac97_pcm.c mask = AC97_SC_SPSR_MASK; mask 196 sound/pci/ac97/ac97_pcm.c old = snd_ac97_read(ac97, reg) & mask; mask 199 sound/pci/ac97/ac97_pcm.c snd_ac97_update_bits_nolock(ac97, reg, mask, bits); mask 46 sound/pci/ak4531_codec.c #define AK4531_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 50 sound/pci/ak4531_codec.c .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22) } mask 51 sound/pci/ak4531_codec.c #define AK4531_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ mask 57 sound/pci/ak4531_codec.c .private_value = reg | (shift << 16) | (mask << 24) | (invert << 22), \ mask 62 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 64 sound/pci/ak4531_codec.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 67 sound/pci/ak4531_codec.c uinfo->value.integer.max = mask; mask 76 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 81 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] >> shift) & mask; mask 84 sound/pci/ak4531_codec.c val = mask - val; mask 95 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 100 sound/pci/ak4531_codec.c val = ucontrol->value.integer.value[0] & mask; mask 102 sound/pci/ak4531_codec.c val = mask - val; mask 106 sound/pci/ak4531_codec.c val = (ak4531->regs[reg] & ~(mask << shift)) | val; mask 113 sound/pci/ak4531_codec.c #define AK4531_DOUBLE(xname, xindex, left_reg, right_reg, left_shift, right_shift, mask, invert) \ mask 117 sound/pci/ak4531_codec.c .private_value = left_reg | (right_reg << 8) | (left_shift << 16) | (right_shift << 19) | (mask << 24) | (invert << 22) } mask 118 sound/pci/ak4531_codec.c #define AK4531_DOUBLE_TLV(xname, xindex, left_reg, right_reg, left_shift, right_shift, mask, invert, xtlv) \ mask 124 sound/pci/ak4531_codec.c .private_value = left_reg | (right_reg << 8) | (left_shift << 16) | (right_shift << 19) | (mask << 24) | (invert << 22), \ mask 129 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 131 sound/pci/ak4531_codec.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 134 sound/pci/ak4531_codec.c uinfo->value.integer.max = mask; mask 145 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 150 sound/pci/ak4531_codec.c left = (ak4531->regs[left_reg] >> left_shift) & mask; mask 151 sound/pci/ak4531_codec.c right = (ak4531->regs[right_reg] >> right_shift) & mask; mask 154 sound/pci/ak4531_codec.c left = mask - left; mask 155 sound/pci/ak4531_codec.c right = mask - right; mask 169 sound/pci/ak4531_codec.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 174 sound/pci/ak4531_codec.c left = ucontrol->value.integer.value[0] & mask; mask 175 sound/pci/ak4531_codec.c right = ucontrol->value.integer.value[1] & mask; mask 177 sound/pci/ak4531_codec.c left = mask - left; mask 178 sound/pci/ak4531_codec.c right = mask - right; mask 184 sound/pci/ak4531_codec.c left = (ak4531->regs[left_reg] & ~((mask << left_shift) | (mask << right_shift))) | left | right; mask 188 sound/pci/ak4531_codec.c left = (ak4531->regs[left_reg] & ~(mask << left_shift)) | left; mask 189 sound/pci/ak4531_codec.c right = (ak4531->regs[right_reg] & ~(mask << right_shift)) | right; mask 504 sound/pci/ali5451/ali5451.c unsigned int mask; mask 509 sound/pci/ali5451/ali5451.c mask = 1 << (channel & 0x1f); mask 511 sound/pci/ali5451/ali5451.c pchregs->data.ainten &= ~mask; mask 605 sound/pci/ali5451/ali5451.c unsigned int mask = 1 << (channel & 0x1f); mask 608 sound/pci/ali5451/ali5451.c outl(mask, ALI_REG(codec, codec->chregs.regs.stop)); mask 837 sound/pci/ali5451/ali5451.c unsigned int old, mask; mask 843 sound/pci/ali5451/ali5451.c mask = 1U << (channel & 0x1f); mask 845 sound/pci/ali5451/ali5451.c if (!(old & mask)) mask 859 sound/pci/ali5451/ali5451.c (inl(ALI_REG(codec, ALI_CSPF)) & mask) == mask); mask 877 sound/pci/ali5451/ali5451.c outl(mask,ALI_REG(codec,pchregs->regs.aint)); mask 878 sound/pci/ali5451/ali5451.c pchregs->data.aint = old & (~mask); mask 1592 sound/pci/ali5451/ali5451.c .mask = 0, mask 1067 sound/pci/asihpi/hpi6000.c u32 mask = 0; mask 1086 sound/pci/asihpi/hpi6000.c mask = 0xFFFFFF00L; mask 1092 sound/pci/asihpi/hpi6000.c mask = 0x00000000L; mask 1098 sound/pci/asihpi/hpi6000.c mask = 0x00000000L; mask 1102 sound/pci/asihpi/hpi6000.c mask = 0xFFFF0000L; mask 1105 sound/pci/asihpi/hpi6000.c test_data = 0xAAAAAA00L & mask; mask 1109 sound/pci/asihpi/hpi6000.c PLD_BASE_ADDRESS + 4L) & mask; mask 1115 sound/pci/asihpi/hpi6000.c test_data = 0x55555500L & mask; mask 1118 sound/pci/asihpi/hpi6000.c PLD_BASE_ADDRESS + 4L) & mask; mask 876 sound/pci/asihpi/hpi_internal.h u16 mask; mask 300 sound/pci/atiixp.c unsigned int mask, unsigned int value) mask 305 sound/pci/atiixp.c data &= ~mask; mask 320 sound/pci/atiixp.c #define atiixp_update(chip,reg,mask,val) \ mask 321 sound/pci/atiixp.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) mask 268 sound/pci/atiixp_modem.c unsigned int mask, unsigned int value) mask 273 sound/pci/atiixp_modem.c data &= ~mask; mask 288 sound/pci/atiixp_modem.c #define atiixp_update(chip,reg,mask,val) \ mask 289 sound/pci/atiixp_modem.c snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) mask 853 sound/pci/atiixp_modem.c .mask = 0, mask 110 sound/pci/au88x0/au88x0_pcm.c .mask = 0, mask 320 sound/pci/azt3328.c snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) mask 327 sound/pci/azt3328.c new = (do_set) ? (prev|mask) : (prev & ~mask); mask 856 sound/pci/azt3328.c unsigned int mask; mask 862 sound/pci/azt3328.c #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ mask 864 sound/pci/azt3328.c (mask << 16) | \ mask 874 sound/pci/azt3328.c r->mask = (val >> 16) & 0xff; mask 891 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ mask 895 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ mask 898 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ mask 902 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ mask 905 sound/pci/azt3328.c #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ mask 909 sound/pci/azt3328.c .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ mask 926 sound/pci/azt3328.c uinfo->type = reg.mask == 1 ? mask 930 sound/pci/azt3328.c uinfo->value.integer.max = reg.mask; mask 945 sound/pci/azt3328.c val = (oreg >> reg.lchan_shift) & reg.mask; mask 947 sound/pci/azt3328.c val = reg.mask - val; mask 950 sound/pci/azt3328.c val = (oreg >> reg.rchan_shift) & reg.mask; mask 952 sound/pci/azt3328.c val = reg.mask - val; mask 959 sound/pci/azt3328.c reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); mask 973 sound/pci/azt3328.c val = ucontrol->value.integer.value[0] & reg.mask; mask 975 sound/pci/azt3328.c val = reg.mask - val; mask 976 sound/pci/azt3328.c nreg = oreg & ~(reg.mask << reg.lchan_shift); mask 979 sound/pci/azt3328.c val = ucontrol->value.integer.value[1] & reg.mask; mask 981 sound/pci/azt3328.c val = reg.mask - val; mask 982 sound/pci/azt3328.c nreg &= ~(reg.mask << reg.rchan_shift); mask 985 sound/pci/azt3328.c if (reg.mask >= 0x07) /* it's a volume control, so better take care */ mask 2023 sound/pci/azt3328.c .mask = 0, mask 1267 sound/pci/ca0106/ca0106_main.c int mask; mask 1282 sound/pci/ca0106/ca0106_main.c mask = 0x11; /* 0x1 for one half, 0x10 for the other half period. */ mask 1285 sound/pci/ca0106/ca0106_main.c if (stat76 & mask) { mask 1296 sound/pci/ca0106/ca0106_main.c mask <<= 1; mask 1298 sound/pci/ca0106/ca0106_main.c mask = 0x110000; /* 0x1 for one half, 0x10 for the other half period. */ mask 1301 sound/pci/ca0106/ca0106_main.c if (stat76 & mask) { mask 1312 sound/pci/ca0106/ca0106_main.c mask <<= 1; mask 90 sound/pci/ca0106/ca0106_mixer.c unsigned int source, mask; mask 92 sound/pci/ca0106/ca0106_mixer.c mask = snd_ca0106_ptr_read(emu, CAPTURE_SOURCE, 0) & 0xffff; mask 93 sound/pci/ca0106/ca0106_mixer.c snd_ca0106_ptr_write(emu, CAPTURE_SOURCE, 0, source | mask); mask 713 sound/pci/cmipci.c .mask = 0, mask 718 sound/pci/cmipci.c .mask = 0, mask 723 sound/pci/cmipci.c .mask = 0, mask 1433 sound/pci/cmipci.c unsigned int status, mask = 0; mask 1443 sound/pci/cmipci.c mask |= CM_CH0_INT_EN; mask 1445 sound/pci/cmipci.c mask |= CM_CH1_INT_EN; mask 1446 sound/pci/cmipci.c snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); mask 1447 sound/pci/cmipci.c snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); mask 1592 sound/pci/cmipci.c .mask = 0, mask 1991 sound/pci/cmipci.c unsigned int mask; mask 1996 sound/pci/cmipci.c #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ mask 1997 sound/pci/cmipci.c ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) mask 1999 sound/pci/cmipci.c #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ mask 2003 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ mask 2006 sound/pci/cmipci.c #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) mask 2007 sound/pci/cmipci.c #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) mask 2019 sound/pci/cmipci.c r->mask = (val >> 24) & 0xff; mask 2028 sound/pci/cmipci.c uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 2031 sound/pci/cmipci.c uinfo->value.integer.max = reg.mask; mask 2044 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; mask 2046 sound/pci/cmipci.c val = reg.mask - val; mask 2049 sound/pci/cmipci.c val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; mask 2051 sound/pci/cmipci.c val = reg.mask - val; mask 2067 sound/pci/cmipci.c left = ucontrol->value.integer.value[0] & reg.mask; mask 2069 sound/pci/cmipci.c left = reg.mask - left; mask 2072 sound/pci/cmipci.c right = ucontrol->value.integer.value[1] & reg.mask; mask 2074 sound/pci/cmipci.c right = reg.mask - right; mask 2080 sound/pci/cmipci.c left |= oleft & ~(reg.mask << reg.left_shift); mask 2088 sound/pci/cmipci.c right |= oright & ~(reg.mask << reg.right_shift); mask 2179 sound/pci/cmipci.c #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ mask 2183 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ mask 2186 sound/pci/cmipci.c #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ mask 2190 sound/pci/cmipci.c .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ mask 2199 sound/pci/cmipci.c uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 2202 sound/pci/cmipci.c uinfo->value.integer.max = reg.mask; mask 2217 sound/pci/cmipci.c val = (oreg >> reg.left_shift) & reg.mask; mask 2219 sound/pci/cmipci.c val = reg.mask - val; mask 2222 sound/pci/cmipci.c val = (oreg >> reg.right_shift) & reg.mask; mask 2224 sound/pci/cmipci.c val = reg.mask - val; mask 2241 sound/pci/cmipci.c val = ucontrol->value.integer.value[0] & reg.mask; mask 2243 sound/pci/cmipci.c val = reg.mask - val; mask 2244 sound/pci/cmipci.c nreg = oreg & ~(reg.mask << reg.left_shift); mask 2247 sound/pci/cmipci.c val = ucontrol->value.integer.value[1] & reg.mask; mask 2249 sound/pci/cmipci.c val = reg.mask - val; mask 2250 sound/pci/cmipci.c nreg &= ~(reg.mask << reg.right_shift); mask 2324 sound/pci/cmipci.c unsigned int mask; /* mask bits */ mask 2351 sound/pci/cmipci.c ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; mask 2384 sound/pci/cmipci.c change = (val & args->mask) != (ucontrol->value.integer.value[0] ? mask 2385 sound/pci/cmipci.c args->mask_on : (args->mask & ~args->mask_on)); mask 2387 sound/pci/cmipci.c val &= ~args->mask; mask 2391 sound/pci/cmipci.c val |= (args->mask & ~args->mask_on); mask 2414 sound/pci/cmipci.c .mask = xmask, \ mask 1478 sound/pci/cs46xx/cs46xx_lib.c .mask = 0 mask 281 sound/pci/echoaudio/echoaudio.c pipe->constr.mask = 0; mask 780 sound/pci/emu10k1/emu10k1x.c int mask; mask 798 sound/pci/emu10k1/emu10k1x.c mask = IPR_CH_0_LOOP|IPR_CH_0_HALF_LOOP; mask 800 sound/pci/emu10k1/emu10k1x.c if (status & mask) { mask 804 sound/pci/emu10k1/emu10k1x.c snd_emu10k1x_intr_disable(chip, mask); mask 807 sound/pci/emu10k1/emu10k1x.c mask <<= 1; mask 580 sound/pci/emu10k1/emumixer.c unsigned int mask = kcontrol->private_value & 0xff; mask 581 sound/pci/emu10k1/emumixer.c ucontrol->value.integer.value[0] = (emu->emu1010.adc_pads & mask) ? 1 : 0; mask 588 sound/pci/emu10k1/emumixer.c unsigned int mask = kcontrol->private_value & 0xff; mask 593 sound/pci/emu10k1/emumixer.c cache = cache | mask; mask 595 sound/pci/emu10k1/emumixer.c cache = cache & ~mask; mask 628 sound/pci/emu10k1/emumixer.c unsigned int mask = kcontrol->private_value & 0xff; mask 629 sound/pci/emu10k1/emumixer.c ucontrol->value.integer.value[0] = (emu->emu1010.dac_pads & mask) ? 1 : 0; mask 636 sound/pci/emu10k1/emumixer.c unsigned int mask = kcontrol->private_value & 0xff; mask 641 sound/pci/emu10k1/emumixer.c cache = cache | mask; mask 643 sound/pci/emu10k1/emumixer.c cache = cache & ~mask; mask 1236 sound/pci/emu10k1/emumixer.c int mask = emu->audigy ? 0x3f : 0x0f; mask 1242 sound/pci/emu10k1/emumixer.c mix->send_routing[voice][idx] & mask; mask 1256 sound/pci/emu10k1/emumixer.c int mask = emu->audigy ? 0x3f : 0x0f; mask 1261 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[(voice * num_efx) + idx] & mask; mask 1450 sound/pci/emu10k1/emumixer.c int mask = emu->audigy ? 0x3f : 0x0f; mask 1455 sound/pci/emu10k1/emumixer.c mix->send_routing[0][idx] & mask; mask 1469 sound/pci/emu10k1/emumixer.c int mask = emu->audigy ? 0x3f : 0x0f; mask 1473 sound/pci/emu10k1/emumixer.c val = ucontrol->value.integer.value[idx] & mask; mask 167 sound/pci/emu10k1/emupcm.c .mask = 0 mask 177 sound/pci/emu10k1/emupcm.c .mask = 0 mask 25 sound/pci/emu10k1/io.c unsigned int mask; mask 27 sound/pci/emu10k1/io.c mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; mask 28 sound/pci/emu10k1/io.c regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK); mask 35 sound/pci/emu10k1/io.c mask = ((1 << size) - 1) << offset; mask 42 sound/pci/emu10k1/io.c return (val & mask) >> offset; mask 58 sound/pci/emu10k1/io.c unsigned int mask; mask 62 sound/pci/emu10k1/io.c mask = emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK; mask 63 sound/pci/emu10k1/io.c regptr = ((reg << 16) & mask) | (chn & PTR_CHANNELNUM_MASK); mask 70 sound/pci/emu10k1/io.c mask = ((1 << size) - 1) << offset; mask 71 sound/pci/emu10k1/io.c data = (data << offset) & mask; mask 75 sound/pci/emu10k1/io.c data |= inl(emu->port + DATA) & ~mask; mask 143 sound/pci/emu10k1/irq.c u32 mask = INTE2_PLAYBACK_CH_0_LOOP; /* Full Loop */ mask 149 sound/pci/emu10k1/irq.c if(status2 & mask) { mask 155 sound/pci/emu10k1/irq.c status2, mask, pvoice, mask 750 sound/pci/emu10k1/p16v.c u32 mask; mask 760 sound/pci/emu10k1/p16v.c mask = snd_emu10k1_ptr20_read(emu, BASIC_INTERRUPT, 0) & 0xffff; mask 761 sound/pci/emu10k1/p16v.c snd_emu10k1_ptr20_write(emu, BASIC_INTERRUPT, 0, source | mask); mask 461 sound/pci/ens1370.c .mask = 0, mask 1680 sound/pci/ens1370.c #define ENSONIQ_CONTROL(xname, mask) \ mask 1683 sound/pci/ens1370.c .private_value = mask } mask 1691 sound/pci/ens1370.c int mask = kcontrol->private_value; mask 1694 sound/pci/ens1370.c ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; mask 1703 sound/pci/ens1370.c int mask = kcontrol->private_value; mask 1707 sound/pci/ens1370.c nval = ucontrol->value.integer.value[0] ? mask : 0; mask 1709 sound/pci/ens1370.c change = (ensoniq->ctrl & mask) != nval; mask 1710 sound/pci/ens1370.c ensoniq->ctrl &= ~mask; mask 2146 sound/pci/ens1370.c unsigned char status, mask, byte; mask 2152 sound/pci/ens1370.c mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; mask 2153 sound/pci/ens1370.c while (mask) { mask 2155 sound/pci/ens1370.c if ((status & mask) == 0) mask 2164 sound/pci/ens1370.c mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; mask 2165 sound/pci/ens1370.c while (mask) { mask 2167 sound/pci/ens1370.c if ((status & mask) == 0) mask 2172 sound/pci/ens1370.c mask &= ~ES_TXRDY; mask 273 sound/pci/es1938.c unsigned char mask, unsigned char val) mask 280 sound/pci/es1938.c oval = old & mask; mask 282 sound/pci/es1938.c new = (old & ~mask) | (val & mask); mask 355 sound/pci/es1938.c static int snd_es1938_bits(struct es1938 *chip, unsigned char reg, unsigned char mask, mask 364 sound/pci/es1938.c oval = old & mask; mask 367 sound/pci/es1938.c new = (old & ~mask) | (val & mask); mask 1143 sound/pci/es1938.c unsigned char mask, unsigned char val) mask 1146 sound/pci/es1938.c return snd_es1938_mixer_bits(chip, reg, mask, val); mask 1148 sound/pci/es1938.c return snd_es1938_bits(chip, reg, mask, val); mask 1159 sound/pci/es1938.c #define ES1938_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ mask 1165 sound/pci/es1938.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ mask 1167 sound/pci/es1938.c #define ES1938_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 1171 sound/pci/es1938.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 1176 sound/pci/es1938.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1178 sound/pci/es1938.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 1181 sound/pci/es1938.c uinfo->value.integer.max = mask; mask 1191 sound/pci/es1938.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1196 sound/pci/es1938.c ucontrol->value.integer.value[0] = (val >> shift) & mask; mask 1198 sound/pci/es1938.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 1208 sound/pci/es1938.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1212 sound/pci/es1938.c val = (ucontrol->value.integer.value[0] & mask); mask 1214 sound/pci/es1938.c val = mask - val; mask 1215 sound/pci/es1938.c mask <<= shift; mask 1217 sound/pci/es1938.c return snd_es1938_reg_bits(chip, reg, mask, val) != val; mask 1220 sound/pci/es1938.c #define ES1938_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \ mask 1226 sound/pci/es1938.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \ mask 1228 sound/pci/es1938.c #define ES1938_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 1232 sound/pci/es1938.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 1237 sound/pci/es1938.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1239 sound/pci/es1938.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 1242 sound/pci/es1938.c uinfo->value.integer.max = mask; mask 1254 sound/pci/es1938.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1263 sound/pci/es1938.c ucontrol->value.integer.value[0] = (left >> shift_left) & mask; mask 1264 sound/pci/es1938.c ucontrol->value.integer.value[1] = (right >> shift_right) & mask; mask 1266 sound/pci/es1938.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 1267 sound/pci/es1938.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 1280 sound/pci/es1938.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1285 sound/pci/es1938.c val1 = ucontrol->value.integer.value[0] & mask; mask 1286 sound/pci/es1938.c val2 = ucontrol->value.integer.value[1] & mask; mask 1288 sound/pci/es1938.c val1 = mask - val1; mask 1289 sound/pci/es1938.c val2 = mask - val2; mask 1293 sound/pci/es1938.c mask1 = mask << shift_left; mask 1294 sound/pci/es1938.c mask2 = mask << shift_right; mask 256 sound/pci/fm801.c unsigned short mask, unsigned short value) mask 264 sound/pci/fm801.c new = (old & ~mask) | value; mask 336 sound/pci/fm801.c .mask = 0, mask 346 sound/pci/fm801.c .mask = 0, mask 835 sound/pci/fm801.c #define FM801_SINGLE(xname, reg, shift, mask, invert) \ mask 838 sound/pci/fm801.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 843 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 845 sound/pci/fm801.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 848 sound/pci/fm801.c uinfo->value.integer.max = mask; mask 858 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 862 sound/pci/fm801.c value[0] = (fm801_ioread16(chip, reg) >> shift) & mask; mask 864 sound/pci/fm801.c value[0] = mask - value[0]; mask 874 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 878 sound/pci/fm801.c val = (ucontrol->value.integer.value[0] & mask); mask 880 sound/pci/fm801.c val = mask - val; mask 881 sound/pci/fm801.c return snd_fm801_update_bits(chip, reg, mask << shift, val << shift); mask 884 sound/pci/fm801.c #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \ mask 887 sound/pci/fm801.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) } mask 888 sound/pci/fm801.c #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \ mask 893 sound/pci/fm801.c .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \ mask 899 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 901 sound/pci/fm801.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 904 sound/pci/fm801.c uinfo->value.integer.max = mask; mask 915 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 920 sound/pci/fm801.c value[0] = (fm801_ioread16(chip, reg) >> shift_left) & mask; mask 921 sound/pci/fm801.c value[1] = (fm801_ioread16(chip, reg) >> shift_right) & mask; mask 924 sound/pci/fm801.c value[0] = mask - value[0]; mask 925 sound/pci/fm801.c value[1] = mask - value[1]; mask 937 sound/pci/fm801.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 941 sound/pci/fm801.c val1 = ucontrol->value.integer.value[0] & mask; mask 942 sound/pci/fm801.c val2 = ucontrol->value.integer.value[1] & mask; mask 944 sound/pci/fm801.c val1 = mask - val1; mask 945 sound/pci/fm801.c val2 = mask - val2; mask 948 sound/pci/fm801.c (mask << shift_left) | (mask << shift_right), mask 1021 sound/pci/hda/hda_auto_parser.c unsigned int mask = 0xffff0000 | q->subdevice_mask; mask 1022 sound/pci/hda/hda_auto_parser.c if ((codec->core.subsystem_id & mask) == (vendorid & mask)) { mask 1295 sound/pci/hda/hda_codec.c int ch, int dir, int idx, int mask, int val) mask 1299 sound/pci/hda/hda_codec.c return snd_hdac_regmap_update_raw(&codec->core, cmd, mask, val); mask 1316 sound/pci/hda/hda_codec.c int direction, int idx, int mask, int val) mask 1320 sound/pci/hda/hda_codec.c if (snd_BUG_ON(mask & ~0xff)) mask 1321 sound/pci/hda/hda_codec.c mask &= 0xff; mask 1324 sound/pci/hda/hda_codec.c idx, mask, val); mask 1344 sound/pci/hda/hda_codec.c int dir, int idx, int mask, int val) mask 1350 sound/pci/hda/hda_codec.c return snd_hdac_regmap_update_raw_once(&codec->core, cmd, mask, val); mask 1366 sound/pci/hda/hda_codec.c int dir, int idx, int mask, int val) mask 1370 sound/pci/hda/hda_codec.c if (snd_BUG_ON(mask & ~0xff)) mask 1371 sound/pci/hda/hda_codec.c mask &= 0xff; mask 1374 sound/pci/hda/hda_codec.c idx, mask, val); mask 2278 sound/pci/hda/hda_codec.c int mask, int val) mask 2283 sound/pci/hda/hda_codec.c mask, val); mask 2289 sound/pci/hda/hda_codec.c AC_VERB_SET_DIGI_CONVERT_1, mask, val); mask 2295 sound/pci/hda/hda_codec.c unsigned int mask = 0; mask 2299 sound/pci/hda/hda_codec.c mask |= 0xff; mask 2303 sound/pci/hda/hda_codec.c mask |= 0xff00; mask 2306 sound/pci/hda/hda_codec.c set_dig_out(codec, nid, mask, val); mask 711 sound/pci/hda/hda_generic.c unsigned int mask, unsigned int val) mask 715 sound/pci/hda/hda_generic.c mask, val); mask 718 sound/pci/hda/hda_generic.c mask, val); mask 728 sound/pci/hda/hda_generic.c unsigned int mask = 0xff; mask 732 sound/pci/hda/hda_generic.c mask &= ~0x80; mask 737 sound/pci/hda/hda_generic.c mask &= ~0x7f; mask 739 sound/pci/hda/hda_generic.c return mask; mask 746 sound/pci/hda/hda_generic.c unsigned int mask, val; mask 750 sound/pci/hda/hda_generic.c mask = get_amp_mask_to_modify(codec, nid, dir, idx_to_check, caps); mask 751 sound/pci/hda/hda_generic.c if (!mask) mask 754 sound/pci/hda/hda_generic.c val &= mask; mask 755 sound/pci/hda/hda_generic.c update_amp(codec, nid, dir, idx, mask, val); mask 3933 sound/pci/hda/hda_generic.c unsigned int mask; mask 3940 sound/pci/hda/hda_generic.c mask = 1U << snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); mask 3945 sound/pci/hda/hda_generic.c spec->micmute_led.capture |= mask; mask 3947 sound/pci/hda/hda_generic.c spec->micmute_led.capture &= ~mask; mask 404 sound/pci/hda/hda_intel.c unsigned char mask, unsigned char val) mask 409 sound/pci/hda/hda_intel.c data &= ~mask; mask 410 sound/pci/hda/hda_intel.c data |= (val & mask); mask 120 sound/pci/hda/hda_local.h int ch, int dir, int idx, int mask, int val); mask 122 sound/pci/hda/hda_local.h int dir, int idx, int mask, int val); mask 124 sound/pci/hda/hda_local.h int direction, int idx, int mask, int val); mask 126 sound/pci/hda/hda_local.h int dir, int idx, int mask, int val); mask 7830 sound/pci/hda/patch_ca0132.c int mask, int data) mask 7835 sound/pci/hda/patch_ca0132.c if (mask >= 0) mask 7837 sound/pci/hda/patch_ca0132.c AC_VERB_SET_GPIO_MASK, mask); mask 613 sound/pci/hda/patch_conexant.c static void cxt_update_gpio_led(struct hda_codec *codec, unsigned int mask, mask 623 sound/pci/hda/patch_conexant.c spec->gpio_led |= mask; mask 625 sound/pci/hda/patch_conexant.c spec->gpio_led &= ~mask; mask 627 sound/pci/hda/patch_conexant.c mask, led_on, spec->gpio_led); mask 3084 sound/pci/hda/patch_hdmi.c .mask = 0, mask 3090 sound/pci/hda/patch_hdmi.c .mask = 0, mask 3754 sound/pci/hda/patch_hdmi.c int mask = snd_hdac_chmap_to_spk_mask(map[i]); mask 3758 sound/pci/hda/patch_hdmi.c if (!mask) mask 3763 sound/pci/hda/patch_hdmi.c if (cap->speakers[chan_idx] == mask) { mask 156 sound/pci/hda/patch_realtek.c unsigned int coef_idx, unsigned int mask, mask 163 sound/pci/hda/patch_realtek.c (val & ~mask) | bits_set); mask 166 sound/pci/hda/patch_realtek.c #define alc_update_coef_idx(codec, coef_idx, mask, bits_set) \ mask 167 sound/pci/hda/patch_realtek.c alc_update_coefex_idx(codec, 0x20, coef_idx, mask, bits_set) mask 183 sound/pci/hda/patch_realtek.c unsigned short mask; mask 188 sound/pci/hda/patch_realtek.c { .nid = (_nid), .idx = (_idx), .mask = (_mask), .val = (_val) } mask 197 sound/pci/hda/patch_realtek.c if (fw->mask == (unsigned short)-1) mask 201 sound/pci/hda/patch_realtek.c fw->mask, fw->val); mask 210 sound/pci/hda/patch_realtek.c static void alc_setup_gpio(struct hda_codec *codec, unsigned int mask) mask 214 sound/pci/hda/patch_realtek.c spec->gpio_mask |= mask; mask 215 sound/pci/hda/patch_realtek.c spec->gpio_dir |= mask; mask 216 sound/pci/hda/patch_realtek.c spec->gpio_data |= mask; mask 227 sound/pci/hda/patch_realtek.c static void alc_update_gpio_data(struct hda_codec *codec, unsigned int mask, mask 234 sound/pci/hda/patch_realtek.c spec->gpio_data |= mask; mask 236 sound/pci/hda/patch_realtek.c spec->gpio_data &= ~mask; mask 258 sound/pci/hda/patch_realtek.c unsigned int mask) mask 261 sound/pci/hda/patch_realtek.c alc_setup_gpio(codec, mask); mask 4082 sound/pci/hda/patch_realtek.c static void alc_update_gpio_led(struct hda_codec *codec, unsigned int mask, mask 4089 sound/pci/hda/patch_realtek.c alc_update_gpio_data(codec, mask, !enabled); /* muted -> LED on */ mask 79 sound/pci/hda/patch_si3054.c #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff)) mask 90 sound/pci/hda/patch_si3054.c u16 mask = PRIVATE_MASK(kcontrol->private_value); mask 91 sound/pci/hda/patch_si3054.c uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ; mask 100 sound/pci/hda/patch_si3054.c u16 mask = PRIVATE_MASK(kcontrol->private_value); mask 102 sound/pci/hda/patch_si3054.c SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask); mask 104 sound/pci/hda/patch_si3054.c SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask); mask 108 sound/pci/hda/patch_si3054.c #define SI3054_KCONTROL(kname,reg,mask) { \ mask 115 sound/pci/hda/patch_si3054.c .private_value = PRIVATE_VALUE(reg,mask), \ mask 162 sound/pci/hda/patch_si3054.c .mask = 0, mask 288 sound/pci/hda/patch_sigmatel.c static void stac_gpio_set(struct hda_codec *codec, unsigned int mask, mask 294 sound/pci/hda/patch_sigmatel.c codec_dbg(codec, "%s msk %x dir %x gpio %x\n", __func__, mask, dir_mask, data); mask 302 sound/pci/hda/patch_sigmatel.c gpiomask |= mask; mask 80 sound/pci/ice1712/ews.c unsigned char mask; mask 84 sound/pci/ice1712/ews.c mask = ICE1712_EWX2496_RW; mask 87 sound/pci/ice1712/ews.c mask |= ICE1712_EWX2496_AK4524_CS; /* CS high also */ mask 90 sound/pci/ice1712/ews.c mask |= ICE1712_6FIRE_AK4524_CS_MASK; /* CS high also */ mask 93 sound/pci/ice1712/ews.c snd_ice1712_gpio_write_bits(ice, mask, mask); mask 105 sound/pci/ice1712/ews.c unsigned char mask = 0; mask 108 sound/pci/ice1712/ews.c mask |= ICE1712_EWX2496_SERIAL_CLOCK; /* write SCL */ mask 110 sound/pci/ice1712/ews.c mask |= ICE1712_EWX2496_SERIAL_DATA; /* write SDA */ mask 112 sound/pci/ice1712/ews.c ice->gpio.direction |= mask; mask 114 sound/pci/ice1712/ews.c snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~mask); mask 575 sound/pci/ice1712/ews.c unsigned char mask = kcontrol->private_value & 0xff; mask 578 sound/pci/ice1712/ews.c ucontrol->value.enumerated.item[0] = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & mask ? 1 : 0; mask 586 sound/pci/ice1712/ews.c unsigned char mask = kcontrol->private_value & 0xff; mask 591 sound/pci/ice1712/ews.c nval = ucontrol->value.enumerated.item[0] ? mask : 0; mask 594 sound/pci/ice1712/ews.c nval |= val & ~mask; mask 927 sound/pci/ice1712/ice1712.c .mask = 0, mask 1754 sound/pci/ice1712/ice1712.c unsigned char mask = kcontrol->private_value & 0xff; mask 1759 sound/pci/ice1712/ice1712.c (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert; mask 1768 sound/pci/ice1712/ice1712.c unsigned char mask = kcontrol->private_value & 0xff; mask 1769 sound/pci/ice1712/ice1712.c int invert = (kcontrol->private_value & (1<<24)) ? mask : 0; mask 1774 sound/pci/ice1712/ice1712.c nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert; mask 1777 sound/pci/ice1712/ice1712.c nval |= val & ~mask; mask 442 sound/pci/ice1712/ice1712.h #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \ mask 445 sound/pci/ice1712/ice1712.h .private_value = mask | (invert << 24) } mask 454 sound/pci/ice1712/ice1712.h unsigned int mask, unsigned int bits) mask 458 sound/pci/ice1712/ice1712.h ice->gpio.direction |= mask; mask 461 sound/pci/ice1712/ice1712.h val &= ~mask; mask 462 sound/pci/ice1712/ice1712.h val |= mask & bits; mask 467 sound/pci/ice1712/ice1712.h unsigned int mask) mask 469 sound/pci/ice1712/ice1712.h ice->gpio.direction &= ~mask; mask 471 sound/pci/ice1712/ice1712.h return snd_ice1712_gpio_read(ice) & mask; mask 209 sound/pci/ice1712/ice1724.c unsigned int mask; mask 211 sound/pci/ice1712/ice1724.c mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22)); mask 213 sound/pci/ice1712/ice1724.c mask = 0; mask 214 sound/pci/ice1712/ice1724.c mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK)); mask 215 sound/pci/ice1712/ice1724.c return mask; mask 297 sound/pci/ice1712/ice1724.c u8 mask = inb(ICEREG1724(ice, IRQMASK)); mask 299 sound/pci/ice1712/ice1724.c mask &= ~flag; mask 301 sound/pci/ice1712/ice1724.c mask |= flag; mask 302 sound/pci/ice1712/ice1724.c outb(mask, ICEREG1724(ice, IRQMASK)); mask 519 sound/pci/ice1712/ice1724.c .mask = 0, mask 525 sound/pci/ice1712/ice1724.c .mask = 0, mask 531 sound/pci/ice1712/ice1724.c .mask = 0, mask 1816 sound/pci/ice1712/ice1724.c int invert = (kcontrol->private_value & (1<<24)) ? mask : 0; mask 137 sound/pci/ice1712/juli.c .mask = 0, mask 94 sound/pci/ice1712/maya44.c unsigned short mask, unsigned short val) mask 96 sound/pci/ice1712/maya44.c val |= wm->regs[reg] & ~mask; mask 112 sound/pci/ice1712/maya44.c unsigned short mask; /* value mask */ mask 123 sound/pci/ice1712/maya44.c .mask = 0x7f, mask 131 sound/pci/ice1712/maya44.c .mask = 0xff, mask 139 sound/pci/ice1712/maya44.c .mask = 0xff, mask 209 sound/pci/ice1712/maya44.c vol->mask | vol->update, data); mask 224 sound/pci/ice1712/maya44.c #define COMPOSE_SW_VAL(idx, reg, mask) ((idx) | ((reg) << 8) | ((mask) << 16)) mask 250 sound/pci/ice1712/maya44.c unsigned int mask, val; mask 254 sound/pci/ice1712/maya44.c mask = 1 << idx; mask 255 sound/pci/ice1712/maya44.c wm->switch_bits &= ~mask; mask 258 sound/pci/ice1712/maya44.c wm->switch_bits |= mask; mask 259 sound/pci/ice1712/maya44.c mask = GET_SW_VAL_MASK(kcontrol->private_value); mask 262 sound/pci/ice1712/maya44.c mask, val ? mask : 0); mask 283 sound/pci/ice1712/maya44.c static int maya_set_gpio_bits(struct snd_ice1712 *ice, unsigned int mask, mask 288 sound/pci/ice1712/maya44.c if ((data & mask) == bits) mask 290 sound/pci/ice1712/maya44.c snd_ice1712_gpio_write(ice, (data & ~mask) | bits); mask 315 sound/pci/ice1712/maya44.c unsigned int val, mask; mask 319 sound/pci/ice1712/maya44.c mask = 1 << shift; mask 323 sound/pci/ice1712/maya44.c val = val ? mask : 0; mask 324 sound/pci/ice1712/maya44.c changed = maya_set_gpio_bits(chip->ice, mask, val); mask 658 sound/pci/ice1712/maya44.c .mask = 0 mask 233 sound/pci/ice1712/quartet.c .mask = 0, mask 320 sound/pci/ice1712/quartet.c unsigned char mask, unsigned char value) mask 327 sound/pci/ice1712/quartet.c tmp &= ~mask; mask 96 sound/pci/ice1712/revo.c unsigned int mask, val; mask 103 sound/pci/ice1712/revo.c mask = VT1724_REVO_I2C_CLOCK | VT1724_REVO_I2C_DATA; mask 104 sound/pci/ice1712/revo.c ice->gpio.direction &= ~mask; mask 107 sound/pci/ice1712/revo.c snd_ice1712_gpio_set_mask(ice, ~mask); mask 595 sound/pci/intel8x0.c static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) mask 600 sound/pci/intel8x0.c if (val & mask) mask 1090 sound/pci/intel8x0.c .mask = 0, mask 1100 sound/pci/intel8x0.c .mask = 0, mask 1110 sound/pci/intel8x0.c .mask = 0, mask 2093 sound/pci/intel8x0.c .mask = 0xfff0, mask 2100 sound/pci/intel8x0.c .mask = 0xfff0, mask 2125 sound/pci/intel8x0.c .mask = 0xfff0, mask 2132 sound/pci/intel8x0.c .mask = 0xfff0, mask 2140 sound/pci/intel8x0.c .mask = 0xfff0, mask 627 sound/pci/intel8x0m.c .mask = 0, mask 237 sound/pci/lola/lola_mixer.c static int lola_mixer_set_src_gains(struct lola *chip, unsigned int mask, mask 242 sound/pci/lola/lola_mixer.c if ((chip->mixer.src_mask & mask) != mask) mask 245 sound/pci/lola/lola_mixer.c if (mask & (1 << i)) { mask 250 sound/pci/lola/lola_mixer.c writel(mask, &chip->mixer.array->src_gain_enable); mask 259 sound/pci/lola/lola_mixer.c if (mask & (1 << i)) { mask 292 sound/pci/lola/lola_mixer.c unsigned int mask, unsigned short *gains) mask 297 sound/pci/lola/lola_mixer.c (chip->mixer.src_mask & mask) != mask) mask 300 sound/pci/lola/lola_mixer.c if (mask & (1 << i)) { mask 305 sound/pci/lola/lola_mixer.c writel(mask, &chip->mixer.array->dest_mix_gain_enable[id]); mask 422 sound/pci/lola/lola_mixer.c unsigned int mask = 3U << n; /* handle the stereo case */ mask 424 sound/pci/lola/lola_mixer.c if (!(chip->input_src_caps_mask & mask)) mask 427 sound/pci/lola/lola_mixer.c new_src = (src_mask & mask) != 0; mask 429 sound/pci/lola/lola_mixer.c src_state = (chip->input_src_mask & mask) != 0; mask 626 sound/pci/lola/lola_mixer.c unsigned int mask; mask 628 sound/pci/lola/lola_mixer.c mask = 0; mask 631 sound/pci/lola/lola_mixer.c mask |= 1 << i; mask 632 sound/pci/lola/lola_mixer.c return lola_set_src_config(chip, mask, true); mask 677 sound/pci/lola/lola_mixer.c unsigned int mask, i; mask 679 sound/pci/lola/lola_mixer.c mask = readl(&chip->mixer.array->src_gain_enable); mask 685 sound/pci/lola/lola_mixer.c if (mask & (1 << idx)) mask 759 sound/pci/lola/lola_mixer.c unsigned int dst, mask, i; mask 762 sound/pci/lola/lola_mixer.c mask = readl(&chip->mixer.array->dest_mix_gain_enable[dst]); mask 768 sound/pci/lola/lola_mixer.c if (mask & (1 << dst)) mask 784 sound/pci/lola/lola_mixer.c unsigned int dst, mask; mask 788 sound/pci/lola/lola_mixer.c mask = 0; mask 794 sound/pci/lola/lola_mixer.c mask |= 1 << i; mask 797 sound/pci/lola/lola_mixer.c mask <<= src_ofs; mask 799 sound/pci/lola/lola_mixer.c return lola_mixer_set_dest_gains(chip, dst, mask, gains); mask 393 sound/pci/nm256/nm256.c .mask = 0, mask 189 sound/pci/oxygen/oxygen.h u8 value, u8 mask); mask 191 sound/pci/oxygen/oxygen.h u16 value, u16 mask); mask 193 sound/pci/oxygen/oxygen.h u32 value, u32 mask); mask 200 sound/pci/oxygen/oxygen.h unsigned int index, u16 data, u16 mask); mask 56 sound/pci/oxygen/oxygen_io.c u8 value, u8 mask) mask 59 sound/pci/oxygen/oxygen_io.c tmp &= ~mask; mask 60 sound/pci/oxygen/oxygen_io.c tmp |= value & mask; mask 67 sound/pci/oxygen/oxygen_io.c u16 value, u16 mask) mask 70 sound/pci/oxygen/oxygen_io.c tmp &= ~mask; mask 71 sound/pci/oxygen/oxygen_io.c tmp |= value & mask; mask 78 sound/pci/oxygen/oxygen_io.c u32 value, u32 mask) mask 81 sound/pci/oxygen/oxygen_io.c tmp &= ~mask; mask 82 sound/pci/oxygen/oxygen_io.c tmp |= value & mask; mask 88 sound/pci/oxygen/oxygen_io.c static int oxygen_ac97_wait(struct oxygen *chip, unsigned int mask) mask 98 sound/pci/oxygen/oxygen_io.c status & mask; }), mask 105 sound/pci/oxygen/oxygen_io.c return status & mask ? 0 : -EIO; mask 176 sound/pci/oxygen/oxygen_io.c unsigned int index, u16 data, u16 mask) mask 179 sound/pci/oxygen/oxygen_io.c value &= ~mask; mask 180 sound/pci/oxygen/oxygen_io.c value |= data & mask; mask 569 sound/pci/oxygen/oxygen_pcm.c unsigned int mask = 0; mask 588 sound/pci/oxygen/oxygen_pcm.c mask |= 1 << oxygen_substream_channel(s); mask 596 sound/pci/oxygen/oxygen_pcm.c chip->pcm_running |= mask; mask 598 sound/pci/oxygen/oxygen_pcm.c chip->pcm_running &= ~mask; mask 602 sound/pci/oxygen/oxygen_pcm.c oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask); mask 604 sound/pci/oxygen/oxygen_pcm.c oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask); mask 234 sound/pci/oxygen/xonar_dg.c unsigned int mask) mask 237 sound/pci/oxygen/xonar_dg.c return (value << (shift_to - shift_from)) & mask; mask 239 sound/pci/oxygen/xonar_dg.c return (value >> (shift_from - shift_to)) & mask; mask 612 sound/pci/oxygen/xonar_wm87x6.c u16 mask, reg_value; mask 626 sound/pci/oxygen/xonar_wm87x6.c mask = (ctl->private_value >> 16) & 0xf; mask 634 sound/pci/oxygen/xonar_wm87x6.c reg_value &= ~(mask << shift); mask 976 sound/pci/oxygen/xonar_wm87x6.c #define _WM8776_FIELD_CTL(xname, reg, shift, initval, min, max, mask, flags) \ mask 980 sound/pci/oxygen/xonar_wm87x6.c ((mask) << 16) | ((shift) << 20) | ((reg) << 24) | (flags) mask 981 sound/pci/oxygen/xonar_wm87x6.c #define WM8776_FIELD_CTL_ENUM(xname, reg, shift, init, min, max, mask, flags) {\ mask 983 sound/pci/oxygen/xonar_wm87x6.c reg, shift, init, min, max, mask, flags), \ mask 114 sound/pci/pcxhr/pcxhr_core.c unsigned char mask, unsigned char bit, int time, mask 121 sound/pci/pcxhr/pcxhr_core.c if ((*read & mask) == bit) { mask 132 sound/pci/pcxhr/pcxhr_core.c reg, mask, *read); mask 274 sound/pci/pcxhr/pcxhr_core.c unsigned char mask; mask 296 sound/pci/pcxhr/pcxhr_core.c mask = 0x80; mask 297 sound/pci/pcxhr/pcxhr_core.c while (mask) { mask 300 sound/pci/pcxhr/pcxhr_core.c if (data & mask) mask 305 sound/pci/pcxhr/pcxhr_core.c mask >>= 1; mask 959 sound/pci/pcxhr/pcxhr_core.c int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask, mask 966 sound/pci/pcxhr/pcxhr_core.c if ((mgr->io_num_reg_cont & mask) == value) { mask 969 sound/pci/pcxhr/pcxhr_core.c mask, value); mask 977 sound/pci/pcxhr/pcxhr_core.c rmh.cmd[1] = mask; mask 982 sound/pci/pcxhr/pcxhr_core.c mgr->io_num_reg_cont &= ~mask; mask 140 sound/pci/pcxhr/pcxhr_core.h int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask, mask 208 sound/pci/pcxhr/pcxhr_mix22.c unsigned short mask = 0x8000; mask 212 sound/pci/pcxhr/pcxhr_mix22.c while (mask) { mask 214 sound/pci/pcxhr/pcxhr_mix22.c data & mask ? PCXHR_DATA_CODEC : 0); mask 215 sound/pci/pcxhr/pcxhr_mix22.c mask >>= 1; mask 408 sound/pci/pcxhr/pcxhr_mix22.c unsigned char mask, reg; mask 412 sound/pci/pcxhr/pcxhr_mix22.c mask = (PCXHR_SUER_CLOCK_PRESENT_MASK | mask 418 sound/pci/pcxhr/pcxhr_mix22.c mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK | mask 429 sound/pci/pcxhr/pcxhr_mix22.c if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) { mask 628 sound/pci/pcxhr/pcxhr_mix22.c unsigned char mask = chip->mgr->board_has_aes1 ? mask 634 sound/pci/pcxhr/pcxhr_mix22.c if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask) mask 574 sound/pci/pcxhr/pcxhr_mixer.c unsigned int mask, reg; mask 579 sound/pci/pcxhr/pcxhr_mixer.c case 0 : mask = PCXHR_SOURCE_AUDIO01_UER; codec = CS8420_01_CS; break; mask 580 sound/pci/pcxhr/pcxhr_mixer.c case 1 : mask = PCXHR_SOURCE_AUDIO23_UER; codec = CS8420_23_CS; break; mask 581 sound/pci/pcxhr/pcxhr_mixer.c case 2 : mask = PCXHR_SOURCE_AUDIO45_UER; codec = CS8420_45_CS; break; mask 582 sound/pci/pcxhr/pcxhr_mixer.c case 3 : mask = PCXHR_SOURCE_AUDIO67_UER; codec = CS8420_67_CS; break; mask 586 sound/pci/pcxhr/pcxhr_mixer.c reg = mask; /* audio source from digital plug */ mask 591 sound/pci/pcxhr/pcxhr_mixer.c pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed); mask 799 sound/pci/riptide/riptide.c static int writearm(struct cmdif *cif, u32 addr, u32 data, u32 mask) mask 806 sound/pci/riptide/riptide.c rptr.retlongs[0] &= (~mask); mask 816 sound/pci/riptide/riptide.c rptr.retlongs[0] &= ~mask; mask 818 sound/pci/riptide/riptide.c snd_printdd("send arm 0x%x 0x%x 0x%x return %d\n", addr, data, mask, mask 834 sound/pci/rme32.c .mask = 0 mask 1157 sound/pci/rme96.c .mask = 0 mask 4259 sound/pci/rme9652/hdsp.c .mask = 0 mask 4267 sound/pci/rme9652/hdsp.c .mask = 0 mask 3959 sound/pci/rme9652/hdspm.c static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) mask 3964 sound/pci/rme9652/hdspm.c return (status & mask) ? 1 : 0; mask 6049 sound/pci/rme9652/hdspm.c .mask = 0 mask 624 sound/pci/rme9652/rme9652.c static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff) mask 627 sound/pci/rme9652/rme9652.c rme9652->control_register |= mask; mask 629 sound/pci/rme9652/rme9652.c rme9652->control_register &= ~mask; mask 636 sound/pci/rme9652/rme9652.c long mask; mask 639 sound/pci/rme9652/rme9652.c for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) { mask 640 sound/pci/rme9652/rme9652.c if (val & mask) mask 652 sound/pci/rme9652/rme9652.c long mask; mask 658 sound/pci/rme9652/rme9652.c for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) { mask 661 sound/pci/rme9652/rme9652.c val |= mask; mask 2221 sound/pci/rme9652/rme9652.c .mask = 0 mask 449 sound/pci/sonicvibes.c unsigned char mask, mask 456 sound/pci/sonicvibes.c if (mask) { mask 460 sound/pci/sonicvibes.c sonic->format = (sonic->format & mask) | value; mask 944 sound/pci/sonicvibes.c #define SONICVIBES_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 948 sound/pci/sonicvibes.c .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } mask 952 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 954 sound/pci/sonicvibes.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 957 sound/pci/sonicvibes.c uinfo->value.integer.max = mask; mask 966 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 970 sound/pci/sonicvibes.c ucontrol->value.integer.value[0] = (snd_sonicvibes_in1(sonic, reg)>> shift) & mask; mask 973 sound/pci/sonicvibes.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 982 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 987 sound/pci/sonicvibes.c val = (ucontrol->value.integer.value[0] & mask); mask 989 sound/pci/sonicvibes.c val = mask - val; mask 993 sound/pci/sonicvibes.c val = (oval & ~(mask << shift)) | val; mask 1000 sound/pci/sonicvibes.c #define SONICVIBES_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 1004 sound/pci/sonicvibes.c .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } mask 1008 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1010 sound/pci/sonicvibes.c uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; mask 1013 sound/pci/sonicvibes.c uinfo->value.integer.max = mask; mask 1024 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1028 sound/pci/sonicvibes.c ucontrol->value.integer.value[0] = (snd_sonicvibes_in1(sonic, left_reg) >> shift_left) & mask; mask 1029 sound/pci/sonicvibes.c ucontrol->value.integer.value[1] = (snd_sonicvibes_in1(sonic, right_reg) >> shift_right) & mask; mask 1032 sound/pci/sonicvibes.c ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; mask 1033 sound/pci/sonicvibes.c ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1]; mask 1045 sound/pci/sonicvibes.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1050 sound/pci/sonicvibes.c val1 = ucontrol->value.integer.value[0] & mask; mask 1051 sound/pci/sonicvibes.c val2 = ucontrol->value.integer.value[1] & mask; mask 1053 sound/pci/sonicvibes.c val1 = mask - val1; mask 1054 sound/pci/sonicvibes.c val2 = mask - val2; mask 1061 sound/pci/sonicvibes.c val1 = (oval1 & ~(mask << shift_left)) | val1; mask 1062 sound/pci/sonicvibes.c val2 = (oval2 & ~(mask << shift_right)) | val2; mask 289 sound/pci/trident/trident_main.c unsigned int mask = 1 << (voice & 0x1f); mask 292 sound/pci/trident/trident_main.c outl(mask, TRID_REG(trident, reg)); mask 313 sound/pci/trident/trident_main.c unsigned int mask = 1 << (voice & 0x1f); mask 316 sound/pci/trident/trident_main.c outl(mask, TRID_REG(trident, reg)); mask 3706 sound/pci/trident/trident_main.c unsigned int audio_int, chn_int, stimer, channel, mask, tmp; mask 3726 sound/pci/trident/trident_main.c mask = 1 << (channel&0x1f); mask 3727 sound/pci/trident/trident_main.c if ((chn_int & mask) == 0) mask 3731 sound/pci/trident/trident_main.c outl(mask, TRID_REG(trident, T4D_STOP_B)); mask 3876 sound/pci/trident/trident_main.c unsigned int i, val, mask[2] = { 0, 0 }; mask 3881 sound/pci/trident/trident_main.c mask[i >> 5] |= 1 << (i & 0x1f); mask 3882 sound/pci/trident/trident_main.c if (mask[0]) { mask 3883 sound/pci/trident/trident_main.c outl(mask[0], TRID_REG(trident, T4D_STOP_A)); mask 3885 sound/pci/trident/trident_main.c outl(val & ~mask[0], TRID_REG(trident, T4D_AINTEN_A)); mask 3887 sound/pci/trident/trident_main.c if (mask[1]) { mask 3888 sound/pci/trident/trident_main.c outl(mask[1], TRID_REG(trident, T4D_STOP_B)); mask 3890 sound/pci/trident/trident_main.c outl(val & ~mask[1], TRID_REG(trident, T4D_AINTEN_B)); mask 1283 sound/pci/via82xx.c .mask = 0, mask 739 sound/pci/via82xx_modem.c .mask = 0, mask 1455 sound/pci/ymfpci/ymfpci_main.c unsigned int mask = 1; mask 1463 sound/pci/ymfpci/ymfpci_main.c (snd_ymfpci_readl(chip, reg) >> shift) & mask; mask 1473 sound/pci/ymfpci/ymfpci_main.c unsigned int mask = 1; mask 1482 sound/pci/ymfpci/ymfpci_main.c val = (ucontrol->value.integer.value[0] & mask); mask 1486 sound/pci/ymfpci/ymfpci_main.c val = (oval & ~(mask << shift)) | val; mask 1520 sound/pci/ymfpci/ymfpci_main.c unsigned int shift_left = 0, shift_right = 16, mask = 16383; mask 1528 sound/pci/ymfpci/ymfpci_main.c ucontrol->value.integer.value[0] = (val >> shift_left) & mask; mask 1529 sound/pci/ymfpci/ymfpci_main.c ucontrol->value.integer.value[1] = (val >> shift_right) & mask; mask 1537 sound/pci/ymfpci/ymfpci_main.c unsigned int shift_left = 0, shift_right = 16, mask = 16383; mask 1543 sound/pci/ymfpci/ymfpci_main.c val1 = ucontrol->value.integer.value[0] & mask; mask 1544 sound/pci/ymfpci/ymfpci_main.c val2 = ucontrol->value.integer.value[1] & mask; mask 1549 sound/pci/ymfpci/ymfpci_main.c val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2; mask 39 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c unsigned short mask, val, tmp; mask 51 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c mask = 0; mask 59 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c mask = PDAUDIOCF_RECORD; mask 77 sound/pcmcia/pdaudiocf/pdaudiocf_pcm.c tmp &= ~mask; mask 224 sound/ppc/awacs.c int mask = 1 << shift; mask 229 sound/ppc/awacs.c val = chip->awacs_reg[reg] & ~mask; mask 231 sound/ppc/awacs.c val |= mask; mask 70 sound/ppc/snd_ps3.c static inline void update_mask_reg(unsigned int reg, u32 mask, u32 or_val) mask 72 sound/ppc/snd_ps3.c u32 newval = (read_reg(reg) & mask) | or_val; mask 61 sound/soc/adi/axi-i2s.c unsigned int mask, val; mask 64 sound/soc/adi/axi-i2s.c mask = AXI_I2S_CTRL_RX_EN; mask 66 sound/soc/adi/axi-i2s.c mask = AXI_I2S_CTRL_TX_EN; mask 72 sound/soc/adi/axi-i2s.c val = mask; mask 83 sound/soc/adi/axi-i2s.c regmap_update_bits(i2s->regmap, AXI_I2S_REG_CTRL, mask, val); mask 110 sound/soc/adi/axi-i2s.c uint32_t mask; mask 114 sound/soc/adi/axi-i2s.c mask = AXI_I2S_RESET_RX_FIFO; mask 116 sound/soc/adi/axi-i2s.c mask = AXI_I2S_RESET_TX_FIFO; mask 118 sound/soc/adi/axi-i2s.c regmap_write(i2s->regmap, AXI_I2S_REG_RESET, mask); mask 132 sound/soc/amd/acp-da7219-max98357a.c .mask = 0, mask 138 sound/soc/amd/acp-da7219-max98357a.c .mask = 0, mask 81 sound/soc/amd/raven/acp3x-pcm-dma.c u16 val, mask; mask 86 sound/soc/amd/raven/acp3x-pcm-dma.c mask = ACP3x_POWER_ON; mask 89 sound/soc/amd/raven/acp3x-pcm-dma.c mask = ACP3x_POWER_OFF; mask 96 sound/soc/amd/raven/acp3x-pcm-dma.c if ((val & ACP3x_POWER_OFF_IN_PROGRESS) == mask) mask 253 sound/soc/atmel/atmel-classd.c u32 mask, val; mask 255 sound/soc/atmel/atmel-classd.c mask = CLASSD_MR_PWMTYP_MASK; mask 258 sound/soc/atmel/atmel-classd.c mask |= CLASSD_MR_NON_OVERLAP_MASK; mask 263 sound/soc/atmel/atmel-classd.c mask |= CLASSD_MR_NOVR_VAL_MASK; mask 291 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); mask 334 sound/soc/atmel/atmel-classd.c u32 mask, val; mask 336 sound/soc/atmel/atmel-classd.c mask = CLASSD_MR_LMUTE_MASK | CLASSD_MR_RMUTE_MASK; mask 339 sound/soc/atmel/atmel-classd.c val = mask; mask 343 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); mask 385 sound/soc/atmel/atmel-classd.c u32 mask, val; mask 410 sound/soc/atmel/atmel-classd.c mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK; mask 414 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val); mask 446 sound/soc/atmel/atmel-classd.c u32 mask, val; mask 448 sound/soc/atmel/atmel-classd.c mask = CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK; mask 454 sound/soc/atmel/atmel-classd.c val = mask; mask 466 sound/soc/atmel/atmel-classd.c snd_soc_component_update_bits(component, CLASSD_MR, mask, val); mask 208 sound/soc/atmel/atmel-i2s.c unsigned int sr, imr, pending, ch, mask; mask 219 sound/soc/atmel/atmel-i2s.c mask = ATMEL_I2SC_SR_RXOR; mask 223 sound/soc/atmel/atmel-i2s.c mask |= ATMEL_I2SC_SR_RXORCH(ch); mask 228 sound/soc/atmel/atmel-i2s.c regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); mask 233 sound/soc/atmel/atmel-i2s.c mask = ATMEL_I2SC_SR_TXUR; mask 237 sound/soc/atmel/atmel-i2s.c mask |= ATMEL_I2SC_SR_TXURCH(ch); mask 242 sound/soc/atmel/atmel-i2s.c regmap_write(dev->regmap, ATMEL_I2SC_SCR, mask); mask 61 sound/soc/atmel/atmel-pcm-dma.c if (ssc_sr & prtd->mask->ssc_error) { mask 69 sound/soc/atmel/atmel-pcm-dma.c ssc_writex(prtd->ssc->regs, SSC_CR, prtd->mask->ssc_disable); mask 159 sound/soc/atmel/atmel-pcm-pdc.c if (ssc_sr & params->mask->ssc_endbuf) { mask 167 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_disable); mask 177 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_enable); mask 180 sound/soc/atmel/atmel-pcm-pdc.c if (ssc_sr & params->mask->ssc_endx) { mask 235 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_disable); mask 248 sound/soc/atmel/atmel-pcm-pdc.c params->mask->ssc_endx | params->mask->ssc_endbuf); mask 250 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_disable); mask 291 sound/soc/atmel/atmel-pcm-pdc.c params->mask->ssc_endx | params->mask->ssc_endbuf); mask 293 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_enable); mask 304 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_disable); mask 310 sound/soc/atmel/atmel-pcm-pdc.c params->mask->pdc_enable); mask 62 sound/soc/atmel/atmel-pcm.h struct atmel_ssc_mask *mask; /* SSC & PDC status bits */ mask 86 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_tx_mask, mask 91 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_rx_mask, mask 96 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_tx_mask, mask 101 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_rx_mask, mask 106 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_tx_mask, mask 111 sound/soc/atmel/atmel_ssc_dai.c .mask = &ssc_rx_mask, mask 161 sound/soc/atmel/atmel_ssc_dai.c ssc_substream_mask = (dma_params->mask->ssc_endx | mask 162 sound/soc/atmel/atmel_ssc_dai.c dma_params->mask->ssc_endbuf); mask 724 sound/soc/atmel/atmel_ssc_dai.c ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); mask 725 sound/soc/atmel/atmel_ssc_dai.c ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); mask 752 sound/soc/atmel/atmel_ssc_dai.c ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); mask 755 sound/soc/atmel/atmel_ssc_dai.c ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); mask 320 sound/soc/bcm/bcm2835-i2s.c unsigned int mask, unsigned int width, mask 323 sound/soc/bcm/bcm2835-i2s.c *ch1_pos = bcm2835_i2s_convert_slot((ffs(mask) - 1), odd_offset) mask 325 sound/soc/bcm/bcm2835-i2s.c *ch2_pos = bcm2835_i2s_convert_slot((fls(mask) - 1), odd_offset) mask 645 sound/soc/bcm/bcm2835-i2s.c uint32_t mask; mask 648 sound/soc/bcm/bcm2835-i2s.c mask = BCM2835_I2S_RXON; mask 650 sound/soc/bcm/bcm2835-i2s.c mask = BCM2835_I2S_TXON; mask 653 sound/soc/bcm/bcm2835-i2s.c BCM2835_I2S_CS_A_REG, mask, 0); mask 664 sound/soc/bcm/bcm2835-i2s.c uint32_t mask; mask 673 sound/soc/bcm/bcm2835-i2s.c mask = BCM2835_I2S_RXON; mask 675 sound/soc/bcm/bcm2835-i2s.c mask = BCM2835_I2S_TXON; mask 678 sound/soc/bcm/bcm2835-i2s.c BCM2835_I2S_CS_A_REG, mask, mask); mask 547 sound/soc/bcm/cygnus-ssp.c u32 mask = 0xf; mask 595 sound/soc/bcm/cygnus-ssp.c value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32); mask 627 sound/soc/bcm/cygnus-ssp.c u32 mask = 0x1f; mask 676 sound/soc/bcm/cygnus-ssp.c value &= ~(mask << BF_SRC_CFGX_BIT_RES); mask 842 sound/soc/bcm/cygnus-ssp.c u32 mask; mask 915 sound/soc/bcm/cygnus-ssp.c mask = BIT(AUD_MISC_SEROUT_LRCK_OE) mask 918 sound/soc/bcm/cygnus-ssp.c mask = mask << (aio->portnum * 4); mask 921 sound/soc/bcm/cygnus-ssp.c val |= mask; mask 924 sound/soc/bcm/cygnus-ssp.c val &= ~mask; mask 227 sound/soc/cirrus/ep93xx-ac97.c unsigned status, mask; mask 235 sound/soc/cirrus/ep93xx-ac97.c mask = ep93xx_ac97_read_reg(info, AC97IM); mask 236 sound/soc/cirrus/ep93xx-ac97.c mask &= ~status; mask 237 sound/soc/cirrus/ep93xx-ac97.c ep93xx_ac97_write_reg(info, AC97IM, mask); mask 334 sound/soc/codecs/88pm860x-codec.c unsigned int mask = (1 << fls(max)) - 1; mask 338 sound/soc/codecs/88pm860x-codec.c ucontrol->value.integer.value[0] = (max - val) & mask; mask 339 sound/soc/codecs/88pm860x-codec.c ucontrol->value.integer.value[1] = (max - val2) & mask; mask 354 sound/soc/codecs/88pm860x-codec.c unsigned int mask = (1 << fls(max)) - 1; mask 358 sound/soc/codecs/88pm860x-codec.c val_mask = mask << shift; mask 359 sound/soc/codecs/88pm860x-codec.c val = ((max - ucontrol->value.integer.value[0]) & mask); mask 360 sound/soc/codecs/88pm860x-codec.c val2 = ((max - ucontrol->value.integer.value[1]) & mask); mask 908 sound/soc/codecs/88pm860x-codec.c int data = 0, mask = MUTE_LEFT | MUTE_RIGHT; mask 911 sound/soc/codecs/88pm860x-codec.c data = mask; mask 912 sound/soc/codecs/88pm860x-codec.c snd_soc_component_update_bits(component, PM860X_DAC_OFFSET, mask, data); mask 923 sound/soc/codecs/88pm860x-codec.c unsigned char inf = 0, mask = 0; mask 936 sound/soc/codecs/88pm860x-codec.c mask |= PCM_INF2_18WL; mask 937 sound/soc/codecs/88pm860x-codec.c snd_soc_component_update_bits(component, PM860X_PCM_IFACE_2, mask, inf); mask 966 sound/soc/codecs/88pm860x-codec.c unsigned char inf = 0, mask = 0; mask 969 sound/soc/codecs/88pm860x-codec.c mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER; mask 994 sound/soc/codecs/88pm860x-codec.c mask |= PCM_MODE_MASK; mask 997 sound/soc/codecs/88pm860x-codec.c snd_soc_component_update_bits(component, PM860X_PCM_IFACE_2, mask, inf); mask 1071 sound/soc/codecs/88pm860x-codec.c unsigned char inf = 0, mask = 0; mask 1073 sound/soc/codecs/88pm860x-codec.c mask |= PCM_INF2_BCLK | PCM_INF2_FS | PCM_INF2_MASTER; mask 1100 sound/soc/codecs/88pm860x-codec.c mask |= PCM_MODE_MASK; mask 1101 sound/soc/codecs/88pm860x-codec.c snd_soc_component_update_bits(component, PM860X_I2S_IFACE_2, mask, inf); mask 1205 sound/soc/codecs/88pm860x-codec.c int mask; mask 1209 sound/soc/codecs/88pm860x-codec.c mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt mask 1236 sound/soc/codecs/88pm860x-codec.c snd_soc_jack_report(pm860x->det.hp_jack, report, mask); mask 1242 sound/soc/codecs/88pm860x-codec.c report, mask); mask 2039 sound/soc/codecs/ab8500-codec.c unsigned int mask, val; mask 2042 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0DEL); mask 2060 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); mask 2069 sound/soc/codecs/ab8500-codec.c unsigned int mask; mask 2072 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) | mask 2094 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); mask 2101 sound/soc/codecs/ab8500-codec.c unsigned int mask; mask 2108 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) | mask 2137 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF3, mask, val); mask 2150 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) | mask 2216 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); mask 2226 sound/soc/codecs/ab8500-codec.c unsigned int val, mask, slot, slots_active; mask 2228 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF2_IF0WL0) | mask 2253 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF2, mask, val); mask 2257 sound/soc/codecs/ab8500-codec.c mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) | mask 2279 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DIGIFCONF1, mask, val); mask 2286 sound/soc/codecs/ab8500-codec.c mask = AB8500_DASLOTCONFX_SLTODAX_MASK; mask 2298 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); mask 2299 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); mask 2300 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); mask 2301 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); mask 2305 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF1, mask, slot); mask 2306 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF3, mask, slot); mask 2308 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF2, mask, slot); mask 2309 sound/soc/codecs/ab8500-codec.c snd_soc_component_update_bits(component, AB8500_DASLOTCONF4, mask, slot); mask 368 sound/soc/codecs/adau1701.c unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK; mask 397 sound/soc/codecs/adau1701.c mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK; mask 400 sound/soc/codecs/adau1701.c regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val); mask 553 sound/soc/codecs/adau1701.c unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD; mask 564 sound/soc/codecs/adau1701.c ADAU1701_AUXNPOW, mask, 0x00); mask 569 sound/soc/codecs/adau1701.c ADAU1701_AUXNPOW, mask, mask); mask 579 sound/soc/codecs/adau1701.c unsigned int mask = ADAU1701_DSPCTRL_DAM; mask 586 sound/soc/codecs/adau1701.c val = mask; mask 588 sound/soc/codecs/adau1701.c regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val); mask 220 sound/soc/codecs/adau17x1.c update.mask = 0xff; mask 796 sound/soc/codecs/adau1977.c unsigned int mask = 0; mask 822 sound/soc/codecs/adau1977.c mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000; mask 824 sound/soc/codecs/adau1977.c mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100; mask 826 sound/soc/codecs/adau1977.c mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000; mask 828 sound/soc/codecs/adau1977.c if (mask == 0) mask 831 sound/soc/codecs/adau1977.c mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK; mask 839 sound/soc/codecs/adau1977.c adau1977->constraints.mask = mask; mask 577 sound/soc/codecs/adav80x.c unsigned int mask; mask 589 sound/soc/codecs/adav80x.c mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id); mask 593 sound/soc/codecs/adav80x.c mask, mask); mask 597 sound/soc/codecs/adav80x.c mask, 0); mask 701 sound/soc/codecs/adav80x.c unsigned int mask = ADAV80X_DAC_CTRL1_PD; mask 709 sound/soc/codecs/adav80x.c regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, mask 713 sound/soc/codecs/adav80x.c regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask, mask 714 sound/soc/codecs/adav80x.c mask); mask 275 sound/soc/codecs/ak4613.c constraint->mask = 0; mask 296 sound/soc/codecs/arizona.c unsigned int val, mask; mask 349 sound/soc/codecs/arizona.c mask = ARIZONA_IN1_DMIC_SUP_MASK | mask 356 sound/soc/codecs/arizona.c mask = ARIZONA_IN1_DMIC_SUP_MASK | mask 364 sound/soc/codecs/arizona.c mask, val); mask 1077 sound/soc/codecs/arizona.c unsigned int mask = 1 << w->shift; mask 1082 sound/soc/codecs/arizona.c val = mask; mask 1095 sound/soc/codecs/arizona.c priv->arizona->hp_ena &= ~mask; mask 1103 sound/soc/codecs/arizona.c mask, val); mask 1371 sound/soc/codecs/arizona.c unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK; mask 1380 sound/soc/codecs/arizona.c mask |= ARIZONA_SYSCLK_FRAC; mask 1437 sound/soc/codecs/arizona.c return regmap_update_bits(arizona->regmap, reg, mask, val); mask 1638 sound/soc/codecs/arizona.c dai_priv->constraint.mask = ARIZONA_RATE_MASK; mask 1640 sound/soc/codecs/arizona.c dai_priv->constraint.mask = ARIZONA_44K1_RATE_MASK; mask 1642 sound/soc/codecs/arizona.c dai_priv->constraint.mask = ARIZONA_48K_RATE_MASK; mask 1973 sound/soc/codecs/arizona.c int channels, unsigned int mask) mask 1981 sound/soc/codecs/arizona.c slot = ffs(mask) - 1; mask 1987 sound/soc/codecs/arizona.c mask &= ~(1 << slot); mask 1990 sound/soc/codecs/arizona.c if (mask) mask 213 sound/soc/codecs/arizona.h .num_regs = 20, .mask = ~ARIZONA_EQ1_B1_MODE }) } mask 219 sound/soc/codecs/cpcap.c u16 mask; mask 409 sound/soc/codecs/cpcap.c unsigned int mask = BIT(e->shift_l); mask 415 sound/soc/codecs/cpcap.c reg_voice = mask; mask 418 sound/soc/codecs/cpcap.c reg_hifi = mask; mask 421 sound/soc/codecs/cpcap.c reg_ext = mask; mask 428 sound/soc/codecs/cpcap.c mask, reg_voice); mask 432 sound/soc/codecs/cpcap.c mask, reg_hifi); mask 436 sound/soc/codecs/cpcap.c mask, reg_ext); mask 450 sound/soc/codecs/cpcap.c int regval, mask; mask 457 sound/soc/codecs/cpcap.c mask = 0; mask 458 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC1_MUX); mask 459 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_HS_MIC_MUX); mask 460 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); mask 461 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_R_ENCODE); mask 463 sound/soc/codecs/cpcap.c switch (regval & mask) { mask 493 sound/soc/codecs/cpcap.c int regval = 0, mask; mask 496 sound/soc/codecs/cpcap.c mask = 0; mask 497 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC1_MUX); mask 498 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_HS_MIC_MUX); mask 499 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_EMU_MIC_MUX); mask 500 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_R_ENCODE); mask 520 sound/soc/codecs/cpcap.c mask, regval); mask 534 sound/soc/codecs/cpcap.c int regval, mask; mask 541 sound/soc/codecs/cpcap.c mask = 0; mask 542 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC2_MUX); mask 543 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_L_ENCODE); mask 545 sound/soc/codecs/cpcap.c switch (regval & mask) { mask 569 sound/soc/codecs/cpcap.c int regval = 0, mask; mask 572 sound/soc/codecs/cpcap.c mask = 0; mask 573 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_MIC2_MUX); mask 574 sound/soc/codecs/cpcap.c mask |= BIT(CPCAP_BIT_RX_L_ENCODE); mask 588 sound/soc/codecs/cpcap.c mask, regval); mask 955 sound/soc/codecs/cpcap.c u16 mask, val; mask 988 sound/soc/codecs/cpcap.c mask = BIT(CPCAP_BIT_CDC_PLL_SEL); mask 991 sound/soc/codecs/cpcap.c mask, val); mask 1144 sound/soc/codecs/cpcap.c static const u16 mask = mask 1216 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); mask 1224 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW); mask 1233 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); mask 1254 sound/soc/codecs/cpcap.c u16 val, mask; mask 1265 sound/soc/codecs/cpcap.c mask = 0x0000; mask 1266 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC1_RX_TIMESLOT0; mask 1267 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC1_RX_TIMESLOT1; mask 1268 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC1_RX_TIMESLOT2; mask 1269 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC2_TIMESLOT0; mask 1270 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC2_TIMESLOT1; mask 1271 sound/soc/codecs/cpcap.c mask |= CPCAP_BIT_MIC2_TIMESLOT2; mask 1275 sound/soc/codecs/cpcap.c err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val); mask 1299 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) | mask 1365 sound/soc/codecs/cpcap.c err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val); mask 1378 sound/soc/codecs/cpcap.c static const u16 mask = BIT(CPCAP_BIT_CDC_SW); mask 1387 sound/soc/codecs/cpcap.c return regmap_update_bits(cpcap->regmap, reg, mask, val); mask 1474 sound/soc/codecs/cpcap.c cpcap_default_regs[i].mask, mask 271 sound/soc/codecs/cs35l33.c unsigned int mask = CS35L33_SDOUT_3ST_I2S | CS35L33_PDN_TDM; mask 301 sound/soc/codecs/cs35l33.c mask, val); mask 1304 sound/soc/codecs/cs42l42.c u8 mask; mask 1351 sound/soc/codecs/cs42l42.c irq_params_table[i].mask; mask 1366 sound/soc/codecs/cs42l42.c if ((~masks[5]) & irq_params_table[5].mask) { mask 1376 sound/soc/codecs/cs42l42.c if ((~masks[11]) & irq_params_table[11].mask) { mask 1401 sound/soc/codecs/cs42l42.c if ((~masks[7]) & irq_params_table[7].mask) { mask 487 sound/soc/codecs/cs42l51.c int mask = CS42L51_DAC_OUT_CTL_DACA_MUTE|CS42L51_DAC_OUT_CTL_DACB_MUTE; mask 492 sound/soc/codecs/cs42l51.c reg |= mask; mask 494 sound/soc/codecs/cs42l51.c reg &= ~mask; mask 270 sound/soc/codecs/cs42xx8.c u32 i, val, mask; mask 339 sound/soc/codecs/cs42xx8.c mask = CS42XX8_FUNCMOD_MFREQ_MASK; mask 343 sound/soc/codecs/cs42xx8.c CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask, mask 1161 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ mask 1168 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ mask 1175 sound/soc/codecs/cx2072x.c .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \ mask 1182 sound/soc/codecs/cx2072x.c .reg = wreg, .shift = wshift, .mask = wmask, \ mask 455 sound/soc/codecs/da7218.c unsigned int mask = (mc->max << lshift) | (mc->max << rshift); mask 462 sound/soc/codecs/da7218.c da7218->alc_en &= ~mask; mask 524 sound/soc/codecs/da7218.c unsigned int mask = (mixer_ctrl->max << lshift) | mask 526 sound/soc/codecs/da7218.c da7218->mic_lvl_det_en &= ~mask; mask 1350 sound/soc/codecs/da7218.c u8 mask; mask 1354 sound/soc/codecs/da7218.c mask = (1 << DA7218_LVL_DET_EN_CHAN1L_SHIFT); mask 1357 sound/soc/codecs/da7218.c mask = (1 << DA7218_LVL_DET_EN_CHAN1R_SHIFT); mask 1360 sound/soc/codecs/da7218.c mask = (1 << DA7218_LVL_DET_EN_CHAN2L_SHIFT); mask 1363 sound/soc/codecs/da7218.c mask = (1 << DA7218_LVL_DET_EN_CHAN2R_SHIFT); mask 1371 sound/soc/codecs/da7218.c da7218->in_filt_en |= mask; mask 1377 sound/soc/codecs/da7218.c if (mask & da7218->mic_lvl_det_en) mask 1381 sound/soc/codecs/da7218.c da7218->in_filt_en &= ~mask; mask 350 sound/soc/codecs/da7219-aad.c int i, report = 0, mask = 0; mask 375 sound/soc/codecs/da7219-aad.c mask |= SND_JACK_MECHANICAL; mask 396 sound/soc/codecs/da7219-aad.c mask |= SND_JACK_HEADSET | SND_JACK_LINEOUT; mask 410 sound/soc/codecs/da7219-aad.c mask |= SND_JACK_BTN_0 >> i; mask 413 sound/soc/codecs/da7219-aad.c snd_soc_jack_report(da7219_aad->jack, report, mask); mask 420 sound/soc/codecs/da7219-aad.c mask |= SND_JACK_BTN_0 >> i; mask 428 sound/soc/codecs/da7219-aad.c mask |= DA7219_AAD_REPORT_ALL_MASK; mask 453 sound/soc/codecs/da7219-aad.c snd_soc_jack_report(da7219_aad->jack, report, mask); mask 716 sound/soc/codecs/da7219-aad.c u8 cfg, mask; mask 746 sound/soc/codecs/da7219-aad.c mask = 0; mask 754 sound/soc/codecs/da7219-aad.c mask |= DA7219_MIC_DET_THRESH_MASK; mask 756 sound/soc/codecs/da7219-aad.c snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_1, mask, cfg); mask 759 sound/soc/codecs/da7219-aad.c mask = 0; mask 771 sound/soc/codecs/da7219-aad.c mask |= DA7219_JACKDET_DEBOUNCE_MASK; mask 780 sound/soc/codecs/da7219-aad.c mask |= DA7219_JACK_DETECT_RATE_MASK; mask 789 sound/soc/codecs/da7219-aad.c mask |= DA7219_JACKDET_REM_DEB_MASK; mask 791 sound/soc/codecs/da7219-aad.c snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_2, mask, cfg); mask 803 sound/soc/codecs/da7219-aad.c mask = 0; mask 811 sound/soc/codecs/da7219-aad.c mask |= DA7219_BUTTON_AVERAGE_MASK; mask 820 sound/soc/codecs/da7219-aad.c mask |= DA7219_ADC_1_BIT_REPEAT_MASK; mask 822 sound/soc/codecs/da7219-aad.c snd_soc_component_update_bits(component, DA7219_ACCDET_CONFIG_7, mask, cfg); mask 891 sound/soc/codecs/da7219-aad.c u8 mask[DA7219_AAD_IRQ_REG_MAX]; mask 924 sound/soc/codecs/da7219-aad.c memset(mask, 0, DA7219_AAD_IRQ_REG_MAX); mask 926 sound/soc/codecs/da7219-aad.c &mask, DA7219_AAD_IRQ_REG_MAX); mask 936 sound/soc/codecs/da7219-aad.c u8 mask[DA7219_AAD_IRQ_REG_MAX]; mask 939 sound/soc/codecs/da7219-aad.c memset(mask, DA7219_BYTE_MASK, DA7219_AAD_IRQ_REG_MAX); mask 941 sound/soc/codecs/da7219-aad.c mask, DA7219_AAD_IRQ_REG_MAX); mask 407 sound/soc/codecs/es8316.c u8 mask; mask 437 sound/soc/codecs/es8316.c mask = ES8316_SERDATA1_MASTER | ES8316_SERDATA1_BCLK_INV; mask 438 sound/soc/codecs/es8316.c snd_soc_component_update_bits(component, ES8316_SERDATA1, mask, serdata1); mask 440 sound/soc/codecs/es8316.c mask = ES8316_SERDATA2_FMT_MASK | ES8316_SERDATA2_ADCLRP; mask 441 sound/soc/codecs/es8316.c snd_soc_component_update_bits(component, ES8316_SERDATA_ADC, mask, serdata2); mask 442 sound/soc/codecs/es8316.c snd_soc_component_update_bits(component, ES8316_SERDATA_DAC, mask, serdata2); mask 1003 sound/soc/codecs/hdac_hdmi.c se->mask = roundup_pow_of_two(se->items) - 1; mask 59 sound/soc/codecs/hdmi-codec.c unsigned long mask; mask 198 sound/soc/codecs/hdmi-codec.c .mask = FL | FR}, mask 201 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE}, mask 204 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC }, mask 207 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR}, mask 210 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR }, mask 213 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR }, mask 216 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR }, mask 219 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | RC }, mask 222 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, mask 225 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC }, mask 227 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RC}, mask 229 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RC }, mask 231 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RC }, mask 233 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RC }, mask 235 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RC | RL | RR }, mask 237 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | RC }, mask 239 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | RC }, mask 241 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR | RLC | RRC }, mask 243 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | RLC | RRC }, mask 245 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | RLC | RRC }, mask 247 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FLC | FRC }, mask 249 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FLC | FRC }, mask 251 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | FLC | FRC }, mask 253 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | FLC | FRC }, mask 255 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RC | FLC | FRC }, mask 257 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RC | FLC | FRC }, mask 259 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RC | FC | FLC | FRC }, mask 261 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RC | FC | FLC | FRC }, mask 263 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | RL | RR | FLC | FRC }, mask 265 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | RL | RR | FLC | FRC }, mask 267 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | FC | RL | RR | FLC | FRC }, mask 269 sound/soc/codecs/hdmi-codec.c .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, mask 360 sound/soc/codecs/hdmi-codec.c if (!(cap->mask == (spk_mask & cap->mask))) mask 237 sound/soc/codecs/jz4740.c unsigned int mask; mask 244 sound/soc/codecs/jz4740.c mask = JZ4740_CODEC_1_VREF_DISABLE | mask 249 sound/soc/codecs/jz4740.c regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); mask 256 sound/soc/codecs/jz4740.c mask = JZ4740_CODEC_1_VREF_DISABLE | mask 263 sound/soc/codecs/jz4740.c regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); mask 266 sound/soc/codecs/jz4740.c mask = JZ4740_CODEC_1_SUSPEND; mask 269 sound/soc/codecs/jz4740.c regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value); mask 606 sound/soc/codecs/madera.c unsigned int mux, val, mask; mask 616 sound/soc/codecs/madera.c mask = (e->mask << e->shift_l) | MADERA_IN1L_SRC_SE_MASK; mask 639 sound/soc/codecs/madera.c mux, e->reg, inmode, mask, val); mask 641 sound/soc/codecs/madera.c ret = regmap_update_bits_check(regmap, e->reg, mask, val, &changed); mask 918 sound/soc/codecs/madera.c unsigned int mask = MADERA_DSP_RATE_MASK; mask 928 sound/soc/codecs/madera.c mask |= MADERA_DSP_CLK_SEL_MASK; mask 944 sound/soc/codecs/madera.c mask, val); mask 1028 sound/soc/codecs/madera.c val &= e->mask; mask 2155 sound/soc/codecs/madera.c unsigned int val, mask; mask 2164 sound/soc/codecs/madera.c mask = (mc->reg - MADERA_ADC_DIGITAL_VOLUME_1L) / 4; mask 2165 sound/soc/codecs/madera.c mask ^= 0x1; /* Flip bottom bit for channel order */ mask 2167 sound/soc/codecs/madera.c if (val & (1 << mask)) { mask 2374 sound/soc/codecs/madera.c unsigned int mask = 1 << w->shift; mask 2381 sound/soc/codecs/madera.c val = mask; mask 2394 sound/soc/codecs/madera.c madera->hp_ena &= ~mask; mask 2414 sound/soc/codecs/madera.c regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1, mask, val); mask 2461 sound/soc/codecs/madera.c unsigned int mask = MADERA_OPCLK_DIV_MASK | MADERA_OPCLK_SEL_MASK; mask 2500 sound/soc/codecs/madera.c mask, val); mask 2642 sound/soc/codecs/madera.c unsigned int mask = MADERA_SYSCLK_FREQ_MASK | MADERA_SYSCLK_SRC_MASK; mask 2653 sound/soc/codecs/madera.c mask |= MADERA_SYSCLK_FRAC; mask 2705 sound/soc/codecs/madera.c mask = MADERA_SYSCLK_SRC_MASK; mask 2713 sound/soc/codecs/madera.c return regmap_update_bits(madera->regmap, reg, mask, val); mask 2927 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_384K_RATE_MASK; mask 2929 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_384K_44K1_RATE_MASK; mask 2931 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_384K_48K_RATE_MASK; mask 2935 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_192K_RATE_MASK; mask 2937 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_192K_44K1_RATE_MASK; mask 2939 sound/soc/codecs/madera.c dai_priv->constraint.mask = MADERA_192K_48K_RATE_MASK; mask 3281 sound/soc/codecs/madera.c int channels, unsigned int mask) mask 3289 sound/soc/codecs/madera.c slot = ffs(mask) - 1; mask 3295 sound/soc/codecs/madera.c mask &= ~(1 << slot); mask 3298 sound/soc/codecs/madera.c if (mask) mask 300 sound/soc/codecs/madera.h .num_regs = 20, .mask = ~MADERA_EQ1_B1_MODE }) } mask 355 sound/soc/codecs/max98090.c unsigned int mask = (1 << fls(mc->max)) - 1; mask 373 sound/soc/codecs/max98090.c val = (val >> mc->shift) & mask; mask 395 sound/soc/codecs/max98090.c unsigned int mask = (1 << fls(mc->max)) - 1; mask 414 sound/soc/codecs/max98090.c val = (val >> mc->shift) & mask; mask 427 sound/soc/codecs/max98090.c mask << mc->shift, mask 2066 sound/soc/codecs/max98090.c unsigned int status, mask; mask 2080 sound/soc/codecs/max98090.c regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); mask 2081 sound/soc/codecs/max98090.c status &= mask; mask 2217 sound/soc/codecs/max98090.c unsigned int mask; mask 2226 sound/soc/codecs/max98090.c ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); mask 2245 sound/soc/codecs/max98090.c active, mask, active & mask); mask 2247 sound/soc/codecs/max98090.c active &= mask; mask 319 sound/soc/codecs/max98373.c unsigned int mask; mask 363 sound/soc/codecs/max98373.c mask = rx_mask; mask 364 sound/soc/codecs/max98373.c for (x = 0 ; x < 16 ; x++, mask >>= 1) { mask 365 sound/soc/codecs/max98373.c if (mask & 0x1) { mask 152 sound/soc/codecs/mc13783.c unsigned int mask = AUDIO_CFS(3) | AUDIO_BCL_INV | AUDIO_CFS_INV | mask 198 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); mask 248 sound/soc/codecs/mc13783.c unsigned int mask = AUDIO_CLK(0x7) | AUDIO_CLK_SEL; mask 265 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, reg, mask, val); mask 300 sound/soc/codecs/mc13783.c unsigned int mask = SSI_NETWORK_DAC_SLOT_MASK | mask 334 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val); mask 345 sound/soc/codecs/mc13783.c unsigned int mask = 0x3f; mask 356 sound/soc/codecs/mc13783.c snd_soc_component_update_bits(component, MC13783_SSI_NETWORK, mask, val); mask 321 sound/soc/codecs/pcm3168a.c u32 fmt, reg, mask, shift; mask 366 sound/soc/codecs/pcm3168a.c mask = PCM3168A_DAC_FMT_MASK; mask 370 sound/soc/codecs/pcm3168a.c mask = PCM3168A_ADC_FMTAD_MASK; mask 377 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); mask 423 sound/soc/codecs/pcm3168a.c u32 val, mask, shift, reg; mask 435 sound/soc/codecs/pcm3168a.c mask = PCM3168A_DAC_MSDA_MASK; mask 440 sound/soc/codecs/pcm3168a.c mask = PCM3168A_ADC_MSAD_MASK; mask 518 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, val); mask 521 sound/soc/codecs/pcm3168a.c mask = PCM3168A_DAC_FMT_MASK; mask 524 sound/soc/codecs/pcm3168a.c mask = PCM3168A_ADC_FMTAD_MASK; mask 528 sound/soc/codecs/pcm3168a.c regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift); mask 2989 sound/soc/codecs/rt5645.c unsigned int mask, val = 0; mask 2998 sound/soc/codecs/rt5645.c mask = 0x8ff0; mask 3004 sound/soc/codecs/rt5645.c mask = 0x7c00; mask 3044 sound/soc/codecs/rt5645.c snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val); mask 2899 sound/soc/codecs/rt5663.c int mask, shift, val; mask 2917 sound/soc/codecs/rt5663.c mask = RT5663_V2_PLL1_SRC_MASK; mask 2921 sound/soc/codecs/rt5663.c mask = RT5663_PLL1_SRC_MASK; mask 2940 sound/soc/codecs/rt5663.c snd_soc_component_update_bits(component, RT5663_GLB_CLK, mask, (val << shift)); mask 382 sound/soc/codecs/ssm2602.c unsigned int mask; mask 386 sound/soc/codecs/ssm2602.c mask = PWR_CLK_OUT_PDN; mask 389 sound/soc/codecs/ssm2602.c mask = PWR_OSC_PDN; mask 396 sound/soc/codecs/ssm2602.c ssm2602->clk_out_pwr |= mask; mask 398 sound/soc/codecs/ssm2602.c ssm2602->clk_out_pwr &= ~mask; mask 398 sound/soc/codecs/tas2552.c u8 reg, mask, val; mask 413 sound/soc/codecs/tas2552.c mask = TAS2552_PLL_SRC_MASK; mask 414 sound/soc/codecs/tas2552.c val = (clk_id << 3) & mask; /* bit 4:5 in the register */ mask 423 sound/soc/codecs/tas2552.c mask = TAS2552_PDM_CLK_SEL_MASK; mask 424 sound/soc/codecs/tas2552.c val = (clk_id >> 1) & mask; /* bit 0:1 in the register */ mask 434 sound/soc/codecs/tas2552.c snd_soc_component_update_bits(component, reg, mask, val); mask 130 sound/soc/codecs/tda7419.c unsigned int reg, rreg, mask, thresh; mask 156 sound/soc/codecs/tda7419.c static inline int tda7419_vol_get_value(int val, unsigned int mask, mask 160 sound/soc/codecs/tda7419.c val &= mask; mask 185 sound/soc/codecs/tda7419.c unsigned int mask = tvc->mask; mask 196 sound/soc/codecs/tda7419.c tda7419_vol_get_value(val, mask, min, thresh, invert); mask 203 sound/soc/codecs/tda7419.c tda7419_vol_get_value(val, mask, min, thresh, invert); mask 233 sound/soc/codecs/tda7419.c unsigned int mask = tvc->mask; mask 242 sound/soc/codecs/tda7419.c mask, val); mask 250 sound/soc/codecs/tda7419.c mask, val); mask 258 sound/soc/codecs/tda7419.c {.reg = xreg, .rreg = xreg, .mask = xmask, .min = xmin, \ mask 264 sound/soc/codecs/tda7419.c {.reg = xregl, .rreg = xregr, .mask = xmask, .min = xmin, \ mask 261 sound/soc/codecs/tlv320aic23.c int mask = sr_valid_mask[i]; mask 263 sound/soc/codecs/tlv320aic23.c j++, mask >>= 1) { mask 267 sound/soc/codecs/tlv320aic23.c if ((mask & 1) == 0) mask 328 sound/soc/codecs/tlv320aic31xx.c unsigned int mask, unsigned int wbits, int sleep, mask 335 sound/soc/codecs/tlv320aic31xx.c while ((bits & mask) != wbits && counter && !ret) { mask 340 sound/soc/codecs/tlv320aic31xx.c if ((bits & mask) != wbits) { mask 343 sound/soc/codecs/tlv320aic31xx.c __func__, reg, bits, wbits, ret, mask, mask 358 sound/soc/codecs/tlv320aic31xx.c unsigned int mask; mask 362 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_LDACPWRSTATUS_MASK; mask 365 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_RDACPWRSTATUS_MASK; mask 368 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_HPLDRVPWRSTATUS_MASK; mask 371 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_HPRDRVPWRSTATUS_MASK; mask 374 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_SPLDRVPWRSTATUS_MASK; mask 377 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_SPRDRVPWRSTATUS_MASK; mask 380 sound/soc/codecs/tlv320aic31xx.c mask = AIC31XX_ADCPWRSTATUS_MASK; mask 391 sound/soc/codecs/tlv320aic31xx.c return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); mask 393 sound/soc/codecs/tlv320aic31xx.c return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); mask 1163 sound/soc/codecs/tlv320aic31xx.c u8 mask = AIC31XX_PM_MASK; mask 1168 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); mask 1170 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); mask 1171 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); mask 1173 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); mask 1175 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); mask 1176 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); mask 1181 sound/soc/codecs/tlv320aic31xx.c u8 mask = AIC31XX_PM_MASK; mask 1185 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); mask 1186 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); mask 1187 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); mask 1188 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); mask 1189 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); mask 1190 sound/soc/codecs/tlv320aic31xx.c snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); mask 151 sound/soc/codecs/tlv320aic3x.c #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ mask 152 sound/soc/codecs/tlv320aic3x.c SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ mask 169 sound/soc/codecs/tlv320aic3x.c unsigned int mask = (1 << fls(max)) - 1; mask 175 sound/soc/codecs/tlv320aic3x.c val = (ucontrol->value.integer.value[0] & mask); mask 177 sound/soc/codecs/tlv320aic3x.c mask = 0xf; mask 179 sound/soc/codecs/tlv320aic3x.c val = mask; mask 184 sound/soc/codecs/tlv320aic3x.c val = mask - val; mask 186 sound/soc/codecs/tlv320aic3x.c mask <<= shift; mask 189 sound/soc/codecs/tlv320aic3x.c change = snd_soc_component_test_bits(component, reg, mask, val); mask 193 sound/soc/codecs/tlv320aic3x.c update.mask = mask; mask 193 sound/soc/codecs/tscs42xx.c unsigned int mask; mask 199 sound/soc/codecs/tscs42xx.c mask = RM_PLLCTL1C_PDB_PLL1; mask 203 sound/soc/codecs/tscs42xx.c mask = RM_PLLCTL1C_PDB_PLL2; mask 215 sound/soc/codecs/tscs42xx.c ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); mask 943 sound/soc/codecs/tscs42xx.c unsigned int mask; mask 1077 sound/soc/codecs/tscs42xx.c pll_ctl->settings[i].mask, mask 101 sound/soc/codecs/tscs454.c u8 mask = 0x01 << (aif_id * 2 + !playback); mask 103 sound/soc/codecs/tscs454.c status->streams |= mask; mask 109 sound/soc/codecs/tscs454.c u8 mask = ~(0x01 << (aif_id * 2 + !playback)); mask 111 sound/soc/codecs/tscs454.c status->streams &= mask; mask 768 sound/soc/codecs/tscs454.c unsigned int mask; mask 787 sound/soc/codecs/tscs454.c mask = FM_I2SPCTL_PORTMS; mask 790 sound/soc/codecs/tscs454.c ret = snd_soc_component_update_bits(component, reg, mask, val); mask 2664 sound/soc/codecs/tscs454.c unsigned int mask; mask 2675 sound/soc/codecs/tscs454.c mask = FM_I2SCMC_BCMP1; mask 2679 sound/soc/codecs/tscs454.c mask = FM_I2SCMC_BCMP2; mask 2683 sound/soc/codecs/tscs454.c mask = FM_I2SCMC_BCMP3; mask 2709 sound/soc/codecs/tscs454.c R_I2SCMC, mask, val << shift); mask 552 sound/soc/codecs/twl4030.c #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ mask 836 sound/soc/codecs/twl4030.c int mask = (1 << fls(max)) - 1; mask 839 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> shift) & mask; mask 846 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> rshift) & mask; mask 865 sound/soc/codecs/twl4030.c int mask = (1 << fls(max)) - 1; mask 868 sound/soc/codecs/twl4030.c val = (ucontrol->value.integer.value[0] & mask); mask 870 sound/soc/codecs/twl4030.c val_mask = mask << shift; mask 875 sound/soc/codecs/twl4030.c val2 = (ucontrol->value.integer.value[1] & mask); mask 876 sound/soc/codecs/twl4030.c val_mask |= mask << rshift; mask 894 sound/soc/codecs/twl4030.c int mask = (1<<fls(max))-1; mask 897 sound/soc/codecs/twl4030.c (twl4030_read(component, reg) >> shift) & mask; mask 899 sound/soc/codecs/twl4030.c (twl4030_read(component, reg2) >> shift) & mask; mask 921 sound/soc/codecs/twl4030.c int mask = (1 << fls(max)) - 1; mask 925 sound/soc/codecs/twl4030.c val_mask = mask << shift; mask 926 sound/soc/codecs/twl4030.c val = (ucontrol->value.integer.value[0] & mask); mask 927 sound/soc/codecs/twl4030.c val2 = (ucontrol->value.integer.value[1] & mask); mask 1620 sound/soc/codecs/twl4030.c u8 reg, mask; mask 1625 sound/soc/codecs/twl4030.c mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; mask 1627 sound/soc/codecs/twl4030.c mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; mask 1630 sound/soc/codecs/twl4030.c reg |= mask; mask 1632 sound/soc/codecs/twl4030.c reg &= ~mask; mask 1905 sound/soc/codecs/twl4030.c u8 reg, mask; mask 1910 sound/soc/codecs/twl4030.c mask = TWL4030_ARXL1_VRX_EN; mask 1912 sound/soc/codecs/twl4030.c mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; mask 1915 sound/soc/codecs/twl4030.c reg |= mask; mask 1917 sound/soc/codecs/twl4030.c reg &= ~mask; mask 203 sound/soc/codecs/twl6040.c int mask = TWL6040_HSDRVMODE | TWL6040_HSDACMODE; mask 209 sound/soc/codecs/twl6040.c hslctl &= ~mask; mask 210 sound/soc/codecs/twl6040.c hsrctl &= ~mask; mask 212 sound/soc/codecs/twl6040.c hslctl |= mask; mask 213 sound/soc/codecs/twl6040.c hsrctl |= mask; mask 113 sound/soc/codecs/uda134x.c unsigned int mask = 1<<6; mask 115 sound/soc/codecs/uda134x.c regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, mask); mask 117 sound/soc/codecs/uda134x.c regmap_update_bits(uda134x->regmap, UDA134X_STATUS0, mask, 0); mask 123 sound/soc/codecs/uda134x.c unsigned int mask = 1<<2; mask 129 sound/soc/codecs/uda134x.c val = mask; mask 133 sound/soc/codecs/uda134x.c return regmap_update_bits(uda134x->regmap, UDA134X_DATA010, mask, val); mask 429 sound/soc/codecs/wcd9335.c u8 mask; mask 2620 sound/soc/codecs/wcd9335.c u8 mask = 0x20; mask 2625 sound/soc/codecs/wcd9335.c mask = 0x40; mask 2627 sound/soc/codecs/wcd9335.c val = set ? mask : 0x00; mask 2632 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, mask 2637 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, mask 2642 sound/soc/codecs/wcd9335.c snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, mask 4838 sound/soc/codecs/wcd9335.c wcd9335_codec_reg_init[i].mask, mask 4993 sound/soc/codecs/wcd9335.c .mask = BIT(0), mask 100 sound/soc/codecs/wm2000.c unsigned int reg, u8 mask) mask 108 sound/soc/codecs/wm2000.c while (!(val & mask) && --timeout) { mask 2121 sound/soc/codecs/wm2200.c unsigned int val, mask; mask 2131 sound/soc/codecs/wm2200.c &mask); mask 2134 sound/soc/codecs/wm2200.c mask = 0; mask 2137 sound/soc/codecs/wm2200.c val &= ~mask; mask 1282 sound/soc/codecs/wm5100.c int lrclk, bclk, mask, base; mask 1291 sound/soc/codecs/wm5100.c mask = 0; mask 1294 sound/soc/codecs/wm5100.c mask = 2; mask 1344 sound/soc/codecs/wm5100.c snd_soc_component_update_bits(component, base + 5, WM5100_AIF1_FMT_MASK, mask); mask 411 sound/soc/codecs/wm5110.c unsigned int mask = (0x1 << mc->shift) | (0x1 << mc->rshift); mask 444 sound/soc/codecs/wm5110.c mask, lnew | rnew); mask 510 sound/soc/codecs/wm5110.c unsigned int reg, mask; mask 518 sound/soc/codecs/wm5110.c mask = ARIZONA_IN1L_PGA_VOL_MASK; mask 529 sound/soc/codecs/wm5110.c snd_soc_component_update_bits(component, reg, mask, mask 546 sound/soc/codecs/wm5110.c snd_soc_component_update_bits(component, reg, mask, mask 1239 sound/soc/codecs/wm8350.c u16 mask) mask 1246 sound/soc/codecs/wm8350.c if (reg & mask) mask 165 sound/soc/codecs/wm8804.c unsigned int mask = 1 << e->shift_l; mask 168 sound/soc/codecs/wm8804.c if (val != 0 && val != mask) mask 173 sound/soc/codecs/wm8804.c if (snd_soc_component_test_bits(component, e->reg, mask, val)) { mask 181 sound/soc/codecs/wm8804.c snd_soc_component_update_bits(component, e->reg, mask, val); mask 1647 sound/soc/codecs/wm8903.c unsigned int int_val, mask, int_pol; mask 1650 sound/soc/codecs/wm8903.c &mask); mask 1662 sound/soc/codecs/wm8903.c int_val &= ~mask; mask 1786 sound/soc/codecs/wm8903.c unsigned int mask, val; mask 1789 sound/soc/codecs/wm8903.c mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK; mask 1794 sound/soc/codecs/wm8903.c WM8903_GPIO_CONTROL_1 + offset, mask, val); mask 1815 sound/soc/codecs/wm8903.c unsigned int mask, val; mask 1818 sound/soc/codecs/wm8903.c mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK; mask 1823 sound/soc/codecs/wm8903.c WM8903_GPIO_CONTROL_1 + offset, mask, val); mask 3010 sound/soc/codecs/wm8962.c unsigned int mask; mask 3021 sound/soc/codecs/wm8962.c &mask); mask 3036 sound/soc/codecs/wm8962.c active &= ~mask; mask 3283 sound/soc/codecs/wm8962.c int mask = 0; mask 3290 sound/soc/codecs/wm8962.c mask = WM8962_CLKOUT2_SEL_MASK; mask 3294 sound/soc/codecs/wm8962.c mask = WM8962_CLKOUT3_SEL_MASK; mask 3301 sound/soc/codecs/wm8962.c if (mask) mask 3303 sound/soc/codecs/wm8962.c mask, val); mask 1407 sound/soc/codecs/wm8993.c int mask, val, ret; mask 1416 sound/soc/codecs/wm8993.c ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask); mask 1424 sound/soc/codecs/wm8993.c val &= ~(mask | WM8993_IRQ); mask 48 sound/soc/codecs/wm8994.c unsigned int mask; mask 300 sound/soc/codecs/wm8994.c int mask, ret; mask 304 sound/soc/codecs/wm8994.c mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | mask 307 sound/soc/codecs/wm8994.c mask = WM8994_AIF1DAC1_DRC_ENA_MASK; mask 312 sound/soc/codecs/wm8994.c if (ret & mask) mask 1047 sound/soc/codecs/wm8994.c int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; mask 1056 sound/soc/codecs/wm8994.c mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; mask 1066 sound/soc/codecs/wm8994.c mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); mask 1091 sound/soc/codecs/wm8994.c mask, adc); mask 1093 sound/soc/codecs/wm8994.c mask, dac); mask 1099 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask, mask 1104 sound/soc/codecs/wm8994.c snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask, mask 1121 sound/soc/codecs/wm8994.c mask, 0); mask 1123 sound/soc/codecs/wm8994.c mask, 0); mask 1339 sound/soc/codecs/wm8994.c unsigned int mask = 1 << w->shift; mask 1342 sound/soc/codecs/wm8994.c mask, mask); mask 3024 sound/soc/codecs/wm8994.c int reg, val, mask; mask 3029 sound/soc/codecs/wm8994.c mask = WM8994_AIF1_TRI; mask 3033 sound/soc/codecs/wm8994.c mask = WM8994_AIF2_TRI; mask 3040 sound/soc/codecs/wm8994.c val = mask; mask 3044 sound/soc/codecs/wm8994.c return snd_soc_component_update_bits(component, reg, mask, val); mask 4220 sound/soc/codecs/wm8994.c wm8994_vu_bits[i].mask, mask 4221 sound/soc/codecs/wm8994.c wm8994_vu_bits[i].mask); mask 589 sound/soc/codecs/wm8995.c unsigned int reg, unsigned int val, unsigned int mask) mask 594 sound/soc/codecs/wm8995.c __func__, reg, val, mask); mask 600 sound/soc/codecs/wm8995.c if ((val & mask) == mask) mask 1684 sound/soc/codecs/wm8995.c int reg, val, mask; mask 1689 sound/soc/codecs/wm8995.c mask = WM8995_AIF1_TRI; mask 1693 sound/soc/codecs/wm8995.c mask = WM8995_AIF2_TRI; mask 1697 sound/soc/codecs/wm8995.c mask = WM8995_AIF3_TRI; mask 1704 sound/soc/codecs/wm8995.c val = mask; mask 1708 sound/soc/codecs/wm8995.c return snd_soc_component_update_bits(component, reg, mask, val); mask 653 sound/soc/codecs/wm8996.c static void wait_for_dc_servo(struct snd_soc_component *component, u16 mask) mask 660 sound/soc/codecs/wm8996.c snd_soc_component_write(component, WM8996_DC_SERVO_2, mask); mask 677 sound/soc/codecs/wm8996.c } while (timeout && ret & mask); mask 680 sound/soc/codecs/wm8996.c dev_err(component->dev, "DC servo timed out for %x\n", mask); mask 682 sound/soc/codecs/wm8996.c dev_dbg(component->dev, "DC servo complete for %x\n", mask); mask 689 sound/soc/codecs/wm8996.c u16 val, mask; mask 708 sound/soc/codecs/wm8996.c mask = 0; mask 711 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; mask 713 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT1L_RMV_SHORT | mask 720 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; mask 722 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT1R_RMV_SHORT | mask 727 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val); mask 730 sound/soc/codecs/wm8996.c mask = 0; mask 733 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; mask 735 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT2L_RMV_SHORT | mask 742 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; mask 744 sound/soc/codecs/wm8996.c mask |= WM8996_HPOUT2R_RMV_SHORT | mask 749 sound/soc/codecs/wm8996.c snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val); mask 224 sound/soc/codecs/wm9712.c unsigned int mixer, mask, shift, old; mask 230 sound/soc/codecs/wm9712.c mask = 1 << shift; mask 235 sound/soc/codecs/wm9712.c wm9712->hp_mixer[mixer] |= mask; mask 237 sound/soc/codecs/wm9712.c wm9712->hp_mixer[mixer] &= ~mask; mask 243 sound/soc/codecs/wm9712.c update.mask = 0x8000; mask 244 sound/soc/codecs/wm9712.c if ((wm9712->hp_mixer[0] & mask) || mask 245 sound/soc/codecs/wm9712.c (wm9712->hp_mixer[1] & mask)) mask 233 sound/soc/codecs/wm9713.c unsigned int mixer, mask, shift, old; mask 239 sound/soc/codecs/wm9713.c mask = (1 << shift); mask 244 sound/soc/codecs/wm9713.c wm9713->hp_mixer[mixer] |= mask; mask 246 sound/soc/codecs/wm9713.c wm9713->hp_mixer[mixer] &= ~mask; mask 252 sound/soc/codecs/wm9713.c update.mask = 0x8000; mask 253 sound/soc/codecs/wm9713.c if ((wm9713->hp_mixer[0] & mask) || mask 254 sound/soc/codecs/wm9713.c (wm9713->hp_mixer[1] & mask)) mask 1258 sound/soc/codecs/wm_hubs.c int mask, val; mask 1270 sound/soc/codecs/wm_hubs.c mask = 0; mask 1273 sound/soc/codecs/wm_hubs.c mask |= WM8993_LINEOUT1N_ENA | WM8993_LINEOUT1P_ENA; mask 1276 sound/soc/codecs/wm_hubs.c mask |= WM8993_LINEOUT2N_ENA | WM8993_LINEOUT2P_ENA; mask 1291 sound/soc/codecs/wm_hubs.c mask, val); mask 191 sound/soc/fsl/fsl-asoc-card.c struct snd_mask *mask; mask 196 sound/soc/fsl/fsl-asoc-card.c mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); mask 197 sound/soc/fsl/fsl-asoc-card.c snd_mask_none(mask); mask 198 sound/soc/fsl/fsl-asoc-card.c snd_mask_set_format(mask, priv->asrc_format); mask 150 sound/soc/fsl/fsl_asrc_dma.c dma_cap_mask_t mask; mask 198 sound/soc/fsl/fsl_asrc_dma.c dma_cap_zero(mask); mask 199 sound/soc/fsl/fsl_asrc_dma.c dma_cap_set(DMA_SLAVE, mask); mask 200 sound/soc/fsl/fsl_asrc_dma.c dma_cap_set(DMA_CYCLIC, mask); mask 216 sound/soc/fsl/fsl_asrc_dma.c pair->dma_chan[dir] = dma_request_channel(mask, filter, &pair->dma_data); mask 87 sound/soc/fsl/fsl_audmix.c unsigned int *mask, unsigned int *ctr, mask 101 sound/soc/fsl/fsl_audmix.c (*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK; mask 161 sound/soc/fsl/fsl_audmix.c unsigned int reg_val, val, mask = 0, ctr = 0; mask 195 sound/soc/fsl/fsl_audmix.c ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]); mask 200 sound/soc/fsl/fsl_audmix.c mask |= FSL_AUDMIX_CTR_OUTSRC_MASK; mask 203 sound/soc/fsl/fsl_audmix.c return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); mask 248 sound/soc/fsl/fsl_audmix.c u32 mask = 0, ctr = 0; mask 280 sound/soc/fsl/fsl_audmix.c mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK; mask 282 sound/soc/fsl/fsl_audmix.c return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); mask 397 sound/soc/fsl/fsl_esai.c u32 xcr = 0, xccr = 0, mask; mask 470 sound/soc/fsl/fsl_esai.c mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; mask 471 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); mask 472 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); mask 474 sound/soc/fsl/fsl_esai.c mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | mask 476 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); mask 477 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); mask 514 sound/soc/fsl/fsl_esai.c u32 bclk, mask, val; mask 527 sound/soc/fsl/fsl_esai.c mask = ESAI_xCR_xSWS_MASK; mask 530 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); mask 533 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); mask 543 sound/soc/fsl/fsl_esai.c mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | mask 548 sound/soc/fsl/fsl_esai.c regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); mask 622 sound/soc/fsl/fsl_esai.c u32 mask; mask 646 sound/soc/fsl/fsl_esai.c mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; mask 649 sound/soc/fsl/fsl_esai.c ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); mask 651 sound/soc/fsl/fsl_esai.c ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); mask 45 sound/soc/fsl/fsl_sai.c u32 flags, xcsr, mask; mask 53 sound/soc/fsl/fsl_sai.c mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; mask 57 sound/soc/fsl/fsl_sai.c flags = xcsr & mask; mask 91 sound/soc/fsl/fsl_sai.c flags = xcsr & mask; mask 326 sound/soc/fsl/fsl_spdif.c u8 mask, u8 cstatus) mask 328 sound/soc/fsl/fsl_spdif.c ctrl->ch_status[3] &= ~mask; mask 329 sound/soc/fsl/fsl_spdif.c ctrl->ch_status[3] |= cstatus & mask; mask 378 sound/soc/fsl/fsl_spdif.c u32 stc, mask, rate; mask 447 sound/soc/fsl/fsl_spdif.c mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | mask 449 sound/soc/fsl/fsl_spdif.c regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); mask 464 sound/soc/fsl/fsl_spdif.c u32 scr, mask; mask 498 sound/soc/fsl/fsl_spdif.c mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | mask 508 sound/soc/fsl/fsl_spdif.c mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| mask 514 sound/soc/fsl/fsl_spdif.c regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); mask 539 sound/soc/fsl/fsl_spdif.c u32 scr, mask, i; mask 543 sound/soc/fsl/fsl_spdif.c mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | mask 550 sound/soc/fsl/fsl_spdif.c mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| mask 554 sound/soc/fsl/fsl_spdif.c regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); mask 679 sound/soc/fsl/fsl_ssi.c u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; mask 762 sound/soc/fsl/fsl_ssi.c mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; mask 766 sound/soc/fsl/fsl_ssi.c regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); mask 870 sound/soc/fsl/fsl_ssi.c u32 strcr = 0, scr = 0, stcr, srcr, mask; mask 981 sound/soc/fsl/fsl_ssi.c mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | mask 984 sound/soc/fsl/fsl_ssi.c regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); mask 985 sound/soc/fsl/fsl_ssi.c regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); mask 987 sound/soc/fsl/fsl_ssi.c mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | mask 989 sound/soc/fsl/fsl_ssi.c regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); mask 187 sound/soc/fsl/wm1133-ev1.c { .pin = "Headphone Jack", .mask = SND_JACK_HEADPHONE }, mask 193 sound/soc/fsl/wm1133-ev1.c { .pin = "Mic1 Jack", .mask = SND_JACK_MICROPHONE }, mask 194 sound/soc/fsl/wm1133-ev1.c { .pin = "Mic2 Jack", .mask = SND_JACK_MICROPHONE }, mask 502 sound/soc/generic/simple-card-utils.c int mask; mask 514 sound/soc/generic/simple-card-utils.c mask = SND_JACK_HEADPHONE; mask 519 sound/soc/generic/simple-card-utils.c mask = SND_JACK_MICROPHONE; mask 528 sound/soc/generic/simple-card-utils.c sjack->pin.mask = mask; mask 531 sound/soc/generic/simple-card-utils.c sjack->gpio.report = mask; mask 536 sound/soc/generic/simple-card-utils.c snd_soc_card_jack_new(card, pin_name, mask, mask 655 sound/soc/intel/baytrail/sst-baytrail-ipc.c static u64 byt_reply_msg_match(u64 header, u64 *mask) mask 658 sound/soc/intel/baytrail/sst-baytrail-ipc.c *mask = IPC_HEADER_MSG_ID_MASK | mask 660 sound/soc/intel/baytrail/sst-baytrail-ipc.c header &= *mask; mask 93 sound/soc/intel/boards/bdw-rt5677.c .mask = SND_JACK_HEADPHONE, mask 98 sound/soc/intel/boards/bdw-rt5677.c .mask = SND_JACK_MICROPHONE, mask 27 sound/soc/intel/boards/broadwell.c .mask = SND_JACK_MICROPHONE, mask 31 sound/soc/intel/boards/broadwell.c .mask = SND_JACK_HEADPHONE, mask 260 sound/soc/intel/boards/bxt_da7219_max98357a.c .mask = 0, mask 270 sound/soc/intel/boards/bxt_da7219_max98357a.c .mask = 0, mask 280 sound/soc/intel/boards/bxt_da7219_max98357a.c .mask = 0, mask 49 sound/soc/intel/boards/bxt_rt298.c .mask = SND_JACK_MICROPHONE, mask 53 sound/soc/intel/boards/bxt_rt298.c .mask = SND_JACK_HEADPHONE, mask 250 sound/soc/intel/boards/bxt_rt298.c .mask = 0, mask 270 sound/soc/intel/boards/bxt_rt298.c .mask = 0, mask 296 sound/soc/intel/boards/bxt_rt298.c .mask = 0, mask 52 sound/soc/intel/boards/byt-max98090.c .mask = SND_JACK_HEADPHONE, mask 56 sound/soc/intel/boards/byt-max98090.c .mask = SND_JACK_MICROPHONE, mask 56 sound/soc/intel/boards/bytcht_cx2072x.c .mask = SND_JACK_MICROPHONE, mask 60 sound/soc/intel/boards/bytcht_cx2072x.c .mask = SND_JACK_HEADPHONE, mask 150 sound/soc/intel/boards/bytcht_es8316.c .mask = SND_JACK_HEADPHONE, mask 154 sound/soc/intel/boards/bytcht_es8316.c .mask = SND_JACK_MICROPHONE, mask 372 sound/soc/intel/boards/bytcr_rt5640.c .mask = SND_JACK_HEADPHONE, mask 376 sound/soc/intel/boards/bytcr_rt5640.c .mask = SND_JACK_MICROPHONE, mask 339 sound/soc/intel/boards/bytcr_rt5651.c .mask = SND_JACK_HEADPHONE, mask 343 sound/soc/intel/boards/bytcr_rt5651.c .mask = SND_JACK_MICROPHONE, mask 155 sound/soc/intel/boards/cht_bsw_max98090_ti.c .mask = SND_JACK_HEADPHONE, mask 159 sound/soc/intel/boards/cht_bsw_max98090_ti.c .mask = SND_JACK_MICROPHONE, mask 33 sound/soc/intel/boards/cht_bsw_nau8824.c .mask = SND_JACK_HEADPHONE, mask 37 sound/soc/intel/boards/cht_bsw_nau8824.c .mask = SND_JACK_MICROPHONE, mask 199 sound/soc/intel/boards/cht_bsw_rt5645.c .mask = SND_JACK_HEADPHONE, mask 203 sound/soc/intel/boards/cht_bsw_rt5645.c .mask = SND_JACK_MICROPHONE, mask 40 sound/soc/intel/boards/cht_bsw_rt5672.c .mask = SND_JACK_MICROPHONE, mask 44 sound/soc/intel/boards/cht_bsw_rt5672.c .mask = SND_JACK_HEADPHONE, mask 247 sound/soc/intel/boards/glk_rt5682_max98357a.c .mask = 0, mask 257 sound/soc/intel/boards/glk_rt5682_max98357a.c .mask = 0, mask 267 sound/soc/intel/boards/glk_rt5682_max98357a.c .mask = 0, mask 254 sound/soc/intel/boards/kbl_da7219_max98357a.c .mask = 0, mask 264 sound/soc/intel/boards/kbl_da7219_max98357a.c .mask = 0, mask 274 sound/soc/intel/boards/kbl_da7219_max98357a.c .mask = 0, mask 429 sound/soc/intel/boards/kbl_da7219_max98927.c .mask = 0, mask 439 sound/soc/intel/boards/kbl_da7219_max98927.c .mask = 0, mask 449 sound/soc/intel/boards/kbl_da7219_max98927.c .mask = 0, mask 72 sound/soc/intel/boards/kbl_rt5660.c .mask = SND_JACK_LINEOUT, mask 77 sound/soc/intel/boards/kbl_rt5660.c .mask = SND_JACK_MICROPHONE, mask 279 sound/soc/intel/boards/kbl_rt5660.c .mask = 0, mask 289 sound/soc/intel/boards/kbl_rt5660.c .mask = 0, mask 355 sound/soc/intel/boards/kbl_rt5663_max98927.c .mask = 0, mask 365 sound/soc/intel/boards/kbl_rt5663_max98927.c .mask = 0, mask 511 sound/soc/intel/boards/kbl_rt5663_max98927.c .mask = 0, mask 521 sound/soc/intel/boards/kbl_rt5663_max98927.c .mask = 0, mask 225 sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c .mask = 0, mask 235 sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c .mask = 0, mask 382 sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c .mask = 0, mask 392 sound/soc/intel/boards/kbl_rt5663_rt5514_max98927.c .mask = 0, mask 254 sound/soc/intel/boards/skl_nau88l25_max98357a.c .mask = 0, mask 264 sound/soc/intel/boards/skl_nau88l25_max98357a.c .mask = 0, mask 336 sound/soc/intel/boards/skl_nau88l25_max98357a.c .mask = 0, mask 346 sound/soc/intel/boards/skl_nau88l25_max98357a.c .mask = 0, mask 274 sound/soc/intel/boards/skl_nau88l25_ssm4567.c .mask = 0, mask 284 sound/soc/intel/boards/skl_nau88l25_ssm4567.c .mask = 0, mask 374 sound/soc/intel/boards/skl_nau88l25_ssm4567.c .mask = 0, mask 384 sound/soc/intel/boards/skl_nau88l25_ssm4567.c .mask = 0, mask 51 sound/soc/intel/boards/skl_rt286.c .mask = SND_JACK_MICROPHONE, mask 55 sound/soc/intel/boards/skl_rt286.c .mask = SND_JACK_HEADPHONE, mask 168 sound/soc/intel/boards/skl_rt286.c .mask = 0, mask 178 sound/soc/intel/boards/skl_rt286.c .mask = 0, mask 267 sound/soc/intel/boards/skl_rt286.c .mask = 0, mask 154 sound/soc/intel/common/sst-dsp.c u32 mask, u32 value) mask 163 sound/soc/intel/common/sst-dsp.c new = (old & (~mask)) | (value & mask); mask 174 sound/soc/intel/common/sst-dsp.c u64 mask, u64 value) mask 181 sound/soc/intel/common/sst-dsp.c new = (old & (~mask)) | (value & mask); mask 193 sound/soc/intel/common/sst-dsp.c u32 mask, u32 value) mask 201 sound/soc/intel/common/sst-dsp.c new = (old & (~mask)) | (value & mask); mask 208 sound/soc/intel/common/sst-dsp.c u32 mask, u32 value) mask 214 sound/soc/intel/common/sst-dsp.c change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value); mask 221 sound/soc/intel/common/sst-dsp.c u64 mask, u64 value) mask 227 sound/soc/intel/common/sst-dsp.c change = sst_dsp_shim_update_bits64_unlocked(sst, offset, mask, value); mask 235 sound/soc/intel/common/sst-dsp.c u32 mask, u32 value) mask 240 sound/soc/intel/common/sst-dsp.c sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value); mask 245 sound/soc/intel/common/sst-dsp.c int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask, mask 263 sound/soc/intel/common/sst-dsp.c while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target) mask 272 sound/soc/intel/common/sst-dsp.c if ((reg & mask) == target) { mask 221 sound/soc/intel/common/sst-dsp.h u32 mask, u32 value); mask 225 sound/soc/intel/common/sst-dsp.h u64 mask, u64 value); mask 227 sound/soc/intel/common/sst-dsp.h u32 mask, u32 value); mask 233 sound/soc/intel/common/sst-dsp.h u32 mask, u32 value); mask 237 sound/soc/intel/common/sst-dsp.h u64 mask, u64 value); mask 239 sound/soc/intel/common/sst-dsp.h u32 mask, u32 value); mask 278 sound/soc/intel/common/sst-dsp.h int sst_dsp_register_poll(struct sst_dsp *dsp, u32 offset, u32 mask, mask 221 sound/soc/intel/common/sst-firmware.c dma_cap_mask_t mask; mask 224 sound/soc/intel/common/sst-firmware.c dma_cap_zero(mask); mask 225 sound/soc/intel/common/sst-firmware.c dma_cap_set(DMA_SLAVE, mask); mask 226 sound/soc/intel/common/sst-firmware.c dma_cap_set(DMA_MEMCPY, mask); mask 228 sound/soc/intel/common/sst-firmware.c dma->ch = dma_request_channel(mask, dma_chan_filter, dsp); mask 222 sound/soc/intel/common/sst-ipc.c u64 mask; mask 225 sound/soc/intel/common/sst-ipc.c header = ipc->ops.reply_msg_match(header, &mask); mask 227 sound/soc/intel/common/sst-ipc.c mask = (u64)-1; mask 236 sound/soc/intel/common/sst-ipc.c if ((msg->tx.header & mask) == header) mask 45 sound/soc/intel/common/sst-ipc.h u64 (*reply_msg_match)(u64 header, u64 *mask); mask 2081 sound/soc/intel/haswell/sst-haswell-ipc.c static u64 hsw_reply_msg_match(u64 header, u64 *mask) mask 2085 sound/soc/intel/haswell/sst-haswell-ipc.c *mask = (u64)-1; mask 26 sound/soc/intel/skylake/skl-i2s.h #define get_clk_src(mclk, mask) \ mask 27 sound/soc/intel/skylake/skl-i2s.h ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask)) mask 45 sound/soc/intel/skylake/skl.c unsigned char mask, unsigned char val) mask 50 sound/soc/intel/skylake/skl.c data &= ~mask; mask 51 sound/soc/intel/skylake/skl.c data |= (val & mask); mask 71 sound/soc/intel/skylake/skl.c unsigned int reg, u32 mask, u32 val) mask 76 sound/soc/intel/skylake/skl.c data &= ~mask; mask 77 sound/soc/intel/skylake/skl.c data |= (val & mask); mask 169 sound/soc/jz4740/jz4740-i2s.c uint32_t mask; mask 172 sound/soc/jz4740/jz4740-i2s.c mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA; mask 174 sound/soc/jz4740/jz4740-i2s.c mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; mask 182 sound/soc/jz4740/jz4740-i2s.c ctrl |= mask; mask 187 sound/soc/jz4740/jz4740-i2s.c ctrl &= ~mask; mask 44 sound/soc/kirkwood/kirkwood-dma.c unsigned long mask, status, cause; mask 46 sound/soc/kirkwood/kirkwood-dma.c mask = readl(priv->io + KIRKWOOD_INT_MASK); mask 47 sound/soc/kirkwood/kirkwood-dma.c status = readl(priv->io + KIRKWOOD_INT_CAUSE) & mask; mask 38 sound/soc/kirkwood/kirkwood-i2s.c unsigned long mask; mask 43 sound/soc/kirkwood/kirkwood-i2s.c mask = KIRKWOOD_I2S_CTL_RJ; mask 46 sound/soc/kirkwood/kirkwood-i2s.c mask = KIRKWOOD_I2S_CTL_LJ; mask 49 sound/soc/kirkwood/kirkwood-i2s.c mask = KIRKWOOD_I2S_CTL_I2S; mask 61 sound/soc/kirkwood/kirkwood-i2s.c value |= mask; mask 66 sound/soc/kirkwood/kirkwood-i2s.c value |= mask; mask 20 sound/soc/mediatek/common/mtk-afe-fe-dai.c unsigned int mask, mask 25 sound/soc/mediatek/common/mtk-afe-fe-dai.c return regmap_update_bits(map, reg, mask << shift, val << shift); mask 180 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c unsigned int mask, val; mask 188 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c mask = ASYS_I2S_CON_FS | mask 198 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c mask |= ASYS_I2S_IN_PHASE_FIX; mask 203 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c mask |= ASYS_I2S_CON_ONE_HEART_MODE; mask 209 sound/soc/mediatek/mt2701/mt2701-afe-pcm.c regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, mask, val); mask 104 sound/soc/mediatek/mt2701/mt2701-cs42448.c .mask = 0, mask 20 sound/soc/mediatek/mt8173/mt8173-max98090.c .mask = SND_JACK_HEADPHONE, mask 24 sound/soc/mediatek/mt8173/mt8173-max98090.c .mask = SND_JACK_MICROPHONE, mask 74 sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c .mask = 0, mask 82 sound/soc/mediatek/mt8183/mt8183-mt6358-ts3a227-max98357.c .mask = 0, mask 182 sound/soc/meson/axg-fifo.c static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask) mask 186 sound/soc/meson/axg-fifo.c CTRL1_INT_CLR(mask)); mask 209 sound/soc/meson/axg-pdm.c unsigned int mask = GENMASK(channels - 1, 0); mask 219 sound/soc/meson/axg-pdm.c PDM_CTRL_CHAN_RSTN(mask) | mask 220 sound/soc/meson/axg-pdm.c PDM_CTRL_CHAN_EN(mask)); mask 34 sound/soc/meson/axg-tdm-formatter.c unsigned long mask; mask 43 sound/soc/meson/axg-tdm-formatter.c mask = ts->mask[i]; mask 45 sound/soc/meson/axg-tdm-formatter.c for (j = find_first_bit(&mask, 32); mask 47 sound/soc/meson/axg-tdm-formatter.c j = find_next_bit(&mask, 32, j + 1)) { mask 20 sound/soc/meson/axg-tdm-interface.c static unsigned int axg_tdm_slots_total(u32 *mask) mask 25 sound/soc/meson/axg-tdm-interface.c if (!mask) mask 30 sound/soc/meson/axg-tdm-interface.c slots += hweight32(mask[i]); mask 84 sound/soc/meson/axg-tdm-interface.c tx->mask = tx_mask; mask 90 sound/soc/meson/axg-tdm-interface.c rx->mask = rx_mask; mask 146 sound/soc/meson/axg-tdm-interface.c if (!axg_tdm_slots_total(ts->mask)) { mask 179 sound/soc/meson/axg-tdm-interface.c if (axg_tdm_slots_total(ts->mask) < channels) { mask 59 sound/soc/meson/axg-tdm.h u32 *mask; mask 84 sound/soc/meson/g12a-tohdmitx.c unsigned int mask) mask 89 sound/soc/meson/g12a-tohdmitx.c return (val & mask) >> __ffs(mask); mask 31 sound/soc/pxa/hx4700.c .mask = SND_JACK_HEADPHONE, mask 36 sound/soc/pxa/hx4700.c .mask = SND_JACK_HEADPHONE, mask 32 sound/soc/pxa/palm27x.c .mask = SND_JACK_HEADPHONE, mask 20 sound/soc/pxa/ttc-dkb.c { .pin = "Headset Stereophone", .mask = SND_JACK_HEADPHONE, }, mask 24 sound/soc/pxa/ttc-dkb.c { .pin = "Headset Mic 2", .mask = SND_JACK_MICROPHONE, }, mask 77 sound/soc/pxa/z2.c .mask = SND_JACK_MICROPHONE, mask 81 sound/soc/pxa/z2.c .mask = SND_JACK_HEADPHONE, mask 85 sound/soc/pxa/z2.c .mask = SND_JACK_HEADPHONE, mask 197 sound/soc/qcom/lpass-cpu.c unsigned int val, mask; mask 201 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_SPKEN_MASK; mask 204 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_MICEN_MASK; mask 209 sound/soc/qcom/lpass-cpu.c mask, val); mask 221 sound/soc/qcom/lpass-cpu.c unsigned int val, mask; mask 229 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_SPKEN_MASK; mask 232 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_MICEN_MASK; mask 238 sound/soc/qcom/lpass-cpu.c mask, val); mask 248 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_SPKEN_MASK; mask 251 sound/soc/qcom/lpass-cpu.c mask = LPAIF_I2SCTL_MICEN_MASK; mask 257 sound/soc/qcom/lpass-cpu.c mask, val); mask 155 sound/soc/qcom/qdsp6/q6asm-dai.c .mask = 0, mask 51 sound/soc/rockchip/rk3288_hdmi_analog.c .mask = SND_JACK_HEADPHONE mask 188 sound/soc/rockchip/rockchip_i2s.c unsigned int mask = 0, val = 0; mask 190 sound/soc/rockchip/rockchip_i2s.c mask = I2S_CKR_MSS_MASK; mask 205 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); mask 207 sound/soc/rockchip/rockchip_i2s.c mask = I2S_CKR_CKP_MASK; mask 219 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); mask 221 sound/soc/rockchip/rockchip_i2s.c mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; mask 242 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); mask 244 sound/soc/rockchip/rockchip_i2s.c mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; mask 265 sound/soc/rockchip/rockchip_i2s.c regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); mask 30 sound/soc/rockchip/rockchip_max98090.c .mask = SND_JACK_HEADPHONE, mask 34 sound/soc/rockchip/rockchip_max98090.c .mask = SND_JACK_MICROPHONE, mask 262 sound/soc/rockchip/rockchip_pdm.c unsigned int mask = 0, val = 0; mask 264 sound/soc/rockchip/rockchip_pdm.c mask = PDM_CKP_MSK; mask 277 sound/soc/rockchip/rockchip_pdm.c regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val); mask 39 sound/soc/samsung/h1940_uda1380.c .mask = SND_JACK_HEADPHONE, mask 43 sound/soc/samsung/h1940_uda1380.c .mask = SND_JACK_HEADPHONE, mask 506 sound/soc/samsung/i2s.c u32 mod, mask, val = 0; mask 518 sound/soc/samsung/i2s.c mask = MOD_OPCLK_MASK; mask 522 sound/soc/samsung/i2s.c mask = 1 << i2s_regs->cdclkcon_off; mask 547 sound/soc/samsung/i2s.c mask = 1 << i2s_regs->rclksrc_off; mask 611 sound/soc/samsung/i2s.c mod = (mod & ~mask) | val; mask 724 sound/soc/samsung/i2s.c u32 mod, mask = 0, val = 0; mask 731 sound/soc/samsung/i2s.c mask |= (MOD_DC2_EN | MOD_DC1_EN); mask 760 sound/soc/samsung/i2s.c mask |= MOD_BLCS_MASK; mask 762 sound/soc/samsung/i2s.c mask |= MOD_BLCP_MASK; mask 765 sound/soc/samsung/i2s.c mask |= MOD_BLC_MASK; mask 800 sound/soc/samsung/i2s.c mod = (mod & ~mask) | val; mask 25 sound/soc/samsung/lowland.c .mask = SND_JACK_HEADPHONE | SND_JACK_LINEOUT, mask 29 sound/soc/samsung/lowland.c .mask = SND_JACK_MICROPHONE, mask 50 sound/soc/samsung/rx1950_uda1380.c .mask = SND_JACK_HEADPHONE, mask 54 sound/soc/samsung/rx1950_uda1380.c .mask = SND_JACK_HEADPHONE, mask 46 sound/soc/samsung/s3c24xx_uda134x.c .mask = 0, mask 83 sound/soc/samsung/smartq_wm8987.c .mask = SND_JACK_HEADPHONE, mask 104 sound/soc/samsung/speyside.c .mask = SND_JACK_MICROPHONE, mask 168 sound/soc/samsung/tobermory.c .mask = SND_JACK_MICROPHONE, mask 172 sound/soc/samsung/tobermory.c .mask = SND_JACK_MICROPHONE, mask 324 sound/soc/sh/fsi.c static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) mask 328 sound/soc/sh/fsi.c val &= ~mask; mask 329 sound/soc/sh/fsi.c val |= data & mask; mask 360 sound/soc/sh/fsi.c u32 reg, u32 mask, u32 data) mask 365 sound/soc/sh/fsi.c __fsi_reg_mask_set(master->base + reg, mask, data); mask 714 sound/soc/sh/fsi.c u32 mask, val; mask 716 sound/soc/sh/fsi.c mask = BP | SE; mask 717 sound/soc/sh/fsi.c val = enable ? mask : 0; mask 720 sound/soc/sh/fsi.c fsi_core_mask_set(master, a_mclk, mask, val) : mask 721 sound/soc/sh/fsi.c fsi_core_mask_set(master, b_mclk, mask, val); mask 1363 sound/soc/sh/fsi.c dma_cap_mask_t mask; mask 1364 sound/soc/sh/fsi.c dma_cap_zero(mask); mask 1365 sound/soc/sh/fsi.c dma_cap_set(DMA_SLAVE, mask); mask 1367 sound/soc/sh/fsi.c io->chan = dma_request_channel(mask, shdma_chan_filter, mask 216 sound/soc/sh/rcar/adg.c u32 mask, val; mask 224 sound/soc/sh/rcar/adg.c mask = 0x0f1f << shift; mask 226 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); mask 240 sound/soc/sh/rcar/adg.c u32 mask, en; mask 252 sound/soc/sh/rcar/adg.c mask = 0x0f1f << shift; mask 254 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in); mask 255 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out); mask 271 sound/soc/sh/rcar/adg.c u32 mask = 0xFF << shift; mask 284 sound/soc/sh/rcar/adg.c rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); mask 545 sound/soc/sh/rcar/core.c u32 mask = 0xF << shift; mask 553 sound/soc/sh/rcar/core.c *status = (*status & ~mask) + (next_val << shift); mask 991 sound/soc/sh/rcar/core.c constraint->mask = 0; mask 415 sound/soc/sh/rcar/dma.c static void rsnd_dmapp_bset(struct rsnd_dma *dma, u32 data, u32 mask, u32 reg) mask 423 sound/soc/sh/rcar/dma.c val &= ~mask; mask 424 sound/soc/sh/rcar/dma.c val |= (data & mask); mask 119 sound/soc/sh/rcar/gen.c enum rsnd_reg reg, u32 mask, u32 data) mask 129 sound/soc/sh/rcar/gen.c rsnd_mod_id_cmd(mod), mask, data); mask 133 sound/soc/sh/rcar/gen.c rsnd_reg_name(gen, reg), reg, data, mask); mask 252 sound/soc/sh/rcar/rsnd.h void rsnd_mod_bset(struct rsnd_mod *mod, enum rsnd_reg reg, u32 mask, u32 data); mask 176 sound/soc/sh/rcar/ssi.c int i, mask; mask 178 sound/soc/sh/rcar/ssi.c mask = 0; mask 184 sound/soc/sh/rcar/ssi.c mask |= 1 << rsnd_mod_id(mod); mask 187 sound/soc/sh/rcar/ssi.c return mask; mask 53 sound/soc/sh/siu_dai.c u32 mask; mask 69 sound/soc/sh/siu_dai.c .mask = 0xd0000000, mask 75 sound/soc/sh/siu_dai.c .mask = 0x0d000000, mask 83 sound/soc/sh/siu_dai.c .mask = 0x00500000, mask 89 sound/soc/sh/siu_dai.c .mask = 0x00050000, mask 617 sound/soc/sh/siu_dai.c ifctl |= ~(siu_flags[info->port_id].playback.mask | mask 618 sound/soc/sh/siu_dai.c siu_flags[info->port_id].capture.mask) & mask 338 sound/soc/sh/siu_pcm.c dma_cap_mask_t mask; mask 341 sound/soc/sh/siu_pcm.c dma_cap_zero(mask); mask 342 sound/soc/sh/siu_pcm.c dma_cap_set(DMA_SLAVE, mask); mask 359 sound/soc/sh/siu_pcm.c siu_stream->chan = dma_request_channel(mask, filter, param); mask 3066 sound/soc/soc-core.c unsigned int *mask) mask 3077 sound/soc/soc-core.c *mask |= (1 << i); mask 388 sound/soc/soc-dapm.c template.mask = (1 << fls(mc->max)) - 1; mask 426 sound/soc/soc-dapm.c template.mask = e->mask; mask 554 sound/soc/soc-dapm.c data->widget->on_val = value & data->widget->mask; mask 628 sound/soc/soc-dapm.c int reg, unsigned int mask, unsigned int value) mask 633 sound/soc/soc-dapm.c mask, value); mask 637 sound/soc/soc-dapm.c int reg, unsigned int mask, unsigned int value) mask 641 sound/soc/soc-dapm.c return snd_soc_component_test_bits(dapm->component, reg, mask, value); mask 759 sound/soc/soc-dapm.c val = (val >> e->shift_l) & e->mask; mask 790 sound/soc/soc-dapm.c unsigned int mask = (1 << fls(max)) - 1; mask 811 sound/soc/soc-dapm.c val = (val >> mc->rshift) & mask; mask 813 sound/soc/soc-dapm.c val = (val >> shift) & mask; mask 1580 sound/soc/soc-dapm.c unsigned int mask = 0; mask 1590 sound/soc/soc-dapm.c mask |= w->mask << w->shift; mask 1598 sound/soc/soc-dapm.c w->name, reg, value, mask); mask 1612 sound/soc/soc-dapm.c value, mask, reg, card->pop_time); mask 1614 sound/soc/soc-dapm.c soc_dapm_update_bits(dapm, reg, mask, value); mask 1761 sound/soc/soc-dapm.c ret = soc_dapm_update_bits(w->dapm, update->reg, update->mask, mask 2129 sound/soc/soc-dapm.c w->reg, w->reg, w->mask << w->shift); mask 3251 sound/soc/soc-dapm.c val &= w->mask; mask 3288 sound/soc/soc-dapm.c unsigned int mask = (1 << fls(max)) - 1; mask 3296 sound/soc/soc-dapm.c val = (reg_val >> shift) & mask; mask 3302 sound/soc/soc-dapm.c rval = (reg_val >> mc->rshift) & mask; mask 3305 sound/soc/soc-dapm.c val = reg_val & mask; mask 3308 sound/soc/soc-dapm.c rval = (reg_val >> width) & mask; mask 3351 sound/soc/soc-dapm.c unsigned int mask = (1 << width) - 1; mask 3358 sound/soc/soc-dapm.c val = (ucontrol->value.integer.value[0] & mask); mask 3365 sound/soc/soc-dapm.c rval = (ucontrol->value.integer.value[1] & mask); mask 3384 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, reg, mask << shift, val); mask 3388 sound/soc/soc-dapm.c mask << mc->rshift, mask 3397 sound/soc/soc-dapm.c update.mask2 = mask << mc->rshift; mask 3402 sound/soc/soc-dapm.c update.mask = mask << shift; mask 3452 sound/soc/soc-dapm.c val = (reg_val >> e->shift_l) & e->mask; mask 3455 sound/soc/soc-dapm.c val = (reg_val >> e->shift_r) & e->mask; mask 3481 sound/soc/soc-dapm.c unsigned int mask; mask 3489 sound/soc/soc-dapm.c mask = e->mask << e->shift_l; mask 3494 sound/soc/soc-dapm.c mask |= e->mask << e->shift_r; mask 3502 sound/soc/soc-dapm.c reg_change = soc_dapm_test_bits(dapm, e->reg, mask, val); mask 3508 sound/soc/soc-dapm.c update.mask = mask; mask 77 sound/soc/soc-io.c unsigned int mask, unsigned int val, bool *change) mask 88 sound/soc/soc-io.c new = (old & ~mask) | (val & mask); mask 110 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) mask 116 sound/soc/soc-io.c ret = regmap_update_bits_check(component->regmap, reg, mask, mask 120 sound/soc/soc-io.c mask, val, &change); mask 146 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int val) mask 153 sound/soc/soc-io.c mask, val, &change); mask 156 sound/soc/soc-io.c mask, val, &change); mask 191 sound/soc/soc-io.c unsigned int reg, unsigned int mask, unsigned int value) mask 199 sound/soc/soc-io.c new = (old & ~mask) | value; mask 78 sound/soc/soc-jack.c void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask) mask 87 sound/soc/soc-jack.c trace_snd_soc_jack_report(jack, mask, status); mask 93 sound/soc/soc-jack.c jack->status &= ~mask; mask 94 sound/soc/soc-jack.c jack->status |= status & mask; mask 99 sound/soc/soc-jack.c enable = pin->mask & jack->status; mask 193 sound/soc/soc-jack.c if (!pins[i].mask) { mask 201 sound/soc/soc-jack.c snd_jack_add_new_kctl(jack->jack, pins[i].pin, pins[i].mask); mask 71 sound/soc/soc-ops.c val = (reg_val >> e->shift_l) & e->mask; mask 75 sound/soc/soc-ops.c val = (reg_val >> e->shift_r) & e->mask; mask 100 sound/soc/soc-ops.c unsigned int mask; mask 105 sound/soc/soc-ops.c mask = e->mask << e->shift_l; mask 110 sound/soc/soc-ops.c mask |= e->mask << e->shift_r; mask 113 sound/soc/soc-ops.c return snd_soc_component_update_bits(component, e->reg, mask, val); mask 133 sound/soc/soc-ops.c unsigned int reg, unsigned int mask, unsigned int shift, mask 143 sound/soc/soc-ops.c val = (val >> shift) & mask; mask 255 sound/soc/soc-ops.c unsigned int mask = (1 << fls(max)) - 1; mask 261 sound/soc/soc-ops.c mask = BIT(sign_bit + 1) - 1; mask 263 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg, mask, shift, sign_bit, &val); mask 274 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg, mask, rshift, mask 277 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg2, mask, shift, mask 315 sound/soc/soc-ops.c unsigned int mask = (1 << fls(max)) - 1; mask 323 sound/soc/soc-ops.c mask = BIT(sign_bit + 1) - 1; mask 325 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[0] + min) & mask); mask 328 sound/soc/soc-ops.c val_mask = mask << shift; mask 331 sound/soc/soc-ops.c val2 = ((ucontrol->value.integer.value[1] + min) & mask); mask 335 sound/soc/soc-ops.c val_mask |= mask << rshift; mask 376 sound/soc/soc-ops.c unsigned int mask = (1U << (fls(min + max) - 1)) - 1; mask 384 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = ((val >> shift) - min) & mask; mask 391 sound/soc/soc-ops.c val = ((val >> rshift) - min) & mask; mask 421 sound/soc/soc-ops.c unsigned int mask = (1U << (fls(min + max) - 1)) - 1; mask 425 sound/soc/soc-ops.c val_mask = mask << shift; mask 426 sound/soc/soc-ops.c val = (ucontrol->value.integer.value[0] + min) & mask; mask 434 sound/soc/soc-ops.c val_mask = mask << rshift; mask 435 sound/soc/soc-ops.c val2 = (ucontrol->value.integer.value[1] + min) & mask; mask 496 sound/soc/soc-ops.c unsigned int mask = (1 << fls(max)) - 1; mask 502 sound/soc/soc-ops.c val = (max - ucontrol->value.integer.value[0]) & mask; mask 504 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[0] + min) & mask); mask 505 sound/soc/soc-ops.c val_mask = mask << shift; mask 514 sound/soc/soc-ops.c val = (max - ucontrol->value.integer.value[1]) & mask; mask 516 sound/soc/soc-ops.c val = ((ucontrol->value.integer.value[1] + min) & mask); mask 517 sound/soc/soc-ops.c val_mask = mask << shift; mask 548 sound/soc/soc-ops.c unsigned int mask = (1 << fls(max)) - 1; mask 557 sound/soc/soc-ops.c ucontrol->value.integer.value[0] = (val >> shift) & mask; mask 570 sound/soc/soc-ops.c ucontrol->value.integer.value[1] = (val >> shift) & mask; mask 650 sound/soc/soc-ops.c if (ret == 0 && params->mask) { mask 653 sound/soc/soc-ops.c ucontrol->value.bytes.data[0] &= ~params->mask; mask 657 sound/soc/soc-ops.c &= cpu_to_be16(~params->mask); mask 661 sound/soc/soc-ops.c &= cpu_to_be32(~params->mask); mask 678 sound/soc/soc-ops.c unsigned int val, mask; mask 695 sound/soc/soc-ops.c if (params->mask) { mask 700 sound/soc/soc-ops.c val &= params->mask; mask 704 sound/soc/soc-ops.c ((u8 *)data)[0] &= ~params->mask; mask 708 sound/soc/soc-ops.c mask = ~params->mask; mask 710 sound/soc/soc-ops.c &mask, &mask); mask 714 sound/soc/soc-ops.c ((u16 *)data)[0] &= mask; mask 724 sound/soc/soc-ops.c mask = ~params->mask; mask 726 sound/soc/soc-ops.c &mask, &mask); mask 730 sound/soc/soc-ops.c ((u32 *)data)[0] &= mask; mask 837 sound/soc/soc-ops.c unsigned long mask = (1UL<<mc->nbits)-1; mask 851 sound/soc/soc-ops.c val &= mask; mask 853 sound/soc/soc-ops.c val |= ~mask; mask 886 sound/soc/soc-ops.c unsigned long mask = (1UL<<mc->nbits)-1; mask 894 sound/soc/soc-ops.c val &= mask; mask 897 sound/soc/soc-ops.c regmask = (mask >> (regwshift*(regcount-i-1))) & regwmask; mask 925 sound/soc/soc-ops.c unsigned int mask = 1 << shift; mask 934 sound/soc/soc-ops.c val &= mask; mask 962 sound/soc/soc-ops.c unsigned int mask = 1 << shift; mask 965 sound/soc/soc-ops.c unsigned int val1 = (strobe ^ invert) ? mask : 0; mask 966 sound/soc/soc-ops.c unsigned int val2 = (strobe ^ invert) ? 0 : mask; mask 969 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg, mask, val1); mask 973 sound/soc/soc-ops.c return snd_soc_component_update_bits(component, reg, mask, val2); mask 834 sound/soc/soc-pcm.c unsigned int mask) mask 837 sound/soc/soc-pcm.c int channels = hweight_long(mask); mask 1050 sound/soc/soc-topology.c se->mask = le32_to_cpu(ec->mask); mask 1446 sound/soc/soc-topology.c se->mask = le32_to_cpu(ec->mask); mask 1621 sound/soc/soc-topology.c template.mask = le32_to_cpu(w->mask); mask 46 sound/soc/sof/intel/hda-codec.c unsigned int mask = 0; mask 50 sound/soc/sof/intel/hda-codec.c mask |= BIT(codec->core.addr); mask 52 sound/soc/sof/intel/hda-codec.c snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, mask); mask 133 sound/soc/sof/intel/hda-stream.c u32 mask; mask 140 sound/soc/sof/intel/hda-stream.c mask = (1 << hstream->index); mask 144 sound/soc/sof/intel/hda-stream.c SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask, mask 330 sound/soc/sof/intel/hda-stream.c u32 val, mask; mask 339 sound/soc/sof/intel/hda-stream.c mask = 0x1 << hstream->index; mask 341 sound/soc/sof/intel/hda-stream.c mask, mask); mask 461 sound/soc/sof/intel/hda-stream.c mask, 0); mask 471 sound/soc/sof/intel/hda-stream.c mask, mask); mask 524 sound/soc/sof/intel/hda-stream.c u32 mask = 0x1 << stream->index; mask 530 sound/soc/sof/intel/hda-stream.c SOF_HDA_REG_PP_PPCTL, mask, 0); mask 16 sound/soc/sof/ops.c u32 mask, u32 value) mask 24 sound/soc/sof/ops.c dev_dbg(sdev->dev, "Debug PCIR: %8.8x at %8.8x\n", old & mask, offset); mask 26 sound/soc/sof/ops.c new = (old & ~mask) | (value & mask); mask 39 sound/soc/sof/ops.c u32 mask, u32 value) mask 45 sound/soc/sof/ops.c change = snd_sof_pci_update_bits_unlocked(sdev, offset, mask, value); mask 52 sound/soc/sof/ops.c u32 offset, u32 mask, u32 value) mask 60 sound/soc/sof/ops.c new = (old & ~mask) | (value & mask); mask 72 sound/soc/sof/ops.c u32 offset, u64 mask, u64 value) mask 78 sound/soc/sof/ops.c new = (old & ~mask) | (value & mask); mask 91 sound/soc/sof/ops.c u32 mask, u32 value) mask 97 sound/soc/sof/ops.c change = snd_sof_dsp_update_bits_unlocked(sdev, bar, offset, mask, mask 105 sound/soc/sof/ops.c u64 mask, u64 value) mask 111 sound/soc/sof/ops.c change = snd_sof_dsp_update_bits64_unlocked(sdev, bar, offset, mask, mask 120 sound/soc/sof/ops.c u32 offset, u32 mask, u32 value) mask 128 sound/soc/sof/ops.c new = (old & ~mask) | (value & mask); mask 135 sound/soc/sof/ops.c u32 offset, u32 mask, u32 value) mask 140 sound/soc/sof/ops.c snd_sof_dsp_update_bits_forced_unlocked(sdev, bar, offset, mask, value); mask 445 sound/soc/sof/ops.h u32 mask, u32 value); mask 448 sound/soc/sof/ops.h u32 offset, u32 mask, u32 value); mask 451 sound/soc/sof/ops.h u32 offset, u64 mask, u64 value); mask 454 sound/soc/sof/ops.h u32 mask, u32 value); mask 457 sound/soc/sof/ops.h u32 offset, u64 mask, u64 value); mask 460 sound/soc/sof/ops.h u32 offset, u32 mask, u32 value); mask 463 sound/soc/sof/ops.h u32 mask, u32 target, u32 timeout_ms, mask 119 sound/soc/sprd/sprd-mcdt.c u32 mask) mask 124 sound/soc/sprd/sprd-mcdt.c tmp = (orig & ~mask) | val; mask 140 sound/soc/sti/sti_uniperif.c uni->tdm_slot.mask = (tx_mask != 0) ? tx_mask : rx_mask; mask 144 sound/soc/sti/sti_uniperif.c if ((uni->tdm_slot.mask >> i) & 0x01) mask 214 sound/soc/sti/sti_uniperif.c unsigned int slots_mask = uni->tdm_slot.mask; mask 19 sound/soc/sti/uniperif.h #define GET_UNIPERIF_REG(ip, offset, shift, mask) \ mask 20 sound/soc/sti/uniperif.h ((readl_relaxed(ip->base + offset) >> shift) & mask) mask 21 sound/soc/sti/uniperif.h #define SET_UNIPERIF_REG(ip, offset, shift, mask, value) \ mask 23 sound/soc/sti/uniperif.h ~(mask << shift)) | (((value) & mask) << shift)), ip->base + offset) mask 24 sound/soc/sti/uniperif.h #define SET_UNIPERIF_BIT_REG(ip, offset, shift, mask, value) \ mask 25 sound/soc/sti/uniperif.h writel_relaxed((((value) & mask) << shift), ip->base + offset) mask 1287 sound/soc/sti/uniperif.h unsigned int mask; mask 188 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int mask, mask 197 sound/soc/stm/stm32_sai_sub.c ret = regmap_update_bits(sai->regmap, reg, mask, val); mask 205 sound/soc/stm/stm32_sai_sub.c unsigned int reg, unsigned int mask, mask 214 sound/soc/stm/stm32_sai_sub.c ret = regmap_write_bits(sai->regmap, reg, mask, val); mask 339 sound/soc/stm/stm32_sai_sub.c int ret, cr1, mask; mask 346 sound/soc/stm/stm32_sai_sub.c mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); mask 348 sound/soc/stm/stm32_sai_sub.c ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); mask 1248 sound/soc/stm/stm32_sai_sub.c unsigned int mask; mask 1255 sound/soc/stm/stm32_sai_sub.c mask = 1 << (frm_cnt - (byte << 3)); mask 1256 sound/soc/stm/stm32_sai_sub.c if (sai->iec958.status[byte] & mask) mask 667 sound/soc/stm/stm32_spdifrx.c unsigned int cr, mask, sr, imr; mask 674 sound/soc/stm/stm32_spdifrx.c mask = imr & SPDIFRX_XIMR_MASK; mask 676 sound/soc/stm/stm32_spdifrx.c if (mask & SPDIFRX_IMR_IFEIE) mask 677 sound/soc/stm/stm32_spdifrx.c mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2); mask 679 sound/soc/stm/stm32_spdifrx.c flags = sr & mask; mask 63 sound/soc/tegra/tegra20_i2s.c unsigned int mask = 0, val = 0; mask 72 sound/soc/tegra/tegra20_i2s.c mask |= TEGRA20_I2S_CTRL_MASTER_ENABLE; mask 83 sound/soc/tegra/tegra20_i2s.c mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | mask 110 sound/soc/tegra/tegra20_i2s.c regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); mask 121 sound/soc/tegra/tegra20_i2s.c unsigned int mask, val; mask 124 sound/soc/tegra/tegra20_i2s.c mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK; mask 142 sound/soc/tegra/tegra20_i2s.c mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK; mask 145 sound/soc/tegra/tegra20_i2s.c regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val); mask 56 sound/soc/tegra/tegra20_spdif.c unsigned int mask = 0, val = 0; mask 59 sound/soc/tegra/tegra20_spdif.c mask |= TEGRA20_SPDIF_CTRL_PACK | mask 70 sound/soc/tegra/tegra20_spdif.c regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val); mask 69 sound/soc/tegra/tegra30_i2s.c unsigned int mask = 0, val = 0; mask 78 sound/soc/tegra/tegra30_i2s.c mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE; mask 89 sound/soc/tegra/tegra30_i2s.c mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK | mask 117 sound/soc/tegra/tegra30_i2s.c regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); mask 129 sound/soc/tegra/tegra30_i2s.c unsigned int mask, val, reg; mask 136 sound/soc/tegra/tegra30_i2s.c mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK; mask 146 sound/soc/tegra/tegra30_i2s.c regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val); mask 74 sound/soc/tegra/tegra_alc5632.c .mask = SND_JACK_MICROPHONE, mask 78 sound/soc/tegra/tegra_alc5632.c .mask = SND_JACK_HEADPHONE, mask 94 sound/soc/tegra/tegra_max98090.c .mask = SND_JACK_HEADPHONE, mask 110 sound/soc/tegra/tegra_max98090.c .mask = SND_JACK_MICROPHONE, mask 77 sound/soc/tegra/tegra_rt5640.c .mask = SND_JACK_HEADPHONE, mask 93 sound/soc/tegra/tegra_rt5677.c .mask = SND_JACK_HEADPHONE, mask 105 sound/soc/tegra/tegra_rt5677.c .mask = SND_JACK_MICROPHONE, mask 94 sound/soc/tegra/tegra_wm8903.c .mask = SND_JACK_HEADPHONE, mask 110 sound/soc/tegra/tegra_wm8903.c .mask = SND_JACK_MICROPHONE, mask 231 sound/soc/ti/ams-delta.c .mask = SND_JACK_MICROPHONE, mask 235 sound/soc/ti/ams-delta.c .mask = SND_JACK_HEADPHONE, mask 240 sound/soc/ti/ams-delta.c .mask = SND_JACK_MICROPHONE, mask 245 sound/soc/ti/ams-delta.c .mask = SND_JACK_HEADPHONE, mask 192 sound/soc/ti/davinci-i2s.c u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; mask 196 sound/soc/ti/davinci-i2s.c spcr |= mask; mask 531 sound/soc/ti/davinci-i2s.c u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; mask 536 sound/soc/ti/davinci-i2s.c if (spcr & mask) { mask 539 sound/soc/ti/davinci-i2s.c spcr & ~mask); mask 142 sound/soc/ti/davinci-mcasp.c u32 val, u32 mask) mask 145 sound/soc/ti/davinci-mcasp.c __raw_writel((__raw_readl(reg) & ~mask) | val, reg); mask 766 sound/soc/ti/davinci-mcasp.c u32 mask = (1ULL << sample_width) - 1; mask 804 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); mask 807 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); mask 942 sound/soc/ti/davinci-mcasp.c u32 mask = 0; mask 961 sound/soc/ti/davinci-mcasp.c mask |= (1 << i); mask 974 sound/soc/ti/davinci-mcasp.c mask |= (1 << i); mask 983 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); mask 988 sound/soc/ti/davinci-mcasp.c mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); mask 28 sound/soc/ti/davinci-vcif.c #define MOD_REG_BIT(val, mask, set) do { \ mask 30 sound/soc/ti/davinci-vcif.c val |= mask; \ mask 32 sound/soc/ti/davinci-vcif.c val &= ~mask; \ mask 110 sound/soc/ti/omap-abe-twl6040.c .mask = SND_JACK_MICROPHONE, mask 114 sound/soc/ti/omap-abe-twl6040.c .mask = SND_JACK_HEADPHONE, mask 122 sound/soc/ti/omap-twl4030.c .mask = SND_JACK_MICROPHONE, mask 126 sound/soc/ti/omap-twl4030.c .mask = SND_JACK_HEADPHONE, mask 348 sound/soc/txx9/txx9aclc.c dma_cap_mask_t mask; mask 362 sound/soc/txx9/txx9aclc.c dma_cap_zero(mask); mask 363 sound/soc/txx9/txx9aclc.c dma_cap_set(DMA_SLAVE, mask); mask 364 sound/soc/txx9/txx9aclc.c dmadata->dma_chan = dma_request_channel(mask, filter, dmadata); mask 501 sound/soc/ux500/ux500_msp_dai.c unsigned int mask, slots_active; mask 517 sound/soc/ux500/ux500_msp_dai.c mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? mask 521 sound/soc/ux500/ux500_msp_dai.c slots_active = hweight32(mask); mask 434 sound/soc/ux500/ux500_msp_i2s.c u32 old_reg, new_reg, mask; mask 467 sound/soc/ux500/ux500_msp_i2s.c mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK | mask 480 sound/soc/ux500/ux500_msp_i2s.c old_reg &= ~mask; mask 200 sound/soc/zte/zx-tdm.c unsigned int mask = 0; mask 221 sound/soc/zte/zx-tdm.c zx_tdm_writel(tdm, REG_TS_MASK0, mask); mask 307 sound/sparc/cs4231.c unsigned char mask, unsigned char value) mask 309 sound/sparc/cs4231.c unsigned char tmp = (chip->image[reg] & mask) | value; mask 1339 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1341 sound/sparc/cs4231.c uinfo->type = (mask == 1) ? mask 1345 sound/sparc/cs4231.c uinfo->value.integer.max = mask; mask 1357 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1362 sound/sparc/cs4231.c ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; mask 1368 sound/sparc/cs4231.c (mask - ucontrol->value.integer.value[0]); mask 1380 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 1385 sound/sparc/cs4231.c val = (ucontrol->value.integer.value[0] & mask); mask 1387 sound/sparc/cs4231.c val = mask - val; mask 1392 sound/sparc/cs4231.c val = (chip->image[reg] & ~(mask << shift)) | val; mask 1404 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1406 sound/sparc/cs4231.c uinfo->type = mask == 1 ? mask 1410 sound/sparc/cs4231.c uinfo->value.integer.max = mask; mask 1424 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1430 sound/sparc/cs4231.c (chip->image[left_reg] >> shift_left) & mask; mask 1432 sound/sparc/cs4231.c (chip->image[right_reg] >> shift_right) & mask; mask 1438 sound/sparc/cs4231.c (mask - ucontrol->value.integer.value[0]); mask 1440 sound/sparc/cs4231.c (mask - ucontrol->value.integer.value[1]); mask 1455 sound/sparc/cs4231.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 1460 sound/sparc/cs4231.c val1 = ucontrol->value.integer.value[0] & mask; mask 1461 sound/sparc/cs4231.c val2 = ucontrol->value.integer.value[1] & mask; mask 1463 sound/sparc/cs4231.c val1 = mask - val1; mask 1464 sound/sparc/cs4231.c val2 = mask - val2; mask 1471 sound/sparc/cs4231.c val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; mask 1472 sound/sparc/cs4231.c val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; mask 1483 sound/sparc/cs4231.c #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ mask 1487 sound/sparc/cs4231.c .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) } mask 1490 sound/sparc/cs4231.c shift_right, mask, invert) \ mask 1495 sound/sparc/cs4231.c ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) } mask 2330 sound/sparc/dbri.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2332 sound/sparc/dbri.c uinfo->type = (mask == 1) ? mask 2336 sound/sparc/dbri.c uinfo->value.integer.max = mask; mask 2346 sound/sparc/dbri.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2354 sound/sparc/dbri.c (dbri->mm.data[elem] >> shift) & mask; mask 2357 sound/sparc/dbri.c (dbri->mm.ctrl[elem - 4] >> shift) & mask; mask 2361 sound/sparc/dbri.c mask - ucontrol->value.integer.value[0]; mask 2371 sound/sparc/dbri.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 2379 sound/sparc/dbri.c val = (ucontrol->value.integer.value[0] & mask); mask 2381 sound/sparc/dbri.c val = mask - val; mask 2386 sound/sparc/dbri.c ~(mask << shift)) | val; mask 2390 sound/sparc/dbri.c ~(mask << shift)) | val; mask 2396 sound/sparc/dbri.c mask, changed, ucontrol->value.integer.value[0], mask 2414 sound/sparc/dbri.c #define CS4215_SINGLE(xname, entry, shift, mask, invert) \ mask 2418 sound/sparc/dbri.c .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ mask 407 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 413 sound/spi/at73c213.c (chip->reg_image[reg] >> shift) & mask; mask 417 sound/spi/at73c213.c mask - ucontrol->value.integer.value[0]; mask 430 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 435 sound/spi/at73c213.c val = (ucontrol->value.integer.value[0] & mask); mask 437 sound/spi/at73c213.c val = mask - val; mask 442 sound/spi/at73c213.c val = (chip->reg_image[reg] & ~(mask << shift)) | val; mask 457 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 459 sound/spi/at73c213.c if (mask == 1) mask 466 sound/spi/at73c213.c uinfo->value.integer.max = mask; mask 479 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 485 sound/spi/at73c213.c (chip->reg_image[left_reg] >> shift_left) & mask; mask 487 sound/spi/at73c213.c (chip->reg_image[right_reg] >> shift_right) & mask; mask 491 sound/spi/at73c213.c mask - ucontrol->value.integer.value[0]; mask 493 sound/spi/at73c213.c mask - ucontrol->value.integer.value[1]; mask 509 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 24) & 0xff; mask 514 sound/spi/at73c213.c val1 = ucontrol->value.integer.value[0] & mask; mask 515 sound/spi/at73c213.c val2 = ucontrol->value.integer.value[1] & mask; mask 517 sound/spi/at73c213.c val1 = mask - val1; mask 518 sound/spi/at73c213.c val2 = mask - val2; mask 525 sound/spi/at73c213.c val1 = (chip->reg_image[left_reg] & ~(mask << shift_left)) | val1; mask 526 sound/spi/at73c213.c val2 = (chip->reg_image[right_reg] & ~(mask << shift_right)) | val2; mask 578 sound/spi/at73c213.c int mask = (kcontrol->private_value >> 16) & 0xff; mask 584 sound/spi/at73c213.c val = mask; mask 589 sound/spi/at73c213.c val = mask - val; mask 594 sound/spi/at73c213.c val |= (chip->reg_image[reg] & ~(mask << shift)); mask 644 sound/spi/at73c213.c #define AT73C213_MONO_SWITCH(xname, xindex, reg, shift, mask, invert) \ mask 652 sound/spi/at73c213.c .private_value = (reg | (shift << 8) | (mask << 16) | (invert << 24)) \ mask 655 sound/spi/at73c213.c #define AT73C213_STEREO(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ mask 665 sound/spi/at73c213.c | (mask << 24) | (invert << 22)) \ mask 69 sound/usb/hiface/pcm.c .mask = 0, mask 1932 sound/usb/mixer.c unsigned int mask; mask 1934 sound/usb/mixer.c mask = snd_usb_combine_bytes(bmaControls + mask 1936 sound/usb/mixer.c if (mask & (1 << i)) mask 1959 sound/usb/mixer.c unsigned int mask; mask 1961 sound/usb/mixer.c mask = snd_usb_combine_bytes(bmaControls + mask 1963 sound/usb/mixer.c if (uac_v2v3_control_is_readable(mask, control)) { mask 1965 sound/usb/mixer.c if (!uac_v2v3_control_is_writeable(mask, control)) mask 1212 sound/usb/pcm.c subs->rate_list.mask = 0; mask 1168 sound/usb/quirks.c unsigned int mask; mask 1173 sound/usb/quirks.c mask = chip->setup & MAUDIO_SET_MASK; mask 1174 sound/usb/quirks.c if (mask == MAUDIO_SET_24B_48K_DI && altno != 2) mask 1176 sound/usb/quirks.c if (mask == MAUDIO_SET_24B_48K_NOTDI && altno != 3) mask 1178 sound/usb/quirks.c if (mask == MAUDIO_SET_16B_48K_NOTDI && altno != 4) mask 1198 sound/usb/quirks.c unsigned int mask; mask 1203 sound/usb/quirks.c mask = chip->setup & MAUDIO_SET_MASK; mask 1204 sound/usb/quirks.c if (mask == MAUDIO_SET_24B_48K_DI && altno != 2) mask 1206 sound/usb/quirks.c if (mask == MAUDIO_SET_24B_48K_NOTDI && altno != 3) mask 1208 sound/usb/quirks.c if (mask == MAUDIO_SET_16B_48K_DI && altno != 4) mask 1210 sound/usb/quirks.c if (mask == MAUDIO_SET_16B_48K_NOTDI && altno != 5) mask 266 sound/usb/usx2y/us122l.c __poll_t mask; mask 270 sound/usb/usx2y/us122l.c mask = EPOLLIN | EPOLLOUT | EPOLLWRNORM | EPOLLERR; mask 280 sound/usb/usx2y/us122l.c mask = EPOLLIN | EPOLLOUT | EPOLLWRNORM; mask 282 sound/usb/usx2y/us122l.c mask = 0; mask 286 sound/usb/usx2y/us122l.c return mask; mask 79 sound/usb/usx2y/usX2Yhwdep.c __poll_t mask = 0; mask 88 sound/usb/usx2y/usX2Yhwdep.c mask |= EPOLLIN; mask 90 sound/usb/usx2y/usX2Yhwdep.c return mask; mask 193 sound/xen/xen_snd_front_alsa.c u64 mask; mask 196 sound/xen/xen_snd_front_alsa.c mask = 0; mask 199 sound/xen/xen_snd_front_alsa.c mask |= BIT_ULL(ALSA_SNDIF_FORMATS[i].sndif); mask 201 sound/xen/xen_snd_front_alsa.c return mask; mask 206 sound/xen/xen_snd_front_alsa.c u64 mask; mask 209 sound/xen/xen_snd_front_alsa.c mask = 0; mask 212 sound/xen/xen_snd_front_alsa.c mask |= pcm_format_to_bits(ALSA_SNDIF_FORMATS[i].alsa); mask 214 sound/xen/xen_snd_front_alsa.c return mask; mask 276 sound/xen/xen_snd_front_alsa.c struct snd_mask mask; mask 310 sound/xen/xen_snd_front_alsa.c snd_mask_none(&mask); mask 311 sound/xen/xen_snd_front_alsa.c mask.bits[0] = (u32)sndif_formats; mask 312 sound/xen/xen_snd_front_alsa.c mask.bits[1] = (u32)(sndif_formats >> 32); mask 313 sound/xen/xen_snd_front_alsa.c ret = snd_mask_refine(formats, &mask); mask 23 sound/xen/xen_snd_front_cfg.c unsigned int mask; mask 28 sound/xen/xen_snd_front_cfg.c { .name = "5512", .mask = SNDRV_PCM_RATE_5512, .value = 5512 }, mask 29 sound/xen/xen_snd_front_cfg.c { .name = "8000", .mask = SNDRV_PCM_RATE_8000, .value = 8000 }, mask 30 sound/xen/xen_snd_front_cfg.c { .name = "11025", .mask = SNDRV_PCM_RATE_11025, .value = 11025 }, mask 31 sound/xen/xen_snd_front_cfg.c { .name = "16000", .mask = SNDRV_PCM_RATE_16000, .value = 16000 }, mask 32 sound/xen/xen_snd_front_cfg.c { .name = "22050", .mask = SNDRV_PCM_RATE_22050, .value = 22050 }, mask 33 sound/xen/xen_snd_front_cfg.c { .name = "32000", .mask = SNDRV_PCM_RATE_32000, .value = 32000 }, mask 34 sound/xen/xen_snd_front_cfg.c { .name = "44100", .mask = SNDRV_PCM_RATE_44100, .value = 44100 }, mask 35 sound/xen/xen_snd_front_cfg.c { .name = "48000", .mask = SNDRV_PCM_RATE_48000, .value = 48000 }, mask 36 sound/xen/xen_snd_front_cfg.c { .name = "64000", .mask = SNDRV_PCM_RATE_64000, .value = 64000 }, mask 37 sound/xen/xen_snd_front_cfg.c { .name = "96000", .mask = SNDRV_PCM_RATE_96000, .value = 96000 }, mask 38 sound/xen/xen_snd_front_cfg.c { .name = "176400", .mask = SNDRV_PCM_RATE_176400, .value = 176400 }, mask 39 sound/xen/xen_snd_front_cfg.c { .name = "192000", .mask = SNDRV_PCM_RATE_192000, .value = 192000 }, mask 44 sound/xen/xen_snd_front_cfg.c u64 mask; mask 50 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U8 mask 54 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S8 mask 58 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U16_LE mask 62 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U16_BE mask 66 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S16_LE mask 70 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S16_BE mask 74 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U24_LE mask 78 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U24_BE mask 82 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S24_LE mask 86 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S24_BE mask 90 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U32_LE mask 94 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_U32_BE mask 98 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S32_LE mask 102 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_S32_BE mask 106 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_A_LAW mask 110 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_MU_LAW mask 114 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_FLOAT_LE mask 118 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_FLOAT_BE mask 122 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_FLOAT64_LE mask 126 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_FLOAT64_BE mask 130 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE mask 134 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE mask 138 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_IMA_ADPCM mask 142 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_MPEG mask 146 sound/xen/xen_snd_front_cfg.c .mask = SNDRV_PCM_FMTBIT_GSM mask 169 sound/xen/xen_snd_front_cfg.c cur_mask = CFG_HW_SUPPORTED_RATES[i].mask; mask 199 sound/xen/xen_snd_front_cfg.c formats |= CFG_HW_SUPPORTED_FORMATS[i].mask; mask 66 tools/arch/s390/include/uapi/asm/kvm.h __u8 mask; mask 212 tools/arch/s390/include/uapi/asm/ptrace.h unsigned long mask; mask 230 tools/arch/s390/include/uapi/asm/sie.h #define INSN_DECODE_IPA0(ipa0, insn, rshift, mask) \ mask 232 tools/arch/s390/include/uapi/asm/sie.h ((ipa0 << 8) | ((insn >> rshift) & mask)) : mask 100 tools/arch/x86/include/uapi/asm/kvm.h __u8 mask:1; mask 647 tools/firewire/nosy-dump.c uint32_t index, shift, mask; mask 651 tools/firewire/nosy-dump.c mask = width == 32 ? ~0 : (1 << width) - 1; mask 653 tools/firewire/nosy-dump.c return (data[index] >> shift) & mask; mask 24 tools/firmware/ihex2fw.c #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) mask 28 tools/gpio/lsgpio.c unsigned long mask; mask 34 tools/gpio/lsgpio.c .mask = GPIOLINE_FLAG_KERNEL, mask 38 tools/gpio/lsgpio.c .mask = GPIOLINE_FLAG_IS_OUT, mask 42 tools/gpio/lsgpio.c .mask = GPIOLINE_FLAG_ACTIVE_LOW, mask 46 tools/gpio/lsgpio.c .mask = GPIOLINE_FLAG_OPEN_DRAIN, mask 50 tools/gpio/lsgpio.c .mask = GPIOLINE_FLAG_OPEN_SOURCE, mask 60 tools/gpio/lsgpio.c if (flags & flagnames[i].mask) { mask 78 tools/iio/iio_generic_buffer.c input &= info->mask; mask 101 tools/iio/iio_generic_buffer.c input &= info->mask; mask 124 tools/iio/iio_generic_buffer.c input &= info->mask; mask 147 tools/iio/iio_generic_buffer.c input &= info->mask; mask 86 tools/iio/iio_utils.c unsigned *shift, uint64_t *mask, unsigned *be, mask 159 tools/iio/iio_utils.c *mask = ~(0ULL); mask 161 tools/iio/iio_utils.c *mask = (1ULL << *bits_used) - 1ULL; mask 502 tools/iio/iio_utils.c ¤t->mask, mask 46 tools/iio/iio_utils.h uint64_t mask; mask 61 tools/iio/iio_utils.h unsigned *shift, uint64_t *mask, unsigned *be, mask 18 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 21 tools/include/asm-generic/bitops/non-atomic.h *p |= mask; mask 26 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 29 tools/include/asm-generic/bitops/non-atomic.h *p &= ~mask; mask 43 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 46 tools/include/asm-generic/bitops/non-atomic.h *p ^= mask; mask 60 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 64 tools/include/asm-generic/bitops/non-atomic.h *p = old | mask; mask 65 tools/include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 79 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 83 tools/include/asm-generic/bitops/non-atomic.h *p = old & ~mask; mask 84 tools/include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 91 tools/include/asm-generic/bitops/non-atomic.h unsigned long mask = BIT_MASK(nr); mask 95 tools/include/asm-generic/bitops/non-atomic.h *p = old ^ mask; mask 96 tools/include/asm-generic/bitops/non-atomic.h return (old & mask) != 0; mask 90 tools/include/linux/bitmap.h unsigned long mask = BIT_MASK(nr); mask 95 tools/include/linux/bitmap.h *p = old | mask; mask 97 tools/include/linux/bitmap.h return (old & mask) != 0; mask 107 tools/include/linux/bitmap.h unsigned long mask = BIT_MASK(nr); mask 112 tools/include/linux/bitmap.h *p = old & ~mask; mask 114 tools/include/linux/bitmap.h return (old & mask) != 0; mask 19 tools/include/linux/kernel.h #define __PERF_ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) mask 382 tools/include/uapi/linux/if_link.h __u32 mask; mask 1028 tools/include/uapi/linux/if_link.h __u32 mask; mask 183 tools/include/uapi/linux/kvm.h __u64 mask; mask 544 tools/include/uapi/linux/kvm.h __u64 mask; mask 166 tools/include/uapi/linux/pkt_cls.h __be32 mask; mask 188 tools/include/uapi/linux/pkt_cls.h __u32 mask; mask 225 tools/include/uapi/linux/pkt_cls.h __u32 mask; mask 1013 tools/include/uapi/sound/asound.h unsigned int mask; mask 15 tools/io_uring/queue.c const unsigned mask = *cq->kring_mask; mask 31 tools/io_uring/queue.c *cqe_ptr = &cq->cqes[head & mask]; mask 71 tools/io_uring/queue.c const unsigned mask = *sq->kring_mask; mask 99 tools/io_uring/queue.c sq->array[ktail & mask] = sq->sqe_head & mask; mask 5908 tools/lib/bpf/libbpf.c int parse_cpu_mask_str(const char *s, bool **mask, int *mask_sz) mask 5913 tools/lib/bpf/libbpf.c *mask = NULL; mask 5936 tools/lib/bpf/libbpf.c tmp = realloc(*mask, end + 1); mask 5941 tools/lib/bpf/libbpf.c *mask = tmp; mask 5953 tools/lib/bpf/libbpf.c free(*mask); mask 5954 tools/lib/bpf/libbpf.c *mask = NULL; mask 5958 tools/lib/bpf/libbpf.c int parse_cpu_mask_file(const char *fcpu, bool **mask, int *mask_sz) mask 5982 tools/lib/bpf/libbpf.c return parse_cpu_mask_str(buf, mask, mask_sz); mask 5990 tools/lib/bpf/libbpf.c bool *mask; mask 5996 tools/lib/bpf/libbpf.c err = parse_cpu_mask_file(fcpu, &mask, &n); mask 6002 tools/lib/bpf/libbpf.c if (mask[i]) mask 6005 tools/lib/bpf/libbpf.c free(mask); mask 66 tools/lib/bpf/libbpf_internal.h int parse_cpu_mask_str(const char *s, bool **mask, int *mask_sz); mask 67 tools/lib/bpf/libbpf_internal.h int parse_cpu_mask_file(const char *fcpu, bool **mask, int *mask_sz); mask 258 tools/lib/bpf/netlink.c __u32 mask; mask 265 tools/lib/bpf/netlink.c mask = flags - 1; mask 266 tools/lib/bpf/netlink.c if (flags && flags & mask) mask 274 tools/lib/bpf/xsk.c fill->mask = umem->config.fill_size - 1; mask 291 tools/lib/bpf/xsk.c comp->mask = umem->config.comp_size - 1; mask 641 tools/lib/bpf/xsk.c rx->mask = xsk->config.rx_size - 1; mask 660 tools/lib/bpf/xsk.c tx->mask = xsk->config.tx_size - 1; mask 30 tools/lib/bpf/xsk.h __u32 mask; \ mask 53 tools/lib/bpf/xsk.h return &addrs[idx & fill->mask]; mask 61 tools/lib/bpf/xsk.h return &addrs[idx & comp->mask]; mask 69 tools/lib/bpf/xsk.h return &descs[idx & tx->mask]; mask 77 tools/lib/bpf/xsk.h return &descs[idx & rx->mask]; mask 60 tools/perf/arch/arm/tests/dwarf-unwind.c regs->mask = PERF_REGS_MASK; mask 60 tools/perf/arch/arm64/tests/dwarf-unwind.c regs->mask = PERF_REGS_MASK; mask 61 tools/perf/arch/powerpc/tests/dwarf-unwind.c regs->mask = PERF_REGS_MASK; mask 61 tools/perf/arch/x86/tests/dwarf-unwind.c regs->mask = PERF_REGS_MASK; mask 393 tools/perf/arch/x86/util/intel-bts.c if (mm->mask) mask 394 tools/perf/arch/x86/util/intel-bts.c *old &= mm->mask; mask 96 tools/perf/arch/x86/util/intel-pt.c static u64 intel_pt_masked_bits(u64 mask, u64 bits) mask 103 tools/perf/arch/x86/util/intel-pt.c if (mask & top_bit) { mask 108 tools/perf/arch/x86/util/intel-pt.c mask <<= 1; mask 119 tools/perf/arch/x86/util/intel-pt.c u64 mask; mask 123 tools/perf/arch/x86/util/intel-pt.c mask = perf_pmu__format_bits(&intel_pt_pmu->format, str); mask 124 tools/perf/arch/x86/util/intel-pt.c if (!mask) mask 129 tools/perf/arch/x86/util/intel-pt.c *res = intel_pt_masked_bits(mask, evsel->core.attr.config); mask 1072 tools/perf/arch/x86/util/intel-pt.c if (mm->mask) mask 1073 tools/perf/arch/x86/util/intel-pt.c *old &= mm->mask; mask 265 tools/perf/bench/numa.c cpu_set_t orig_mask, mask; mask 271 tools/perf/bench/numa.c CPU_ZERO(&mask); mask 277 tools/perf/bench/numa.c CPU_SET(cpu, &mask); mask 280 tools/perf/bench/numa.c CPU_SET(target_cpu, &mask); mask 283 tools/perf/bench/numa.c ret = sched_setaffinity(0, sizeof(mask), &mask); mask 292 tools/perf/bench/numa.c cpu_set_t orig_mask, mask; mask 302 tools/perf/bench/numa.c CPU_ZERO(&mask); mask 306 tools/perf/bench/numa.c CPU_SET(cpu, &mask); mask 314 tools/perf/bench/numa.c CPU_SET(cpu, &mask); mask 317 tools/perf/bench/numa.c ret = sched_setaffinity(0, sizeof(mask), &mask); mask 323 tools/perf/bench/numa.c static void bind_to_cpumask(cpu_set_t mask) mask 327 tools/perf/bench/numa.c ret = sched_setaffinity(0, sizeof(mask), &mask); mask 588 tools/perf/builtin-script.c static int perf_sample__fprintf_regs(struct regs_dump *regs, uint64_t mask, mask 600 tools/perf/builtin-script.c for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { mask 1717 tools/perf/builtin-trace.c .mask = 0, mask 1736 tools/perf/builtin-trace.c if (arg.mask & bit) mask 1774 tools/perf/builtin-trace.c if (arg.mask & bit) mask 89 tools/perf/examples/bpf/augmented_syscalls.c long mask; mask 20 tools/perf/lib/include/internal/mmap.h int mask; mask 138 tools/perf/lib/include/perf/event.h unsigned long mask[]; mask 20 tools/perf/tests/cpumap.c struct perf_record_record_cpu_map *mask; mask 29 tools/perf/tests/cpumap.c mask = (struct perf_record_record_cpu_map *)data->data; mask 31 tools/perf/tests/cpumap.c TEST_ASSERT_VAL("wrong nr", mask->nr == 1); mask 34 tools/perf/tests/cpumap.c TEST_ASSERT_VAL("wrong cpu", test_bit(i, mask->mask)); mask 107 tools/perf/tests/sample-parsing.c size_t sz = hweight_long(s1->user_regs.mask) * sizeof(u64); mask 109 tools/perf/tests/sample-parsing.c COMP(user_regs.mask); mask 138 tools/perf/tests/sample-parsing.c size_t sz = hweight_long(s1->intr_regs.mask) * sizeof(u64); mask 140 tools/perf/tests/sample-parsing.c COMP(intr_regs.mask); mask 204 tools/perf/tests/sample-parsing.c .mask = sample_regs, mask 217 tools/perf/tests/sample-parsing.c .mask = sample_regs, mask 105 tools/perf/trace/beauty/beauty.h u8 mask; mask 67 tools/perf/trace/beauty/clone.c arg->mask |= SCC_PARENT_TIDPTR; mask 70 tools/perf/trace/beauty/clone.c arg->mask |= SCC_CHILD_TIDPTR; mask 73 tools/perf/trace/beauty/clone.c arg->mask |= SCC_TLS; mask 64 tools/perf/trace/beauty/fcntl.c arg->mask |= (1 << 2); mask 38 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(WAIT); arg->mask |= SCF_VAL3|SCF_UADDR2; break; mask 39 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(WAKE); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break; mask 40 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(FD); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break; mask 41 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(REQUEUE); arg->mask |= SCF_VAL3|SCF_TIMEOUT; break; mask 42 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(CMP_REQUEUE); arg->mask |= SCF_TIMEOUT; break; mask 43 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(CMP_REQUEUE_PI); arg->mask |= SCF_TIMEOUT; break; mask 45 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(LOCK_PI); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break; mask 46 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(UNLOCK_PI); arg->mask |= SCF_VAL3|SCF_UADDR2|SCF_TIMEOUT; break; mask 47 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(TRYLOCK_PI); arg->mask |= SCF_VAL3|SCF_UADDR2; break; mask 48 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(WAIT_BITSET); arg->mask |= SCF_UADDR2; break; mask 49 tools/perf/trace/beauty/futex_op.c P_FUTEX_OP(WAKE_BITSET); arg->mask |= SCF_UADDR2; break; mask 40 tools/perf/trace/beauty/kcmp.c arg->mask |= (1 << 3) | (1 << 4); /* Ignore idx1 and idx2 */ mask 50 tools/perf/trace/beauty/mmap.c arg->mask |= (1 << 4) | (1 << 5); /* Mask 4th ('fd') and 5th ('offset') args, ignored */ mask 85 tools/perf/trace/beauty/open_flags.c arg->mask |= 1 << (arg->idx + 1); /* Mask the mode parm */ mask 78 tools/perf/trace/beauty/prctl.c arg->mask |= masks[option]; mask 75 tools/perf/util/auxtrace.c mm->mask = mp->mask; mask 121 tools/perf/util/auxtrace.c mp->mask = is_power_of_2(mp->len) ? mp->len - 1 : 0; mask 1258 tools/perf/util/auxtrace.c if (mm->mask) { mask 1259 tools/perf/util/auxtrace.c head_off = head & mm->mask; mask 1260 tools/perf/util/auxtrace.c old_off = old & mm->mask; mask 1276 tools/perf/util/auxtrace.c if (head > old || size <= head || mm->mask) { mask 274 tools/perf/util/auxtrace.h size_t mask; mask 294 tools/perf/util/auxtrace.h size_t mask; mask 45 tools/perf/util/cpumap.c static struct perf_cpu_map *cpu_map__from_mask(struct perf_record_record_cpu_map *mask) mask 48 tools/perf/util/cpumap.c int nr, nbits = mask->nr * mask->long_size * BITS_PER_BYTE; mask 50 tools/perf/util/cpumap.c nr = bitmap_weight(mask->mask, nbits); mask 56 tools/perf/util/cpumap.c for_each_set_bit(cpu, mask->mask, nbits) mask 49 tools/perf/util/event.h u64 mask; mask 914 tools/perf/util/evlist.c mp.mask = evlist->core.mmap_len - page_size - 1; mask 107 tools/perf/util/evsel.c u64 mask = sample_type & PERF_SAMPLE_MASK; mask 112 tools/perf/util/evsel.c if (mask & (1ULL << i)) mask 2137 tools/perf/util/evsel.c u64 mask = evsel->core.attr.sample_regs_user; mask 2139 tools/perf/util/evsel.c sz = hweight64(mask) * sizeof(u64); mask 2141 tools/perf/util/evsel.c data->user_regs.mask = mask; mask 2193 tools/perf/util/evsel.c u64 mask = evsel->core.attr.sample_regs_intr; mask 2195 tools/perf/util/evsel.c sz = hweight64(mask) * sizeof(u64); mask 2197 tools/perf/util/evsel.c data->intr_regs.mask = mask; mask 665 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c uint32_t mask = ~(first_missing_bit - 1); mask 667 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c *last_mtc |= mtc & mask; mask 1629 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c memset(decoder->state.items.mask, 0, sizeof(decoder->state.items.mask)); mask 1639 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c } else if (decoder->state.items.mask[decoder->blk_type_pos]) { mask 1657 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c if (decoder->state.items.mask[pos] & bit) { mask 1662 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c decoder->state.items.mask[pos] |= bit; mask 118 tools/perf/util/intel-pt-decoder/intel-pt-decoder.h uint32_t mask[INTEL_PT_BLK_TYPE_CNT]; mask 1599 tools/perf/util/intel-pt.c u32 mask = items->mask[INTEL_PT_GP_REGS_POS]; mask 1614 tools/perf/util/intel-pt.c if (mask & 1 << n && regs_mask & bit) { mask 1615 tools/perf/util/intel-pt.c intr_regs->mask |= bit; mask 1631 tools/perf/util/intel-pt.c u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0); mask 1640 tools/perf/util/intel-pt.c intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0; mask 1642 tools/perf/util/intel-pt.c for (; mask; mask >>= 1, xmm++) { mask 1643 tools/perf/util/intel-pt.c if (mask & 1) mask 1683 tools/perf/util/intel-pt.c u32 mask = items->mask[i]; mask 1686 tools/perf/util/intel-pt.c for (; mask; mask >>= 3, from += 3) { mask 1687 tools/perf/util/intel-pt.c if ((mask & 7) == 7) { mask 1759 tools/perf/util/intel-pt.c items->mask[INTEL_PT_GP_REGS_POS]) { mask 1760 tools/perf/util/intel-pt.c u64 regs[sizeof(sample.intr_regs.mask)]; mask 1780 tools/perf/util/intel-pt.c if (items->mask[INTEL_PT_LBR_0_POS] || mask 1781 tools/perf/util/intel-pt.c items->mask[INTEL_PT_LBR_1_POS] || mask 1782 tools/perf/util/intel-pt.c items->mask[INTEL_PT_LBR_2_POS]) { mask 281 tools/perf/util/mem-events.c u64 mask = PERF_MEM_LOCK_NA; mask 285 tools/perf/util/mem-events.c mask = mem_info->data_src.mem_lock; mask 287 tools/perf/util/mem-events.c if (mask & PERF_MEM_LOCK_NA) mask 289 tools/perf/util/mem-events.c else if (mask & PERF_MEM_LOCK_LOCKED) mask 28 tools/perf/util/mmap.c return map->core.mask + 1 + page_size; mask 42 tools/perf/util/mmap.c event = (union perf_event *)&data[*startp & map->core.mask]; mask 52 tools/perf/util/mmap.c if ((*startp & map->core.mask) + size != ((*startp + size) & map->core.mask)) { mask 58 tools/perf/util/mmap.c cpy = min(map->core.mask + 1 - (offset & map->core.mask), len); mask 59 tools/perf/util/mmap.c memcpy(dst, &data[offset & map->core.mask], cpy); mask 330 tools/perf/util/mmap.c static void build_node_mask(int node, cpu_set_t *mask) mask 343 tools/perf/util/mmap.c CPU_SET(cpu, mask); mask 373 tools/perf/util/mmap.c map->core.mask = mp->mask; mask 409 tools/perf/util/mmap.c static int overwrite_rb_find_range(void *buf, int mask, u64 *start, u64 *end) mask 413 tools/perf/util/mmap.c int size = mask + 1; mask 416 tools/perf/util/mmap.c pheader = (struct perf_event_header *)(buf + (*start & mask)); mask 426 tools/perf/util/mmap.c pheader = (struct perf_event_header *)(buf + (evt_head & mask)); mask 458 tools/perf/util/mmap.c if (size > (unsigned long)(md->core.mask) + 1) { mask 471 tools/perf/util/mmap.c if (overwrite_rb_find_range(data, md->core.mask, &md->core.start, &md->core.end)) mask 504 tools/perf/util/mmap.c if ((md->core.start & md->core.mask) + size != (md->core.end & md->core.mask)) { mask 505 tools/perf/util/mmap.c buf = &data[md->core.start & md->core.mask]; mask 506 tools/perf/util/mmap.c size = md->core.mask + 1 - (md->core.start & md->core.mask); mask 515 tools/perf/util/mmap.c buf = &data[md->core.start & md->core.mask]; mask 40 tools/perf/util/mmap.h int prot, mask, nr_cblocks, affinity, flush, comp_level; mask 19 tools/perf/util/parse-regs-options.c uint64_t mask; mask 31 tools/perf/util/parse-regs-options.c mask = arch__intr_reg_mask(); mask 33 tools/perf/util/parse-regs-options.c mask = arch__user_reg_mask(); mask 50 tools/perf/util/parse-regs-options.c if (r->mask & mask) mask 58 tools/perf/util/parse-regs-options.c if ((r->mask & mask) && !strcasecmp(s, r->name)) mask 67 tools/perf/util/parse-regs-options.c *mode |= r->mask; mask 79 tools/perf/util/parse-regs-options.c *mode = mask; mask 30 tools/perf/util/perf_regs.c u64 mask = regs->mask; mask 35 tools/perf/util/perf_regs.c if (!(mask & (1ULL << id))) mask 39 tools/perf/util/perf_regs.c if (mask & (1ULL << i)) mask 12 tools/perf/util/perf_regs.h uint64_t mask; mask 14 tools/perf/util/perf_regs.h #define SMPL_REG(n, b) { .name = #n, .mask = 1ULL << (b) } mask 15 tools/perf/util/perf_regs.h #define SMPL_REG2(n, b) { .name = #n, .mask = 3ULL << (b) } mask 10 tools/perf/util/print_binary.c size_t i, j, mask; mask 17 tools/perf/util/print_binary.c mask = bytes_per_line - 1; mask 21 tools/perf/util/print_binary.c if ((i & mask) == 0) { mask 28 tools/perf/util/print_binary.c if (((i & mask) == mask) || i == len - 1) { mask 29 tools/perf/util/print_binary.c for (j = 0; j < mask-(i & mask); j++) mask 33 tools/perf/util/print_binary.c for (j = i & ~mask; j <= i; j++) mask 35 tools/perf/util/print_binary.c for (j = 0; j < mask-(i & mask); j++) mask 688 tools/perf/util/scripting-engines/trace-event-python.c static int regs_map(struct regs_dump *regs, uint64_t mask, char *bf, int size) mask 695 tools/perf/util/scripting-engines/trace-event-python.c for_each_set_bit(r, (unsigned long *) &mask, sizeof(mask) * 8) { mask 850 tools/perf/util/session.c struct perf_record_record_cpu_map *mask; mask 865 tools/perf/util/session.c mask = (struct perf_record_record_cpu_map *)data->data; mask 867 tools/perf/util/session.c mask->nr = bswap_16(mask->nr); mask 868 tools/perf/util/session.c mask->long_size = bswap_16(mask->long_size); mask 870 tools/perf/util/session.c switch (mask->long_size) { mask 871 tools/perf/util/session.c case 4: mem_bswap_32(&mask->mask, mask->nr); break; mask 872 tools/perf/util/session.c case 8: mem_bswap_64(&mask->mask, mask->nr); break; mask 1091 tools/perf/util/session.c static void regs_dump__printf(u64 mask, u64 *regs) mask 1095 tools/perf/util/session.c for_each_set_bit(rid, (unsigned long *) &mask, sizeof(mask) * 8) { mask 1119 tools/perf/util/session.c u64 mask = regs->mask; mask 1123 tools/perf/util/session.c mask, mask 1126 tools/perf/util/session.c regs_dump__printf(mask, regs->regs); mask 241 tools/perf/util/stat.c unsigned long *mask = counter->per_pkg_mask; mask 253 tools/perf/util/stat.c if (!mask) { mask 254 tools/perf/util/stat.c mask = zalloc(cpu__max_cpu()); mask 255 tools/perf/util/stat.c if (!mask) mask 258 tools/perf/util/stat.c counter->per_pkg_mask = mask; mask 276 tools/perf/util/stat.c *skip = test_and_set_bit(s, mask) == 1; mask 929 tools/perf/util/synthetic-events.c static void synthesize_mask(struct perf_record_record_cpu_map *mask, mask 934 tools/perf/util/synthetic-events.c mask->nr = BITS_TO_LONGS(max); mask 935 tools/perf/util/synthetic-events.c mask->long_size = sizeof(long); mask 938 tools/perf/util/synthetic-events.c set_bit(map->map[i], mask->mask); mask 1193 tools/perf/util/synthetic-events.c sz = hweight64(sample->user_regs.mask) * sizeof(u64); mask 1221 tools/perf/util/synthetic-events.c sz = hweight64(sample->intr_regs.mask) * sizeof(u64); mask 1350 tools/perf/util/synthetic-events.c sz = hweight64(sample->user_regs.mask) * sizeof(u64); mask 1386 tools/perf/util/synthetic-events.c sz = hweight64(sample->intr_regs.mask) * sizeof(u64); mask 126 tools/power/x86/intel-speed-select/isst-core.c unsigned long long mask; mask 139 tools/power/x86/intel-speed-select/isst-core.c mask = (unsigned long long)resp << (32 * i); mask 140 tools/power/x86/intel-speed-select/isst-core.c set_cpu_mask_from_punit_coremask(cpu, mask, mask 254 tools/power/x86/intel-speed-select/isst-core.c unsigned long long mask; mask 267 tools/power/x86/intel-speed-select/isst-core.c mask = (unsigned long long)resp << (32 * i); mask 268 tools/power/x86/intel-speed-select/isst-core.c set_cpu_mask_from_punit_coremask(cpu, mask, mask 42 tools/power/x86/intel-speed-select/isst-display.c unsigned int *mask; mask 49 tools/power/x86/intel-speed-select/isst-display.c mask = calloc(size, sizeof(unsigned int)); mask 50 tools/power/x86/intel-speed-select/isst-display.c if (!mask) mask 61 tools/power/x86/intel-speed-select/isst-display.c mask[mask_index] |= BIT(bit_index); mask 67 tools/power/x86/intel-speed-select/isst-display.c mask[i]); mask 75 tools/power/x86/intel-speed-select/isst-display.c free(mask); mask 616 tools/testing/nvdimm/test/nfit.c const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1; mask 620 tools/testing/nvdimm/test/nfit.c if ((clear_err->address & mask) || (clear_err->length & mask)) mask 2701 tools/testing/nvdimm/test/nfit.c unsigned long mask, cmd_size, offset; mask 2746 tools/testing/nvdimm/test/nfit.c mask = 1UL << ND_CMD_SMART | 1UL << ND_CMD_SMART_THRESHOLD mask 2753 tools/testing/nvdimm/test/nfit.c .dsm_mask = mask, mask 2761 tools/testing/nvdimm/test/nfit.c .cmd_mask = mask, mask 60 tools/testing/radix-tree/multiorder.c unsigned long mask = (1UL << order[i]) - 1; mask 62 tools/testing/radix-tree/multiorder.c assert((xas.xa_index | mask) == (index[i] | mask)); mask 65 tools/testing/radix-tree/multiorder.c assert((item->index | mask) == (index[i] | mask)); mask 109 tools/testing/radix-tree/multiorder.c unsigned long mask; mask 112 tools/testing/radix-tree/multiorder.c mask = (1UL << order[k]) - 1; mask 114 tools/testing/radix-tree/multiorder.c assert((xas.xa_index | mask) == (tag_index[i] | mask)); mask 116 tools/testing/radix-tree/multiorder.c assert((item->index | mask) == (tag_index[i] | mask)); mask 126 tools/testing/radix-tree/multiorder.c int mask, k; mask 139 tools/testing/radix-tree/multiorder.c mask = (1 << order[k]) - 1; mask 141 tools/testing/radix-tree/multiorder.c assert((xas.xa_index | mask) == (tag_index[i] | mask)); mask 143 tools/testing/radix-tree/multiorder.c assert((item->index | mask) == (tag_index[i] | mask)); mask 48 tools/testing/radix-tree/test.c unsigned long mask; mask 51 tools/testing/radix-tree/test.c mask = (1UL << item->order) - 1; mask 52 tools/testing/radix-tree/test.c assert((item->index | mask) == (index | mask)); mask 34 tools/testing/scatterlist/linux/mm.h #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) mask 9 tools/testing/selftests/bpf/bpf_rand.h static inline uint64_t bpf_rand_mask(uint64_t mask) mask 12 tools/testing/selftests/bpf/bpf_rand.h ((uint64_t)(uint32_t)rand() << 32)) & mask; mask 36 tools/testing/selftests/ir/ir_loopback.c unsigned int mask; mask 134 tools/testing/selftests/ir/ir_loopback.c unsigned int scancode = rand() & protocols[i].mask; mask 27 tools/testing/selftests/kvm/lib/aarch64/processor.c uint64_t mask = (1UL << (vm->va_bits - shift)) - 1; mask 29 tools/testing/selftests/kvm/lib/aarch64/processor.c return (gva >> shift) & mask; mask 35 tools/testing/selftests/kvm/lib/aarch64/processor.c uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; mask 40 tools/testing/selftests/kvm/lib/aarch64/processor.c return (gva >> shift) & mask; mask 46 tools/testing/selftests/kvm/lib/aarch64/processor.c uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; mask 51 tools/testing/selftests/kvm/lib/aarch64/processor.c return (gva >> shift) & mask; mask 56 tools/testing/selftests/kvm/lib/aarch64/processor.c uint64_t mask = (1UL << (vm->page_shift - 3)) - 1; mask 57 tools/testing/selftests/kvm/lib/aarch64/processor.c return (gva >> vm->page_shift) & mask; mask 62 tools/testing/selftests/kvm/lib/aarch64/processor.c uint64_t mask = ((1UL << (vm->va_bits - vm->page_shift)) - 1) << vm->page_shift; mask 63 tools/testing/selftests/kvm/lib/aarch64/processor.c return entry & mask; mask 25 tools/testing/selftests/kvm/lib/kvm_util.c size_t mask = size - 1; mask 28 tools/testing/selftests/kvm/lib/kvm_util.c return (void *) (((size_t) x + mask) & ~mask); mask 174 tools/testing/selftests/kvm/lib/sparsebit.c mask_t mask; mask 199 tools/testing/selftests/kvm/lib/sparsebit.c return nodep->num_after + __builtin_popcount(nodep->mask); mask 288 tools/testing/selftests/kvm/lib/sparsebit.c root->mask = subtree->mask; mask 387 tools/testing/selftests/kvm/lib/sparsebit.c assert(!(nodep->mask & (1 << n1))); mask 388 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask |= (1 << n1); mask 543 tools/testing/selftests/kvm/lib/sparsebit.c nodep2->mask = ~(mask_t) 0; mask 546 tools/testing/selftests/kvm/lib/sparsebit.c nodep2->mask = (1 << nodep2->num_after) - 1; mask 610 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask == 0 && nodep->num_after == 0) { mask 648 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask == 0) { mask 655 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask = ~0; mask 658 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask = (1u << nodep->num_after) - 1; mask 675 tools/testing/selftests/kvm/lib/sparsebit.c if (prev->mask == 0 && prev->num_after == 0) { mask 686 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask + 1 == 0 && mask 689 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask = 0; mask 703 tools/testing/selftests/kvm/lib/sparsebit.c (nodep->mask | (nodep->mask >> 1)) == nodep->mask) { mask 712 tools/testing/selftests/kvm/lib/sparsebit.c = __builtin_popcount(nodep->mask); mask 714 tools/testing/selftests/kvm/lib/sparsebit.c ((1ULL << num_contiguous) - 1) == nodep->mask); mask 717 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask = 0; mask 749 tools/testing/selftests/kvm/lib/sparsebit.c if (next->mask == 0 && next->num_after == 0) { mask 760 tools/testing/selftests/kvm/lib/sparsebit.c next->mask == ~(mask_t) 0) { mask 762 tools/testing/selftests/kvm/lib/sparsebit.c next->mask = 0; mask 799 tools/testing/selftests/kvm/lib/sparsebit.c return !!(nodep->mask & (1 << (idx - nodep->idx))); mask 822 tools/testing/selftests/kvm/lib/sparsebit.c assert(!(nodep->mask & (1 << (idx - nodep->idx)))); mask 823 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask |= 1 << (idx - nodep->idx); mask 857 tools/testing/selftests/kvm/lib/sparsebit.c assert(nodep->mask & (1 << (idx - nodep->idx))); mask 858 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask &= ~(1 << (idx - nodep->idx)); mask 890 tools/testing/selftests/kvm/lib/sparsebit.c indent, "", nodep->idx, nodep->mask, nodep->num_after); mask 904 tools/testing/selftests/kvm/lib/sparsebit.c int n1 = __builtin_ctz(nodep->mask & -leading); mask 912 tools/testing/selftests/kvm/lib/sparsebit.c int n1 = __builtin_ctz(~nodep->mask & -leading); mask 1065 tools/testing/selftests/kvm/lib/sparsebit.c assert(s->root->mask != 0); mask 1068 tools/testing/selftests/kvm/lib/sparsebit.c s->root->mask == ~(mask_t) 0)); mask 1114 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep1->mask != ~(mask_t) 0) mask 1128 tools/testing/selftests/kvm/lib/sparsebit.c assert(nodep1->mask == ~(mask_t) 0); mask 1196 tools/testing/selftests/kvm/lib/sparsebit.c assert(candidate->mask != 0); mask 1220 tools/testing/selftests/kvm/lib/sparsebit.c if (start < MASK_BITS && candidate->mask >= (1 << start)) mask 1269 tools/testing/selftests/kvm/lib/sparsebit.c if (!(nodep1->mask & (1 << idx))) mask 1431 tools/testing/selftests/kvm/lib/sparsebit.c if (!(nodep->mask & (1 << n1))) { mask 1432 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask |= 1 << n1; mask 1494 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask & (1 << n1)) { mask 1495 tools/testing/selftests/kvm/lib/sparsebit.c nodep->mask &= ~(1 << n1); mask 1607 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask & (1 << n1)) { mask 1611 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask & (1 << n1)) mask 1650 tools/testing/selftests/kvm/lib/sparsebit.c if (!(nodep->mask & (1 << (MASK_BITS - 1))) && nodep->num_after) { mask 1701 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask & (1 << n1)) mask 1713 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask == 0) { mask 1716 tools/testing/selftests/kvm/lib/sparsebit.c nodep, nodep->mask); mask 1843 tools/testing/selftests/kvm/lib/sparsebit.c if (nodep->mask == ~(mask_t) 0 && mask 123 tools/testing/selftests/net/msg_zerocopy.c cpu_set_t mask; mask 125 tools/testing/selftests/net/msg_zerocopy.c CPU_ZERO(&mask); mask 126 tools/testing/selftests/net/msg_zerocopy.c CPU_SET(cpu, &mask); mask 127 tools/testing/selftests/net/msg_zerocopy.c if (sched_setaffinity(0, sizeof(mask), &mask)) mask 399 tools/testing/selftests/net/psock_fanout.c cpu_set_t mask; mask 401 tools/testing/selftests/net/psock_fanout.c CPU_ZERO(&mask); mask 402 tools/testing/selftests/net/psock_fanout.c CPU_SET(cpuid, &mask); mask 403 tools/testing/selftests/net/psock_fanout.c if (sched_setaffinity(0, sizeof(mask), &mask)) { mask 105 tools/testing/selftests/net/udpgso_bench_tx.c cpu_set_t mask; mask 107 tools/testing/selftests/net/udpgso_bench_tx.c CPU_ZERO(&mask); mask 108 tools/testing/selftests/net/udpgso_bench_tx.c CPU_SET(cpu, &mask); mask 109 tools/testing/selftests/net/udpgso_bench_tx.c if (sched_setaffinity(0, sizeof(mask), &mask)) mask 50 tools/testing/selftests/networking/timestamping/rxtimestamp.c int mask; mask 136 tools/testing/selftests/networking/timestamping/rxtimestamp.c if (t->sockopt.so_timestamping & sof_flags[f].mask) mask 38 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c cpu_set_t mask; mask 42 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c CPU_ZERO(&mask); mask 43 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c CPU_SET(cpu, &mask); mask 44 tools/testing/selftests/powerpc/dscr/dscr_sysfs_thread_test.c if (sched_setaffinity(0, sizeof(mask), &mask)) mask 26 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c uint64_t mask, val; mask 28 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c mask = MMCR0_PMAO | MMCR0_FC; mask 45 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c mask &= ~MMCR0_FC; mask 50 tools/testing/selftests/powerpc/pmu/ebb/cycles_with_freeze_test.c reset_ebb_with_clear_mask(mask); mask 20 tools/testing/selftests/powerpc/pmu/lib.c cpu_set_t mask; mask 24 tools/testing/selftests/powerpc/pmu/lib.c CPU_ZERO(&mask); mask 25 tools/testing/selftests/powerpc/pmu/lib.c CPU_SET(cpu, &mask); mask 27 tools/testing/selftests/powerpc/pmu/lib.c return sched_setaffinity(0, sizeof(mask), &mask); mask 23 tools/testing/selftests/powerpc/primitives/word-at-a-time.h unsigned long mask = (val & c->low_bits) + c->low_bits; mask 24 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return ~(mask | rhs); mask 27 tools/testing/selftests/powerpc/primitives/word-at-a-time.h #define create_zero_mask(mask) (mask) mask 29 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline long find_zero(unsigned long mask) mask 33 tools/testing/selftests/powerpc/primitives/word-at-a-time.h asm (PPC_CNTLZL "%0,%1" : "=r" (leading_zero_bits) : "r" (mask)); mask 44 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline unsigned long zero_bytemask(unsigned long mask) mask 46 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return ~1ul << __fls(mask); mask 91 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 93 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return mask >> 3; mask 97 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline unsigned long zero_bytemask(unsigned long mask) mask 99 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return (1UL << mask) - 1; mask 119 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline long count_masked_bytes(long mask) mask 122 tools/testing/selftests/powerpc/primitives/word-at-a-time.h long a = (0x0ff0001+mask) >> 23; mask 124 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return a & mask; mask 133 tools/testing/selftests/powerpc/primitives/word-at-a-time.h static inline unsigned long find_zero(unsigned long mask) mask 135 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return count_masked_bytes(mask); mask 141 tools/testing/selftests/powerpc/primitives/word-at-a-time.h unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; mask 142 tools/testing/selftests/powerpc/primitives/word-at-a-time.h *bits = mask; mask 143 tools/testing/selftests/powerpc/primitives/word-at-a-time.h return mask; mask 152 tools/testing/selftests/powerpc/primitives/word-at-a-time.h #define zero_bytemask(mask) (mask) mask 91 tools/testing/selftests/powerpc/utils.c cpu_set_t mask; mask 94 tools/testing/selftests/powerpc/utils.c CPU_ZERO(&mask); mask 96 tools/testing/selftests/powerpc/utils.c if (sched_getaffinity(0, sizeof(mask), &mask)) { mask 103 tools/testing/selftests/powerpc/utils.c if (CPU_ISSET(cpu, &mask)) mask 108 tools/testing/selftests/powerpc/utils.c if (CPU_ISSET(cpu, &mask)) mask 117 tools/testing/selftests/proc/fd-003-kthread.c unsigned int mask, void *stx) mask 119 tools/testing/selftests/proc/fd-003-kthread.c return syscall(SYS_statx, dirfd, pathname, flags, mask, stx); mask 971 tools/testing/selftests/seccomp/seccomp_bpf.c sigset_t mask; mask 974 tools/testing/selftests/seccomp/seccomp_bpf.c sigemptyset(&mask); mask 975 tools/testing/selftests/seccomp/seccomp_bpf.c sigaddset(&mask, SIGSYS); mask 983 tools/testing/selftests/seccomp/seccomp_bpf.c ret = sigprocmask(SIG_UNBLOCK, &mask, NULL); mask 247 tools/testing/selftests/uevent/uevent_filtering.c sigset_t mask; mask 251 tools/testing/selftests/uevent/uevent_filtering.c sigemptyset(&mask); mask 252 tools/testing/selftests/uevent/uevent_filtering.c sigaddset(&mask, SIGCHLD); mask 254 tools/testing/selftests/uevent/uevent_filtering.c ret = sigprocmask(SIG_BLOCK, &mask, &orig_mask); mask 321 tools/testing/selftests/uevent/uevent_filtering.c ret = sigtimedwait(&mask, NULL, &timeout); mask 404 tools/testing/selftests/x86/protection_keys.c u32 mask = (PKEY_DISABLE_ACCESS|PKEY_DISABLE_WRITE); mask 415 tools/testing/selftests/x86/protection_keys.c masked_pkru = shifted_pkru & mask; mask 426 tools/testing/selftests/x86/protection_keys.c u32 mask = (PKEY_DISABLE_ACCESS|PKEY_DISABLE_WRITE); mask 431 tools/testing/selftests/x86/protection_keys.c assert(!(rights & ~mask)); mask 436 tools/testing/selftests/x86/protection_keys.c new_pkru &= ~(mask << (pkey * PKRU_BITS_PER_PKEY)); mask 29 tools/testing/selftests/x86/vdso_restorer.c unsigned int mask[2]; mask 94 tools/virtio/virtio-trace/trace-agent-rw.c cpu_set_t mask; mask 96 tools/virtio/virtio-trace/trace-agent-rw.c CPU_ZERO(&mask); mask 97 tools/virtio/virtio-trace/trace-agent-rw.c CPU_SET(cpu_num, &mask); mask 100 tools/virtio/virtio-trace/trace-agent-rw.c if (sched_setaffinity(0, sizeof(mask), &mask) == -1) mask 1145 tools/vm/page-types.c static void add_bits_filter(uint64_t mask, uint64_t bits) mask 1150 tools/vm/page-types.c opt_mask[nr_bit_filters] = mask; mask 1196 tools/vm/page-types.c uint64_t mask; mask 1202 tools/vm/page-types.c mask = KPF_ALL_BITS; mask 1205 tools/vm/page-types.c mask = parse_flag_names(optarg, 0); mask 1208 tools/vm/page-types.c mask = parse_flag_names(optarg, 1); mask 1211 tools/vm/page-types.c mask = parse_flag_names(optarg, 0); mask 1215 tools/vm/page-types.c add_bits_filter(mask, bits); mask 135 virt/kvm/arm/arch_timer.c timecounter->mask, mask 486 virt/kvm/arm/arm.c void force_vm_exit(const cpumask_t *mask) mask 489 virt/kvm/arm/arm.c smp_call_function_many(mask, exit_vm_noop, NULL, true); mask 87 virt/kvm/arm/mmio.c int mask; mask 104 virt/kvm/arm/mmio.c mask = 1U << ((len * 8) - 1); mask 105 virt/kvm/arm/mmio.c data = (data ^ mask) - mask; mask 1388 virt/kvm/arm/mmu.c unsigned long mask; mask 1407 virt/kvm/arm/mmu.c mask = PTRS_PER_PMD - 1; mask 1408 virt/kvm/arm/mmu.c VM_BUG_ON((gfn & mask) != (pfn & mask)); mask 1409 virt/kvm/arm/mmu.c if (pfn & mask) { mask 1412 virt/kvm/arm/mmu.c pfn &= ~mask; mask 1566 virt/kvm/arm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 1569 virt/kvm/arm/mmu.c phys_addr_t start = (base_gfn + __ffs(mask)) << PAGE_SHIFT; mask 1570 virt/kvm/arm/mmu.c phys_addr_t end = (base_gfn + __fls(mask) + 1) << PAGE_SHIFT; mask 1584 virt/kvm/arm/mmu.c gfn_t gfn_offset, unsigned long mask) mask 1586 virt/kvm/arm/mmu.c kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); mask 533 virt/kvm/arm/pmu.c u64 mask; mask 536 virt/kvm/arm/pmu.c mask = kvm_pmu_valid_counter_mask(vcpu); mask 539 virt/kvm/arm/pmu.c __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask); mask 541 virt/kvm/arm/pmu.c kvm_pmu_disable_counter_mask(vcpu, mask); mask 1271 virt/kvm/kvm_main.c unsigned long mask; mask 1278 virt/kvm/kvm_main.c mask = xchg(&dirty_bitmap[i], 0); mask 1279 virt/kvm/kvm_main.c dirty_bitmap_buffer[i] = mask; mask 1283 virt/kvm/kvm_main.c offset, mask); mask 1343 virt/kvm/kvm_main.c unsigned long mask = *dirty_bitmap_buffer++; mask 1345 virt/kvm/kvm_main.c if (!mask) mask 1348 virt/kvm/kvm_main.c mask &= atomic_long_fetch_andnot(mask, p); mask 1356 virt/kvm/kvm_main.c if (mask) { mask 1359 virt/kvm/kvm_main.c offset, mask);