CNL_DPLL_ENABLE 2025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); CNL_DPLL_ENABLE 2027 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); CNL_DPLL_ENABLE 2030 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), CNL_DPLL_ENABLE 2063 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); CNL_DPLL_ENABLE 2065 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); CNL_DPLL_ENABLE 2068 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) CNL_DPLL_ENABLE 2107 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); CNL_DPLL_ENABLE 2109 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); CNL_DPLL_ENABLE 2112 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) CNL_DPLL_ENABLE 2125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); CNL_DPLL_ENABLE 2127 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(CNL_DPLL_ENABLE(id), val); CNL_DPLL_ENABLE 2130 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), CNL_DPLL_ENABLE 2151 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = I915_READ(CNL_DPLL_ENABLE(id)); CNL_DPLL_ENABLE 3146 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); CNL_DPLL_ENABLE 3274 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); CNL_DPLL_ENABLE 3382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);