CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN  166 arch/mips/kernel/mips-cm.c 	if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN  194 arch/mips/kernel/mips-cm.c 	write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);