lock_addr         133 arch/c6x/platforms/dscr.c 	void __iomem *lock_addr = dscr.base + lock;
lock_addr         148 arch/c6x/platforms/dscr.c 		      : "a"(reg_addr), "b"(val), "a"(lock_addr), "b"(key)
lock_addr         152 arch/c6x/platforms/dscr.c 	soc_writel(0, lock_addr);
lock_addr         295 drivers/clk/tegra/clk-pll.c 	void __iomem *lock_addr;
lock_addr         302 drivers/clk/tegra/clk-pll.c 	lock_addr = pll->clk_base;
lock_addr         304 drivers/clk/tegra/clk-pll.c 		lock_addr += pll->params->misc_reg;
lock_addr         306 drivers/clk/tegra/clk-pll.c 		lock_addr += pll->params->base_reg;
lock_addr         311 drivers/clk/tegra/clk-pll.c 		val = readl_relaxed(lock_addr);
lock_addr         292 drivers/crypto/chelsio/chtls/chtls.h 	__be32 lock_addr;
lock_addr         347 drivers/crypto/chelsio/chtls/chtls_hw.c 	kwr->req.lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(kaddr));
lock_addr          39 drivers/hwspinlock/omap_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          42 drivers/hwspinlock/omap_hwspinlock.c 	return (SPINLOCK_NOTTAKEN == readl(lock_addr));
lock_addr          47 drivers/hwspinlock/omap_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          50 drivers/hwspinlock/omap_hwspinlock.c 	writel(SPINLOCK_NOTTAKEN, lock_addr);
lock_addr          36 drivers/hwspinlock/sirf_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          39 drivers/hwspinlock/sirf_hwspinlock.c 	return !!readl(lock_addr);
lock_addr          44 drivers/hwspinlock/sirf_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          47 drivers/hwspinlock/sirf_hwspinlock.c 	writel(0, lock_addr);
lock_addr          65 drivers/hwspinlock/sprd_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          67 drivers/hwspinlock/sprd_hwspinlock.c 	writel(HWSPINLOCK_NOTTAKEN, lock_addr);
lock_addr          30 drivers/hwspinlock/stm32_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          33 drivers/hwspinlock/stm32_hwspinlock.c 	writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID, lock_addr);
lock_addr          34 drivers/hwspinlock/stm32_hwspinlock.c 	status = readl(lock_addr);
lock_addr          41 drivers/hwspinlock/stm32_hwspinlock.c 	void __iomem *lock_addr = lock->priv;
lock_addr          43 drivers/hwspinlock/stm32_hwspinlock.c 	writel(STM32_MUTEX_COREID, lock_addr);
lock_addr          53 drivers/hwspinlock/u8500_hsem.c 	void __iomem *lock_addr = lock->priv;
lock_addr          55 drivers/hwspinlock/u8500_hsem.c 	writel(HSEM_MASTER_ID, lock_addr);
lock_addr          61 drivers/hwspinlock/u8500_hsem.c 	return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
lock_addr          66 drivers/hwspinlock/u8500_hsem.c 	void __iomem *lock_addr = lock->priv;
lock_addr          69 drivers/hwspinlock/u8500_hsem.c 	writel(RESET_SEMAPHORE, lock_addr);
lock_addr          95 drivers/infiniband/hw/cxgb4/mem.c 	req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr));
lock_addr         161 drivers/infiniband/hw/cxgb4/mem.c 		req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3));
lock_addr        1717 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h 	__be32 lock_addr;
lock_addr        1904 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c 	req->lock_addr = htonl(ULP_MEMIO_ADDR_V(pm_addr >> 5));
lock_addr          87 drivers/target/iscsi/cxgbit/cxgbit_ddp.c 	req->lock_addr = htonl(ULP_MEMIO_ADDR_V(pm_addr >> 5));
lock_addr          48 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);
lock_addr          61 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);
lock_addr          73 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);				\
lock_addr          85 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);				\
lock_addr          99 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);				\
lock_addr         136 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);
lock_addr         151 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);
lock_addr         166 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);
lock_addr         180 lib/atomic64.c 	raw_spinlock_t *lock = lock_addr(v);