local_flush_icache_range   82 arch/mips/include/asm/cacheflush.h extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
local_flush_icache_range  163 arch/mips/kernel/machine_kexec.c 	local_flush_icache_range((unsigned long)relocated_kexec_smp_wait,
local_flush_icache_range  201 arch/mips/kernel/machine_kexec.c 	local_flush_icache_range(reboot_code_buffer,
local_flush_icache_range  628 arch/mips/kernel/pm-cps.c 	local_flush_icache_range((unsigned long)buf, (unsigned long)p);
local_flush_icache_range  376 arch/mips/kernel/smp-bmips.c 	local_flush_icache_range(0, ~0);
local_flush_icache_range  461 arch/mips/kernel/smp-bmips.c 	local_flush_icache_range(dst, dst + (end - start));
local_flush_icache_range 1964 arch/mips/kernel/traps.c 		local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
local_flush_icache_range 2043 arch/mips/kernel/traps.c 		local_flush_icache_range((unsigned long)b,
local_flush_icache_range 2065 arch/mips/kernel/traps.c 		local_flush_icache_range((unsigned long)b,
local_flush_icache_range 2237 arch/mips/kernel/traps.c 	local_flush_icache_range(ebase + offset, ebase + offset + size);
local_flush_icache_range 2443 arch/mips/kernel/traps.c 	local_flush_icache_range(ebase, ebase + vec_size);
local_flush_icache_range 1849 arch/mips/kvm/emulate.c 				local_flush_icache_range(0, 0);
local_flush_icache_range 1863 arch/mips/kvm/emulate.c 				local_flush_icache_range(0, 0);
local_flush_icache_range 1113 arch/mips/kvm/vz.c 			local_flush_icache_range(0, 0);
local_flush_icache_range  278 arch/mips/mm/c-octeon.c 	local_flush_icache_range	= local_octeon_flush_icache_range;
local_flush_icache_range  304 arch/mips/mm/c-r3k.c 	local_flush_icache_range = r3k_flush_icache_range;
local_flush_icache_range 1870 arch/mips/mm/c-r4k.c 	local_flush_icache_range	= local_r4k_flush_icache_range;
local_flush_icache_range 1923 arch/mips/mm/c-r4k.c 		local_flush_icache_range = (void *)b5k_instruction_hazard;
local_flush_icache_range  350 arch/mips/mm/c-tx39.c 		local_flush_icache_range = (void *) tx39h_flush_icache_all;
local_flush_icache_range  376 arch/mips/mm/c-tx39.c 		local_flush_icache_range = tx39_flush_icache_range;
local_flush_icache_range  395 arch/mips/mm/c-tx39.c 	__local_flush_icache_user_range = local_flush_icache_range;
local_flush_icache_range   36 arch/mips/mm/cache.c void (*local_flush_icache_range)(unsigned long start, unsigned long end);
local_flush_icache_range   37 arch/mips/mm/cache.c EXPORT_SYMBOL_GPL(local_flush_icache_range);
local_flush_icache_range  444 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase, ebase + 0x80);
local_flush_icache_range 1477 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase, ebase + 0x100);
local_flush_icache_range 1582 arch/mips/mm/tlbex.c 	local_flush_icache_range(ebase + 0x80, ebase + 0x100);
local_flush_icache_range 2423 arch/mips/mm/tlbex.c 	local_flush_icache_range((unsigned long)handle_tlbl,
local_flush_icache_range 2425 arch/mips/mm/tlbex.c 	local_flush_icache_range((unsigned long)handle_tlbs,
local_flush_icache_range 2427 arch/mips/mm/tlbex.c 	local_flush_icache_range((unsigned long)handle_tlbm,
local_flush_icache_range 2429 arch/mips/mm/tlbex.c 	local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
local_flush_icache_range   29 arch/sh/include/asm/cacheflush.h extern void (*local_flush_icache_range)(void *args);
local_flush_icache_range   59 arch/sh/mm/cache-j2.c 	local_flush_icache_range = j2_flush_icache;
local_flush_icache_range  183 arch/sh/mm/cache-sh2a.c 	local_flush_icache_range	= sh2a_flush_icache_range;
local_flush_icache_range  385 arch/sh/mm/cache-sh4.c 	local_flush_icache_range	= sh4_flush_icache_range;
local_flush_icache_range  614 arch/sh/mm/cache-sh5.c 	local_flush_icache_range	= sh5_flush_icache_range;
local_flush_icache_range  187 arch/sh/mm/cache-sh7705.c 	local_flush_icache_range	= sh7705_flush_icache_range;
local_flush_icache_range   24 arch/sh/mm/cache.c void (*local_flush_icache_range)(void *args) = cache_noop;
local_flush_icache_range  232 arch/sh/mm/cache.c 	cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
local_flush_icache_range  106 arch/xtensa/include/asm/cacheflush.h #define flush_icache_range local_flush_icache_range
local_flush_icache_range  142 arch/xtensa/include/asm/cacheflush.h #define flush_icache_range local_flush_icache_range
local_flush_icache_range   36 arch/xtensa/kernel/jump_label.c 	local_flush_icache_range(addr, addr + sz);
local_flush_icache_range  587 arch/xtensa/kernel/smp.c 	local_flush_icache_range(fd->addr1, fd->addr2);