link_train 262 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; link_train 264 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lt_state = CLOCK_RECOVERY; link_train 265 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.eq_loop = 0; link_train 268 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane] = 0; link_train 271 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); link_train 272 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_lane_count(dp, dp->link_train.lane_count); link_train 275 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c buf[0] = dp->link_train.link_rate; link_train 276 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c buf[1] = dp->link_train.lane_count; link_train 438 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lt_state = FAILED; link_train 447 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; link_train 461 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane] = training_lane; link_train 473 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; link_train 495 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lt_state = EQUALIZER_TRAINING; link_train 509 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane]++; link_train 511 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || link_train 515 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane], link_train 527 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane], lane); link_train 530 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane, lane_count); link_train 545 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; link_train 576 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate = reg; link_train 578 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate); link_train 581 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = reg; link_train 583 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count); link_train 585 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lt_state = FINISHED; link_train 591 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.eq_loop++; link_train 593 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.eq_loop > MAX_EQ_LOOP) { link_train 601 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane], lane); link_train 604 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane, lane_count); link_train 652 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); link_train 653 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); link_train 655 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && link_train 656 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c (dp->link_train.link_rate != DP_LINK_BW_2_7) && link_train 657 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c (dp->link_train.link_rate != DP_LINK_BW_5_4)) { link_train 659 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate); link_train 660 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate = DP_LINK_BW_1_62; link_train 663 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.lane_count == 0) { link_train 665 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count); link_train 666 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = (u8)LANE_COUNT1; link_train 670 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.lane_count > max_lanes) link_train 671 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = max_lanes; link_train 672 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.link_rate > max_rate) link_train 673 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.link_rate = max_rate; link_train 678 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lt_state = START; link_train 682 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c switch (dp->link_train.lt_state) { link_train 719 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); link_train 720 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_lane_count(dp, dp->link_train.lane_count); link_train 722 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (i = 0; i < dp->link_train.lane_count; i++) { link_train 724 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[i], i); link_train 769 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count)) { link_train 776 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count)) { link_train 169 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h struct link_train link_train;