lane_status       317 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status *dpcd_lane_status)
lane_status       331 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status *dpcd_lane_status,
lane_status       496 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status *ln_status,
lane_status       684 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
lane_status       751 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 					union lane_status *dpcd_lane_status)
lane_status       775 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
lane_status       837 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
lane_status      1478 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_status lane_status;
lane_status      1496 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		lane_status.raw = get_nibble_at_index(
lane_status      1500 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
lane_status      1501 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			!lane_status.bits.CR_DONE_0 ||
lane_status      1502 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			!lane_status.bits.SYMBOL_LOCKED_0) {
lane_status       374 drivers/gpu/drm/amd/display/dc/dc_dp_types.h 		union lane_status lane01_status;/* 202h */
lane_status       375 drivers/gpu/drm/amd/display/dc/dc_dp_types.h 		union lane_status lane23_status;/* 203h */
lane_status       337 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	u8 lane_status;
lane_status       340 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		lane_status = analogix_dp_get_lane_status(link_status, lane);
lane_status       341 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		if ((lane_status & DP_LANE_CR_DONE) == 0)
lane_status       351 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	u8 lane_status;
lane_status       357 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		lane_status = analogix_dp_get_lane_status(link_status, lane);
lane_status       358 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		lane_status &= DP_CHANNEL_EQ_BITS;
lane_status       359 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 		if (lane_status != DP_CHANNEL_EQ_BITS)
lane_status        66 drivers/gpu/drm/drm_dp_helper.c 	u8 lane_status;
lane_status        74 drivers/gpu/drm/drm_dp_helper.c 		lane_status = dp_get_lane_status(link_status, lane);
lane_status        75 drivers/gpu/drm/drm_dp_helper.c 		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
lane_status        86 drivers/gpu/drm/drm_dp_helper.c 	u8 lane_status;
lane_status        89 drivers/gpu/drm/drm_dp_helper.c 		lane_status = dp_get_lane_status(link_status, lane);
lane_status        90 drivers/gpu/drm/drm_dp_helper.c 		if ((lane_status & DP_LANE_CR_DONE) == 0)
lane_status      1350 drivers/gpu/drm/gma500/cdv_intel_dp.c 	uint8_t lane_status;
lane_status      1353 drivers/gpu/drm/gma500/cdv_intel_dp.c 		lane_status = cdv_intel_get_lane_status(link_status, lane);
lane_status      1354 drivers/gpu/drm/gma500/cdv_intel_dp.c 		if ((lane_status & DP_LANE_CR_DONE) == 0)
lane_status      1369 drivers/gpu/drm/gma500/cdv_intel_dp.c 	uint8_t lane_status;
lane_status      1377 drivers/gpu/drm/gma500/cdv_intel_dp.c 		lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
lane_status      1378 drivers/gpu/drm/gma500/cdv_intel_dp.c 		if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
lane_status        42 drivers/net/ethernet/sfc/falcon/mdio_10g.h 	int i, lane_status;
lane_status        46 drivers/net/ethernet/sfc/falcon/mdio_10g.h 		lane_status = ef4_mdio_read(efx, MDIO_MMD_PHYXS,
lane_status        49 drivers/net/ethernet/sfc/falcon/mdio_10g.h 	sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);
lane_status        52 drivers/net/ethernet/sfc/falcon/mdio_10g.h 			  lane_status);