lane_count_set    525 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	union lane_count_set lane_count_set = { {0} };
lane_count_set    538 drivers/gpu/drm/amd/display/dc/core/dc_link.c 				&lane_count_set.raw,
lane_count_set    539 drivers/gpu/drm/amd/display/dc/core/dc_link.c 				sizeof(lane_count_set));
lane_count_set    546 drivers/gpu/drm/amd/display/dc/core/dc_link.c 			link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
lane_count_set    134 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_count_set lane_count_set = { {0} };
lane_count_set    140 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.LANE_COUNT_SET =
lane_count_set    143 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
lane_count_set    144 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
lane_count_set    149 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
lane_count_set    157 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		&lane_count_set.raw, 1);
lane_count_set    929 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	union lane_count_set lane_count_set = { {0} };
lane_count_set    952 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
lane_count_set    953 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
lane_count_set    954 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
lane_count_set    959 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		&lane_count_set.raw,
lane_count_set    960 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 		sizeof(lane_count_set));