k0 34 arch/mips/include/asm/pm.h mfc0 k0, CP0_STATUS k0 35 arch/mips/include/asm/pm.h LONG_S k0, PT_STATUS(sp) k0 43 arch/mips/include/asm/pm.h LONG_L k0, PT_STATUS(sp) k0 44 arch/mips/include/asm/pm.h mtc0 k0, CP0_STATUS k0 75 arch/mips/include/asm/pm.h mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ k0 76 arch/mips/include/asm/pm.h LONG_S k0, SSS_SEGCTL0(t1) k0 77 arch/mips/include/asm/pm.h mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ k0 78 arch/mips/include/asm/pm.h LONG_S k0, SSS_SEGCTL1(t1) k0 79 arch/mips/include/asm/pm.h mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ k0 80 arch/mips/include/asm/pm.h LONG_S k0, SSS_SEGCTL2(t1) k0 94 arch/mips/include/asm/pm.h LONG_L k0, SSS_SEGCTL0(t1) k0 95 arch/mips/include/asm/pm.h mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ k0 96 arch/mips/include/asm/pm.h LONG_L k0, SSS_SEGCTL1(t1) k0 97 arch/mips/include/asm/pm.h mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ k0 98 arch/mips/include/asm/pm.h LONG_L k0, SSS_SEGCTL2(t1) k0 99 arch/mips/include/asm/pm.h mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ k0 119 arch/mips/include/asm/stackframe.h ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG k0 129 arch/mips/include/asm/stackframe.h LONG_SRL k0, SMP_CPUID_PTRSHIFT k0 130 arch/mips/include/asm/stackframe.h LONG_ADDU k1, k0 k0 132 arch/mips/include/asm/stackframe.h move k0, sp k0 134 arch/mips/include/asm/stackframe.h .cfi_register sp, k0 k0 156 arch/mips/include/asm/stackframe.h move k0, ra k0 165 arch/mips/include/asm/stackframe.h 1: move ra, k0 k0 166 arch/mips/include/asm/stackframe.h li k0, 3 k0 167 arch/mips/include/asm/stackframe.h mtc0 k0, $22 k0 179 arch/mips/include/asm/stackframe.h move k0, sp k0 181 arch/mips/include/asm/stackframe.h .cfi_register sp, k0 k0 198 arch/mips/include/asm/stackframe.h mfc0 k0, CP0_STATUS k0 199 arch/mips/include/asm/stackframe.h sll k0, 3 /* extract cu0 bit */ k0 201 arch/mips/include/asm/stackframe.h bltz k0, 8f k0 202 arch/mips/include/asm/stackframe.h move k0, sp k0 204 arch/mips/include/asm/stackframe.h .cfi_register sp, k0 k0 228 arch/mips/include/asm/stackframe.h MFC0 k0, CP0_ENTRYHI k0 229 arch/mips/include/asm/stackframe.h MTC0 k0, CP0_ENTRYHI k0 245 arch/mips/include/asm/stackframe.h cfi_st k0, PT_R29, \docfi k0 277 arch/mips/include/asm/stackframe.h mfc0 k0, CP0_STATUS k0 278 arch/mips/include/asm/stackframe.h sll k0, 3 /* extract cu0 bit */ k0 279 arch/mips/include/asm/stackframe.h bltz k0, 9f k0 384 arch/mips/include/asm/stackframe.h LONG_L k0, PT_EPC(sp) k0 386 arch/mips/include/asm/stackframe.h jr k0 k0 1955 arch/mips/kernel/traps.c unsigned int k0 = 26; k0 1960 arch/mips/kernel/traps.c UASM_i_LA(&buf, k0, handler); k0 1961 arch/mips/kernel/traps.c uasm_i_jr(&buf, k0); k0 60 crypto/tea.c u32 k0, k1, k2, k3; k0 68 crypto/tea.c k0 = ctx->KEY[0]; k0 77 crypto/tea.c y += ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1); k0 88 crypto/tea.c u32 k0, k1, k2, k3; k0 96 crypto/tea.c k0 = ctx->KEY[0]; k0 107 crypto/tea.c y -= ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1); k0 294 crypto/vmac.c p += MUL32(a2, k0); k0 300 crypto/vmac.c p += MUL32(a3, k0); k0 304 crypto/vmac.c p += MUL32(a0, k0); k0 314 crypto/vmac.c p += MUL32(a1, k0); k0 366 kernel/locking/lockdep.c u32 k0 = key, k1 = key >> 32; k0 368 kernel/locking/lockdep.c __jhash_mix(idx, k0, k1); /* Macro that modifies arguments! */ k0 370 kernel/locking/lockdep.c return k0 | (u64)k1 << 32;