k 75 arch/alpha/include/asm/termios.h #define user_termios_to_kernel_termios(k, u) \ k 76 arch/alpha/include/asm/termios.h copy_from_user(k, u, sizeof(struct termios2)) k 78 arch/alpha/include/asm/termios.h #define kernel_termios_to_user_termios(u, k) \ k 79 arch/alpha/include/asm/termios.h copy_to_user(u, k, sizeof(struct termios2)) k 81 arch/alpha/include/asm/termios.h #define user_termios_to_kernel_termios_1(k, u) \ k 82 arch/alpha/include/asm/termios.h copy_from_user(k, u, sizeof(struct termios)) k 84 arch/alpha/include/asm/termios.h #define kernel_termios_to_user_termios_1(u, k) \ k 85 arch/alpha/include/asm/termios.h copy_to_user(u, k, sizeof(struct termios)) k 57 arch/arc/include/asm/uaccess.h #define __get_user_fn(sz, u, k) \ k 61 arch/arc/include/asm/uaccess.h case 1: __arc_get_user_one(*(k), u, "ldb", __ret); break; \ k 62 arch/arc/include/asm/uaccess.h case 2: __arc_get_user_one(*(k), u, "ldw", __ret); break; \ k 63 arch/arc/include/asm/uaccess.h case 4: __arc_get_user_one(*(k), u, "ld", __ret); break; \ k 64 arch/arc/include/asm/uaccess.h case 8: __arc_get_user_one_64(*(k), u, __ret); break; \ k 118 arch/arc/include/asm/uaccess.h #define __put_user_fn(sz, u, k) \ k 122 arch/arc/include/asm/uaccess.h case 1: __arc_put_user_one(*(k), u, "stb", __ret); break; \ k 123 arch/arc/include/asm/uaccess.h case 2: __arc_put_user_one(*(k), u, "stw", __ret); break; \ k 124 arch/arc/include/asm/uaccess.h case 4: __arc_put_user_one(*(k), u, "st", __ret); break; \ k 125 arch/arc/include/asm/uaccess.h case 8: __arc_put_user_one_64(*(k), u, __ret); break; \ k 35 arch/arm/crypto/ghash-ce-glue.c be128 k; k 49 arch/arm/crypto/ghash-ce-glue.c struct ghash_key const *k, k 53 arch/arm/crypto/ghash-ce-glue.c struct ghash_key const *k, k 57 arch/arm/crypto/ghash-ce-glue.c struct ghash_key const *k, k 90 arch/arm/crypto/ghash-ce-glue.c gf128mul_lle(&dst, &key->k); k 149 arch/arm/crypto/ghash-ce-glue.c static void ghash_reflect(u64 h[], const be128 *k) k 151 arch/arm/crypto/ghash-ce-glue.c u64 carry = be64_to_cpu(k->a) >> 63; k 153 arch/arm/crypto/ghash-ce-glue.c h[0] = (be64_to_cpu(k->b) << 1) | carry; k 154 arch/arm/crypto/ghash-ce-glue.c h[1] = (be64_to_cpu(k->a) << 1) | (be64_to_cpu(k->b) >> 63); k 172 arch/arm/crypto/ghash-ce-glue.c memcpy(&key->k, inkey, GHASH_BLOCK_SIZE); k 173 arch/arm/crypto/ghash-ce-glue.c ghash_reflect(key->h, &key->k); k 175 arch/arm/crypto/ghash-ce-glue.c h = key->k; k 176 arch/arm/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 179 arch/arm/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 182 arch/arm/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 464 arch/arm/mach-pxa/sharpsl_pm.c int i, j, k, temp, sum = 0; k 478 arch/arm/mach-pxa/sharpsl_pm.c k = 4; k 482 arch/arm/mach-pxa/sharpsl_pm.c k = i; k 487 arch/arm/mach-pxa/sharpsl_pm.c if (i != j && i != k) k 600 arch/arm/mach-s3c24xx/mach-h1940.c #define DECLARE_BUTTON(p, k, n, w) \ k 603 arch/arm/mach-s3c24xx/mach-h1940.c .code = k, \ k 67 arch/arm/mach-shmobile/platsmp-apmu.c int k; k 69 arch/arm/mach-shmobile/platsmp-apmu.c for (k = 0; k < 1000; k++) { k 75 arch/arm/mach-shmobile/platsmp-scu.c int k; k 81 arch/arm/mach-shmobile/platsmp-scu.c for (k = 0; k < 1000; k++) { k 106 arch/arm/net/bpf_jit_32.c #define STACK_OFFSET(k) (-4 - (k) * 4) k 354 arch/arm/net/bpf_jit_32.c static u16 imm_offset(u32 k, struct jit_ctx *ctx) k 366 arch/arm/net/bpf_jit_32.c if (ctx->imms[i] == k) k 372 arch/arm/net/bpf_jit_32.c ctx->imms[i] = k; k 380 arch/arm/net/bpf_jit_32.c ctx->target[offset / 4] = k; k 520 arch/arm/probes/kprobes/test-core.c struct kprobe k = { k 525 arch/arm/probes/kprobes/test-core.c int ret = register_kprobe(&k); k 533 arch/arm/probes/kprobes/test-core.c unregister_kprobe(&k); k 39 arch/arm64/crypto/ghash-ce-glue.c be128 k; k 54 arch/arm64/crypto/ghash-ce-glue.c struct ghash_key const *k, k 58 arch/arm64/crypto/ghash-ce-glue.c struct ghash_key const *k, k 62 arch/arm64/crypto/ghash-ce-glue.c const u8 src[], struct ghash_key const *k, k 67 arch/arm64/crypto/ghash-ce-glue.c const u8 src[], struct ghash_key const *k, k 85 arch/arm64/crypto/ghash-ce-glue.c struct ghash_key const *k, k 107 arch/arm64/crypto/ghash-ce-glue.c gf128mul_lle(&dst, &key->k); k 122 arch/arm64/crypto/ghash-ce-glue.c struct ghash_key const *k, k 214 arch/arm64/crypto/ghash-ce-glue.c static void ghash_reflect(u64 h[], const be128 *k) k 216 arch/arm64/crypto/ghash-ce-glue.c u64 carry = be64_to_cpu(k->a) & BIT(63) ? 1 : 0; k 218 arch/arm64/crypto/ghash-ce-glue.c h[0] = (be64_to_cpu(k->b) << 1) | carry; k 219 arch/arm64/crypto/ghash-ce-glue.c h[1] = (be64_to_cpu(k->a) << 1) | (be64_to_cpu(k->b) >> 63); k 231 arch/arm64/crypto/ghash-ce-glue.c memcpy(&key->k, inkey, GHASH_BLOCK_SIZE); k 233 arch/arm64/crypto/ghash-ce-glue.c ghash_reflect(key->h, &key->k); k 235 arch/arm64/crypto/ghash-ce-glue.c h = key->k; k 236 arch/arm64/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 239 arch/arm64/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 242 arch/arm64/crypto/ghash-ce-glue.c gf128mul_lle(&h, &key->k); k 46 arch/arm64/include/asm/pointer_auth.h #define __ptrauth_key_install(k, v) \ k 49 arch/arm64/include/asm/pointer_auth.h write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \ k 50 arch/arm64/include/asm/pointer_auth.h write_sysreg_s(__pki_v.hi, SYS_ ## k ## KEYHI_EL1); \ k 1029 arch/arm64/kvm/sys_regs.c #define __PTRAUTH_KEY(k) \ k 1030 arch/arm64/kvm/sys_regs.c { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \ k 1033 arch/arm64/kvm/sys_regs.c #define PTRAUTH_KEY(k) \ k 1034 arch/arm64/kvm/sys_regs.c __PTRAUTH_KEY(k ## KEYLO_EL1), \ k 1035 arch/arm64/kvm/sys_regs.c __PTRAUTH_KEY(k ## KEYHI_EL1) k 128 arch/csky/mm/highmem.c int i, j, k; k 134 arch/csky/mm/highmem.c k = __pmd_offset(vaddr); k 141 arch/csky/mm/highmem.c for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { k 154 arch/csky/mm/highmem.c k = 0; k 25 arch/ia64/include/asm/kregs.h #define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n) k 53 arch/ia64/include/asm/termios.h #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) k 54 arch/ia64/include/asm/termios.h #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) k 55 arch/ia64/include/asm/termios.h #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) k 56 arch/ia64/include/asm/termios.h #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) k 311 arch/ia64/kernel/efi.c kern_memdesc_t *k; k 315 arch/ia64/kernel/efi.c for (k = kern_memmap; k->start != ~0UL; k++) { k 316 arch/ia64/kernel/efi.c if (k->attribute != attr) k 318 arch/ia64/kernel/efi.c start = PAGE_ALIGN(k->start); k 319 arch/ia64/kernel/efi.c end = (k->start + (k->num_pages << EFI_PAGE_SHIFT)) & PAGE_MASK; k 1051 arch/ia64/kernel/efi.c struct kern_memdesc *k, *prev = NULL; k 1059 arch/ia64/kernel/efi.c k = kern_memmap = find_memmap_space(); k 1071 arch/ia64/kernel/efi.c k->attribute = EFI_MEMORY_UC; k 1072 arch/ia64/kernel/efi.c k->start = md->phys_addr; k 1073 arch/ia64/kernel/efi.c k->num_pages = md->num_pages; k 1074 arch/ia64/kernel/efi.c k++; k 1103 arch/ia64/kernel/efi.c if (k > kern_memmap && k 1104 arch/ia64/kernel/efi.c (k-1)->attribute == EFI_MEMORY_UC && k 1105 arch/ia64/kernel/efi.c kmd_end(k-1) == md->phys_addr) { k 1106 arch/ia64/kernel/efi.c (k-1)->num_pages += k 1110 arch/ia64/kernel/efi.c k->attribute = EFI_MEMORY_UC; k 1111 arch/ia64/kernel/efi.c k->start = md->phys_addr; k 1112 arch/ia64/kernel/efi.c k->num_pages = (lim - md->phys_addr) k 1114 arch/ia64/kernel/efi.c k++; k 1124 arch/ia64/kernel/efi.c if (lim == md->phys_addr && k > kern_memmap && k 1125 arch/ia64/kernel/efi.c (k-1)->attribute == EFI_MEMORY_UC && k 1126 arch/ia64/kernel/efi.c kmd_end(k-1) == md->phys_addr) { k 1127 arch/ia64/kernel/efi.c (k-1)->num_pages += md->num_pages; k 1129 arch/ia64/kernel/efi.c k->attribute = EFI_MEMORY_UC; k 1130 arch/ia64/kernel/efi.c k->start = lim; k 1131 arch/ia64/kernel/efi.c k->num_pages = (efi_md_end(md) - lim) k 1133 arch/ia64/kernel/efi.c k++; k 1157 arch/ia64/kernel/efi.c k->attribute = EFI_MEMORY_WB; k 1158 arch/ia64/kernel/efi.c k->start = as; k 1159 arch/ia64/kernel/efi.c k->num_pages = (ae - as) >> EFI_PAGE_SHIFT; k 1161 arch/ia64/kernel/efi.c prev = k++; k 1163 arch/ia64/kernel/efi.c k->start = ~0L; /* end-marker */ k 1167 arch/ia64/kernel/efi.c *e = (u64)++k; k 216 arch/ia64/kernel/palinfo.c int j, k; k 262 arch/ia64/kernel/palinfo.c for(k=0; k < 8; k++ ) { k 264 arch/ia64/kernel/palinfo.c seq_printf(m, "[%s]", cache_st_hints[k]); k 269 arch/ia64/kernel/palinfo.c for(k=0; k < 8; k++ ) { k 271 arch/ia64/kernel/palinfo.c seq_printf(m, "[%s]", cache_ld_hints[k]); k 5207 arch/ia64/kernel/perfmon.c int j, k, ret = 0; k 5236 arch/ia64/kernel/perfmon.c for(j=0, k=0; smpl_pmds; j++, smpl_pmds >>=1) { k 5238 arch/ia64/kernel/perfmon.c ovfl_arg->smpl_pmds_values[k++] = PMD_IS_COUNTING(j) ? pfm_read_soft_counter(ctx, j) : ia64_get_pmd(j); k 5239 arch/ia64/kernel/perfmon.c DPRINT_ovfl(("smpl_pmd[%d]=pmd%u=0x%lx\n", k-1, j, ovfl_arg->smpl_pmds_values[k-1])); k 36 arch/ia64/kernel/signal.c # define PUT_SIGSET(k,u) __copy_to_user((u)->sig, (k)->sig, sizeof(sigset_t)) k 37 arch/ia64/kernel/signal.c # define GET_SIGSET(k,u) __copy_from_user((k)->sig, (u)->sig, sizeof(sigset_t)) k 39 arch/ia64/kernel/signal.c # define PUT_SIGSET(k,u) __put_user((k)->sig[0], &(u)->sig[0]) k 40 arch/ia64/kernel/signal.c # define GET_SIGSET(k,u) __get_user((k)->sig[0], &(u)->sig[0]) k 269 arch/ia64/kernel/topology.c #define to_object(k) container_of(k, struct cache_info, kobj) k 173 arch/m68k/fpsp040/fpsp.h .set kfact_bit,12 | distinguishes static/dynamic k-factor k 21 arch/microblaze/include/asm/cpuinfo.h const unsigned k; k 28 arch/microblaze/include/asm/cpuinfo.h const unsigned k; k 131 arch/microblaze/kernel/cpu/cpuinfo-static.c ci->ver_code = cpu_ver_lookup[i].k; k 137 arch/microblaze/kernel/cpu/cpuinfo-static.c ci->fpga_family_code = family_string_lookup[i].k; k 36 arch/microblaze/kernel/cpu/mb.c if (cpuinfo.fpga_family_code == family_string_lookup[i].k) { k 44 arch/microblaze/kernel/cpu/mb.c if (cpuinfo.ver_code == cpu_ver_lookup[i].k) { k 101 arch/mips/ar7/clock.c int i, j, k, freq, res = target; k 104 arch/mips/ar7/clock.c for (k = 1; k <= 32; k++) { k 105 arch/mips/ar7/clock.c freq = abs(base / j * i / k - target); k 110 arch/mips/ar7/clock.c *postdiv = k; k 52 arch/mips/include/asm/sibyte/bcm1480_int.h #define _BCM1480_INT_HIGH(k) (k) k 53 arch/mips/include/asm/sibyte/bcm1480_int.h #define _BCM1480_INT_LOW(k) ((k)+64) k 81 arch/mips/include/asm/termios.h static inline int user_termios_to_kernel_termios(struct ktermios __user *k, k 84 arch/mips/include/asm/termios.h return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0; k 88 arch/mips/include/asm/termios.h struct ktermios *k) k 90 arch/mips/include/asm/termios.h return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0; k 93 arch/mips/include/asm/termios.h static inline int user_termios_to_kernel_termios_1(struct ktermios *k, k 96 arch/mips/include/asm/termios.h return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0; k 100 arch/mips/include/asm/termios.h struct ktermios *k) k 102 arch/mips/include/asm/termios.h return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0; k 50 arch/mips/kernel/cevt-r4k.c unsigned int cnt, i, j, k, l; k 69 arch/mips/kernel/cevt-r4k.c for (k = 0; k < j; ++k) { k 70 arch/mips/kernel/cevt-r4k.c if (cnt < buf1[k]) { k 73 arch/mips/kernel/cevt-r4k.c for (; l > k; --l) k 78 arch/mips/kernel/cevt-r4k.c if (k < ARRAY_SIZE(buf1)) k 79 arch/mips/kernel/cevt-r4k.c buf1[k] = cnt; k 83 arch/mips/kernel/cevt-r4k.c for (k = 0; k < i && k < ARRAY_SIZE(buf2); ++k) { k 84 arch/mips/kernel/cevt-r4k.c if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { k 87 arch/mips/kernel/cevt-r4k.c for (; l > k; --l) k 92 arch/mips/kernel/cevt-r4k.c if (k < ARRAY_SIZE(buf2)) k 93 arch/mips/kernel/cevt-r4k.c buf2[k] = buf1[ARRAY_SIZE(buf1) - 1]; k 118 arch/mips/kernel/smp.c int i, k, core_present; k 125 arch/mips/kernel/smp.c for_each_cpu(k, &temp_foreign_map) k 126 arch/mips/kernel/smp.c if (cpus_are_siblings(i, k)) k 570 arch/mips/kvm/trap_emul.c int i, j, k; k 588 arch/mips/kvm/trap_emul.c for (k = 0; k < PTRS_PER_PMD; k++) { k 589 arch/mips/kvm/trap_emul.c if (pmd_none(pmd[k])) k 592 arch/mips/kvm/trap_emul.c pmd_va = pud_va | (k << PMD_SHIFT); k 595 arch/mips/kvm/trap_emul.c pte = pte_offset(pmd + k, 0); k 238 arch/mips/mm/init.c int i, j, k; k 244 arch/mips/mm/init.c k = __pmd_offset(vaddr); k 251 arch/mips/mm/init.c for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) { k 265 arch/mips/mm/init.c k = 0; k 81 arch/mips/sibyte/bcm1480/irq.c int i = 0, old_cpu, cpu, int_on, k; k 100 arch/mips/sibyte/bcm1480/irq.c for (k=0; k<2; k++) { /* Loop through high and low interrupt mask register */ k 101 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); k 106 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(old_cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); k 111 arch/mips/sibyte/bcm1480/irq.c cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); k 113 arch/mips/sibyte/bcm1480/irq.c ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); k 144 arch/mips/sibyte/bcm1480/irq.c int k; k 156 arch/mips/sibyte/bcm1480/irq.c for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ k 158 arch/mips/sibyte/bcm1480/irq.c R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); k 169 arch/mips/sibyte/bcm1480/irq.c R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); k 172 arch/mips/sibyte/bcm1480/irq.c __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); k 47 arch/parisc/include/asm/termios.h #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) k 48 arch/parisc/include/asm/termios.h #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) k 49 arch/parisc/include/asm/termios.h #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) k 50 arch/parisc/include/asm/termios.h #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) k 897 arch/parisc/kernel/drivers.c int k; k 899 arch/parisc/kernel/drivers.c for (k = 0; k < dev->num_addrs; k++) k 900 arch/parisc/kernel/drivers.c pr_cont("0x%lx ", dev->addr[k]); k 234 arch/parisc/kernel/irq.c unsigned int k, avg, min, max; k 238 arch/parisc/kernel/irq.c for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { k 239 arch/parisc/kernel/irq.c int hist = action->cr16_hist[k]; k 250 arch/parisc/kernel/irq.c avg /= k; k 399 arch/parisc/kernel/ptrace.c __u64 *k = kbuf; k 408 arch/parisc/kernel/ptrace.c *k++ = regs->fr[pos++]; k 414 arch/parisc/kernel/ptrace.c kbuf = k; k 428 arch/parisc/kernel/ptrace.c const __u64 *k = kbuf; k 437 arch/parisc/kernel/ptrace.c regs->fr[pos++] = *k++; k 445 arch/parisc/kernel/ptrace.c kbuf = k; k 535 arch/parisc/kernel/ptrace.c unsigned long *k = kbuf; k 544 arch/parisc/kernel/ptrace.c *k++ = get_reg(regs, pos++); k 549 arch/parisc/kernel/ptrace.c kbuf = k; k 563 arch/parisc/kernel/ptrace.c const unsigned long *k = kbuf; k 572 arch/parisc/kernel/ptrace.c set_reg(regs, pos++, *k++); k 580 arch/parisc/kernel/ptrace.c kbuf = k; k 615 arch/parisc/kernel/ptrace.c compat_ulong_t *k = kbuf; k 624 arch/parisc/kernel/ptrace.c *k++ = get_reg(regs, pos++); k 630 arch/parisc/kernel/ptrace.c kbuf = k; k 644 arch/parisc/kernel/ptrace.c const compat_ulong_t *k = kbuf; k 653 arch/parisc/kernel/ptrace.c set_reg(regs, pos++, *k++); k 661 arch/parisc/kernel/ptrace.c kbuf = k; k 132 arch/powerpc/kernel/cacheinfo.c static struct cache_index_dir *kobj_to_cache_index_dir(struct kobject *k) k 134 arch/powerpc/kernel/cacheinfo.c return container_of(k, struct cache_index_dir, kobj); k 518 arch/powerpc/kernel/cacheinfo.c static ssize_t cache_index_show(struct kobject *k, struct attribute *attr, char *buf) k 524 arch/powerpc/kernel/cacheinfo.c return kobj_attr->show(k, kobj_attr, buf); k 527 arch/powerpc/kernel/cacheinfo.c static struct cache *index_kobj_to_cache(struct kobject *k) k 531 arch/powerpc/kernel/cacheinfo.c index = kobj_to_cache_index_dir(k); k 536 arch/powerpc/kernel/cacheinfo.c static ssize_t size_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 541 arch/powerpc/kernel/cacheinfo.c cache = index_kobj_to_cache(k); k 553 arch/powerpc/kernel/cacheinfo.c static ssize_t line_size_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 558 arch/powerpc/kernel/cacheinfo.c cache = index_kobj_to_cache(k); k 569 arch/powerpc/kernel/cacheinfo.c static ssize_t nr_sets_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 574 arch/powerpc/kernel/cacheinfo.c cache = index_kobj_to_cache(k); k 585 arch/powerpc/kernel/cacheinfo.c static ssize_t associativity_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 590 arch/powerpc/kernel/cacheinfo.c cache = index_kobj_to_cache(k); k 601 arch/powerpc/kernel/cacheinfo.c static ssize_t type_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 605 arch/powerpc/kernel/cacheinfo.c cache = index_kobj_to_cache(k); k 613 arch/powerpc/kernel/cacheinfo.c static ssize_t level_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 618 arch/powerpc/kernel/cacheinfo.c index = kobj_to_cache_index_dir(k); k 650 arch/powerpc/kernel/cacheinfo.c static ssize_t shared_cpu_map_show(struct kobject *k, struct kobj_attribute *attr, char *buf) k 657 arch/powerpc/kernel/cacheinfo.c index = kobj_to_cache_index_dir(k); k 2025 arch/powerpc/kernel/ptrace.c compat_ulong_t *k = kbuf; k 2034 arch/powerpc/kernel/ptrace.c *k++ = regs[pos++]; k 2043 arch/powerpc/kernel/ptrace.c *k++ = reg; k 2052 arch/powerpc/kernel/ptrace.c *k++ = regs[pos++]; k 2058 arch/powerpc/kernel/ptrace.c kbuf = k; k 2072 arch/powerpc/kernel/ptrace.c const compat_ulong_t *k = kbuf; k 2081 arch/powerpc/kernel/ptrace.c regs[pos++] = *k++; k 2092 arch/powerpc/kernel/ptrace.c reg = *k++; k 2102 arch/powerpc/kernel/ptrace.c regs[pos++] = *k++; k 2104 arch/powerpc/kernel/ptrace.c ++k; k 2118 arch/powerpc/kernel/ptrace.c reg = *k++; k 2126 arch/powerpc/kernel/ptrace.c kbuf = k; k 573 arch/powerpc/kvm/book3s_hv_rm_mmu.c long int i, j, k, n, found, indexes[4]; k 669 arch/powerpc/kvm/book3s_hv_rm_mmu.c for (k = 0; k < n; ++k) { k 670 arch/powerpc/kvm/book3s_hv_rm_mmu.c j = indexes[k]; k 672 arch/powerpc/kvm/book3s_hv_rm_mmu.c hp = hptes[k]; k 673 arch/powerpc/kvm/book3s_hv_rm_mmu.c rev = revs[k]; k 893 arch/powerpc/lib/test_emulate_step.c unsigned int i, j, k, instr; k 924 arch/powerpc/lib/test_emulate_step.c for (k = 0; k < 32; k++) { k 925 arch/powerpc/lib/test_emulate_step.c ignore_gpr = flags & IGNORE_GPR(k); k 926 arch/powerpc/lib/test_emulate_step.c if (!ignore_gpr && exp.gpr[k] != got.gpr[k]) { k 928 arch/powerpc/lib/test_emulate_step.c gpr_mismatch(k, exp.gpr[k], got.gpr[k]); k 13 arch/powerpc/mm/ptdump/bats.c static char *pp_601(int k, int pp) k 16 arch/powerpc/mm/ptdump/bats.c return k ? "NA" : "RWX"; k 18 arch/powerpc/mm/ptdump/bats.c return k ? "ROX" : "RWX"; k 20 arch/powerpc/mm/ptdump/bats.c return k ? "RWX" : "RWX"; k 21 arch/powerpc/mm/ptdump/bats.c return k ? "ROX" : "ROX"; k 27 arch/powerpc/mm/ptdump/bats.c u32 k = (upper >> 2) & 3; k 46 arch/powerpc/mm/ptdump/bats.c seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp)); k 75 arch/powerpc/mm/ptdump/bats.c u32 k = upper & 3; k 80 arch/powerpc/mm/ptdump/bats.c if (k == 0) { k 92 arch/powerpc/mm/ptdump/bats.c if (k == 1) k 94 arch/powerpc/mm/ptdump/bats.c else if (k == 2) k 124 arch/powerpc/net/bpf_jit_comp.c unsigned int K = filter[i].k; k 136 arch/powerpc/oprofile/cell/spu_profiler.c int cpu, node, k, num_samples, spu_num; k 165 arch/powerpc/oprofile/cell/spu_profiler.c for (k = 0; k < SPUS_PER_NODE; k++) { k 166 arch/powerpc/oprofile/cell/spu_profiler.c spu_num = k + (node * SPUS_PER_NODE); k 168 arch/powerpc/oprofile/cell/spu_profiler.c samples + (k * TRACE_ARRAY_SIZE), k 621 arch/powerpc/oprofile/cell/spu_task_sync.c int k; k 644 arch/powerpc/oprofile/cell/spu_task_sync.c for (k = 0; k < num_spu_nodes; k++) { k 645 arch/powerpc/oprofile/cell/spu_task_sync.c spu_buff[k].ctx_sw_seen = 0; k 651 arch/powerpc/oprofile/cell/spu_task_sync.c kfree(spu_buff[k].buff); k 652 arch/powerpc/oprofile/cell/spu_task_sync.c spu_buff[k].buff = 0; k 77 arch/powerpc/platforms/powermac/udbg_adb.c int k, t, on; k 84 arch/powerpc/platforms/powermac/udbg_adb.c k = -1; k 94 arch/powerpc/platforms/powermac/udbg_adb.c k = udbg_adb_old_getc_poll(); k 95 arch/powerpc/platforms/powermac/udbg_adb.c } while (k == -1 && xmon_adb_keycode == -1); k 98 arch/powerpc/platforms/powermac/udbg_adb.c if (k != -1) k 99 arch/powerpc/platforms/powermac/udbg_adb.c return k; k 100 arch/powerpc/platforms/powermac/udbg_adb.c k = xmon_adb_keycode; k 103 arch/powerpc/platforms/powermac/udbg_adb.c if ((k & 0x7f) == 0x38 || (k & 0x7f) == 0x7b) { k 104 arch/powerpc/platforms/powermac/udbg_adb.c xmon_adb_shiftstate = (k & 0x80) == 0; k 107 arch/powerpc/platforms/powermac/udbg_adb.c if (k >= 0x80) k 109 arch/powerpc/platforms/powermac/udbg_adb.c k = (xmon_adb_shiftstate? xmon_shift_keytab: xmon_keytab)[k]; k 110 arch/powerpc/platforms/powermac/udbg_adb.c if (k != 0) k 114 arch/powerpc/platforms/powermac/udbg_adb.c return k; k 1011 arch/s390/crypto/aes_s390.c u8 k[AES_MAX_KEY_SIZE]; /* Key */ k 1033 arch/s390/crypto/aes_s390.c memcpy(param.k, ctx->key, ctx->key_len); k 165 arch/s390/crypto/paes_s390.c unsigned int nbytes, n, k; k 172 arch/s390/crypto/paes_s390.c k = cpacf_km(ctx->fc | modifier, ctx->pk.protkey, k 174 arch/s390/crypto/paes_s390.c if (k) k 175 arch/s390/crypto/paes_s390.c ret = blkcipher_walk_done(desc, walk, nbytes - k); k 176 arch/s390/crypto/paes_s390.c if (k < n) { k 283 arch/s390/crypto/paes_s390.c unsigned int nbytes, n, k; k 296 arch/s390/crypto/paes_s390.c k = cpacf_kmc(ctx->fc | modifier, ¶m, k 298 arch/s390/crypto/paes_s390.c if (k) k 299 arch/s390/crypto/paes_s390.c ret = blkcipher_walk_done(desc, walk, nbytes - k); k 300 arch/s390/crypto/paes_s390.c if (k < n) { k 437 arch/s390/crypto/paes_s390.c unsigned int keylen, offset, nbytes, n, k; k 466 arch/s390/crypto/paes_s390.c k = cpacf_km(ctx->fc | modifier, xts_param.key + offset, k 468 arch/s390/crypto/paes_s390.c if (k) k 469 arch/s390/crypto/paes_s390.c ret = blkcipher_walk_done(desc, walk, nbytes - k); k 470 arch/s390/crypto/paes_s390.c if (k < n) { k 596 arch/s390/crypto/paes_s390.c unsigned int nbytes, n, k; k 607 arch/s390/crypto/paes_s390.c k = cpacf_kmctr(ctx->fc | modifier, ctx->pk.protkey, k 610 arch/s390/crypto/paes_s390.c if (k) { k 612 arch/s390/crypto/paes_s390.c memcpy(walk->iv, ctrptr + k - AES_BLOCK_SIZE, k 617 arch/s390/crypto/paes_s390.c if (k < n) { k 89 arch/s390/include/asm/kvm_host.h unsigned long k : 1; k 21 arch/s390/include/asm/termios.h #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) k 22 arch/s390/include/asm/termios.h #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) k 17 arch/s390/include/uapi/asm/runtime_instr.h __u32 k : 1; k 901 arch/s390/kernel/ptrace.c unsigned long *k = kbuf; k 903 arch/s390/kernel/ptrace.c *k++ = __peek_user(target, pos); k 904 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 905 arch/s390/kernel/ptrace.c pos += sizeof(*k); k 930 arch/s390/kernel/ptrace.c const unsigned long *k = kbuf; k 932 arch/s390/kernel/ptrace.c rc = __poke_user(target, pos, *k++); k 933 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 934 arch/s390/kernel/ptrace.c pos += sizeof(*k); k 1020 arch/s390/kernel/ptrace.c unsigned long *k = kbuf; k 1021 arch/s390/kernel/ptrace.c *k = target->thread.last_break; k 1251 arch/s390/kernel/ptrace.c cb->k == 1 && k 1435 arch/s390/kernel/ptrace.c compat_ulong_t *k = kbuf; k 1437 arch/s390/kernel/ptrace.c *k++ = __peek_user_compat(target, pos); k 1438 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 1439 arch/s390/kernel/ptrace.c pos += sizeof(*k); k 1464 arch/s390/kernel/ptrace.c const compat_ulong_t *k = kbuf; k 1466 arch/s390/kernel/ptrace.c rc = __poke_user_compat(target, pos, *k++); k 1467 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 1468 arch/s390/kernel/ptrace.c pos += sizeof(*k); k 1499 arch/s390/kernel/ptrace.c compat_ulong_t *k = kbuf; k 1501 arch/s390/kernel/ptrace.c *k++ = *gprs_high; k 1503 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 1528 arch/s390/kernel/ptrace.c const compat_ulong_t *k = kbuf; k 1530 arch/s390/kernel/ptrace.c *gprs_high = *k++; k 1532 arch/s390/kernel/ptrace.c count -= sizeof(*k); k 1560 arch/s390/kernel/ptrace.c unsigned long *k = kbuf; k 1561 arch/s390/kernel/ptrace.c *k = last_break; k 57 arch/s390/kernel/runtime_instr.c cb->k = 1; k 290 arch/s390/kvm/gaccess.c if (old.k) { k 296 arch/s390/kvm/gaccess.c new.k = 1; k 316 arch/s390/kvm/gaccess.c new.k = 0; k 339 arch/s390/kvm/gaccess.c new.k = 1; k 356 arch/s390/kvm/gaccess.c new.k = 0; k 117 arch/sh/boards/mach-migor/lcd_qvga.c int k; k 151 arch/sh/boards/mach-migor/lcd_qvga.c for (k = 0; k < (xres * 256); k++) /* yes, 256 words per line */ k 135 arch/sh/kernel/cpu/sh2a/clock-sh7264.c int k, ret = 0; k 145 arch/sh/kernel/cpu/sh2a/clock-sh7264.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 146 arch/sh/kernel/cpu/sh2a/clock-sh7264.c ret = clk_register(main_clks[k]); k 167 arch/sh/kernel/cpu/sh2a/clock-sh7269.c int k, ret = 0; k 169 arch/sh/kernel/cpu/sh2a/clock-sh7269.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 170 arch/sh/kernel/cpu/sh2a/clock-sh7269.c ret = clk_register(main_clks[k]); k 254 arch/sh/kernel/cpu/sh4a/clock-sh7343.c int k, ret = 0; k 262 arch/sh/kernel/cpu/sh4a/clock-sh7343.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 263 arch/sh/kernel/cpu/sh4a/clock-sh7343.c ret = clk_register(main_clks[k]); k 247 arch/sh/kernel/cpu/sh4a/clock-sh7366.c int k, ret = 0; k 255 arch/sh/kernel/cpu/sh4a/clock-sh7366.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 256 arch/sh/kernel/cpu/sh4a/clock-sh7366.c ret = clk_register(main_clks[k]); k 222 arch/sh/kernel/cpu/sh4a/clock-sh7722.c int k, ret = 0; k 230 arch/sh/kernel/cpu/sh4a/clock-sh7722.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 231 arch/sh/kernel/cpu/sh4a/clock-sh7722.c ret = clk_register(main_clks[k]); k 270 arch/sh/kernel/cpu/sh4a/clock-sh7723.c int k, ret = 0; k 278 arch/sh/kernel/cpu/sh4a/clock-sh7723.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 279 arch/sh/kernel/cpu/sh4a/clock-sh7723.c ret |= clk_register(main_clks[k]); k 344 arch/sh/kernel/cpu/sh4a/clock-sh7724.c int k, ret = 0; k 352 arch/sh/kernel/cpu/sh4a/clock-sh7724.c for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) k 353 arch/sh/kernel/cpu/sh4a/clock-sh7724.c ret = clk_register(main_clks[k]); k 31 arch/sh/kernel/cpu/shmobile/cpuidle.c int k; k 34 arch/sh/kernel/cpu/shmobile/cpuidle.c for (k = ARRAY_SIZE(cpuidle_mode) - 1; k > 0; k--) k 35 arch/sh/kernel/cpu/shmobile/cpuidle.c if (cpuidle_mode[k] == allowed_mode) k 38 arch/sh/kernel/cpu/shmobile/cpuidle.c allowed_state = k; k 44 arch/sh/kernel/cpu/shmobile/cpuidle.c k = min_t(int, allowed_state, requested_state); k 46 arch/sh/kernel/cpu/shmobile/cpuidle.c sh_mobile_call_standby(cpuidle_mode[k]); k 48 arch/sh/kernel/cpu/shmobile/cpuidle.c return k; k 51 arch/sh/kernel/dma-coherent.c int k; k 56 arch/sh/kernel/dma-coherent.c for (k = 0; k < (1 << order); k++) k 57 arch/sh/kernel/dma-coherent.c __free_pages(pfn_to_page(pfn + k), 0); k 46 arch/sh/kernel/io_trapped.c int k, n; k 55 arch/sh/kernel/io_trapped.c for (k = 0; k < tiop->num_resources; k++) { k 56 arch/sh/kernel/io_trapped.c res = tiop->resource + k; k 70 arch/sh/kernel/io_trapped.c for (k = 0; k < n; k++) k 71 arch/sh/kernel/io_trapped.c pages[k] = virt_to_page(tiop); k 78 arch/sh/kernel/io_trapped.c for (k = 0; k < tiop->num_resources; k++) { k 79 arch/sh/kernel/io_trapped.c res = tiop->resource + k; k 114 arch/sh/kernel/io_trapped.c int k, len; k 120 arch/sh/kernel/io_trapped.c for (k = 0; k < tiop->num_resources; k++) { k 121 arch/sh/kernel/io_trapped.c res = tiop->resource + k; k 168 arch/sh/kernel/io_trapped.c int k; k 170 arch/sh/kernel/io_trapped.c for (k = 0; k < tiop->num_resources; k++) { k 171 arch/sh/kernel/io_trapped.c res = tiop->resource + k; k 23 arch/sh/mm/consistent.c int k = strlen(name); k 27 arch/sh/mm/consistent.c if (!strncmp(name, p, k) && p[k] == '=') { k 28 arch/sh/mm/consistent.c p += k + 1; k 171 arch/sh/mm/init.c int i, j, k; k 177 arch/sh/mm/init.c k = __pmd_offset(vaddr); k 185 arch/sh/mm/init.c pmd += k; k 187 arch/sh/mm/init.c for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { k 192 arch/sh/mm/init.c k = 0; k 67 arch/sparc/include/asm/termios.h #define user_termios_to_kernel_termios(k, u) \ k 70 arch/sparc/include/asm/termios.h err = get_user((k)->c_iflag, &(u)->c_iflag); \ k 71 arch/sparc/include/asm/termios.h err |= get_user((k)->c_oflag, &(u)->c_oflag); \ k 72 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cflag, &(u)->c_cflag); \ k 73 arch/sparc/include/asm/termios.h err |= get_user((k)->c_lflag, &(u)->c_lflag); \ k 74 arch/sparc/include/asm/termios.h err |= get_user((k)->c_line, &(u)->c_line); \ k 75 arch/sparc/include/asm/termios.h err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \ k 76 arch/sparc/include/asm/termios.h if ((k)->c_lflag & ICANON) { \ k 77 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \ k 78 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \ k 80 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \ k 81 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \ k 83 arch/sparc/include/asm/termios.h err |= get_user((k)->c_ispeed, &(u)->c_ispeed); \ k 84 arch/sparc/include/asm/termios.h err |= get_user((k)->c_ospeed, &(u)->c_ospeed); \ k 88 arch/sparc/include/asm/termios.h #define kernel_termios_to_user_termios(u, k) \ k 91 arch/sparc/include/asm/termios.h err = put_user((k)->c_iflag, &(u)->c_iflag); \ k 92 arch/sparc/include/asm/termios.h err |= put_user((k)->c_oflag, &(u)->c_oflag); \ k 93 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cflag, &(u)->c_cflag); \ k 94 arch/sparc/include/asm/termios.h err |= put_user((k)->c_lflag, &(u)->c_lflag); \ k 95 arch/sparc/include/asm/termios.h err |= put_user((k)->c_line, &(u)->c_line); \ k 96 arch/sparc/include/asm/termios.h err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \ k 97 arch/sparc/include/asm/termios.h if (!((k)->c_lflag & ICANON)) { \ k 98 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \ k 99 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \ k 101 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \ k 102 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \ k 104 arch/sparc/include/asm/termios.h err |= put_user((k)->c_ispeed, &(u)->c_ispeed); \ k 105 arch/sparc/include/asm/termios.h err |= put_user((k)->c_ospeed, &(u)->c_ospeed); \ k 109 arch/sparc/include/asm/termios.h #define user_termios_to_kernel_termios_1(k, u) \ k 112 arch/sparc/include/asm/termios.h err = get_user((k)->c_iflag, &(u)->c_iflag); \ k 113 arch/sparc/include/asm/termios.h err |= get_user((k)->c_oflag, &(u)->c_oflag); \ k 114 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cflag, &(u)->c_cflag); \ k 115 arch/sparc/include/asm/termios.h err |= get_user((k)->c_lflag, &(u)->c_lflag); \ k 116 arch/sparc/include/asm/termios.h err |= get_user((k)->c_line, &(u)->c_line); \ k 117 arch/sparc/include/asm/termios.h err |= copy_from_user((k)->c_cc, (u)->c_cc, NCCS); \ k 118 arch/sparc/include/asm/termios.h if ((k)->c_lflag & ICANON) { \ k 119 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \ k 120 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \ k 122 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \ k 123 arch/sparc/include/asm/termios.h err |= get_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \ k 128 arch/sparc/include/asm/termios.h #define kernel_termios_to_user_termios_1(u, k) \ k 131 arch/sparc/include/asm/termios.h err = put_user((k)->c_iflag, &(u)->c_iflag); \ k 132 arch/sparc/include/asm/termios.h err |= put_user((k)->c_oflag, &(u)->c_oflag); \ k 133 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cflag, &(u)->c_cflag); \ k 134 arch/sparc/include/asm/termios.h err |= put_user((k)->c_lflag, &(u)->c_lflag); \ k 135 arch/sparc/include/asm/termios.h err |= put_user((k)->c_line, &(u)->c_line); \ k 136 arch/sparc/include/asm/termios.h err |= copy_to_user((u)->c_cc, (k)->c_cc, NCCS); \ k 137 arch/sparc/include/asm/termios.h if (!((k)->c_lflag & ICANON)) { \ k 138 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VMIN], &(u)->c_cc[_VMIN]); \ k 139 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VTIME], &(u)->c_cc[_VTIME]); \ k 141 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VEOF], &(u)->c_cc[VEOF]); \ k 142 arch/sparc/include/asm/termios.h err |= put_user((k)->c_cc[VEOL], &(u)->c_cc[VEOL]); \ k 56 arch/sparc/kernel/ptrace_32.c unsigned long *k = kbuf; k 68 arch/sparc/kernel/ptrace_32.c *k++ = regs->u_regs[pos++]; k 73 arch/sparc/kernel/ptrace_32.c if (get_user(*k++, ®_window[pos++])) k 113 arch/sparc/kernel/ptrace_32.c *k++ = reg; k 134 arch/sparc/kernel/ptrace_32.c const unsigned long *k = kbuf; k 146 arch/sparc/kernel/ptrace_32.c regs->u_regs[pos++] = *k++; k 151 arch/sparc/kernel/ptrace_32.c if (put_user(*k++, ®_window[pos++])) k 173 arch/sparc/kernel/ptrace_32.c reg = *k++; k 523 arch/sparc/kernel/ptrace_64.c compat_ulong_t *k = kbuf; k 535 arch/sparc/kernel/ptrace_64.c *k++ = regs->u_regs[pos++]; k 541 arch/sparc/kernel/ptrace_64.c if (get_user(*k++, ®_window[pos++])) k 549 arch/sparc/kernel/ptrace_64.c k, sizeof(*k), k 551 arch/sparc/kernel/ptrace_64.c != sizeof(*k)) k 553 arch/sparc/kernel/ptrace_64.c k++; k 614 arch/sparc/kernel/ptrace_64.c *k++ = reg; k 635 arch/sparc/kernel/ptrace_64.c const compat_ulong_t *k = kbuf; k 647 arch/sparc/kernel/ptrace_64.c regs->u_regs[pos++] = *k++; k 653 arch/sparc/kernel/ptrace_64.c if (put_user(*k++, ®_window[pos++])) k 661 arch/sparc/kernel/ptrace_64.c (void *) k, k 662 arch/sparc/kernel/ptrace_64.c sizeof(*k), k 664 arch/sparc/kernel/ptrace_64.c != sizeof(*k)) k 666 arch/sparc/kernel/ptrace_64.c k++; k 710 arch/sparc/kernel/ptrace_64.c reg = *k++; k 97 arch/sparc/mm/io-unit.c int i, j, k, npages; k 128 arch/sparc/mm/io-unit.c for (k = 1, scan++; k < npages; k++) k 135 arch/sparc/mm/io-unit.c for (k = 0; k < npages; k++, iopte = __iopte(iopte_val(iopte) + 0x100), scan++) { k 391 arch/sparc/net/bpf_jit_comp_32.c unsigned int K = filter[i].k; k 82 arch/sparc/vdso/vdso2c.h int k; k 89 arch/sparc/vdso/vdso2c.h for (k = 0; k < NSYMS; k++) { k 90 arch/sparc/vdso/vdso2c.h if (!strcmp(name, required_syms[k].name)) { k 91 arch/sparc/vdso/vdso2c.h if (syms[k]) { k 93 arch/sparc/vdso/vdso2c.h required_syms[k].name); k 102 arch/sparc/vdso/vdso2c.h syms[k] = GET_BE(&sym->st_value); k 185 arch/x86/boot/compressed/kaslr.c char *k = strchr(str, ','); k 187 arch/x86/boot/compressed/kaslr.c if (k) k 188 arch/x86/boot/compressed/kaslr.c *k++ = 0; k 193 arch/x86/boot/compressed/kaslr.c str = k; k 93 arch/x86/entry/vdso/vdso2c.h int k; k 100 arch/x86/entry/vdso/vdso2c.h for (k = 0; k < NSYMS; k++) { k 101 arch/x86/entry/vdso/vdso2c.h if (!strcmp(sym_name, required_syms[k].name)) { k 102 arch/x86/entry/vdso/vdso2c.h if (syms[k]) { k 104 arch/x86/entry/vdso/vdso2c.h required_syms[k].name); k 113 arch/x86/entry/vdso/vdso2c.h syms[k] = GET_LE(&sym->st_value); k 805 arch/x86/kernel/cpu/cacheinfo.c unsigned char k = 0; k 808 arch/x86/kernel/cpu/cacheinfo.c while (cache_table[k].descriptor != 0) { k 809 arch/x86/kernel/cpu/cacheinfo.c if (cache_table[k].descriptor == des) { k 810 arch/x86/kernel/cpu/cacheinfo.c if (only_trace && cache_table[k].cache_type != LVL_TRACE) k 812 arch/x86/kernel/cpu/cacheinfo.c switch (cache_table[k].cache_type) { k 814 arch/x86/kernel/cpu/cacheinfo.c l1i += cache_table[k].size; k 817 arch/x86/kernel/cpu/cacheinfo.c l1d += cache_table[k].size; k 820 arch/x86/kernel/cpu/cacheinfo.c l2 += cache_table[k].size; k 823 arch/x86/kernel/cpu/cacheinfo.c l3 += cache_table[k].size; k 826 arch/x86/kernel/cpu/cacheinfo.c trace += cache_table[k].size; k 833 arch/x86/kernel/cpu/cacheinfo.c k++; k 857 arch/x86/kernel/cpu/intel.c unsigned char k; k 862 arch/x86/kernel/cpu/intel.c for (k = 0; intel_tlb_table[k].descriptor != desc && \ k 863 arch/x86/kernel/cpu/intel.c intel_tlb_table[k].descriptor != 0; k++) k 866 arch/x86/kernel/cpu/intel.c if (intel_tlb_table[k].tlb_type == 0) k 869 arch/x86/kernel/cpu/intel.c switch (intel_tlb_table[k].tlb_type) { k 871 arch/x86/kernel/cpu/intel.c if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) k 872 arch/x86/kernel/cpu/intel.c tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; k 873 arch/x86/kernel/cpu/intel.c if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) k 874 arch/x86/kernel/cpu/intel.c tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; k 877 arch/x86/kernel/cpu/intel.c if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) k 878 arch/x86/kernel/cpu/intel.c tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; k 879 arch/x86/kernel/cpu/intel.c if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) k 880 arch/x86/kernel/cpu/intel.c tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; k 881 arch/x86/kernel/cpu/intel.c if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) k 882 arch/x86/kernel/cpu/intel.c tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; k 883 arch/x86/kernel/cpu/intel.c if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) k 884 arch/x86/kernel/cpu/intel.c tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; k 885 arch/x86/kernel/cpu/intel.c if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) k 886 arch/x86/kernel/cpu/intel.c tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; k 887 arch/x86/kernel/cpu/intel.c if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) k 888 arch/x86/kernel/cpu/intel.c tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; k 891 arch/x86/kernel/cpu/intel.c if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) k 892 arch/x86/kernel/cpu/intel.c tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; k 893 arch/x86/kernel/cpu/intel.c if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) k 894 arch/x86/kernel/cpu/intel.c tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; k 895 arch/x86/kernel/cpu/intel.c if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) k 896 arch/x86/kernel/cpu/intel.c tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; k 899 arch/x86/kernel/cpu/intel.c if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) k 900 arch/x86/kernel/cpu/intel.c tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; k 903 arch/x86/kernel/cpu/intel.c if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) k 904 arch/x86/kernel/cpu/intel.c tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; k 907 arch/x86/kernel/cpu/intel.c if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) k 908 arch/x86/kernel/cpu/intel.c tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; k 909 arch/x86/kernel/cpu/intel.c if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) k 910 arch/x86/kernel/cpu/intel.c tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; k 914 arch/x86/kernel/cpu/intel.c if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) k 915 arch/x86/kernel/cpu/intel.c tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; k 919 arch/x86/kernel/cpu/intel.c if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) k 920 arch/x86/kernel/cpu/intel.c tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; k 924 arch/x86/kernel/cpu/intel.c if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) k 925 arch/x86/kernel/cpu/intel.c tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; k 926 arch/x86/kernel/cpu/intel.c if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) k 927 arch/x86/kernel/cpu/intel.c tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; k 930 arch/x86/kernel/cpu/intel.c if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) k 931 arch/x86/kernel/cpu/intel.c tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; k 932 arch/x86/kernel/cpu/intel.c if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) k 933 arch/x86/kernel/cpu/intel.c tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; k 936 arch/x86/kernel/cpu/intel.c if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) k 937 arch/x86/kernel/cpu/intel.c tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; k 1133 arch/x86/kernel/cpu/mce/amd.c #define to_block(k) container_of(k, struct threshold_block, kobj) k 92 arch/x86/kernel/dumpstack_64.c unsigned int k; k 110 arch/x86/kernel/dumpstack_64.c k = (stk - begin) >> PAGE_SHIFT; k 112 arch/x86/kernel/dumpstack_64.c ep = &estack_pages[k]; k 971 arch/x86/kernel/e820.c char *k = strchr(str, ','); k 973 arch/x86/kernel/e820.c if (k) k 974 arch/x86/kernel/e820.c *k++ = 0; k 977 arch/x86/kernel/e820.c str = k; k 35 arch/x86/kernel/early_printk.c int i, k, j; k 40 arch/x86/kernel/early_printk.c for (k = 1, j = 0; k < max_ypos; k++, j++) { k 42 arch/x86/kernel/early_printk.c writew(readw(VGABASE+2*(max_xpos*k+i)), k 428 arch/x86/kernel/ptrace.c unsigned long *k = kbuf; k 429 arch/x86/kernel/ptrace.c while (count >= sizeof(*k)) { k 430 arch/x86/kernel/ptrace.c *k++ = getreg(target, pos); k 431 arch/x86/kernel/ptrace.c count -= sizeof(*k); k 432 arch/x86/kernel/ptrace.c pos += sizeof(*k); k 454 arch/x86/kernel/ptrace.c const unsigned long *k = kbuf; k 455 arch/x86/kernel/ptrace.c while (count >= sizeof(*k) && !ret) { k 456 arch/x86/kernel/ptrace.c ret = putreg(target, pos, *k++); k 457 arch/x86/kernel/ptrace.c count -= sizeof(*k); k 458 arch/x86/kernel/ptrace.c pos += sizeof(*k); k 995 arch/x86/kernel/ptrace.c compat_ulong_t *k = kbuf; k 996 arch/x86/kernel/ptrace.c while (count >= sizeof(*k)) { k 997 arch/x86/kernel/ptrace.c getreg32(target, pos, k++); k 998 arch/x86/kernel/ptrace.c count -= sizeof(*k); k 999 arch/x86/kernel/ptrace.c pos += sizeof(*k); k 1023 arch/x86/kernel/ptrace.c const compat_ulong_t *k = kbuf; k 1024 arch/x86/kernel/ptrace.c while (count >= sizeof(*k) && !ret) { k 1025 arch/x86/kernel/ptrace.c ret = putreg32(target, pos, *k++); k 1026 arch/x86/kernel/ptrace.c count -= sizeof(*k); k 1027 arch/x86/kernel/ptrace.c pos += sizeof(*k); k 10122 arch/x86/kvm/x86.c u32 i, j, k; k 10131 arch/x86/kvm/x86.c k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); k 10137 arch/x86/kvm/x86.c } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); k 234 arch/x86/mm/numa.c int i, j, k; k 285 arch/x86/mm/numa.c for (k = 0; k < mi->nr_blks; k++) { k 286 arch/x86/mm/numa.c struct numa_memblk *bk = &mi->blk[k]; k 293 arch/x86/mm/numa.c if (k < mi->nr_blks) k 125 arch/x86/mm/pageattr-test.c int i, k; k 152 arch/x86/mm/pageattr-test.c for (k = 0; k < len[i]; k++) { k 153 arch/x86/mm/pageattr-test.c pte = lookup_address(addr[i] + k*PAGE_SIZE, &level); k 159 arch/x86/mm/pageattr-test.c if (k == 0) { k 164 arch/x86/mm/pageattr-test.c len[i] = k; k 168 arch/x86/mm/pageattr-test.c if (test_bit(pfn + k, bm)) { k 169 arch/x86/mm/pageattr-test.c len[i] = k; k 172 arch/x86/mm/pageattr-test.c __set_bit(pfn + k, bm); k 173 arch/x86/mm/pageattr-test.c addrs[k] = addr[i] + k*PAGE_SIZE; k 174 arch/x86/mm/pageattr-test.c pages[k] = pfn_to_page(pfn + k); k 176 arch/x86/mm/pageattr-test.c if (!addr[i] || !pte || !k) { k 93 arch/x86/net/bpf_jit_comp32.c #define STACK_OFFSET(k) (k) k 576 arch/x86/platform/uv/uv_nmi.c int i, j, k, n = num_online_cpus(); k 582 arch/x86/platform/uv/uv_nmi.c k = 0; k 584 arch/x86/platform/uv/uv_nmi.c k = n - cpumask_weight(uv_nmi_cpu_mask); k 590 arch/x86/platform/uv/uv_nmi.c return n - k - 1; k 600 arch/x86/platform/uv/uv_nmi.c if (++k >= n) k 604 arch/x86/platform/uv/uv_nmi.c if (k >= n) { /* all in? */ k 605 arch/x86/platform/uv/uv_nmi.c k = n; k 608 arch/x86/platform/uv/uv_nmi.c if (last_k != k) { /* abort if no new CPU's coming in */ k 609 arch/x86/platform/uv/uv_nmi.c last_k = k; k 615 arch/x86/platform/uv/uv_nmi.c if (waiting && (n - k) == 1 && k 621 arch/x86/platform/uv/uv_nmi.c atomic_set(&uv_nmi_cpus_in_nmi, k); k 622 arch/x86/platform/uv/uv_nmi.c return n - k; k 236 arch/x86/um/ldt.c int i, size, k, order; k 288 arch/x86/um/ldt.c for (i=0, k=0; i<ret/LDT_ENTRY_SIZE; i++) { k 290 arch/x86/um/ldt.c host_ldt_entries[k++] = i; k 292 arch/x86/um/ldt.c host_ldt_entries[k] = -1; k 243 arch/xtensa/mm/init.c char *k = strchr(str, ','); k 245 arch/xtensa/mm/init.c if (k) k 246 arch/xtensa/mm/init.c *k++ = 0; k 249 arch/xtensa/mm/init.c str = k; k 55 arch/xtensa/mm/kasan_init.c int k; k 57 arch/xtensa/mm/kasan_init.c for (k = 0; k < PTRS_PER_PTE; ++k, ++j) { k 2427 block/blk-mq.c int k; k 2431 block/blk-mq.c for (k = HCTX_TYPE_DEFAULT; k < HCTX_MAX_TYPES; k++) k 2432 block/blk-mq.c INIT_LIST_HEAD(&__ctx->rq_lists[k]); k 1153 crypto/aes_generic.c #define f_rn(bo, bi, n, k) do { \ k 1157 crypto/aes_generic.c crypto_ft_tab[3][byte(bi[(n + 3) & 3], 3)] ^ *(k + n); \ k 1160 crypto/aes_generic.c #define f_nround(bo, bi, k) do {\ k 1161 crypto/aes_generic.c f_rn(bo, bi, 0, k); \ k 1162 crypto/aes_generic.c f_rn(bo, bi, 1, k); \ k 1163 crypto/aes_generic.c f_rn(bo, bi, 2, k); \ k 1164 crypto/aes_generic.c f_rn(bo, bi, 3, k); \ k 1165 crypto/aes_generic.c k += 4; \ k 1168 crypto/aes_generic.c #define f_rl(bo, bi, n, k) do { \ k 1172 crypto/aes_generic.c crypto_fl_tab[3][byte(bi[(n + 3) & 3], 3)] ^ *(k + n); \ k 1175 crypto/aes_generic.c #define f_lround(bo, bi, k) do {\ k 1176 crypto/aes_generic.c f_rl(bo, bi, 0, k); \ k 1177 crypto/aes_generic.c f_rl(bo, bi, 1, k); \ k 1178 crypto/aes_generic.c f_rl(bo, bi, 2, k); \ k 1179 crypto/aes_generic.c f_rl(bo, bi, 3, k); \ k 1223 crypto/aes_generic.c #define i_rn(bo, bi, n, k) do { \ k 1227 crypto/aes_generic.c crypto_it_tab[3][byte(bi[(n + 1) & 3], 3)] ^ *(k + n); \ k 1230 crypto/aes_generic.c #define i_nround(bo, bi, k) do {\ k 1231 crypto/aes_generic.c i_rn(bo, bi, 0, k); \ k 1232 crypto/aes_generic.c i_rn(bo, bi, 1, k); \ k 1233 crypto/aes_generic.c i_rn(bo, bi, 2, k); \ k 1234 crypto/aes_generic.c i_rn(bo, bi, 3, k); \ k 1235 crypto/aes_generic.c k += 4; \ k 1238 crypto/aes_generic.c #define i_rl(bo, bi, n, k) do { \ k 1242 crypto/aes_generic.c crypto_il_tab[3][byte(bi[(n + 1) & 3], 3)] ^ *(k + n); \ k 1245 crypto/aes_generic.c #define i_lround(bo, bi, k) do {\ k 1246 crypto/aes_generic.c i_rl(bo, bi, 0, k); \ k 1247 crypto/aes_generic.c i_rl(bo, bi, 1, k); \ k 1248 crypto/aes_generic.c i_rl(bo, bi, 2, k); \ k 1249 crypto/aes_generic.c i_rl(bo, bi, 3, k); \ k 404 crypto/cast5_generic.c static void key_schedule(u32 *x, u32 *z, u32 *k) k 418 crypto/cast5_generic.c k[0] = s5[zi(8)] ^ s6[zi(9)] ^ s7[zi(7)] ^ sb8[zi(6)] ^ s5[zi(2)]; k 419 crypto/cast5_generic.c k[1] = s5[zi(10)] ^ s6[zi(11)] ^ s7[zi(5)] ^ sb8[zi(4)] ^ k 421 crypto/cast5_generic.c k[2] = s5[zi(12)] ^ s6[zi(13)] ^ s7[zi(3)] ^ sb8[zi(2)] ^ k 423 crypto/cast5_generic.c k[3] = s5[zi(14)] ^ s6[zi(15)] ^ s7[zi(1)] ^ sb8[zi(0)] ^ k 434 crypto/cast5_generic.c k[4] = s5[xi(3)] ^ s6[xi(2)] ^ s7[xi(12)] ^ sb8[xi(13)] ^ k 436 crypto/cast5_generic.c k[5] = s5[xi(1)] ^ s6[xi(0)] ^ s7[xi(14)] ^ sb8[xi(15)] ^ k 438 crypto/cast5_generic.c k[6] = s5[xi(7)] ^ s6[xi(6)] ^ s7[xi(8)] ^ sb8[xi(9)] ^ s7[xi(3)]; k 439 crypto/cast5_generic.c k[7] = s5[xi(5)] ^ s6[xi(4)] ^ s7[xi(10)] ^ sb8[xi(11)] ^ k 450 crypto/cast5_generic.c k[8] = s5[zi(3)] ^ s6[zi(2)] ^ s7[zi(12)] ^ sb8[zi(13)] ^ k 452 crypto/cast5_generic.c k[9] = s5[zi(1)] ^ s6[zi(0)] ^ s7[zi(14)] ^ sb8[zi(15)] ^ k 454 crypto/cast5_generic.c k[10] = s5[zi(7)] ^ s6[zi(6)] ^ s7[zi(8)] ^ sb8[zi(9)] ^ s7[zi(2)]; k 455 crypto/cast5_generic.c k[11] = s5[zi(5)] ^ s6[zi(4)] ^ s7[zi(10)] ^ sb8[zi(11)] ^ k 466 crypto/cast5_generic.c k[12] = s5[xi(8)] ^ s6[xi(9)] ^ s7[xi(7)] ^ sb8[xi(6)] ^ s5[xi(3)]; k 467 crypto/cast5_generic.c k[13] = s5[xi(10)] ^ s6[xi(11)] ^ s7[xi(5)] ^ sb8[xi(4)] ^ k 469 crypto/cast5_generic.c k[14] = s5[xi(12)] ^ s6[xi(13)] ^ s7[xi(3)] ^ sb8[xi(2)] ^ k 471 crypto/cast5_generic.c k[15] = s5[xi(14)] ^ s6[xi(15)] ^ s7[xi(1)] ^ sb8[xi(0)] ^ k 485 crypto/cast5_generic.c u32 k[16]; k 499 crypto/cast5_generic.c key_schedule(x, z, k); k 501 crypto/cast5_generic.c c->Km[i] = k[i]; k 502 crypto/cast5_generic.c key_schedule(x, z, k); k 504 crypto/cast5_generic.c c->Kr[i] = k[i] & 0x1f; k 382 crypto/ecc.c unsigned int i, k; k 387 crypto/ecc.c for (k = 0; k < ndigits * 2 - 1; k++) { k 390 crypto/ecc.c if (k < ndigits) k 393 crypto/ecc.c min = (k + 1) - ndigits; k 395 crypto/ecc.c for (i = min; i <= k && i < ndigits; i++) { k 398 crypto/ecc.c product = mul_64_64(left[i], right[k - i]); k 404 crypto/ecc.c result[k] = r01.m_low; k 418 crypto/ecc.c unsigned int k; k 420 crypto/ecc.c for (k = 0; k < ndigits; k++) { k 423 crypto/ecc.c product = mul_64_64(left[k], right); k 426 crypto/ecc.c result[k] = r01.m_low; k 430 crypto/ecc.c result[k] = r01.m_low; k 431 crypto/ecc.c for (++k; k < ndigits * 2; k++) k 432 crypto/ecc.c result[k] = 0; k 439 crypto/ecc.c int i, k; k 441 crypto/ecc.c for (k = 0; k < ndigits * 2 - 1; k++) { k 444 crypto/ecc.c if (k < ndigits) k 447 crypto/ecc.c min = (k + 1) - ndigits; k 449 crypto/ecc.c for (i = min; i <= k && i <= k - i; i++) { k 452 crypto/ecc.c product = mul_64_64(left[i], left[k - i]); k 454 crypto/ecc.c if (i < k - i) { k 465 crypto/ecc.c result[k] = r01.m_low; k 66 crypto/fcrypt.c #define ror56_64(k, n) \ k 68 crypto/fcrypt.c k = (k >> n) | ((k & ((1 << n) - 1)) << (56 - n)); \ k 311 crypto/fcrypt.c u64 k; /* k holds all 56 non-parity bits */ k 314 crypto/fcrypt.c k = (*key++) >> 1; k 315 crypto/fcrypt.c k <<= 7; k 316 crypto/fcrypt.c k |= (*key++) >> 1; k 317 crypto/fcrypt.c k <<= 7; k 318 crypto/fcrypt.c k |= (*key++) >> 1; k 319 crypto/fcrypt.c k <<= 7; k 320 crypto/fcrypt.c k |= (*key++) >> 1; k 321 crypto/fcrypt.c k <<= 7; k 322 crypto/fcrypt.c k |= (*key++) >> 1; k 323 crypto/fcrypt.c k <<= 7; k 324 crypto/fcrypt.c k |= (*key++) >> 1; k 325 crypto/fcrypt.c k <<= 7; k 326 crypto/fcrypt.c k |= (*key++) >> 1; k 327 crypto/fcrypt.c k <<= 7; k 328 crypto/fcrypt.c k |= (*key) >> 1; k 331 crypto/fcrypt.c ctx->sched[0x0] = cpu_to_be32(k); ror56_64(k, 11); k 332 crypto/fcrypt.c ctx->sched[0x1] = cpu_to_be32(k); ror56_64(k, 11); k 333 crypto/fcrypt.c ctx->sched[0x2] = cpu_to_be32(k); ror56_64(k, 11); k 334 crypto/fcrypt.c ctx->sched[0x3] = cpu_to_be32(k); ror56_64(k, 11); k 335 crypto/fcrypt.c ctx->sched[0x4] = cpu_to_be32(k); ror56_64(k, 11); k 336 crypto/fcrypt.c ctx->sched[0x5] = cpu_to_be32(k); ror56_64(k, 11); k 337 crypto/fcrypt.c ctx->sched[0x6] = cpu_to_be32(k); ror56_64(k, 11); k 338 crypto/fcrypt.c ctx->sched[0x7] = cpu_to_be32(k); ror56_64(k, 11); k 339 crypto/fcrypt.c ctx->sched[0x8] = cpu_to_be32(k); ror56_64(k, 11); k 340 crypto/fcrypt.c ctx->sched[0x9] = cpu_to_be32(k); ror56_64(k, 11); k 341 crypto/fcrypt.c ctx->sched[0xa] = cpu_to_be32(k); ror56_64(k, 11); k 342 crypto/fcrypt.c ctx->sched[0xb] = cpu_to_be32(k); ror56_64(k, 11); k 343 crypto/fcrypt.c ctx->sched[0xc] = cpu_to_be32(k); ror56_64(k, 11); k 344 crypto/fcrypt.c ctx->sched[0xd] = cpu_to_be32(k); ror56_64(k, 11); k 345 crypto/fcrypt.c ctx->sched[0xe] = cpu_to_be32(k); ror56_64(k, 11); k 346 crypto/fcrypt.c ctx->sched[0xf] = cpu_to_be32(k); k 263 crypto/gf128mul.c int i, j, k; k 284 crypto/gf128mul.c for (k = 1; k < j; ++k) k 285 crypto/gf128mul.c be128_xor(&t->t[i]->t[j + k], k 286 crypto/gf128mul.c &t->t[i]->t[j], &t->t[i]->t[k]); k 344 crypto/gf128mul.c int j, k; k 355 crypto/gf128mul.c for (k = 1; k < j; ++k) k 356 crypto/gf128mul.c be128_xor(&t->t[j + k], &t->t[j], &t->t[k]); k 366 crypto/gf128mul.c int j, k; k 377 crypto/gf128mul.c for (k = 1; k < j; ++k) k 378 crypto/gf128mul.c be128_xor(&t->t[j + k], &t->t[j], &t->t[k]); k 59 crypto/ghash-generic.c be128 k; k 69 crypto/ghash-generic.c BUILD_BUG_ON(sizeof(k) != GHASH_BLOCK_SIZE); k 70 crypto/ghash-generic.c memcpy(&k, key, GHASH_BLOCK_SIZE); /* avoid violating alignment rules */ k 71 crypto/ghash-generic.c ctx->gf128 = gf128mul_init_4k_lle(&k); k 72 crypto/ghash-generic.c memzero_explicit(&k, GHASH_BLOCK_SIZE); k 379 crypto/jitterentropy.c unsigned int k = 0; k 393 crypto/jitterentropy.c if (++k >= (DATA_SIZE_BITS * ec->osr)) k 63 crypto/md4.c #define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s)) k 64 crypto/md4.c #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (u32)0x5A827999,s)) k 65 crypto/md4.c #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (u32)0x6ED9EBA1,s)) k 40 crypto/rmd128.c #define ROUND(a, b, c, d, f, k, x, s) { \ k 41 crypto/rmd128.c (a) += f((b), (c), (d)) + le32_to_cpup(&(x)) + (k); \ k 43 crypto/rmd160.c #define ROUND(a, b, c, d, e, f, k, x, s) { \ k 44 crypto/rmd160.c (a) += f((b), (c), (d)) + le32_to_cpup(&(x)) + (k); \ k 40 crypto/rmd256.c #define ROUND(a, b, c, d, f, k, x, s) { \ k 41 crypto/rmd256.c (a) += f((b), (c), (d)) + le32_to_cpup(&(x)) + (k); \ k 43 crypto/rmd320.c #define ROUND(a, b, c, d, e, f, k, x, s) { \ k 44 crypto/rmd320.c (a) += f((b), (c), (d)) + le32_to_cpup(&(x)) + (k); \ k 30 crypto/serpent_generic.c ({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; }) k 33 crypto/serpent_generic.c ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; }) k 36 crypto/serpent_generic.c ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; }) k 42 crypto/serpent_generic.c x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \ k 43 crypto/serpent_generic.c x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \ k 53 crypto/serpent_generic.c x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \ k 54 crypto/serpent_generic.c x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\ k 55 crypto/serpent_generic.c x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \ k 59 crypto/serpent_generic.c x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \ k 60 crypto/serpent_generic.c x3 ^= k[4*i+3]; x0 = ror32(x0, 5); x2 = ror32(x2, 22);\ k 234 crypto/serpent_generic.c u32 r3, u32 r4, u32 *k) k 236 crypto/serpent_generic.c k += 100; k 251 crypto/serpent_generic.c k -= 50; k 263 crypto/serpent_generic.c k -= 50; k 277 crypto/serpent_generic.c u32 *k = ctx->expkey; k 278 crypto/serpent_generic.c u8 *k8 = (u8 *)k; k 293 crypto/serpent_generic.c r0 = le32_to_cpu(k[3]); k 294 crypto/serpent_generic.c r1 = le32_to_cpu(k[4]); k 295 crypto/serpent_generic.c r2 = le32_to_cpu(k[5]); k 296 crypto/serpent_generic.c r3 = le32_to_cpu(k[6]); k 297 crypto/serpent_generic.c r4 = le32_to_cpu(k[7]); k 299 crypto/serpent_generic.c keyiter(le32_to_cpu(k[0]), r0, r4, r2, 0, 0); k 300 crypto/serpent_generic.c keyiter(le32_to_cpu(k[1]), r1, r0, r3, 1, 1); k 301 crypto/serpent_generic.c keyiter(le32_to_cpu(k[2]), r2, r1, r4, 2, 2); k 302 crypto/serpent_generic.c keyiter(le32_to_cpu(k[3]), r3, r2, r0, 3, 3); k 303 crypto/serpent_generic.c keyiter(le32_to_cpu(k[4]), r4, r3, r1, 4, 4); k 304 crypto/serpent_generic.c keyiter(le32_to_cpu(k[5]), r0, r4, r2, 5, 5); k 305 crypto/serpent_generic.c keyiter(le32_to_cpu(k[6]), r1, r0, r3, 6, 6); k 306 crypto/serpent_generic.c keyiter(le32_to_cpu(k[7]), r2, r1, r4, 7, 7); k 308 crypto/serpent_generic.c keyiter(k[0], r3, r2, r0, 8, 8); k 309 crypto/serpent_generic.c keyiter(k[1], r4, r3, r1, 9, 9); k 310 crypto/serpent_generic.c keyiter(k[2], r0, r4, r2, 10, 10); k 311 crypto/serpent_generic.c keyiter(k[3], r1, r0, r3, 11, 11); k 312 crypto/serpent_generic.c keyiter(k[4], r2, r1, r4, 12, 12); k 313 crypto/serpent_generic.c keyiter(k[5], r3, r2, r0, 13, 13); k 314 crypto/serpent_generic.c keyiter(k[6], r4, r3, r1, 14, 14); k 315 crypto/serpent_generic.c keyiter(k[7], r0, r4, r2, 15, 15); k 316 crypto/serpent_generic.c keyiter(k[8], r1, r0, r3, 16, 16); k 317 crypto/serpent_generic.c keyiter(k[9], r2, r1, r4, 17, 17); k 318 crypto/serpent_generic.c keyiter(k[10], r3, r2, r0, 18, 18); k 319 crypto/serpent_generic.c keyiter(k[11], r4, r3, r1, 19, 19); k 320 crypto/serpent_generic.c keyiter(k[12], r0, r4, r2, 20, 20); k 321 crypto/serpent_generic.c keyiter(k[13], r1, r0, r3, 21, 21); k 322 crypto/serpent_generic.c keyiter(k[14], r2, r1, r4, 22, 22); k 323 crypto/serpent_generic.c keyiter(k[15], r3, r2, r0, 23, 23); k 324 crypto/serpent_generic.c keyiter(k[16], r4, r3, r1, 24, 24); k 325 crypto/serpent_generic.c keyiter(k[17], r0, r4, r2, 25, 25); k 326 crypto/serpent_generic.c keyiter(k[18], r1, r0, r3, 26, 26); k 327 crypto/serpent_generic.c keyiter(k[19], r2, r1, r4, 27, 27); k 328 crypto/serpent_generic.c keyiter(k[20], r3, r2, r0, 28, 28); k 329 crypto/serpent_generic.c keyiter(k[21], r4, r3, r1, 29, 29); k 330 crypto/serpent_generic.c keyiter(k[22], r0, r4, r2, 30, 30); k 331 crypto/serpent_generic.c keyiter(k[23], r1, r0, r3, 31, 31); k 333 crypto/serpent_generic.c k += 50; k 335 crypto/serpent_generic.c keyiter(k[-26], r2, r1, r4, 32, -18); k 336 crypto/serpent_generic.c keyiter(k[-25], r3, r2, r0, 33, -17); k 337 crypto/serpent_generic.c keyiter(k[-24], r4, r3, r1, 34, -16); k 338 crypto/serpent_generic.c keyiter(k[-23], r0, r4, r2, 35, -15); k 339 crypto/serpent_generic.c keyiter(k[-22], r1, r0, r3, 36, -14); k 340 crypto/serpent_generic.c keyiter(k[-21], r2, r1, r4, 37, -13); k 341 crypto/serpent_generic.c keyiter(k[-20], r3, r2, r0, 38, -12); k 342 crypto/serpent_generic.c keyiter(k[-19], r4, r3, r1, 39, -11); k 343 crypto/serpent_generic.c keyiter(k[-18], r0, r4, r2, 40, -10); k 344 crypto/serpent_generic.c keyiter(k[-17], r1, r0, r3, 41, -9); k 345 crypto/serpent_generic.c keyiter(k[-16], r2, r1, r4, 42, -8); k 346 crypto/serpent_generic.c keyiter(k[-15], r3, r2, r0, 43, -7); k 347 crypto/serpent_generic.c keyiter(k[-14], r4, r3, r1, 44, -6); k 348 crypto/serpent_generic.c keyiter(k[-13], r0, r4, r2, 45, -5); k 349 crypto/serpent_generic.c keyiter(k[-12], r1, r0, r3, 46, -4); k 350 crypto/serpent_generic.c keyiter(k[-11], r2, r1, r4, 47, -3); k 351 crypto/serpent_generic.c keyiter(k[-10], r3, r2, r0, 48, -2); k 352 crypto/serpent_generic.c keyiter(k[-9], r4, r3, r1, 49, -1); k 353 crypto/serpent_generic.c keyiter(k[-8], r0, r4, r2, 50, 0); k 354 crypto/serpent_generic.c keyiter(k[-7], r1, r0, r3, 51, 1); k 355 crypto/serpent_generic.c keyiter(k[-6], r2, r1, r4, 52, 2); k 356 crypto/serpent_generic.c keyiter(k[-5], r3, r2, r0, 53, 3); k 357 crypto/serpent_generic.c keyiter(k[-4], r4, r3, r1, 54, 4); k 358 crypto/serpent_generic.c keyiter(k[-3], r0, r4, r2, 55, 5); k 359 crypto/serpent_generic.c keyiter(k[-2], r1, r0, r3, 56, 6); k 360 crypto/serpent_generic.c keyiter(k[-1], r2, r1, r4, 57, 7); k 361 crypto/serpent_generic.c keyiter(k[0], r3, r2, r0, 58, 8); k 362 crypto/serpent_generic.c keyiter(k[1], r4, r3, r1, 59, 9); k 363 crypto/serpent_generic.c keyiter(k[2], r0, r4, r2, 60, 10); k 364 crypto/serpent_generic.c keyiter(k[3], r1, r0, r3, 61, 11); k 365 crypto/serpent_generic.c keyiter(k[4], r2, r1, r4, 62, 12); k 366 crypto/serpent_generic.c keyiter(k[5], r3, r2, r0, 63, 13); k 367 crypto/serpent_generic.c keyiter(k[6], r4, r3, r1, 64, 14); k 368 crypto/serpent_generic.c keyiter(k[7], r0, r4, r2, 65, 15); k 369 crypto/serpent_generic.c keyiter(k[8], r1, r0, r3, 66, 16); k 370 crypto/serpent_generic.c keyiter(k[9], r2, r1, r4, 67, 17); k 371 crypto/serpent_generic.c keyiter(k[10], r3, r2, r0, 68, 18); k 372 crypto/serpent_generic.c keyiter(k[11], r4, r3, r1, 69, 19); k 373 crypto/serpent_generic.c keyiter(k[12], r0, r4, r2, 70, 20); k 374 crypto/serpent_generic.c keyiter(k[13], r1, r0, r3, 71, 21); k 375 crypto/serpent_generic.c keyiter(k[14], r2, r1, r4, 72, 22); k 376 crypto/serpent_generic.c keyiter(k[15], r3, r2, r0, 73, 23); k 377 crypto/serpent_generic.c keyiter(k[16], r4, r3, r1, 74, 24); k 378 crypto/serpent_generic.c keyiter(k[17], r0, r4, r2, 75, 25); k 379 crypto/serpent_generic.c keyiter(k[18], r1, r0, r3, 76, 26); k 380 crypto/serpent_generic.c keyiter(k[19], r2, r1, r4, 77, 27); k 381 crypto/serpent_generic.c keyiter(k[20], r3, r2, r0, 78, 28); k 382 crypto/serpent_generic.c keyiter(k[21], r4, r3, r1, 79, 29); k 383 crypto/serpent_generic.c keyiter(k[22], r0, r4, r2, 80, 30); k 384 crypto/serpent_generic.c keyiter(k[23], r1, r0, r3, 81, 31); k 386 crypto/serpent_generic.c k += 50; k 388 crypto/serpent_generic.c keyiter(k[-26], r2, r1, r4, 82, -18); k 389 crypto/serpent_generic.c keyiter(k[-25], r3, r2, r0, 83, -17); k 390 crypto/serpent_generic.c keyiter(k[-24], r4, r3, r1, 84, -16); k 391 crypto/serpent_generic.c keyiter(k[-23], r0, r4, r2, 85, -15); k 392 crypto/serpent_generic.c keyiter(k[-22], r1, r0, r3, 86, -14); k 393 crypto/serpent_generic.c keyiter(k[-21], r2, r1, r4, 87, -13); k 394 crypto/serpent_generic.c keyiter(k[-20], r3, r2, r0, 88, -12); k 395 crypto/serpent_generic.c keyiter(k[-19], r4, r3, r1, 89, -11); k 396 crypto/serpent_generic.c keyiter(k[-18], r0, r4, r2, 90, -10); k 397 crypto/serpent_generic.c keyiter(k[-17], r1, r0, r3, 91, -9); k 398 crypto/serpent_generic.c keyiter(k[-16], r2, r1, r4, 92, -8); k 399 crypto/serpent_generic.c keyiter(k[-15], r3, r2, r0, 93, -7); k 400 crypto/serpent_generic.c keyiter(k[-14], r4, r3, r1, 94, -6); k 401 crypto/serpent_generic.c keyiter(k[-13], r0, r4, r2, 95, -5); k 402 crypto/serpent_generic.c keyiter(k[-12], r1, r0, r3, 96, -4); k 403 crypto/serpent_generic.c keyiter(k[-11], r2, r1, r4, 97, -3); k 404 crypto/serpent_generic.c keyiter(k[-10], r3, r2, r0, 98, -2); k 405 crypto/serpent_generic.c keyiter(k[-9], r4, r3, r1, 99, -1); k 406 crypto/serpent_generic.c keyiter(k[-8], r0, r4, r2, 100, 0); k 407 crypto/serpent_generic.c keyiter(k[-7], r1, r0, r3, 101, 1); k 408 crypto/serpent_generic.c keyiter(k[-6], r2, r1, r4, 102, 2); k 409 crypto/serpent_generic.c keyiter(k[-5], r3, r2, r0, 103, 3); k 410 crypto/serpent_generic.c keyiter(k[-4], r4, r3, r1, 104, 4); k 411 crypto/serpent_generic.c keyiter(k[-3], r0, r4, r2, 105, 5); k 412 crypto/serpent_generic.c keyiter(k[-2], r1, r0, r3, 106, 6); k 413 crypto/serpent_generic.c keyiter(k[-1], r2, r1, r4, 107, 7); k 414 crypto/serpent_generic.c keyiter(k[0], r3, r2, r0, 108, 8); k 415 crypto/serpent_generic.c keyiter(k[1], r4, r3, r1, 109, 9); k 416 crypto/serpent_generic.c keyiter(k[2], r0, r4, r2, 110, 10); k 417 crypto/serpent_generic.c keyiter(k[3], r1, r0, r3, 111, 11); k 418 crypto/serpent_generic.c keyiter(k[4], r2, r1, r4, 112, 12); k 419 crypto/serpent_generic.c keyiter(k[5], r3, r2, r0, 113, 13); k 420 crypto/serpent_generic.c keyiter(k[6], r4, r3, r1, 114, 14); k 421 crypto/serpent_generic.c keyiter(k[7], r0, r4, r2, 115, 15); k 422 crypto/serpent_generic.c keyiter(k[8], r1, r0, r3, 116, 16); k 423 crypto/serpent_generic.c keyiter(k[9], r2, r1, r4, 117, 17); k 424 crypto/serpent_generic.c keyiter(k[10], r3, r2, r0, 118, 18); k 425 crypto/serpent_generic.c keyiter(k[11], r4, r3, r1, 119, 19); k 426 crypto/serpent_generic.c keyiter(k[12], r0, r4, r2, 120, 20); k 427 crypto/serpent_generic.c keyiter(k[13], r1, r0, r3, 121, 21); k 428 crypto/serpent_generic.c keyiter(k[14], r2, r1, r4, 122, 22); k 429 crypto/serpent_generic.c keyiter(k[15], r3, r2, r0, 123, 23); k 430 crypto/serpent_generic.c keyiter(k[16], r4, r3, r1, 124, 24); k 431 crypto/serpent_generic.c keyiter(k[17], r0, r4, r2, 125, 25); k 432 crypto/serpent_generic.c keyiter(k[18], r1, r0, r3, 126, 26); k 433 crypto/serpent_generic.c keyiter(k[19], r2, r1, r4, 127, 27); k 434 crypto/serpent_generic.c keyiter(k[20], r3, r2, r0, 128, 28); k 435 crypto/serpent_generic.c keyiter(k[21], r4, r3, r1, 129, 29); k 436 crypto/serpent_generic.c keyiter(k[22], r0, r4, r2, 130, 30); k 437 crypto/serpent_generic.c keyiter(k[23], r1, r0, r3, 131, 31); k 454 crypto/serpent_generic.c const u32 *k = ctx->expkey; k 519 crypto/serpent_generic.c const u32 *k = ctx->expkey; k 117 crypto/tcrypt.c int k, rem; k 132 crypto/tcrypt.c for (k = 0; k < np; k++) k 133 crypto/tcrypt.c sg_set_buf(&sg[k + 1], xbuf[k], PAGE_SIZE); k 136 crypto/tcrypt.c sg_set_buf(&sg[k + 1], xbuf[k], rem); k 816 crypto/tcrypt.c unsigned int i, j, k; k 870 crypto/tcrypt.c for (k = 0; k < num_mb; k++) k 871 crypto/tcrypt.c ahash_request_set_crypt(data[k].req, data[k].sg, k 872 crypto/tcrypt.c data[k].result, speed[i].blen); k 895 crypto/tcrypt.c for (k = 0; k < num_mb; ++k) k 896 crypto/tcrypt.c ahash_request_free(data[k].req); k 898 crypto/tcrypt.c for (k = 0; k < num_mb; ++k) k 899 crypto/tcrypt.c testmgr_free_buf(data[k].xbuf); k 1355 crypto/tcrypt.c unsigned int k = *b_size; k 1356 crypto/tcrypt.c unsigned int pages = DIV_ROUND_UP(k, PAGE_SIZE); k 1361 crypto/tcrypt.c while (k > PAGE_SIZE) { k 1366 crypto/tcrypt.c k -= PAGE_SIZE; k 1369 crypto/tcrypt.c sg_set_buf(cur->sg + p, cur->xbuf[p], k); k 1370 crypto/tcrypt.c memset(cur->xbuf[p], 0xff, k); k 1493 crypto/tcrypt.c unsigned int ret, i, j, k, iv_len; k 1567 crypto/tcrypt.c k = *keysize + *b_size; k 1568 crypto/tcrypt.c sg_init_table(sg, DIV_ROUND_UP(k, PAGE_SIZE)); k 1570 crypto/tcrypt.c if (k > PAGE_SIZE) { k 1573 crypto/tcrypt.c k -= PAGE_SIZE; k 1575 crypto/tcrypt.c while (k > PAGE_SIZE) { k 1579 crypto/tcrypt.c k -= PAGE_SIZE; k 1581 crypto/tcrypt.c sg_set_buf(sg + j, tvmem[j], k); k 1582 crypto/tcrypt.c memset(tvmem[j], 0xff, k); k 2355 crypto/testmgr.c unsigned int i, j, k; k 2409 crypto/testmgr.c for (k = 0; k < template[i].len; k 2410 crypto/testmgr.c k += crypto_cipher_blocksize(tfm)) { k 2412 crypto/testmgr.c crypto_cipher_encrypt_one(tfm, data + k, k 2413 crypto/testmgr.c data + k); k 2415 crypto/testmgr.c crypto_cipher_decrypt_one(tfm, data + k, k 2416 crypto/testmgr.c data + k); k 535 crypto/twofish_common.c #define CALC_K(a, j, k, l, m, n) \ k 536 crypto/twofish_common.c x = CALC_K_2 (k, l, k, l, 0); \ k 548 crypto/twofish_common.c #define CALC_K192(a, j, k, l, m, n) \ k 549 crypto/twofish_common.c x = CALC_K192_2 (l, l, k, k, 0); \ k 561 crypto/twofish_common.c #define CALC_K256(a, j, k, l, m, n) \ k 562 crypto/twofish_common.c x = CALC_K256_2 (k, l, 0); \ k 572 crypto/twofish_common.c int i, j, k; k 637 crypto/twofish_common.c for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) { k 638 crypto/twofish_common.c CALC_SB256_2( i, calc_sb_tbl[j], calc_sb_tbl[k] ); k 655 crypto/twofish_common.c CALC_K256 (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]); k 659 crypto/twofish_common.c for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) { k 660 crypto/twofish_common.c CALC_SB192_2( i, calc_sb_tbl[j], calc_sb_tbl[k] ); k 668 crypto/twofish_common.c CALC_K192 (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]); k 672 crypto/twofish_common.c for ( i = j = 0, k = 1; i < 256; i++, j += 2, k += 2 ) { k 673 crypto/twofish_common.c CALC_SB_2( i, calc_sb_tbl[j], calc_sb_tbl[k] ); k 681 crypto/twofish_common.c CALC_K (k, i, q0[i+8], q1[i+8], q0[i+9], q1[i+9]); k 55 crypto/twofish_generic.c x += y; y += x + ctx->k[2 * (n) + 1]; \ k 56 crypto/twofish_generic.c (c) ^= x + ctx->k[2 * (n)]; \ k 63 crypto/twofish_generic.c (d) ^= y + ctx->k[2 * (n) + 1]; \ k 66 crypto/twofish_generic.c (c) ^= (x + ctx->k[2 * (n)]) k 265 drivers/acpi/acpica/exconvrt.c u32 k = 0; k 316 drivers/acpi/acpica/exconvrt.c string[k] = (u8) (ACPI_ASCII_ZERO + remainder); k 317 drivers/acpi/acpica/exconvrt.c k++; k 331 drivers/acpi/acpica/exconvrt.c string[k] = (u8) k 333 drivers/acpi/acpica/exconvrt.c k++; k 347 drivers/acpi/acpica/exconvrt.c if (!k) { k 349 drivers/acpi/acpica/exconvrt.c k = 1; k 352 drivers/acpi/acpica/exconvrt.c string[k] = 0; k 353 drivers/acpi/acpica/exconvrt.c return ((u32) k); k 32 drivers/acpi/acpica/utownerid.c u32 k; k 63 drivers/acpi/acpica/utownerid.c for (k = acpi_gbl_next_owner_id_offset; k < 32; k++) { k 77 drivers/acpi/acpica/utownerid.c if (!(acpi_gbl_owner_id_mask[j] & ((u32)1 << k))) { k 83 drivers/acpi/acpica/utownerid.c acpi_gbl_owner_id_mask[j] |= ((u32)1 << k); k 86 drivers/acpi/acpica/utownerid.c acpi_gbl_next_owner_id_offset = (u8)(k + 1); k 95 drivers/acpi/acpica/utownerid.c (acpi_owner_id)((k + 1) + ACPI_MUL_32(j)); k 57 drivers/acpi/device_sysfs.c #define to_data_node(k) container_of(k, struct acpi_data_node, kobj) k 105 drivers/acpi/x86/apple.c unsigned int k = 1 + numvalid + j * 2; /* index into newprops */ k 106 drivers/acpi/x86/apple.c unsigned int v = k + 1; k 110 drivers/acpi/x86/apple.c newprops[1 + j].package.elements = &newprops[k]; k 112 drivers/acpi/x86/apple.c newprops[k].type = ACPI_TYPE_STRING; k 113 drivers/acpi/x86/apple.c newprops[k].string.length = key->string.length; k 114 drivers/acpi/x86/apple.c newprops[k].string.pointer = free_space; k 314 drivers/ata/sata_highbank.c u32 tmp, k = 0; k 321 drivers/ata/sata_highbank.c } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); k 3261 drivers/atm/idt77252.c int i, k; k 3380 drivers/atm/idt77252.c for (k = 0, i = 1; k < card->vcibits; k++) { k 260 drivers/auxdisplay/cfag12864b.c unsigned short i, j, k, b; k 271 drivers/auxdisplay/cfag12864b.c for (k = 0; k < CFAG12864B_ADDRESSES; k++) { k 275 drivers/auxdisplay/cfag12864b.c + k / 8 + (j * 8 + b) * k 277 drivers/auxdisplay/cfag12864b.c & bit(k % 8)) k 743 drivers/base/bus.c struct kobject *k = kset_find_obj(bus_kset, name); k 744 drivers/base/bus.c return k ? to_bus(k) : NULL; k 1788 drivers/base/core.c struct kobject *k; k 1815 drivers/base/core.c list_for_each_entry(k, &dev->class->p->glue_dirs.list, entry) k 1816 drivers/base/core.c if (k->parent == parent_kobj) { k 1817 drivers/base/core.c kobj = kobject_get(k); k 1827 drivers/base/core.c k = class_dir_create_and_add(dev->class, parent_kobj); k 1830 drivers/base/core.c return k; k 215 drivers/base/driver.c struct kobject *k = kset_find_obj(bus->p->drivers_kset, name); k 218 drivers/base/driver.c if (k) { k 220 drivers/base/driver.c kobject_put(k); k 221 drivers/base/driver.c priv = to_driver(k); k 1559 drivers/base/platform.c int k, n, i; k 1563 drivers/base/platform.c k = early_platform_driver_probe_id(class_str, i, nr_probe - n); k 1565 drivers/base/platform.c if (k < 0) k 1568 drivers/base/platform.c n += k; k 55 drivers/base/swnode.c struct kobject *k; k 62 drivers/base/swnode.c list_for_each_entry(k, &swnode_kset->list, entry) { k 63 drivers/base/swnode.c swnode = kobj_to_swnode(k); k 640 drivers/base/swnode.c struct kobject *k; k 647 drivers/base/swnode.c list_for_each_entry(k, &swnode_kset->list, entry) { k 648 drivers/base/swnode.c swnode = kobj_to_swnode(k); k 282 drivers/bcma/scan.c u8 i, j, k; k 376 drivers/bcma/scan.c k = 0; k 386 drivers/bcma/scan.c } else if (k < ARRAY_SIZE(core->addr_s)) { k 387 drivers/bcma/scan.c core->addr_s[k] = tmp; k 388 drivers/bcma/scan.c k++; k 231 drivers/block/aoe/aoe.h int aoe_ktstart(struct ktstate *k); k 232 drivers/block/aoe/aoe.h void aoe_ktstop(struct ktstate *k); k 1229 drivers/block/aoe/aoecmd.c struct ktstate *k; k 1233 drivers/block/aoe/aoecmd.c k = vp; k 1236 drivers/block/aoe/aoecmd.c complete(&k->rendez); /* tell spawner we're running */ k 1238 drivers/block/aoe/aoecmd.c spin_lock_irq(k->lock); k 1239 drivers/block/aoe/aoecmd.c more = k->fn(k->id); k 1241 drivers/block/aoe/aoecmd.c add_wait_queue(k->waitq, &wait); k 1244 drivers/block/aoe/aoecmd.c spin_unlock_irq(k->lock); k 1247 drivers/block/aoe/aoecmd.c remove_wait_queue(k->waitq, &wait); k 1251 drivers/block/aoe/aoecmd.c complete(&k->rendez); /* tell spawner we're stopping */ k 1256 drivers/block/aoe/aoecmd.c aoe_ktstop(struct ktstate *k) k 1258 drivers/block/aoe/aoecmd.c kthread_stop(k->task); k 1259 drivers/block/aoe/aoecmd.c wait_for_completion(&k->rendez); k 1263 drivers/block/aoe/aoecmd.c aoe_ktstart(struct ktstate *k) k 1267 drivers/block/aoe/aoecmd.c init_completion(&k->rendez); k 1268 drivers/block/aoe/aoecmd.c task = kthread_run(kthread, k, "%s", k->name); k 1271 drivers/block/aoe/aoecmd.c k->task = task; k 1272 drivers/block/aoe/aoecmd.c wait_for_completion(&k->rendez); /* allow kthread to start */ k 1273 drivers/block/aoe/aoecmd.c init_completion(&k->rendez); /* for waiting for exit later */ k 72 drivers/block/paride/aten.c { int k, a, b, c, d; k 77 drivers/block/paride/aten.c for (k=0;k<count/2;k++) { k 81 drivers/block/paride/aten.c buf[2*k] = j44(c,d); k 82 drivers/block/paride/aten.c buf[2*k+1] = j44(a,b); k 88 drivers/block/paride/aten.c for (k=0;k<count/2;k++) { k 91 drivers/block/paride/aten.c buf[2*k] = b; buf[2*k+1] = a; k 100 drivers/block/paride/aten.c { int k; k 103 drivers/block/paride/aten.c for (k=0;k<count/2;k++) { k 104 drivers/block/paride/aten.c w0(buf[2*k+1]); w2(0xe); w2(6); k 105 drivers/block/paride/aten.c w0(buf[2*k]); w2(7); w2(6); k 350 drivers/block/paride/bpck.c { int i, j, k, p, v, f, om, od; k 364 drivers/block/paride/bpck.c for (k=0;k<9;k++) { k 373 drivers/block/paride/bpck.c for (k=0;k<8;k++) { k 151 drivers/block/paride/comm.c { int k; k 157 drivers/block/paride/comm.c for (k=0;k<count;k++) { k 158 drivers/block/paride/comm.c w2(5); w0(buf[k^1]); w2(7); k 164 drivers/block/paride/comm.c for (k=0;k<count;k++) w4(buf[k^1]); k 168 drivers/block/paride/comm.c for (k=0;k<count/2;k++) w4w(pi_swab16(buf,k)); k 172 drivers/block/paride/comm.c for (k=0;k<count/4;k++) w4l(pi_swab32(buf,k)); k 117 drivers/block/paride/dstr.c { int k, a, b; k 125 drivers/block/paride/dstr.c case 0: for (k=0;k<count;k++) { k 128 drivers/block/paride/dstr.c buf[k] = j44(a,b); k 133 drivers/block/paride/dstr.c for (k=0;k<count;k++) { k 134 drivers/block/paride/dstr.c w2(0x26); buf[k] = r0(); w2(0x24); k 140 drivers/block/paride/dstr.c for (k=0;k<count;k++) buf[k] = r4(); k 145 drivers/block/paride/dstr.c for (k=0;k<count/2;k++) ((u16 *)buf)[k] = r4w(); k 150 drivers/block/paride/dstr.c for (k=0;k<count/4;k++) ((u32 *)buf)[k] = r4l(); k 159 drivers/block/paride/dstr.c { int k; k 168 drivers/block/paride/dstr.c case 1: for (k=0;k<count;k++) { k 169 drivers/block/paride/dstr.c w2(5); w0(buf[k]); w2(7); k 175 drivers/block/paride/dstr.c for (k=0;k<count;k++) w4(buf[k]); k 180 drivers/block/paride/dstr.c for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]); k 185 drivers/block/paride/dstr.c for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]); k 99 drivers/block/paride/epat.c { int k, ph, a, b; k 105 drivers/block/paride/epat.c for(k=0;k<count;k++) { k 106 drivers/block/paride/epat.c if (k == count-1) w0(0xfd); k 110 drivers/block/paride/epat.c buf[k] = j44(a,b); k 118 drivers/block/paride/epat.c for(k=0;k<count;k++) { k 119 drivers/block/paride/epat.c if (k == count-1) w0(0xfd); k 122 drivers/block/paride/epat.c buf[k] = j53(a,b); k 130 drivers/block/paride/epat.c for(k=0;k<count-1;k++) { k 132 drivers/block/paride/epat.c buf[k] = r0(); k 140 drivers/block/paride/epat.c for(k=0;k<count-1;k++) buf[k] = r4(); k 146 drivers/block/paride/epat.c for(k=0;k<(count/2)-1;k++) ((u16 *)buf)[k] = r4w(); k 153 drivers/block/paride/epat.c for(k=0;k<(count/4)-1;k++) ((u32 *)buf)[k] = r4l(); k 154 drivers/block/paride/epat.c for(k=count-4;k<count-1;k++) buf[k] = r4(); k 164 drivers/block/paride/epat.c { int ph, k; k 172 drivers/block/paride/epat.c for(k=0;k<count;k++) { k 173 drivers/block/paride/epat.c w0(buf[k]); k 181 drivers/block/paride/epat.c for(k=0;k<count;k++) w4(buf[k]); k 186 drivers/block/paride/epat.c for(k=0;k<(count/2);k++) w4w(((u16 *)buf)[k]); k 191 drivers/block/paride/epat.c for(k=0;k<(count/4);k++) w4l(((u32 *)buf)[k]); k 253 drivers/block/paride/epat.c { int k, j, f, cc; k 263 drivers/block/paride/epat.c for (k=0;k<256;k++) { k 264 drivers/block/paride/epat.c WRi(2,k^0xaa); k 265 drivers/block/paride/epat.c WRi(3,k^0x55); k 266 drivers/block/paride/epat.c if (RRi(2) != (k^0xaa)) e[j]++; k 276 drivers/block/paride/epat.c for (k=0;k<256;k++) { k 277 drivers/block/paride/epat.c if ((scratch[2*k] & 0xff) != k) f++; k 278 drivers/block/paride/epat.c if ((scratch[2*k+1] & 0xff) != (0xff-k)) f++; k 138 drivers/block/paride/epia.c { int k, ph, a, b; k 144 drivers/block/paride/epia.c for (k=0;k<count;k++) { k 147 drivers/block/paride/epia.c buf[k] = j44(a,b); k 156 drivers/block/paride/epia.c for (k=0;k<count;k++) { k 159 drivers/block/paride/epia.c buf[k] = j53(a,b); k 167 drivers/block/paride/epia.c for (k=0;k<count;k++) { k 169 drivers/block/paride/epia.c buf[k] = r0(); k 177 drivers/block/paride/epia.c for (k=0;k<count;k++) buf[k] = r4(); k 183 drivers/block/paride/epia.c for (k=0;k<count/2;k++) ((u16 *)buf)[k] = r4w(); k 189 drivers/block/paride/epia.c for (k=0;k<count/4;k++) ((u32 *)buf)[k] = r4l(); k 198 drivers/block/paride/epia.c { int ph, k, last, d; k 206 drivers/block/paride/epia.c for (k=0;k<count;k++) { k 207 drivers/block/paride/epia.c d = buf[k]; k 217 drivers/block/paride/epia.c for (k=0;k<count;k++) w4(buf[k]); k 223 drivers/block/paride/epia.c for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]); k 229 drivers/block/paride/epia.c for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]); k 239 drivers/block/paride/epia.c { int j, k, f; k 245 drivers/block/paride/epia.c for (k=0;k<256;k++) { k 246 drivers/block/paride/epia.c WR(2,k^0xaa); k 247 drivers/block/paride/epia.c WR(3,k^0x55); k 248 drivers/block/paride/epia.c if (RR(2) != (k^0xaa)) e[j]++; k 258 drivers/block/paride/epia.c for (k=0;k<256;k++) { k 259 drivers/block/paride/epia.c if ((scratch[2*k] & 0xff) != ((k+1) & 0xff)) f++; k 260 drivers/block/paride/epia.c if ((scratch[2*k+1] & 0xff) != ((-2-k) & 0xff)) f++; k 66 drivers/block/paride/fit2.c { int k, a, b, c, d; k 70 drivers/block/paride/fit2.c for (k=0;k<count/4;k++) { k 75 drivers/block/paride/fit2.c buf[4*k+0] = j44(a,b); k 76 drivers/block/paride/fit2.c buf[4*k+1] = j44(d,c); k 81 drivers/block/paride/fit2.c buf[4*k+2] = j44(d,c); k 82 drivers/block/paride/fit2.c buf[4*k+3] = j44(a,b); k 92 drivers/block/paride/fit2.c { int k; k 96 drivers/block/paride/fit2.c for (k=0;k<count/2;k++) { k 97 drivers/block/paride/fit2.c w2(4); w0(buf[2*k]); k 98 drivers/block/paride/fit2.c w2(5); w0(buf[2*k+1]); k 97 drivers/block/paride/fit3.c { int k, a, b, c, d; k 102 drivers/block/paride/fit3.c for (k=0;k<count/2;k++) { k 107 drivers/block/paride/fit3.c buf[2*k ] = j44(a,b); k 108 drivers/block/paride/fit3.c buf[2*k+1] = j44(c,d); k 115 drivers/block/paride/fit3.c for (k=0;k<count/2;k++) { k 118 drivers/block/paride/fit3.c buf[2*k ] = a; k 119 drivers/block/paride/fit3.c buf[2*k+1] = b; k 127 drivers/block/paride/fit3.c for (k=0;k<count;k++) buf[k] = r4(); k 136 drivers/block/paride/fit3.c { int k; k 142 drivers/block/paride/fit3.c for (k=0;k<count/2;k++) { k 143 drivers/block/paride/fit3.c w0(buf[2*k ]); w2(0xd); k 144 drivers/block/paride/fit3.c w0(buf[2*k+1]); w2(0xc); k 149 drivers/block/paride/fit3.c for (k=0;k<count;k++) w4(buf[k]); k 79 drivers/block/paride/friq.c { int h, l, k, ph; k 84 drivers/block/paride/friq.c for (k=0;k<count;k++) { k 87 drivers/block/paride/friq.c buf[k] = j44(l,h); k 95 drivers/block/paride/friq.c for (k=0;k<count;k++) { k 97 drivers/block/paride/friq.c buf[k] = r0(); k 104 drivers/block/paride/friq.c for (k=0;k<count-2;k++) buf[k] = r4(); k 112 drivers/block/paride/friq.c for (k=0;k<(count/2)-1;k++) ((u16 *)buf)[k] = r4w(); k 120 drivers/block/paride/friq.c for (k=0;k<(count/4)-1;k++) ((u32 *)buf)[k] = r4l(); k 139 drivers/block/paride/friq.c { int k; k 145 drivers/block/paride/friq.c for (k=0;k<count;k++) { k 146 drivers/block/paride/friq.c w0(buf[k]); k 153 drivers/block/paride/friq.c for (k=0;k<count;k++) w4(buf[k]); k 158 drivers/block/paride/friq.c for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]); k 163 drivers/block/paride/friq.c for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]); k 185 drivers/block/paride/friq.c { int j, k, r; k 196 drivers/block/paride/friq.c for (k=0;k<256;k++) { k 197 drivers/block/paride/friq.c friq_write_regr(pi,0,2,k^0xaa); k 198 drivers/block/paride/friq.c friq_write_regr(pi,0,3,k^0x55); k 199 drivers/block/paride/friq.c if (friq_read_regr(pi,0,2) != (k^0xaa)) e[j]++; k 207 drivers/block/paride/friq.c for (k=0;k<128;k++) if (scratch[k] != k) r++; k 76 drivers/block/paride/frpw.c { int h, l, k, ph; k 81 drivers/block/paride/frpw.c for (k=0;k<count;k++) { k 84 drivers/block/paride/frpw.c buf[k] = j44(l,h); k 92 drivers/block/paride/frpw.c for (k=0;k<count;k++) { k 94 drivers/block/paride/frpw.c buf[k] = r0(); k 101 drivers/block/paride/frpw.c for (k=0;k<count;k++) buf[k] = r4(); k 107 drivers/block/paride/frpw.c for (k=0;k<count-2;k++) buf[k] = r4(); k 115 drivers/block/paride/frpw.c for (k=0;k<(count/2)-1;k++) ((u16 *)buf)[k] = r4w(); k 123 drivers/block/paride/frpw.c for (k=0;k<(count/4)-1;k++) ((u32 *)buf)[k] = r4l(); k 142 drivers/block/paride/frpw.c { int k; k 149 drivers/block/paride/frpw.c for (k=0;k<count;k++) { k 150 drivers/block/paride/frpw.c w0(buf[k]); k 157 drivers/block/paride/frpw.c for (k=0;k<count;k++) w4(buf[k]); k 162 drivers/block/paride/frpw.c for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]); k 167 drivers/block/paride/frpw.c for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]); k 226 drivers/block/paride/frpw.c { int j, k, r; k 249 drivers/block/paride/frpw.c for (k=0;k<256;k++) { k 250 drivers/block/paride/frpw.c frpw_write_regr(pi,0,2,k^0xaa); k 251 drivers/block/paride/frpw.c frpw_write_regr(pi,0,3,k^0x55); k 252 drivers/block/paride/frpw.c if (frpw_read_regr(pi,0,2) != (k^0xaa)) e[j]++; k 260 drivers/block/paride/frpw.c for (k=0;k<128;k++) if (scratch[k] != k) r++; k 136 drivers/block/paride/kbic.c { int k, a, b; k 141 drivers/block/paride/kbic.c for (k=0;k<count/2;k++) { k 144 drivers/block/paride/kbic.c buf[2*k] = j44(a,b); k 147 drivers/block/paride/kbic.c buf[2*k+1] = j44(a,b); k 153 drivers/block/paride/kbic.c for (k=0;k<count/4;k++) { k 156 drivers/block/paride/kbic.c w0(8); buf[4*k] = j53(r12w()); k 157 drivers/block/paride/kbic.c w0(0xb8); buf[4*k+1] = j53(r12w()); k 159 drivers/block/paride/kbic.c buf[4*k+3] = j53(r12w()); k 160 drivers/block/paride/kbic.c w0(8); buf[4*k+2] = j53(r12w()); k 166 drivers/block/paride/kbic.c for (k=0;k<count/2;k++) { k 167 drivers/block/paride/kbic.c w2(0xa0); w2(0xa1); buf[2*k] = r0(); k 168 drivers/block/paride/kbic.c w2(0xa5); buf[2*k+1] = r0(); k 174 drivers/block/paride/kbic.c for (k=0;k<count;k++) buf[k] = r4(); k 179 drivers/block/paride/kbic.c for (k=0;k<count/2;k++) ((u16 *)buf)[k] = r4w(); k 184 drivers/block/paride/kbic.c for (k=0;k<count/4;k++) ((u32 *)buf)[k] = r4l(); k 194 drivers/block/paride/kbic.c { int k; k 201 drivers/block/paride/kbic.c for(k=0;k<count/2;k++) { k 202 drivers/block/paride/kbic.c w0(buf[2*k+1]); w2(0); w2(4); k 203 drivers/block/paride/kbic.c w0(buf[2*k]); w2(5); w2(4); k 208 drivers/block/paride/kbic.c for(k=0;k<count/2;k++) { k 209 drivers/block/paride/kbic.c w4(buf[2*k+1]); k 210 drivers/block/paride/kbic.c w4(buf[2*k]); k 216 drivers/block/paride/kbic.c for(k=0;k<count/2;k++) w4w(pi_swab16(buf,k)); k 221 drivers/block/paride/kbic.c for(k=0;k<count/4;k++) w4l(pi_swab32(buf,k)); k 56 drivers/block/paride/ktti.c { int k, a, b; k 58 drivers/block/paride/ktti.c for (k=0;k<count/2;k++) { k 61 drivers/block/paride/ktti.c buf[2*k] = j44(a,b); k 63 drivers/block/paride/ktti.c buf[2*k+1] = j44(a,b); k 69 drivers/block/paride/ktti.c { int k; k 71 drivers/block/paride/ktti.c for (k=0;k<count/2;k++) { k 73 drivers/block/paride/ktti.c w0(buf[2*k]); w2(3); k 74 drivers/block/paride/ktti.c w0(buf[2*k+1]); w2(6); k 89 drivers/block/paride/on20.c { int k, l, h; k 93 drivers/block/paride/on20.c for (k=0;k<count;k++) k 95 drivers/block/paride/on20.c w2(4); w2(0x26); buf[k] = r0(); k 99 drivers/block/paride/on20.c buf[k] = j44(l,h); k 106 drivers/block/paride/on20.c { int k; k 110 drivers/block/paride/on20.c for (k=0;k<count;k++) { w2(5); w0(buf[k]); w2(7); } k 188 drivers/block/paride/on26.c { int k, a, b; k 194 drivers/block/paride/on26.c for (k=0;k<count;k++) { k 197 drivers/block/paride/on26.c buf[k] = j44(a,b); k 204 drivers/block/paride/on26.c for (k=0;k<count/2;k++) { k 205 drivers/block/paride/on26.c w2(0x26); buf[2*k] = r0(); k 206 drivers/block/paride/on26.c w2(0x24); buf[2*k+1] = r0(); k 214 drivers/block/paride/on26.c for (k=0;k<count;k++) buf[k] = r4(); k 221 drivers/block/paride/on26.c for (k=0;k<count/2;k++) ((u16 *)buf)[k] = r4w(); k 228 drivers/block/paride/on26.c for (k=0;k<count/4;k++) ((u32 *)buf)[k] = r4l(); k 237 drivers/block/paride/on26.c { int k; k 245 drivers/block/paride/on26.c for (k=0;k<count/2;k++) { k 246 drivers/block/paride/on26.c w2(5); w0(buf[2*k]); k 247 drivers/block/paride/on26.c w2(7); w0(buf[2*k+1]); k 256 drivers/block/paride/on26.c for (k=0;k<count;k++) w4(buf[k]); k 263 drivers/block/paride/on26.c for (k=0;k<count/2;k++) w4w(((u16 *)buf)[k]); k 270 drivers/block/paride/on26.c for (k=0;k<count/4;k++) w4l(((u32 *)buf)[k]); k 172 drivers/block/paride/paride.c int j, k; k 179 drivers/block/paride/paride.c for (k = 0; k < 256; k++) { k 180 drivers/block/paride/paride.c pi_write_regr(pi, 0, 2, k ^ 0xaa); k 181 drivers/block/paride/paride.c pi_write_regr(pi, 0, 3, k ^ 0x55); k 182 drivers/block/paride/paride.c if (pi_read_regr(pi, 0, 2) != (k ^ 0xaa)) k 212 drivers/block/paride/paride.c int k; k 214 drivers/block/paride/paride.c for (k = 0; k < MAX_PROTOS; k++) k 215 drivers/block/paride/paride.c if (protocols[k] && !strcmp(pr->name, protocols[k]->name)) { k 220 drivers/block/paride/paride.c k = 0; k 221 drivers/block/paride/paride.c while ((k < MAX_PROTOS) && (protocols[k])) k 222 drivers/block/paride/paride.c k++; k 223 drivers/block/paride/paride.c if (k == MAX_PROTOS) { k 227 drivers/block/paride/paride.c protocols[k] = pr; k 228 drivers/block/paride/paride.c pr->index = k; k 229 drivers/block/paride/paride.c printk("paride: %s registered as protocol %d\n", pr->name, k); k 354 drivers/block/paride/paride.c int p, k, s, e; k 407 drivers/block/paride/paride.c k = 0; k 408 drivers/block/paride/paride.c while ((pi->port = lpts[k++])) k 118 drivers/block/paride/paride.h static inline u16 pi_swab16( char *b, int k) k 122 drivers/block/paride/paride.h r.t[0]=b[2*k+1]; r.t[1]=b[2*k]; k 126 drivers/block/paride/paride.h static inline u32 pi_swab32( char *b, int k) k 130 drivers/block/paride/paride.h r.f[0]=b[4*k+1]; r.f[1]=b[4*k]; k 131 drivers/block/paride/paride.h r.f[2]=b[4*k+3]; r.f[3]=b[4*k+2]; k 434 drivers/block/paride/pcd.c int r, d, p, n, k, j; k 437 drivers/block/paride/pcd.c k = 0; k 459 drivers/block/paride/pcd.c cd->name, fun, p, d, k); k 466 drivers/block/paride/pcd.c if (k++ > PCD_TMO) { k 564 drivers/block/paride/pcd.c int i, k, flg; k 573 drivers/block/paride/pcd.c k = 0; k 574 drivers/block/paride/pcd.c while ((k++ < PCD_RESET_TMO) && (status_reg(cd) & IDE_BUSY)) k 582 drivers/block/paride/pcd.c printk("%s: Reset (%d) signature = ", cd->name, k); k 602 drivers/block/paride/pcd.c int k, p; k 604 drivers/block/paride/pcd.c k = 0; k 605 drivers/block/paride/pcd.c while (k < tmo) { k 613 drivers/block/paride/pcd.c k++; k 633 drivers/block/paride/pcd.c int k, s; k 650 drivers/block/paride/pcd.c k = 16; k 651 drivers/block/paride/pcd.c while ((k >= 0) && (id[k] <= 0x20)) { k 652 drivers/block/paride/pcd.c id[k] = 0; k 653 drivers/block/paride/pcd.c k--; k 711 drivers/block/paride/pcd.c int k, unit; k 723 drivers/block/paride/pcd.c k = 0; k 730 drivers/block/paride/pcd.c k++; k 747 drivers/block/paride/pcd.c k++; k 752 drivers/block/paride/pcd.c if (k) k 309 drivers/block/paride/pd.c int k, r, e; k 311 drivers/block/paride/pd.c k = 0; k 312 drivers/block/paride/pd.c while (k < PD_SPIN) { k 314 drivers/block/paride/pd.c k++; k 320 drivers/block/paride/pd.c if (k >= PD_SPIN) k 561 drivers/block/paride/pf.c int i, k, flg; k 570 drivers/block/paride/pf.c k = 0; k 571 drivers/block/paride/pf.c while ((k++ < PF_RESET_TMO) && (status_reg(pf) & STAT_BUSY)) k 579 drivers/block/paride/pf.c printk("%s: Reset (%d) signature = ", pf->name, k); k 605 drivers/block/paride/pf.c int j, k, l; k 609 drivers/block/paride/pf.c for (k = 0; k < len; k++) k 610 drivers/block/paride/pf.c if ((buf[k + offs] != 0x20) || (buf[k + offs] != l)) k 611 drivers/block/paride/pf.c l = targ[j++] = buf[k + offs]; k 619 drivers/block/paride/pf.c int v, k; k 622 drivers/block/paride/pf.c for (k = 0; k < 4; k++) k 623 drivers/block/paride/pf.c v = v * 256 + (buf[k + offs] & 0xff); k 725 drivers/block/paride/pf.c int k, unit; k 735 drivers/block/paride/pf.c k = 0; k 741 drivers/block/paride/pf.c k++; k 756 drivers/block/paride/pf.c k++; k 761 drivers/block/paride/pf.c if (k) k 322 drivers/block/paride/pg.c int k; k 347 drivers/block/paride/pg.c for (k = 0; k < 12; k++) k 348 drivers/block/paride/pg.c printk("%02x ", cmd[k] & 0xff); k 390 drivers/block/paride/pg.c int i, k, err; k 400 drivers/block/paride/pg.c k = 0; k 401 drivers/block/paride/pg.c while ((k++ < PG_RESET_TMO) && (status_reg(dev) & STAT_BUSY)) k 410 drivers/block/paride/pg.c printk("%s: Reset (%d) signature = ", dev->name, k); k 425 drivers/block/paride/pg.c int k; k 427 drivers/block/paride/pg.c for (k = 0; k < len; k++) { k 481 drivers/block/paride/pg.c int k, unit; k 491 drivers/block/paride/pg.c k = 0; k 497 drivers/block/paride/pg.c k++; k 512 drivers/block/paride/pg.c k++; k 518 drivers/block/paride/pg.c if (k) k 124 drivers/block/paride/ppc6lnx.c u8 i, j, k; k 176 drivers/block/paride/ppc6lnx.c k = inb(ppc->lpt_addr + 1) & 0xB8; k 178 drivers/block/paride/ppc6lnx.c if (j == k) k 184 drivers/block/paride/ppc6lnx.c k = (inb(ppc->lpt_addr + 1) & 0xB8) ^ 0xB8; k 186 drivers/block/paride/ppc6lnx.c if (j == k) k 397 drivers/block/paride/pt.c int k, e, s; k 399 drivers/block/paride/pt.c k = 0; k 402 drivers/block/paride/pt.c while (k < tmo) { k 404 drivers/block/paride/pt.c k++; k 413 drivers/block/paride/pt.c if ((k >= tmo) || (s & STAT_ERR)) { k 414 drivers/block/paride/pt.c if (k >= tmo) k 454 drivers/block/paride/pt.c int i, k, flg; k 463 drivers/block/paride/pt.c k = 0; k 464 drivers/block/paride/pt.c while ((k++ < PT_RESET_TMO) && (status_reg(pi) & STAT_BUSY)) k 472 drivers/block/paride/pt.c printk("%s: Reset (%d) signature = ", tape->name, k); k 487 drivers/block/paride/pt.c int k, p; k 489 drivers/block/paride/pt.c k = 0; k 490 drivers/block/paride/pt.c while (k < tmo) { k 498 drivers/block/paride/pt.c k++; k 506 drivers/block/paride/pt.c int j, k, l; k 510 drivers/block/paride/pt.c for (k = 0; k < len; k++) k 511 drivers/block/paride/pt.c if ((buf[k + offs] != 0x20) || (buf[k + offs] != l)) k 512 drivers/block/paride/pt.c l = targ[j++] = buf[k + offs]; k 520 drivers/block/paride/pt.c int v, k; k 523 drivers/block/paride/pt.c for (k = 0; k < size; k++) k 524 drivers/block/paride/pt.c v = v * 256 + (buf[k + offs] & 0xff); k 770 drivers/block/paride/pt.c int k, n, r, p, s, t, b; k 836 drivers/block/paride/pt.c k = n; k 837 drivers/block/paride/pt.c if (k > PT_BUFSIZE) k 838 drivers/block/paride/pt.c k = PT_BUFSIZE; k 839 drivers/block/paride/pt.c pi_read_block(pi, tape->bufptr, k); k 840 drivers/block/paride/pt.c n -= k; k 841 drivers/block/paride/pt.c b = k; k 867 drivers/block/paride/pt.c int k, n, r, p, s, t, b; k 937 drivers/block/paride/pt.c k = n; k 938 drivers/block/paride/pt.c if (k > PT_BUFSIZE) k 939 drivers/block/paride/pt.c k = PT_BUFSIZE; k 940 drivers/block/paride/pt.c b = k; k 947 drivers/block/paride/pt.c pi_write_block(pi, tape->bufptr, k); k 950 drivers/block/paride/pt.c n -= k; k 61 drivers/bus/omap_l3_noc.c int k; k 124 drivers/bus/omap_l3_noc.c for (k = 0, master = l3->l3_masters; k < l3->num_masters; k 125 drivers/bus/omap_l3_noc.c k++, master++) { k 332 drivers/char/agp/hp-agp.c int i, k; k 364 drivers/char/agp/hp-agp.c for (k = 0; k 365 drivers/char/agp/hp-agp.c k < hp->io_pages_per_kpage; k 366 drivers/char/agp/hp-agp.c k++, j++, paddr += hp->io_page_size) { k 297 drivers/char/agp/i460-agp.c int i, j, k, num_entries; k 329 drivers/char/agp/i460-agp.c for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size) k 124 drivers/char/agp/parisc-agp.c int i, k; k 155 drivers/char/agp/parisc-agp.c for (k = 0; k 156 drivers/char/agp/parisc-agp.c k < info->io_pages_per_kpage; k 157 drivers/char/agp/parisc-agp.c k++, j++, paddr += info->io_page_size) { k 159 drivers/char/hpet.c unsigned long m, t, mc, base, k; k 182 drivers/char/hpet.c k = (mc - base + hpetp->hp_delta) / t; k 183 drivers/char/hpet.c write_counter(t * (k + 1) + base, k 927 drivers/char/pcmcia/cm4000_cs.c int i, j, k; k 989 drivers/char/pcmcia/cm4000_cs.c k = dev->rpos; k 990 drivers/char/pcmcia/cm4000_cs.c if (k + j > 255) k 991 drivers/char/pcmcia/cm4000_cs.c j = 256 - k; k 994 drivers/char/pcmcia/cm4000_cs.c xoutb(k++, REG_BUF_ADDR(iobase)); k 998 drivers/char/pcmcia/cm4000_cs.c if (k + j > 255) { k 1003 drivers/char/pcmcia/cm4000_cs.c xoutb(k++, REG_BUF_ADDR(iobase)); k 643 drivers/clk/berlin/bg2.c int k; k 645 drivers/clk/berlin/bg2.c for (k = 0; k < dd->num_parents; k++) k 646 drivers/clk/berlin/bg2.c parent_names[k] = clk_names[dd->parent_ids[k]]; k 336 drivers/clk/berlin/bg2q.c int k; k 338 drivers/clk/berlin/bg2q.c for (k = 0; k < dd->num_parents; k++) k 339 drivers/clk/berlin/bg2q.c parent_names[k] = clk_names[dd->parent_ids[k]]; k 31 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 99 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 114 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 127 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 153 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 202 drivers/clk/sunxi-ng/ccu-sun4i-a10.c .k = _SUNXI_CCU_MULT(4, 2), k 30 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .k = _SUNXI_CCU_MULT(4, 2), k 110 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), k 124 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), k 177 drivers/clk/sunxi-ng/ccu-sun50i-a64.c .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), k 29 drivers/clk/sunxi-ng/ccu-sun5i.c .k = _SUNXI_CCU_MULT(4, 2), k 101 drivers/clk/sunxi-ng/ccu-sun5i.c .k = _SUNXI_CCU_MULT(4, 2), k 116 drivers/clk/sunxi-ng/ccu-sun5i.c .k = _SUNXI_CCU_MULT(4, 2), k 143 drivers/clk/sunxi-ng/ccu-sun5i.c .k = _SUNXI_CCU_MULT(4, 2), k 32 drivers/clk/sunxi-ng/ccu-sun8i-a23.c .k = _SUNXI_CCU_MULT(4, 2), k 30 drivers/clk/sunxi-ng/ccu-sun8i-a33.c .k = _SUNXI_CCU_MULT(4, 2), k 31 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .k = _SUNXI_CCU_MULT(4, 2), k 103 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .k = _SUNXI_CCU_MULT(4, 2), k 137 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .k = _SUNXI_CCU_MULT(4, 2), k 166 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .k = _SUNXI_CCU_MULT(4, 2), k 216 drivers/clk/sunxi-ng/ccu-sun8i-r40.c .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), k 31 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .k = _SUNXI_CCU_MULT(4, 2), k 98 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c .k = _SUNXI_CCU_MULT(4, 2), k 15 drivers/clk/sunxi-ng/ccu_nk.c unsigned long k, min_k, max_k; k 40 drivers/clk/sunxi-ng/ccu_nk.c nk->k = best_k; k 69 drivers/clk/sunxi-ng/ccu_nk.c unsigned long rate, n, k; k 80 drivers/clk/sunxi-ng/ccu_nk.c k = reg >> nk->k.shift; k 81 drivers/clk/sunxi-ng/ccu_nk.c k &= (1 << nk->k.width) - 1; k 82 drivers/clk/sunxi-ng/ccu_nk.c k += nk->k.offset; k 83 drivers/clk/sunxi-ng/ccu_nk.c if (!k) k 84 drivers/clk/sunxi-ng/ccu_nk.c k++; k 86 drivers/clk/sunxi-ng/ccu_nk.c rate = parent_rate * n * k; k 104 drivers/clk/sunxi-ng/ccu_nk.c _nk.min_k = nk->k.min ?: 1; k 105 drivers/clk/sunxi-ng/ccu_nk.c _nk.max_k = nk->k.max ?: 1 << nk->k.width; k 108 drivers/clk/sunxi-ng/ccu_nk.c rate = *parent_rate * _nk.n * _nk.k; k 129 drivers/clk/sunxi-ng/ccu_nk.c _nk.min_k = nk->k.min ?: 1; k 130 drivers/clk/sunxi-ng/ccu_nk.c _nk.max_k = nk->k.max ?: 1 << nk->k.width; k 138 drivers/clk/sunxi-ng/ccu_nk.c reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift); k 140 drivers/clk/sunxi-ng/ccu_nk.c reg |= (_nk.k - nk->k.offset) << nk->k.shift; k 26 drivers/clk/sunxi-ng/ccu_nk.h struct ccu_mult_internal k; k 41 drivers/clk/sunxi-ng/ccu_nk.h .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \ k 15 drivers/clk/sunxi-ng/ccu_nkm.c unsigned long k, min_k, max_k; k 46 drivers/clk/sunxi-ng/ccu_nkm.c nkm->k = best_k; k 75 drivers/clk/sunxi-ng/ccu_nkm.c unsigned long n, m, k, rate; k 86 drivers/clk/sunxi-ng/ccu_nkm.c k = reg >> nkm->k.shift; k 87 drivers/clk/sunxi-ng/ccu_nkm.c k &= (1 << nkm->k.width) - 1; k 88 drivers/clk/sunxi-ng/ccu_nkm.c k += nkm->k.offset; k 89 drivers/clk/sunxi-ng/ccu_nkm.c if (!k) k 90 drivers/clk/sunxi-ng/ccu_nkm.c k++; k 98 drivers/clk/sunxi-ng/ccu_nkm.c rate = parent_rate * n * k / m; k 117 drivers/clk/sunxi-ng/ccu_nkm.c _nkm.min_k = nkm->k.min ?: 1; k 118 drivers/clk/sunxi-ng/ccu_nkm.c _nkm.max_k = nkm->k.max ?: 1 << nkm->k.width; k 127 drivers/clk/sunxi-ng/ccu_nkm.c rate = *parent_rate * _nkm.n * _nkm.k / _nkm.m; k 157 drivers/clk/sunxi-ng/ccu_nkm.c _nkm.min_k = nkm->k.min ?: 1; k 158 drivers/clk/sunxi-ng/ccu_nkm.c _nkm.max_k = nkm->k.max ?: 1 << nkm->k.width; k 168 drivers/clk/sunxi-ng/ccu_nkm.c reg &= ~GENMASK(nkm->k.width + nkm->k.shift - 1, nkm->k.shift); k 172 drivers/clk/sunxi-ng/ccu_nkm.c reg |= (_nkm.k - nkm->k.offset) << nkm->k.shift; k 25 drivers/clk/sunxi-ng/ccu_nkm.h struct ccu_mult_internal k; k 43 drivers/clk/sunxi-ng/ccu_nkm.h .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \ k 64 drivers/clk/sunxi-ng/ccu_nkm.h .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \ k 15 drivers/clk/sunxi-ng/ccu_nkmp.c unsigned long k, min_k, max_k; k 21 drivers/clk/sunxi-ng/ccu_nkmp.c unsigned long n, unsigned long k, k 26 drivers/clk/sunxi-ng/ccu_nkmp.c rate *= n * k; k 65 drivers/clk/sunxi-ng/ccu_nkmp.c nkmp->k = best_k; k 95 drivers/clk/sunxi-ng/ccu_nkmp.c unsigned long n, m, k, p, rate; k 106 drivers/clk/sunxi-ng/ccu_nkmp.c k = reg >> nkmp->k.shift; k 107 drivers/clk/sunxi-ng/ccu_nkmp.c k &= (1 << nkmp->k.width) - 1; k 108 drivers/clk/sunxi-ng/ccu_nkmp.c k += nkmp->k.offset; k 109 drivers/clk/sunxi-ng/ccu_nkmp.c if (!k) k 110 drivers/clk/sunxi-ng/ccu_nkmp.c k++; k 121 drivers/clk/sunxi-ng/ccu_nkmp.c rate = ccu_nkmp_calc_rate(parent_rate, n, k, m, 1 << p); k 146 drivers/clk/sunxi-ng/ccu_nkmp.c _nkmp.min_k = nkmp->k.min ?: 1; k 147 drivers/clk/sunxi-ng/ccu_nkmp.c _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; k 155 drivers/clk/sunxi-ng/ccu_nkmp.c rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k, k 177 drivers/clk/sunxi-ng/ccu_nkmp.c _nkmp.min_k = nkmp->k.min ?: 1; k 178 drivers/clk/sunxi-ng/ccu_nkmp.c _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; k 195 drivers/clk/sunxi-ng/ccu_nkmp.c if (nkmp->k.width) k 196 drivers/clk/sunxi-ng/ccu_nkmp.c k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, k 197 drivers/clk/sunxi-ng/ccu_nkmp.c nkmp->k.shift); k 211 drivers/clk/sunxi-ng/ccu_nkmp.c reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask; k 25 drivers/clk/sunxi-ng/ccu_nkmp.h struct ccu_mult_internal k; k 45 drivers/clk/sunxi-ng/ccu_nkmp.h .k = _SUNXI_CCU_MULT(_kshift, _kwidth), \ k 43 drivers/clk/sunxi/clk-factors.c u8 n = 1, k = 0, p = 0, m = 0; k 56 drivers/clk/sunxi/clk-factors.c k = FACTOR_GET(config->kshift, config->kwidth, reg); k 66 drivers/clk/sunxi/clk-factors.c .k = k, k 83 drivers/clk/sunxi/clk-factors.c rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1); k 154 drivers/clk/sunxi/clk-factors.c reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k); k 27 drivers/clk/sunxi/clk-factors.h u8 k; k 47 drivers/clk/sunxi/clk-sunxi.c req->k = 1; k 49 drivers/clk/sunxi/clk-sunxi.c req->k = 0; k 70 drivers/clk/sunxi/clk-sunxi.c div /= (req->k + 1); k 105 drivers/clk/sunxi/clk-sunxi.c req->k = 3; k 108 drivers/clk/sunxi/clk-sunxi.c req->k = 2; k 111 drivers/clk/sunxi/clk-sunxi.c req->k = 1; k 114 drivers/clk/sunxi/clk-sunxi.c req->k = 0; k 137 drivers/clk/sunxi/clk-sunxi.c req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz) k 171 drivers/clk/sunxi/clk-sunxi.c req->k = 1; k 173 drivers/clk/sunxi/clk-sunxi.c req->k = 0; k 190 drivers/clk/sunxi/clk-sunxi.c div /= (req->k + 1); k 210 drivers/clk/sunxi/clk-sunxi.c req->k = 0; k 212 drivers/clk/sunxi/clk-sunxi.c req->k = 1; k 214 drivers/clk/sunxi/clk-sunxi.c req->k = 2; k 216 drivers/clk/sunxi/clk-sunxi.c req->k = 3; k 218 drivers/clk/sunxi/clk-sunxi.c req->n = DIV_ROUND_UP(div, (req->k + 1)); k 236 drivers/clk/sunxi/clk-sunxi.c req->k = div / 32; k 237 drivers/clk/sunxi/clk-sunxi.c if (req->k > 3) k 238 drivers/clk/sunxi/clk-sunxi.c req->k = 3; k 240 drivers/clk/sunxi/clk-sunxi.c req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; k 117 drivers/clk/tegra/clk-emc.c int i, k, t; k 121 drivers/clk/tegra/clk-emc.c for (k = 0; k < tegra->num_timings; k++) { k 122 drivers/clk/tegra/clk-emc.c if (tegra->timings[k].ram_code == ram_code) k 126 drivers/clk/tegra/clk-emc.c for (t = k; t < tegra->num_timings; t++) { k 131 drivers/clk/tegra/clk-emc.c for (i = k; i < t; i++) { k 138 drivers/clk/tegra/clk-emc.c i = max(i, k + 1); k 316 drivers/clocksource/sh_cmt.c int k, ret; k 357 drivers/clocksource/sh_cmt.c for (k = 0; k < 100; k++) { k 277 drivers/cpufreq/arm_big_little.c int i, j, k = 0, count = 1; k 293 drivers/cpufreq/arm_big_little.c table[k].frequency = VIRT_FREQ(i, k 295 drivers/cpufreq/arm_big_little.c pr_debug("%s: index: %d, freq: %d\n", __func__, k, k 296 drivers/cpufreq/arm_big_little.c table[k].frequency); k 297 drivers/cpufreq/arm_big_little.c k++; k 301 drivers/cpufreq/arm_big_little.c table[k].driver_data = k; k 302 drivers/cpufreq/arm_big_little.c table[k].frequency = CPUFREQ_TABLE_END; k 304 drivers/cpufreq/arm_big_little.c pr_debug("%s: End, table: %p, count: %d\n", __func__, table, k); k 927 drivers/cpufreq/cpufreq.c #define to_policy(k) container_of(k, struct cpufreq_policy, kobj) k 185 drivers/cpufreq/e_powersaver.c int k, step, voltage; k 346 drivers/cpufreq/e_powersaver.c k = 0; k 350 drivers/cpufreq/e_powersaver.c voltage = (k * step) / 256 + min_voltage; k 351 drivers/cpufreq/e_powersaver.c f_table[k].frequency = fsb * i; k 352 drivers/cpufreq/e_powersaver.c f_table[k].driver_data = (i << 8) | voltage; k 353 drivers/cpufreq/e_powersaver.c k++; k 355 drivers/cpufreq/e_powersaver.c f_table[k].frequency = CPUFREQ_TABLE_END; k 426 drivers/cpufreq/longhaul.c unsigned int i, j, k = 0; k 488 drivers/cpufreq/longhaul.c longhaul_table[k].frequency = calc_speed(ratio); k 489 drivers/cpufreq/longhaul.c longhaul_table[k].driver_data = j; k 490 drivers/cpufreq/longhaul.c k++; k 492 drivers/cpufreq/longhaul.c if (k <= 1) { k 497 drivers/cpufreq/longhaul.c for (j = 0; j < k - 1; j++) { k 501 drivers/cpufreq/longhaul.c for (i = j + 1; i < k; i++) { k 515 drivers/cpufreq/longhaul.c longhaul_table[k].frequency = CPUFREQ_TABLE_END; k 518 drivers/cpufreq/longhaul.c for (j = 0; j < k; j++) { k 506 drivers/cpufreq/powernow-k7.c unsigned int k; k 508 drivers/cpufreq/powernow-k7.c for (k = 0; k < number_scales; k++) k 392 drivers/cpuidle/sysfs.c #define kobj_to_state_obj(k) container_of(k, struct cpuidle_state_kobj, kobj) k 393 drivers/cpuidle/sysfs.c #define kobj_to_state(k) (kobj_to_state_obj(k)->state) k 394 drivers/cpuidle/sysfs.c #define kobj_to_state_usage(k) (kobj_to_state_obj(k)->state_usage) k 395 drivers/cpuidle/sysfs.c #define kobj_to_device(k) (kobj_to_state_obj(k)->device) k 513 drivers/cpuidle/sysfs.c #define kobj_to_driver_kobj(k) container_of(k, struct cpuidle_driver_kobj, kobj) k 239 drivers/crypto/chelsio/chcr_algo.c int i, j, k; k 277 drivers/crypto/chelsio/chcr_algo.c for (k = 0, j = i % nk; k < nk; k++) { k 278 drivers/crypto/chelsio/chcr_algo.c *((u32 *)dec_key + k) = htonl(w_ring[j]); k 804 drivers/crypto/n2_core.c int i, j, k; k 808 drivers/crypto/n2_core.c j = k = 0; k 815 drivers/crypto/n2_core.c j = (j + key[k] + a) & 0xff; k 818 drivers/crypto/n2_core.c if (++k >= keylen) k 819 drivers/crypto/n2_core.c k = 0; k 261 drivers/crypto/rockchip/rk3288_crypto.c unsigned int i, k; k 278 drivers/crypto/rockchip/rk3288_crypto.c for (k = 0; k < i; k++) { k 280 drivers/crypto/rockchip/rk3288_crypto.c crypto_unregister_alg(&rk_cipher_algs[k]->alg.crypto); k 1318 drivers/crypto/sahara.c unsigned int i, j, k, l; k 1326 drivers/crypto/sahara.c for (k = 0; k < ARRAY_SIZE(sha_v3_algs); k++) { k 1327 drivers/crypto/sahara.c err = crypto_register_ahash(&sha_v3_algs[k]); k 1346 drivers/crypto/sahara.c for (j = 0; j < k; j++) k 1584 drivers/crypto/stm32/stm32-cryp.c unsigned int i = 0, j, k; k 1633 drivers/crypto/stm32/stm32-cryp.c for (k = 0; k < sizeof(u32); k++) { k 1634 drivers/crypto/stm32/stm32-cryp.c d8[k] = *((u8 *)src); k 151 drivers/dma-buf/dma-resv.c unsigned int i, j, k, max; k 177 drivers/dma-buf/dma-resv.c for (i = 0, j = 0, k = max; i < (old ? old->shared_count : 0); ++i) { k 183 drivers/dma-buf/dma-resv.c RCU_INIT_POINTER(new->shared[--k], fence); k 203 drivers/dma-buf/dma-resv.c for (i = k; i < max; ++i) { k 1312 drivers/dma/ipu/ipu_idmac.c int j, k; k 1319 drivers/dma/ipu/ipu_idmac.c for_each_sg(desc->sg, sg, desc->sg_len, k) { k 3365 drivers/dma/ppc4xx/adma.c int k = 0, op = 0, lop = 0; k 3370 drivers/dma/ppc4xx/adma.c if (k == XOR_MAX_OPS) { k 3371 drivers/dma/ppc4xx/adma.c k = 0; k 3377 drivers/dma/ppc4xx/adma.c if ((xcb->ops[k++].h & (DMA_RXOR12 << DMA_CUED_REGION_OFF)) == k 3384 drivers/dma/ppc4xx/adma.c BUG_ON(k < 1); k 3386 drivers/dma/ppc4xx/adma.c if (test_bit(k-1, desc->reverse_flags)) { k 3389 drivers/dma/ppc4xx/adma.c ppc440spe_rxor_set_src(desc, k - 1, addr); k 3393 drivers/dma/ppc4xx/adma.c ppc440spe_rxor_set_src(desc, k - 1, addr); k 3406 drivers/dma/ppc4xx/adma.c int k = 0, op = 0, lop = 0; k 3411 drivers/dma/ppc4xx/adma.c if (k == XOR_MAX_OPS) { k 3412 drivers/dma/ppc4xx/adma.c k = 0; k 3419 drivers/dma/ppc4xx/adma.c if ((xcb->ops[k++].h & (DMA_RXOR12 << DMA_CUED_REGION_OFF)) == k 3426 drivers/dma/ppc4xx/adma.c BUG_ON(k < 1); k 3427 drivers/dma/ppc4xx/adma.c if (test_bit(k-1, desc->reverse_flags)) { k 3429 drivers/dma/ppc4xx/adma.c ppc440spe_rxor_set_mult(desc, k - 1, op - index - 1, mult); k 3432 drivers/dma/ppc4xx/adma.c ppc440spe_rxor_set_mult(desc, k - 1, index - lop, mult); k 610 drivers/dma/sa11x0-dma.c unsigned i, j, k, sglen, sgperiod; k 632 drivers/dma/sa11x0-dma.c for (i = k = 0; i < size / period; i++) { k 635 drivers/dma/sa11x0-dma.c for (j = 0; j < sgperiod; j++, k++) { k 643 drivers/dma/sa11x0-dma.c txd->sg[k].addr = addr; k 644 drivers/dma/sa11x0-dma.c txd->sg[k].len = tlen; k 652 drivers/dma/sa11x0-dma.c WARN_ON(k != sglen); k 1598 drivers/dma/ti/edma.c int k = (j << 5) + i; k 1605 drivers/dma/ti/edma.c edma_error_handler(&ecc->slave_chans[k]); k 499 drivers/edac/amd64_edac.h #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 23 drivers/edac/edac_device_sysfs.c #define to_edacdev(k) container_of(k, struct edac_device_ctl_info, kobj) k 113 drivers/edac/edac_device_sysfs.c #define to_ctl_info(k) container_of(k, struct edac_device_ctl_info, kobj) k 320 drivers/edac/edac_device_sysfs.c #define to_instance(k) container_of(k, struct edac_device_instance, kobj) k 406 drivers/edac/edac_device_sysfs.c #define to_block(k) container_of(k, struct edac_device_block, kobj) k 96 drivers/edac/edac_mc.h #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 123 drivers/edac/edac_mc_sysfs.c #define to_csrow(k) container_of(k, struct csrow_info, dev) k 141 drivers/edac/edac_mc_sysfs.c #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) k 471 drivers/edac/edac_mc_sysfs.c #define to_dimm(k) container_of(k, struct dimm_info, dev) k 668 drivers/edac/edac_mc_sysfs.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 70 drivers/edac/edac_pci_sysfs.c #define to_instance(k) container_of(k, struct edac_pci_ctl_info, kobj) k 210 drivers/edac/edac_pci_sysfs.c #define to_edacpci(k) container_of(k, struct edac_pci_ctl_info, kobj) k 57 drivers/edac/fsl_ddr_edac.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 97 drivers/edac/highbank_mc_edac.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 834 drivers/edac/i5100_edac.c int k; k 840 drivers/edac/i5100_edac.c for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) k 841 drivers/edac/i5100_edac.c priv->dmir[i][j].rank[k] = k 842 drivers/edac/i5100_edac.c i5100_dmir_rank(dw, k); k 944 drivers/edac/i5100_edac.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 652 drivers/edac/i7core_edac.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 26 drivers/edac/octeon_edac-lmc.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 1757 drivers/edac/sb_edac.c int i, j, k, n_sads, n_tads, sad_interl; k 1898 drivers/edac/sb_edac.c for (k = 0; k < rir_way; k++) { k 1900 drivers/edac/sb_edac.c rir_offset[j][k], k 1906 drivers/edac/sb_edac.c i, j, k, k 910 drivers/edac/synopsys_edac.c #define to_mci(k) container_of(k, struct mem_ctl_info, dev) k 93 drivers/firewire/core-card.c int i, j, k, length; k 135 drivers/firewire/core-card.c for (k = 0; k < desc->length; k++) k 136 drivers/firewire/core-card.c config_rom[i + k] = cpu_to_be32(desc->data[k]); k 518 drivers/firmware/efi/libstub/efi-stub-helper.c int i, j, k; k 671 drivers/firmware/efi/libstub/efi-stub-helper.c for (k = j; k < i; k++) k 672 drivers/firmware/efi/libstub/efi-stub-helper.c efi_file_close(files[k].handle); k 299 drivers/firmware/qemu_fw_cfg.c static ssize_t fw_cfg_showrev(struct kobject *k, struct attribute *a, char *buf) k 306 drivers/firmware/qemu_fw_cfg.c ssize_t (*show)(struct kobject *k, struct attribute *a, char *buf); k 564 drivers/firmware/qemu_fw_cfg.c struct kobject *k, *next; k 566 drivers/firmware/qemu_fw_cfg.c list_for_each_entry_safe(k, next, &kset->list, entry) k 568 drivers/firmware/qemu_fw_cfg.c if (k->ktype == kset->kobj.ktype) k 569 drivers/firmware/qemu_fw_cfg.c fw_cfg_kset_unregister_recursive(to_kset(k)); k 223 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c unsigned int i, j, k; k 240 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) { k 249 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c RCU_INIT_POINTER(new->shared[k++], f); k 252 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c new->shared_count = k; k 262 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c for (i = j, k = 0; i < old->shared_count; ++i) { k 303 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c int i, j, k, path_size, device_support; k 373 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { k 374 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); k 378 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); k 401 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c for (k = 0; k < router_obj->ucNumberOfObjects; k++) { k 402 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); k 406 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); k 414 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); k 77 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c unsigned i, j, k; k 167 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c for (k = 0; k < adev->vcn.num_enc_rings; ++k) k 168 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k]; k 269 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c int i, j, k; k 309 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c for (k = 0; k < num_base_address; k++) { k 314 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ip->base_address[k] = le32_to_cpu(ip->base_address[k]); k 315 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); k 109 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c unsigned i, j, k; k 123 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c for (k = 0; k < src->num_types; ++k) { k 124 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c atomic_set(&src->enabled_types[k], 0); k 125 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c r = src->funcs->set(adev, src, k, k 463 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c int i, j, k; k 474 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c for (k = 0; k < src->num_types; k++) k 475 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c amdgpu_irq_update(adev, src, k); k 1305 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c int i, j, k, r, ring_id = 0; k 1379 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { k 1380 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) k 1384 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c i, k, j); k 1396 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { k 1397 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, k 1402 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c i, k, j); k 1653 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c int i, j, k; k 1694 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c for (k = 0; k < max_wgp_per_sh; k++) { k 1695 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c if (!(wgp_active_bitmap & (1 << k))) { k 1696 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gcrd_targets_disable_tcp |= 3 << (2 * k); k 1697 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c utcl_invreq_disable |= (3 << (2 * k)) | k 1698 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (3 << (2 * (max_wgp_per_sh + k))); k 5437 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c int i, j, k, counter, active_cu_number = 0; k 5459 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { k 1545 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c int i, j, k; k 1557 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (k = 0; k < 16; k++) { k 1558 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c mask <<= k; k 3575 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c int i, j, k, counter, active_cu_number = 0; k 3603 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { k 3366 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c u32 i, j, k; k 3373 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (k = 0; k < adev->usec_timeout; k++) { k 3387 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (k = 0; k < adev->usec_timeout; k++) { k 4433 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c int i, j, k, r, ring_id; k 4502 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { k 4503 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) k 4508 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c i, k, j); k 5108 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c int i, j, k, counter, active_cu_number = 0; k 5136 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { k 1953 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c int i, j, k, r, ring_id; k 2055 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { k 2056 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) k 2061 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c i, k, j); k 3869 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c u32 i, j, k; k 3876 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (k = 0; k < adev->usec_timeout; k++) { k 3881 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c if (k == adev->usec_timeout) { k 3898 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (k = 0; k < adev->usec_timeout; k++) { k 7130 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c int i, j, k, counter, active_cu_number = 0; k 7158 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { k 1493 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t i, j, k; k 1511 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { k 2193 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c int i, j, k, r, ring_id; k 2286 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { k 2287 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) k 2292 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c i, k, j); k 2548 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u32 i, j, k; k 2555 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < adev->usec_timeout; k++) { k 2560 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (k == adev->usec_timeout) { k 2577 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < adev->usec_timeout; k++) { k 4268 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c int r, i, j, k; k 4382 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < sec_ded_counter_registers[i].instance; k++) { k 4383 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_v9_0_select_se_sh(adev, j, 0x0, k); k 6453 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c int i, j, k, counter, active_cu_number = 0; k 6496 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { k 2706 drivers/gpu/drm/amd/amdgpu/kv_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 2753 drivers/gpu/drm/amd/amdgpu/kv_dpm.c k = 0; k 2759 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) k 2765 drivers/gpu/drm/amd/amdgpu/kv_dpm.c &adev->pm.dpm.ps[i], k, k 2767 drivers/gpu/drm/amd/amdgpu/kv_dpm.c k++; k 1934 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 k = dte_data->k; k 1943 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < k; i++) { k 2581 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (dte_data->k <= 0) k 2590 drivers/gpu/drm/amd/amdgpu/si_dpm.c table_size = dte_data->k; k 3360 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 k, a, ah, al; k 3366 drivers/gpu/drm/amd/amdgpu/si_dpm.c k = (100 * fh) / fl; k 3367 drivers/gpu/drm/amd/amdgpu/si_dpm.c t1 = (t * (k - 100)); k 5819 drivers/gpu/drm/amd/amdgpu/si_dpm.c u8 i, j, k; k 5830 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (k = 0; k < table->num_entries; k++) k 5831 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5833 drivers/gpu/drm/amd/amdgpu/si_dpm.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 5841 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (k = 0; k < table->num_entries; k++) { k 5842 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5844 drivers/gpu/drm/amd/amdgpu/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 5846 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 5855 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (k = 0; k < table->num_entries; k++) k 5856 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5857 drivers/gpu/drm/amd/amdgpu/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 5865 drivers/gpu/drm/amd/amdgpu/si_dpm.c for(k = 0; k < table->num_entries; k++) k 5866 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5868 drivers/gpu/drm/amd/amdgpu/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 7218 drivers/gpu/drm/amd/amdgpu/si_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 7268 drivers/gpu/drm/amd/amdgpu/si_dpm.c k = 0; k 7274 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) k 7280 drivers/gpu/drm/amd/amdgpu/si_dpm.c &adev->pm.dpm.ps[i], k, k 7282 drivers/gpu/drm/amd/amdgpu/si_dpm.c k++; k 891 drivers/gpu/drm/amd/amdgpu/si_dpm.h u32 k; k 936 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c int i, j, k, r; k 938 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { k 939 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << k)) k 942 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, k 952 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { k 953 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c if (adev->uvd.harvest_config & (1 << k)) k 955 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring; k 957 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, k 961 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, k 965 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), k 971 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, k 983 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, k 996 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); k 997 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); k 999 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); k 1000 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); k 1001 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); k 1002 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); k 1003 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); k 1004 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); k 1007 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, k 1012 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, k 1016 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, k 1020 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); k 1027 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c status = RREG32_SOC15(UVD, k, mmUVD_STATUS); k 1036 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); k 1037 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), k 1041 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, k 1048 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); k 1052 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), k 1057 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, k 1068 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); k 1071 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); k 1074 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, k 1078 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, k 1080 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, k 1084 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); k 1086 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); k 1087 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, k 1090 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, k 1093 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring_enc[0]; k 1094 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); k 1095 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); k 1096 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); k 1097 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); k 1098 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); k 1100 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring = &adev->uvd.inst[k].ring_enc[1]; k 1101 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); k 1102 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); k 1103 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); k 1104 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); k 1105 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); k 715 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c int i, j, k, r; k 801 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c for (k = 0; k < 10; ++k) { k 619 drivers/gpu/drm/amd/amdkfd/kfd_crat.c int i, j, k; k 699 drivers/gpu/drm/amd/amdkfd/kfd_crat.c for (k = 0; k < cu_info->num_cu_per_sh; k 700 drivers/gpu/drm/amd/amdkfd/kfd_crat.c k += pcache_info[ct].num_cu_shared) { k 709 drivers/gpu/drm/amd/amdkfd/kfd_crat.c k); k 186 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h int i, j, k; k 538 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h for (k = 0; k < 8; k++) { k 541 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k])); k 543 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h i, j, k, k 544 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k])); k 100 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c int32_t i, j, k; k 1196 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= 7; k++) { k 1202 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_add(bw_mul((bw_add(data->total_dmifmc_urgent_latency, data->dmif_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->dmif_buffer_transfer_time[i]), data->active_time[i])); k 1249 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))))); k 1252 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->line_source_transfer_time[i][j][k] = bw_max2(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), bw_sub(bw_mul((bw_add(vbios->mcifwrmc_urgent_latency, data->mcifwr_burst_time[j][k])), bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])); k 1258 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))); k 1279 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1280 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k]) { k 1283 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->display_pstate_change_enable[k] = 0; k 1319 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1320 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0))) { k 1321 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) { k 1322 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->line_source_transfer_time[k][i][j])); k 1323 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->active_time[k])))); k 1327 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) { k 1328 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, bw_sub(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k])); k 1332 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->blackout_duration_margin[i][j] = bw_min2(data->blackout_duration_margin[i][j], bw_sub(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->line_source_transfer_time[k][i][j])); k 1333 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_blackout_duration[i][j] = bw_max3(data->dispclk_required_for_blackout_duration[i][j], bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->minimum_latency_hiding_with_cursor[k], vbios->blackout_duration), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k])))); k 1337 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j])))))) { k 1338 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_blackout_recovery[i][j] = bw_max2(data->dispclk_required_for_blackout_recovery[i][j], bw_div(bw_mul(bw_div(bw_div((bw_sub(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, vbios->maximum_blackout_recovery_time))), data->adjusted_data_buffer_size[k])), bw_int_to_fixed(data->bytes_per_pixel[k])), (bw_sub(vbios->maximum_blackout_recovery_time, (bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[i][j]))))), data->latency_hiding_lines[k]), data->lines_interleaved_in_mem_access[k])); k 1383 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1384 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k]) { k 1385 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) { k 1386 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]); k 1391 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->active_time[k])))); k 1393 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->display_pstate_change_enable[k] = 1; k 1400 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_margin = bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->mcifwr_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]); k 1405 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dispclk_required_for_dram_speed_change_pipe[i][j] = bw_max2(bw_div(bw_div(bw_mul(data->src_pixels_for_first_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]))), bw_div(bw_div(bw_mul(data->src_pixels_for_last_output_pixel[k], dceip->display_pipe_throughput_factor), dceip->lb_write_pixels_per_dispclk), (bw_add(bw_sub(bw_sub(bw_sub(bw_sub(data->maximum_latency_hiding_with_cursor[k], vbios->nbp_state_change_latency), data->dmif_burst_time[i][j]), data->dram_speed_change_line_source_transfer_time[k][i][j]), data->mcifwr_burst_time[i][j]), data->active_time[k])))); k 1407 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->display_pstate_change_enable[k] = 1; k 1418 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1419 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k] == 1 && data->display_pstate_change_enable[k] == 1) { k 1427 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1428 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k]) { k 1429 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) { k 1430 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]); k 1431 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]); k 1434 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_blank_dram_speed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div(data->src_height[k], data->v_scale_ratio[k]), bw_int_to_fixed(4)))), data->h_total[k]), data->pixel_rate[k]), vbios->nbp_state_change_latency), data->dmif_burst_time[low][s_low]), data->mcifwr_burst_time[low][s_low]), data->dram_speed_change_line_source_transfer_time[k][low][s_low]); k 1435 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->min_vblank_dram_speed_change_margin = bw_min2(data->min_vblank_dram_speed_change_margin, data->v_blank_dram_speed_change_margin[k]); k 1792 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 1793 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k] && bw_mtn(vbios->blackout_duration, bw_int_to_fixed(0)) && data->cpup_state_change_enable == bw_def_yes) { k 1794 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (surface_type[k] != bw_def_display_write_back420_luma && surface_type[k] != bw_def_display_write_back420_chroma) { k 1796 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])))))) { k 1797 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_mul(bw_int_to_fixed(2), data->total_dmifmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]))))); k 1802 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_ltn(data->adjusted_data_buffer_size[k], bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), (bw_add(vbios->blackout_duration, bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])))))) { k 1803 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->blackout_recovery_time = bw_max2(data->blackout_recovery_time, bw_div((bw_add(bw_mul(bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]), vbios->blackout_duration), bw_sub(bw_div(bw_mul(bw_mul(bw_mul((bw_add(bw_add(bw_mul(bw_int_to_fixed(2), vbios->mcifwrmc_urgent_latency), data->dmif_burst_time[data->y_clk_level][data->sclk_level]), data->mcifwr_burst_time[data->y_clk_level][data->sclk_level])), data->dispclk), bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), data->adjusted_data_buffer_size[k]))), (bw_sub(bw_div(bw_mul(bw_mul(data->dispclk, bw_int_to_fixed(data->bytes_per_pixel[k])), data->lines_interleaved_in_mem_access[k]), data->latency_hiding_lines[k]), bw_div(bw_mul(data->display_bandwidth[k], data->useful_bytes_per_request[k]), data->bytes_per_request[k]))))); k 2006 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c for (k = 0; k <= maximum_number_of_surfaces - 1; k++) { k 2007 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bpphdmi[k] = bw_def_na; k 2008 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr[k] = bw_def_na; k 2009 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr2[k] = bw_def_na; k 2010 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr3[k] = bw_def_na; k 2011 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (data->enable[k]) { k 2012 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bpphdmi[k] = bw_fixed_to_int(bw_mul(bw_div(bw_min2(bw_int_to_fixed(600), data->max_phyclk), data->pixel_rate[k]), bw_int_to_fixed(24))); k 2014 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(270), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8))); k 2017 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr2[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(540), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8))); k 2020 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->output_bppdp4_lane_hbr3[k] = bw_fixed_to_int(bw_mul(bw_div(bw_mul(bw_int_to_fixed(810), bw_int_to_fixed(4)), data->pixel_rate[k]), bw_int_to_fixed(8))); k 42 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c int k; k 43 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 45 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 46 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; k 47 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; k 50 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; k 51 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; k 55 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 56 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k] / v->scaler_recout_height[k]); k 59 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->h_ratio[k] =dcn_bw_max2(v->viewport_height[k] / v->scaler_rec_out_width[k], v->viewport_width[k] / v->scaler_recout_height[k]); k 61 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio[k] = v->h_ratio[k]; k 63 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->interlace_output[k] == 1.0) { k 64 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio[k] = 2.0 * v->v_ratio[k]; k 66 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->underscan_output[k] == 1.0) { k 67 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->h_ratio[k] = v->h_ratio[k] * v->under_scan_factor; k 68 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio[k] = v->v_ratio[k] * v->under_scan_factor; k 73 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 74 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] > 1.0) { k 75 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->acceptable_quality_hta_ps =dcn_bw_min2(v->max_hscl_taps, 2.0 *dcn_bw_ceil2(v->h_ratio[k], 1.0)); k 77 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->h_ratio[k] < 1.0) { k 84 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->htaps[k] = v->override_hta_ps[k]; k 87 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->htaps[k] = v->acceptable_quality_hta_ps; k 89 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] > 1.0) { k 90 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->acceptable_quality_vta_ps =dcn_bw_min2(v->max_vscl_taps, 2.0 *dcn_bw_ceil2(v->v_ratio[k], 1.0)); k 92 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->v_ratio[k] < 1.0) { k 99 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->vtaps[k] = v->override_vta_ps[k]; k 102 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->vtaps[k] = v->acceptable_quality_vta_ps; k 104 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { k 105 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->vta_pschroma[k] = 0.0; k 106 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->hta_pschroma[k] = 0.0; k 110 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->vta_pschroma[k] = v->override_vta_pschroma[k]; k 111 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->hta_pschroma[k] = v->override_hta_pschroma[k]; k 114 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->vta_pschroma[k] = v->acceptable_quality_vta_ps; k 115 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->hta_pschroma[k] = v->acceptable_quality_hta_ps; k 125 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c int k; k 131 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 132 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) { k 139 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 140 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_surface_mode[k] == dcn_bw_sw_linear && v->source_scan[k] != dcn_bw_hor) || ((v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x || v->source_surface_mode[k] == dcn_bw_sw_var_d || v->source_surface_mode[k] == dcn_bw_sw_var_d_x) && v->source_pixel_format[k] != dcn_bw_rgb_sub_64)) { k 146 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 147 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 148 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_ysingle_dpp[k] = v->viewport_width[k]; k 151 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_ysingle_dpp[k] = v->viewport_height[k]; k 153 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 154 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_dety[k] = 8.0; k 155 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_detc[k] = 0.0; k 157 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { k 158 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_dety[k] = 4.0; k 159 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_detc[k] = 0.0; k 161 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { k 162 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_dety[k] = 2.0; k 163 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_detc[k] = 0.0; k 165 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 166 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_dety[k] = 1.0; k 167 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_detc[k] = 2.0; k 170 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_dety[k] = 4.0f / 3.0f; k 171 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_in_detc[k] = 8.0f / 3.0f; k 175 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 176 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth[k] = v->swath_width_ysingle_dpp[k] * (dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) * v->v_ratio[k] +dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); k 177 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 178 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); k 180 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes && v->source_scan[k] != dcn_bw_hor && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x)) { k 181 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 64); k 183 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->pte_enable == dcn_bw_yes && v->source_scan[k] == dcn_bw_hor && (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32) && (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x)) { k 184 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 256); k 187 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth[k] = v->read_bandwidth[k] * (1 + 1 / 512); k 189 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_read_bandwidth_consumed_gbyte_per_second = v->total_read_bandwidth_consumed_gbyte_per_second + v->read_bandwidth[k] / 1000.0; k 192 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 193 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { k 194 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; k 196 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->output[k] == dcn_bw_writeback) { k 197 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; k 200 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->write_bandwidth[k] = 0.0; k 202 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_write_bandwidth_consumed_gbyte_per_second = v->total_write_bandwidth_consumed_gbyte_per_second + v->write_bandwidth[k] / 1000.0; k 206 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 207 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 241 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 242 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { k 245 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->output[k] == dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / v->write_back_latency) { k 262 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 263 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_dp && v->dsc_capability == dcn_bw_yes) { k 264 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output_format[k] == dcn_bw_420) { k 265 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_output_bw = v->pixel_clock[k] / 2.0; k 268 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_output_bw = v->pixel_clock[k]; k 271 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->output_format[k] == dcn_bw_420) { k 272 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0; k 275 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_output_bw = v->pixel_clock[k] * 3.0; k 277 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_hdmi) { k 278 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = v->required_output_bw; k 279 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c switch (v->output_deep_color[k]) { k 281 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = v->required_phyclk[k] * 5.0 / 4; k 284 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = v->required_phyclk[k] * 3.0 / 2; k 289 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = v->required_phyclk[k] / 3.0; k 291 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->output[k] == dcn_bw_dp) { k 292 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = v->required_output_bw / 4.0; k 295 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_phyclk[k] = 0.0; k 300 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 301 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->required_phyclk[k] > v->phyclk_per_state[i] || (v->output[k] == dcn_bw_hdmi && v->required_phyclk[k] > 600.0)) { k 309 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 310 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback) { k 322 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 323 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] > 1.0) { k 324 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); k 327 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_factor[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); k 329 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_in_detc[k] == 0.0) { k 330 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_factor_chroma[k] = 0.0; k 331 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0); k 334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] / 2.0 > 1.0) { k 335 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); k 338 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_factor_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); k 340 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0); k 343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 344 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { k 345 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 346 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 1.0; k 348 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 349 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 4.0; k 352 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 8.0; k 354 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; k 355 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_c[k] = 0.0; k 356 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_width_c[k] = 0.0; k 359 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 360 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 1.0; k 361 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_c[k] = 1.0; k 363 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 364 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 16.0; k 365 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_c[k] = 8.0; k 368 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_y[k] = 8.0; k 369 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_height_c[k] = 8.0; k 371 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_width_y[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->read256_block_height_y[k]; k 372 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read256_block_width_c[k] = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->read256_block_height_c[k]; k 374 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 375 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_swath_height_y[k] = v->read256_block_height_y[k]; k 376 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_swath_height_c[k] = v->read256_block_height_c[k]; k 379 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_swath_height_y[k] = v->read256_block_width_y[k]; k 380 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_swath_height_c[k] = v->read256_block_width_c[k]; k 382 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { k 383 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { k 384 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k]; k 387 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; k 389 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k]; k 392 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 393 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k]; k 394 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k]; k 396 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { k 397 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; k 399 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k]; k 402 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; k 405 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { k 406 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k] / 2.0; k 408 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k]; k 411 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k] / 2.0; k 415 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_y[k] = v->max_swath_height_y[k]; k 416 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_swath_height_c[k] = v->max_swath_height_c[k]; k 419 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 425 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->number_of_dpp_required_for_det_size =dcn_bw_ceil2(v->swath_width_ysingle_dpp[k] /dcn_bw_min2(v->maximum_swath_width, v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / (v->byte_per_pixel_in_dety[k] * v->min_swath_height_y[k] + v->byte_per_pixel_in_detc[k] / 2.0 * v->min_swath_height_c[k])), 1.0); k 426 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_in_detc[k] == 0.0) { k 427 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0); k 430 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0)); k 432 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->number_of_dpp_required_for_det_and_lb_size[k] =dcn_bw_max2(v->number_of_dpp_required_for_det_size, v->number_of_dpp_required_for_lb_size); k 439 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 440 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); k 442 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k] / 2.0, v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); k 445 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); k 451 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->min_dispclk_using_single_dpp <=dcn_bw_min2(v->max_dispclk[i], (j + 1) * v->max_dppclk[i]) && v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { k 452 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->no_of_dpp[i][j][k] = 1.0; k 456 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->no_of_dpp[i][j][k] = 2.0; k 460 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->no_of_dpp[i][j][k] = 2.0; k 464 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k]; k 470 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 471 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_single_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] * (j + 1)) * (1.0 + v->downspreading / 100.0); k 472 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_dispclk_using_dual_dpp =dcn_bw_max2(v->pixel_clock[k], v->min_dppclk_using_single_dpp[k] / 2.0 * (j + 1)) * (1.0 + v->downspreading / 100.0); k 477 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->number_of_dpp_required_for_det_and_lb_size[k] <= 1.0) { k 478 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->no_of_dpp[i][j][k] = 1.0; k 485 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->no_of_dpp[i][j][k] = 2.0; k 491 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_number_of_active_dpp[i][j] = v->total_number_of_active_dpp[i][j] + v->no_of_dpp[i][j][k]; k 499 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 500 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->number_of_dpp_required_for_det_and_lb_size[k] > 2.0) { k 518 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 521 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_yper_state[i][j][k] = v->swath_width_ysingle_dpp[k] / v->no_of_dpp[i][j][k]; k 522 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_granularity_y = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->max_swath_height_y[k]; k 523 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->rounded_up_max_swath_size_bytes_y = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] - 1.0, v->swath_width_granularity_y) + v->swath_width_granularity_y) * v->byte_per_pixel_in_dety[k] * v->max_swath_height_y[k]; k 524 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { k 527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->max_swath_height_c[k] > 0.0) { k 528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_granularity_c = 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->max_swath_height_c[k]; k 530 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->rounded_up_max_swath_size_bytes_c = (dcn_bw_ceil2(v->swath_width_yper_state[i][j][k] / 2.0 - 1.0, v->swath_width_granularity_c) + v->swath_width_granularity_c) * v->byte_per_pixel_in_detc[k] * v->max_swath_height_c[k]; k 531 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { k 535 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_yper_state[i][j][k] = v->max_swath_height_y[k]; k 536 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_cper_state[i][j][k] = v->max_swath_height_c[k]; k 539 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_yper_state[i][j][k] = v->min_swath_height_y[k]; k 540 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_cper_state[i][j][k] = v->min_swath_height_c[k]; k 542 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_in_detc[k] == 0.0) { k 543 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; k 546 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->swath_height_yper_state[i][j][k] <= v->swath_height_cper_state[i][j][k]) { k 547 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; k 548 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 2.0 / v->byte_per_pixel_in_detc[k] / (v->swath_width_yper_state[i][j][k] / 2.0); k 551 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_det_luma = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0 / v->byte_per_pixel_in_dety[k] / v->swath_width_yper_state[i][j][k]; k 552 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_det_chroma = v->det_buffer_size_in_kbyte * 1024.0 / 3.0 / v->byte_per_pixel_in_dety[k] / (v->swath_width_yper_state[i][j][k] / 2.0); k 554 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); k 555 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_lb_latency_hiding_source_lines_chroma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); k 556 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_detlb_lines_luma =dcn_bw_floor2(v->lines_in_det_luma +dcn_bw_min2(v->lines_in_det_luma * v->required_dispclk[i][j] * v->byte_per_pixel_in_dety[k] * v->pscl_factor[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_yper_state[i][j][k]); k 557 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_detlb_lines_chroma =dcn_bw_floor2(v->lines_in_det_chroma +dcn_bw_min2(v->lines_in_det_chroma * v->required_dispclk[i][j] * v->byte_per_pixel_in_detc[k] * v->pscl_factor_chroma[k] / v->return_bw_per_state[i], v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_cper_state[i][j][k]); k 558 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_in_detc[k] == 0.0) { k 559 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us_per_state[i][j][k] = v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]); k 562 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us_per_state[i][j][k] =dcn_bw_min2(v->effective_detlb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_detlb_lines_luma * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k]), v->effective_detlb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_detlb_lines_chroma * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / (v->return_bw_per_state[i] / v->no_of_dpp[i][j][k])); k 570 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 571 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->urgent_latency_support_us_per_state[i][j][k] < v->urgent_latency / 1.0) { k 582 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 583 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 584 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_number_of_dcc_active_dpp[i][j] = v->total_number_of_dcc_active_dpp[i][j] + v->no_of_dpp[i][j][k]; k 592 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 593 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, v->pixel_clock[k] / 16.0); k 594 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_in_detc[k] == 0.0) { k 595 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] <= 1.0) { k 596 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); k 599 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 64.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); k 603 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] <= 1.0) { k 604 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->h_ratio[k] * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); k 607 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 32.0 * v->pscl_factor[k] * v->required_dispclk[i][j] / (1 + j)); k 609 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] / 2.0 <= 1.0) { k 610 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->h_ratio[k] / 2.0 * v->pixel_clock[k] / v->no_of_dpp[i][j][k]); k 613 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->projected_dcfclk_deep_sleep =dcn_bw_max2(v->projected_dcfclk_deep_sleep, 1.1 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 32.0 * v->pscl_factor_chroma[k] * v->required_dispclk[i][j] / (1 + j)); k 617 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 618 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 619 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_req_height_y = 8.0 * v->read256_block_height_y[k]; k 620 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_req_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->meta_req_height_y; k 621 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surface_width_y =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0, v->meta_req_width_y) + v->meta_req_width_y; k 622 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surface_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, v->meta_req_height_y) + v->meta_req_height_y; k 624 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_per_frame_y = (dcn_bw_ceil2((v->meta_surface_width_y * v->meta_surface_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; k 629 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 630 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes_y = v->meta_surface_width_y * v->meta_req_height_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; k 633 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes_y = v->meta_surface_height_y * v->meta_req_width_y *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / 256.0; k 641 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 645 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { k 647 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_y = 4.0 * v->read256_block_height_y[k]; k 649 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { k 651 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_y = 16.0 * v->read256_block_height_y[k]; k 655 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_y = 32.0 * v->read256_block_height_y[k]; k 661 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_pte_req_height_y = 16.0 * v->read256_block_height_y[k]; k 663 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) / v->data_pte_req_height_y * 8; k 664 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 665 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_y / (v->viewport_width[k] / v->no_of_dpp[i][j][k]), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_y, 1.0) + 1); k 667 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_scan[k] == dcn_bw_hor) { k 668 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] - 1.0) / v->data_pte_req_width_y, 1.0) + 1); k 671 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->data_pte_req_height_y, 1.0) + 1); k 677 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { k 678 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 679 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_req_height_c = 8.0 * v->read256_block_height_c[k]; k 680 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_req_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->meta_req_height_c; k 681 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surface_width_c =dcn_bw_ceil2(v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0, v->meta_req_width_c) + v->meta_req_width_c; k 682 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surface_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, v->meta_req_height_c) + v->meta_req_height_c; k 684 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_per_frame_c = (dcn_bw_ceil2((v->meta_surface_width_c * v->meta_surface_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; k 689 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 690 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes_c = v->meta_surface_width_c * v->meta_req_height_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; k 693 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes_c = v->meta_surface_height_c * v->meta_req_width_c *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 256.0; k 701 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { k 707 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_c = 4.0 * v->read256_block_height_c[k]; k 709 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { k 711 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_c = 16.0 * v->read256_block_height_c[k]; k 715 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_height_c = 32.0 * v->read256_block_height_c[k]; k 717 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->macro_tile_block_width_c = v->macro_tile_block_size_bytes_c /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->macro_tile_block_height_c; k 722 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_pte_req_height_c = 16.0 * v->read256_block_height_c[k]; k 724 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / v->data_pte_req_height_c * 8; k 725 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 726 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->data_pte_req_width_c / (v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0), 2.0), 1.0))) - 1.0) / v->data_pte_req_width_c, 1.0) + 1); k 728 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_scan[k] == dcn_bw_hor) { k 729 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_width[k] / v->no_of_dpp[i][j][k] / 2.0 - 1.0) / v->data_pte_req_width_c, 1.0) + 1); k 732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->data_pte_req_height_c, 1.0) + 1); k 744 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpte_bytes_per_row[k] = v->dpte_bytes_per_row_y + v->dpte_bytes_per_row_c; k 745 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_per_frame[k] = v->meta_pte_bytes_per_frame_y + v->meta_pte_bytes_per_frame_c; k 746 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes[k] = v->meta_row_bytes_y + v->meta_row_bytes_c; k 747 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0; k 748 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefill_y[k] =dcn_bw_floor2(v->v_init_y, 1.0); k 749 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_num_sw_y[k] =dcn_bw_ceil2((v->prefill_y[k] - 1.0) / v->swath_height_yper_state[i][j][k], 1.0) + 1; k 750 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->prefill_y[k] > 1.0) { k 751 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] - 2.0), v->swath_height_yper_state[i][j][k]); k 754 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_sw_y =dcn_bw_mod((v->prefill_y[k] + v->swath_height_yper_state[i][j][k] - 2.0), v->swath_height_yper_state[i][j][k]); k 757 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_lines_y[k] = v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k] + v->max_partial_sw_y; k 758 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { k 759 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0; k 760 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefill_c[k] =dcn_bw_floor2(v->v_init_c, 1.0); k 761 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_num_sw_c[k] =dcn_bw_ceil2((v->prefill_c[k] - 1.0) / v->swath_height_cper_state[i][j][k], 1.0) + 1; k 762 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->prefill_c[k] > 1.0) { k 763 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] - 2.0), v->swath_height_cper_state[i][j][k]); k 766 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_sw_c =dcn_bw_mod((v->prefill_c[k] + v->swath_height_cper_state[i][j][k] - 2.0), v->swath_height_cper_state[i][j][k]); k 769 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_lines_c[k] = v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k] + v->max_partial_sw_c; k 772 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_lines_c[k] = 0.0; k 774 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dst_x_after_scaler = 90.0 * v->pixel_clock[k] / (v->required_dispclk[i][j] / (j + 1)) + 42.0 * v->pixel_clock[k] / v->required_dispclk[i][j]; k 775 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->no_of_dpp[i][j][k] > 1.0) { k 776 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dst_x_after_scaler = v->dst_x_after_scaler + v->scaler_rec_out_width[k] / 2.0; k 778 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output_format[k] == dcn_bw_420) { k 785 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); k 787 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; k 788 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; k 789 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k]; k 795 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->maximum_vstartup = v->vtotal[k] - v->vactive[k] - 1.0; k 798 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0; k 802 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]); k 803 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4; k 804 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); k 806 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { k 808 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], k 810 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->htotal[k] / v->pixel_clock[k] / 4.0); k 812 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; k 815 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { k 817 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k], k 818 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, k 822 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, k 826 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 827 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 830 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0) k 836 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 837 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->bw_available_for_immediate_flip = v->bw_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth[k], v->prefetch_bw[k]); k 839 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 840 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_immediate_flip_bytes[k] = 0.0; k 841 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 842 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_immediate_flip_bytes[k] = v->total_immediate_flip_bytes[k] + v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]; k 845 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 846 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { k 847 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); k 850 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0; k 852 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) { k 853 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency); k 856 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip); k 858 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 859 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 860 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k]; k 861 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k]; k 863 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywith_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; k 864 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_yper_state[i][j][k] > 4.0)) { k 865 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { k 866 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywith_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); k 869 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; k 872 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwith_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip; k 873 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_cper_state[i][j][k] > 4.0)) { k 874 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { k 875 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwith_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwith_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); k 878 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; k 881 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_with_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); k 884 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywith_immediate_flip[i][j][k] = 999999.0; k 885 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwith_immediate_flip[i][j][k] = 999999.0; k 886 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k] = 999999.0; k 889 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; k 890 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_yper_state[i][j][k] > 4.0)) { k 891 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0 > 0.0) { k 892 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_ywithout_immediate_flip[i][j][k], (v->max_num_sw_y[k] * v->swath_height_yper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_y[k] - 3.0) / 2.0)); k 895 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; k 898 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip; k 899 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_cper_state[i][j][k] > 4.0)) { k 900 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0 > 0.0) { k 901 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwithout_immediate_flip[i][j][k] =dcn_bw_max2(v->v_ratio_pre_cwithout_immediate_flip[i][j][k], (v->max_num_sw_c[k] * v->swath_height_cper_state[i][j][k]) / (v->line_times_to_request_prefetch_pixel_data_without_immediate_flip - (v->prefill_c[k] - 3.0) / 2.0)); k 904 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; k 907 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = v->no_of_dpp[i][j][k] * (v->prefetch_lines_y[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] / v->line_times_to_request_prefetch_pixel_data_without_immediate_flip *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0) / 2.0) * v->swath_width_yper_state[i][j][k] / (v->htotal[k] / v->pixel_clock[k]); k 910 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_ywithout_immediate_flip[i][j][k] = 999999.0; k 911 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_pre_cwithout_immediate_flip[i][j][k] = 999999.0; k 912 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k] = 999999.0; k 916 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 917 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 918 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_with_immediate_flip[i][j][k]) +dcn_bw_max2(v->meta_pte_bytes_per_frame[k] / (v->lines_for_meta_pte_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / (v->lines_for_meta_and_dpte_row_with_immediate_flip[k] * v->htotal[k] / v->pixel_clock[k])); k 921 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->maximum_read_bandwidth_with_prefetch_with_immediate_flip = v->maximum_read_bandwidth_with_prefetch_with_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); k 925 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 926 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->maximum_read_bandwidth_with_prefetch_without_immediate_flip = v->maximum_read_bandwidth_with_prefetch_without_immediate_flip +dcn_bw_max2(v->read_bandwidth[k], v->required_prefetch_pixel_data_bw_without_immediate_flip[i][j][k]); k 932 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 933 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_with_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_with_immediate_flip[k] >= 16.0) { k 941 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 942 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->line_times_for_prefetch[k] < 2.0 || v->lines_for_meta_pte_without_immediate_flip[k] >= 8.0 || v->lines_for_meta_and_dpte_row_without_immediate_flip[k] >= 16.0) { k 951 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 952 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywith_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwith_immediate_flip[i][j][k] > 4.0)) || ((v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 || v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) && (v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)))) { k 957 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 958 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->v_ratio_pre_ywithout_immediate_flip[i][j][k] > 4.0 || v->v_ratio_pre_cwithout_immediate_flip[i][j][k] > 4.0)) { k 1010 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1011 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k]; k 1020 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c int k; k 1025 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1026 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_number_of_active_dpp_per_ratio[j] = v->total_number_of_active_dpp_per_ratio[j] + v->dpp_per_plane_per_ratio[j][k]; k 1037 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1038 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpp_per_plane[k] = v->dpp_per_plane_per_ratio[v->dispclk_dppclk_ratio - 1][k]; k 1040 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1041 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 1045 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { k 1049 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { k 1053 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 1061 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { k 1062 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1065 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 1076 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1080 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 1091 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 1099 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { k 1100 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear || (v->source_pixel_format[k] == dcn_bw_rgb_sub_64 && (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_var_s || v->source_surface_mode[k] == dcn_bw_sw_var_s_x) && v->source_scan[k] == dcn_bw_hor)) { k 1109 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1113 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8 && v->source_scan[k] == dcn_bw_hor) { k 1122 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10 && v->source_scan[k] == dcn_bw_hor) { k 1136 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 1137 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width = v->viewport_width[k] / v->dpp_per_plane[k]; k 1140 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width = v->viewport_height[k] / v->dpp_per_plane[k]; k 1144 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { k 1151 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_10) { k 1155 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_y[k] = v->maximum_swath_height_y; k 1156 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_c[k] = v->maximum_swath_height_c; k 1159 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_y[k] = v->minimum_swath_height_y; k 1160 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_height_c[k] = v->minimum_swath_height_c; k 1162 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->swath_height_c[k] == 0.0) { k 1163 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0; k 1164 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_c[k] = 0.0; k 1166 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->swath_height_y[k] <= v->swath_height_c[k]) { k 1167 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; k 1168 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 2.0; k 1171 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_y[k] = v->det_buffer_size_in_kbyte * 1024.0 * 2.0 / 3.0; k 1172 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->det_buffer_size_c[k] = v->det_buffer_size_in_kbyte * 1024.0 / 3.0; k 1178 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c int k; k 1183 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1184 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] > 1.0) { k 1185 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] /dcn_bw_ceil2(v->htaps[k] / 6.0, 1.0)); k 1188 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_throughput[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); k 1190 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dppclk_using_single_dpp_luma = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_throughput[k], 1.0); k 1191 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 1192 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_throughput_chroma[k] = 0.0; k 1196 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->h_ratio[k] > 1.0) { k 1197 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput * v->h_ratio[k] / 2.0 /dcn_bw_ceil2(v->hta_pschroma[k] / 6.0, 1.0)); k 1200 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pscl_throughput_chroma[k] =dcn_bw_min2(v->max_dchub_topscl_throughput, v->max_pscl_tolb_throughput); k 1202 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dppclk_using_single_dpp_chroma = v->pixel_clock[k] *dcn_bw_max3(v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_throughput_chroma[k], 1.0); k 1206 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); k 1207 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k] / v->dpp_per_plane[k]) * (1.0 + v->downspreading / 100.0)); k 1210 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_with_ramping =dcn_bw_max2(v->dispclk_with_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0) * (1.0 + v->dispclk_ramping_margin / 100.0)); k 1211 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dispclk_without_ramping =dcn_bw_max2(v->dispclk_without_ramping,dcn_bw_max2(v->dppclk_using_single_dpp / v->dpp_per_plane[k] * v->dispclk_dppclk_ratio, v->pixel_clock[k]) * (1.0 + v->downspreading / 100.0)); k 1228 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1229 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1249 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1250 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 1251 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; k 1254 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; k 1257 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1258 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 1259 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_dety[k] = 8.0; k 1260 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_detc[k] = 0.0; k 1262 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { k 1263 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_dety[k] = 4.0; k 1264 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_detc[k] = 0.0; k 1266 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { k 1267 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_dety[k] = 2.0; k 1268 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_detc[k] = 0.0; k 1270 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 1271 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_dety[k] = 1.0; k 1272 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_detc[k] = 2.0; k 1275 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_dety[k] = 4.0f / 3.0f; k 1276 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->byte_per_pixel_detc[k] = 8.0f / 3.0f; k 1280 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1281 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; k 1282 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; k 1283 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_data_read_bandwidth = v->total_data_read_bandwidth + v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; k 1287 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1288 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_active_dpp = v->total_active_dpp + v->dpp_per_plane[k]; k 1289 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1290 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->total_dcc_active_dpp = v->total_dcc_active_dpp + v->dpp_per_plane[k]; k 1295 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1296 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] <= 1.0) { k 1297 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; k 1300 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; k 1302 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_fabric_line_delivery_time_luma = v->swath_width_y[k] * v->swath_height_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->return_bw * v->read_bandwidth_plane_luma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); k 1303 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_luma - v->display_pipe_line_delivery_time_luma[k]); k 1304 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] == 0.0) { k 1305 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma[k] = 0.0; k 1308 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio[k] / 2.0 <= 1.0) { k 1309 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] / (v->h_ratio[k] / 2.0) / v->pixel_clock[k]; k 1312 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; k 1314 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->data_fabric_line_delivery_time_chroma = v->swath_width_y[k] / 2.0 * v->swath_height_c[k] *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->return_bw * v->read_bandwidth_plane_chroma[k] / v->dpp_per_plane[k] / v->total_data_read_bandwidth); k 1315 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->last_pixel_of_line_extra_watermark =dcn_bw_max2(v->last_pixel_of_line_extra_watermark, v->data_fabric_line_delivery_time_chroma - v->display_pipe_line_delivery_time_chroma[k]); k 1328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1329 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback) { k 1341 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1342 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_dety[k] = v->det_buffer_size_y[k] / v->byte_per_pixel_dety[k] / v->swath_width_y[k]; k 1343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_dety_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_dety[k], v->swath_height_y[k]); k 1344 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->full_det_buffering_time_y[k] = v->lines_in_dety_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k]; k 1345 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] > 0.0) { k 1346 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_detc[k] = v->det_buffer_size_c[k] / v->byte_per_pixel_detc[k] / (v->swath_width_y[k] / 2.0); k 1347 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_detc_rounded_down_to_swath[k] =dcn_bw_floor2(v->lines_in_detc[k], v->swath_height_c[k]); k 1348 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->full_det_buffering_time_c[k] = v->lines_in_detc_rounded_down_to_swath[k] * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0); k 1351 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_detc[k] = 0.0; k 1352 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_in_detc_rounded_down_to_swath[k] = 0.0; k 1353 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->full_det_buffering_time_c[k] = 999999.0; k 1357 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1358 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->full_det_buffering_time_y[k] < v->min_full_det_buffering_time) { k 1359 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_full_det_buffering_time = v->full_det_buffering_time_y[k]; k 1360 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k]; k 1362 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->full_det_buffering_time_c[k] < v->min_full_det_buffering_time) { k 1363 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_full_det_buffering_time = v->full_det_buffering_time_c[k]; k 1364 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->frame_time_for_min_full_det_buffering_time = v->vtotal[k] * v->htotal[k] / v->pixel_clock[k]; k 1368 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1369 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1370 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / v->dcc_rate[k] / 1000.0; k 1373 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] / 1000.0; k 1375 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1376 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 256.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 256.0; k 1379 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->average_read_bandwidth_gbyte_per_second = v->average_read_bandwidth_gbyte_per_second + v->read_bandwidth_plane_luma[k] / 1000.0 / 512.0 + v->read_bandwidth_plane_chroma[k] / 1000.0 / 512.0; k 1391 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1393 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_blank_time = (v->vtotal[k] - v->vactive[k]) * v->htotal[k] / v->pixel_clock[k]; k 1403 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1404 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] > 0.0) { k 1405 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 32.0 / v->display_pipe_line_delivery_time_luma[k], 1.1 * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 32.0 / v->display_pipe_line_delivery_time_chroma[k]); k 1408 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcfclk_deep_sleep_per_plane[k] = 1.1 * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 64.0 / v->display_pipe_line_delivery_time_luma[k]; k 1410 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcfclk_deep_sleep_per_plane[k] =dcn_bw_max2(v->dcfclk_deep_sleep_per_plane[k], v->pixel_clock[k] / 16.0); k 1413 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1414 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dcf_clk_deep_sleep =dcn_bw_max2(v->dcf_clk_deep_sleep, v->dcfclk_deep_sleep_per_plane[k]); k 1422 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1423 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); k 1424 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us_luma = v->effective_det_plus_lb_lines_luma * (v->htotal[k] / v->pixel_clock[k]) / v->v_ratio[k] - v->effective_det_plus_lb_lines_luma * v->swath_width_y[k] * v->byte_per_pixel_dety[k] / (v->return_bw / v->dpp_per_plane[k]); k 1425 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] > 0.0) { k 1426 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); k 1427 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us_chroma = v->effective_det_plus_lb_lines_chroma * (v->htotal[k] / v->pixel_clock[k]) / (v->v_ratio[k] / 2.0) - v->effective_det_plus_lb_lines_chroma * (v->swath_width_y[k] / 2.0) * v->byte_per_pixel_detc[k] / (v->return_bw / v->dpp_per_plane[k]); k 1428 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us[k] =dcn_bw_min2(v->urgent_latency_support_us_luma, v->urgent_latency_support_us_chroma); k 1431 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->urgent_latency_support_us[k] = v->urgent_latency_support_us_luma; k 1435 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1436 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_urgent_latency_support_us =dcn_bw_min2(v->min_urgent_latency_support_us, v->urgent_latency_support_us[k]); k 1443 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1444 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] == dcn_bw_rgb_sub_64 || v->source_pixel_format[k] == dcn_bw_rgb_sub_32 || v->source_pixel_format[k] == dcn_bw_rgb_sub_16)) { k 1445 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1448 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 1457 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1461 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 1470 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1471 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_request_width_y = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (8.0 * v->block_height256_bytes_y); k 1472 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surf_width_y =dcn_bw_ceil2(v->swath_width_y[k] - 1.0, v->meta_request_width_y) + v->meta_request_width_y; k 1473 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surf_height_y =dcn_bw_ceil2(v->viewport_height[k] - 1.0, 8.0 * v->block_height256_bytes_y) + 8.0 * v->block_height256_bytes_y; k 1475 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_frame_y = (dcn_bw_ceil2((v->meta_surf_width_y * v->meta_surf_height_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; k 1480 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 1481 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_byte_y = v->meta_surf_width_y * 8.0 * v->block_height256_bytes_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; k 1484 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_byte_y = v->meta_surf_height_y * v->meta_request_width_y *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / 256.0; k 1492 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1496 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { k 1500 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { k 1514 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_req_width_y = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / v->pixel_pte_req_height_y * 8; k 1515 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1516 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] *dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_y / v->swath_width_y[k], 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); k 1518 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_scan[k] == dcn_bw_hor) { k 1519 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] - 1.0) / v->pixel_pte_req_width_y, 1.0) + 1); k 1522 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_y = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] - 1.0) / v->pixel_pte_req_height_y, 1.0) + 1); k 1528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { k 1529 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dcc_enable[k] == dcn_bw_yes) { k 1530 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_request_width_c = 64.0 * 256.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (8.0 * v->block_height256_bytes_c); k 1531 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surf_width_c =dcn_bw_ceil2(v->swath_width_y[k] / 2.0 - 1.0, v->meta_request_width_c) + v->meta_request_width_c; k 1532 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_surf_height_c =dcn_bw_ceil2(v->viewport_height[k] / 2.0 - 1.0, 8.0 * v->block_height256_bytes_c) + 8.0 * v->block_height256_bytes_c; k 1534 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_frame_c = (dcn_bw_ceil2((v->meta_surf_width_c * v->meta_surf_height_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0 - 4096.0) / 8.0 / 4096.0, 1.0) + 1) * 64.0; k 1539 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_scan[k] == dcn_bw_hor) { k 1540 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_byte_c = v->meta_surf_width_c * 8.0 * v->block_height256_bytes_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; k 1543 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_byte_c = v->meta_surf_height_c * v->meta_request_width_c *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 256.0; k 1551 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1555 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_4_kb_s || v->source_surface_mode[k] == dcn_bw_sw_4_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d || v->source_surface_mode[k] == dcn_bw_sw_4_kb_d_x) { k 1559 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_surface_mode[k] == dcn_bw_sw_64_kb_s || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_s_x || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_t || v->source_surface_mode[k] == dcn_bw_sw_64_kb_d_x) { k 1573 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_req_width_c = 4096.0 /dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / v->pixel_pte_req_height_c * 8; k 1574 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->source_surface_mode[k] == dcn_bw_sw_linear) { k 1575 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 * dcn_bw_min2(128.0, dcn_bw_pow(2.0,dcn_bw_floor2(dcn_bw_log(v->pte_buffer_size_in_requests * v->pixel_pte_req_width_c / (v->swath_width_y[k] / 2.0), 2.0), 1.0))) - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); k 1577 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->source_scan[k] == dcn_bw_hor) { k 1578 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->swath_width_y[k] / 2.0 - 1.0) / v->pixel_pte_req_width_c, 1.0) + 1); k 1581 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row_c = 64.0 * (dcn_bw_ceil2((v->viewport_height[k] / 2.0 - 1.0) / v->pixel_pte_req_height_c, 1.0) + 1); k 1593 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->pixel_pte_bytes_per_row[k] = v->pixel_pte_bytes_per_row_y + v->pixel_pte_bytes_per_row_c; k 1594 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_pte_bytes_frame[k] = v->meta_pte_bytes_frame_y + v->meta_pte_bytes_frame_c; k 1595 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->meta_row_byte[k] = v->meta_row_byte_y + v->meta_row_byte_c; k 1596 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_init_pre_fill_y[k] =dcn_bw_floor2((v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0, 1.0); k 1597 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_num_swath_y[k] =dcn_bw_ceil2((v->v_init_pre_fill_y[k] - 1.0) / v->swath_height_y[k], 1.0) + 1; k 1598 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_init_pre_fill_y[k] > 1.0) { k 1599 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] - 2.0), v->swath_height_y[k]); k 1602 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_swath_y =dcn_bw_mod((v->v_init_pre_fill_y[k] + v->swath_height_y[k] - 2.0), v->swath_height_y[k]); k 1605 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_source_lines_y[k] = v->max_num_swath_y[k] * v->swath_height_y[k] + v->max_partial_swath_y; k 1606 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16)) { k 1607 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_init_pre_fill_c[k] =dcn_bw_floor2((v->v_ratio[k] / 2.0 + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k] / 2.0) / 2.0, 1.0); k 1608 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_num_swath_c[k] =dcn_bw_ceil2((v->v_init_pre_fill_c[k] - 1.0) / v->swath_height_c[k], 1.0) + 1; k 1609 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_init_pre_fill_c[k] > 1.0) { k 1610 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] - 2.0), v->swath_height_c[k]); k 1613 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_partial_swath_c =dcn_bw_mod((v->v_init_pre_fill_c[k] + v->swath_height_c[k] - 2.0), v->swath_height_c[k]); k 1618 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_num_swath_c[k] = 0.0; k 1621 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_source_lines_c[k] = v->max_num_swath_c[k] * v->swath_height_c[k] + v->max_partial_swath_c; k 1624 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1626 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_vstartup_lines[k] = v->vtotal[k] - v->vactive[k] - 1.0; k 1629 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_vstartup_lines[k] = v->v_sync_plus_back_porch[k] - 1.0; k 1642 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1643 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; k 1644 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->dpp_per_plane[k] > 1.0) { k 1645 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dstx_after_scaler = v->dstx_after_scaler + v->scaler_rec_out_width[k] / 2.0; k 1647 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output_format[k] == dcn_bw_420) { k 1653 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_update_offset_pix[k] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); k 1655 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk + v->total_repeater_delay_time) * v->pixel_clock[k]; k 1656 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ready_offset_pix[k] = dcn_bw_max2(150.0 / v->dppclk, v->total_repeater_delay_time + 20.0 / v->dcf_clk_deep_sleep + 10.0 / v->dppclk) * v->pixel_clock[k]; k 1657 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->t_setup = (v->v_update_offset_pix[k] + v->v_update_width_pix[k] + v->v_ready_offset_pix[k]) / v->pixel_clock[k]; k 1658 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_startup[k] =dcn_bw_min2(v->v_startup_lines, v->max_vstartup_lines[k]); k 1668 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->destination_lines_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->v_startup[k] - v->t_wait / (v->htotal[k] / v->pixel_clock[k]) - (v->t_calc + v->t_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dsty_after_scaler + v->dstx_after_scaler / v->htotal[k]) + 0.125), 1.0) / 4; k 1669 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->destination_lines_for_prefetch[k] > 0.0) { k 1670 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_bandwidth[k] = (v->meta_pte_bytes_frame[k] + 2.0 * v->meta_row_byte[k] + 2.0 * v->pixel_pte_bytes_per_row[k] + v->prefetch_source_lines_y[k] * v->swath_width_y[k] *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] * v->swath_width_y[k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0)) / (v->destination_lines_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]); k 1673 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->prefetch_bandwidth[k] = 999999.0; k 1677 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1678 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->bandwidth_available_for_immediate_flip = v->bandwidth_available_for_immediate_flip -dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->prefetch_bandwidth[k]); k 1681 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1682 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 1683 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->tot_immediate_flip_bytes = v->tot_immediate_flip_bytes + v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]; k 1687 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1688 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) { k 1689 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 1690 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_meta_pte =dcn_bw_max5(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->meta_pte_bytes_frame[k] * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); k 1693 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_meta_pte =dcn_bw_max3(v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0); k 1697 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_meta_pte = v->htotal[k] / v->pixel_clock[k] / 4.0; k 1699 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->destination_lines_to_request_vm_inv_blank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_meta_pte / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 1700 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes)) { k 1701 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 1702 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_row_in_vblank =dcn_bw_max5((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) * v->tot_immediate_flip_bytes / (v->bandwidth_available_for_immediate_flip * (v->meta_pte_bytes_frame[k] + v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k])), v->urgent_extra_latency, 2.0 * v->urgent_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); k 1705 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_row_in_vblank =dcn_bw_max3((v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / v->prefetch_bandwidth[k], v->urgent_extra_latency, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); k 1709 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->time_for_fetching_row_in_vblank =dcn_bw_max2(v->urgent_extra_latency - v->time_for_fetching_meta_pte, v->htotal[k] / v->pixel_clock[k] - v->time_for_fetching_meta_pte); k 1711 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->destination_lines_to_request_row_in_vblank[k] =dcn_bw_floor2(4.0 * (v->time_for_fetching_row_in_vblank / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4; k 1712 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lines_to_request_prefetch_pixel_data = v->destination_lines_for_prefetch[k] - v->destination_lines_to_request_vm_inv_blank[k] - v->destination_lines_to_request_row_in_vblank[k]; k 1714 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_y[k] = v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data; k 1715 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_y[k] > 4.0)) { k 1716 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_y[k] - 3.0) / 2.0) { k 1717 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], v->max_num_swath_y[k] * v->swath_height_y[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_y[k] - 3.0) / 2.0)); k 1720 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_y[k] = 999999.0; k 1725 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_y[k] = 999999.0; k 1727 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_y[k] =dcn_bw_max2(v->v_ratio_prefetch_y[k], 1.0); k 1729 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_c[k] = v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data; k 1730 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if ((v->swath_height_c[k] > 4.0)) { k 1731 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->lines_to_request_prefetch_pixel_data > (v->v_init_pre_fill_c[k] - 3.0) / 2.0) { k 1732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], v->max_num_swath_c[k] * v->swath_height_c[k] / (v->lines_to_request_prefetch_pixel_data - (v->v_init_pre_fill_c[k] - 3.0) / 2.0)); k 1735 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_c[k] = 999999.0; k 1740 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_c[k] = 999999.0; k 1742 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_ratio_prefetch_c[k] =dcn_bw_max2(v->v_ratio_prefetch_c[k], 1.0); k 1744 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->required_prefetch_pix_data_bw = v->dpp_per_plane[k] * (v->prefetch_source_lines_y[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) + v->prefetch_source_lines_c[k] / v->lines_to_request_prefetch_pixel_data *dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / 2.0) * v->swath_width_y[k] / (v->htotal[k] / v->pixel_clock[k]); k 1749 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k], v->required_prefetch_pix_data_bw); k 1750 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->immediate_flip_supported == dcn_bw_yes && (v->source_pixel_format[k] != dcn_bw_yuv420_sub_8 && v->source_pixel_format[k] != dcn_bw_yuv420_sub_10)) { k 1751 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_rd_bandwidth = v->max_rd_bandwidth +dcn_bw_max2(v->meta_pte_bytes_frame[k] / (v->destination_lines_to_request_vm_inv_blank[k] * v->htotal[k] / v->pixel_clock[k]), (v->meta_row_byte[k] + v->pixel_pte_bytes_per_row[k]) / (v->destination_lines_to_request_row_in_vblank[k] * v->htotal[k] / v->pixel_clock[k])); k 1753 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { k 1756 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->destination_lines_for_prefetch[k] < 2.0) { k 1759 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->max_vstartup_lines[k] > v->v_startup_lines) { k 1760 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->required_prefetch_pix_data_bw > (v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k])) { k 1763 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio_prefetch_y[k] > 4.0 || v->v_ratio_prefetch_c[k] > 4.0) { k 1766 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->destination_lines_for_prefetch[k] < 2.0) { k 1781 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1782 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio_prefetch_y[k] <= 1.0) { k 1783 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; k 1786 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_luma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; k 1788 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] == 0.0) { k 1789 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma_prefetch[k] = 0.0; k 1792 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->v_ratio_prefetch_c[k] <= 1.0) { k 1793 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] * v->dpp_per_plane[k] / v->h_ratio[k] / v->pixel_clock[k]; k 1796 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->display_pipe_line_delivery_time_chroma_prefetch[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; k 1802 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1804 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_clock_change_during_vblank[k] = dcn_bw_yes; k 1805 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; k 1806 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max3(v->dram_clock_change_watermark, v->stutter_enter_plus_exit_watermark, v->urgent_watermark); k 1809 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; k 1810 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_yes; k 1811 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_ttuv_blank[k] = v->t_calc +dcn_bw_max2(v->stutter_enter_plus_exit_watermark, v->urgent_watermark); k 1814 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_clock_change_during_vblank[k] = dcn_bw_no; k 1815 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->allow_dram_self_refresh_during_vblank[k] = dcn_bw_no; k 1816 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_ttuv_blank[k] = v->t_calc + v->urgent_watermark; k 1822 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1823 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dp_ps = v->active_dp_ps + v->dpp_per_plane[k]; k 1825 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1826 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lb_latency_hiding_source_lines_y =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); k 1827 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->lb_latency_hiding_source_lines_c =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_y[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0)), 1.0)) - (v->vta_pschroma[k] - 1.0); k 1828 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_lb_latency_hiding_y = v->lb_latency_hiding_source_lines_y / v->v_ratio[k] * (v->htotal[k] / v->pixel_clock[k]); k 1829 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->effective_lb_latency_hiding_c = v->lb_latency_hiding_source_lines_c / (v->v_ratio[k] / 2.0) * (v->htotal[k] / v->pixel_clock[k]); k 1830 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->swath_width_y[k] > 2.0 * v->dpp_output_buffer_pixels) { k 1831 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpp_output_buffer_lines_y = v->dpp_output_buffer_pixels / v->swath_width_y[k]; k 1833 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->swath_width_y[k] > v->dpp_output_buffer_pixels) { k 1839 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->swath_width_y[k] / 2.0 > 2.0 * v->dpp_output_buffer_pixels) { k 1840 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dpp_output_buffer_lines_c = v->dpp_output_buffer_pixels / (v->swath_width_y[k] / 2.0); k 1842 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->swath_width_y[k] / 2.0 > v->dpp_output_buffer_pixels) { k 1848 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dppopp_buffering_y = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_y + v->opp_output_buffer_lines); k 1849 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_det_buffering_time_y = v->full_det_buffering_time_y[k] + (v->lines_in_dety[k] - v->lines_in_dety_rounded_down_to_swath[k]) / v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); k 1852 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dram_clock_change_latency_margin_y = v->active_dram_clock_change_latency_margin_y - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_y[k] * (v->htotal[k] / v->pixel_clock[k]); k 1854 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->byte_per_pixel_detc[k] > 0.0) { k 1855 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->dppopp_buffering_c = (v->htotal[k] / v->pixel_clock[k]) * (v->dpp_output_buffer_lines_c + v->opp_output_buffer_lines); k 1856 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->max_det_buffering_time_c = v->full_det_buffering_time_c[k] + (v->lines_in_detc[k] - v->lines_in_detc_rounded_down_to_swath[k]) / v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); k 1859 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dram_clock_change_latency_margin_c = v->active_dram_clock_change_latency_margin_c - (1.0 - 1.0 / (v->active_dp_ps - 1.0)) * v->swath_height_c[k] * (v->htotal[k] / v->pixel_clock[k]); k 1861 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin_y, v->active_dram_clock_change_latency_margin_c); k 1864 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dram_clock_change_latency_margin[k] = v->active_dram_clock_change_latency_margin_y; k 1866 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output_format[k] == dcn_bw_444) { k 1867 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->writeback_dram_clock_change_latency_margin = (v->writeback_luma_buffer_size + v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0) - v->writeback_dram_clock_change_watermark; k 1870 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->writeback_dram_clock_change_latency_margin =dcn_bw_min2(v->writeback_luma_buffer_size, 2.0 * v->writeback_chroma_buffer_size) * 1024.0 / (v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k])) - v->writeback_dram_clock_change_watermark; k 1872 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback) { k 1873 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->active_dram_clock_change_latency_margin[k] =dcn_bw_min2(v->active_dram_clock_change_latency_margin[k], v->writeback_dram_clock_change_latency_margin); k 1876 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1877 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->allow_dram_clock_change_during_vblank[k] == dcn_bw_yes) { k 1878 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_blank_dram_clock_change_latency_margin[k] = (v->vtotal[k] - v->scaler_recout_height[k]) * (v->htotal[k] / v->pixel_clock[k]) -dcn_bw_max2(v->dram_clock_change_watermark, v->writeback_dram_clock_change_watermark); k 1881 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_blank_dram_clock_change_latency_margin[k] = 0.0; k 1887 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1888 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->active_dram_clock_change_latency_margin[k] < v->min_active_dram_clock_change_margin) { k 1890 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; k 1891 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->v_blank_of_min_active_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; k 1893 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->active_dram_clock_change_latency_margin[k] < v->second_min_active_dram_clock_change_margin) { k 1894 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->second_min_active_dram_clock_change_margin = v->active_dram_clock_change_latency_margin[k]; k 1898 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1899 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->min_vblank_dram_clock_change_margin > v->v_blank_dram_clock_change_latency_margin[k]) { k 1900 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->min_vblank_dram_clock_change_margin = v->v_blank_dram_clock_change_latency_margin[k]; k 1924 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1925 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c if (v->output[k] == dcn_bw_writeback && v->output_format[k] == dcn_bw_444) { k 1926 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; k 1928 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c else if (v->output[k] == dcn_bw_writeback) { k 1929 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c v->wr_bandwidth = v->wr_bandwidth + v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; k 732 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int i, input_idx, k; k 1057 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1058 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (v->source_scan[k] == dcn_bw_hor) k 1059 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k]; k 1061 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k]; k 1063 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1064 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) { k 1065 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_dety[k] = 8.0; k 1066 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_detc[k] = 0.0; k 1067 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) { k 1068 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_dety[k] = 4.0; k 1069 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_detc[k] = 0.0; k 1070 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) { k 1071 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_dety[k] = 2.0; k 1072 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_detc[k] = 0.0; k 1073 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) { k 1074 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_dety[k] = 1.0; k 1075 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_detc[k] = 2.0; k 1077 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_dety[k] = 4.0f / 3.0f; k 1078 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->byte_per_pixel_detc[k] = 8.0f / 3.0f; k 1083 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c for (k = 0; k <= v->number_of_active_planes - 1; k++) { k 1084 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] * k 1085 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k]; k 1086 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] * k 1087 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0; k 1089 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k]; k 127 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c int k; k 134 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c for (k = 0; k < MAX_PIPES; k++) k 135 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c if (stream == context->res_ctx.pipe_ctx[k].stream) { k 136 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pipe_ctx = &context->res_ctx.pipe_ctx[k]; k 869 drivers/gpu/drm/amd/display/dc/core/dc.c int i, j, k; k 924 drivers/gpu/drm/amd/display/dc/core/dc.c for (k = 0; k < group_size; k++) { k 925 drivers/gpu/drm/amd/display/dc/core/dc.c struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream); k 929 drivers/gpu/drm/amd/display/dc/core/dc.c if (k == 0) k 1060 drivers/gpu/drm/amd/display/dc/core/dc.c int i, k, l; k 1124 drivers/gpu/drm/amd/display/dc/core/dc.c for (k = 0; k < MAX_PIPES; k++) { k 1125 drivers/gpu/drm/amd/display/dc/core/dc.c pipe = &context->res_ctx.pipe_ctx[k]; k 499 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c int k; k 506 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c for (k = 0; k < MAX_PIPES; k++) k 507 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c if (stream == context->res_ctx.pipe_ctx[k].stream) { k 508 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pipe_ctx = &context->res_ctx.pipe_ctx[k]; k 441 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; k 490 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c for (k = 0; k < 16; k++) { k 491 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (seg_distr[k] != -1) k 492 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c hw_points += (1 << seg_distr[k]); k 496 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c for (k = 0; k < (region_end - region_start); k++) { k 497 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); k 498 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c start_index = (region_start + k + MAX_LOW_POINT) * k 558 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c k = 0; k 560 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (seg_distr[k] != -1) { k 561 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; k 563 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); k 565 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c k++; k 568 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (seg_distr[k] != -1) k 569 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; k 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; k 369 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (k = 0; k < MAX_REGIONS_NUMBER; k++) { k 370 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) k 371 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c hw_points += (1 << seg_distr[k]); k 375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (k = 0; k < (region_end - region_start); k++) { k 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); k 377 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c start_index = (region_start + k + MAX_LOW_POINT) * k 452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c k = 0; k 454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) { k 455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].segments_num = k 456 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c seg_distr[k]; k 458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]); k 460 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c k++; k 463 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) k 464 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].segments_num = seg_distr[k]; k 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; k 535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (k = 0; k < MAX_REGIONS_NUMBER; k++) { k 536 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) k 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c hw_points += (1 << seg_distr[k]); k 541 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c for (k = 0; k < (region_end - region_start); k++) { k 542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); k 543 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c start_index = (region_start + k + MAX_LOW_POINT) * k 609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c k = 0; k 611 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) { k 612 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].segments_num = k 613 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c seg_distr[k]; k 615 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]); k 617 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c k++; k 620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c if (seg_distr[k] != -1) k 621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c lut_params->arr_curve_points[k].segments_num = seg_distr[k]; k 2207 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int i, j, k, dwb_pipe; k 2231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { k 2232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; k 2233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; k 1087 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int j, k; k 1096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k]) { k 1102 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackPixelFormat[k], k 1103 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k], k 1104 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackHRatio[k], k 1105 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackVRatio[k], k 1106 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaHTaps[k], k 1107 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaVTaps[k], k 1108 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaHTaps[k], k 1109 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaVTaps[k], k 1110 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDestinationWidth[k], k 1111 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k], k 1116 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1117 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.HRatio[k] > 1) { k 1118 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1121 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 1123 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.htaps[k] k 1127 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1133 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 1135 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.vtaps[k] / 6.0 k 1138 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k]), k 1140 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 1141 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] k 1142 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k], k 1145 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) k 1147 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c < 2 * mode_lib->vba.PixelClock[k]) { k 1148 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k]; k 1151 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 1152 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 1153 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0; k 1154 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLKUsingSingleDPP[k] = k 1157 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.HRatio[k] > 1) { k 1158 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = k 1162 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 1165 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTAPsChroma[k] k 1169 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min( k 1174 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 1176 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTAPsChroma[k] k 1180 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 1183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 1184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] k 1186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k], k 1189 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6) k 1191 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c < 2 * mode_lib->vba.PixelClock[k]) { k 1193 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k]; k 1196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max( k 1202 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] != k) k 1205 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ODMCombineEnabled[k]) { k 1209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] / 2 k 1219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] / 2 k 1223 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1227 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 1237 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 1274 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1275 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DPPPerPlane[k] == 0) { k 1276 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK_calculated[k] = 0; k 1278 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k] k 1279 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k] k 1284 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK_calculated[k]); k 1289 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1290 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255 k 1292 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK_calculated[k] * 255 k 1295 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]); k 1300 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 1301 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k]) k 1330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourceScan[k] == dm_horz) k 1334 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k]; k 1336 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k]; k 1338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ODMCombineEnabled[k] == true) k 1341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == j k 1346 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] = dml_min( k 1347 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.SwathWidthSingleDPPY[k], k 1349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HActive[k] / 2.0 k 1350 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k])); k 1352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DPPPerPlane[k] == 0) { k 1353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] = 0; k 1355 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k]; k 1361 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 1363 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 8; k 1364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1365 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 1366 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 4; k 1367 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1368 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 1369 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 2; k 1370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1371 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { k 1372 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 1; k 1373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 1375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 1; k 1376 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 2; k 1378 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0; k 1379 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0; k 1384 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1385 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1386 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) k 1387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1388 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k]; k 1389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1390 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2) k 1391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] / 2; k 1395 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c k, k 1396 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1397 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k]); k 1398 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1399 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k]; k 1404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.DPPPerPlane[k]; k 1407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k]) k 1409 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.DPPPerPlane[k]; k 1419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatio[k] <= 1.0) k 1423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = k 1424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.SwathWidthY[k] k 1425 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.DPPPerPlane[k] k 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.HRatio[k] k 1427 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = k 1430 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.SwathWidthY[k] k 1431 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPCLK[k]; k 1434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c DataFabricLineDeliveryTimeLuma = mode_lib->vba.SwathWidthSingleDPPY[k] k 1435 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.SwathHeightY[k] k 1436 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) k 1437 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.ReturnBW * mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1442 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]); k 1444 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] == 0) k 1445 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0; k 1446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) k 1447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = k 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] / 2.0 k 1449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.DPPPerPlane[k] k 1450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HRatio[k] / 2.0) k 1451 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 1453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = k 1454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] / 2.0 k 1455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] k 1456 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPCLK[k]; k 1458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c DataFabricLineDeliveryTimeChroma = mode_lib->vba.SwathWidthSingleDPPY[k] / 2.0 k 1459 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.SwathHeightC[k] k 1460 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2) k 1462 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1468 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]); k 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k]) k 1493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k]; k 1529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k] k 1531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k]; k 1532 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor( k 1533 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETY[k], k 1534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k]); k 1535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeY[k] = k 1536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETYRoundedDownToSwath[k] k 1537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 1538 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) k 1539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.VRatio[k]; k 1540 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] k 1542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.BytePerPixelDETC[k] k 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.SwathWidthY[k] / 2); k 1544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( k 1545 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETC[k], k 1546 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k]); k 1547 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeC[k] = k 1548 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] k 1549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 1550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) k 1551 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.VRatio[k] / 2); k 1553 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETC[k] = 0; k 1554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0; k 1555 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeC[k] = 999999; k 1560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.FullDETBufferingTimeY[k] k 1564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeY[k]; k 1566 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] k 1567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 1569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.FullDETBufferingTimeC[k] k 1572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeC[k]; k 1574 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] k 1575 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 1580 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1581 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k]) { k 1584 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1585 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DCCRate[k] k 1587 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DCCRate[k] k 1593 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1598 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k]) { k 1601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1603 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1640 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1642 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k] k 1643 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k] k 1644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 1662 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) { k 1663 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1664 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = k 1666 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 1.1 * mode_lib->vba.SwathWidthY[k] k 1668 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k], k 1670 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], k 1671 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 1.1 * mode_lib->vba.SwathWidthY[k] / 2.0 k 1673 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k], k 1675 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]); k 1677 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k] k 1678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0 k 1679 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]; k 1680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( k 1681 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k], k 1682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] / 16.0); k 1685 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); k 1689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c k, k 1690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); k 1707 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1710 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETY[k] k 1712 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETY[k] k 1713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.DPPCLK[k] k 1714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.BytePerPixelDETY[k] k 1715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 1717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k]), k 1719 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k]); k 1722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1723 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.VRatio[k] k 1725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.SwathWidthY[k] k 1726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.BytePerPixelDETY[k] k 1728 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k]); k 1730 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETC[k] k 1735 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.LinesInDETC[k] k 1736 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.DPPCLK[k] k 1737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.BytePerPixelDETC[k] k 1738 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] k 1740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k]), k 1742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k]); k 1745 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 1746 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) k 1747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.VRatio[k] / 2) k 1749 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.SwathWidthY[k] k 1751 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.BytePerPixelDETC[k] k 1753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPPerPlane[k]); k 1754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.UrgentLatencySupportUs[k] = dml_min( k 1758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.UrgentLatencySupportUs[k] = k 1764 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1767 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.UrgentLatencySupportUs[k]); k 1775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1776 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { k 1777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCCLK_calculated[k] = 0.0; k 1779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 1780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.OutputFormat[k] == dm_n422) k 1784 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ODMCombineEnabled[k]) k 1785 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCCLK_calculated[k] = k 1786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClockBackEnd[k] / 6 k 1792 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCCLK_calculated[k] = k 1793 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClockBackEnd[k] / 3 k 1803 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1804 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c double bpp = mode_lib->vba.OutputBpp[k]; k 1805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; k 1807 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { k 1808 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1809 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k] = k 1811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k], k 1814 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.HActive[k] k 1815 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.NumberOfDSCSlices[k], k 1818 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]) k 1820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]); k 1822 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k] = k 1825 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k], k 1828 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.HActive[k] k 1829 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.NumberOfDSCSlices[k], k 1832 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]) k 1834 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k])); k 1836 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] k 1837 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k] k 1838 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClockBackEnd[k]; k 1840 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k] = 0; k 1844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 1846 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (j != k && mode_lib->vba.BlendingAndTiming[k] == j k 1848 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j]; k 1851 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1860 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 1861 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 1862 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 1863 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), k 1864 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.BlockHeight256BytesY[k], k 1865 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.BlockHeight256BytesC[k], k 1866 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.BlockWidth256BytesY[k], k 1867 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.BlockWidth256BytesC[k]); k 1870 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 1871 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BlockHeight256BytesY[k], k 1872 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BlockWidth256BytesY[k], k 1873 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 1874 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 1875 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 1876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourceScan[k], k 1877 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k], k 1878 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportHeight[k], k 1879 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k], k 1884 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PitchY[k], k 1885 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCMetaPitchY[k], k 1886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MacroTileWidthY[k], k 1890 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_height[k], k 1891 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_height[k]); k 1892 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( k 1894 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 1895 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.vtaps[k], k 1896 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 1898 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k], k 1899 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportYStartY[k], k 1900 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VInitPreFillY[k], k 1901 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MaxNumSwathY[k]); k 1903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 1904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 1905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 1906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) { k 1910 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 1911 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BlockHeight256BytesC[k], k 1912 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BlockWidth256BytesC[k], k 1913 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 1914 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 1916 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k], k 1918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourceScan[k], k 1919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k] / 2, k 1920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportHeight[k] / 2, k 1921 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] / 2, k 1926 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PitchC[k], k 1928 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MacroTileWidthC[k], k 1932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_height_chroma[k], k 1933 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_height_chroma[k]); k 1934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( k 1936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k] / 2, k 1937 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTAPsChroma[k], k 1938 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 1940 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k], k 1941 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportYStartC[k], k 1942 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VInitPreFillC[k], k 1943 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MaxNumSwathC[k]); k 1948 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxNumSwathC[k] = 0; k 1949 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchSourceLinesC[k] = 0; k 1952 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; k 1953 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY k 1955 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC; k 1959 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 1960 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 1961 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 1962 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 1965 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height[k], k 1966 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height_chroma[k], k 1969 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height[k], k 1970 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height_chroma[k], k 1971 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_bw[k], k 1972 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_bw[k], k 1973 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.qual_row_bw[k]); k 1978 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1979 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 1980 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 1981 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 1984 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackPixelFormat[k], k 1985 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackHRatio[k], k 1986 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackVRatio[k], k 1987 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaHTaps[k], k 1988 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaVTaps[k], k 1989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaHTaps[k], k 1990 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaVTaps[k], k 1991 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDestinationWidth[k]) k 1994 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; k 1996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[j] == k k 1998 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2000 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k], k 2017 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2019 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == j) k 2020 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2024 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2025 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxVStartupLines[k] = k 2026 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] k 2030 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] k 2031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] k 2032 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]), k 2036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2039 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxVStartupLines[k]); k 2041 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2042 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.cursor_bw[k] = 0.0; k 2043 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j) k 2044 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j] k 2045 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.CursorBPP[k][j] / 8.0 k 2046 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 2047 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k]; k 2062 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2063 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2067 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 2068 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k], k 2070 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k], k 2072 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] k 2073 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k], k 2089 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ErrorResult[k] = k 2092 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPCLK[k], k 2094 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k], k 2096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelay[k], k 2097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPPerPlane[k], k 2098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ScalerEnabled[k], k 2099 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.NumberOfCursors[k], k 2106 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (unsigned int) (mode_lib->vba.SwathWidthY[k] k 2107 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.HRatio[k]), k 2108 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 2109 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTotal[k] k 2110 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.VActive[k], k 2111 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k], k 2115 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxVStartupLines[k]), k 2118 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataEnable[k], k 2119 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 2120 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 2121 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 2125 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k], k 2126 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MetaRowByte[k], k 2127 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelPTEBytesPerRow[k], k 2128 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchSourceLinesY[k], k 2129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k], k 2130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETY[k], k 2131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VInitPreFillY[k], k 2132 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxNumSwathY[k], k 2133 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchSourceLinesC[k], k 2134 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelDETC[k], k 2135 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VInitPreFillC[k], k 2136 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxNumSwathC[k], k 2137 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k], k 2138 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k], k 2140 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCEnabled[k], k 2142 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 2144 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DSTXAfterScaler[k], k 2145 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DSTYAfterScaler[k], k 2146 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesForPrefetch[k], k 2147 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PrefetchBandwidth[k], k 2148 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestVMInVBlank[k], k 2149 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestRowInVBlank[k], k 2150 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VRatioPrefetchY[k], k 2151 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VRatioPrefetchC[k], k 2152 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.RequiredPrefetchPixDataBWLuma[k], k 2154 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.Tno_bw[k], k 2155 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VUpdateOffsetPix[k], k 2156 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VUpdateWidthPix[k], k 2157 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VReadyOffsetPix[k]); k 2158 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2159 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VStartup[k] = dml_min( k 2161 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxVStartupLines[k]); k 2164 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VStartup[k] = k 2168 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VStartup[k] = k 2171 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); k 2175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0) k 2178 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k] = 0; k 2179 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) { k 2180 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k] = k 2181 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k] k 2182 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k] = 0; k 2189 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k] k 2191 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k] = 0; k 2192 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) { k 2193 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k] = k 2194 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (double) (mode_lib->vba.MetaRowByte[k] k 2195 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.PixelPTEBytesPerRow[k]) k 2196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] k 2197 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2200 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k] = 0; k 2205 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k] k 2207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k], k 2209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k], k 2211 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2212 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k], k 2213 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]) k 2214 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.meta_row_bw[k] k 2215 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.dpte_row_bw[k])); k 2217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2) k 2219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatioPrefetchY[k] > 4 k 2220 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VRatioPrefetchC[k] > 4) k 2240 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2243 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.cursor_bw[k] k 2245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 2247 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.qual_row_bw[k], k 2248 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchBandwidth[k]); k 2251 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2252 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c ImmediateFlipBytes[k] = 0; k 2253 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 2254 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 2255 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c ImmediateFlipBytes[k] = k 2256 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k] k 2257 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.MetaRowByte[k] k 2258 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.PixelPTEBytesPerRow[k]; k 2262 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2263 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 2264 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 2267 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + ImmediateFlipBytes[k]; k 2270 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2279 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 2280 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c ImmediateFlipBytes[k], k 2281 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] k 2282 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k], k 2283 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 2284 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Tno_bw[k], k 2285 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k], k 2286 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MetaRowByte[k], k 2287 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelPTEBytesPerRow[k], k 2288 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 2289 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height[k], k 2290 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height[k], k 2291 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.qual_row_bw[k], k 2292 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], k 2293 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], k 2294 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &final_flip_bw[k], k 2295 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); k 2297 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2300 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.cursor_bw[k] k 2302 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k], k 2304 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k], k 2305 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c final_flip_bw[k] k 2307 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2308 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ReadBandwidthPlaneChroma[k], k 2309 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]))); k 2315 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2316 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { k 2324 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ErrorResult[k]) { k 2339 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2340 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatioPrefetchY[k] <= 1) { k 2341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = k 2342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k] k 2343 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.HRatio[k] k 2344 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 2346 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = k 2347 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] k 2348 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 2349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPCLK[k]; k 2351 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] == 0) { k 2352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; k 2354 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatioPrefetchC[k] <= 1) { k 2355 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 2356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] k 2357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.DPPPerPlane[k] k 2358 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.HRatio[k] k 2359 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 2361 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 2362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k] k 2363 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 2364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.DPPCLK[k]; k 2370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2372 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true; k 2373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MinTTUVBlank[k] = dml_max( k 2380 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; k 2381 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2382 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MinTTUVBlank[k] = dml_max( k 2386 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; k 2387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false; k 2388 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark; k 2390 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (!mode_lib->vba.DynamicMetadataEnable[k]) k 2391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc k 2392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.MinTTUVBlank[k]; k 2398 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2399 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; k 2402 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.LBBitPerPixel[k] k 2417 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.SwathWidthY[k] k 2419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k], k 2421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 1)) - (mode_lib->vba.vtaps[k] - 1); k 2428 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.LBBitPerPixel[k] k 2429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.SwathWidthY[k] k 2432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 2436 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - (mode_lib->vba.VTAPsChroma[k] - 1); k 2439 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.VRatio[k] k 2440 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); k 2443 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.VRatio[k] / 2) k 2444 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); k 2446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) { k 2448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.SwathWidthY[k]; k 2449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) { k 2455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) { k 2457 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.SwathWidthY[k] / 2); k 2458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) { k 2464 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 2466 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k] k 2467 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + (mode_lib->vba.LinesInDETY[k] k 2468 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.LinesInDETYRoundedDownToSwath[k]) k 2469 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.SwathHeightY[k] k 2470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 2471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2480 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.SwathHeightY[k] k 2481 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 2482 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2485 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 2486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c double DPPOPPBufferingC = (mode_lib->vba.HTotal[k] k 2487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) k 2491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.FullDETBufferingTimeC[k] k 2492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + (mode_lib->vba.LinesInDETC[k] k 2493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.LinesInDETCRoundedDownToSwath[k]) k 2494 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.SwathHeightC[k] k 2495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 2496 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2508 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.SwathHeightC[k] k 2509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] k 2510 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]); k 2512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 2516 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = k 2520 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k]) { k 2523 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 2527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 2529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 2530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) k 2534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 2542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 2544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 2545 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2546 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k])) k 2554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2555 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 2556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 2557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2558 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k])) k 2561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 2562 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], k 2568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] k 2572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; k 2586 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2587 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) { k 2596 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.soc.num_states; k++) k 2598 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0]; k 2601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2602 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2605 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset; k 2606 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth; k 2607 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset; k 2615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 2616 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthY[k], k 2617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 2618 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 2631 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = k 2634 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] k 2635 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]), k 2637 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCTransferDelay[k] = k 2640 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] k 2641 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]), k 2643 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCPrechargeDelay[k] = k 2648 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] k 2649 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]), k 2654 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2655 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) k 2656 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2657 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k] k 2669 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCPrefetchMargin[k] = k 2672 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2673 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) k 2674 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 2675 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]; k 2677 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0; k 2678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVupdateWidth[k] = 0; k 2679 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCSlaveVReadyOffset[k] = 0; k 2680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0; k 2681 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCPrechargeDelay[k] = 0; k 2682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCTransferDelay[k] = 0; k 2683 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCPrefetchMargin[k] = 0; k 2690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2691 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2692 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) k 2693 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; k 2703 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) { k 2705 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; k 2729 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int j, k; k 2731 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2734 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 2740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2743 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { k 2746 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2755 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2756 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2760 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2762 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2763 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2776 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2797 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2798 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2799 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2800 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2801 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 2802 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2803 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.SurfaceTiling[k] k 2805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2807 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2809 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2813 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2815 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 2817 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 2819 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 k 2820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] != dm_horz) { k 2827 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2830 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 2831 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2834 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 2835 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2845 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c SwathWidth = mode_lib->vba.ViewportWidth[k]; k 2847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c SwathWidth = mode_lib->vba.ViewportHeight[k]; k 2850 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ODMCombineEnabled[k] == true) { k 2854 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == j k 2863 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]); k 2865 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DPPPerPlane[k] == 0) k 2868 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k]; k 2876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2887 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2897 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; k 2898 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; k 2900 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; k 2901 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; k 2904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SwathHeightC[k] == 0) { k 2905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024; k 2906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeC[k] = 0; k 2907 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { k 2908 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte k 2910 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte k 2913 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte k 2915 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte k 3289 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c unsigned int j, k, m; k 3296 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3297 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ScalerEnabled[k] == false k 3298 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3299 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3300 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3301 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3302 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) k 3303 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.HRatio[k] != 1.0 k 3304 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.htaps[k] != 1.0 k 3305 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VRatio[k] != 1.0 k 3306 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.vtaps[k] != 1.0)) { k 3308 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 k 3309 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0 k 3310 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.htaps[k] > 1.0 k 3311 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.htaps[k] % 2) == 1) k 3312 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio k 3313 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio k 3314 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] k 3315 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] k 3316 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3317 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3318 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3319 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3320 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 k 3321 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.HRatio[k] / 2.0 k 3322 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.HTAPsChroma[k] k 3323 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VRatio[k] / 2.0 k 3324 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.VTAPsChroma[k]))) { k 3331 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3332 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] != dm_horz) k 3334 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d k 3335 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x k 3336 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d k 3337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t k 3338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x k 3339 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d k 3340 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x) k 3341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_64) k 3342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x k 3343 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8 k 3344 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] k 3346 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] k 3348 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl k 3349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3351 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && !((mode_lib->vba.SourcePixelFormat[k] k 3353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] k 3355 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] k 3359 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.DCCEnable[k] k 3361 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.DCCEnable[k] == true k 3362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.SurfaceTiling[k] k 3364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] k 3366 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] k 3373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 3375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 8.0; k 3376 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 0.0; k 3377 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 3378 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 4.0; k 3379 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 0.0; k 3380 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3381 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { k 3382 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 2.0; k 3383 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 0.0; k 3384 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { k 3385 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 1.0; k 3386 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 0.0; k 3387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 3388 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 1.0; k 3389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 2.0; k 3391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETY[k] = 4.0 / 3; k 3392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->BytePerPixelInDETC[k] = 8.0 / 3; k 3394 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3395 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; k 3397 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; k 3400 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3401 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0) k 3402 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; k 3403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0) k 3404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; k 3405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k]; k 3407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true k 3409 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 3412 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 3413 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 3414 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) * 4.0; k 3415 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.WritebackEnable[k] == true k 3416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3417 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3418 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 3419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 3420 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 3421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) * 3.0; k 3422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.WritebackEnable[k] == true) { k 3423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackDestinationHeight[k] k 3425 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.WritebackSourceHeight[k] k 3426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HTotal[k] k 3427 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k]) * 1.5; k 3429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WriteBandwidth[k] = 0.0; k 3433 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k] == true) { k 3496 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3498 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->WriteBandwidth[k] k 3506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->WriteBandwidth[k] k 3534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0) k 3537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ActiveWritebacksPerPlane[k] = 1; k 3540 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ActiveWritebacksPerPlane[k]; k 3547 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3548 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true k 3550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3558 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.WritebackHRatio[k] != 1.0 k 3561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackVRatio[k] != 1.0)) { k 3564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio k 3565 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackVRatio[k] k 3567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackHRatio[k] k 3569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackVRatio[k] k 3571 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackLumaHTaps[k] k 3573 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackLumaVTaps[k] k 3575 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackHRatio[k] k 3576 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.WritebackLumaHTaps[k] k 3577 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackVRatio[k] k 3578 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.WritebackLumaVTaps[k] k 3579 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackLumaHTaps[k] > 2.0 k 3580 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && ((mode_lib->vba.WritebackLumaHTaps[k] % 2) k 3582 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32 k 3583 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.WritebackChromaHTaps[k] k 3585 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.WritebackChromaVTaps[k] k 3588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackHRatio[k] k 3589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.WritebackChromaHTaps[k] k 3591 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.WritebackVRatio[k] k 3592 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > mode_lib->vba.WritebackChromaVTaps[k] k 3593 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackChromaHTaps[k] > 2.0 k 3594 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) { k 3597 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackVRatio[k] < 1.0) { k 3599 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0); k 3603 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32 k 3604 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackLumaVTaps[k] k 3608 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.WritebackDestinationWidth[k] k 3610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackLumaVTaps[k] k 3613 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3616 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackLumaVTaps[k] k 3619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.WritebackDestinationWidth[k] k 3623 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) { k 3628 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3629 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackChromaVTaps[k] k 3631 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3633 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3634 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.WritebackChromaVTaps[k] k 3637 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.WritebackDestinationWidth[k] k 3646 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3647 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3652 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackPixelFormat[k], k 3653 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k], k 3654 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackHRatio[k], k 3655 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackVRatio[k], k 3656 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaHTaps[k], k 3657 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaVTaps[k], k 3658 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaHTaps[k], k 3659 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaVTaps[k], k 3660 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDestinationWidth[k], k 3661 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k], k 3665 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3666 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.HRatio[k] > 1.0) { k 3667 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR[k] = dml_min( k 3670 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 3672 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.htaps[k] k 3676 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR[k] = dml_min( k 3680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3681 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR_CHROMA[k] = 0.0; k 3682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] = k 3683 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 3685 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.vtaps[k] / 6.0 k 3688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k]), k 3689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 3690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] k 3691 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / locals->PSCL_FACTOR[k], k 3693 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0) k 3694 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && locals->MinDPPCLKUsingSingleDPP[k] k 3695 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3696 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3697 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k]; k 3700 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) { k 3701 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR_CHROMA[k] = k 3705 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 3708 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTAPsChroma[k] k 3712 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR_CHROMA[k] = dml_min( k 3716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] = k 3717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 3719 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.vtaps[k] / 6.0 k 3722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k]), k 3723 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 3724 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] k 3725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / locals->PSCL_FACTOR[k], k 3726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTAPsChroma[k] k 3730 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 3732 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 3733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.VRatio[k] k 3735 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / locals->PSCL_FACTOR_CHROMA[k], k 3737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0 k 3738 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.HTAPsChroma[k] > 6.0 k 3739 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.VTAPsChroma[k] > 6.0) k 3740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && locals->MinDPPCLKUsingSingleDPP[k] k 3741 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3743 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k]; k 3747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3749 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 3750 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 3751 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 3752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETC[k], 2.0), k 3753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &locals->Read256BlockHeightY[k], k 3754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &locals->Read256BlockHeightC[k], k 3755 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &locals->Read256BlockWidthY[k], k 3756 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &locals->Read256BlockWidthC[k]); k 3757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k]; k 3759 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k]; k 3761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k]; k 3762 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k]; k 3764 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3765 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 3766 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3767 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16 k 3768 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) { k 3769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && (mode_lib->vba.SurfaceTiling[k] k 3773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3783 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.SurfaceTiling[k] k 3785 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 3786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3788 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3791 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3793 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3794 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3795 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3796 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 3797 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3798 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3800 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3801 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 3802 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3803 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k] k 3805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3807 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3808 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (locals->BytePerPixelInDETY[k] k 3821 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * locals->MinSwathHeightY[k] k 3822 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + locals->BytePerPixelInDETC[k] k 3824 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * locals->MinSwathHeightC[k])); k 3825 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3828 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * dml_max(mode_lib->vba.HRatio[k], 1.0) k 3829 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.LBBitPerPixel[k] k 3830 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.vtaps[k] k 3833 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 3842 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k], k 3844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.LBBitPerPixel[k] k 3845 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.vtaps[k] k 3848 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 3854 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HRatio[k] k 3857 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.LBBitPerPixel[k] k 3858 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.VTAPsChroma[k] k 3861 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k] k 3867 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaximumSwathWidth[k] = dml_min( k 3881 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3883 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3887 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k] k 3890 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3894 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3897 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ODMCombineEnablePerState[i][k] = false; k 3900 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ODMCombineEnablePerState[i][k] = true; k 3903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity k 3904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k] k 3905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && locals->ODMCombineEnablePerState[i][k] == false) { k 3906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->NoOfDPP[i][j][k] = 1; k 3907 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiredDPPCLK[i][j][k] = k 3908 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); k 3910 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->NoOfDPP[i][j][k] = 2; k 3911 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiredDPPCLK[i][j][k] = k 3912 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; k 3917 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3924 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 3925 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 3934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 3935 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) { k 3936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k]; k 3937 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c NumberOfNonSplitPlaneOfMaximumBandwidth = k; k 3950 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3951 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ODMCombineEnablePerState[i][k] = false; k 3952 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { k 3953 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->NoOfDPP[i][j][k] = 1; k 3954 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 3957 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->NoOfDPP[i][j][k] = 2; k 3958 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 3963 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] k 3967 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k] k 3973 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3979 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 3980 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 3995 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 3997 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) k 3998 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c > locals->MaximumSwathWidth[k]) { k 4002 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) { k 4021 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4022 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4035 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4036 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 k 4037 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 k 4038 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) { k 4043 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4044 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = 0; k 4045 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = 0; k 4046 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4047 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Output[k] == dm_hdmi) { k 4048 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = 0; k 4049 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = 0; k 4050 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[i][k] = TruncToValidBPP( k 4051 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, k 4053 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4054 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4055 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4056 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.Output[k] == dm_dp k 4057 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.Output[k] == dm_edp) { k 4058 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Output[k] == dm_edp) { k 4067 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4069 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4070 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4071 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4074 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4076 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4077 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4078 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4079 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4080 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = true; k 4081 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Output[k] == dm_dp) { k 4082 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = true; k 4084 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4088 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = false; k 4089 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4091 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4099 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4100 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4103 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4105 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4106 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4107 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4108 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4109 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = true; k 4110 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Output[k] == dm_dp) { k 4111 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = true; k 4113 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4117 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = false; k 4118 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4120 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4127 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4134 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4136 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Output[k], k 4137 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4138 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4139 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { k 4140 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = true; k 4141 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.Output[k] == dm_dp) { k 4142 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = true; k 4144 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4148 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[i][k] = false; k 4149 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresFEC[i][k] = false; k 4151 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[i][k] = k 4156 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE; k 4162 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4163 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->OutputBppPerState[i][k] == BPP_INVALID k 4164 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.OutputFormat[k] == dm_420 k 4165 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.Interlace[k] == true k 4172 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4174 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.Output[k] == dm_dp k 4176 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.Output[k] == dm_edp)) { k 4177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 4178 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.OutputFormat[k] k 4184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->RequiresDSC[i][k] == true) { k 4185 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ODMCombineEnablePerState[i][k] k 4187 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor k 4193 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor k 4207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->RequiresDSC[i][k] == true) { k 4209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4225 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4226 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] != k) { k 4228 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (locals->RequiresDSC[i][k] == 0 k 4229 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->RequiresDSC[i][k] == false) { k 4231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { k 4233 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClockBackEnd[k] / 400.0, k 4235 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { k 4237 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { k 4239 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { k 4244 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE k 4245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->OutputBppPerState[i][k] == BPP_INVALID) { k 4248 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.bpp = locals->OutputBppPerState[i][k]; k 4250 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) { k 4251 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ODMCombineEnablePerState[i][k] == false) { k 4252 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] = k 4254 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k], k 4257 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HActive[k] k 4261 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]) k 4263 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]); k 4265 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] = k 4267 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCInputBitPerComponent[k], k 4269 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), k 4271 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k]) k 4272 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + dscComputeDelay(mode_lib->vba.OutputFormat[k])); k 4274 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] = k 4275 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k]; k 4277 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] = 0.0; k 4280 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4283 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true) k 4284 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m]; k 4293 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4294 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->ODMCombineEnablePerState[i][k] == true) k 4295 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); k 4297 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; k 4298 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; k 4299 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) k 4300 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; k 4301 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->SourcePixelFormat[k] == dm_420_10) { k 4304 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->MaxSwathHeightC[k] > 0) { k 4305 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k]; k 4307 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC) k 4308 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k]; k 4310 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->SourcePixelFormat[k] == dm_420_10) { k 4317 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; k 4318 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; k 4320 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; k 4321 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; k 4324 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->BytePerPixelInDETC[k] == 0) { k 4325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; k 4327 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c } else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) { k 4328 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] / k 4329 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYPerState[i][j][k]; k 4330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); k 4332 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; k 4333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); k 4337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] k 4338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); k 4341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] k 4342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (locals->SwathWidthYPerState[i][j][k] / 2 k 4343 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); k 4346 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * k 4347 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i], k 4349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightYPerState[i][j][k]); k 4352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] * k 4353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i], k 4355 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightCPerState[i][j][k]); k 4357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->BytePerPixelInDETC[k] == 0) { k 4358 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) k 4359 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * k 4360 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]); k 4362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min( k 4363 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) k 4364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * k 4365 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]), k 4366 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) - k 4367 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 * k 4368 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k])); k 4377 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4378 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency) k 4389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4390 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->DCCEnable[k] == true) { k 4392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4402 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k]; k 4404 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k]; k 4405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k]; k 4406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k]; k 4407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k]; k 4410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k] / 16.0); k 4411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) { k 4412 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatio[k] <= 1.0) { k 4418 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETY[k], k 4421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 4422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k] k 4423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4430 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETY[k], k 4433 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PSCL_FACTOR[k] k 4434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4437 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatio[k] <= 1.0) { k 4443 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETY[k], k 4446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 4447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k] k 4448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETY[k], k 4458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PSCL_FACTOR[k] k 4459 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) { k 4467 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETC[k], k 4470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.HRatio[k] k 4472 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PixelClock[k] k 4473 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4480 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETC[k], k 4483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.PSCL_FACTOR_CHROMA[k] k 4484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 4492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Read256BlockHeightY[k], k 4493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Read256BlockWidthY[k], k 4494 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 4495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 4496 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), k 4497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourceScan[k], k 4498 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k], k 4499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportHeight[k], k 4500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthYPerState[i][j][k], k 4505 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PitchY[k], k 4506 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCMetaPitchY[k], k 4507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MacroTileWidthY[k], k 4510 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k], k 4511 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_height[k], k 4512 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_height[k]); k 4513 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines( k 4515 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 4516 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.vtaps[k], k 4517 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 4519 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightYPerState[i][j][k], k 4520 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportYStartY[k], k 4521 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PrefillY[k], k 4522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MaxNumSwY[k]); k 4523 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 4524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 4525 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 4526 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 4527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) { k 4530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 4531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Read256BlockHeightY[k], k 4532 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Read256BlockWidthY[k], k 4533 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 4534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SurfaceTiling[k], k 4535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), k 4536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourceScan[k], k 4537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k] / 2.0, k 4538 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportHeight[k] / 2.0, k 4539 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, k 4544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PitchC[k], k 4546 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MacroTileWidthC[k], k 4549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k], k 4550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_height_chroma[k], k 4551 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_height_chroma[k]); k 4552 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines( k 4554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k] / 2.0, k 4555 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTAPsChroma[k], k 4556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 4558 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightCPerState[i][j][k], k 4559 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportYStartC[k], k 4560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PrefillC[k], k 4561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.MaxNumSwC[k]); k 4566 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PrefetchLinesC[k] = 0.0; k 4567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PTEBufferSizeNotExceededC[i][j][k] = true; k 4570 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->PDEAndMetaPTEBytesPerFrame[k] = k 4572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC; k 4573 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC; k 4577 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 4578 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 4579 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 4580 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4583 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height[k], k 4584 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height_chroma[k], k 4587 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height[k], k 4588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height_chroma[k], k 4589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.meta_row_bw[k], k 4590 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.dpte_row_bw[k], k 4591 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.qual_row_bw[k]); k 4609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.WritebackEnable[k] == true) { k 4612 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency k 4614 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackPixelFormat[k], k 4615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackHRatio[k], k 4616 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackVRatio[k], k 4617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaHTaps[k], k 4618 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackLumaVTaps[k], k 4619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaHTaps[k], k 4620 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackChromaVTaps[k], k 4621 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; k 4623 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WritebackDelay[i][k] = 0.0; k 4626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[m] == k k 4629 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k], k 4643 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4645 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == m) { k 4646 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m]; k 4650 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4651 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (m = 0; m < locals->NumberOfCursors[k]; m++) k 4652 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m] k 4653 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k]; k 4656 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4657 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] k 4658 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)); k 4671 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4673 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.XFCEnabled[k] == true) { k 4677 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 4678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->SwathWidthYPerState[i][j][k], k 4679 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 4680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4696 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.IsErrorResult[i][j][k] = k 4699 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.RequiredDPPCLK[i][j][k], k 4701 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PixelClock[k], k 4703 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCDelayPerState[i][k], k 4704 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.NoOfDPP[i][j][k], k 4705 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ScalerEnabled[k], k 4706 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.NumberOfCursors[k], k 4713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthYPerState[i][j][k] k 4714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.HRatio[k], k 4715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputFormat[k], k 4716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VTotal[k] k 4717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.VActive[k], k 4718 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k], k 4720 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaximumVStartup[k], k 4723 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataEnable[k], k 4724 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 4725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 4726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 4730 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], k 4731 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MetaRowBytes[k], k 4732 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPTEBytesPerRow[k], k 4733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchLinesY[k], k 4734 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathWidthYPerState[i][j][k], k 4735 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETY[k], k 4736 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefillY[k], k 4737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxNumSwY[k], k 4738 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchLinesC[k], k 4739 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.BytePerPixelInDETC[k], k 4740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefillC[k], k 4741 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxNumSwC[k], k 4742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightYPerState[i][j][k], k 4743 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SwathHeightCPerState[i][j][k], k 4745 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.XFCEnabled[k], k 4747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Interlace[k], k 4751 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.LineTimesForPrefetch[k], k 4752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.PrefetchBW[k], k 4753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.LinesForMetaPTE[k], k 4754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.LinesForMetaAndDPTERow[k], k 4755 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VRatioPreY[i][j][k], k 4756 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VRatioPreC[i][j][k], k 4757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k], k 4759 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.Tno_bw[k], k 4760 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VUpdateOffsetPix[k], k 4761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VUpdateWidthPix[k], k 4762 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.VReadyOffsetPix[k]); k 4768 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->PDEAndMetaPTEBytesPerFrame[k] == 0) k 4770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_vm_bw[k] = 0; k 4771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c else if (locals->LinesForMetaPTE[k] > 0) k 4772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[k] k 4773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]); k 4775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_vm_bw[k] = 0; k 4778 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k] == 0) k 4779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_row_bw[k] = 0; k 4780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c else if (locals->LinesForMetaAndDPTERow[k] > 0) k 4781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_row_bw[k] = (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k]) k 4782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]); k 4784 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->prefetch_row_bw[k] = 0; k 4789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]; k 4792 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.cursor_bw[k] k 4794 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k], k 4795 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k], k 4796 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_max(mode_lib->vba.ReadBandwidth[k], k 4797 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]) k 4798 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]); k 4809 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4810 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->LineTimesForPrefetch[k] < 2.0 k 4811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->LinesForMetaPTE[k] >= 8.0 k 4812 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->LinesForMetaAndDPTERow[k] >= 16.0 k 4813 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4818 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4819 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->VRatioPreY[i][j][k] > 4.0 k 4820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->VRatioPreC[i][j][k] > 4.0 k 4821 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4832 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4835 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c - mode_lib->vba.cursor_bw[k] k 4837 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k], k 4838 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PrefetchBW[k]); k 4840 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4841 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ImmediateFlipBytes[k] = 0.0; k 4842 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 4843 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 4844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ImmediateFlipBytes[k] = k 4845 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k] k 4846 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.MetaRowBytes[k] k 4847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.DPTEBytesPerRow[k]; k 4851 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4852 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 4853 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 4856 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.ImmediateFlipBytes[k]; k 4860 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4869 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.SourcePixelFormat[k], k 4870 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ImmediateFlipBytes[k], k 4871 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.HTotal[k] k 4872 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.PixelClock[k], k 4873 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.VRatio[k], k 4874 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.Tno_bw[k], k 4875 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], k 4876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MetaRowBytes[k], k 4877 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPTEBytesPerRow[k], k 4878 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCEnable[k], k 4879 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.dpte_row_height[k], k 4880 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.meta_row_height[k], k 4881 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.qual_row_bw[k], k 4882 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], k 4883 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], k 4884 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.final_flip_bw[k], k 4885 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); k 4888 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4891 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c + mode_lib->vba.cursor_bw[k] k 4893 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_vm_bw[k], k 4894 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.prefetch_row_bw[k], k 4895 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.final_flip_bw[k] k 4897 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ReadBandwidth[k], k 4898 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])); k 4905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { k 4918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) k 4919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.MaxTotalVActiveRDBandwidth = mode_lib->vba.MaxTotalVActiveRDBandwidth + mode_lib->vba.ReadBandwidth[k]; k 4935 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->PTEBufferSizeNotExceededY[i][j][k] == false k 4937 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || locals->PTEBufferSizeNotExceededC[i][j][k] == false) { k 4945 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4947 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.CursorWidth[k][j] > 0.0) { k 4953 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / (mode_lib->vba.CursorWidth[k][j] k 4954 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * mode_lib->vba.CursorBPP[k][j] k 4957 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 4958 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c / mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly k 4959 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c || (mode_lib->vba.CursorBPP[k][j] == 64.0 k 4969 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4970 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->AlignedYPitch[k] = dml_ceil( k 4971 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]), k 4972 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MacroTileWidthY[k]); k 4973 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) { k 4976 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.DCCEnable[k] == true) { k 4977 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->AlignedDCCMetaPitch[k] = dml_ceil( k 4979 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DCCMetaPitchY[k], k 4980 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k]), k 4981 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 64.0 * locals->Read256BlockWidthY[k]); k 4983 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k]; k 4985 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) { k 4988 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 4989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 4990 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 4991 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 4992 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { k 4993 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->AlignedCPitch[k] = dml_ceil( k 4995 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.PitchC[k], k 4996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ViewportWidth[k] / 2.0), k 4997 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->MacroTileWidthC[k]); k 4999 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k]; k 5001 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) { k 5080 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5081 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5082 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5093 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5094 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 5095 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ODMCombineEnabled[k] = k 5096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; k 5098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.ODMCombineEnabled[k] = 0; k 5100 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.DSCEnabled[k] = k 5101 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; k 5102 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c mode_lib->vba.OutputBpp[k] = k 5103 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k]; k 1146 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int j, k; k 1155 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1156 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k]) { k 1161 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackPixelFormat[k], k 1162 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k], k 1163 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackHRatio[k], k 1164 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackVRatio[k], k 1165 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaHTaps[k], k 1166 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaVTaps[k], k 1167 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaHTaps[k], k 1168 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaVTaps[k], k 1169 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDestinationWidth[k], k 1170 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k], k 1175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1176 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.HRatio[k] > 1) { k 1177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1180 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 1182 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.htaps[k] k 1186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1192 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 1194 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.vtaps[k] / 6.0 k 1197 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k]), k 1199 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 1200 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] k 1201 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k], k 1204 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) k 1206 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c < 2 * mode_lib->vba.PixelClock[k]) { k 1207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k]; k 1210 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 1211 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 1212 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0; k 1213 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLKUsingSingleDPP[k] = k 1216 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.HRatio[k] > 1) { k 1217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = k 1221 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 1224 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTAPsChroma[k] k 1228 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min( k 1233 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 1235 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTAPsChroma[k] k 1239 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 1242 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 1243 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] k 1245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k], k 1248 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6) k 1250 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c < 2 * mode_lib->vba.PixelClock[k]) { k 1252 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k]; k 1255 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max( k 1261 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1262 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] != k) k 1264 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ODMCombineEnabled[k]) { k 1268 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] / 2 k 1278 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] / 2 k 1282 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1286 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 1296 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 1333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1334 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DPPPerPlane[k] == 0) { k 1335 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK_calculated[k] = 0; k 1337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k] k 1338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k] k 1343 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK_calculated[k]); k 1348 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255 k 1351 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK_calculated[k] * 255 k 1354 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]); k 1359 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 1360 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k]) k 1389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourceScan[k] == dm_horz) k 1393 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k]; k 1395 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k]; k 1397 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ODMCombineEnabled[k] == true) k 1400 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == j k 1405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] = dml_min( k 1406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.SwathWidthSingleDPPY[k], k 1408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HActive[k] / 2.0 k 1409 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k])); k 1411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DPPPerPlane[k] == 0) { k 1412 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] = 0; k 1414 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1415 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k]; k 1420 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 1422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 8; k 1423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 1425 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 4; k 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1427 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 1428 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 2; k 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1430 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { k 1431 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 1; k 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 0; k 1433 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 1434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 1; k 1435 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 2; k 1437 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0; k 1438 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0; k 1443 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1444 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1445 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) k 1446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k]; k 1448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k] k 1449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2) k 1450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1451 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] / 2; k 1454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c k, k 1455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1456 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k]); k 1457 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k]; k 1463 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.DPPPerPlane[k]; k 1466 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k]) k 1468 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.DPPPerPlane[k]; k 1478 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1479 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatio[k] <= 1.0) k 1480 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = k 1481 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.SwathWidthY[k] k 1482 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.DPPPerPlane[k] k 1483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.HRatio[k] k 1484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 1486 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] = k 1487 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.SwathWidthY[k] k 1488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 1489 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPCLK[k]; k 1491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] == 0) k 1492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0; k 1493 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) k 1494 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = k 1495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] / 2.0 k 1496 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.DPPPerPlane[k] k 1497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HRatio[k] / 2.0) k 1498 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 1500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = k 1501 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] / 2.0 k 1502 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] k 1503 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPCLK[k]; k 1526 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k]) k 1528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k]; k 1564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1565 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k] k 1566 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k]; k 1567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor( k 1568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETY[k], k 1569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k]); k 1570 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeY[k] = k 1571 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETYRoundedDownToSwath[k] k 1572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 1573 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) k 1574 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.VRatio[k]; k 1575 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1576 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k] k 1577 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.BytePerPixelDETC[k] k 1578 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.SwathWidthY[k] / 2); k 1579 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor( k 1580 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETC[k], k 1581 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k]); k 1582 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeC[k] = k 1583 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] k 1584 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 1585 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) k 1586 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.VRatio[k] / 2); k 1588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETC[k] = 0; k 1589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0; k 1590 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeC[k] = 999999; k 1595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1596 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.FullDETBufferingTimeY[k] k 1599 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeY[k]; k 1601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] k 1602 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 1604 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.FullDETBufferingTimeC[k] k 1607 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeC[k]; k 1609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] k 1610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 1615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1616 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k]) { k 1619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1620 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DCCRate[k] k 1622 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1623 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DCCRate[k] k 1628 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1630 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1633 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k]) { k 1636 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1638 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1644 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneLuma[k] k 1646 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 1675 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1677 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k] k 1678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k] k 1679 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 1697 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) { k 1698 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1699 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = k 1701 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 1.1 * mode_lib->vba.SwathWidthY[k] k 1703 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k], k 1705 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], k 1706 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 1.1 * mode_lib->vba.SwathWidthY[k] / 2.0 k 1708 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k], k 1710 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]); k 1712 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k] k 1713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0 k 1714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k]; k 1715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( k 1716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k], k 1717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] / 16.0); k 1720 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); k 1724 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c k, k 1725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); k 1742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1745 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETY[k] k 1747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETY[k] k 1748 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.DPPCLK[k] k 1749 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.BytePerPixelDETY[k] k 1750 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 1752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k]), k 1754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k]); k 1757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.VRatio[k] k 1760 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.SwathWidthY[k] k 1761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.BytePerPixelDETY[k] k 1763 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k]); k 1765 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 1768 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETC[k] k 1770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.LinesInDETC[k] k 1771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.DPPCLK[k] k 1772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.BytePerPixelDETC[k] k 1773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] k 1775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k]), k 1777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k]); k 1780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 1781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) k 1782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.VRatio[k] / 2) k 1784 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.SwathWidthY[k] k 1786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.BytePerPixelDETC[k] k 1788 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPPerPlane[k]); k 1789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.UrgentLatencySupportUs[k] = dml_min( k 1793 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.UrgentLatencySupportUs[k] = k 1799 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1802 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.UrgentLatencySupportUs[k]); k 1810 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { k 1812 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCCLK_calculated[k] = 0.0; k 1814 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 1815 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.OutputFormat[k] == dm_n422) k 1819 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ODMCombineEnabled[k]) k 1820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCCLK_calculated[k] = k 1821 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClockBackEnd[k] / 6 k 1827 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCCLK_calculated[k] = k 1828 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClockBackEnd[k] / 3 k 1838 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1839 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c double bpp = mode_lib->vba.OutputBpp[k]; k 1840 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; k 1842 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { k 1843 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCDelay[k] = k 1846 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k], k 1849 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.HActive[k] k 1850 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.NumberOfDSCSlices[k], k 1853 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]) k 1855 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]); k 1857 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCDelay[k] = k 1860 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k], k 1863 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.HActive[k] k 1864 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.NumberOfDSCSlices[k], k 1867 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]) k 1869 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k])); k 1871 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k] k 1872 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k] k 1873 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClockBackEnd[k]; k 1875 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCDelay[k] = 0; k 1879 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 1881 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (j != k && mode_lib->vba.BlendingAndTiming[k] == j k 1883 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j]; k 1886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1895 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 1896 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 1897 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 1898 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2), k 1899 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.BlockHeight256BytesY[k], k 1900 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.BlockHeight256BytesC[k], k 1901 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.BlockWidth256BytesY[k], k 1902 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.BlockWidth256BytesC[k]); k 1905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 1906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BlockHeight256BytesY[k], k 1907 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BlockWidth256BytesY[k], k 1908 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 1909 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 1910 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 1911 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourceScan[k], k 1912 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k], k 1913 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportHeight[k], k 1914 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k], k 1919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PitchY[k], k 1920 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCMetaPitchY[k], k 1921 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MacroTileWidthY[k], k 1925 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_height[k], k 1926 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_height[k]); k 1927 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( k 1929 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 1930 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.vtaps[k], k 1931 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 1933 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k], k 1934 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportYStartY[k], k 1935 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VInitPreFillY[k], k 1936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MaxNumSwathY[k]); k 1938 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 1939 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 1940 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 1941 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) { k 1945 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 1946 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BlockHeight256BytesC[k], k 1947 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BlockWidth256BytesC[k], k 1948 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 1949 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 1951 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k], k 1953 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourceScan[k], k 1954 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k] / 2, k 1955 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportHeight[k] / 2, k 1956 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] / 2, k 1961 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PitchC[k], k 1963 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MacroTileWidthC[k], k 1967 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_height_chroma[k], k 1968 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_height_chroma[k]); k 1969 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( k 1971 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k] / 2, k 1972 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTAPsChroma[k], k 1973 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 1975 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k], k 1976 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportYStartC[k], k 1977 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VInitPreFillC[k], k 1978 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MaxNumSwathC[k]); k 1983 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxNumSwathC[k] = 0; k 1984 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchSourceLinesC[k] = 0; k 1987 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; k 1988 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY k 1990 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC; k 1994 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 1995 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 1996 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 1997 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 2000 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height[k], k 2001 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height_chroma[k], k 2004 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height[k], k 2005 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height_chroma[k], k 2006 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_bw[k], k 2007 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_bw[k], k 2008 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.qual_row_bw[k]); k 2013 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2014 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2015 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 2016 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2019 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackPixelFormat[k], k 2020 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackHRatio[k], k 2021 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackVRatio[k], k 2022 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaHTaps[k], k 2023 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaVTaps[k], k 2024 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaHTaps[k], k 2025 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaVTaps[k], k 2026 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDestinationWidth[k]) k 2029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; k 2031 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[j] == k k 2033 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2035 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k], k 2052 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2054 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == j) k 2055 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2059 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2060 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxVStartupLines[k] = k 2061 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] k 2065 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] k 2066 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] k 2067 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]), k 2071 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2074 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxVStartupLines[k]); k 2076 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2077 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.cursor_bw[k] = 0.0; k 2078 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j) k 2079 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j] k 2080 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.CursorBPP[k][j] / 8.0 k 2081 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 2082 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k]; k 2097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2102 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 2103 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k], k 2105 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k], k 2107 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] k 2108 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k], k 2125 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth, k 2126 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], k 2127 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], k 2129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], k 2130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], k 2131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); k 2133 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ErrorResult[k] = k 2136 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPCLK[k], k 2138 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k], k 2140 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPPerPlane[k], k 2141 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.NumberOfCursors[k], k 2142 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTotal[k] k 2143 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.VActive[k], k 2144 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k], k 2148 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxVStartupLines[k]), k 2151 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataEnable[k], k 2152 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 2153 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 2154 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 2158 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k], k 2159 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MetaRowByte[k], k 2160 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelPTEBytesPerRow[k], k 2161 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchSourceLinesY[k], k 2162 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k], k 2163 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETY[k], k 2164 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VInitPreFillY[k], k 2165 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxNumSwathY[k], k 2166 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchSourceLinesC[k], k 2167 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelDETC[k], k 2168 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VInitPreFillC[k], k 2169 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxNumSwathC[k], k 2170 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k], k 2171 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k], k 2173 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCEnabled[k], k 2175 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 2177 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSTXAfterScaler[k], k 2178 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSTYAfterScaler[k], k 2179 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesForPrefetch[k], k 2180 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PrefetchBandwidth[k], k 2181 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestVMInVBlank[k], k 2182 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestRowInVBlank[k], k 2183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VRatioPrefetchY[k], k 2184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VRatioPrefetchC[k], k 2185 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.RequiredPrefetchPixDataBWLuma[k], k 2186 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.Tno_bw[k], k 2187 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VUpdateOffsetPix[k], k 2188 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VUpdateWidthPix[k], k 2189 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VReadyOffsetPix[k]); k 2191 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2192 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VStartup[k] = dml_min( k 2194 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxVStartupLines[k]); k 2197 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VStartup[k] = k 2201 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VStartup[k] = k 2204 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); k 2208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2210 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0) k 2211 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k] = 0; k 2212 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) { k 2213 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k] = k 2214 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k] k 2215 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2216 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k] = 0; k 2222 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k] k 2224 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k] = 0; k 2225 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) { k 2226 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k] = k 2227 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (double) (mode_lib->vba.MetaRowByte[k] k 2228 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.PixelPTEBytesPerRow[k]) k 2229 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] k 2230 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2233 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k] = 0; k 2238 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k] k 2240 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k], k 2242 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k], k 2244 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k], k 2246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]) k 2247 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.meta_row_bw[k] k 2248 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.dpte_row_bw[k])); k 2250 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2) k 2252 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatioPrefetchY[k] > 4 k 2253 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VRatioPrefetchC[k] > 4) k 2273 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2276 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.cursor_bw[k] k 2278 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2279 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k] k 2280 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.qual_row_bw[k], k 2281 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchBandwidth[k]); k 2284 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2285 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c ImmediateFlipBytes[k] = 0; k 2286 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 2287 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 2288 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c ImmediateFlipBytes[k] = k 2289 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k] k 2290 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.MetaRowByte[k] k 2291 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.PixelPTEBytesPerRow[k]; k 2295 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2296 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 2297 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 2300 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + ImmediateFlipBytes[k]; k 2303 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2312 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 2313 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c ImmediateFlipBytes[k], k 2314 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] k 2315 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k], k 2316 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 2317 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Tno_bw[k], k 2318 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesFrame[k], k 2319 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MetaRowByte[k], k 2320 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelPTEBytesPerRow[k], k 2321 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 2322 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height[k], k 2323 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height[k], k 2324 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.qual_row_bw[k], k 2325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], k 2326 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], k 2327 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &final_flip_bw[k], k 2328 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); k 2330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.cursor_bw[k] k 2335 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k], k 2337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k], k 2338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c final_flip_bw[k] k 2340 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidthPlaneLuma[k] k 2341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ReadBandwidthPlaneChroma[k], k 2342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredPrefetchPixDataBWLuma[k]))); k 2348 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { k 2357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2358 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ErrorResult[k]) { k 2372 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatioPrefetchY[k] <= 1) { k 2374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = k 2375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k] k 2376 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.HRatio[k] k 2377 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 2379 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = k 2380 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] k 2381 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 2382 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPCLK[k]; k 2384 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] == 0) { k 2385 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; k 2387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatioPrefetchC[k] <= 1) { k 2388 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 2389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] k 2390 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.DPPPerPlane[k] k 2391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.HRatio[k] k 2392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 2394 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 2395 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k] k 2396 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] k 2397 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.DPPCLK[k]; k 2403 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true; k 2406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MinTTUVBlank[k] = dml_max( k 2413 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; k 2414 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2415 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MinTTUVBlank[k] = dml_max( k 2419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false; k 2420 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false; k 2421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark; k 2423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (!mode_lib->vba.DynamicMetadataEnable[k]) k 2424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc k 2425 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.MinTTUVBlank[k]; k 2431 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k]; k 2435 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.LBBitPerPixel[k] k 2450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.SwathWidthY[k] k 2452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k], k 2454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 1)) - (mode_lib->vba.vtaps[k] - 1); k 2461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.LBBitPerPixel[k] k 2462 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.SwathWidthY[k] k 2465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 2469 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - (mode_lib->vba.VTAPsChroma[k] - 1); k 2472 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.VRatio[k] k 2473 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); k 2476 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.VRatio[k] / 2) k 2477 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]); k 2479 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) { k 2481 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.SwathWidthY[k]; k 2482 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) { k 2488 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) { k 2490 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.SwathWidthY[k] / 2); k 2491 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) { k 2497 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 2499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k] k 2500 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + (mode_lib->vba.LinesInDETY[k] k 2501 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.LinesInDETYRoundedDownToSwath[k]) k 2502 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.SwathHeightY[k] k 2503 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 2504 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2513 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.SwathHeightY[k] k 2514 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 2515 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2518 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelDETC[k] > 0) { k 2519 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c double DPPOPPBufferingC = (mode_lib->vba.HTotal[k] k 2520 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) k 2524 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.FullDETBufferingTimeC[k] k 2525 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + (mode_lib->vba.LinesInDETC[k] k 2526 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.LinesInDETCRoundedDownToSwath[k]) k 2527 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.SwathHeightC[k] k 2528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 2529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2541 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.SwathHeightC[k] k 2542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] k 2543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]); k 2545 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 2549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = k 2553 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k]) { k 2556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 2560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 2562 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 2563 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) k 2567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 2575 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2576 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 2577 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 2578 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2579 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k])) k 2587 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackDestinationWidth[k] k 2588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 2589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 2590 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2591 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k])) k 2594 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 2595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], k 2601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2602 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] k 2605 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; k 2618 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2619 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) { k 2628 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.soc.num_states; k++) k 2630 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0]; k 2633 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2634 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2637 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset; k 2638 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth; k 2639 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset; k 2647 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 2648 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthY[k], k 2649 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1), k 2650 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 2663 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = k 2666 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] k 2667 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]), k 2669 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCTransferDelay[k] = k 2672 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] k 2673 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]), k 2675 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCPrechargeDelay[k] = k 2680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] k 2681 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]), k 2686 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) k 2688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k] k 2701 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCPrefetchMargin[k] = k 2704 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] k 2705 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]) k 2706 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 2707 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]; k 2709 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0; k 2710 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVupdateWidth[k] = 0; k 2711 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCSlaveVReadyOffset[k] = 0; k 2712 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0; k 2713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCPrechargeDelay[k] = 0; k 2714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCTransferDelay[k] = 0; k 2715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCPrefetchMargin[k] = 0; k 2722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2723 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2724 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k]) k 2725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]; k 2735 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) { k 2737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]; k 2761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int j, k; k 2763 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2766 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 2772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { k 2778 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2787 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2788 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2790 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2792 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2794 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2795 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2808 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2821 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2829 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2830 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2831 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2832 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2833 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 2834 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2835 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.SurfaceTiling[k] k 2837 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2839 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2841 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2843 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2845 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 2849 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 2851 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 k 2852 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] != dm_horz) { k 2859 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2862 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 2863 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2866 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 2867 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2877 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c SwathWidth = mode_lib->vba.ViewportWidth[k]; k 2879 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c SwathWidth = mode_lib->vba.ViewportHeight[k]; k 2882 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ODMCombineEnabled[k] == true) { k 2886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == j k 2895 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]); k 2897 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DPPPerPlane[k] == 0) k 2900 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k]; k 2908 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2929 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; k 2930 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; k 2932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; k 2933 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; k 2936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SwathHeightC[k] == 0) { k 2937 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024; k 2938 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeC[k] = 0; k 2939 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) { k 2940 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte k 2942 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte k 2945 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte k 2947 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte k 3321 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c unsigned int j, k, m; k 3328 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3329 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ScalerEnabled[k] == false k 3330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3331 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3332 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3334 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) k 3335 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.HRatio[k] != 1.0 k 3336 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.htaps[k] != 1.0 k 3337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VRatio[k] != 1.0 k 3338 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.vtaps[k] != 1.0)) { k 3340 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 k 3341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0 k 3342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.htaps[k] > 1.0 k 3343 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.htaps[k] % 2) == 1) k 3344 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio k 3345 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio k 3346 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] k 3347 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] k 3348 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3350 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3351 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 k 3353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.HRatio[k] / 2.0 k 3354 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.HTAPsChroma[k] k 3355 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VRatio[k] / 2.0 k 3356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.VTAPsChroma[k]))) { k 3363 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3365 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] != dm_horz) k 3366 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d k 3367 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x k 3368 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d k 3369 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t k 3370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x k 3371 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d k 3372 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x) k 3373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_64) k 3374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x k 3375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8 k 3376 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] k 3378 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] k 3380 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl k 3381 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3383 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && !((mode_lib->vba.SourcePixelFormat[k] k 3385 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] k 3387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] k 3391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.DCCEnable[k] k 3393 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.DCCEnable[k] == true k 3394 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.SurfaceTiling[k] k 3396 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] k 3398 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] k 3405 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3406 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 3407 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 8.0; k 3408 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 0.0; k 3409 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 3410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 4.0; k 3411 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 0.0; k 3412 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3413 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { k 3414 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 2.0; k 3415 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 0.0; k 3416 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { k 3417 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 1.0; k 3418 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 0.0; k 3419 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 3420 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 1.0; k 3421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 2.0; k 3423 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETY[k] = 4.0 / 3; k 3424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->BytePerPixelInDETC[k] = 8.0 / 3; k 3426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3427 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; k 3429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; k 3432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3433 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0) k 3434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; k 3435 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0) k 3436 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; k 3437 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k]; k 3439 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3440 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true k 3441 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3442 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3443 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 3444 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 3445 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 3446 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) * 4.0; k 3447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.WritebackEnable[k] == true k 3448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3450 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 3451 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 3452 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 3453 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) * 3.0; k 3454 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.WritebackEnable[k] == true) { k 3455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3456 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackDestinationHeight[k] k 3457 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.WritebackSourceHeight[k] k 3458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HTotal[k] k 3459 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k]) * 1.5; k 3461 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WriteBandwidth[k] = 0.0; k 3465 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3466 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k] == true) { k 3528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->WriteBandwidth[k] k 3538 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->WriteBandwidth[k] k 3566 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0) k 3569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ActiveWritebacksPerPlane[k] = 1; k 3572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ActiveWritebacksPerPlane[k]; k 3579 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3580 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true k 3582 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3590 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3592 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.WritebackHRatio[k] != 1.0 k 3593 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackVRatio[k] != 1.0)) { k 3596 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio k 3597 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackVRatio[k] k 3599 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackHRatio[k] k 3601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackVRatio[k] k 3603 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackLumaHTaps[k] k 3605 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackLumaVTaps[k] k 3607 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackHRatio[k] k 3608 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.WritebackLumaHTaps[k] k 3609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackVRatio[k] k 3610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.WritebackLumaVTaps[k] k 3611 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackLumaHTaps[k] > 2.0 k 3612 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && ((mode_lib->vba.WritebackLumaHTaps[k] % 2) k 3614 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32 k 3615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.WritebackChromaHTaps[k] k 3617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.WritebackChromaVTaps[k] k 3620 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackHRatio[k] k 3621 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.WritebackChromaHTaps[k] k 3623 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.WritebackVRatio[k] k 3624 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > mode_lib->vba.WritebackChromaVTaps[k] k 3625 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackChromaHTaps[k] > 2.0 k 3626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) { k 3629 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackVRatio[k] < 1.0) { k 3631 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0); k 3635 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32 k 3636 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackLumaVTaps[k] k 3640 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.WritebackDestinationWidth[k] k 3642 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3643 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackLumaVTaps[k] k 3645 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3647 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3648 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackLumaVTaps[k] k 3651 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.WritebackDestinationWidth[k] k 3655 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) { k 3660 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3661 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackChromaVTaps[k] k 3663 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3665 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3666 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.WritebackChromaVTaps[k] k 3669 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.WritebackDestinationWidth[k] k 3678 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3679 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3684 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackPixelFormat[k], k 3685 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k], k 3686 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackHRatio[k], k 3687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackVRatio[k], k 3688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaHTaps[k], k 3689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaVTaps[k], k 3690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaHTaps[k], k 3691 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaVTaps[k], k 3692 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDestinationWidth[k], k 3693 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k], k 3697 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3698 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.HRatio[k] > 1.0) { k 3699 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR[k] = dml_min( k 3702 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 3704 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.htaps[k] k 3708 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR[k] = dml_min( k 3712 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR_CHROMA[k] = 0.0; k 3714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] = k 3715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 3717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.vtaps[k] / 6.0 k 3720 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k]), k 3721 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 3722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] k 3723 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / locals->PSCL_FACTOR[k], k 3725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0) k 3726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && locals->MinDPPCLKUsingSingleDPP[k] k 3727 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3728 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3729 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k]; k 3732 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) { k 3733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR_CHROMA[k] = k 3737 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 3740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTAPsChroma[k] k 3744 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR_CHROMA[k] = dml_min( k 3748 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] = k 3749 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 3751 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.vtaps[k] / 6.0 k 3754 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k]), k 3755 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 3756 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] k 3757 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / locals->PSCL_FACTOR[k], k 3758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTAPsChroma[k] k 3762 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 3764 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 3765 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.VRatio[k] k 3767 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / locals->PSCL_FACTOR_CHROMA[k], k 3769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0 k 3770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.HTAPsChroma[k] > 6.0 k 3771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.VTAPsChroma[k] > 6.0) k 3772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && locals->MinDPPCLKUsingSingleDPP[k] k 3773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3774 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k]; k 3779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 3782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 3783 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 3784 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETC[k], 2.0), k 3785 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &locals->Read256BlockHeightY[k], k 3786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &locals->Read256BlockHeightC[k], k 3787 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &locals->Read256BlockWidthY[k], k 3788 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &locals->Read256BlockWidthC[k]); k 3789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3790 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k]; k 3791 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k]; k 3793 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k]; k 3794 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k]; k 3796 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3797 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 3798 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3799 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16 k 3800 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) { k 3801 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3802 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3803 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && (mode_lib->vba.SurfaceTiling[k] k 3805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3807 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3809 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3811 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3813 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3815 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.SurfaceTiling[k] k 3817 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 3818 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3820 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3823 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3825 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3826 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3827 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3828 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 3829 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3830 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3832 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3833 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 3834 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3835 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k] k 3837 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3839 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3840 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3843 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3852 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (locals->BytePerPixelInDETY[k] k 3853 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * locals->MinSwathHeightY[k] k 3854 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + locals->BytePerPixelInDETC[k] k 3856 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * locals->MinSwathHeightC[k])); k 3857 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3860 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * dml_max(mode_lib->vba.HRatio[k], 1.0) k 3861 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.LBBitPerPixel[k] k 3862 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.vtaps[k] k 3865 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 3874 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k], k 3876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.LBBitPerPixel[k] k 3877 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.vtaps[k] k 3880 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 3886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HRatio[k] k 3889 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.LBBitPerPixel[k] k 3890 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.VTAPsChroma[k] k 3893 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k] k 3899 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaximumSwathWidth[k] = dml_min( k 3913 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3915 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k] k 3922 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3926 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3929 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ODMCombineEnablePerState[i][k] = false; k 3932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ODMCombineEnablePerState[i][k] = true; k 3935 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity k 3936 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k] k 3937 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && locals->ODMCombineEnablePerState[i][k] == false) { k 3938 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->NoOfDPP[i][j][k] = 1; k 3939 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiredDPPCLK[i][j][k] = k 3940 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); k 3942 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->NoOfDPP[i][j][k] = 2; k 3943 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiredDPPCLK[i][j][k] = k 3944 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; k 3949 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3956 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 3957 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 3966 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 3967 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) { k 3968 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k]; k 3969 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c NumberOfNonSplitPlaneOfMaximumBandwidth = k; k 3982 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3983 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ODMCombineEnablePerState[i][k] = false; k 3984 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { k 3985 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->NoOfDPP[i][j][k] = 1; k 3986 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 3989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->NoOfDPP[i][j][k] = 2; k 3990 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 3995 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] k 3999 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k] k 4005 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 4011 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 4012 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4027 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4028 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4029 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) k 4030 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c > locals->MaximumSwathWidth[k]) { k 4034 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) { k 4053 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4054 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4067 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4068 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 k 4069 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 k 4070 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) { k 4075 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4076 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = 0; k 4077 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = 0; k 4078 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4079 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Output[k] == dm_hdmi) { k 4080 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = 0; k 4081 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = 0; k 4082 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[i][k] = TruncToValidBPP( k 4083 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, k 4085 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4086 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4087 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4088 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.Output[k] == dm_dp k 4089 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.Output[k] == dm_edp) { k 4090 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Output[k] == dm_edp) { k 4099 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4101 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4102 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4103 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4106 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4108 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4109 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4110 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4111 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4112 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = true; k 4113 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Output[k] == dm_dp) { k 4114 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = true; k 4116 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4120 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = false; k 4121 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4123 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4128 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4130 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4132 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4135 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4137 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4138 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4139 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4140 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4141 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = true; k 4142 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Output[k] == dm_dp) { k 4143 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = true; k 4145 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4149 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = false; k 4150 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4152 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4159 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4161 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4162 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4163 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4166 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4168 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Output[k], k 4169 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k], k 4170 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4171 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { k 4172 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = true; k 4173 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.Output[k] == dm_dp) { k 4174 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = true; k 4176 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4180 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[i][k] = false; k 4181 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresFEC[i][k] = false; k 4183 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[i][k] = k 4188 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE; k 4194 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4195 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->OutputBppPerState[i][k] == BPP_INVALID k 4196 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.OutputFormat[k] == dm_420 k 4197 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.Interlace[k] == true k 4204 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4206 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4207 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.Output[k] == dm_dp k 4208 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.Output[k] == dm_edp)) { k 4209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 4210 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.OutputFormat[k] k 4216 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->RequiresDSC[i][k] == true) { k 4217 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ODMCombineEnablePerState[i][k] k 4219 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor k 4225 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor k 4239 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4240 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->RequiresDSC[i][k] == true) { k 4241 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4257 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4258 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] != k) { k 4260 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (locals->RequiresDSC[i][k] == 0 k 4261 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->RequiresDSC[i][k] == false) { k 4263 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { k 4265 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClockBackEnd[k] / 400.0, k 4267 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { k 4269 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { k 4271 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { k 4276 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE k 4277 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->OutputBppPerState[i][k] == BPP_INVALID) { k 4280 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.bpp = locals->OutputBppPerState[i][k]; k 4282 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) { k 4283 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ODMCombineEnablePerState[i][k] == false) { k 4284 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] = k 4286 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k], k 4289 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HActive[k] k 4293 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]) k 4295 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]); k 4297 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] = k 4299 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCInputBitPerComponent[k], k 4301 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), k 4303 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputFormat[k]) k 4304 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + dscComputeDelay(mode_lib->vba.OutputFormat[k])); k 4306 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] = k 4307 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k]; k 4309 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] = 0.0; k 4312 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4315 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true) k 4316 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m]; k 4325 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4326 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->ODMCombineEnablePerState[i][k] == true) k 4327 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k])); k 4329 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; k 4330 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthGranularityY = 256 / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k]; k 4331 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY) k 4332 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; k 4333 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->SourcePixelFormat[k] == dm_420_10) { k 4336 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->MaxSwathHeightC[k] > 0) { k 4337 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k]; k 4339 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC) k 4340 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k]; k 4342 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->SourcePixelFormat[k] == dm_420_10) { k 4349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k]; k 4350 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k]; k 4352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k]; k 4353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k]; k 4356 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->BytePerPixelInDETC[k] == 0) { k 4357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; k 4359 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c } else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) { k 4360 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] / k 4361 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYPerState[i][j][k]; k 4362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2); k 4364 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k]; k 4365 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2); k 4369 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k] k 4370 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1); k 4373 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] k 4374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (locals->SwathWidthYPerState[i][j][k] / 2 k 4375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1); k 4378 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] * k 4379 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i], k 4381 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightYPerState[i][j][k]); k 4384 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] * k 4385 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i], k 4387 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightCPerState[i][j][k]); k 4389 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->BytePerPixelInDETC[k] == 0) { k 4390 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) k 4391 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * k 4392 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]); k 4394 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min( k 4395 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k]) k 4396 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] * k 4397 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]), k 4398 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) - k 4399 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 * k 4400 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k])); k 4409 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4410 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency) k 4421 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4422 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->DCCEnable[k] == true) { k 4424 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4433 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4434 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k]; k 4439 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k < locals->NumberOfActivePlanes; k++) { k 4440 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k]; k 4441 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k]; k 4442 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k]; k 4443 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k]; k 4444 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k]; k 4447 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k] / 16.0); k 4448 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) { k 4449 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatio[k] <= 1.0) { k 4455 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETY[k], k 4458 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 4459 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k] k 4460 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4467 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETY[k], k 4470 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PSCL_FACTOR[k] k 4471 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4474 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatio[k] <= 1.0) { k 4480 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETY[k], k 4483 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 4484 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k] k 4485 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4492 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETY[k], k 4495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PSCL_FACTOR[k] k 4496 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4498 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) { k 4504 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETC[k], k 4507 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.HRatio[k] k 4509 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PixelClock[k] k 4510 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.NoOfDPP[i][j][k]); k 4517 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETC[k], k 4520 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.PSCL_FACTOR_CHROMA[k] k 4521 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.RequiredDPPCLK[i][j][k]); k 4525 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4528 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 4529 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Read256BlockHeightY[k], k 4530 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Read256BlockWidthY[k], k 4531 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 4532 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 4533 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0), k 4534 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourceScan[k], k 4535 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k], k 4536 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportHeight[k], k 4537 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthYPerState[i][j][k], k 4542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PitchY[k], k 4543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCMetaPitchY[k], k 4544 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MacroTileWidthY[k], k 4547 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k], k 4548 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_height[k], k 4549 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_height[k]); k 4550 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines( k 4552 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 4553 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.vtaps[k], k 4554 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 4556 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightYPerState[i][j][k], k 4557 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportYStartY[k], k 4558 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PrefillY[k], k 4559 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MaxNumSwY[k]); k 4560 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 4561 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 4562 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 4563 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 4564 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) { k 4567 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 4568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Read256BlockHeightY[k], k 4569 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Read256BlockWidthY[k], k 4570 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 4571 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SurfaceTiling[k], k 4572 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0), k 4573 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourceScan[k], k 4574 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k] / 2.0, k 4575 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportHeight[k] / 2.0, k 4576 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0, k 4581 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PitchC[k], k 4583 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MacroTileWidthC[k], k 4586 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k], k 4587 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_height_chroma[k], k 4588 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_height_chroma[k]); k 4589 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines( k 4591 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k] / 2.0, k 4592 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTAPsChroma[k], k 4593 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 4595 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightCPerState[i][j][k], k 4596 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportYStartC[k], k 4597 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PrefillC[k], k 4598 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.MaxNumSwC[k]); k 4603 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PrefetchLinesC[k] = 0.0; k 4604 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PTEBufferSizeNotExceededC[i][j][k] = true; k 4607 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->PDEAndMetaPTEBytesPerFrame[k] = k 4609 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC; k 4610 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC; k 4614 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 4615 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 4616 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 4617 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4620 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height[k], k 4621 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height_chroma[k], k 4624 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height[k], k 4625 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height_chroma[k], k 4626 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.meta_row_bw[k], k 4627 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.dpte_row_bw[k], k 4628 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.qual_row_bw[k]); k 4646 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4647 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4648 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.WritebackEnable[k] == true) { k 4649 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency k 4651 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackPixelFormat[k], k 4652 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackHRatio[k], k 4653 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackVRatio[k], k 4654 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaHTaps[k], k 4655 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackLumaVTaps[k], k 4656 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaHTaps[k], k 4657 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackChromaVTaps[k], k 4658 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; k 4660 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WritebackDelay[i][k] = 0.0; k 4663 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[m] == k k 4666 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k], k 4680 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == m) { k 4683 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m]; k 4687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (m = 0; m < locals->NumberOfCursors[k]; m++) k 4689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m] k 4690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k]; k 4693 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4694 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] k 4695 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)); k 4708 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4710 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.XFCEnabled[k] == true) { k 4714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 4715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->SwathWidthYPerState[i][j][k], k 4716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 4717 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4734 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth, k 4735 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k], k 4736 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k], k 4738 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k], k 4739 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP, k 4740 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]); k 4742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.IsErrorResult[i][j][k] = k 4745 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredDPPCLK[i][j][k], k 4747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PixelClock[k], k 4749 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.NoOfDPP[i][j][k], k 4750 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.NumberOfCursors[k], k 4751 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VTotal[k] k 4752 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.VActive[k], k 4753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k], k 4755 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaximumVStartup[k], k 4758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataEnable[k], k 4759 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 4760 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 4761 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 4765 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], k 4766 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MetaRowBytes[k], k 4767 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPTEBytesPerRow[k], k 4768 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchLinesY[k], k 4769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathWidthYPerState[i][j][k], k 4770 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETY[k], k 4771 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefillY[k], k 4772 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxNumSwY[k], k 4773 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchLinesC[k], k 4774 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.BytePerPixelInDETC[k], k 4775 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefillC[k], k 4776 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MaxNumSwC[k], k 4777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightYPerState[i][j][k], k 4778 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SwathHeightCPerState[i][j][k], k 4780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.XFCEnabled[k], k 4782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Interlace[k], k 4784 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSTXAfterScaler[k], k 4785 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSTYAfterScaler[k], k 4786 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.LineTimesForPrefetch[k], k 4787 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.PrefetchBW[k], k 4788 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.LinesForMetaPTE[k], k 4789 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.LinesForMetaAndDPTERow[k], k 4790 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VRatioPreY[i][j][k], k 4791 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VRatioPreC[i][j][k], k 4792 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k], k 4793 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.Tno_bw[k], k 4794 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VUpdateOffsetPix[k], k 4795 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VUpdateWidthPix[k], k 4796 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.VReadyOffsetPix[k]); k 4802 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4803 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->PDEAndMetaPTEBytesPerFrame[k] == 0) k 4804 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_vm_bw[k] = 0; k 4805 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c else if (locals->LinesForMetaPTE[k] > 0) k 4806 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[k] k 4807 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]); k 4809 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_vm_bw[k] = 0; k 4812 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k] == 0) k 4813 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_row_bw[k] = 0; k 4814 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c else if (locals->LinesForMetaAndDPTERow[k] > 0) k 4815 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_row_bw[k] = (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k]) k 4816 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]); k 4818 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->prefetch_row_bw[k] = 0; k 4823 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]; k 4826 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.cursor_bw[k] k 4828 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k], k 4829 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k], k 4830 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_max(mode_lib->vba.ReadBandwidth[k], k 4831 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]) k 4832 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]); k 4843 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4844 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->LineTimesForPrefetch[k] < 2.0 k 4845 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->LinesForMetaPTE[k] >= 8.0 k 4846 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->LinesForMetaAndDPTERow[k] >= 16.0 k 4847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4852 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4853 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->VRatioPreY[i][j][k] > 4.0 k 4854 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->VRatioPreC[i][j][k] > 4.0 k 4855 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4866 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4869 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c - mode_lib->vba.cursor_bw[k] k 4871 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k], k 4872 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PrefetchBW[k]); k 4874 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4875 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ImmediateFlipBytes[k] = 0.0; k 4876 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 4877 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 4878 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ImmediateFlipBytes[k] = k 4879 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k] k 4880 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.MetaRowBytes[k] k 4881 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.DPTEBytesPerRow[k]; k 4885 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4886 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 4887 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 4890 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.ImmediateFlipBytes[k]; k 4894 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4903 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.SourcePixelFormat[k], k 4904 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ImmediateFlipBytes[k], k 4905 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.HTotal[k] k 4906 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.PixelClock[k], k 4907 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.VRatio[k], k 4908 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.Tno_bw[k], k 4909 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k], k 4910 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.MetaRowBytes[k], k 4911 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPTEBytesPerRow[k], k 4912 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCEnable[k], k 4913 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.dpte_row_height[k], k 4914 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.meta_row_height[k], k 4915 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.qual_row_bw[k], k 4916 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k], k 4917 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k], k 4918 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.final_flip_bw[k], k 4919 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c &mode_lib->vba.ImmediateFlipSupportedForPipe[k]); k 4922 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4925 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c + mode_lib->vba.cursor_bw[k] k 4927 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_vm_bw[k], k 4928 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.prefetch_row_bw[k], k 4929 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.final_flip_bw[k] k 4931 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ReadBandwidth[k], k 4932 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])); k 4939 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4940 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) { k 4966 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4967 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->PTEBufferSizeNotExceededY[i][j][k] == false k 4968 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || locals->PTEBufferSizeNotExceededC[i][j][k] == false) { k 4976 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4978 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.CursorWidth[k][j] > 0.0) { k 4984 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / (mode_lib->vba.CursorWidth[k][j] k 4985 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * mode_lib->vba.CursorBPP[k][j] k 4988 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c * (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 4989 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c / mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly k 4990 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c || (mode_lib->vba.CursorBPP[k][j] == 64.0 k 5000 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5001 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->AlignedYPitch[k] = dml_ceil( k 5002 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]), k 5003 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MacroTileWidthY[k]); k 5004 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) { k 5007 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.DCCEnable[k] == true) { k 5008 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->AlignedDCCMetaPitch[k] = dml_ceil( k 5010 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DCCMetaPitchY[k], k 5011 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k]), k 5012 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 64.0 * locals->Read256BlockWidthY[k]); k 5014 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k]; k 5016 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) { k 5019 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 5020 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 5021 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 5022 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 5023 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { k 5024 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->AlignedCPitch[k] = dml_ceil( k 5026 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.PitchC[k], k 5027 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ViewportWidth[k] / 2.0), k 5028 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->MacroTileWidthC[k]); k 5030 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k]; k 5032 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) { k 5111 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5112 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5113 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5124 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5125 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 5126 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ODMCombineEnabled[k] = k 5127 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; k 5129 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.ODMCombineEnabled[k] = 0; k 5131 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.DSCEnabled[k] = k 5132 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; k 5133 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c mode_lib->vba.OutputBpp[k] = k 5134 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k]; k 1466 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int j, k; k 1475 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1476 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k]) { k 1481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackPixelFormat[k], k 1482 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k], k 1483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackHRatio[k], k 1484 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackVRatio[k], k 1485 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaHTaps[k], k 1486 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaVTaps[k], k 1487 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaHTaps[k], k 1488 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaVTaps[k], k 1489 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackDestinationWidth[k], k 1490 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k], k 1495 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1496 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.HRatio[k] > 1) { k 1497 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1500 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HRatio[k] k 1502 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.htaps[k] k 1506 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_THROUGHPUT_LUMA[k] = dml_min( k 1512 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 1514 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.vtaps[k] / 6.0 k 1517 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k]), k 1519 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 1520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] k 1521 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->PSCL_THROUGHPUT_LUMA[k], k 1524 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) k 1526 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c < 2 * mode_lib->vba.PixelClock[k]) { k 1527 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k]; k 1530 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8 k 1531 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) { k 1532 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0; k 1533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPPCLKUsingSingleDPP[k] = k 1536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.HRatio[k] > 1) { k 1537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_THROUGHPUT_CHROMA[k] = k 1541 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HRatio[k] k 1544 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTAPsChroma[k] k 1548 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min( k 1553 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 1555 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VTAPsChroma[k] k 1559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 1562 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 1563 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] k 1565 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->PSCL_THROUGHPUT_CHROMA[k], k 1568 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6) k 1570 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c < 2 * mode_lib->vba.PixelClock[k]) { k 1572 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.PixelClock[k]; k 1575 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPPCLKUsingSingleDPP[k] = dml_max( k 1581 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1582 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] != k) k 1584 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ODMCombineEnabled[k]) { k 1588 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] / 2 k 1598 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] / 2 k 1602 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1606 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 1616 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 1653 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1654 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k] k 1655 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.DPPPerPlane[k] k 1659 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPCLK_calculated[k]); k 1664 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1665 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255 k 1667 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPCLK_calculated[k] * 255 k 1670 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DTRACE(" dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]); k 1678 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1681 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourceScan[k] == dm_horz) k 1682 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k]; k 1684 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k]; k 1686 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ODMCombineEnabled[k] == true) k 1689 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == j k 1694 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k] = dml_min( k 1695 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (double) locals->SwathWidthSingleDPPY[k], k 1697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HActive[k] / 2.0 k 1698 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HRatio[k])); k 1700 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k] k 1701 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.DPPPerPlane[k]; k 1704 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1705 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 1706 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 8; k 1707 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 0; k 1708 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 1709 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 4; k 1710 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 0; k 1711 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { k 1712 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 2; k 1713 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 0; k 1714 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { k 1715 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 1; k 1716 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 0; k 1717 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 1718 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 1; k 1719 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 2; k 1721 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k] = 4.0 / 3.0; k 1722 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k] = 8.0 / 3.0; k 1727 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1728 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k] k 1729 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * dml_ceil(locals->BytePerPixelDETY[k], 1) k 1730 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1731 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k]; k 1732 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k] k 1733 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / 2 * dml_ceil(locals->BytePerPixelDETC[k], 2) k 1734 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) k 1735 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] / 2; k 1738 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c k, k 1739 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneLuma[k] k 1740 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneChroma[k]); k 1741 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k] k 1742 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneChroma[k]; k 1762 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1763 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) { k 1764 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCCLK_calculated[k] = 0.0; k 1766 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 1767 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.OutputFormat[k] == dm_n422) k 1771 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ODMCombineEnabled[k]) k 1772 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCCLK_calculated[k] = k 1773 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClockBackEnd[k] / 6 k 1779 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCCLK_calculated[k] = k 1780 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClockBackEnd[k] / 3 k 1790 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1791 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c double bpp = mode_lib->vba.OutputBpp[k]; k 1792 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; k 1794 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DSCEnabled[k] && bpp != 0) { k 1795 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (!mode_lib->vba.ODMCombineEnabled[k]) { k 1796 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k] = k 1798 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k], k 1801 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (double) mode_lib->vba.HActive[k] k 1802 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.NumberOfDSCSlices[k], k 1805 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]) k 1807 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]); k 1809 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k] = k 1812 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k], k 1815 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (double) mode_lib->vba.HActive[k] k 1816 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.NumberOfDSCSlices[k], k 1819 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]) k 1821 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k])); k 1823 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k] = locals->DSCDelay[k] k 1824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.PixelClock[k] k 1825 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClockBackEnd[k]; k 1827 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k] = 0; k 1831 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 1833 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (j != k && mode_lib->vba.BlendingAndTiming[k] == j k 1835 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k] = locals->DSCDelay[j]; k 1838 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1849 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 1850 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 1851 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelDETY[k], 1), k 1852 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelDETC[k], 2), k 1853 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->BlockHeight256BytesY[k], k 1854 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->BlockHeight256BytesC[k], k 1855 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->BlockWidth256BytesY[k], k 1856 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->BlockWidth256BytesC[k]); k 1858 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines( k 1860 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 1861 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.vtaps[k], k 1862 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Interlace[k], k 1864 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 1865 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportYStartY[k], k 1866 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VInitPreFillY[k], k 1867 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MaxNumSwathY[k]); k 1869 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 1870 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 1871 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 1872 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) { k 1876 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 1877 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BlockHeight256BytesC[k], k 1878 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BlockWidth256BytesC[k], k 1879 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 1880 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 1882 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k], k 1884 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourceScan[k], k 1885 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k] / 2, k 1886 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportHeight[k] / 2, k 1887 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k] / 2, k 1894 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PitchC[k], k 1895 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCMetaPitchC[k], k 1896 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MacroTileWidthC[k], k 1900 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_width_chroma_ub[k], k 1901 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_height_chroma[k], k 1902 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_width_chroma[k], k 1903 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_height_chroma[k], k 1904 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_width_chroma[k], k 1905 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_height_chroma[k], k 1908 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PixelPTEReqWidthC[k], k 1909 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PixelPTEReqHeightC[k], k 1910 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PTERequestSizeC[k], k 1911 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpde0_bytes_per_frame_ub_c[k], k 1912 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_pte_bytes_per_frame_ub_c[k]); k 1914 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines( k 1916 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k] / 2, k 1917 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VTAPsChroma[k], k 1918 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Interlace[k], k 1920 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k], k 1921 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportYStartC[k], k 1922 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VInitPreFillC[k], k 1923 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MaxNumSwathC[k]); k 1928 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxNumSwathC[k] = 0; k 1929 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchSourceLinesC[k] = 0; k 1935 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 1936 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BlockHeight256BytesY[k], k 1937 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BlockWidth256BytesY[k], k 1938 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 1939 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 1940 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelDETY[k], 1), k 1941 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourceScan[k], k 1942 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k], k 1943 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportHeight[k], k 1944 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k], k 1951 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PitchY[k], k 1952 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCMetaPitchY[k], k 1953 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MacroTileWidthY[k], k 1957 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_width_luma_ub[k], k 1958 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_height[k], k 1959 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_width[k], k 1960 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_height[k], k 1961 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_width[k], k 1962 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_height[k], k 1963 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->vm_group_bytes[k], k 1964 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_group_bytes[k], k 1965 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PixelPTEReqWidthY[k], k 1966 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PixelPTEReqHeightY[k], k 1967 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PTERequestSizeY[k], k 1968 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpde0_bytes_per_frame_ub_l[k], k 1969 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_pte_bytes_per_frame_ub_l[k]); k 1971 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC; k 1972 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY k 1974 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC; k 1978 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 1979 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 1980 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 1981 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 1984 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height[k], k 1985 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height_chroma[k], k 1988 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height[k], k 1989 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height_chroma[k], k 1990 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_bw[k], k 1991 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_bw[k]); k 1996 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 1998 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + mode_lib->vba.DPPPerPlane[k]; k 1999 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DCCEnable[k]) k 2001 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + mode_lib->vba.DPPPerPlane[k]; k 2035 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2036 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2037 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 2038 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2041 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackPixelFormat[k], k 2042 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackHRatio[k], k 2043 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackVRatio[k], k 2044 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaHTaps[k], k 2045 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaVTaps[k], k 2046 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaHTaps[k], k 2047 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaVTaps[k], k 2048 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackDestinationWidth[k]) k 2051 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0; k 2053 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[j] == k k 2055 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2057 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[mode_lib->vba.VoltageLevel][k], k 2074 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2076 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == j) k 2077 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = k 2081 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2082 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1)); k 2085 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 2086 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]); k 2103 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2107 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2111 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 2112 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k], k 2114 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k], k 2116 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] k 2117 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k], k 2134 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.DPPCLK = locals->DPPCLK[k]; k 2136 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.PixelClock = mode_lib->vba.PixelClock[k]; k 2138 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k]; k 2139 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; k 2140 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.SourceScan = mode_lib->vba.SourceScan[k]; k 2141 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k]; k 2142 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k]; k 2143 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k]; k 2144 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k]; k 2145 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; k 2146 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; k 2147 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; k 2148 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.HTotal = mode_lib->vba.HTotal[k]; k 2155 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ErrorResult[k] = k 2161 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelay[k], k 2168 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (unsigned int) (locals->SwathWidthY[k] k 2169 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.HRatio[k]), k 2170 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 2172 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]), k 2173 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxVStartupLines[k], k 2177 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataEnable[k], k 2178 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 2179 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 2180 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 2184 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesFrame[k], k 2185 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowByte[k], k 2186 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PixelPTEBytesPerRow[k], k 2187 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchSourceLinesY[k], k 2188 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k], k 2189 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k], k 2190 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VInitPreFillY[k], k 2191 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxNumSwathY[k], k 2192 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchSourceLinesC[k], k 2193 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k], k 2194 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VInitPreFillC[k], k 2195 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxNumSwathC[k], k 2196 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 2197 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k], k 2199 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.XFCEnabled[k], k 2202 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DSTXAfterScaler[k], k 2203 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DSTYAfterScaler[k], k 2204 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesForPrefetch[k], k 2205 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PrefetchBandwidth[k], k 2206 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestVMInVBlank[k], k 2207 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestRowInVBlank[k], k 2208 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VRatioPrefetchY[k], k 2209 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VRatioPrefetchC[k], k 2210 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->RequiredPrefetchPixDataBWLuma[k], k 2211 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->RequiredPrefetchPixDataBWChroma[k], k 2213 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Tno_bw[k], k 2214 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->prefetch_vmrow_bw[k], k 2215 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->swath_width_luma_ub[k], k 2216 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->swath_width_chroma_ub[k], k 2217 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VUpdateOffsetPix[k], k 2218 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VUpdateWidthPix[k], k 2219 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VReadyOffsetPix[k]); k 2220 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 2221 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VStartup[k] = dml_min( k 2223 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxVStartupLines[k]); k 2226 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VStartup[k] = k 2230 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VStartup[k] = k 2233 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]); k 2237 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2240 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw[k] = 0; k 2241 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw_pre[k] = 0; k 2242 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { k 2243 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; k 2244 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k]; k 2249 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 2250 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k], k 2251 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k], k 2252 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / k 2253 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k], k 2256 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], k 2257 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), k 2258 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 2259 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VRatioPrefetchY[k], k 2260 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VRatioPrefetchC[k], k 2261 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k], k 2262 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETC[k], k 2263 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorCursor[k], k 2264 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorCursorPre[k], k 2265 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorLuma[k], k 2266 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorLumaPre[k], k 2267 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorChroma[k], k 2268 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorChromaPre[k], k 2273 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorLuma[k] = 1; k 2274 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorChroma[k] = 1; k 2275 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorCursor[k] = 1; k 2276 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorLumaPre[k] = 1; k 2277 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorChromaPre[k] = 1; k 2278 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorCursorPre[k] = 1; k 2282 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max3(locals->prefetch_vmrow_bw[k], k 2283 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k] k 2284 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] k 2285 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k], k 2286 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k] k 2287 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); k 2290 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max3(locals->prefetch_vmrow_bw[k], k 2291 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k] k 2292 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->meta_row_bw[k] + locals->dpte_row_bw[k], k 2293 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]); k 2295 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->DestinationLinesForPrefetch[k] < 2) k 2297 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4) k 2313 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2317 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k] k 2318 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] k 2319 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], k 2320 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + k 2321 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] + k 2322 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); k 2326 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2327 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k]; k 2329 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2341 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesFrame[k], k 2342 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowByte[k], k 2343 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PixelPTEBytesPerRow[k], k 2346 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 2347 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 2348 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 2349 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Tno_bw[k], k 2350 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 2351 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height[k], k 2352 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height[k], k 2353 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height_chroma[k], k 2354 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height_chroma[k], k 2355 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestVMInImmediateFlip[k], k 2356 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestRowInImmediateFlip[k], k 2357 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->final_flip_bw[k], k 2358 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->ImmediateFlipSupportedForPipe[k]); k 2362 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2365 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->prefetch_vmrow_bw[k], k 2366 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] k 2367 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], k 2368 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] k 2369 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] k 2370 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); k 2373 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max3(locals->prefetch_vmrow_bw[k], k 2374 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k], k 2375 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]); k 2384 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2385 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ImmediateFlipSupportedForPipe[k] == false) { k 2393 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2394 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ErrorResult[k]) { k 2557 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMClockChangeDuringVBlank[k] = true; k 2560 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2561 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinTTUVBlank[k] = dml_max( k 2567 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMClockChangeDuringVBlank[k] = false; k 2568 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMSelfRefreshDuringVBlank[k] = true; k 2569 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinTTUVBlank[k] = dml_max( k 2573 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMClockChangeDuringVBlank[k] = false; k 2574 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AllowDRAMSelfRefreshDuringVBlank[k] = false; k 2575 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark; k 2577 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (!mode_lib->vba.DynamicMetadataEnable[k]) k 2578 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinTTUVBlank[k] = mode_lib->vba.TCalc k 2579 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->MinTTUVBlank[k]; k 2584 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2585 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration( k 2586 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 2588 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k], k 2589 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportHeight[k], k 2591 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BlockHeight256BytesY[k], k 2592 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 2593 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 2594 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelDETY[k], k 2595 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourceScan[k], k 2596 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DCCYMaxUncompressedBlock[k], k 2597 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DCCYMaxCompressedBlock[k], k 2598 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DCCYIndependent64ByteBlock[k]); k 2602 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2603 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.XFCEnabled[k] == true) { k 2606 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset; k 2607 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth; k 2608 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset; k 2616 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 2617 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthY[k], k 2618 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelDETY[k], 1), k 2619 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 2632 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCRemoteSurfaceFlipLatency[k] = k 2635 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] k 2636 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]), k 2638 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCTransferDelay[k] = k 2641 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] k 2642 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]), k 2644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCPrechargeDelay[k] = k 2649 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] k 2650 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]), k 2655 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (locals->DestinationLinesToRequestVMInVBlank[k] k 2656 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->DestinationLinesToRequestRowInVBlank[k]) k 2657 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HTotal[k] k 2658 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k] k 2670 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCPrefetchMargin[k] = k 2673 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + (locals->DestinationLinesToRequestVMInVBlank[k] k 2674 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->DestinationLinesToRequestRowInVBlank[k]) k 2675 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HTotal[k] k 2676 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]; k 2678 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVUpdateOffset[k] = 0; k 2679 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVupdateWidth[k] = 0; k 2680 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCSlaveVReadyOffset[k] = 0; k 2681 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCRemoteSurfaceFlipLatency[k] = 0; k 2682 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCPrechargeDelay[k] = 0; k 2683 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCTransferDelay[k] = 0; k 2684 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->XFCPrefetchMargin[k] = 0; k 2689 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2692 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 2693 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k], k 2694 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DETBufferSizeY[k], k 2695 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DETBufferSizeC[k]); k 2697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->LinesInDETY[k] = locals->DETBufferSizeY[k] k 2698 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->BytePerPixelDETY[k] / locals->SwathWidthY[k]; k 2699 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->LinesInDETYRoundedDownToSwath[k] = dml_floor( k 2700 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->LinesInDETY[k], k 2701 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k]); k 2702 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->FullDETBufferingTimeY[k] = k 2703 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->LinesInDETYRoundedDownToSwath[k] k 2704 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * (mode_lib->vba.HTotal[k] k 2705 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]) k 2706 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.VRatio[k]; k 2710 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2711 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) { k 2712 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k]; k 2714 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k] k 2715 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]; k 2716 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1); k 2717 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k]; k 2719 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]); k 2725 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2728 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DCCEnable[k]) { k 2729 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->DCCYMaxCompressedBlock[k] == 256) k 2736 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) / k 2737 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit); k 2741 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneLuma[k] k 2742 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthPlaneChroma[k]; k 2745 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_bw[k] + locals->dpte_row_bw[k]; k 2769 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2770 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 2784 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2786 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k] k 2787 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k] k 2788 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]; k 2822 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int j, k; k 2824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 2827 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2830 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 2833 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2836 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) { k 2839 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2847 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2848 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2849 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2850 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2851 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2853 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 2855 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2856 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16) { k 2866 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2869 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 2882 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2890 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2891 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 2892 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 2893 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) { k 2894 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 2895 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 2896 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.SurfaceTiling[k] k 2898 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2900 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2902 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2904 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2906 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2908 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 2910 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 2912 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 k 2913 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] != dm_horz) { k 2920 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 2923 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 2924 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2927 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 2928 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 2937 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 2938 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c SwathWidth = mode_lib->vba.ViewportWidth[k]; k 2940 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c SwathWidth = mode_lib->vba.ViewportHeight[k]; k 2943 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ODMCombineEnabled[k] == true) { k 2947 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == j k 2956 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]); k 2958 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k]; k 2966 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2977 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 2987 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY; k 2988 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC; k 2990 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY; k 2991 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC; k 2996 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightY[k], k 2997 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathHeightC[k], k 2998 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.DETBufferSizeY[k], k 2999 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.DETBufferSizeC[k]); k 3393 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int j, k, m; k 3400 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3401 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ScalerEnabled[k] == false k 3402 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3403 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3404 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3405 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3406 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) k 3407 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.HRatio[k] != 1.0 k 3408 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.htaps[k] != 1.0 k 3409 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.VRatio[k] != 1.0 k 3410 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.vtaps[k] != 1.0)) { k 3412 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 k 3413 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0 k 3414 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.htaps[k] > 1.0 k 3415 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.htaps[k] % 2) == 1) k 3416 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio k 3417 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio k 3418 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k] k 3419 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] k 3420 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 3421 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 3422 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 3423 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 3424 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8 k 3425 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.HRatio[k] / 2.0 k 3426 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.HTAPsChroma[k] k 3427 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.VRatio[k] / 2.0 k 3428 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.VTAPsChroma[k]))) { k 3435 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3436 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3437 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] != dm_horz) k 3438 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d k 3439 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x k 3440 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d k 3441 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t k 3442 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x k 3443 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d k 3444 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x) k 3445 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_64) k 3446 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x k 3447 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8 k 3448 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] k 3450 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] k 3452 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl k 3453 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3455 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && !((mode_lib->vba.SourcePixelFormat[k] k 3457 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] k 3459 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] k 3463 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.DCCEnable[k] k 3465 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.DCCEnable[k] == true k 3466 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.SurfaceTiling[k] k 3468 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] k 3470 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] k 3477 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3478 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) { k 3479 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 8.0; k 3480 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 0.0; k 3481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) { k 3482 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 4.0; k 3483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 0.0; k 3484 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3485 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) { k 3486 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 2.0; k 3487 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 0.0; k 3488 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) { k 3489 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 1.0; k 3490 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 0.0; k 3491 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) { k 3492 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 1.0; k 3493 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 2.0; k 3495 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k] = 4.0 / 3; k 3496 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k] = 8.0 / 3; k 3498 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3499 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k]; k 3501 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k]; k 3504 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3505 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0) k 3506 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; k 3507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0) k 3508 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0; k 3509 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k]; k 3511 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3512 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true k 3513 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3514 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3515 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.WritebackDestinationHeight[k] k 3516 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.WritebackSourceHeight[k] k 3517 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HTotal[k] k 3518 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]) * 4.0; k 3519 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.WritebackEnable[k] == true k 3520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3521 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3522 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.WritebackDestinationHeight[k] k 3523 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.WritebackSourceHeight[k] k 3524 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HTotal[k] k 3525 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]) * 3.0; k 3526 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.WritebackEnable[k] == true) { k 3527 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] k 3528 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.WritebackDestinationHeight[k] k 3529 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.WritebackSourceHeight[k] k 3530 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HTotal[k] k 3531 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.PixelClock[k]) * 1.5; k 3533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WriteBandwidth[k] = 0.0; k 3537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3538 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DCCEnable[k] == true) { k 3560 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3561 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3562 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) { k 3563 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->WriteBandwidth[k] k 3570 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->WriteBandwidth[k] k 3601 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3602 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3603 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0) k 3604 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveWritebacksPerPlane[k] = 1; k 3607 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + mode_lib->vba.ActiveWritebacksPerPlane[k]; k 3614 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3615 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true k 3617 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) { k 3624 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3625 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3627 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.WritebackHRatio[k] != 1.0 k 3628 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackVRatio[k] != 1.0)) { k 3631 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio k 3632 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackVRatio[k] k 3634 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackHRatio[k] k 3636 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackVRatio[k] k 3638 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackLumaHTaps[k] k 3640 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackLumaVTaps[k] k 3642 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackHRatio[k] k 3643 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.WritebackLumaHTaps[k] k 3644 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackVRatio[k] k 3645 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.WritebackLumaVTaps[k] k 3646 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackLumaHTaps[k] > 2.0 k 3647 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && ((mode_lib->vba.WritebackLumaHTaps[k] % 2) k 3649 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32 k 3650 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.WritebackChromaHTaps[k] k 3652 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.WritebackChromaVTaps[k] k 3655 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.WritebackHRatio[k] k 3656 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.WritebackChromaHTaps[k] k 3658 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.WritebackVRatio[k] k 3659 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > mode_lib->vba.WritebackChromaVTaps[k] k 3660 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackChromaHTaps[k] > 2.0 k 3661 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) { k 3664 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackVRatio[k] < 1.0) { k 3666 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0); k 3670 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32 k 3671 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackLumaVTaps[k] k 3675 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.WritebackDestinationWidth[k] k 3677 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3678 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackLumaVTaps[k] k 3680 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3682 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3683 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackLumaVTaps[k] k 3686 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.WritebackDestinationWidth[k] k 3690 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) { k 3695 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8 k 3696 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackChromaVTaps[k] k 3698 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k] k 3700 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10 k 3701 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.WritebackChromaVTaps[k] k 3704 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.WritebackDestinationWidth[k] k 3713 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3714 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 3719 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackPixelFormat[k], k 3720 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k], k 3721 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackHRatio[k], k 3722 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackVRatio[k], k 3723 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaHTaps[k], k 3724 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaVTaps[k], k 3725 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaHTaps[k], k 3726 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaVTaps[k], k 3727 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackDestinationWidth[k], k 3728 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k], k 3732 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3733 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.HRatio[k] > 1.0) { k 3734 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_FACTOR[k] = dml_min( k 3737 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HRatio[k] k 3739 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.htaps[k] k 3743 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_FACTOR[k] = dml_min( k 3747 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3748 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_FACTOR_CHROMA[k] = 0.0; k 3749 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] = k 3750 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 3752 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.vtaps[k] / 6.0 k 3755 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k]), k 3756 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 3757 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] k 3758 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->PSCL_FACTOR[k], k 3760 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0) k 3761 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && locals->MinDPPCLKUsingSingleDPP[k] k 3762 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3763 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3764 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.PixelClock[k]; k 3767 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) { k 3768 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_FACTOR_CHROMA[k] = k 3772 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.HRatio[k] k 3775 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTAPsChroma[k] k 3779 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PSCL_FACTOR_CHROMA[k] = dml_min( k 3783 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] = k 3784 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 3786 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.vtaps[k] / 6.0 k 3789 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k]), k 3790 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 3791 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] k 3792 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->PSCL_FACTOR[k], k 3793 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VTAPsChroma[k] k 3797 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 3799 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 3800 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.VRatio[k] k 3802 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->PSCL_FACTOR_CHROMA[k], k 3804 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0 k 3805 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.HTAPsChroma[k] > 6.0 k 3806 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.VTAPsChroma[k] > 6.0) k 3807 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && locals->MinDPPCLKUsingSingleDPP[k] k 3808 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c < 2.0 * mode_lib->vba.PixelClock[k]) { k 3809 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] = 2.0 k 3810 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.PixelClock[k]; k 3814 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3816 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 3817 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 3818 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 3819 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelInDETC[k], 2.0), k 3820 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Read256BlockHeightY[k], k 3821 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Read256BlockHeightC[k], k 3822 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Read256BlockWidthY[k], k 3823 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Read256BlockWidthC[k]); k 3824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourceScan[k] == dm_horz) { k 3825 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k]; k 3826 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k]; k 3828 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k]; k 3829 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k]; k 3831 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3832 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_32 k 3833 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_444_16 k 3834 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16 k 3835 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) { k 3836 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear k 3837 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.SourcePixelFormat[k] == dm_444_64 k 3838 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && (mode_lib->vba.SurfaceTiling[k] k 3840 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3842 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3844 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3846 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3848 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3850 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.SurfaceTiling[k] k 3852 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz)) { k 3853 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3855 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3858 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3860 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3861 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3862 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3863 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8 k 3864 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3865 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k] k 3867 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3868 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10 k 3869 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourceScan[k] == dm_horz) { k 3870 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k] k 3872 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3874 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]; k 3875 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]; k 3878 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) { k 3887 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (locals->BytePerPixelInDETY[k] k 3888 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->MinSwathHeightY[k] k 3889 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->BytePerPixelInDETC[k] k 3891 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->MinSwathHeightC[k])); k 3892 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->BytePerPixelInDETC[k] == 0.0) { k 3895 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * dml_max(mode_lib->vba.HRatio[k], 1.0) k 3896 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.LBBitPerPixel[k] k 3897 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.vtaps[k] k 3900 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 3909 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k], k 3911 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.LBBitPerPixel[k] k 3912 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.vtaps[k] k 3915 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 3921 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HRatio[k] k 3924 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / mode_lib->vba.LBBitPerPixel[k] k 3925 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (mode_lib->vba.VTAPsChroma[k] k 3928 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k] k 3934 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaximumSwathWidth[k] = dml_min( k 3948 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 3950 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 3959 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k] k 3962 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3966 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2 k 3969 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ODMCombineEnablePerState[i][k] = false; k 3972 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ODMCombineEnablePerState[i][k] = true; k 3975 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity k 3976 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k] k 3977 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && locals->ODMCombineEnablePerState[i][k] == false) { k 3978 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->NoOfDPP[i][j][k] = 1; k 3979 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredDPPCLK[i][j][k] = k 3980 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0); k 3982 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->NoOfDPP[i][j][k] = 2; k 3983 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredDPPCLK[i][j][k] = k 3984 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0; k 3989 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 3996 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 3997 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4006 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 4007 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) { k 4008 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k]; k 4009 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c NumberOfNonSplitPlaneOfMaximumBandwidth = k; k 4022 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4023 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ODMCombineEnablePerState[i][k] = false; k 4024 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) { k 4025 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->NoOfDPP[i][j][k] = 1; k 4026 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 4029 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->NoOfDPP[i][j][k] = 2; k 4030 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k] k 4035 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k] k 4039 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k] k 4045 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) k 4051 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) k 4052 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4067 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4068 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4069 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) k 4070 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c > locals->MaximumSwathWidth[k]) { k 4074 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) { k 4093 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4094 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4107 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4108 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0 k 4109 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.DSCInputBitPerComponent[k] == 10.0 k 4110 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) { k 4115 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4116 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = 0; k 4117 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = 0; k 4118 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4119 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Output[k] == dm_hdmi) { k 4120 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = 0; k 4121 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = 0; k 4122 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[i][k] = TruncToValidBPP( k 4123 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, k 4124 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4126 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4127 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4128 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4129 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.Output[k] == dm_dp k 4130 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.Output[k] == dm_edp) { k 4131 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Output[k] == dm_edp) { k 4140 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4141 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4143 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4144 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4145 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4148 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4149 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4151 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4152 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4153 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4154 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4155 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = true; k 4156 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Output[k] == dm_dp) { k 4157 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = true; k 4159 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4163 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = false; k 4164 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4166 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4171 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4172 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4174 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4175 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4176 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4179 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4180 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4182 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4184 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4185 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DSCEnabled[k] == true) { k 4186 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = true; k 4187 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Output[k] == dm_dp) { k 4188 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = true; k 4190 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4194 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = false; k 4195 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4197 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp; k 4204 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4205 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4207 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4208 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4209 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4212 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, k 4213 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ForcedOutputLinkBPP[k], k 4215 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Output[k], k 4216 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4217 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k]); k 4218 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) { k 4219 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = true; k 4220 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.Output[k] == dm_dp) { k 4221 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = true; k 4223 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4227 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[i][k] = false; k 4228 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresFEC[i][k] = false; k 4230 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[i][k] = k 4235 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE; k 4241 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4242 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->OutputBppPerState[i][k] == BPP_INVALID k 4243 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || (mode_lib->vba.OutputFormat[k] == dm_420 k 4244 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.Interlace[k] == true k 4251 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4253 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4254 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.Output[k] == dm_dp k 4255 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.Output[k] == dm_edp)) { k 4256 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.OutputFormat[k] == dm_420 k 4257 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.OutputFormat[k] k 4263 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->RequiresDSC[i][k] == true) { k 4264 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ODMCombineEnablePerState[i][k] k 4266 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor k 4272 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor k 4286 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4287 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->RequiresDSC[i][k] == true) { k 4288 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4304 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4305 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] != k) { k 4307 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (locals->RequiresDSC[i][k] == 0 k 4308 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->RequiresDSC[i][k] == false) { k 4310 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) { k 4312 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClockBackEnd[k] / 400.0, k 4314 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) { k 4316 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) { k 4318 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) { k 4323 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE k 4324 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->OutputBppPerState[i][k] == BPP_INVALID) { k 4327 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.bpp = locals->OutputBppPerState[i][k]; k 4329 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) { k 4330 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ODMCombineEnablePerState[i][k] == false) { k 4331 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] = k 4333 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k], k 4336 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HActive[k] k 4340 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]) k 4342 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]); k 4344 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] = k 4346 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCInputBitPerComponent[k], k 4348 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0), k 4350 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k]) k 4351 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dscComputeDelay(mode_lib->vba.OutputFormat[k])); k 4353 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] = k 4354 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k]; k 4356 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] = 0.0; k 4359 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4362 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true) k 4363 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m]; k 4373 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 4374 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DCCEnable[k] == true) k 4375 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k]; k 4391 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4392 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k]; k 4393 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k]; k 4394 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ODMCombineEnablePerState[i][k] == true) { k 4395 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k] = k 4396 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])); k 4398 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k]; k 4401 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / dml_ceil(locals->BytePerPixelInDETY[k], 1.0) k 4402 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / locals->MaxSwathHeightY[k]; k 4404 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c (dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY) k 4405 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k]; k 4406 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 4411 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->MaxSwathHeightC[k] > 0.0) { k 4412 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k]; k 4413 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC) k 4414 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k]; k 4415 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) { k 4423 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k]; k 4424 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k]; k 4426 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightYThisState[k] = k 4427 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightY[k]; k 4428 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightCThisState[k] = k 4429 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MinSwathHeightC[k]; k 4448 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4449 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 4450 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 4451 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 4452 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 4453 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) { k 4456 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 4457 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Read256BlockHeightC[k], k 4458 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Read256BlockWidthC[k], k 4459 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 4460 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 4461 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelInDETC[k], 2.0), k 4462 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourceScan[k], k 4463 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k] / 2.0, k 4464 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportHeight[k] / 2.0, k 4465 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k] / 2.0, k 4472 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PitchC[k], k 4474 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MacroTileWidthC[k], k 4477 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PTEBufferSizeNotExceededC[i][j][k], k 4479 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_height_chroma[k], k 4480 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_width_chroma[k], k 4481 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_height_chroma[k], k 4482 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_width_chroma[k], k 4483 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_height_chroma[k], k 4491 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchLinesC[k] = CalculatePrefetchSourceLines( k 4493 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k]/2, k 4494 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VTAPsChroma[k], k 4495 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Interlace[k], k 4497 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightCThisState[k], k 4498 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportYStartC[k], k 4499 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PrefillC[k], k 4500 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MaxNumSwC[k]); k 4506 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchLinesC[k] = 0.0; k 4507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PTEBufferSizeNotExceededC[i][j][k] = true; k 4512 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 4513 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Read256BlockHeightY[k], k 4514 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Read256BlockWidthY[k], k 4515 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 4516 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SurfaceTiling[k], k 4517 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 4518 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourceScan[k], k 4519 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k], k 4520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportHeight[k], k 4521 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k], k 4528 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PitchY[k], k 4529 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCMetaPitchY[k], k 4530 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MacroTileWidthY[k], k 4533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PTEBufferSizeNotExceededY[i][j][k], k 4535 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_height[k], k 4536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_width[k], k 4537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_req_height[k], k 4538 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_width[k], k 4539 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_height[k], k 4540 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->vm_group_bytes[k], k 4541 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_group_bytes[k], k 4547 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchLinesY[k] = CalculatePrefetchSourceLines( k 4549 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 4550 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.vtaps[k], k 4551 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.Interlace[k], k 4553 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightYThisState[k], k 4554 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportYStartY[k], k 4555 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PrefillY[k], k 4556 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->MaxNumSwY[k]); k 4557 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesPerFrame[k] = k 4559 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC; k 4560 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC; k 4564 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 4565 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 4566 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 4567 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / k 4568 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PixelClock[k], k 4571 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height[k], k 4572 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height_chroma[k], k 4575 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height[k], k 4576 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height_chroma[k], k 4577 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->meta_row_bw[k], k 4578 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->dpte_row_bw[k]); k 4598 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4599 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 4600 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.WritebackEnable[k] == true) { k 4601 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency k 4603 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackPixelFormat[k], k 4604 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackHRatio[k], k 4605 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackVRatio[k], k 4606 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaHTaps[k], k 4607 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackLumaVTaps[k], k 4608 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaHTaps[k], k 4609 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackChromaVTaps[k], k 4610 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j]; k 4612 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[i][k] = 0.0; k 4615 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[m] == k k 4618 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k], k 4632 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4634 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == m) { k 4635 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m]; k 4640 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4641 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] k 4642 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0)); k 4643 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.MaxMaxVStartup = dml_max(mode_lib->vba.MaxMaxVStartup, locals->MaximumVStartup[k]); k 4657 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4661 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.XFCEnabled[k] == true) { k 4665 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 4666 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k], k 4667 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil(locals->BytePerPixelInDETY[k], 1.0), k 4668 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4685 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k]; k 4687 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.PixelClock = mode_lib->vba.PixelClock[k]; k 4689 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k]; k 4690 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k]; k 4691 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.SourceScan = mode_lib->vba.SourceScan[k]; k 4692 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k]; k 4693 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k]; k 4694 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k]; k 4695 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k]; k 4696 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; k 4697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k]; k 4698 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]; k 4699 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c myPipe.HTotal = mode_lib->vba.HTotal[k]; k 4707 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule( k 4712 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DSCDelayPerState[i][k], k 4719 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k], k 4720 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputFormat[k], k 4722 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[k]), k 4723 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaximumVStartup[k], k 4727 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataEnable[k], k 4728 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k], k 4729 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DynamicMetadataTransmittedBytes[k], k 4730 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 4734 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesPerFrame[k], k 4735 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowBytes[k], k 4736 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPTEBytesPerRow[k], k 4737 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchLinesY[k], k 4738 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k], k 4739 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k], k 4740 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefillY[k], k 4741 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxNumSwY[k], k 4742 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefetchLinesC[k], k 4743 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k], k 4744 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PrefillC[k], k 4745 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MaxNumSwC[k], k 4746 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightYThisState[k], k 4747 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightCThisState[k], k 4749 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.XFCEnabled[k], k 4754 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->LineTimesForPrefetch[k], k 4755 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->PrefetchBW[k], k 4756 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->LinesForMetaPTE[k], k 4757 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->LinesForMetaAndDPTERow[k], k 4758 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VRatioPreY[i][j][k], k 4759 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->VRatioPreC[i][j][k], k 4760 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->RequiredPrefetchPixelDataBWLuma[i][j][k], k 4761 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->RequiredPrefetchPixelDataBWChroma[i][j][k], k 4763 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->Tno_bw[k], k 4764 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->prefetch_vmrow_bw[k], k 4767 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VUpdateOffsetPix[k], k 4768 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VUpdateWidthPix[k], k 4769 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &mode_lib->vba.VReadyOffsetPix[k]); k 4773 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4776 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw[k] = 0; k 4777 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw_pre[k] = 0; k 4778 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { k 4779 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] k 4780 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; k 4781 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] k 4782 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k]; k 4787 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightYThisState[k], k 4788 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathHeightCThisState[k], k 4789 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->SwathWidthYThisState[k], k 4790 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4793 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1], k 4794 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]), k 4795 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 4796 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VRatioPreY[i][j][k], k 4797 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->VRatioPreC[i][j][k], k 4798 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETY[k], k 4799 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->BytePerPixelInDETC[k], k 4800 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorCursor[k], k 4801 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorCursorPre[k], k 4802 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorLuma[k], k 4803 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorLumaPre[k], k 4804 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorChroma[k], k 4805 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->UrgentBurstFactorChromaPre[k], k 4810 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorCursor[k] = 1; k 4811 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorCursorPre[k] = 1; k 4812 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorLuma[k] = 1; k 4813 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorLumaPre[k] = 1; k 4814 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorChroma[k] = 1; k 4815 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->UrgentBurstFactorChromaPre[k] = 1; k 4819 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k] k 4820 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k] k 4821 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k]; k 4823 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_max3(locals->prefetch_vmrow_bw[k], k 4824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k] k 4825 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] k 4826 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->meta_row_bw[k] + locals->dpte_row_bw[k], k 4827 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k] k 4828 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] k 4829 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); k 4843 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4844 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->LineTimesForPrefetch[k] < 2.0 k 4845 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->LinesForMetaPTE[k] >= 32.0 k 4846 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->LinesForMetaAndDPTERow[k] >= 16.0 k 4847 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4852 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4853 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->VRatioPreY[i][j][k] > 4.0 k 4854 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->VRatioPreC[i][j][k] > 4.0 k 4855 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || mode_lib->vba.IsErrorResult[i][j][k] == true) { k 4860 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 4861 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) { k 4878 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4880 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] k 4881 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] k 4882 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], k 4883 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k] k 4884 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k] k 4885 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]); k 4888 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4890 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->PDEAndMetaPTEBytesPerFrame[k] + locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k]; k 4893 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4905 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->PDEAndMetaPTEBytesPerFrame[k], k 4906 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MetaRowBytes[k], k 4907 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPTEBytesPerRow[k], k 4910 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.SourcePixelFormat[k], k 4911 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k], k 4912 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.VRatio[k], k 4913 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->Tno_bw[k], k 4914 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCEnable[k], k 4915 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height[k], k 4916 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height[k], k 4917 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->dpte_row_height_chroma[k], k 4918 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->meta_row_height_chroma[k], k 4919 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestVMInImmediateFlip[k], k 4920 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->DestinationLinesToRequestRowInImmediateFlip[k], k 4921 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->final_flip_bw[k], k 4922 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c &locals->ImmediateFlipSupportedForPipe[k]); k 4925 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4927 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->prefetch_vmrow_bw[k], k 4928 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] k 4929 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] k 4930 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k], k 4931 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k] k 4932 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k] k 4933 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] k 4934 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * locals->UrgentBurstFactorCursorPre[k]); k 4941 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 4942 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->ImmediateFlipSupportedForPipe[k] == false) { k 5016 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 5017 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k]; k 5042 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5043 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->PTEBufferSizeNotExceededY[i][j][k] == false k 5044 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c || locals->PTEBufferSizeNotExceededC[i][j][k] == false) { k 5053 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5054 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.CursorWidth[k][0] > 0.0) { k 5055 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { k 5056 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) { k 5065 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5066 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AlignedYPitch[k] = dml_ceil( k 5067 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]), k 5068 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MacroTileWidthY[k]); k 5069 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) { k 5072 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.DCCEnable[k] == true) { k 5073 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AlignedDCCMetaPitch[k] = dml_ceil( k 5075 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCCMetaPitchY[k], k 5076 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k]), k 5077 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 64.0 * locals->Read256BlockWidthY[k]); k 5079 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k]; k 5081 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) { k 5084 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64 k 5085 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_32 k 5086 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_444_16 k 5087 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_16 k 5088 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) { k 5089 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AlignedCPitch[k] = dml_ceil( k 5091 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.PitchC[k], k 5092 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ViewportWidth[k] / 2.0), k 5093 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->MacroTileWidthC[k]); k 5095 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k]; k 5097 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) { k 5182 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5184 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k]; k 5194 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { k 5195 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.BlendingAndTiming[k] == k) { k 5196 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ODMCombineEnabled[k] = k 5197 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k]; k 5199 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ODMCombineEnabled[k] = 0; k 5201 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DSCEnabled[k] = k 5202 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->RequiresDSC[mode_lib->vba.VoltageLevel][k]; k 5203 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.OutputBpp[k] = k 5204 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k]; k 5285 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int k, j; k 5289 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5290 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k]; k 5291 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (DCCEnable[k] == true) { k 5292 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k]; k 5297 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5299 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k]; k 5307 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5308 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (WritebackEnable[k] == true) { k 5327 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5330 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) k 5331 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - (vtaps[k] - 1); k 5334 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1)) k 5335 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - (VTAPsChroma[k] - 1); k 5337 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] k 5338 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * (HTotal[k] / PixelClock[k]); k 5341 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]); k 5343 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) { k 5344 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k]; k 5345 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (SwathWidthY[k] > DPPOutputBufferPixels) { k 5351 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) { k 5353 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (SwathWidthY[k] / 2.0); k 5354 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c } else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) { k 5362 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c SwathHeightY[k], k 5363 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c SwathHeightC[k], k 5367 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; k 5368 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); k 5369 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] k 5370 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * (HTotal[k] / PixelClock[k]) / VRatio[k]; k 5371 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 5372 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0); k 5373 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); k 5375 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2); k 5381 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k] k 5383 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark; k 5387 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; k 5390 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 5391 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k] k 5396 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2); k 5398 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 5402 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; k 5405 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (WritebackEnable[k] == true) { k 5406 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (WritebackPixelFormat[k] == dm_444_32) { k 5408 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k] k 5409 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] k 5410 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark; k 5414 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k] k 5415 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k])) k 5418 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min( k 5419 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], k 5426 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5427 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] k 5430 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; k 5431 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BlendingAndTiming[k] == k) { k 5432 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c PlaneWithMinActiveDRAMClockChangeMargin = k; k 5435 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BlendingAndTiming[k] == j) { k 5446 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5447 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) k 5448 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) k 5449 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] k 5452 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; k 5457 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5458 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BlendingAndTiming[k] == k) { k 5475 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5476 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) { k 5477 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] k 5478 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) k 5479 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * (HTotal[k] / PixelClock[k]) / VRatio[k]; k 5507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int k; k 5512 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5513 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatio[k] <= 1) { k 5514 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] k 5515 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / HRatio[k] / PixelClock[k]; k 5517 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] k 5518 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / DPPCLK[k]; k 5520 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5523 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatio[k] / 2 <= 1) { k 5524 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0 k 5525 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k]; k 5527 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0 k 5528 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; k 5532 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 5533 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( k 5534 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1) k 5536 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 1.1 * SwathWidthY[k] / 2.0 k 5537 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * dml_ceil(BytePerPixelDETC[k], 2) / 32.0 k 5540 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k] k 5541 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * dml_ceil(BytePerPixelDETY[k], 1) / 64.0 k 5544 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max( k 5545 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k], k 5546 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c PixelClock[k] / 16); k 5551 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5554 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c mode_lib->vba.DCFCLKDeepSleepPerPlane[k]); k 5727 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int k; k 5729 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5730 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatio[k] <= 1) { k 5731 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] k 5732 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / HRatio[k] / PixelClock[k]; k 5734 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] k 5735 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PSCL_THROUGHPUT[k] / DPPCLK[k]; k 5738 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5739 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma[k] = 0; k 5741 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatio[k] / 2 <= 1) { k 5742 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] k 5743 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k]; k 5745 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] k 5746 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; k 5750 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatioPrefetchY[k] <= 1) { k 5751 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] k 5752 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * DPPPerPlane[k] / HRatio[k] / PixelClock[k]; k 5754 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] k 5755 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PSCL_THROUGHPUT[k] / DPPCLK[k]; k 5758 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5759 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0; k 5761 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (VRatioPrefetchC[k] <= 1) { k 5762 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 5763 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c swath_width_chroma_ub[k] * DPPPerPlane[k] k 5764 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / (HRatio[k] / 2) / PixelClock[k]; k 5766 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChromaPrefetch[k] = k 5767 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k]; k 5772 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5773 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SourceScan[k] == dm_horz) { k 5774 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k]; k 5776 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k]; k 5778 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] k 5780 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = k 5781 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub; k 5782 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5783 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeChroma[k] = 0; k 5784 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0; k 5786 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SourceScan[k] == dm_horz) { k 5787 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c req_per_swath_ub = swath_width_chroma_ub[k] k 5788 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / BlockWidth256BytesC[k]; k 5790 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c req_per_swath_ub = swath_width_chroma_ub[k] k 5791 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / BlockHeight256BytesC[k]; k 5793 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeChroma[k] = k 5794 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub; k 5795 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = k 5796 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub; k 5869 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c unsigned int k; k 5871 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5873 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k]; k 5874 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5875 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_PTE_ROW_NOM_C[k] = 0; k 5877 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2); k 5880 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_PTE_ROW_NOM_L[k] = 0; k 5881 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_PTE_ROW_NOM_C[k] = 0; k 5883 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (DCCEnable[k] == true) { k 5884 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k]; k 5886 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DST_Y_PER_META_ROW_NOM_L[k] = 0; k 5890 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5891 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (DCCEnable[k] == true) { k 5893 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; k 5895 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k]; k 5896 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width; k 5897 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c meta_row_remainder = meta_row_width[k] % meta_chunk_width; k 5898 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SourceScan[k] == dm_horz) { k 5899 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; k 5902 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c - meta_req_height[k]; k 5909 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] k 5910 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k] / meta_chunks_per_row_ub; k 5911 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] k 5912 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; k 5913 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] k 5914 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub; k 5916 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkNominal[k] = 0; k 5917 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkVBlank[k] = 0; k 5918 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerMetaChunkFlip[k] = 0; k 5922 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5924 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SourceScan[k] == dm_horz) { k 5925 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] k 5926 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * PixelPTEReqWidthY[k]; k 5928 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] k 5929 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * PixelPTEReqHeightY[k]; k 5932 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_row_width_luma_ub[k] / dpte_group_width_luma, k 5934 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] k 5935 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k] / dpte_groups_per_row_luma_ub; k 5936 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] k 5937 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub; k 5938 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_flip_luma[k] = k 5939 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] k 5940 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k] k 5942 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] == 0) { k 5943 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_nom_chroma[k] = 0; k 5944 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_vblank_chroma[k] = 0; k 5945 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_flip_chroma[k] = 0; k 5947 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (SourceScan[k] == dm_horz) { k 5948 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_group_width_chroma = dpte_group_bytes[k] k 5949 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PTERequestSizeC[k] * PixelPTEReqWidthC[k]; k 5951 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_group_width_chroma = dpte_group_bytes[k] k 5952 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PTERequestSizeC[k] k 5953 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * PixelPTEReqHeightC[k]; k 5956 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dpte_row_width_chroma_ub[k] k 5959 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] k 5960 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] k 5962 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_vblank_chroma[k] = k 5963 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DestinationLinesToRequestRowInVBlank[k] * HTotal[k] k 5964 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k] k 5966 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_flip_chroma[k] = k 5967 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c DestinationLinesToRequestRowInImmediateFlip[k] k 5968 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] k 5972 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_nom_luma[k] = 0; k 5973 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_vblank_luma[k] = 0; k 5974 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_flip_luma[k] = 0; k 5975 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_nom_chroma[k] = 0; k 5976 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_vblank_chroma[k] = 0; k 5977 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c time_per_pte_group_flip_chroma[k] = 0; k 5981 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; ++k) { k 5982 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) { k 5983 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (DCCEnable[k] == false) { k 5984 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 5986 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) k 5987 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); k 5990 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); k 5994 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 5996 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) k 5997 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); k 6000 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); k 6003 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 6005 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) k 6006 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1) k 6007 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) k 6008 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1); k 6011 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1) k 6012 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1); k 6017 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (DCCEnable[k] == false) { k 6018 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 6019 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] k 6020 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / 64 + dpde0_bytes_per_frame_ub_c[k] / 64; k 6022 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] k 6027 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 6028 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 k 6029 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + meta_pte_bytes_per_frame_ub_c[k] / 64; k 6031 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64; k 6034 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c if (BytePerPixelDETC[k] > 0) { k 6035 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 k 6036 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + dpde0_bytes_per_frame_ub_c[k] / 64 k 6037 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + meta_pte_bytes_per_frame_ub_l[k] / 64 k 6038 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + meta_pte_bytes_per_frame_ub_c[k] / 64; k 6040 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 k 6041 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + meta_pte_bytes_per_frame_ub_l[k] / 64; k 6046 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] k 6047 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c / PixelClock[k] / num_group_per_lower_vm_stage; k 6048 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] k 6049 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage; k 6050 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] k 6051 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; k 6052 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] k 6053 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage; k 6056 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2; k 6057 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2; k 6058 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2; k 6059 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2; k 6063 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupVBlank[k] = 0; k 6064 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMGroupFlip[k] = 0; k 6065 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestVBlank[k] = 0; k 6066 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c TimePerVMRequestFlip[k] = 0; k 6108 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c int k; k 6110 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c for (k = 0; k < NumberOfActivePlanes; k++) { k 6112 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c + NumberOfDPP[k] * dpte_group_bytes[k] k 171 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c unsigned int k; k 174 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 175 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c immediate_flip_bw += mode_lib->vba.ImmediateFlipBW[k]; k 184 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c unsigned int k; k 188 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 189 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c total_prefetch_bw += mode_lib->vba.PrefetchBandwidth[k]; k 355 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c unsigned int j, k; k 360 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) k 361 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c visited[k] = false; k 541 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < DC__NUM_CURSOR__MAX; ++k) { k 542 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c switch (k) { k 582 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) { k 583 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c display_pipe_source_params_st *src_k = &pipes[k].pipe.src; k 584 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest; k 586 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c if (src_k->is_hsplit && !visited[k] k 588 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.pipe_plane[k] = k 602 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c visited[k] = true; k 607 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c if (pipes[k].pipe.src.immediate_flip) k 620 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = j + 1; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 621 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c if (!PlaneVisited[k] && OTGInstPlane[j] == OTGInstPlane[k]) { k 625 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.BlendingAndTiming[k] = j; k 626 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c PlaneVisited[k] = true; k 640 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 1; k < mode_lib->vba.cache_num_pipes; ++k) k 641 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c ASSERT(mode_lib->vba.SynchronizedVBlank == pipes[k].pipe.dest.synchronized_vblank_all_planes); k 648 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) { k 649 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable || !!pipes[k].pipe.src.gpuvm || !!pipes[k].pipe.src.vm; k 651 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c (pipes[k].pipe.src.gpuvm_levels_force_en k 653 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c < pipes[k].pipe.src.gpuvm_levels_force) ? k 654 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c pipes[k].pipe.src.gpuvm_levels_force : k 657 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable || !!pipes[k].pipe.src.hostvm || !!pipes[k].pipe.src.vm; k 659 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c (pipes[k].pipe.src.hostvm_levels_force_en k 661 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c < pipes[k].pipe.src.hostvm_levels_force) ? k 662 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c pipes[k].pipe.src.hostvm_levels_force : k 774 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c unsigned int k; k 777 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { k 778 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c if (mode_lib->vba.Interlace[k] == 1 k 780 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClockBackEnd[k]; k 802 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c unsigned int k; k 821 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) k 822 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c total_pipes += mode_lib->vba.DPPPerPlane[k]; k 722 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c int i, j, k; k 750 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (k = 0; k < SMU7_DTE_SINKS; k++) { k 751 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1); k 752 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2); k 2583 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint8_t i, j, k; k 2597 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2598 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2600 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 2609 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2610 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2612 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 2615 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 2624 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2625 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2626 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 2637 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2638 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2640 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 1858 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c int i, j, k; k 1895 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (k = 0; k < SMU71_DTE_SINKS; k++) { k 1896 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1); k 1897 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2); k 2512 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint8_t i, j, k; k 2526 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2527 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2529 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 2538 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2539 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2541 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 2544 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 2554 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2555 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2556 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 2567 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2568 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2570 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 435 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c int i, j, k; k 460 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (k = 0; k < SMU74_DTE_SINKS; k++) { k 461 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); k 462 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); k 1835 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c int i, j, k; k 1859 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (k = 0; k < SMU72_DTE_SINKS; k++) { k 1860 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c dpm_table->BAPMTI_R[i][j][k] = k 1862 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c dpm_table->BAPMTI_RC[i][j][k] = k 2975 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint8_t i, j, k; k 2990 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (k = 0; k < table->num_entries; k++) { k 2991 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 2993 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 3002 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (k = 0; k < table->num_entries; k++) { k 3003 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 3005 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 3008 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 3017 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (k = 0; k < table->num_entries; k++) k 3018 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 3019 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 3029 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (k = 0; k < table->num_entries; k++) { k 3030 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c table->mc_reg_table_entry[k].mc_data[j] = k 3032 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 1453 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c int i, j, k; k 1478 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (k = 0; k < SMU75_DTE_SINKS; k++) { k 1479 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); k 1480 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); k 798 drivers/gpu/drm/exynos/exynos_drm_gsc.c int i, j, k, sc_ratio; k 817 drivers/gpu/drm/exynos/exynos_drm_gsc.c for (k = 0; k < GSC_COEF_DEPTH; k++) k 819 drivers/gpu/drm/exynos/exynos_drm_gsc.c GSC_HCOEF(i, j, k)); k 824 drivers/gpu/drm/exynos/exynos_drm_gsc.c int i, j, k, sc_ratio; k 843 drivers/gpu/drm/exynos/exynos_drm_gsc.c for (k = 0; k < GSC_COEF_DEPTH; k++) k 845 drivers/gpu/drm/exynos/exynos_drm_gsc.c GSC_VCOEF(i, j, k)); k 378 drivers/gpu/drm/i915/display/intel_dp.c int i = 0, j = 0, k = 0; k 382 drivers/gpu/drm/i915/display/intel_dp.c if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) k 383 drivers/gpu/drm/i915/display/intel_dp.c return k; k 384 drivers/gpu/drm/i915/display/intel_dp.c common_rates[k] = source_rates[i]; k 385 drivers/gpu/drm/i915/display/intel_dp.c ++k; k 394 drivers/gpu/drm/i915/display/intel_dp.c return k; k 1335 drivers/gpu/drm/i915/display/intel_hdcp.c msgs.stream_manage.k = cpu_to_be16(1); k 1762 drivers/gpu/drm/i915/display/intel_hdcp.c data->k = 1; k 1764 drivers/gpu/drm/i915/display/intel_hdcp.c data->streams = kcalloc(data->k, k 257 drivers/gpu/drm/lima/lima_vm.c int i, j, k; k 274 drivers/gpu/drm/lima/lima_vm.c for (k = 0; k < LIMA_PAGE_ENT_NUM; k++) { k 278 drivers/gpu/drm/lima/lima_vm.c printk(KERN_INFO " pt %03x:%08x\n", k, pte); k 1019 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c int k; k 1021 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c for (k = 0; k < count; index++, offset++, k++) { k 322 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c int i, j, k; k 331 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c for (k = 0; k < 2; k++) { k 332 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c rs[k] = max((int64_t)rs[k], id2); k 335 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c struct filter_params *p = &fparams[k][j]; k 341 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c p->ki3r*i*i*i) * rs[k] k 345 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c p->ki3rf*i*i*i) * flicker * rs[k]; k 347 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c (*filters[k])[j][i] = (c + id5/2) >> 39 k 41 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c int i, j, k; k 62 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.c for (k = 0; k < 4; k++) k 66 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c calc_bias(struct nvkm_fb *fb, int k, int i, int j) k 70 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >> k 78 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c calc_ref(struct nvkm_fb *fb, int l, int k, int i) k 83 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c int m = (l >> (8 * i) & 0xff) + calc_bias(fb, k, i, j); k 1921 drivers/gpu/drm/radeon/btc_dpm.c u8 i, j, k; k 1930 drivers/gpu/drm/radeon/btc_dpm.c for (k = 0; k < table->num_entries; k++) { k 1931 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 1933 drivers/gpu/drm/radeon/btc_dpm.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 1943 drivers/gpu/drm/radeon/btc_dpm.c for (k = 0; k < table->num_entries; k++) { k 1944 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 1946 drivers/gpu/drm/radeon/btc_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 1948 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 1959 drivers/gpu/drm/radeon/btc_dpm.c for (k = 0; k < table->num_entries; k++) { k 1960 drivers/gpu/drm/radeon/btc_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 1962 drivers/gpu/drm/radeon/btc_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 439 drivers/gpu/drm/radeon/ci_dpm.c int i, j, k; k 467 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < SMU7_DTE_SINKS; k++) { k 468 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1); k 469 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2); k 4340 drivers/gpu/drm/radeon/ci_dpm.c u8 i, j, k; k 4351 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4352 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 4353 drivers/gpu/drm/radeon/ci_dpm.c ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 4362 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4363 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 4364 drivers/gpu/drm/radeon/ci_dpm.c (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 4366 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 4375 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4376 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 4377 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 4388 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4389 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 4390 drivers/gpu/drm/radeon/ci_dpm.c (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 4537 drivers/gpu/drm/radeon/ci_dpm.c u8 i, k; k 4552 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4553 drivers/gpu/drm/radeon/ci_dpm.c if ((table->mc_reg_table_entry[k].mclk_max == 125000) || k 4554 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mclk_max == 137500)) k 4555 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4556 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | k 4561 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4562 drivers/gpu/drm/radeon/ci_dpm.c if ((table->mc_reg_table_entry[k].mclk_max == 125000) || k 4563 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mclk_max == 137500)) k 4564 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4565 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | k 4570 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4571 drivers/gpu/drm/radeon/ci_dpm.c if ((table->mc_reg_table_entry[k].mclk_max == 125000) || k 4572 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mclk_max == 137500)) k 4573 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4574 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | k 4579 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4580 drivers/gpu/drm/radeon/ci_dpm.c if ((table->mc_reg_table_entry[k].mclk_max == 125000) || k 4581 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mclk_max == 137500)) k 4582 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = 0; k 4586 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4587 drivers/gpu/drm/radeon/ci_dpm.c if (table->mc_reg_table_entry[k].mclk_max == 125000) k 4588 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4589 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | k 4591 drivers/gpu/drm/radeon/ci_dpm.c else if (table->mc_reg_table_entry[k].mclk_max == 137500) k 4592 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4593 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | k 4598 drivers/gpu/drm/radeon/ci_dpm.c for (k = 0; k < table->num_entries; k++) { k 4599 drivers/gpu/drm/radeon/ci_dpm.c if (table->mc_reg_table_entry[k].mclk_max == 125000) k 4600 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4601 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | k 4603 drivers/gpu/drm/radeon/ci_dpm.c else if (table->mc_reg_table_entry[k].mclk_max == 137500) k 4604 drivers/gpu/drm/radeon/ci_dpm.c table->mc_reg_table_entry[k].mc_data[i] = k 4605 drivers/gpu/drm/radeon/ci_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | k 5548 drivers/gpu/drm/radeon/ci_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 5598 drivers/gpu/drm/radeon/ci_dpm.c k = 0; k 5604 drivers/gpu/drm/radeon/ci_dpm.c if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS) k 5610 drivers/gpu/drm/radeon/ci_dpm.c &rdev->pm.dpm.ps[i], k, k 5612 drivers/gpu/drm/radeon/ci_dpm.c k++; k 5798 drivers/gpu/drm/radeon/cik.c u32 i, j, k; k 5804 drivers/gpu/drm/radeon/cik.c for (k = 0; k < rdev->usec_timeout; k++) { k 5814 drivers/gpu/drm/radeon/cik.c for (k = 0; k < rdev->usec_timeout; k++) { k 6564 drivers/gpu/drm/radeon/cik.c u32 i, j, k, active_cu_number = 0; k 6573 drivers/gpu/drm/radeon/cik.c for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) { k 4157 drivers/gpu/drm/radeon/evergreen.c u32 dws, data, i, j, k, reg_num; k 4312 drivers/gpu/drm/radeon/evergreen.c for (k = 0; k < reg_num; k++) { k 4313 drivers/gpu/drm/radeon/evergreen.c data = cs_data[i].section[j].extent[k]; k 4314 drivers/gpu/drm/radeon/evergreen.c dst_ptr[reg_list_blk_index + k] = cpu_to_le32(data); k 2638 drivers/gpu/drm/radeon/kv_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 2685 drivers/gpu/drm/radeon/kv_dpm.c k = 0; k 2691 drivers/gpu/drm/radeon/kv_dpm.c if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) k 2697 drivers/gpu/drm/radeon/kv_dpm.c &rdev->pm.dpm.ps[i], k, k 2699 drivers/gpu/drm/radeon/kv_dpm.c k++; k 2713 drivers/gpu/drm/radeon/ni_dpm.c u8 i, j, k; k 2724 drivers/gpu/drm/radeon/ni_dpm.c for (k = 0; k < table->num_entries; k++) k 2725 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 2727 drivers/gpu/drm/radeon/ni_dpm.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 2735 drivers/gpu/drm/radeon/ni_dpm.c for(k = 0; k < table->num_entries; k++) { k 2736 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 2738 drivers/gpu/drm/radeon/ni_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 2740 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 2750 drivers/gpu/drm/radeon/ni_dpm.c for (k = 0; k < table->num_entries; k++) k 2751 drivers/gpu/drm/radeon/ni_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 2753 drivers/gpu/drm/radeon/ni_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 223 drivers/gpu/drm/radeon/r600_dpm.c u32 k, a, ah, al; k 229 drivers/gpu/drm/radeon/r600_dpm.c k = (100 * fh) / fl; k 230 drivers/gpu/drm/radeon/r600_dpm.c t1 = (t * (k - 100)); k 534 drivers/gpu/drm/radeon/radeon_atombios.c int i, j, k, path_size, device_support; k 663 drivers/gpu/drm/radeon/radeon_atombios.c for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { k 664 drivers/gpu/drm/radeon/radeon_atombios.c u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); k 668 drivers/gpu/drm/radeon/radeon_atombios.c le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); k 694 drivers/gpu/drm/radeon/radeon_atombios.c for (k = 0; k < router_obj->ucNumberOfObjects; k++) { k 695 drivers/gpu/drm/radeon/radeon_atombios.c u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); k 699 drivers/gpu/drm/radeon/radeon_atombios.c le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); k 707 drivers/gpu/drm/radeon/radeon_atombios.c le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); k 336 drivers/gpu/drm/radeon/radeon_i2c.c int i, j, k, ret = num; k 480 drivers/gpu/drm/radeon/radeon_i2c.c for (k = 0; k < 32; k++) { k 512 drivers/gpu/drm/radeon/radeon_i2c.c for (k = 0; k < 32; k++) { k 540 drivers/gpu/drm/radeon/radeon_i2c.c for (k = 0; k < 32; k++) { k 528 drivers/gpu/drm/radeon/radeon_test.c int i, j, k; k 549 drivers/gpu/drm/radeon/radeon_test.c for (k = 0; k < j; ++k) { k 550 drivers/gpu/drm/radeon/radeon_test.c struct radeon_ring *ringC = &rdev->ring[k]; k 560 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k); k 563 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j); k 566 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k); k 569 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i); k 572 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j); k 575 drivers/gpu/drm/radeon/radeon_test.c DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i); k 3000 drivers/gpu/drm/radeon/si.c int i, j, k; k 3010 drivers/gpu/drm/radeon/si.c for (k = 0; k < 16; k++) { k 3011 drivers/gpu/drm/radeon/si.c mask <<= k; k 5324 drivers/gpu/drm/radeon/si.c u32 i, j, k, active_cu_number = 0; k 5333 drivers/gpu/drm/radeon/si.c for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { k 1843 drivers/gpu/drm/radeon/si_dpm.c u32 k = dte_data->k; k 1852 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < k; i++) { k 2485 drivers/gpu/drm/radeon/si_dpm.c if (dte_data->k <= 0) k 2494 drivers/gpu/drm/radeon/si_dpm.c table_size = dte_data->k; k 5360 drivers/gpu/drm/radeon/si_dpm.c u8 i, j, k; k 5371 drivers/gpu/drm/radeon/si_dpm.c for (k = 0; k < table->num_entries; k++) k 5372 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5374 drivers/gpu/drm/radeon/si_dpm.c ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); k 5382 drivers/gpu/drm/radeon/si_dpm.c for (k = 0; k < table->num_entries; k++) { k 5383 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5385 drivers/gpu/drm/radeon/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 5387 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] |= 0x100; k 5396 drivers/gpu/drm/radeon/si_dpm.c for (k = 0; k < table->num_entries; k++) k 5397 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5398 drivers/gpu/drm/radeon/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; k 5408 drivers/gpu/drm/radeon/si_dpm.c for(k = 0; k < table->num_entries; k++) k 5409 drivers/gpu/drm/radeon/si_dpm.c table->mc_reg_table_entry[k].mc_data[j] = k 5411 drivers/gpu/drm/radeon/si_dpm.c (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); k 6813 drivers/gpu/drm/radeon/si_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 6863 drivers/gpu/drm/radeon/si_dpm.c k = 0; k 6869 drivers/gpu/drm/radeon/si_dpm.c if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) k 6875 drivers/gpu/drm/radeon/si_dpm.c &rdev->pm.dpm.ps[i], k, k 6877 drivers/gpu/drm/radeon/si_dpm.c k++; k 75 drivers/gpu/drm/radeon/si_dpm.h u32 k; k 1457 drivers/gpu/drm/radeon/sumo_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 1504 drivers/gpu/drm/radeon/sumo_dpm.c k = 0; k 1508 drivers/gpu/drm/radeon/sumo_dpm.c if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) k 1515 drivers/gpu/drm/radeon/sumo_dpm.c &rdev->pm.dpm.ps[i], k, k 1517 drivers/gpu/drm/radeon/sumo_dpm.c k++; k 1735 drivers/gpu/drm/radeon/trinity_dpm.c int i, j, k, non_clock_array_index, clock_array_index; k 1782 drivers/gpu/drm/radeon/trinity_dpm.c k = 0; k 1788 drivers/gpu/drm/radeon/trinity_dpm.c if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) k 1794 drivers/gpu/drm/radeon/trinity_dpm.c &rdev->pm.dpm.ps[i], k, k 1796 drivers/gpu/drm/radeon/trinity_dpm.c k++; k 502 drivers/gpu/drm/tegra/dc.c unsigned int i, k; k 508 drivers/gpu/drm/tegra/dc.c for (i = 0, k = 128; i < 16; i++, k -= 8) k 509 drivers/gpu/drm/tegra/dc.c tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); k 1123 drivers/gpu/drm/tegra/dsi.c unsigned int i, j, k; k 1175 drivers/gpu/drm/tegra/dsi.c for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) k 1176 drivers/gpu/drm/tegra/dsi.c rx[j + k] = (value >> (k << 3)) & 0xff; k 38 drivers/gpu/drm/udl/udl_transfer.c int j, k; k 53 drivers/gpu/drm/udl/udl_transfer.c for (k = width - 1; k > j; k--) { k 54 drivers/gpu/drm/udl/udl_transfer.c if (back[k] != front[k]) { k 55 drivers/gpu/drm/udl/udl_transfer.c end = k+1; k 157 drivers/gpu/drm/vc4/vc4_gem.c unsigned int i, j, k, unref_list_count; k 193 drivers/gpu/drm/vc4/vc4_gem.c k = 0; k 208 drivers/gpu/drm/vc4/vc4_gem.c kernel_state->bo[k++] = &exec[i]->bo[j]->base; k 216 drivers/gpu/drm/vc4/vc4_gem.c kernel_state->bo[k++] = &bo->base.base; k 220 drivers/gpu/drm/vc4/vc4_gem.c WARN_ON_ONCE(k != state->bo_count); k 2450 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c u32 i, k; k 2467 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c for (k = 0; k < num_units; k++) { k 2468 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c struct vmw_display_unit *unit = units[k]; k 511 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c int i, k; k 518 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c for (i = 0, k = 0; i < VMW_MAX_NUM_STREAMS; i++) k 520 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c k++; k 524 drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c return k; k 625 drivers/hid/hid-debug.c unsigned i,k; k 639 drivers/hid/hid-debug.c for (k = 0; k < report->maxfield; k++) { k 641 drivers/hid/hid-debug.c seq_printf(f, "Field(%d)\n", k); k 642 drivers/hid/hid-debug.c hid_dump_field(report->field[k], 6, f); k 1013 drivers/hid/hid-debug.c int i, j, k; k 1017 drivers/hid/hid-debug.c for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) { k 1018 drivers/hid/hid-debug.c list_for_each_entry(report, &hid->report_enum[k].report_list, list) { k 90 drivers/hid/hid-input.c unsigned int i, j, k, cur_idx = 0; k 94 drivers/hid/hid-input.c for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) { k 95 drivers/hid/hid-input.c list_for_each_entry(report, &hid->report_enum[k].report_list, list) { k 1789 drivers/hid/hid-input.c int i, k; k 1795 drivers/hid/hid-input.c for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) { k 1796 drivers/hid/hid-input.c if (k == HID_OUTPUT_REPORT && k 1800 drivers/hid/hid-input.c list_for_each_entry(report, &hid->report_enum[k].report_list, k 1862 drivers/hid/hid-input.c int i, k; k 1884 drivers/hid/hid-input.c for (k = HID_INPUT_REPORT; k <= HID_OUTPUT_REPORT; k++) { k 1885 drivers/hid/hid-input.c if (k == HID_OUTPUT_REPORT && k 1889 drivers/hid/hid-input.c list_for_each_entry(report, &hid->report_enum[k].report_list, list) { k 75 drivers/hid/hid-picolcd_core.c int i, j, k; k 92 drivers/hid/hid-picolcd_core.c for (i = k = 0; i < report->maxfield; i++) k 94 drivers/hid/hid-picolcd_core.c hid_set_field(report->field[i], j, k < size ? raw_data[k] : 0); k 95 drivers/hid/hid-picolcd_core.c k++; k 761 drivers/hid/usbhid/hid-pidff.c int i, j, k, found; k 763 drivers/hid/usbhid/hid-pidff.c for (k = 0; k < count; k++) { k 773 drivers/hid/usbhid/hid-pidff.c (HID_UP_PID | table[k])) { k 775 drivers/hid/usbhid/hid-pidff.c k, i, j); k 776 drivers/hid/usbhid/hid-pidff.c usage[k].field = report->field[i]; k 777 drivers/hid/usbhid/hid-pidff.c usage[k].value = k 787 drivers/hid/usbhid/hid-pidff.c pr_debug("failed to locate %d\n", k); k 2524 drivers/hid/wacom_sys.c int error, k; k 2529 drivers/hid/wacom_sys.c for (k = 0; k < WACOM_MAX_REMOTES; k++) { k 2530 drivers/hid/wacom_sys.c if (remote->remotes[k].serial == serial) k 2534 drivers/hid/wacom_sys.c if (k < WACOM_MAX_REMOTES) { k 252 drivers/hwmon/i5k_amb.c int i, j, k, d = 0; k 276 drivers/hwmon/i5k_amb.c k = amb_num_from_reg(i, j); k 288 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 303 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 319 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 335 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 351 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 366 drivers/hwmon/i5k_amb.c iattr->s_attr.index = k; k 404 drivers/i2c/busses/i2c-bcm-kona.c int k; k 419 drivers/i2c/busses/i2c-bcm-kona.c for (k = 0; k < len; k++) k 420 drivers/i2c/busses/i2c-bcm-kona.c writel(buf[k], (dev->base + DAT_OFFSET)); k 109 drivers/i2c/busses/i2c-mpc.c int k; k 115 drivers/i2c/busses/i2c-mpc.c for (k = 9; k; k--) { k 803 drivers/i2c/busses/i2c-sh_mobile.c int k = 0, ret; k 805 drivers/i2c/busses/i2c-sh_mobile.c while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { k 814 drivers/i2c/busses/i2c-sh_mobile.c k++; k 817 drivers/i2c/busses/i2c-sh_mobile.c return k > 0 ? 0 : -ENOENT; k 292 drivers/iio/adc/palmas_gpadc.c int k; k 317 drivers/iio/adc/palmas_gpadc.c k = (1000 + (1000 * (d2 - d1)) / (x2 - x1)); k 322 drivers/iio/adc/palmas_gpadc.c adc->adc_info[adc_chan].gain_error = k; k 325 drivers/iio/adc/palmas_gpadc.c adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1); k 902 drivers/iio/adc/ti-ads1015.c unsigned int k; k 920 drivers/iio/adc/ti-ads1015.c for (k = 0; k < ADS1015_CHANNELS; ++k) { k 921 drivers/iio/adc/ti-ads1015.c data->channel_data[k].pga = ADS1015_DEFAULT_PGA; k 922 drivers/iio/adc/ti-ads1015.c data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE; k 215 drivers/iio/adc/ti_am335x_adc.c int i, k, fifo1count, read; k 219 drivers/iio/adc/ti_am335x_adc.c for (k = 0; k < fifo1count; k = k + i) { k 563 drivers/iio/adc/twl6030-gpadc.c int b, k, gain, x1, x2, i; k 576 drivers/iio/adc/twl6030-gpadc.c k = 1000 + (((d2 - d1) * 1000) / (x2 - x1)); k 579 drivers/iio/adc/twl6030-gpadc.c b = (d1 * 1000) - (k - 1000) * x1; k 582 drivers/iio/adc/twl6030-gpadc.c gpadc->twl6030_cal_tbl[i].gain_error = k; k 590 drivers/iio/adc/twl6030-gpadc.c dev_dbg(gpadc->dev, "GPADC k for Chn: %d = %d\n", channel, k); k 595 drivers/infiniband/core/umem_odp.c int j, k, ret = 0, start_idx, npages = 0; k 631 drivers/infiniband/core/umem_odp.c k = start_idx; k 673 drivers/infiniband/core/umem_odp.c umem_odp, k, local_page_list[j], k 684 drivers/infiniband/core/umem_odp.c k++; k 702 drivers/infiniband/core/umem_odp.c if (npages < 0 && k == start_idx) k 705 drivers/infiniband/core/umem_odp.c ret = k - start_idx; k 342 drivers/infiniband/hw/bnxt_re/qplib_res.c int i, j, k, rc = 0; k 413 drivers/infiniband/hw/bnxt_re/qplib_res.c for (k = 0; k < ctx->tqm_tbl[i].pbl[PBL_LVL_1].pg_count; k 414 drivers/infiniband/hw/bnxt_re/qplib_res.c k++) k 415 drivers/infiniband/hw/bnxt_re/qplib_res.c pbl_ptr[PTR_PG(j + k)][PTR_IDX(j + k)] = k 417 drivers/infiniband/hw/bnxt_re/qplib_res.c ctx->tqm_tbl[i].pbl[PBL_LVL_1].pg_map_arr[k] k 3045 drivers/infiniband/hw/hns/hns_roce_hw_v2.c int i, j, k; k 3060 drivers/infiniband/hw/hns/hns_roce_hw_v2.c k = mhop.l2_idx; k 3066 drivers/infiniband/hw/hns/hns_roce_hw_v2.c k; k 143 drivers/infiniband/hw/i40iw/i40iw_ctrl.c u32 k = 0; k 158 drivers/infiniband/hw/i40iw/i40iw_ctrl.c k = i; k 171 drivers/infiniband/hw/i40iw/i40iw_ctrl.c size = info[k].cnt * info[k].size + info[k].base; k 584 drivers/infiniband/hw/mlx4/alias_GUID.c int j, k, entry; k 589 drivers/infiniband/hw/mlx4/alias_GUID.c for (k = 0; k < NUM_ALIAS_GUID_IN_REC; k++) { k 590 drivers/infiniband/hw/mlx4/alias_GUID.c entry = j * NUM_ALIAS_GUID_IN_REC + k; k 598 drivers/infiniband/hw/mlx4/alias_GUID.c [GUID_REC_SIZE * k] = guid; k 1435 drivers/infiniband/hw/mlx4/main.c int i, j, k; k 1449 drivers/infiniband/hw/mlx4/main.c for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS && k 1450 drivers/infiniband/hw/mlx4/main.c j < flow_attr->num_of_specs; k++) { k 1456 drivers/infiniband/hw/mlx4/main.c (pdefault_rules->mandatory_fields[k] & k 1459 drivers/infiniband/hw/mlx4/main.c pdefault_rules->mandatory_fields[k])) k 1464 drivers/infiniband/hw/mlx4/main.c pdefault_rules->mandatory_fields[k]) { k 1474 drivers/infiniband/hw/mlx4/main.c for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++) k 1477 drivers/infiniband/hw/mlx4/main.c pdefault_rules->mandatory_not_fields[k]) k 104 drivers/infiniband/hw/mlx4/mr.c int k; k 126 drivers/infiniband/hw/mlx4/mr.c for (k = 0; k < mtt_entries; ++k) { k 127 drivers/infiniband/hw/mlx4/mr.c pages[*npages] = cur_start_addr + (mtt_size * k); k 134 drivers/infiniband/hw/mlx5/mem.c int i, k, idx; k 167 drivers/infiniband/hw/mlx5/mem.c k = (offset << shift) - i; k 170 drivers/infiniband/hw/mlx5/mem.c k = 0; k 173 drivers/infiniband/hw/mlx5/mem.c for (; k < len; k++) { k 175 drivers/infiniband/hw/mlx5/mem.c cur = base + (k << PAGE_SHIFT); k 347 drivers/input/input-mt.c int i, k, sum; k 349 drivers/input/input-mt.c for (k = 0; k < nrc; k++) { k 863 drivers/input/input.c u8 *k = (u8 *)dev->keycode; k 864 drivers/input/input.c *old_keycode = k[index]; k 865 drivers/input/input.c k[index] = ke->keycode; k 869 drivers/input/input.c u16 *k = (u16 *)dev->keycode; k 870 drivers/input/input.c *old_keycode = k[index]; k 871 drivers/input/input.c k[index] = ke->keycode; k 875 drivers/input/input.c u32 *k = (u32 *)dev->keycode; k 876 drivers/input/input.c *old_keycode = k[index]; k 877 drivers/input/input.c k[index] = ke->keycode; k 574 drivers/input/joystick/sidewinder.c int i, j, k, l; k 637 drivers/input/joystick/sidewinder.c k = SW_FAIL; /* Try SW_FAIL times */ k 641 drivers/input/joystick/sidewinder.c k--; k 644 drivers/input/joystick/sidewinder.c dbg("Init 3: Mode %d. Length %d. Last %d. Tries %d.", m, i, l, k); k 695 drivers/input/joystick/sidewinder.c } while (k && sw->type == -1); k 714 drivers/input/joystick/sidewinder.c k = i; k 763 drivers/input/joystick/sidewinder.c dbg("%s%s [%d-bit id %d data %d]\n", sw->name, comment, m, l, k); k 134 drivers/input/joystick/tmdc.c int i[2], j[2], t[2], p, k; k 138 drivers/input/joystick/tmdc.c for (k = 0; k < 2; k++) { k 139 drivers/input/joystick/tmdc.c t[k] = gameport_time(gameport, TMDC_MAX_START); k 140 drivers/input/joystick/tmdc.c i[k] = j[k] = 0; k 152 drivers/input/joystick/tmdc.c for (k = 0, v = w, u = x; k < 2; k++, v >>= 2, u >>= 2) { k 154 drivers/input/joystick/tmdc.c if (t[k] <= 0 || i[k] >= TMDC_MAX_LENGTH) continue; k 155 drivers/input/joystick/tmdc.c t[k] = p; k 156 drivers/input/joystick/tmdc.c if (j[k] == 0) { /* Start bit */ k 157 drivers/input/joystick/tmdc.c if (~v & 1) t[k] = 0; k 158 drivers/input/joystick/tmdc.c data[k][i[k]] = 0; j[k]++; continue; k 160 drivers/input/joystick/tmdc.c if (j[k] == 9) { /* Stop bit */ k 161 drivers/input/joystick/tmdc.c if (v & 1) t[k] = 0; k 162 drivers/input/joystick/tmdc.c j[k] = 0; i[k]++; continue; k 164 drivers/input/joystick/tmdc.c data[k][i[k]] |= (~v & 1) << (j[k]++ - 1); /* Data bit */ k 166 drivers/input/joystick/tmdc.c t[k]--; k 177 drivers/input/joystick/tmdc.c int i, k, l; k 207 drivers/input/joystick/tmdc.c for (k = l = 0; k < 4; k++) { k 208 drivers/input/joystick/tmdc.c for (i = 0; i < port->btnc[k]; i++) k 210 drivers/input/joystick/tmdc.c ((data[tmdc_byte_d[k]] >> (i + port->btno[k])) & 1)); k 211 drivers/input/joystick/tmdc.c l += port->btnc[k]; k 75 drivers/input/keyboard/sh_keysc.c int k; k 77 drivers/input/keyboard/sh_keysc.c for (k = 0; k < BITS_TO_LONGS(SH_KEYSC_MAXKEYS); k++) k 78 drivers/input/keyboard/sh_keysc.c dev_dbg(dev, "%s[%d] 0x%lx\n", str, k, map[k]); k 92 drivers/input/keyboard/sh_keysc.c int i, k, n; k 114 drivers/input/keyboard/sh_keysc.c for (k = 0; k < keyin_nr; k++) { k 115 drivers/input/keyboard/sh_keysc.c if (tmp & (1 << k)) k 116 drivers/input/keyboard/sh_keysc.c __set_bit(n + k, keys); k 138 drivers/input/keyboard/sh_keysc.c k = pdata->keycodes[i]; k 139 drivers/input/keyboard/sh_keysc.c if (!k) k 146 drivers/input/keyboard/sh_keysc.c input_event(priv->input, EV_KEY, k, 1); k 151 drivers/input/keyboard/sh_keysc.c input_event(priv->input, EV_KEY, k, 0); k 801 drivers/input/misc/cm109.c unsigned short k = keymap(i); k 802 drivers/input/misc/cm109.c dev->keymap[i] = k; k 803 drivers/input/misc/cm109.c __set_bit(k, input_dev->keybit); k 60 drivers/input/misc/yealink.c #define _LOC(k,l) { .a = (k), .m = (l) } k 956 drivers/input/misc/yealink.c int k = map_p1k_to_key(i); k 957 drivers/input/misc/yealink.c if (k >= 0) { k 958 drivers/input/misc/yealink.c set_bit(k & 0xff, input_dev->keybit); k 959 drivers/input/misc/yealink.c if (k >> 8) k 960 drivers/input/misc/yealink.c set_bit(k >> 8, input_dev->keybit); k 23 drivers/input/sparse-keymap.c const struct key_entry *k) k 30 drivers/input/sparse-keymap.c if (key == k) k 50 drivers/input/touchscreen/cyttsp4_core.c int i, k; k 60 drivers/input/touchscreen/cyttsp4_core.c for (i = k = 0; i < size && k < max; i++, k += 3) k 61 drivers/input/touchscreen/cyttsp4_core.c scnprintf(pr_buf + k, CY_MAX_PRBUF_SIZE, fmt, dptr[i]); k 306 drivers/irqchip/irq-renesas-intc-irqpin.c int k; k 308 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < 8; k++) { k 309 drivers/irqchip/irq-renesas-intc-irqpin.c if (reg_source & BIT(7 - k)) { k 310 drivers/irqchip/irq-renesas-intc-irqpin.c if (BIT(k) & p->shared_irq_mask) k 313 drivers/irqchip/irq-renesas-intc-irqpin.c status |= intc_irqpin_irq_handler(irq, &p->irq[k]); k 389 drivers/irqchip/irq-renesas-intc-irqpin.c int k; k 412 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { k 413 drivers/irqchip/irq-renesas-intc-irqpin.c io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); k 414 drivers/irqchip/irq-renesas-intc-irqpin.c if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) { k 422 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < INTC_IRQPIN_MAX; k++) { k 423 drivers/irqchip/irq-renesas-intc-irqpin.c irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); k 427 drivers/irqchip/irq-renesas-intc-irqpin.c p->irq[k].p = p; k 428 drivers/irqchip/irq-renesas-intc-irqpin.c p->irq[k].requested_irq = irq->start; k 431 drivers/irqchip/irq-renesas-intc-irqpin.c nirqs = k; k 439 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { k 440 drivers/irqchip/irq-renesas-intc-irqpin.c i = &p->iomem[k]; k 443 drivers/irqchip/irq-renesas-intc-irqpin.c if (!io[k]) k 446 drivers/irqchip/irq-renesas-intc-irqpin.c switch (resource_size(io[k])) { k 463 drivers/irqchip/irq-renesas-intc-irqpin.c i->iomem = devm_ioremap_nocache(dev, io[k]->start, k 464 drivers/irqchip/irq-renesas-intc-irqpin.c resource_size(io[k])); k 482 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < nirqs; k++) k 483 drivers/irqchip/irq-renesas-intc-irqpin.c intc_irqpin_mask_unmask_prio(p, k, 1); k 491 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 1; k < nirqs; k++) { k 492 drivers/irqchip/irq-renesas-intc-irqpin.c if (ref_irq != p->irq[k].requested_irq) { k 538 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < nirqs; k++) { k 539 drivers/irqchip/irq-renesas-intc-irqpin.c if (devm_request_irq(dev, p->irq[k].requested_irq, k 541 drivers/irqchip/irq-renesas-intc-irqpin.c &p->irq[k])) { k 550 drivers/irqchip/irq-renesas-intc-irqpin.c for (k = 0; k < nirqs; k++) k 551 drivers/irqchip/irq-renesas-intc-irqpin.c intc_irqpin_mask_unmask_prio(p, k, 0); k 131 drivers/irqchip/irq-renesas-irqc.c int k; k 144 drivers/irqchip/irq-renesas-irqc.c for (k = 0; k < IRQC_IRQ_MAX; k++) { k 145 drivers/irqchip/irq-renesas-irqc.c irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); k 149 drivers/irqchip/irq-renesas-irqc.c p->irq[k].p = p; k 150 drivers/irqchip/irq-renesas-irqc.c p->irq[k].hw_irq = k; k 151 drivers/irqchip/irq-renesas-irqc.c p->irq[k].requested_irq = irq->start; k 154 drivers/irqchip/irq-renesas-irqc.c p->number_of_irqs = k; k 198 drivers/irqchip/irq-renesas-irqc.c for (k = 0; k < p->number_of_irqs; k++) { k 199 drivers/irqchip/irq-renesas-irqc.c if (devm_request_irq(dev, p->irq[k].requested_irq, k 200 drivers/irqchip/irq-renesas-irqc.c irqc_irq_handler, 0, name, &p->irq[k])) { k 942 drivers/isdn/hardware/mISDN/hfcsusb.c int k; k 952 drivers/isdn/hardware/mISDN/hfcsusb.c for (k = 0; k < num_packets; k++) { k 953 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].offset = packet_size * k; k 954 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].length = packet_size; k 955 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].actual_length = 0; k 966 drivers/isdn/hardware/mISDN/hfcsusb.c int k, len, errcode, offset, num_isoc_packets, fifon, maxlen, k 1004 drivers/isdn/hardware/mISDN/hfcsusb.c for (k = 0; k < num_isoc_packets; ++k) { k 1005 drivers/isdn/hardware/mISDN/hfcsusb.c len = urb->iso_frame_desc[k].actual_length; k 1006 drivers/isdn/hardware/mISDN/hfcsusb.c offset = urb->iso_frame_desc[k].offset; k 1008 drivers/isdn/hardware/mISDN/hfcsusb.c iso_status = urb->iso_frame_desc[k].status; k 1013 drivers/isdn/hardware/mISDN/hfcsusb.c hw->name, __func__, k, iso_status); k 1022 drivers/isdn/hardware/mISDN/hfcsusb.c k, num_isoc_packets - 1, k 1161 drivers/isdn/hardware/mISDN/hfcsusb.c int k, tx_offset, num_isoc_packets, sink, remain, current_len, k 1231 drivers/isdn/hardware/mISDN/hfcsusb.c for (k = 0; k < num_isoc_packets; ++k) { k 1234 drivers/isdn/hardware/mISDN/hfcsusb.c errcode = urb->iso_frame_desc[k].status; k 1238 drivers/isdn/hardware/mISDN/hfcsusb.c hw->name, __func__, k, errcode); k 1286 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].offset = tx_offset; k 1287 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].length = current_len + 1; k 1295 drivers/isdn/hardware/mISDN/hfcsusb.c k, num_isoc_packets - 1, k 1296 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].offset, k 1297 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].length); k 1299 drivers/isdn/hardware/mISDN/hfcsusb.c for (i = urb->iso_frame_desc[k].offset; k 1300 drivers/isdn/hardware/mISDN/hfcsusb.c i < (urb->iso_frame_desc[k].offset k 1301 drivers/isdn/hardware/mISDN/hfcsusb.c + urb->iso_frame_desc[k].length); k 1312 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].offset = tx_offset++; k 1313 drivers/isdn/hardware/mISDN/hfcsusb.c urb->iso_frame_desc[k].length = 1; k 1382 drivers/isdn/hardware/mISDN/hfcsusb.c int i, k, errcode; k 1416 drivers/isdn/hardware/mISDN/hfcsusb.c for (k = 0; k < num_packets_per_urb; k++) { k 1418 drivers/isdn/hardware/mISDN/hfcsusb.c iso_frame_desc[k].offset = k 1419 drivers/isdn/hardware/mISDN/hfcsusb.c k * packet_size; k 1421 drivers/isdn/hardware/mISDN/hfcsusb.c iso_frame_desc[k].length = k 193 drivers/isdn/mISDN/dsp_audio.c int i, j, k; k 200 drivers/isdn/mISDN/dsp_audio.c for (k = 0; k < 256; k++) { k 201 drivers/isdn/mISDN/dsp_audio.c if (dsp_audio_alaw_to_s32[k] k 462 drivers/isdn/mISDN/dsp_blowfish.c u8 k = dsp->bf_decrypt_out_pos; k 479 drivers/isdn/mISDN/dsp_blowfish.c *data++ = bf_data_out[k++]; k 481 drivers/isdn/mISDN/dsp_blowfish.c if (k == 9) k 482 drivers/isdn/mISDN/dsp_blowfish.c k = 0; /* repeat if no sync has been found */ k 551 drivers/isdn/mISDN/dsp_blowfish.c k = 0; /* start with new decoded frame */ k 556 drivers/isdn/mISDN/dsp_blowfish.c dsp->bf_decrypt_out_pos = k; k 740 drivers/isdn/mISDN/dsp_core.c int k; k 746 drivers/isdn/mISDN/dsp_core.c k = *digits | DTMF_TONE_VAL; k 748 drivers/isdn/mISDN/dsp_core.c MISDN_ID_ANY, sizeof(int), &k, k 786 drivers/isdn/mISDN/dsp_core.c int k; k 792 drivers/isdn/mISDN/dsp_core.c k = *digits | DTMF_TONE_VAL; k 794 drivers/isdn/mISDN/dsp_core.c MISDN_ID_ANY, sizeof(int), &k, k 124 drivers/isdn/mISDN/dsp_dtmf.c int k, n, i; k 158 drivers/isdn/mISDN/dsp_dtmf.c for (k = 0; k < NCOEFF; k++) { k 166 drivers/isdn/mISDN/dsp_dtmf.c result[k] = k 168 drivers/isdn/mISDN/dsp_dtmf.c (((cos2pik[k] * sk) >> 15) * sk2) + k 184 drivers/isdn/mISDN/dsp_dtmf.c for (k = 0; k < NCOEFF; k++) { k 189 drivers/isdn/mISDN/dsp_dtmf.c cos2pik_ = cos2pik[k]; k 200 drivers/isdn/mISDN/dsp_dtmf.c result[k] = k 202 drivers/isdn/mISDN/dsp_dtmf.c (((cos2pik[k] * sk) >> 15) * sk2) + k 481 drivers/md/bcache/alloc.c void bch_bucket_free(struct cache_set *c, struct bkey *k) k 485 drivers/md/bcache/alloc.c for (i = 0; i < KEY_PTRS(k); i++) k 486 drivers/md/bcache/alloc.c __bch_bucket_free(PTR_CACHE(c, k, i), k 487 drivers/md/bcache/alloc.c PTR_BUCKET(c, k, i)); k 491 drivers/md/bcache/alloc.c struct bkey *k, int n, bool wait) k 502 drivers/md/bcache/alloc.c bkey_init(k); k 513 drivers/md/bcache/alloc.c k->ptr[i] = MAKE_PTR(ca->buckets[b].gen, k 517 drivers/md/bcache/alloc.c SET_KEY_PTRS(k, i + 1); k 522 drivers/md/bcache/alloc.c bch_bucket_free(c, k); k 523 drivers/md/bcache/alloc.c bkey_put(c, k); k 528 drivers/md/bcache/alloc.c struct bkey *k, int n, bool wait) k 533 drivers/md/bcache/alloc.c ret = __bch_bucket_alloc_set(c, reserve, k, n, wait); k 614 drivers/md/bcache/alloc.c struct bkey *k, k 634 drivers/md/bcache/alloc.c while (!(b = pick_data_bucket(c, k, write_point, &alloc.key))) { k 661 drivers/md/bcache/alloc.c k->ptr[i] = b->key.ptr[i]; k 665 drivers/md/bcache/alloc.c SET_KEY_OFFSET(k, KEY_OFFSET(k) + sectors); k 666 drivers/md/bcache/alloc.c SET_KEY_SIZE(k, sectors); k 667 drivers/md/bcache/alloc.c SET_KEY_PTRS(k, KEY_PTRS(&b->key)); k 674 drivers/md/bcache/alloc.c bkey_copy_key(&b->key, k); k 736 drivers/md/bcache/alloc.c struct task_struct *k = kthread_run(bch_allocator_thread, k 738 drivers/md/bcache/alloc.c if (IS_ERR(k)) k 739 drivers/md/bcache/alloc.c return PTR_ERR(k); k 741 drivers/md/bcache/alloc.c ca->alloc_thread = k; k 783 drivers/md/bcache/bcache.h const struct bkey *k, k 786 drivers/md/bcache/bcache.h return c->cache[PTR_DEV(k, ptr)]; k 790 drivers/md/bcache/bcache.h const struct bkey *k, k 793 drivers/md/bcache/bcache.h return sector_to_bucket(c, PTR_OFFSET(k, ptr)); k 797 drivers/md/bcache/bcache.h const struct bkey *k, k 800 drivers/md/bcache/bcache.h return PTR_CACHE(c, k, ptr)->buckets + PTR_BUCKET_NR(c, k, ptr); k 810 drivers/md/bcache/bcache.h static inline uint8_t ptr_stale(struct cache_set *c, const struct bkey *k, k 813 drivers/md/bcache/bcache.h return gen_after(PTR_BUCKET(c, k, i)->gen, PTR_GEN(k, i)); k 816 drivers/md/bcache/bcache.h static inline bool ptr_available(struct cache_set *c, const struct bkey *k, k 819 drivers/md/bcache/bcache.h return (PTR_DEV(k, i) < MAX_CACHES_PER_SET) && PTR_CACHE(c, k, i); k 959 drivers/md/bcache/bcache.h struct bkey *k, unsigned int ptr); k 968 drivers/md/bcache/bcache.h void bch_bucket_free(struct cache_set *c, struct bkey *k); k 972 drivers/md/bcache/bcache.h struct bkey *k, int n, bool wait); k 974 drivers/md/bcache/bcache.h struct bkey *k, int n, bool wait); k 975 drivers/md/bcache/bcache.h bool bch_alloc_sectors(struct cache_set *c, struct bkey *k, k 23 drivers/md/bcache/bset.c struct bkey *k, *next; k 25 drivers/md/bcache/bset.c for (k = i->start; k < bset_bkey_last(i); k = next) { k 26 drivers/md/bcache/bset.c next = bkey_next(k); k 29 drivers/md/bcache/bset.c (unsigned int) ((u64 *) k - i->d), i->keys); k 32 drivers/md/bcache/bset.c b->ops->key_dump(b, k); k 34 drivers/md/bcache/bset.c pr_err("%llu:%llu\n", KEY_INODE(k), KEY_OFFSET(k)); k 37 drivers/md/bcache/bset.c bkey_cmp(k, b->ops->is_extents ? k 58 drivers/md/bcache/bset.c struct bkey *k; k 61 drivers/md/bcache/bset.c for_each_key(b, k, &iter) k 62 drivers/md/bcache/bset.c ret += KEY_SIZE(k); k 69 drivers/md/bcache/bset.c struct bkey *k, *p = NULL; k 73 drivers/md/bcache/bset.c for_each_key(b, k, &iter) { k 76 drivers/md/bcache/bset.c if (p && bkey_cmp(&START_KEY(p), &START_KEY(k)) > 0) k 79 drivers/md/bcache/bset.c if (bch_ptr_invalid(b, k)) k 83 drivers/md/bcache/bset.c if (p && bkey_cmp(p, &START_KEY(k)) > 0) k 86 drivers/md/bcache/bset.c if (bch_ptr_bad(b, k)) k 90 drivers/md/bcache/bset.c if (p && !bkey_cmp(p, k)) k 93 drivers/md/bcache/bset.c p = k; k 113 drivers/md/bcache/bset.c struct bkey *k = iter->data->k, *next = bkey_next(k); k 116 drivers/md/bcache/bset.c bkey_cmp(k, iter->b->ops->is_extents ? k 160 drivers/md/bcache/bset.c struct bkey *k = l->keys; k 162 drivers/md/bcache/bset.c if (k == l->top) k 165 drivers/md/bcache/bset.c while (bkey_next(k) != l->top) k 166 drivers/md/bcache/bset.c k = bkey_next(k); k 168 drivers/md/bcache/bset.c return l->top = k; k 195 drivers/md/bcache/bset.c bool __bch_cut_front(const struct bkey *where, struct bkey *k) k 199 drivers/md/bcache/bset.c if (bkey_cmp(where, &START_KEY(k)) <= 0) k 202 drivers/md/bcache/bset.c if (bkey_cmp(where, k) < 0) k 203 drivers/md/bcache/bset.c len = KEY_OFFSET(k) - KEY_OFFSET(where); k 205 drivers/md/bcache/bset.c bkey_copy_key(k, where); k 207 drivers/md/bcache/bset.c for (i = 0; i < KEY_PTRS(k); i++) k 208 drivers/md/bcache/bset.c SET_PTR_OFFSET(k, i, PTR_OFFSET(k, i) + KEY_SIZE(k) - len); k 210 drivers/md/bcache/bset.c BUG_ON(len > KEY_SIZE(k)); k 211 drivers/md/bcache/bset.c SET_KEY_SIZE(k, len); k 215 drivers/md/bcache/bset.c bool __bch_cut_back(const struct bkey *where, struct bkey *k) k 219 drivers/md/bcache/bset.c if (bkey_cmp(where, k) >= 0) k 222 drivers/md/bcache/bset.c BUG_ON(KEY_INODE(where) != KEY_INODE(k)); k 224 drivers/md/bcache/bset.c if (bkey_cmp(where, &START_KEY(k)) > 0) k 225 drivers/md/bcache/bset.c len = KEY_OFFSET(where) - KEY_START(k); k 227 drivers/md/bcache/bset.c bkey_copy_key(k, where); k 229 drivers/md/bcache/bset.c BUG_ON(len > KEY_SIZE(k)); k 230 drivers/md/bcache/bset.c SET_KEY_SIZE(k, len); k 533 drivers/md/bcache/bset.c static unsigned int bkey_to_cacheline(struct bset_tree *t, struct bkey *k) k 535 drivers/md/bcache/bset.c return ((void *) k - (void *) t->data) / BSET_CACHELINE; k 540 drivers/md/bcache/bset.c struct bkey *k) k 542 drivers/md/bcache/bset.c return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); k 585 drivers/md/bcache/bset.c static inline unsigned int bfloat_mantissa(const struct bkey *k, k 588 drivers/md/bcache/bset.c const uint64_t *p = &k->low - (f->exponent >> 6); k 695 drivers/md/bcache/bset.c struct bkey *prev = NULL, *k = t->data->start; k 717 drivers/md/bcache/bset.c while (bkey_to_cacheline(t, k) < cacheline) k 718 drivers/md/bcache/bset.c prev = k, k = bkey_next(k); k 721 drivers/md/bcache/bset.c t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); k 724 drivers/md/bcache/bset.c while (bkey_next(k) != bset_bkey_last(t->data)) k 725 drivers/md/bcache/bset.c k = bkey_next(k); k 727 drivers/md/bcache/bset.c t->end = *k; k 739 drivers/md/bcache/bset.c void bch_bset_fix_invalidated_key(struct btree_keys *b, struct bkey *k) k 745 drivers/md/bcache/bset.c if (k < bset_bkey_last(t->data)) k 753 drivers/md/bcache/bset.c inorder = bkey_to_cacheline(t, k); k 755 drivers/md/bcache/bset.c if (k == t->data->start) k 758 drivers/md/bcache/bset.c if (bkey_next(k) == bset_bkey_last(t->data)) { k 759 drivers/md/bcache/bset.c t->end = *k; k 767 drivers/md/bcache/bset.c k == tree_to_bkey(t, j)) k 777 drivers/md/bcache/bset.c k == tree_to_prev_bkey(t, j)) k 787 drivers/md/bcache/bset.c struct bkey *k) k 789 drivers/md/bcache/bset.c unsigned int shift = bkey_u64s(k); k 790 drivers/md/bcache/bset.c unsigned int j = bkey_to_cacheline(t, k); k 802 drivers/md/bcache/bset.c table_to_bkey(t, j) <= k) k 813 drivers/md/bcache/bset.c k = table_to_bkey(t, j - 1); k 815 drivers/md/bcache/bset.c while (k < cacheline_to_bkey(t, j, 0)) k 816 drivers/md/bcache/bset.c k = bkey_next(k); k 818 drivers/md/bcache/bset.c t->prev[j] = bkey_to_cacheline_offset(t, j, k); k 827 drivers/md/bcache/bset.c for (k = table_to_bkey(t, t->size - 1); k 828 drivers/md/bcache/bset.c k != bset_bkey_last(t->data); k 829 drivers/md/bcache/bset.c k = bkey_next(k)) k 830 drivers/md/bcache/bset.c if (t->size == bkey_to_cacheline(t, k)) { k 832 drivers/md/bcache/bset.c bkey_to_cacheline_offset(t, t->size, k); k 880 drivers/md/bcache/bset.c unsigned int bch_btree_insert_key(struct btree_keys *b, struct bkey *k, k 890 drivers/md/bcache/bset.c BUG_ON(b->ops->is_extents && !KEY_SIZE(k)); k 898 drivers/md/bcache/bset.c preceding_key(&START_KEY(k), &preceding_key_p); k 900 drivers/md/bcache/bset.c preceding_key(k, &preceding_key_p); k 904 drivers/md/bcache/bset.c if (b->ops->insert_fixup(b, k, &iter, replace_key)) k 910 drivers/md/bcache/bset.c bkey_cmp(k, b->ops->is_extents ? &START_KEY(m) : m) > 0) k 916 drivers/md/bcache/bset.c bch_bkey_try_merge(b, prev, k)) k 921 drivers/md/bcache/bset.c KEY_PTRS(m) == KEY_PTRS(k) && !KEY_SIZE(m)) k 926 drivers/md/bcache/bset.c bch_bkey_try_merge(b, k, m)) k 929 drivers/md/bcache/bset.c bch_bset_insert(b, m, k); k 930 drivers/md/bcache/bset.c copy: bkey_copy(m, k); k 1090 drivers/md/bcache/bset.c return bkey_cmp(l.k, r.k) > 0; k 1098 drivers/md/bcache/bset.c void bch_btree_iter_push(struct btree_iter *iter, struct bkey *k, k 1101 drivers/md/bcache/bset.c if (k != end) k 1103 drivers/md/bcache/bset.c ((struct btree_iter_set) { k, end }), k 1146 drivers/md/bcache/bset.c ret = iter->data->k; k 1147 drivers/md/bcache/bset.c iter->data->k = bkey_next(iter->data->k); k 1149 drivers/md/bcache/bset.c if (iter->data->k > iter->data->end) { k 1151 drivers/md/bcache/bset.c iter->data->k = iter->data->end; k 1154 drivers/md/bcache/bset.c if (iter->data->k == iter->data->end) k 1206 drivers/md/bcache/bset.c struct bkey *k, *last = NULL; k 1207 drivers/md/bcache/bset.c BKEY_PADDED(k) tmp; k 1218 drivers/md/bcache/bset.c k = b->ops->sort_fixup(iter, &tmp.k); k 1220 drivers/md/bcache/bset.c k = NULL; k 1222 drivers/md/bcache/bset.c if (!k) k 1223 drivers/md/bcache/bset.c k = __bch_btree_iter_next(iter, b->ops->sort_cmp); k 1225 drivers/md/bcache/bset.c if (bad(b, k)) k 1230 drivers/md/bcache/bset.c bkey_copy(last, k); k 1231 drivers/md/bcache/bset.c } else if (!bch_bkey_try_merge(b, last, k)) { k 1233 drivers/md/bcache/bset.c bkey_copy(last, k); k 199 drivers/md/bcache/bset.h const struct bkey *k); k 201 drivers/md/bcache/bset.h const struct bkey *k); k 206 drivers/md/bcache/bset.h const struct bkey *k); k 208 drivers/md/bcache/bset.h const struct bkey *k); k 244 drivers/md/bcache/bset.h static inline bool bkey_written(struct btree_keys *b, struct bkey *k) k 246 drivers/md/bcache/bset.h return !b->last_set_unwritten || k < b->set[b->nsets].data->start; k 261 drivers/md/bcache/bset.h #define __set_bytes(i, k) (sizeof(*(i)) + (k) * sizeof(uint64_t)) k 264 drivers/md/bcache/bset.h #define __set_blocks(i, k, block_bytes) \ k 265 drivers/md/bcache/bset.h DIV_ROUND_UP(__set_bytes(i, k), block_bytes) k 300 drivers/md/bcache/bset.h void bch_bset_fix_invalidated_key(struct btree_keys *b, struct bkey *k); k 304 drivers/md/bcache/bset.h unsigned int bch_btree_insert_key(struct btree_keys *b, struct bkey *k, k 323 drivers/md/bcache/bset.h struct bkey *k, *end; k 327 drivers/md/bcache/bset.h typedef bool (*ptr_filter_fn)(struct btree_keys *b, const struct bkey *k); k 334 drivers/md/bcache/bset.h void bch_btree_iter_push(struct btree_iter *iter, struct bkey *k, k 353 drivers/md/bcache/bset.h #define for_each_key_filter(b, k, iter, filter) \ k 355 drivers/md/bcache/bset.h ((k) = bch_btree_iter_next_filter((iter), (b), filter));) k 357 drivers/md/bcache/bset.h #define for_each_key(b, k, iter) \ k 359 drivers/md/bcache/bset.h ((k) = bch_btree_iter_next(iter));) k 408 drivers/md/bcache/bset.h static inline void bkey_init(struct bkey *k) k 410 drivers/md/bcache/bset.h *k = ZERO_KEY; k 423 drivers/md/bcache/bset.h bool __bch_cut_front(const struct bkey *where, struct bkey *k); k 424 drivers/md/bcache/bset.h bool __bch_cut_back(const struct bkey *where, struct bkey *k); k 426 drivers/md/bcache/bset.h static inline bool bch_cut_front(const struct bkey *where, struct bkey *k) k 428 drivers/md/bcache/bset.h BUG_ON(bkey_cmp(where, k) > 0); k 429 drivers/md/bcache/bset.h return __bch_cut_front(where, k); k 432 drivers/md/bcache/bset.h static inline bool bch_cut_back(const struct bkey *where, struct bkey *k) k 434 drivers/md/bcache/bset.h BUG_ON(bkey_cmp(where, &START_KEY(k)) < 0); k 435 drivers/md/bcache/bset.h return __bch_cut_back(where, k); k 447 drivers/md/bcache/bset.h static inline void preceding_key(struct bkey *k, struct bkey **preceding_key_p) k 449 drivers/md/bcache/bset.h if (KEY_INODE(k) || KEY_OFFSET(k)) { k 450 drivers/md/bcache/bset.h (**preceding_key_p) = KEY(KEY_INODE(k), KEY_OFFSET(k), 0); k 459 drivers/md/bcache/bset.h static inline bool bch_ptr_invalid(struct btree_keys *b, const struct bkey *k) k 461 drivers/md/bcache/bset.h return b->ops->key_invalid(b, k); k 464 drivers/md/bcache/bset.h static inline bool bch_ptr_bad(struct btree_keys *b, const struct bkey *k) k 466 drivers/md/bcache/bset.h return b->ops->key_bad(b, k); k 470 drivers/md/bcache/bset.h size_t size, const struct bkey *k) k 472 drivers/md/bcache/bset.h return b->ops->key_to_text(buf, size, k); k 505 drivers/md/bcache/bset.h static inline void bch_keylist_init_single(struct keylist *l, struct bkey *k) k 507 drivers/md/bcache/bset.h l->keys = k; k 508 drivers/md/bcache/bset.h l->top = bkey_next(k); k 516 drivers/md/bcache/bset.h static inline void bch_keylist_add(struct keylist *l, struct bkey *k) k 518 drivers/md/bcache/bset.h bkey_copy(l->top, k); k 99 drivers/md/bcache/btree.c #define PTR_HASH(c, k) \ k 100 drivers/md/bcache/btree.c (((k)->ptr[0] >> c->bucket_bits) | PTR_GEN(k, 0)) k 184 drivers/md/bcache/btree.c void bkey_put(struct cache_set *c, struct bkey *k) k 188 drivers/md/bcache/btree.c for (i = 0; i < KEY_PTRS(k); i++) k 189 drivers/md/bcache/btree.c if (ptr_available(c, k, i)) k 190 drivers/md/bcache/btree.c atomic_dec_bug(&PTR_BUCKET(c, k, i)->pin); k 398 drivers/md/bcache/btree.c BKEY_PADDED(key) k; k 427 drivers/md/bcache/btree.c bkey_copy(&k.key, &b->key); k 428 drivers/md/bcache/btree.c SET_PTR_OFFSET(&k.key, 0, PTR_OFFSET(&k.key, 0) + k 441 drivers/md/bcache/btree.c bch_submit_bbio(b->bio, b->c, &k.key, 0); k 452 drivers/md/bcache/btree.c bch_submit_bbio(b->bio, b->c, &k.key, 0); k 594 drivers/md/bcache/btree.c static unsigned int btree_order(struct bkey *k) k 596 drivers/md/bcache/btree.c return ilog2(KEY_SIZE(k) / PAGE_SECTORS ?: 1); k 599 drivers/md/bcache/btree.c static void mca_data_alloc(struct btree *b, struct bkey *k, gfp_t gfp) k 604 drivers/md/bcache/btree.c btree_order(k)), k 614 drivers/md/bcache/btree.c struct bkey *k, gfp_t gfp) k 634 drivers/md/bcache/btree.c mca_data_alloc(b, k, gfp); k 868 drivers/md/bcache/btree.c static struct hlist_head *mca_hash(struct cache_set *c, struct bkey *k) k 870 drivers/md/bcache/btree.c return &c->bucket_hash[hash_32(PTR_HASH(c, k), BUCKET_HASH_BITS)]; k 873 drivers/md/bcache/btree.c static struct btree *mca_find(struct cache_set *c, struct bkey *k) k 878 drivers/md/bcache/btree.c hlist_for_each_entry_rcu(b, mca_hash(c, k), hash) k 879 drivers/md/bcache/btree.c if (PTR_HASH(c, &b->key) == PTR_HASH(c, k)) k 903 drivers/md/bcache/btree.c struct bkey *k) k 913 drivers/md/bcache/btree.c if (!mca_reap(b, btree_order(k), false)) k 917 drivers/md/bcache/btree.c if (!mca_reap(b, btree_order(k), true)) k 939 drivers/md/bcache/btree.c struct bkey *k, int level) k 947 drivers/md/bcache/btree.c if (mca_find(c, k)) k 954 drivers/md/bcache/btree.c if (!mca_reap(b, btree_order(k), false)) k 962 drivers/md/bcache/btree.c mca_data_alloc(b, k, __GFP_NOWARN|GFP_NOIO); k 969 drivers/md/bcache/btree.c b = mca_bucket_alloc(c, k, __GFP_NOWARN|GFP_NOIO); k 979 drivers/md/bcache/btree.c bkey_copy(&b->key, k); k 982 drivers/md/bcache/btree.c hlist_add_head_rcu(&b->hash, mca_hash(c, k)); k 1002 drivers/md/bcache/btree.c b = mca_cannibalize(c, op, k); k 1019 drivers/md/bcache/btree.c struct bkey *k, int level, bool write, k 1027 drivers/md/bcache/btree.c b = mca_find(c, k); k 1034 drivers/md/bcache/btree.c b = mca_alloc(c, op, k, level); k 1048 drivers/md/bcache/btree.c if (PTR_HASH(c, &b->key) != PTR_HASH(c, k)) { k 1076 drivers/md/bcache/btree.c static void btree_node_prefetch(struct btree *parent, struct bkey *k) k 1081 drivers/md/bcache/btree.c b = mca_alloc(parent->c, NULL, k, parent->level - 1); k 1133 drivers/md/bcache/btree.c BKEY_PADDED(key) k; k 1138 drivers/md/bcache/btree.c if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, wait)) k 1141 drivers/md/bcache/btree.c bkey_put(c, &k.key); k 1142 drivers/md/bcache/btree.c SET_KEY_SIZE(&k.key, c->btree_pages * PAGE_SECTORS); k 1144 drivers/md/bcache/btree.c b = mca_alloc(c, op, &k.key, level); k 1163 drivers/md/bcache/btree.c bch_bucket_free(c, &k.key); k 1193 drivers/md/bcache/btree.c static void make_btree_freeing_key(struct btree *b, struct bkey *k) k 1201 drivers/md/bcache/btree.c bkey_copy(k, &b->key); k 1202 drivers/md/bcache/btree.c bkey_copy_key(k, &ZERO_KEY); k 1204 drivers/md/bcache/btree.c for (i = 0; i < KEY_PTRS(k); i++) k 1205 drivers/md/bcache/btree.c SET_PTR_GEN(k, i, k 1237 drivers/md/bcache/btree.c struct bkey *k) k 1248 drivers/md/bcache/btree.c if (!bkey_cmp(k, &ZERO_KEY)) k 1251 drivers/md/bcache/btree.c for (i = 0; i < KEY_PTRS(k); i++) { k 1252 drivers/md/bcache/btree.c if (!ptr_available(c, k, i)) k 1255 drivers/md/bcache/btree.c g = PTR_BUCKET(c, k, i); k 1257 drivers/md/bcache/btree.c if (gen_after(g->last_gc, PTR_GEN(k, i))) k 1258 drivers/md/bcache/btree.c g->last_gc = PTR_GEN(k, i); k 1260 drivers/md/bcache/btree.c if (ptr_stale(c, k, i)) { k 1261 drivers/md/bcache/btree.c stale = max(stale, ptr_stale(c, k, i)); k 1272 drivers/md/bcache/btree.c else if (KEY_DIRTY(k)) k 1279 drivers/md/bcache/btree.c GC_SECTORS_USED(g) + KEY_SIZE(k), k 1288 drivers/md/bcache/btree.c #define btree_mark_key(b, k) __bch_btree_mark_key(b->c, b->level, k) k 1290 drivers/md/bcache/btree.c void bch_initial_mark_key(struct cache_set *c, int level, struct bkey *k) k 1294 drivers/md/bcache/btree.c for (i = 0; i < KEY_PTRS(k); i++) k 1295 drivers/md/bcache/btree.c if (ptr_available(c, k, i) && k 1296 drivers/md/bcache/btree.c !ptr_stale(c, k, i)) { k 1297 drivers/md/bcache/btree.c struct bucket *b = PTR_BUCKET(c, k, i); k 1299 drivers/md/bcache/btree.c b->gen = PTR_GEN(k, i); k 1301 drivers/md/bcache/btree.c if (level && bkey_cmp(k, &ZERO_KEY)) k 1307 drivers/md/bcache/btree.c __bch_btree_mark_key(c, level, k); k 1319 drivers/md/bcache/btree.c struct bkey *k; k 1325 drivers/md/bcache/btree.c for_each_key_filter(&b->keys, k, &iter, bch_ptr_invalid) { k 1326 drivers/md/bcache/btree.c stale = max(stale, btree_mark_key(b, k)); k 1329 drivers/md/bcache/btree.c if (bch_ptr_bad(&b->keys, k)) k 1332 drivers/md/bcache/btree.c gc->key_bytes += bkey_u64s(k); k 1336 drivers/md/bcache/btree.c gc->data += KEY_SIZE(k); k 1376 drivers/md/bcache/btree.c struct bkey *k; k 1417 drivers/md/bcache/btree.c struct bkey *k, *last = NULL; k 1422 drivers/md/bcache/btree.c for (k = n2->start; k 1423 drivers/md/bcache/btree.c k < bset_bkey_last(n2); k 1424 drivers/md/bcache/btree.c k = bkey_next(k)) { k 1426 drivers/md/bcache/btree.c bkey_u64s(k), k 1430 drivers/md/bcache/btree.c last = k; k 1431 drivers/md/bcache/btree.c keys += bkey_u64s(k); k 1523 drivers/md/bcache/btree.c while ((k = bch_keylist_pop(&keylist))) k 1524 drivers/md/bcache/btree.c if (!bkey_cmp(k, &ZERO_KEY)) k 1574 drivers/md/bcache/btree.c struct bkey *k; k 1578 drivers/md/bcache/btree.c for_each_key_filter(&b->keys, k, &iter, bch_ptr_bad) k 1579 drivers/md/bcache/btree.c ret += bkey_u64s(k); k 1615 drivers/md/bcache/btree.c struct bkey *k; k 1626 drivers/md/bcache/btree.c k = bch_btree_iter_next_filter(&iter, &b->keys, bch_ptr_bad); k 1627 drivers/md/bcache/btree.c if (k) { k 1628 drivers/md/bcache/btree.c r->b = bch_btree_node_get(b->c, op, k, b->level - 1, k 1920 drivers/md/bcache/btree.c struct bkey *k, *p = NULL; k 1923 drivers/md/bcache/btree.c for_each_key_filter(&b->keys, k, &iter, bch_ptr_invalid) k 1924 drivers/md/bcache/btree.c bch_initial_mark_key(b->c, b->level, k); k 1932 drivers/md/bcache/btree.c k = bch_btree_iter_next_filter(&iter, &b->keys, k 1934 drivers/md/bcache/btree.c if (k) { k 1935 drivers/md/bcache/btree.c btree_node_prefetch(b, k); k 1946 drivers/md/bcache/btree.c p = k; k 2003 drivers/md/bcache/btree.c static bool btree_insert_key(struct btree *b, struct bkey *k, k 2008 drivers/md/bcache/btree.c BUG_ON(bkey_cmp(k, &b->key) > 0); k 2010 drivers/md/bcache/btree.c status = bch_btree_insert_key(&b->keys, k, replace_key); k 2015 drivers/md/bcache/btree.c trace_bcache_btree_insert_key(b, k, replace_key != NULL, k 2043 drivers/md/bcache/btree.c struct bkey *k = insert_keys->keys; k 2045 drivers/md/bcache/btree.c if (bkey_u64s(k) > insert_u64s_remaining(b)) k 2048 drivers/md/bcache/btree.c if (bkey_cmp(k, &b->key) <= 0) { k 2050 drivers/md/bcache/btree.c bkey_put(b->c, k); k 2052 drivers/md/bcache/btree.c ret |= btree_insert_key(b, k, replace_key); k 2054 drivers/md/bcache/btree.c } else if (bkey_cmp(&START_KEY(k), &b->key) < 0) { k 2347 drivers/md/bcache/btree.c struct bkey *k; k 2351 drivers/md/bcache/btree.c while ((k = bch_keylist_pop(keys))) k 2352 drivers/md/bcache/btree.c bkey_put(c, k); k 2392 drivers/md/bcache/btree.c struct bkey *k; k 2397 drivers/md/bcache/btree.c while ((k = bch_btree_iter_next_filter(&iter, &b->keys, k 2399 drivers/md/bcache/btree.c ret = btree(map_nodes_recurse, k, b, k 2425 drivers/md/bcache/btree.c struct bkey *k; k 2430 drivers/md/bcache/btree.c while ((k = bch_btree_iter_next_filter(&iter, &b->keys, bch_ptr_bad))) { k 2432 drivers/md/bcache/btree.c ? fn(op, b, k) k 2433 drivers/md/bcache/btree.c : btree(map_keys_recurse, k, b, op, from, fn, flags); k 2480 drivers/md/bcache/btree.c struct bkey *k) k 2486 drivers/md/bcache/btree.c if (bkey_cmp(k, refill->end) > 0) { k 2491 drivers/md/bcache/btree.c if (!KEY_SIZE(k)) /* end key */ k 2494 drivers/md/bcache/btree.c if (refill->pred(buf, k)) { k 2506 drivers/md/bcache/btree.c bkey_copy(&w->key, k); k 2519 drivers/md/bcache/btree.c buf->last_scanned = *k; k 199 drivers/md/bcache/btree.h void bkey_put(struct cache_set *c, struct bkey *k); k 252 drivers/md/bcache/btree.h struct bkey *k, int level, bool write, k 264 drivers/md/bcache/btree.h void bch_initial_mark_key(struct cache_set *c, int level, struct bkey *k); k 316 drivers/md/bcache/btree.h struct bkey *k); k 320 drivers/md/bcache/btree.h typedef bool (keybuf_pred_fn)(struct keybuf *buf, struct bkey *k); k 166 drivers/md/bcache/debug.c static bool dump_pred(struct keybuf *buf, struct bkey *k) k 33 drivers/md/bcache/extents.c i->k = bkey_next(i->k); k 35 drivers/md/bcache/extents.c if (i->k == i->end) k 42 drivers/md/bcache/extents.c int64_t c = bkey_cmp(l.k, r.k); k 44 drivers/md/bcache/extents.c return c ? c > 0 : l.k < r.k; k 47 drivers/md/bcache/extents.c static bool __ptr_invalid(struct cache_set *c, const struct bkey *k) k 51 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) k 52 drivers/md/bcache/extents.c if (ptr_available(c, k, i)) { k 53 drivers/md/bcache/extents.c struct cache *ca = PTR_CACHE(c, k, i); k 54 drivers/md/bcache/extents.c size_t bucket = PTR_BUCKET_NR(c, k, i); k 55 drivers/md/bcache/extents.c size_t r = bucket_remainder(c, PTR_OFFSET(k, i)); k 57 drivers/md/bcache/extents.c if (KEY_SIZE(k) + r > c->sb.bucket_size || k 68 drivers/md/bcache/extents.c static const char *bch_ptr_status(struct cache_set *c, const struct bkey *k) k 72 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) k 73 drivers/md/bcache/extents.c if (ptr_available(c, k, i)) { k 74 drivers/md/bcache/extents.c struct cache *ca = PTR_CACHE(c, k, i); k 75 drivers/md/bcache/extents.c size_t bucket = PTR_BUCKET_NR(c, k, i); k 76 drivers/md/bcache/extents.c size_t r = bucket_remainder(c, PTR_OFFSET(k, i)); k 78 drivers/md/bcache/extents.c if (KEY_SIZE(k) + r > c->sb.bucket_size) k 84 drivers/md/bcache/extents.c if (ptr_stale(c, k, i)) k 88 drivers/md/bcache/extents.c if (!bkey_cmp(k, &ZERO_KEY)) k 90 drivers/md/bcache/extents.c if (!KEY_PTRS(k)) k 92 drivers/md/bcache/extents.c if (!KEY_SIZE(k)) k 97 drivers/md/bcache/extents.c void bch_extent_to_text(char *buf, size_t size, const struct bkey *k) k 104 drivers/md/bcache/extents.c p("%llu:%llu len %llu -> [", KEY_INODE(k), KEY_START(k), KEY_SIZE(k)); k 106 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) { k 110 drivers/md/bcache/extents.c if (PTR_DEV(k, i) == PTR_CHECK_DEV) k 113 drivers/md/bcache/extents.c p("%llu:%llu gen %llu", PTR_DEV(k, i), k 114 drivers/md/bcache/extents.c PTR_OFFSET(k, i), PTR_GEN(k, i)); k 119 drivers/md/bcache/extents.c if (KEY_DIRTY(k)) k 121 drivers/md/bcache/extents.c if (KEY_CSUM(k)) k 122 drivers/md/bcache/extents.c p(" cs%llu %llx", KEY_CSUM(k), k->ptr[1]); k 126 drivers/md/bcache/extents.c static void bch_bkey_dump(struct btree_keys *keys, const struct bkey *k) k 132 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 135 drivers/md/bcache/extents.c for (j = 0; j < KEY_PTRS(k); j++) { k 136 drivers/md/bcache/extents.c size_t n = PTR_BUCKET_NR(b->c, k, j); k 141 drivers/md/bcache/extents.c PTR_BUCKET(b->c, k, j)->prio); k 144 drivers/md/bcache/extents.c pr_err(" %s\n", bch_ptr_status(b->c, k)); k 149 drivers/md/bcache/extents.c bool __bch_btree_ptr_invalid(struct cache_set *c, const struct bkey *k) k 153 drivers/md/bcache/extents.c if (!KEY_PTRS(k) || !KEY_SIZE(k) || KEY_DIRTY(k)) k 156 drivers/md/bcache/extents.c if (__ptr_invalid(c, k)) k 161 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 162 drivers/md/bcache/extents.c cache_bug(c, "spotted btree ptr %s: %s", buf, bch_ptr_status(c, k)); k 166 drivers/md/bcache/extents.c static bool bch_btree_ptr_invalid(struct btree_keys *bk, const struct bkey *k) k 170 drivers/md/bcache/extents.c return __bch_btree_ptr_invalid(b->c, k); k 173 drivers/md/bcache/extents.c static bool btree_ptr_bad_expensive(struct btree *b, const struct bkey *k) k 180 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) k 181 drivers/md/bcache/extents.c if (ptr_available(b->c, k, i)) { k 182 drivers/md/bcache/extents.c g = PTR_BUCKET(b->c, k, i); k 184 drivers/md/bcache/extents.c if (KEY_DIRTY(k) || k 197 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 200 drivers/md/bcache/extents.c buf, PTR_BUCKET_NR(b->c, k, i), atomic_read(&g->pin), k 205 drivers/md/bcache/extents.c static bool bch_btree_ptr_bad(struct btree_keys *bk, const struct bkey *k) k 210 drivers/md/bcache/extents.c if (!bkey_cmp(k, &ZERO_KEY) || k 211 drivers/md/bcache/extents.c !KEY_PTRS(k) || k 212 drivers/md/bcache/extents.c bch_ptr_invalid(bk, k)) k 215 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) k 216 drivers/md/bcache/extents.c if (!ptr_available(b->c, k, i) || k 217 drivers/md/bcache/extents.c ptr_stale(b->c, k, i)) k 221 drivers/md/bcache/extents.c btree_ptr_bad_expensive(b, k)) k 261 drivers/md/bcache/extents.c int64_t c = bkey_cmp(&START_KEY(l.k), &START_KEY(r.k)); k 263 drivers/md/bcache/extents.c return c ? c > 0 : l.k < r.k; k 276 drivers/md/bcache/extents.c if (bkey_cmp(top->k, &START_KEY(i->k)) <= 0) k 279 drivers/md/bcache/extents.c if (!KEY_SIZE(i->k)) { k 285 drivers/md/bcache/extents.c if (top->k > i->k) { k 286 drivers/md/bcache/extents.c if (bkey_cmp(top->k, i->k) >= 0) k 289 drivers/md/bcache/extents.c bch_cut_front(top->k, i->k); k 294 drivers/md/bcache/extents.c BUG_ON(!bkey_cmp(&START_KEY(top->k), &START_KEY(i->k))); k 296 drivers/md/bcache/extents.c if (bkey_cmp(i->k, top->k) < 0) { k 297 drivers/md/bcache/extents.c bkey_copy(tmp, top->k); k 299 drivers/md/bcache/extents.c bch_cut_back(&START_KEY(i->k), tmp); k 300 drivers/md/bcache/extents.c bch_cut_front(i->k, top->k); k 305 drivers/md/bcache/extents.c bch_cut_back(&START_KEY(i->k), top->k); k 313 drivers/md/bcache/extents.c static void bch_subtract_dirty(struct bkey *k, k 318 drivers/md/bcache/extents.c if (KEY_DIRTY(k)) k 319 drivers/md/bcache/extents.c bcache_dev_sectors_dirty_add(c, KEY_INODE(k), k 337 drivers/md/bcache/extents.c struct bkey *k = bch_btree_iter_next(iter); k 339 drivers/md/bcache/extents.c if (!k) k 342 drivers/md/bcache/extents.c if (bkey_cmp(&START_KEY(k), insert) >= 0) { k 343 drivers/md/bcache/extents.c if (KEY_SIZE(k)) k 349 drivers/md/bcache/extents.c if (bkey_cmp(k, &START_KEY(insert)) <= 0) k 352 drivers/md/bcache/extents.c old_offset = KEY_START(k); k 353 drivers/md/bcache/extents.c old_size = KEY_SIZE(k); k 363 drivers/md/bcache/extents.c if (replace_key && KEY_SIZE(k)) { k 369 drivers/md/bcache/extents.c uint64_t offset = KEY_START(k) - k 373 drivers/md/bcache/extents.c if (KEY_START(k) < KEY_START(replace_key) || k 374 drivers/md/bcache/extents.c KEY_OFFSET(k) > KEY_OFFSET(replace_key)) k 378 drivers/md/bcache/extents.c if (KEY_START(k) > KEY_START(insert) + sectors_found) k 381 drivers/md/bcache/extents.c if (!bch_bkey_equal_header(k, replace_key)) k 390 drivers/md/bcache/extents.c if (k->ptr[i] != replace_key->ptr[i] + offset) k 393 drivers/md/bcache/extents.c sectors_found = KEY_OFFSET(k) - KEY_START(insert); k 396 drivers/md/bcache/extents.c if (bkey_cmp(insert, k) < 0 && k 397 drivers/md/bcache/extents.c bkey_cmp(&START_KEY(insert), &START_KEY(k)) > 0) { k 407 drivers/md/bcache/extents.c bch_subtract_dirty(k, c, KEY_START(insert), k 410 drivers/md/bcache/extents.c if (bkey_written(b, k)) { k 425 drivers/md/bcache/extents.c bch_bset_insert(b, top, k); k 428 drivers/md/bcache/extents.c bkey_copy(&temp.key, k); k 429 drivers/md/bcache/extents.c bch_bset_insert(b, k, &temp.key); k 430 drivers/md/bcache/extents.c top = bkey_next(k); k 434 drivers/md/bcache/extents.c bch_cut_back(&START_KEY(insert), k); k 435 drivers/md/bcache/extents.c bch_bset_fix_invalidated_key(b, k); k 439 drivers/md/bcache/extents.c if (bkey_cmp(insert, k) < 0) { k 440 drivers/md/bcache/extents.c bch_cut_front(insert, k); k 442 drivers/md/bcache/extents.c if (bkey_cmp(&START_KEY(insert), &START_KEY(k)) > 0) k 445 drivers/md/bcache/extents.c if (bkey_written(b, k) && k 446 drivers/md/bcache/extents.c bkey_cmp(&START_KEY(insert), &START_KEY(k)) <= 0) { k 451 drivers/md/bcache/extents.c bch_cut_front(k, k); k 453 drivers/md/bcache/extents.c __bch_cut_back(&START_KEY(insert), k); k 454 drivers/md/bcache/extents.c bch_bset_fix_invalidated_key(b, k); k 458 drivers/md/bcache/extents.c bch_subtract_dirty(k, c, old_offset, old_size - KEY_SIZE(k)); k 480 drivers/md/bcache/extents.c bool __bch_extent_invalid(struct cache_set *c, const struct bkey *k) k 484 drivers/md/bcache/extents.c if (!KEY_SIZE(k)) k 487 drivers/md/bcache/extents.c if (KEY_SIZE(k) > KEY_OFFSET(k)) k 490 drivers/md/bcache/extents.c if (__ptr_invalid(c, k)) k 495 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 496 drivers/md/bcache/extents.c cache_bug(c, "spotted extent %s: %s", buf, bch_ptr_status(c, k)); k 500 drivers/md/bcache/extents.c static bool bch_extent_invalid(struct btree_keys *bk, const struct bkey *k) k 504 drivers/md/bcache/extents.c return __bch_extent_invalid(b->c, k); k 507 drivers/md/bcache/extents.c static bool bch_extent_bad_expensive(struct btree *b, const struct bkey *k, k 510 drivers/md/bcache/extents.c struct bucket *g = PTR_BUCKET(b->c, k, ptr); k 517 drivers/md/bcache/extents.c (GC_MARK(g) != GC_MARK_DIRTY && KEY_DIRTY(k)))) k 529 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 532 drivers/md/bcache/extents.c buf, PTR_BUCKET_NR(b->c, k, ptr), atomic_read(&g->pin), k 537 drivers/md/bcache/extents.c static bool bch_extent_bad(struct btree_keys *bk, const struct bkey *k) k 543 drivers/md/bcache/extents.c if (!KEY_PTRS(k) || k 544 drivers/md/bcache/extents.c bch_extent_invalid(bk, k)) k 547 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) k 548 drivers/md/bcache/extents.c if (!ptr_available(b->c, k, i)) k 551 drivers/md/bcache/extents.c for (i = 0; i < KEY_PTRS(k); i++) { k 552 drivers/md/bcache/extents.c stale = ptr_stale(b->c, k, i); k 554 drivers/md/bcache/extents.c if (stale && KEY_DIRTY(k)) { k 555 drivers/md/bcache/extents.c bch_extent_to_text(buf, sizeof(buf), k); k 568 drivers/md/bcache/extents.c bch_extent_bad_expensive(b, k, i)) k 11 drivers/md/bcache/extents.h void bch_extent_to_text(char *buf, size_t size, const struct bkey *k); k 12 drivers/md/bcache/extents.h bool __bch_btree_ptr_invalid(struct cache_set *c, const struct bkey *k); k 13 drivers/md/bcache/extents.h bool __bch_extent_invalid(struct cache_set *c, const struct bkey *k); k 46 drivers/md/bcache/io.c struct bkey *k, unsigned int ptr) k 50 drivers/md/bcache/io.c bch_bkey_copy_single_ptr(&b->key, k, ptr); k 303 drivers/md/bcache/journal.c struct bkey *k; k 331 drivers/md/bcache/journal.c for (k = i->j.start; k 332 drivers/md/bcache/journal.c k < bset_bkey_last(&i->j); k 333 drivers/md/bcache/journal.c k = bkey_next(k)) k 334 drivers/md/bcache/journal.c if (!__bch_extent_invalid(c, k)) { k 337 drivers/md/bcache/journal.c for (j = 0; j < KEY_PTRS(k); j++) k 338 drivers/md/bcache/journal.c if (ptr_available(c, k, j)) k 339 drivers/md/bcache/journal.c atomic_inc(&PTR_BUCKET(c, k, j)->pin); k 341 drivers/md/bcache/journal.c bch_initial_mark_key(c, 0, k); k 361 drivers/md/bcache/journal.c struct bkey *k; k 383 drivers/md/bcache/journal.c for (k = i->j.start; k 384 drivers/md/bcache/journal.c k < bset_bkey_last(&i->j); k 385 drivers/md/bcache/journal.c k = bkey_next(k)) { k 386 drivers/md/bcache/journal.c trace_bcache_journal_replay_key(k); k 388 drivers/md/bcache/journal.c bch_keylist_init_single(&keylist, k); k 641 drivers/md/bcache/journal.c struct bkey *k = &c->journal.key; k 685 drivers/md/bcache/journal.c k->ptr[n++] = MAKE_PTR(0, k 692 drivers/md/bcache/journal.c bkey_init(k); k 693 drivers/md/bcache/journal.c SET_KEY_PTRS(k, n); k 761 drivers/md/bcache/journal.c struct bkey *k = &c->journal.key; k 797 drivers/md/bcache/journal.c for (i = 0; i < KEY_PTRS(k); i++) { k 798 drivers/md/bcache/journal.c ca = PTR_CACHE(c, k, i); k 804 drivers/md/bcache/journal.c bio->bi_iter.bi_sector = PTR_OFFSET(k, i); k 817 drivers/md/bcache/journal.c SET_PTR_OFFSET(k, i, PTR_OFFSET(k, i) + sectors); k 22 drivers/md/bcache/movinggc.c static bool moving_pred(struct keybuf *buf, struct bkey *k) k 28 drivers/md/bcache/movinggc.c for (i = 0; i < KEY_PTRS(k); i++) k 29 drivers/md/bcache/movinggc.c if (ptr_available(c, k, i) && k 30 drivers/md/bcache/movinggc.c GC_MOVE(PTR_BUCKET(c, k, i))) k 40 drivers/md/bcache/request.c static void bio_csum(struct bio *bio, struct bkey *k) k 53 drivers/md/bcache/request.c k->ptr[KEY_PTRS(k)] = csum & (~0ULL >> 1); k 218 drivers/md/bcache/request.c struct bkey *k; k 229 drivers/md/bcache/request.c k = op->insert_keys.top; k 230 drivers/md/bcache/request.c bkey_init(k); k 231 drivers/md/bcache/request.c SET_KEY_INODE(k, op->inode); k 232 drivers/md/bcache/request.c SET_KEY_OFFSET(k, bio->bi_iter.bi_sector); k 234 drivers/md/bcache/request.c if (!bch_alloc_sectors(op->c, k, bio_sectors(bio), k 239 drivers/md/bcache/request.c n = bio_next_split(bio, KEY_SIZE(k), GFP_NOIO, split); k 245 drivers/md/bcache/request.c SET_KEY_DIRTY(k, true); k 247 drivers/md/bcache/request.c for (i = 0; i < KEY_PTRS(k); i++) k 248 drivers/md/bcache/request.c SET_GC_MARK(PTR_BUCKET(op->c, k, i), k 252 drivers/md/bcache/request.c SET_KEY_CSUM(k, op->csum); k 253 drivers/md/bcache/request.c if (KEY_CSUM(k)) k 254 drivers/md/bcache/request.c bio_csum(n, k); k 256 drivers/md/bcache/request.c trace_bcache_cache_insert(k); k 260 drivers/md/bcache/request.c bch_submit_bbio(n, op->c, k, 0); k 370 drivers/md/bcache/request.c static struct hlist_head *iohash(struct cached_dev *dc, uint64_t k) k 372 drivers/md/bcache/request.c return &dc->io_hash[hash_64(k, RECENT_IO_BITS)]; k 524 drivers/md/bcache/request.c static int cache_lookup_fn(struct btree_op *op, struct btree *b, struct bkey *k) k 531 drivers/md/bcache/request.c if (bkey_cmp(k, &KEY(s->iop.inode, bio->bi_iter.bi_sector, 0)) <= 0) k 534 drivers/md/bcache/request.c if (KEY_INODE(k) != s->iop.inode || k 535 drivers/md/bcache/request.c KEY_START(k) > bio->bi_iter.bi_sector) { k 537 drivers/md/bcache/request.c unsigned int sectors = KEY_INODE(k) == s->iop.inode k 539 drivers/md/bcache/request.c KEY_START(k) - bio->bi_iter.bi_sector) k 550 drivers/md/bcache/request.c if (!KEY_SIZE(k)) k 556 drivers/md/bcache/request.c PTR_BUCKET(b->c, k, ptr)->prio = INITIAL_PRIO; k 558 drivers/md/bcache/request.c if (KEY_DIRTY(k)) k 562 drivers/md/bcache/request.c KEY_OFFSET(k) - bio->bi_iter.bi_sector), k 566 drivers/md/bcache/request.c bch_bkey_copy_single_ptr(bio_key, k, ptr); k 79 drivers/md/bcache/stats.c static void bch_stats_release(struct kobject *k) k 340 drivers/md/bcache/super.c struct bkey *k, struct closure *parent) k 351 drivers/md/bcache/super.c for (i = 0; i < KEY_PTRS(k); i++) { k 355 drivers/md/bcache/super.c bio->bi_iter.bi_size = KEY_SIZE(k) << 9; k 362 drivers/md/bcache/super.c bch_submit_bbio(bio, c, k, i); k 368 drivers/md/bcache/super.c bch_extent_to_text(buf, sizeof(buf), k); k 382 drivers/md/bcache/super.c struct bkey *k = &j->uuid_bucket; k 384 drivers/md/bcache/super.c if (__bch_btree_ptr_invalid(c, k)) k 387 drivers/md/bcache/super.c bkey_copy(&c->uuid_bucket, k); k 388 drivers/md/bcache/super.c uuid_io(c, REQ_OP_READ, 0, k, cl); k 423 drivers/md/bcache/super.c BKEY_PADDED(key) k; k 430 drivers/md/bcache/super.c if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, true)) k 433 drivers/md/bcache/super.c SET_KEY_SIZE(&k.key, c->sb.bucket_size); k 434 drivers/md/bcache/super.c uuid_io(c, REQ_OP_WRITE, 0, &k.key, &cl); k 438 drivers/md/bcache/super.c ca = PTR_CACHE(c, &k.key, 0); k 441 drivers/md/bcache/super.c bkey_copy(&c->uuid_bucket, &k.key); k 442 drivers/md/bcache/super.c bkey_put(c, &k.key); k 1863 drivers/md/bcache/super.c struct bkey *k; k 1888 drivers/md/bcache/super.c k = &j->btree_root; k 1891 drivers/md/bcache/super.c if (__bch_btree_ptr_invalid(c, k)) k 1895 drivers/md/bcache/super.c c->root = bch_btree_node_get(c, NULL, k, k 2329 drivers/md/bcache/super.c static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr, k 2331 drivers/md/bcache/super.c static ssize_t bch_pending_bdevs_cleanup(struct kobject *k, k 2372 drivers/md/bcache/super.c static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr, k 2491 drivers/md/bcache/super.c static ssize_t bch_pending_bdevs_cleanup(struct kobject *k, k 635 drivers/md/bcache/sysfs.c struct bkey *k; k 648 drivers/md/bcache/sysfs.c for_each_key_filter(&b->keys, k, &iter, bch_ptr_bad) k 649 drivers/md/bcache/sysfs.c bytes += bkey_bytes(k); k 918 drivers/md/bcache/sysfs.c static void bch_cache_set_internal_release(struct kobject *k) k 556 drivers/md/bcache/writeback.c static bool dirty_pred(struct keybuf *buf, struct bkey *k) k 562 drivers/md/bcache/writeback.c BUG_ON(KEY_INODE(k) != dc->disk.id); k 564 drivers/md/bcache/writeback.c return KEY_DIRTY(k); k 763 drivers/md/bcache/writeback.c struct bkey *k) k 767 drivers/md/bcache/writeback.c if (KEY_INODE(k) > op->inode) k 770 drivers/md/bcache/writeback.c if (KEY_DIRTY(k)) k 771 drivers/md/bcache/writeback.c bcache_dev_sectors_dirty_add(b->c, KEY_INODE(k), k 772 drivers/md/bcache/writeback.c KEY_START(k), KEY_SIZE(k)); k 777 drivers/md/bcache/writeback.c bkey_copy_key(&op->start, k); k 125 drivers/md/dm-cache-target.c static inline void init_continuation(struct continuation *k, k 128 drivers/md/dm-cache-target.c INIT_WORK(&k->ws, fn); k 129 drivers/md/dm-cache-target.c k->input = 0; k 133 drivers/md/dm-cache-target.c struct continuation *k) k 135 drivers/md/dm-cache-target.c queue_work(wq, &k->ws); k 178 drivers/md/dm-cache-target.c struct continuation *k; k 199 drivers/md/dm-cache-target.c k = container_of(ws, struct continuation, ws); k 200 drivers/md/dm-cache-target.c k->input = r; k 239 drivers/md/dm-cache-target.c static void continue_after_commit(struct batcher *b, struct continuation *k) k 246 drivers/md/dm-cache-target.c list_add_tail(&k->ws.entry, &b->work_items); k 498 drivers/md/dm-cache-target.c struct continuation k; k 1166 drivers/md/dm-cache-target.c init_continuation(&mg->k, continuation); k 1167 drivers/md/dm-cache-target.c dm_cell_quiesce_v2(mg->cache->prison, mg->cell, &mg->k.ws); k 1172 drivers/md/dm-cache-target.c struct continuation *k = container_of(ws, struct continuation, ws); k 1173 drivers/md/dm-cache-target.c return container_of(k, struct dm_cache_migration, k); k 1178 drivers/md/dm-cache-target.c struct dm_cache_migration *mg = container_of(context, struct dm_cache_migration, k); k 1181 drivers/md/dm-cache-target.c mg->k.input = BLK_STS_IOERR; k 1183 drivers/md/dm-cache-target.c queue_continuation(mg->cache->wq, &mg->k); k 1200 drivers/md/dm-cache-target.c dm_kcopyd_copy(cache->copier, &o_region, 1, &c_region, 0, copy_complete, &mg->k); k 1202 drivers/md/dm-cache-target.c dm_kcopyd_copy(cache->copier, &c_region, 1, &o_region, 0, copy_complete, &mg->k); k 1223 drivers/md/dm-cache-target.c mg->k.input = bio->bi_status; k 1225 drivers/md/dm-cache-target.c queue_continuation(cache->wq, &mg->k); k 1245 drivers/md/dm-cache-target.c init_continuation(&mg->k, continuation); k 1278 drivers/md/dm-cache-target.c else if (mg->k.input) k 1279 drivers/md/dm-cache-target.c mg->overwrite_bio->bi_status = mg->k.input; k 1324 drivers/md/dm-cache-target.c mg_complete(mg, mg->k.input == 0); k 1378 drivers/md/dm-cache-target.c init_continuation(&mg->k, mg_success); k 1379 drivers/md/dm-cache-target.c continue_after_commit(&cache->committer, &mg->k); k 1396 drivers/md/dm-cache-target.c if (mg->k.input) k 1410 drivers/md/dm-cache-target.c if (mg->k.input) k 1443 drivers/md/dm-cache-target.c init_continuation(&mg->k, mg_upgrade_lock); k 1510 drivers/md/dm-cache-target.c mg_copy(&mg->k.ws); k 1562 drivers/md/dm-cache-target.c invalidate_complete(mg, !mg->k.input); k 1600 drivers/md/dm-cache-target.c init_continuation(&mg->k, invalidate_completed); k 1601 drivers/md/dm-cache-target.c continue_after_commit(&cache->committer, &mg->k); k 1636 drivers/md/dm-cache-target.c init_continuation(&mg->k, invalidate_remove); k 1637 drivers/md/dm-cache-target.c queue_work(cache->wq, &mg->k.ws); k 2176 drivers/md/dm-integrity.c unsigned k, l, next_loop; k 2193 drivers/md/dm-integrity.c for (k = j + 1; k < ic->journal_section_entries; k++) { k 2194 drivers/md/dm-integrity.c struct journal_entry *je2 = access_journal_entry(ic, i, k); k 2201 drivers/md/dm-integrity.c if (area2 != area || offset2 != offset + ((k - j) << ic->sb->log2_sectors_per_block)) k 2203 drivers/md/dm-integrity.c restore_last_bytes(ic, access_journal_data(ic, i, k), je2); k 2205 drivers/md/dm-integrity.c next_loop = k - 1; k 2210 drivers/md/dm-integrity.c io->range.n_sectors = (k - j) << ic->sb->log2_sectors_per_block; k 2219 drivers/md/dm-integrity.c while (j < k && find_newer_committed_node(ic, §ion_node[j])) { k 2228 drivers/md/dm-integrity.c while (j < k && find_newer_committed_node(ic, §ion_node[k - 1])) { k 2229 drivers/md/dm-integrity.c struct journal_entry *je2 = access_journal_entry(ic, i, k - 1); k 2232 drivers/md/dm-integrity.c remove_journal_node(ic, §ion_node[k - 1]); k 2233 drivers/md/dm-integrity.c k--; k 2235 drivers/md/dm-integrity.c if (j == k) { k 2241 drivers/md/dm-integrity.c for (l = j; l < k; l++) { k 2248 drivers/md/dm-integrity.c for (l = j; l < k; l++) { k 2275 drivers/md/dm-integrity.c (k - j) << ic->sb->log2_sectors_per_block, k 2587 drivers/md/dm-integrity.c unsigned char k; k 2588 drivers/md/dm-integrity.c for (k = 0; k < N_COMMIT_IDS; k++) { k 2589 drivers/md/dm-integrity.c if (dm_integrity_commit_id(ic, i, j, k) == id) k 2590 drivers/md/dm-integrity.c return k; k 2639 drivers/md/dm-integrity.c int k; k 2641 drivers/md/dm-integrity.c k = find_commit_seq(ic, i, j, js->commit_id); k 2642 drivers/md/dm-integrity.c if (k < 0) k 2644 drivers/md/dm-integrity.c used_commit_ids[k] = true; k 2645 drivers/md/dm-integrity.c max_commit_id_sections[k] = i; k 3246 drivers/md/dm-integrity.c char *k; k 3254 drivers/md/dm-integrity.c k = strchr(a->alg_string, ':'); k 3255 drivers/md/dm-integrity.c if (k) { k 3256 drivers/md/dm-integrity.c *k = 0; k 3257 drivers/md/dm-integrity.c a->key_string = k + 1; k 89 drivers/md/dm-table.c static inline unsigned int get_child(unsigned int n, unsigned int k) k 91 drivers/md/dm-table.c return (n * CHILDREN_PER_NODE) + k; k 124 drivers/md/dm-table.c unsigned int n, k; k 130 drivers/md/dm-table.c for (k = 0U; k < KEYS_PER_NODE; k++) k 131 drivers/md/dm-table.c node[k] = high(t, l + 1, get_child(n, k)); k 1365 drivers/md/dm-table.c unsigned int l, n = 0, k = 0; k 1372 drivers/md/dm-table.c n = get_child(n, k); k 1375 drivers/md/dm-table.c for (k = 0; k < KEYS_PER_NODE; k++) k 1376 drivers/md/dm-table.c if (node[k] >= sector) k 1380 drivers/md/dm-table.c return &t->targets[(KEYS_PER_NODE * n) + k]; k 212 drivers/md/dm-verity-fec.c unsigned n, k; k 287 drivers/md/dm-verity-fec.c k = fec_buffer_rs_index(n, j) + block_offset; k 289 drivers/md/dm-verity-fec.c if (k >= 1 << v->data_dev_block_bits) k 293 drivers/md/dm-verity-fec.c rs_block[i] = bbuf[k]; k 1737 drivers/md/md-bitmap.c unsigned long k, pages; k 1763 drivers/md/md-bitmap.c for (k = 0; k < pages; k++) k 1764 drivers/md/md-bitmap.c if (bp[k].map && !bp[k].hijacked) k 1765 drivers/md/md-bitmap.c kfree(bp[k].map); k 2164 drivers/md/md-bitmap.c unsigned long k; k 2167 drivers/md/md-bitmap.c for (k = 0; k < page; k++) { k 2168 drivers/md/md-bitmap.c kfree(new_bp[k].map); k 2218 drivers/md/md-bitmap.c unsigned long k; k 2219 drivers/md/md-bitmap.c for (k = 0; k < old_counts.pages; k++) k 2220 drivers/md/md-bitmap.c if (!old_counts.bp[k].hijacked) k 2221 drivers/md/md-bitmap.c kfree(old_counts.bp[k].map); k 623 drivers/md/persistent-data/dm-btree-remove.c uint64_t k; k 652 drivers/md/persistent-data/dm-btree-remove.c k = le64_to_cpu(n->keys[index]); k 653 drivers/md/persistent-data/dm-btree-remove.c if (k >= keys[last_level] && k < end_key) { k 659 drivers/md/persistent-data/dm-btree-remove.c keys[last_level] = k + 1ull; k 52 drivers/md/raid0.c int j, k; k 65 drivers/md/raid0.c for (k = 0; k < conf->strip_zone[j].nb_dev; k++) k 66 drivers/md/raid0.c len += snprintf(line+len, 200-len, "%s%s", k?"/":"", k 68 drivers/md/raid0.c + k]->bdev, b)); k 3139 drivers/md/raid10.c int k; k 3179 drivers/md/raid10.c for (k=0; k<conf->copies; k++) k 3180 drivers/md/raid10.c if (r10_bio->devs[k].devnum == i) k 3182 drivers/md/raid10.c BUG_ON(k == conf->copies); k 3183 drivers/md/raid10.c to_addr = r10_bio->devs[k].addr; k 3230 drivers/md/raid10.c int k; k 3231 drivers/md/raid10.c for (k = 0; k < conf->copies; k++) k 3232 drivers/md/raid10.c if (r10_bio->devs[k].devnum == i) k 3238 drivers/md/raid10.c r10_bio->devs[k].addr, k 3244 drivers/md/raid10.c r10_bio->devs[k].addr, k 6680 drivers/md/raid5.c int i, j, k; k 6715 drivers/md/raid5.c for (k = 0; k < NR_STRIPE_HASH_LOCKS; k++) k 6716 drivers/md/raid5.c INIT_LIST_HEAD(worker->temp_inactive_list + k); k 847 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c static void precalculate_color(struct tpg_data *tpg, int k) k 849 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c int col = k; k 856 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c if (k == TPG_COLOR_TEXTBG) { k 862 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c } else if (k == TPG_COLOR_TEXTFG) { k 870 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c } else if (k == TPG_COLOR_RANDOM) { k 872 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c } else if (k >= TPG_COLOR_RAMP) { k 873 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c r = g = b = k - TPG_COLOR_RAMP; k 963 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][0] = h; k 964 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][1] = s; k 965 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][2] = v; k 1010 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][0] = y; k 1011 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][1] = cb; k 1012 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][2] = cr; k 1017 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][0] = r >> 4; k 1080 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][0] = r; k 1081 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][1] = g; k 1082 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c tpg->colors[k][2] = b; k 1090 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c int k; k 1092 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c for (k = 0; k < TPG_COLOR_MAX; k++) k 1093 drivers/media/common/v4l2-tpg/v4l2-tpg-core.c precalculate_color(tpg, k); k 859 drivers/media/dvb-frontends/dib3000mc.c int k; k 870 drivers/media/dvb-frontends/dib3000mc.c for (k = no_of_demods-1; k >= 0; k--) { k 871 drivers/media/dvb-frontends/dib3000mc.c dmcst->cfg = &cfg[k]; k 874 drivers/media/dvb-frontends/dib3000mc.c new_addr = DIB3000MC_I2C_ADDRESS[k]; k 879 drivers/media/dvb-frontends/dib3000mc.c dprintk("-E- DiB3000P/MC #%d: not identified\n", k); k 892 drivers/media/dvb-frontends/dib3000mc.c for (k = 0; k < no_of_demods; k++) { k 893 drivers/media/dvb-frontends/dib3000mc.c dmcst->cfg = &cfg[k]; k 894 drivers/media/dvb-frontends/dib3000mc.c dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k]; k 1357 drivers/media/dvb-frontends/dib7000m.c int k = 0; k 1360 drivers/media/dvb-frontends/dib7000m.c for (k = no_of_demods-1; k >= 0; k--) { k 1361 drivers/media/dvb-frontends/dib7000m.c st.cfg = cfg[k]; k 1364 drivers/media/dvb-frontends/dib7000m.c new_addr = (0x40 + k) << 1; k 1369 drivers/media/dvb-frontends/dib7000m.c dprintk("DiB7000M #%d: not identified\n", k); k 1382 drivers/media/dvb-frontends/dib7000m.c dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); k 1385 drivers/media/dvb-frontends/dib7000m.c for (k = 0; k < no_of_demods; k++) { k 1386 drivers/media/dvb-frontends/dib7000m.c st.cfg = cfg[k]; k 1387 drivers/media/dvb-frontends/dib7000m.c st.i2c_addr = (0x40 + k) << 1; k 1213 drivers/media/dvb-frontends/dib7000p.c int k; k 1227 drivers/media/dvb-frontends/dib7000p.c for (k = 0; k < 8; k++) { k 1228 drivers/media/dvb-frontends/dib7000p.c pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff; k 1231 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = 256; k 1232 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = 0; k 1234 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = sine[256 - (pha & 0xff)]; k 1235 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = sine[pha & 0xff]; k 1237 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = 0; k 1238 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = 256; k 1240 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = -sine[pha & 0xff]; k 1241 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = sine[256 - (pha & 0xff)]; k 1243 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = -256; k 1244 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = 0; k 1246 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = -sine[256 - (pha & 0xff)]; k 1247 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = -sine[pha & 0xff]; k 1249 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = 0; k 1250 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = -256; k 1252 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = sine[pha & 0xff]; k 1253 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = -sine[256 - (pha & 0xff)]; k 1256 drivers/media/dvb-frontends/dib7000p.c coef_re[k] *= notch[k]; k 1257 drivers/media/dvb-frontends/dib7000p.c coef_re[k] += (1 << 14); k 1258 drivers/media/dvb-frontends/dib7000p.c if (coef_re[k] >= (1 << 24)) k 1259 drivers/media/dvb-frontends/dib7000p.c coef_re[k] = (1 << 24) - 1; k 1260 drivers/media/dvb-frontends/dib7000p.c coef_re[k] /= (1 << 15); k 1262 drivers/media/dvb-frontends/dib7000p.c coef_im[k] *= notch[k]; k 1263 drivers/media/dvb-frontends/dib7000p.c coef_im[k] += (1 << 14); k 1264 drivers/media/dvb-frontends/dib7000p.c if (coef_im[k] >= (1 << 24)) k 1265 drivers/media/dvb-frontends/dib7000p.c coef_im[k] = (1 << 24) - 1; k 1266 drivers/media/dvb-frontends/dib7000p.c coef_im[k] /= (1 << 15); k 1268 drivers/media/dvb-frontends/dib7000p.c dprintk("PALF COEF: %d re: %d im: %d\n", k, coef_re[k], coef_im[k]); k 1270 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); k 1271 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 144, coef_im[k] & 0x3ff); k 1272 drivers/media/dvb-frontends/dib7000p.c dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff)); k 2086 drivers/media/dvb-frontends/dib7000p.c int k = 0; k 2096 drivers/media/dvb-frontends/dib7000p.c for (k = no_of_demods - 1; k >= 0; k--) { k 2097 drivers/media/dvb-frontends/dib7000p.c dpst->cfg = cfg[k]; k 2100 drivers/media/dvb-frontends/dib7000p.c if (cfg[k].default_i2c_addr != 0) k 2101 drivers/media/dvb-frontends/dib7000p.c new_addr = cfg[k].default_i2c_addr + (k << 1); k 2103 drivers/media/dvb-frontends/dib7000p.c new_addr = (0x40 + k) << 1; k 2110 drivers/media/dvb-frontends/dib7000p.c dprintk("DiB7000P #%d: not identified\n", k); k 2122 drivers/media/dvb-frontends/dib7000p.c dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); k 2125 drivers/media/dvb-frontends/dib7000p.c for (k = 0; k < no_of_demods; k++) { k 2126 drivers/media/dvb-frontends/dib7000p.c dpst->cfg = cfg[k]; k 2127 drivers/media/dvb-frontends/dib7000p.c if (cfg[k].default_i2c_addr != 0) k 2128 drivers/media/dvb-frontends/dib7000p.c dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1; k 2130 drivers/media/dvb-frontends/dib7000p.c dpst->i2c_addr = (0x40 + k) << 1; k 4267 drivers/media/dvb-frontends/dib8000.c int k = 0, ret = 0; k 4290 drivers/media/dvb-frontends/dib8000.c for (k = no_of_demods - 1; k >= 0; k--) { k 4292 drivers/media/dvb-frontends/dib8000.c new_addr = first_addr + (k << 1); k 4303 drivers/media/dvb-frontends/dib8000.c dprintk("#%d: not identified\n", k); k 4317 drivers/media/dvb-frontends/dib8000.c dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); k 4320 drivers/media/dvb-frontends/dib8000.c for (k = 0; k < no_of_demods; k++) { k 4321 drivers/media/dvb-frontends/dib8000.c new_addr = first_addr | (k << 1); k 2377 drivers/media/dvb-frontends/dib9000.c int k = 0, ret = 0; k 2396 drivers/media/dvb-frontends/dib9000.c for (k = no_of_demods - 1; k >= 0; k--) { k 2398 drivers/media/dvb-frontends/dib9000.c new_addr = first_addr + (k << 1); k 2415 drivers/media/dvb-frontends/dib9000.c dprintk("DiB9000 #%d: not identified\n", k); k 2424 drivers/media/dvb-frontends/dib9000.c dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); k 2427 drivers/media/dvb-frontends/dib9000.c for (k = 0; k < no_of_demods; k++) { k 2428 drivers/media/dvb-frontends/dib9000.c new_addr = first_addr | (k << 1); k 1153 drivers/media/dvb-frontends/drx39xyj/drxj.c u32 k = 0; k 1162 drivers/media/dvb-frontends/drx39xyj/drxj.c for (k = scale; k > 0; k--) { k 1168 drivers/media/dvb-frontends/drx39xyj/drxj.c for (k = scale; k < 31; k++) { k 1179 drivers/media/dvb-frontends/drx39xyj/drxj.c y = k * ((((u32) 1) << scale) * 200); k 487 drivers/media/dvb-frontends/stv0367.c int i, j, k, freq; k 494 drivers/media/dvb-frontends/stv0367.c k = 1; /* equivalent to Xtal 25M on 362*/ k 496 drivers/media/dvb-frontends/stv0367.c k = 0; /* equivalent to Xtal 27M on 362*/ k 498 drivers/media/dvb-frontends/stv0367.c k = 2; /* equivalent to Xtal 30M on 362*/ k 508 drivers/media/dvb-frontends/stv0367.c MSB(CellsCoeffs[k][i-1][j-1])); k 511 drivers/media/dvb-frontends/stv0367.c LSB(CellsCoeffs[k][i-1][j-1])); k 626 drivers/media/firewire/firedtv-avc.c int ret, pos, k; k 646 drivers/media/firewire/firedtv-avc.c for (k = 0; k < pidc; k++) { k 649 drivers/media/firewire/firedtv-avc.c c->operand[pos++] = (pid[k] >> 8) & 0x1f; k 650 drivers/media/firewire/firedtv-avc.c c->operand[pos++] = pid[k] & 0xff; k 834 drivers/media/firewire/firedtv-avc.c int pos, j, k, ret; k 853 drivers/media/firewire/firedtv-avc.c for (k = 0; k < diseqcmd[j].msg_len; k++) k 854 drivers/media/firewire/firedtv-avc.c c->operand[pos++] = diseqcmd[j].msg[k]; k 516 drivers/media/i2c/cx25840/cx25840-ir.c unsigned int i, j, k; k 599 drivers/media/i2c/cx25840/cx25840-ir.c k = kfifo_in_locked(&ir_state->rx_kfifo, k 602 drivers/media/i2c/cx25840/cx25840-ir.c if (k != j) k 532 drivers/media/pci/cx23885/cx23888-ir.c unsigned int i, j, k; k 599 drivers/media/pci/cx23885/cx23888-ir.c k = kfifo_in_locked(&state->rx_kfifo, k 602 drivers/media/pci/cx23885/cx23888-ir.c if (k != j) k 479 drivers/media/pci/dm1105/dm1105.c int addr, rc, i, j, k, len, byte, data; k 513 drivers/media/pci/dm1105/dm1105.c k = 1; k 518 drivers/media/pci/dm1105/dm1105.c data = msgs[i].buf[k + byte]; k 532 drivers/media/pci/dm1105/dm1105.c k += 48; k 123 drivers/media/pci/ttpci/av7110_hw.c int k; k 127 drivers/media/pci/ttpci/av7110_hw.c for (k = 0; k < 100; k++) { k 778 drivers/media/pci/tw68/tw68-video.c int i, j, k; k 802 drivers/media/pci/tw68/tw68-video.c for (k = 0; k < 4; k++) { k 187 drivers/media/platform/am437x/am437x-vpfe.c unsigned int k; k 189 drivers/media/platform/am437x/am437x-vpfe.c for (k = 0; k < ARRAY_SIZE(formats); k++) { k 190 drivers/media/platform/am437x/am437x-vpfe.c fmt = &formats[k]; k 201 drivers/media/platform/am437x/am437x-vpfe.c unsigned int k; k 203 drivers/media/platform/am437x/am437x-vpfe.c for (k = 0; k < ARRAY_SIZE(formats); k++) { k 204 drivers/media/platform/am437x/am437x-vpfe.c fmt = &formats[k]; k 1506 drivers/media/platform/am437x/am437x-vpfe.c unsigned int k; k 1518 drivers/media/platform/am437x/am437x-vpfe.c for (k = 0; k < ARRAY_SIZE(formats); k++) { k 1519 drivers/media/platform/am437x/am437x-vpfe.c if (formats[k].index == f->index) { k 1520 drivers/media/platform/am437x/am437x-vpfe.c fmt = &formats[k]; k 282 drivers/media/platform/coda/coda-common.c int k; k 289 drivers/media/platform/coda/coda-common.c for (k = 0; k < num_codecs; k++) { k 290 drivers/media/platform/coda/coda-common.c if (codecs[k].src_fourcc == src_fourcc && k 291 drivers/media/platform/coda/coda-common.c codecs[k].dst_fourcc == dst_fourcc) k 295 drivers/media/platform/coda/coda-common.c if (k == num_codecs) k 298 drivers/media/platform/coda/coda-common.c return &codecs[k]; k 308 drivers/media/platform/coda/coda-common.c int k; k 314 drivers/media/platform/coda/coda-common.c for (k = 0, w = 0, h = 0; k < num_codecs; k++) { k 315 drivers/media/platform/coda/coda-common.c w = max(w, codecs[k].max_w); k 316 drivers/media/platform/coda/coda-common.c h = max(h, codecs[k].max_h); k 1369 drivers/media/platform/davinci/vpbe_display.c int k; k 1458 drivers/media/platform/davinci/vpbe_display.c for (k = 0; k < VPBE_DISPLAY_MAX_DEVICES; k++) { k 1460 drivers/media/platform/davinci/vpbe_display.c if (disp_dev->dev[k]) { k 1461 drivers/media/platform/davinci/vpbe_display.c video_unregister_device(&disp_dev->dev[k]->video_dev); k 1462 drivers/media/platform/davinci/vpbe_display.c kfree(disp_dev->dev[k]); k 1415 drivers/media/platform/davinci/vpif_capture.c int j, err, k; k 1478 drivers/media/platform/davinci/vpif_capture.c for (k = 0; k < j; k++) { k 1480 drivers/media/platform/davinci/vpif_capture.c ch = vpif_obj.dev[k]; k 1481 drivers/media/platform/davinci/vpif_capture.c common = &ch->common[k]; k 1143 drivers/media/platform/davinci/vpif_display.c int j, err, k; k 1148 drivers/media/platform/davinci/vpif_display.c for (k = 0; k < VPIF_NUMOBJECTS; k++) { k 1149 drivers/media/platform/davinci/vpif_display.c common = &ch->common[k]; k 1226 drivers/media/platform/davinci/vpif_display.c for (k = 0; k < j; k++) { k 1227 drivers/media/platform/davinci/vpif_display.c ch = vpif_obj.dev[k]; k 1228 drivers/media/platform/davinci/vpif_display.c common = &ch->common[k]; k 174 drivers/media/platform/imx-pxp.c unsigned int k; k 176 drivers/media/platform/imx-pxp.c for (k = 0; k < NUM_FORMATS; k++) { k 177 drivers/media/platform/imx-pxp.c fmt = &formats[k]; k 182 drivers/media/platform/imx-pxp.c if (k == NUM_FORMATS) k 185 drivers/media/platform/imx-pxp.c return &formats[k]; k 106 drivers/media/platform/m2m-deinterlace.c unsigned int k; k 108 drivers/media/platform/m2m-deinterlace.c for (k = 0; k < NUM_FORMATS; k++) { k 109 drivers/media/platform/m2m-deinterlace.c fmt = &formats[k]; k 115 drivers/media/platform/m2m-deinterlace.c if (k == NUM_FORMATS) k 118 drivers/media/platform/m2m-deinterlace.c return &formats[k]; k 144 drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c unsigned int k, fmt_flag; k 150 drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c for (k = 0; k < MTK_JPEG_NUM_FORMATS; k++) { k 151 drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c struct mtk_jpeg_fmt *fmt = &mtk_jpeg_formats[k]; k 77 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c unsigned int k; k 79 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c for (k = 0; k < NUM_FORMATS; k++) { k 80 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c fmt = &mtk_video_formats[k]; k 280 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c unsigned int k; k 283 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c for (k = 0; k < NUM_FORMATS; k++) { k 284 drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c fmt = &mtk_video_formats[k]; k 272 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c unsigned int k; k 274 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c for (k = 0; k < NUM_FORMATS; k++) { k 275 drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c fmt = &mtk_video_formats[k]; k 182 drivers/media/platform/mx2_emmaprp.c unsigned int k; k 184 drivers/media/platform/mx2_emmaprp.c for (k = 0; k < NUM_FORMATS; k++) { k 185 drivers/media/platform/mx2_emmaprp.c fmt = &formats[k]; k 190 drivers/media/platform/mx2_emmaprp.c if (k == NUM_FORMATS) k 193 drivers/media/platform/mx2_emmaprp.c return &formats[k]; k 1441 drivers/media/platform/omap/omap_vout.c int ret = 0, k; k 1452 drivers/media/platform/omap/omap_vout.c for (k = 0; k < pdev->num_resources; k++) { k 1460 drivers/media/platform/omap/omap_vout.c vout->vid = k; k 1461 drivers/media/platform/omap/omap_vout.c vid_dev->vouts[k] = vout; k 1465 drivers/media/platform/omap/omap_vout.c vout->vid_info.overlays[0] = vid_dev->overlays[k + 2]; k 1468 drivers/media/platform/omap/omap_vout.c vout->vid_info.overlays[0] = vid_dev->overlays[k + 1]; k 1470 drivers/media/platform/omap/omap_vout.c vout->vid_info.id = k + 1; k 1495 drivers/media/platform/omap/omap_vout.c if (omap_vout_setup_video_bufs(pdev, k) != 0) { k 1515 drivers/media/platform/omap/omap_vout.c if (k == (pdev->num_resources - 1)) k 1572 drivers/media/platform/omap/omap_vout.c int k; k 1578 drivers/media/platform/omap/omap_vout.c for (k = 0; k < pdev->num_resources; k++) k 1579 drivers/media/platform/omap/omap_vout.c omap_vout_cleanup_device(vid_dev->vouts[k]); k 1581 drivers/media/platform/omap/omap_vout.c for (k = 0; k < vid_dev->num_displays; k++) { k 1582 drivers/media/platform/omap/omap_vout.c if (vid_dev->displays[k]->state != OMAP_DSS_DISPLAY_DISABLED) k 1583 drivers/media/platform/omap/omap_vout.c vid_dev->displays[k]->driver->disable(vid_dev->displays[k]); k 1585 drivers/media/platform/omap/omap_vout.c omap_dss_put_device(vid_dev->displays[k]); k 535 drivers/media/platform/qcom/camss/camss-video.c int i, j, k; k 544 drivers/media/platform/qcom/camss/camss-video.c k = -1; k 553 drivers/media/platform/qcom/camss/camss-video.c k++; k 555 drivers/media/platform/qcom/camss/camss-video.c if (k == f->index) k 559 drivers/media/platform/qcom/camss/camss-video.c if (k < f->index) k 591 drivers/media/platform/qcom/camss/camss.c int i, j, k; k 673 drivers/media/platform/qcom/camss/camss.c for (k = 0; k < camss->vfe_num; k++) k 674 drivers/media/platform/qcom/camss/camss.c for (j = 0; j < ARRAY_SIZE(camss->vfe[k].line); j++) { k 678 drivers/media/platform/qcom/camss/camss.c &camss->vfe[k].line[j].subdev.entity, k 685 drivers/media/platform/qcom/camss/camss.c camss->vfe[k].line[j].subdev.entity.name, k 116 drivers/media/platform/qcom/venus/vdec.c unsigned int i, k = 0; k 128 drivers/media/platform/qcom/venus/vdec.c if (k == index && valid) k 131 drivers/media/platform/qcom/venus/vdec.c k++; k 88 drivers/media/platform/qcom/venus/venc.c unsigned int i, k = 0; k 100 drivers/media/platform/qcom/venus/venc.c if (k == index && valid) k 103 drivers/media/platform/qcom/venus/venc.c k++; k 1368 drivers/media/platform/s5p-jpeg/jpeg-core.c unsigned int k, fmt_flag; k 1379 drivers/media/platform/s5p-jpeg/jpeg-core.c for (k = 0; k < ARRAY_SIZE(sjpeg_formats); k++) { k 1380 drivers/media/platform/s5p-jpeg/jpeg-core.c struct s5p_jpeg_fmt *fmt = &sjpeg_formats[k]; k 315 drivers/media/platform/ti-vpe/cal.c unsigned int k; k 317 drivers/media/platform/ti-vpe/cal.c for (k = 0; k < ctx->num_active_fmt; k++) { k 318 drivers/media/platform/ti-vpe/cal.c fmt = ctx->active_fmt[k]; k 330 drivers/media/platform/ti-vpe/cal.c unsigned int k; k 332 drivers/media/platform/ti-vpe/cal.c for (k = 0; k < ctx->num_active_fmt; k++) { k 333 drivers/media/platform/ti-vpe/cal.c fmt = ctx->active_fmt[k]; k 1434 drivers/media/platform/ti-vpe/cal.c int i, j, k; k 1461 drivers/media/platform/ti-vpe/cal.c for (k = 0; k < ARRAY_SIZE(cal_formats); k++) { k 1462 drivers/media/platform/ti-vpe/cal.c fmt = &cal_formats[k]; k 344 drivers/media/platform/ti-vpe/vpe.c unsigned int k; k 346 drivers/media/platform/ti-vpe/vpe.c for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) { k 347 drivers/media/platform/ti-vpe/vpe.c fmt = &vpe_formats[k]; k 621 drivers/media/platform/vicodec/codec-fwht.c unsigned int k, l; k 629 drivers/media/platform/vicodec/codec-fwht.c for (k = 0; k < 8; k++) { k 663 drivers/media/platform/vicodec/codec-fwht.c int k, l; k 665 drivers/media/platform/vicodec/codec-fwht.c for (k = 0; k < 8; k++) { k 158 drivers/media/platform/vim2m.c unsigned int k; k 160 drivers/media/platform/vim2m.c for (k = 0; k < NUM_FORMATS; k++) { k 161 drivers/media/platform/vim2m.c fmt = &formats[k]; k 166 drivers/media/platform/vim2m.c if (k == NUM_FORMATS) k 169 drivers/media/platform/vim2m.c return &formats[k]; k 745 drivers/media/platform/vivid/vivid-vid-common.c unsigned k; k 747 drivers/media/platform/vivid/vivid-vid-common.c for (k = 0; k < ARRAY_SIZE(vivid_formats); k++) { k 748 drivers/media/platform/vivid/vivid-vid-common.c fmt = &vivid_formats[k]; k 101 drivers/media/tuners/e4000.c unsigned int div_n, k, k_cw, div_out; k 143 drivers/media/tuners/e4000.c div_n = div_u64_rem(f_vco, F_REF, &k); k 144 drivers/media/tuners/e4000.c k_cw = div_u64((u64) k * 0x10000, F_REF); k 148 drivers/media/tuners/e4000.c dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k, k 32 drivers/media/tuners/fc2580.c unsigned int uitmp, div_ref, div_ref_val, div_n, k, k_cw, div_out; k 91 drivers/media/tuners/fc2580.c div_n = div_u64_rem(f_vco, uitmp, &k); k 92 drivers/media/tuners/fc2580.c k_cw = div_u64((u64) k * 0x100000, uitmp); k 97 drivers/media/tuners/fc2580.c div_n, k, div_out, k_cw); k 87 drivers/media/tuners/msi001.c unsigned int uitmp, div_n, k, k_thresh, k_frac, div_lo, f_if1; k 211 drivers/media/tuners/msi001.c div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k); k 213 drivers/media/tuners/msi001.c k_frac = div_u64((u64) k * k_thresh, (DIV_PRE_N * F_REF)); k 3417 drivers/media/tuners/mxl5005s.c u16 i, j, k; k 3436 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->Init_Ctrl[i].size; k++) k 3437 drivers/media/tuners/mxl5005s.c ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); k 3458 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->CH_Ctrl[i].size; k++) k 3459 drivers/media/tuners/mxl5005s.c ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); k 3481 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->MXL_Ctrl[i].size; k++) k 3483 drivers/media/tuners/mxl5005s.c MXL_Ctrl[i].val[k] * k 3484 drivers/media/tuners/mxl5005s.c (1 << k); k 3513 drivers/media/tuners/mxl5005s.c u16 i, k ; k 3520 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->Init_Ctrl[i].size; k++) k 3521 drivers/media/tuners/mxl5005s.c ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k); k 3532 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->CH_Ctrl[i].size; k++) k 3533 drivers/media/tuners/mxl5005s.c ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); k 3546 drivers/media/tuners/mxl5005s.c for (k = 0; k < state->MXL_Ctrl[i].size; k++) k 3547 drivers/media/tuners/mxl5005s.c ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); k 203 drivers/media/usb/au0828/au0828-video.c int j, k; k 260 drivers/media/usb/au0828/au0828-video.c k = 0; k 262 drivers/media/usb/au0828/au0828-video.c urb->iso_frame_desc[j].offset = k; k 265 drivers/media/usb/au0828/au0828-video.c k += dev->isoc_ctl.max_pkt_size; k 275 drivers/media/usb/cx231xx/cx231xx-audio.c int j, k; k 302 drivers/media/usb/cx231xx/cx231xx-audio.c for (j = k = 0; j < CX231XX_ISO_NUM_AUDIO_PACKETS; k 303 drivers/media/usb/cx231xx/cx231xx-audio.c j++, k += dev->adev.max_pkt_size) { k 304 drivers/media/usb/cx231xx/cx231xx-audio.c urb->iso_frame_desc[j].offset = k; k 995 drivers/media/usb/cx231xx/cx231xx-core.c int j, k; k 1086 drivers/media/usb/cx231xx/cx231xx-core.c k = 0; k 1088 drivers/media/usb/cx231xx/cx231xx-core.c urb->iso_frame_desc[j].offset = k; k 1091 drivers/media/usb/cx231xx/cx231xx-core.c k += dev->video_mode.isoc_ctl.max_pkt_size; k 430 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c int i, k, ret = 0; k 540 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c for (k = 0; k < 26; k++) k 541 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c buf[k] = USB_END_I2C_CMD; k 665 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c for (k = 0; k 666 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c k < 8-(i+1); k 667 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c k++) { k 669 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c msg->buf[(index*8)+(k+i+1)] = k 670 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c readbuff[k]; k 672 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c msg->buf[(index*8)+(k+i)], k 673 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c (index*8)+(k+i)); k 675 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c msg->buf[(index*8)+(k+i+1)], k 676 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c readbuff[k]); k 698 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c for (k = 0; k < 26; k++) k 699 drivers/media/usb/dvb-usb-v2/mxl111sf-i2c.c buf[k] = USB_END_I2C_CMD; k 860 drivers/media/usb/em28xx/em28xx-audio.c int j, k; k 890 drivers/media/usb/em28xx/em28xx-audio.c for (j = k = 0; j < npackets; j++, k += ep_size) { k 891 drivers/media/usb/em28xx/em28xx-audio.c urb->iso_frame_desc[j].offset = k; k 618 drivers/media/usb/em28xx/em28xx-core.c u8 k = 0; k 620 drivers/media/usb/em28xx/em28xx-core.c while (dev->board.leds[k].role >= 0 && k 621 drivers/media/usb/em28xx/em28xx-core.c dev->board.leds[k].role < EM28XX_NUM_LED_ROLES) { k 622 drivers/media/usb/em28xx/em28xx-core.c if (dev->board.leds[k].role == role) k 623 drivers/media/usb/em28xx/em28xx-core.c return &dev->board.leds[k]; k 624 drivers/media/usb/em28xx/em28xx-core.c k++; k 892 drivers/media/usb/em28xx/em28xx-core.c int j, k; k 987 drivers/media/usb/em28xx/em28xx-core.c k = 0; k 989 drivers/media/usb/em28xx/em28xx-core.c urb->iso_frame_desc[j].offset = k; k 992 drivers/media/usb/em28xx/em28xx-core.c k += usb_bufs->max_pkt_size; k 562 drivers/media/usb/gspca/cpia1.c u8 i, u8 j, u8 k, u8 l) k 580 drivers/media/usb/gspca/cpia1.c gspca_dev->usb_buf[6] = k; k 428 drivers/media/usb/gspca/pac7302.c const unsigned int k = 1000; /* precision factor */ k 432 drivers/media/usb/gspca/pac7302.c norm = k * (rgb_ctrl_val - PAC7302_RGB_BALANCE_MIN) k 435 drivers/media/usb/gspca/pac7302.c return 64 * norm * norm / (k*k) + 32 * norm / k + 32; k 673 drivers/media/usb/msi2500/msi2500.c unsigned int f_vco, f_sr, div_n, k, k_cw, div_out; k 781 drivers/media/usb/msi2500/msi2500.c div_n = div_u64_rem(f_vco, DIV_PRE_N * F_REF, &k); k 782 drivers/media/usb/msi2500/msi2500.c k_cw = div_u64((u64) k * 0x200000, DIV_PRE_N * F_REF); k 791 drivers/media/usb/msi2500/msi2500.c f_sr, f_vco, div_n, k, div_out, reg3, reg4); k 92 drivers/media/usb/pwc/pwc-dec23.c int compression_mode, j, k, bit, pw; k 104 drivers/media/usb/pwc/pwc-dec23.c for (k = 0; k < 16; k++) { k 105 drivers/media/usb/pwc/pwc-dec23.c if (k == 0) k 107 drivers/media/usb/pwc/pwc-dec23.c else if (k >= 1 && k < 3) k 109 drivers/media/usb/pwc/pwc-dec23.c else if (k >= 3 && k < 6) k 111 drivers/media/usb/pwc/pwc-dec23.c else if (k >= 6 && k < 10) k 113 drivers/media/usb/pwc/pwc-dec23.c else if (k >= 10 && k < 13) k 115 drivers/media/usb/pwc/pwc-dec23.c else if (k >= 13 && k < 15) k 119 drivers/media/usb/pwc/pwc-dec23.c if (k == 0) k 126 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x00] = (1 * pw) + 0x80; k 127 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x10] = (2 * pw) + 0x80; k 128 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x20] = (3 * pw) + 0x80; k 129 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x30] = (4 * pw) + 0x80; k 130 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x40] = (-1 * pw) + 0x80; k 131 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x50] = (-2 * pw) + 0x80; k 132 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x60] = (-3 * pw) + 0x80; k 133 drivers/media/usb/pwc/pwc-dec23.c p0[k + 0x70] = (-4 * pw) + 0x80; k 414 drivers/media/usb/stk1160/stk1160-video.c int i, j, k, sb_size, max_packets, num_bufs; k 489 drivers/media/usb/stk1160/stk1160-video.c k = 0; k 491 drivers/media/usb/stk1160/stk1160-video.c urb->iso_frame_desc[j].offset = k; k 494 drivers/media/usb/stk1160/stk1160-video.c k += dev->isoc_ctl.max_pkt_size; k 146 drivers/media/usb/usbvision/usbvision-core.c int i, k; k 148 drivers/media/usb/usbvision/usbvision-core.c for (i = k = 0; len > 0; i++, len--) { k 151 drivers/media/usb/usbvision/usbvision-core.c k = 0; k 153 drivers/media/usb/usbvision/usbvision-core.c k += sprintf(&tmp[k], "%02x ", data[i]); k 155 drivers/media/usb/usbvision/usbvision-core.c if (k > 0) k 2283 drivers/media/usb/usbvision/usbvision-core.c int j, k; k 2308 drivers/media/usb/usbvision/usbvision-core.c for (j = k = 0; j < USBVISION_URB_FRAMES; j++, k 2309 drivers/media/usb/usbvision/usbvision-core.c k += usbvision->isoc_packet_size) { k 2310 drivers/media/usb/usbvision/usbvision-core.c urb->iso_frame_desc[j].offset = k; k 394 drivers/mfd/sm501.c unsigned int m, n, k; k 453 drivers/mfd/sm501.c unsigned int m, n, k; k 462 drivers/mfd/sm501.c for (k = 0; k <= 1; k++) { k 463 drivers/mfd/sm501.c mclk = (24000000UL * m / n) >> k; k 469 drivers/mfd/sm501.c clock->k = k; k 542 drivers/mfd/sm501.c pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; k 403 drivers/misc/altera-stapl/altera-jtag.c u32 i, j, k; k 414 drivers/misc/altera-stapl/altera-jtag.c k = preamble_count + target_count; k 415 drivers/misc/altera-stapl/altera-jtag.c for (; i < k; ++i, ++j) { k 424 drivers/misc/altera-stapl/altera-jtag.c k = preamble_count + target_count + postamble_count; k 425 drivers/misc/altera-stapl/altera-jtag.c for (; i < k; ++i, ++j) { k 570 drivers/misc/altera-stapl/altera-jtag.c u32 k; k 573 drivers/misc/altera-stapl/altera-jtag.c k = start_index + target_count; k 574 drivers/misc/altera-stapl/altera-jtag.c for (i = start_index; i < k; ++i, ++j) { k 142 drivers/misc/altera-stapl/altera.c u32 size, line, lines, linebits, value, j, k; k 165 drivers/misc/altera-stapl/altera.c for (k = 0; k < linebits; ++k) { k 166 drivers/misc/altera-stapl/altera.c i = k + offset; k 175 drivers/misc/altera-stapl/altera.c if ((k & 3) > 0) k 1647 drivers/misc/altera-stapl/altera.c s32 k = long_idx; k 1657 drivers/misc/altera-stapl/altera.c if (charptr_tmp[k >> 3] & k 1658 drivers/misc/altera-stapl/altera.c (1 << (k & 7))) k 1665 drivers/misc/altera-stapl/altera.c ++k; k 578 drivers/misc/mei/hdcp/mei_hdcp.c (data->k * sizeof(struct hdcp2_streamid_type))); k 580 drivers/misc/mei/hdcp/mei_hdcp.c verify_mprime_in.k = cpu_to_be16(data->k); k 357 drivers/misc/mei/hdcp/mei_hdcp.h __be16 k; k 576 drivers/misc/mic/scif/scif_rma.c int i, j, k, err = 0, nr_contig_pages; k 592 drivers/misc/mic/scif/scif_rma.c for (k = i + 1; k < window->nr_pages; k++) { k 593 drivers/misc/mic/scif/scif_rma.c phys_curr = page_to_phys(pin->pages[k]); k 24 drivers/misc/mic/vop/vop_debugfs.c int j, k; k 59 drivers/misc/mic/vop/vop_debugfs.c for (k = 0; k < d->num_vq; k++) { k 60 drivers/misc/mic/vop/vop_debugfs.c vqconfig = mic_vq_config(d) + k; k 61 drivers/misc/mic/vop/vop_debugfs.c seq_printf(s, "vqconfig[%d]: ", k); k 74 drivers/misc/mic/vop/vop_debugfs.c for (k = 0; k < d->config_len; k++) k 75 drivers/misc/mic/vop/vop_debugfs.c seq_printf(s, "config[%d]=%d\n", k, config[k]); k 145 drivers/misc/sgi-gru/grufault.c unsigned long i, k; k 151 drivers/misc/sgi-gru/grufault.c k = tfm->fault_bits[i]; k 152 drivers/misc/sgi-gru/grufault.c if (k) k 153 drivers/misc/sgi-gru/grufault.c k = xchg(&tfm->fault_bits[i], 0UL); k 154 drivers/misc/sgi-gru/grufault.c imap->fault_bits[i] = k; k 155 drivers/misc/sgi-gru/grufault.c k = tfm->done_bits[i]; k 156 drivers/misc/sgi-gru/grufault.c if (k) k 157 drivers/misc/sgi-gru/grufault.c k = xchg(&tfm->done_bits[i], 0UL); k 158 drivers/misc/sgi-gru/grufault.c dmap->fault_bits[i] = k; k 1051 drivers/misc/sgi-gru/grukservices.c int i, k, istatus, bytes; k 1070 drivers/misc/sgi-gru/grukservices.c k = numcb; k 1090 drivers/misc/sgi-gru/grukservices.c k--; k 1093 drivers/misc/sgi-gru/grukservices.c } while (k); k 527 drivers/misc/sgi-gru/grutables.h #define for_each_cbr_in_allocation_map(i, map, k) \ k 528 drivers/misc/sgi-gru/grutables.h for_each_set_bit((k), (map), GRU_CBR_AU) \ k 529 drivers/misc/sgi-gru/grutables.h for ((i) = (k)*GRU_CBR_AU_SIZE; \ k 530 drivers/misc/sgi-gru/grutables.h (i) < ((k) + 1) * GRU_CBR_AU_SIZE; (i)++) k 533 drivers/misc/sgi-gru/grutables.h #define for_each_dsr_in_allocation_map(i, map, k) \ k 534 drivers/misc/sgi-gru/grutables.h for_each_set_bit((k), (const unsigned long *)(map), GRU_DSR_AU) \ k 535 drivers/misc/sgi-gru/grutables.h for ((i) = (k) * GRU_DSR_AU_CL; \ k 536 drivers/misc/sgi-gru/grutables.h (i) < ((k) + 1) * GRU_DSR_AU_CL; (i)++) k 458 drivers/misc/xilinx_sdfec.c static int xsdfec_reg0_write(struct xsdfec_dev *xsdfec, u32 n, u32 k, u32 psize, k 464 drivers/misc/xilinx_sdfec.c (n > XSDFEC_REG0_N_MUL_P * psize) || n <= k || ((n % psize) != 0)) { k 470 drivers/misc/xilinx_sdfec.c if (k < XSDFEC_REG0_K_MIN || k > XSDFEC_REG0_K_MAX || k 471 drivers/misc/xilinx_sdfec.c (k > XSDFEC_REG0_K_MUL_P * psize) || ((k % psize) != 0)) { k 475 drivers/misc/xilinx_sdfec.c k = k << XSDFEC_REG0_K_LSB; k 476 drivers/misc/xilinx_sdfec.c wdata = k | n; k 678 drivers/misc/xilinx_sdfec.c ret = xsdfec_reg0_write(xsdfec, ldpc->n, ldpc->k, ldpc->psize, k 1275 drivers/mmc/host/wbsd.c int i, j, k; k 1302 drivers/mmc/host/wbsd.c for (k = 0; k < ARRAY_SIZE(valid_ids); k++) { k 1303 drivers/mmc/host/wbsd.c if (id == valid_ids[k]) { k 196 drivers/mtd/nand/raw/atmel/pmecc.c const unsigned int k = BIT(deg(poly)); k 200 drivers/mtd/nand/raw/atmel/pmecc.c if (k != (1u << mm)) k 210 drivers/mtd/nand/raw/atmel/pmecc.c if (x & k) k 500 drivers/mtd/nand/raw/atmel/pmecc.c int i, j, k; k 593 drivers/mtd/nand/raw/atmel/pmecc.c for (k = 0; k < num; k++) k 594 drivers/mtd/nand/raw/atmel/pmecc.c smu[(i + 1) * num + k] = 0; k 597 drivers/mtd/nand/raw/atmel/pmecc.c for (k = 0; k <= lmu[ro] >> 1; k++) { k 600 drivers/mtd/nand/raw/atmel/pmecc.c if (!(smu[ro * num + k] && dmu[i])) k 605 drivers/mtd/nand/raw/atmel/pmecc.c c = index_of[smu[ro * num + k]]; k 608 drivers/mtd/nand/raw/atmel/pmecc.c smu[(i + 1) * num + (k + diff)] = a; k 611 drivers/mtd/nand/raw/atmel/pmecc.c for (k = 0; k <= lmu[i] >> 1; k++) k 612 drivers/mtd/nand/raw/atmel/pmecc.c smu[(i + 1) * num + k] ^= smu[i * num + k]; k 623 drivers/mtd/nand/raw/atmel/pmecc.c for (k = 0; k <= (lmu[i + 1] >> 1); k++) { k 625 drivers/mtd/nand/raw/atmel/pmecc.c if (k == 0) { k 627 drivers/mtd/nand/raw/atmel/pmecc.c } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) { k 630 drivers/mtd/nand/raw/atmel/pmecc.c a = index_of[smu[(i + 1) * num + k]]; k 631 drivers/mtd/nand/raw/atmel/pmecc.c b = si[2 * (i - 1) + 3 - k]; k 439 drivers/mtd/nand/raw/fsmc_nand.c int k, written_bits = 0; k 441 drivers/mtd/nand/raw/fsmc_nand.c for (k = 0; k < size; k++) { k 442 drivers/mtd/nand/raw/fsmc_nand.c written_bits += hweight8(~buff[k]); k 114 drivers/mtd/nand/raw/nand_onfi.c int i, j, k; k 122 drivers/mtd/nand/raw/nand_onfi.c for (k = 0; k < nsrcbufs; k++) { k 123 drivers/mtd/nand/raw/nand_onfi.c const u8 *srcbuf = srcbufs[k]; k 77 drivers/mtd/ssfdc.c int k; k 80 drivers/mtd/ssfdc.c k = 0; k 81 drivers/mtd/ssfdc.c while (chs_table[k].size > 0 && size > chs_table[k].size) k 82 drivers/mtd/ssfdc.c k++; k 84 drivers/mtd/ssfdc.c if (chs_table[k].size > 0) { k 86 drivers/mtd/ssfdc.c *cyl = chs_table[k].cyl; k 88 drivers/mtd/ssfdc.c *head = chs_table[k].head; k 90 drivers/mtd/ssfdc.c *sec = chs_table[k].sec; k 105 drivers/mtd/ssfdc.c int ret, k, cis_sector; k 121 drivers/mtd/ssfdc.c for (k = 0, offset = 0; k < 4; k++, offset += mtd->erasesize) { k 185 drivers/mtd/ssfdc.c int k; k 189 drivers/mtd/ssfdc.c for (k = 0; k < size; k++) { k 190 drivers/mtd/ssfdc.c parity += (number >> k); k 210 drivers/mtd/tests/oobtest.c int k; k 239 drivers/mtd/tests/oobtest.c k = use_offset + use_len; k 240 drivers/mtd/tests/oobtest.c bitflips += memffshow(addr, k, readbuf + k, k 241 drivers/mtd/tests/oobtest.c mtd->oobavail - k); k 163 drivers/mtd/tests/speedtest.c uint64_t k; k 169 drivers/mtd/tests/speedtest.c k = (uint64_t)goodebcnt * (mtd->erasesize / 1024) * 1000; k 170 drivers/mtd/tests/speedtest.c do_div(k, ms); k 171 drivers/mtd/tests/speedtest.c return k; k 176 drivers/mtd/tests/speedtest.c int err, i, blocks, j, k; k 371 drivers/mtd/tests/speedtest.c for (k = 1; k < 7; k++) { k 372 drivers/mtd/tests/speedtest.c blocks = 1 << k; k 81 drivers/mtd/tests/subpagetest.c int err = 0, k; k 84 drivers/mtd/tests/subpagetest.c for (k = 1; k < 33; ++k) { k 85 drivers/mtd/tests/subpagetest.c if (addr + (subpgsize * k) > (loff_t)(ebnum + 1) * mtd->erasesize) k 87 drivers/mtd/tests/subpagetest.c prandom_bytes_state(&rnd_state, writebuf, subpgsize * k); k 88 drivers/mtd/tests/subpagetest.c err = mtd_write(mtd, addr, subpgsize * k, &written, writebuf); k 89 drivers/mtd/tests/subpagetest.c if (unlikely(err || written != subpgsize * k)) { k 92 drivers/mtd/tests/subpagetest.c if (written != subpgsize * k) { k 94 drivers/mtd/tests/subpagetest.c subpgsize * k); k 100 drivers/mtd/tests/subpagetest.c addr += subpgsize * k; k 181 drivers/mtd/tests/subpagetest.c int err = 0, k; k 184 drivers/mtd/tests/subpagetest.c for (k = 1; k < 33; ++k) { k 185 drivers/mtd/tests/subpagetest.c if (addr + (subpgsize * k) > (loff_t)(ebnum + 1) * mtd->erasesize) k 187 drivers/mtd/tests/subpagetest.c prandom_bytes_state(&rnd_state, writebuf, subpgsize * k); k 188 drivers/mtd/tests/subpagetest.c clear_data(readbuf, subpgsize * k); k 189 drivers/mtd/tests/subpagetest.c err = mtd_read(mtd, addr, subpgsize * k, &read, readbuf); k 190 drivers/mtd/tests/subpagetest.c if (unlikely(err || read != subpgsize * k)) { k 191 drivers/mtd/tests/subpagetest.c if (mtd_is_bitflip(err) && read == subpgsize * k) { k 201 drivers/mtd/tests/subpagetest.c if (unlikely(memcmp(readbuf, writebuf, subpgsize * k))) { k 206 drivers/mtd/tests/subpagetest.c addr += subpgsize * k; k 1173 drivers/mtd/ubi/build.c int err, i, k; k 1266 drivers/mtd/ubi/build.c for (k = 0; k < i; k++) k 1267 drivers/mtd/ubi/build.c if (ubi_devices[k]) { k 1269 drivers/mtd/ubi/build.c ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1); k 317 drivers/net/dsa/sja1105/sja1105_ethtool.c int rc, i, k = 0; k 328 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.n_runt; k 329 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.n_soferr; k 330 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.n_alignerr; k 331 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.n_miierr; k 332 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.typeerr; k 333 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.sizeerr; k 334 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.tctimeout; k 335 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.priorerr; k 336 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.nomaster; k 337 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.memov; k 338 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.memerr; k 339 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.invtyp; k 340 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.intcyov; k 341 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.domerr; k 342 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.pcfbagdrop; k 343 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.spcprior; k 344 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.ageprior; k 345 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.portdrop; k 346 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.lendrop; k 347 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.bagdrop; k 348 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.policeerr; k 349 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.drpnona664err; k 350 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.spcerr; k 351 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.mac.agedrp; k 352 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_n664err; k 353 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_vlanerr; k 354 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_unreleased; k 355 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_sizeerr; k 356 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_crcerr; k 357 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_vlnotfound; k 358 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_ctpolerr; k 359 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_polerr; k 360 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_rxfrm; k 361 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_rxbyte; k 362 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_txfrm; k 363 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl1.n_txbyte; k 364 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.n_qfull; k 365 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.n_part_drop; k 366 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.n_egr_disabled; k 367 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.n_not_reach; k 373 drivers/net/dsa/sja1105/sja1105_ethtool.c memset(data + k, 0, ARRAY_SIZE(sja1105pqrs_extra_port_stats) * k 376 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.qlevel_hwm[i]; k 377 drivers/net/dsa/sja1105/sja1105_ethtool.c data[k++] = status.hl2.qlevel[i]; k 429 drivers/net/dsa/sja1105/sja1105_main.c int i, k = 0; k 435 drivers/net/dsa/sja1105/sja1105_main.c priv->ports[i].mgmt_slot = k++; k 476 drivers/net/dsa/sja1105/sja1105_main.c int i, j, k; k 498 drivers/net/dsa/sja1105/sja1105_main.c for (i = 0, k = 0; i < SJA1105_NUM_PORTS; i++) { k 501 drivers/net/dsa/sja1105/sja1105_main.c for (j = 0; j < SJA1105_NUM_TC; j++, k++) k 502 drivers/net/dsa/sja1105/sja1105_main.c sja1105_setup_policer(policing, k); k 101 drivers/net/dsa/sja1105/sja1105_tas.c int i, k = 0; k 197 drivers/net/dsa/sja1105/sja1105_tas.c schedule_start_idx = k; k 198 drivers/net/dsa/sja1105/sja1105_tas.c schedule_end_idx = k + offload->num_entries - 1; k 219 drivers/net/dsa/sja1105/sja1105_tas.c for (i = 0; i < offload->num_entries; i++, k++) { k 222 drivers/net/dsa/sja1105/sja1105_tas.c schedule[k].delta = ns_to_sja1105_delta(delta_ns); k 223 drivers/net/dsa/sja1105/sja1105_tas.c schedule[k].destports = BIT(port); k 224 drivers/net/dsa/sja1105/sja1105_tas.c schedule[k].resmedia_en = true; k 225 drivers/net/dsa/sja1105/sja1105_tas.c schedule[k].resmedia = SJA1105_GATE_MASK & k 2766 drivers/net/ethernet/3com/3c59x.c int k; k 2768 drivers/net/ethernet/3com/3c59x.c for (k=0; k<=skb_shinfo(skb)->nr_frags; k++) k 2770 drivers/net/ethernet/3com/3c59x.c le32_to_cpu(vp->tx_ring[i].frag[k].addr), k 2771 drivers/net/ethernet/3com/3c59x.c le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF, k 1955 drivers/net/ethernet/agere/et131x.c u32 k = (i * FBR_CHUNKS) + j; k 1960 drivers/net/ethernet/agere/et131x.c fbr->virt[k] = (u8 *)fbr->mem_virtaddrs[i] + k 1966 drivers/net/ethernet/agere/et131x.c fbr->bus_high[k] = upper_32_bits(fbr_physaddr); k 1967 drivers/net/ethernet/agere/et131x.c fbr->bus_low[k] = lower_32_bits(fbr_physaddr); k 1449 drivers/net/ethernet/amazon/ena/ena_netdev.c int rc = 0, i, k; k 1478 drivers/net/ethernet/amazon/ena/ena_netdev.c for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) { k 1479 drivers/net/ethernet/amazon/ena/ena_netdev.c irq = &adapter->irq_tbl[k]; k 933 drivers/net/ethernet/amd/ni65.c int k, num1; k 934 drivers/net/ethernet/amd/ni65.c for(k=0;k<RMDNUM;k++) { k 935 drivers/net/ethernet/amd/ni65.c num1 = (p->rmdnum + k) & (RMDNUM-1); k 939 drivers/net/ethernet/amd/ni65.c if(!k) k 946 drivers/net/ethernet/amd/ni65.c for(k=0;k<RMDNUM;k++) { k 947 drivers/net/ethernet/amd/ni65.c sprintf(buf1,"%02x ",(p->rmdhead[k].u.s.status)); /* & RCV_OWN) ); */ k 96 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c int k = 0; k 122 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c for (k = 0; k < 1000; k++) { k 131 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c if (k == 1000) { k 152 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c for (k = 0; k < 1000; k++) { k 159 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c if (k == 1000) { k 172 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c int k; k 201 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c for (k = 0; k < 1000; k++) { k 221 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c for (k = 0; k < 1000; k++) { k 228 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c if (k == 1000) { k 240 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c int k; k 244 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c for (k = 0; k < 1000; ++k) { k 253 drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c if (k == 1000) { k 1518 drivers/net/ethernet/broadcom/b44.c int k, j, len = offset; k 1534 drivers/net/ethernet/broadcom/b44.c for (k = 0; k< ethaddr_bytes; k++) { k 1536 drivers/net/ethernet/broadcom/b44.c (j * ETH_ALEN) + k] = macaddr[k]; k 5448 drivers/net/ethernet/broadcom/bnx2.c int k, last; k 5464 drivers/net/ethernet/broadcom/bnx2.c for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) { k 5468 drivers/net/ethernet/broadcom/bnx2.c skb_frag_size(&skb_shinfo(skb)->frags[k]), k 8290 drivers/net/ethernet/broadcom/bnx2.c u8 num, k, skip0; k 8298 drivers/net/ethernet/broadcom/bnx2.c for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { k 8299 drivers/net/ethernet/broadcom/bnx2.c if (num >= k || !skip0 || k == 1) { k 8300 drivers/net/ethernet/broadcom/bnx2.c bp->fw_version[j++] = (num / k) + '0'; k 852 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c u32 i, j, k, n; k 872 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c for (k = 0; k < read_num; k++) { k 873 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c if (IS_REG_IN_PRESET(read_addr[k].presets, k 875 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c size = read_addr[k].size; k 877 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c addr = read_addr[k].addr + n*4; k 3187 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c int i, j, k, start; k 3192 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c k = 0; k 3199 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c snprintf(buf + (k + j)*ETH_GSTRING_LEN, k 3203 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c k += BNX2X_NUM_Q_STATS; k 3210 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c strcpy(buf + (k + j)*ETH_GSTRING_LEN, k 3239 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c int i, j, k = 0; k 3247 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = 0; k 3254 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = (u64) *offset; k 3258 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = HILO_U64(*offset, *(offset + 1)); k 3260 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c k += BNX2X_NUM_Q_STATS; k 3270 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = 0; k 3277 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = (u64) *offset; k 3282 drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c buf[k + j] = HILO_U64(*offset, *(offset + 1)); k 2489 drivers/net/ethernet/broadcom/bnxt/bnxt.c int k, last; k 2525 drivers/net/ethernet/broadcom/bnxt/bnxt.c for (k = 0; k < last; k++, j++) { k 2527 drivers/net/ethernet/broadcom/bnxt/bnxt.c skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; k 4872 drivers/net/ethernet/broadcom/bnxt/bnxt.c u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings; k 4887 drivers/net/ethernet/broadcom/bnxt/bnxt.c for (i = 0, k = 0; i < nr_ctxs; i++) { k 4901 drivers/net/ethernet/broadcom/bnxt/bnxt.c k++; k 4902 drivers/net/ethernet/broadcom/bnxt/bnxt.c if (k == max_rings) { k 4903 drivers/net/ethernet/broadcom/bnxt/bnxt.c k = 0; k 551 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c int k; k 553 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c for (k = 0; k < stat_fields; j++, k++) k 554 drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c buf[j] = le64_to_cpu(hw_stats[k]); k 408 drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c u32 nr_pages, size, i, j, k = 0; k 430 drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c for (j = 0; j < BNXT_HWRM_REQS_PER_PAGE && k < num_vfs; j++) { k 431 drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c struct bnxt_vf_info *vf = &bp->pf.vf[k]; k 438 drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c k++; k 913 drivers/net/ethernet/broadcom/cnic.c int i, k, arr_size; k 923 drivers/net/ethernet/broadcom/cnic.c k = 0; k 935 drivers/net/ethernet/broadcom/cnic.c for (j = lo; j < hi; j += cp->cids_per_blk, k++) k 936 drivers/net/ethernet/broadcom/cnic.c cp->ctx_arr[k].cid = j; k 939 drivers/net/ethernet/broadcom/cnic.c cp->ctx_blks = k; k 9719 drivers/net/ethernet/broadcom/tg3.c int j, k; k 9726 drivers/net/ethernet/broadcom/tg3.c for (k = 0; k < 8; k++) { k 12892 drivers/net/ethernet/broadcom/tg3.c int i, j, k, err = 0, size; k 12981 drivers/net/ethernet/broadcom/tg3.c for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { k 12987 drivers/net/ethernet/broadcom/tg3.c parity[k++] = buf8[i] & msk; k 12994 drivers/net/ethernet/broadcom/tg3.c parity[k++] = buf8[i] & msk; k 12998 drivers/net/ethernet/broadcom/tg3.c parity[k++] = buf8[i] & msk; k 203 drivers/net/ethernet/brocade/bna/bna_enet.c int k; k 206 drivers/net/ethernet/brocade/bna/bna_enet.c for (k = 0; k < count; k++) { k 207 drivers/net/ethernet/brocade/bna/bna_enet.c stats_dst[k] = be64_to_cpu(*stats_src); k 218 drivers/net/ethernet/brocade/bna/bna_enet.c int k; k 221 drivers/net/ethernet/brocade/bna/bna_enet.c for (k = 0; k < count; k++) { k 222 drivers/net/ethernet/brocade/bna/bna_enet.c stats_dst[k] = be64_to_cpu(*stats_src); k 1015 drivers/net/ethernet/chelsio/cxgb3/sge.c unsigned int i, j = 0, k = 0, nfrags; k 1019 drivers/net/ethernet/chelsio/cxgb3/sge.c sgp->addr[j++] = cpu_to_be64(addr[k++]); k 1027 drivers/net/ethernet/chelsio/cxgb3/sge.c sgp->addr[j] = cpu_to_be64(addr[k++]); k 1985 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c u8 i, k; k 2058 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++) k 2059 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c dst_off[k] = cpu_to_be64(src_off[k]); k 2838 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c int i, k, rc; k 2850 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c for (k = 0; k < mbox_cmds; k++) { k 2851 drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c entry_idx = log->cursor + k; k 3559 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c unsigned int i, j, k; k 3646 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { k 3684 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c cpu_to_be64(adapter->hma.phy_addr[j + k]); k 3463 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c int k, int c) k 3472 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c if (k > c) { k 3484 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), k 3485 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); k 3546 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c uint32_t d, c, k; k 3550 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; k 3561 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), k 3562 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); k 157 drivers/net/ethernet/cisco/enic/enic_clsf.c struct flow_keys *k) k 162 drivers/net/ethernet/cisco/enic/enic_clsf.c if (tpos->keys.addrs.v4addrs.src == k->addrs.v4addrs.src && k 163 drivers/net/ethernet/cisco/enic/enic_clsf.c tpos->keys.addrs.v4addrs.dst == k->addrs.v4addrs.dst && k 164 drivers/net/ethernet/cisco/enic/enic_clsf.c tpos->keys.ports.ports == k->ports.ports && k 165 drivers/net/ethernet/cisco/enic/enic_clsf.c tpos->keys.basic.ip_proto == k->basic.ip_proto && k 166 drivers/net/ethernet/cisco/enic/enic_clsf.c tpos->keys.basic.n_proto == k->basic.n_proto) k 994 drivers/net/ethernet/dec/tulip/de4x5.c static void de4x5_dbg_mii(struct net_device *dev, int k); k 4031 drivers/net/ethernet/dec/tulip/de4x5.c int broken, i, k, tmp, status = 0; k 4037 drivers/net/ethernet/dec/tulip/de4x5.c for (i=0,k=0,j=0;j<3;j++) { k 4038 drivers/net/ethernet/dec/tulip/de4x5.c k <<= 1; k 4039 drivers/net/ethernet/dec/tulip/de4x5.c if (k > 0xffff) k-=0xffff; k 4044 drivers/net/ethernet/dec/tulip/de4x5.c k += (u_char) tmp; k 4047 drivers/net/ethernet/dec/tulip/de4x5.c k += (u_short) (tmp << 8); k 4057 drivers/net/ethernet/dec/tulip/de4x5.c k += (u_char) (tmp = inb(EISA_APROM)); k 4059 drivers/net/ethernet/dec/tulip/de4x5.c k += (u_short) ((tmp = inb(EISA_APROM)) << 8); k 4063 drivers/net/ethernet/dec/tulip/de4x5.c if (k > 0xffff) k-=0xffff; k 4065 drivers/net/ethernet/dec/tulip/de4x5.c if (k == 0xffff) k=0; k 4073 drivers/net/ethernet/dec/tulip/de4x5.c if ((k != chksum) && (dec_only)) status = -1; k 4078 drivers/net/ethernet/dec/tulip/de4x5.c if ((k != chksum) && (dec_only)) status = -1; k 4973 drivers/net/ethernet/dec/tulip/de4x5.c int i, j, k, n, limit=ARRAY_SIZE(phy_info); k 4988 drivers/net/ethernet/dec/tulip/de4x5.c for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); k 4989 drivers/net/ethernet/dec/tulip/de4x5.c if (k < DE4X5_MAX_PHY) { k 4990 drivers/net/ethernet/dec/tulip/de4x5.c memcpy((char *)&lp->phy[k], k 4992 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].addr = i; k 5001 drivers/net/ethernet/dec/tulip/de4x5.c for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); k 5002 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].addr = i; k 5003 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].id = id; k 5004 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ k 5005 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ k 5006 drivers/net/ethernet/dec/tulip/de4x5.c lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */ k 5012 drivers/net/ethernet/dec/tulip/de4x5.c de4x5_dbg_mii(dev, k); k 5020 drivers/net/ethernet/dec/tulip/de4x5.c for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/ k 5021 drivers/net/ethernet/dec/tulip/de4x5.c mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII); k 5022 drivers/net/ethernet/dec/tulip/de4x5.c while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST); k 5024 drivers/net/ethernet/dec/tulip/de4x5.c de4x5_dbg_mii(dev, k); k 5266 drivers/net/ethernet/dec/tulip/de4x5.c de4x5_dbg_mii(struct net_device *dev, int k) k 5272 drivers/net/ethernet/dec/tulip/de4x5.c printk("\nMII device address: %d\n", lp->phy[k].addr); k 5273 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII)); k 5274 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII)); k 5275 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII)); k 5276 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII)); k 5277 drivers/net/ethernet/dec/tulip/de4x5.c if (lp->phy[k].id != BROADCOM_T4) { k 5278 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII)); k 5279 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII)); k 5281 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII)); k 5282 drivers/net/ethernet/dec/tulip/de4x5.c if (lp->phy[k].id != BROADCOM_T4) { k 5283 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII)); k 5284 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII)); k 5286 drivers/net/ethernet/dec/tulip/de4x5.c printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII)); k 496 drivers/net/ethernet/dnet.c int k; k 498 drivers/net/ethernet/dnet.c for (k = 0; k < skb->len; k++) k 499 drivers/net/ethernet/dnet.c printk(" %02x", (unsigned int)skb->data[k]); k 186 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c int j, k, err; k 223 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c for (k = 0; k < num_cnt; k++) k 224 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c *(data + i++) = dpni_stats.raw.counter[k]; k 228 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c for_each_online_cpu(k) { k 229 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c extras = per_cpu_ptr(priv->percpu_extras, k); k 236 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c for (k = 0; k < priv->num_channels; k++) { k 237 drivers/net/ethernet/freescale/dpaa2/dpaa2-ethtool.c ch_stats = &priv->channel[k]->stats; k 42 drivers/net/ethernet/freescale/fman/fman_sp.c int i = 0, j = 0, k = 0; k 68 drivers/net/ethernet/freescale/fman/fman_sp.c for (k = i; k > j; k--) k 69 drivers/net/ethernet/freescale/fman/fman_sp.c ordered_array[k] = k 70 drivers/net/ethernet/freescale/fman/fman_sp.c ordered_array[k - 1]; k 75 drivers/net/ethernet/freescale/fman/fman_sp.c ordered_array[k] = k 709 drivers/net/ethernet/freescale/gianfar_ethtool.c int i = 0x0, k = 0x0; k 789 drivers/net/ethernet/freescale/gianfar_ethtool.c for (k = j+1; k < MAX_FILER_IDX; k++) { k 790 drivers/net/ethernet/freescale/gianfar_ethtool.c priv->ftp_rqfpr[priv->cur_filer_idx] = local_rqfpr[k]; k 791 drivers/net/ethernet/freescale/gianfar_ethtool.c priv->ftp_rqfcr[priv->cur_filer_idx] = local_rqfcr[k]; k 793 drivers/net/ethernet/freescale/gianfar_ethtool.c local_rqfcr[k], local_rqfpr[k]); k 338 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c int k; k 345 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c for (k = 0; k < handle->q_num; k++) { k 347 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c hns_rcb_int_clr_hw(handle->qs[k], k 350 drivers/net/ethernet/hisilicon/hns/hns_ae_adapt.c hns_rcbv2_int_clr_hw(handle->qs[k], k 285 drivers/net/ethernet/hisilicon/hns/hns_enet.c int k; k 292 drivers/net/ethernet/hisilicon/hns/hns_enet.c for (k = 0; k < frag_buf_num; k++) k 293 drivers/net/ethernet/hisilicon/hns/hns_enet.c fill_v2_desc_hw(ring, priv, k == 0 ? size : 0, k 294 drivers/net/ethernet/hisilicon/hns/hns_enet.c (k == frag_buf_num - 1) ? k 296 drivers/net/ethernet/hisilicon/hns/hns_enet.c dma + BD_MAX_SEND_SIZE * k, k 297 drivers/net/ethernet/hisilicon/hns/hns_enet.c frag_end && (k == frag_buf_num - 1) ? 1 : 0, k 299 drivers/net/ethernet/hisilicon/hns/hns_enet.c (type == DESC_TYPE_SKB && !k) ? k 1115 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c int k, sizeoflast; k 1162 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c for (k = 0; k < frag_buf_num; k++) { k 1167 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k; k 1168 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c desc_cb->type = (type == DESC_TYPE_SKB && !k) ? k 1172 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); k 1173 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? k 1176 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c frag_end && (k == frag_buf_num - 1) ? k 421 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int i, k, n; k 443 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (k = 0; k < n; k++) { k 458 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c u16 i, k, n; k 485 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (k = 0; k < n; k++) { k 9657 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int i, k, n; k 9687 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (k = 0; k < n; k++) { k 9711 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c int i, k, n; k 9741 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c for (k = 0; k < n; k++) { k 703 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define calc_x(x, k, v) ((x) = (~(k) & (v))) k 704 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h #define calc_y(y, k, v) \ k 706 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h const typeof(k) _k_ = (k); \ k 621 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c int k; k 634 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->tm_info.num_tc; k++) k 635 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT; k 779 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c u32 i, k; k 783 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) { k 785 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c &vport[k].nic.kinfo; k 789 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c hdev, vport[k].qs_offset + i, i); k 796 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) k 799 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c hdev, vport[k].qs_offset + i, k); k 950 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c u32 i, k; k 961 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) { k 963 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c hdev, vport[k].qs_offset + i, k 964 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c vport[k].dwrr); k 1163 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c u8 i, k; k 1171 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) { k 1173 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c hdev, vport[k].qs_offset + i, k 1257 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c int k, ret; k 1259 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) { k 1260 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c struct hclge_vport *vport = &hdev->vport[k]; k 1363 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c u32 i, k; k 1368 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c for (k = 0; k < hdev->num_alloc_vport; k++) { k 1369 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c kinfo = &vport[k].nic.kinfo; k 226 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c int i, k, tmp; k 237 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++) k 238 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c tmp += port->port_res[k].p_stats.poll_receive_errors; k 241 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++) k 242 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c tmp += port->port_res[k].p_stats.err_tcp_cksum; k 245 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++) k 246 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c tmp += port->port_res[k].p_stats.err_ip_cksum; k 249 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++) k 250 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c tmp += port->port_res[k].p_stats.err_frame_crc; k 253 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0, tmp = 0; k < EHEA_MAX_PORT_RES; k++) k 254 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c tmp += port->port_res[k].p_stats.queue_stopped; k 257 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c for (k = 0; k < 16; k++) k 258 drivers/net/ethernet/ibm/ehea/ehea_ethtool.c data[i++] = atomic_read(&port->port_res[k].swqe_avail); k 148 drivers/net/ethernet/ibm/ehea/ehea_main.c int num_fw_handles, k, l; k 156 drivers/net/ethernet/ibm/ehea/ehea_main.c for (k = 0; k < EHEA_MAX_PORTS; k++) { k 157 drivers/net/ethernet/ibm/ehea/ehea_main.c struct ehea_port *port = adapter->port[k]; k 182 drivers/net/ethernet/ibm/ehea/ehea_main.c for (k = 0; k < EHEA_MAX_PORTS; k++) { k 183 drivers/net/ethernet/ibm/ehea/ehea_main.c struct ehea_port *port = adapter->port[k]; k 236 drivers/net/ethernet/ibm/ehea/ehea_main.c int k; k 242 drivers/net/ethernet/ibm/ehea/ehea_main.c for (k = 0; k < EHEA_MAX_PORTS; k++) { k 243 drivers/net/ethernet/ibm/ehea/ehea_main.c struct ehea_port *port = adapter->port[k]; k 262 drivers/net/ethernet/ibm/ehea/ehea_main.c for (k = 0; k < EHEA_MAX_PORTS; k++) { k 263 drivers/net/ethernet/ibm/ehea/ehea_main.c struct ehea_port *port = adapter->port[k]; k 44 drivers/net/ethernet/ibm/ehea/ehea_qmr.c int i, k; k 68 drivers/net/ethernet/ibm/ehea/ehea_qmr.c for (k = 0; k < pages_per_kpage && i < nr_of_pages; k++) { k 799 drivers/net/ethernet/ibm/ehea/ehea_qmr.c unsigned long k = 0; k 807 drivers/net/ethernet/ibm/ehea/ehea_qmr.c pg = sectbase + ((k++) * EHEA_PAGESIZE); k 1384 drivers/net/ethernet/intel/e1000/e1000_ethtool.c int i, j, k, l, lc, good_cnt, ret_val = 0; k 1399 drivers/net/ethernet/intel/e1000/e1000_ethtool.c k = l = 0; k 1405 drivers/net/ethernet/intel/e1000/e1000_ethtool.c txdr->buffer_info[k].dma, k 1406 drivers/net/ethernet/intel/e1000/e1000_ethtool.c txdr->buffer_info[k].length, k 1408 drivers/net/ethernet/intel/e1000/e1000_ethtool.c if (unlikely(++k == txdr->count)) k 1409 drivers/net/ethernet/intel/e1000/e1000_ethtool.c k = 0; k 1411 drivers/net/ethernet/intel/e1000/e1000_ethtool.c ew32(TDT, k); k 1632 drivers/net/ethernet/intel/e1000e/ethtool.c int i, j, k, l; k 1650 drivers/net/ethernet/intel/e1000e/ethtool.c k = 0; k 1656 drivers/net/ethernet/intel/e1000e/ethtool.c buffer_info = &tx_ring->buffer_info[k]; k 1663 drivers/net/ethernet/intel/e1000e/ethtool.c k++; k 1664 drivers/net/ethernet/intel/e1000e/ethtool.c if (k == tx_ring->count) k 1665 drivers/net/ethernet/intel/e1000e/ethtool.c k = 0; k 1667 drivers/net/ethernet/intel/e1000e/ethtool.c ew32(TDT(0), k); k 231 drivers/net/ethernet/intel/igb/e1000_i210.c u32 i, k, eewr = 0; k 252 drivers/net/ethernet/intel/igb/e1000_i210.c for (k = 0; k < attempts; k++) { k 223 drivers/net/ethernet/intel/igc/igc_i225.c u32 i, k, eewr = 0; k 243 drivers/net/ethernet/intel/igc/igc_i225.c for (k = 0; k < attempts; k++) { k 919 drivers/net/ethernet/mediatek/mtk_eth_soc.c int k = 0; k 954 drivers/net/ethernet/mediatek/mtk_eth_soc.c k++); k 1010 drivers/net/ethernet/mediatek/mtk_eth_soc.c frag_map_size, k++); k 1024 drivers/net/ethernet/mediatek/mtk_eth_soc.c if (k & 0x1) k 555 drivers/net/ethernet/mellanox/mlx4/qp.c int k; k 616 drivers/net/ethernet/mellanox/mlx4/qp.c for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]); k 617 drivers/net/ethernet/mellanox/mlx4/qp.c k++) { k 690 drivers/net/ethernet/mellanox/mlx4/qp.c err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size), k 697 drivers/net/ethernet/mellanox/mlx4/qp.c err = mlx4_bitmap_init(*bitmap + k, 1, k 700 drivers/net/ethernet/mellanox/mlx4/qp.c mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0); k 708 drivers/net/ethernet/mellanox/mlx4/qp.c err = mlx4_zone_add_one(qp_table->zones, *bitmap + k, k 712 drivers/net/ethernet/mellanox/mlx4/qp.c offset, qp_table->zones_uids + k); k 726 drivers/net/ethernet/mellanox/mlx4/qp.c for (k = 0; k < bitmap_initialized; k++) k 727 drivers/net/ethernet/mellanox/mlx4/qp.c mlx4_bitmap_cleanup(*bitmap + k); k 767 drivers/net/ethernet/mellanox/mlx4/qp.c int k; k 785 drivers/net/ethernet/mellanox/mlx4/qp.c for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++) k 786 drivers/net/ethernet/mellanox/mlx4/qp.c fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k]; k 859 drivers/net/ethernet/mellanox/mlx4/qp.c for (k = 0; k < dev->caps.num_ports; k++) { k 860 drivers/net/ethernet/mellanox/mlx4/qp.c dev->caps.spec_qps[k].qp0_proxy = dev->phys_caps.base_proxy_sqpn + k 861 drivers/net/ethernet/mellanox/mlx4/qp.c 8 * mlx4_master_func_num(dev) + k; k 862 drivers/net/ethernet/mellanox/mlx4/qp.c dev->caps.spec_qps[k].qp0_tunnel = dev->caps.spec_qps[k].qp0_proxy + 8 * MLX4_MFUNC_MAX; k 863 drivers/net/ethernet/mellanox/mlx4/qp.c dev->caps.spec_qps[k].qp1_proxy = dev->phys_caps.base_proxy_sqpn + k 864 drivers/net/ethernet/mellanox/mlx4/qp.c 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k; k 865 drivers/net/ethernet/mellanox/mlx4/qp.c dev->caps.spec_qps[k].qp1_tunnel = dev->caps.spec_qps[k].qp1_proxy + 8 * MLX4_MFUNC_MAX; k 1852 drivers/net/ethernet/mellanox/mlx5/core/cmd.c int k; k 1855 drivers/net/ethernet/mellanox/mlx5/core/cmd.c for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) { k 1856 drivers/net/ethernet/mellanox/mlx5/core/cmd.c ch = &cmd->cache[k]; k 1859 drivers/net/ethernet/mellanox/mlx5/core/cmd.c ch->num_ent = cmd_cache_num_ent[k]; k 1860 drivers/net/ethernet/mellanox/mlx5/core/cmd.c ch->max_inbox_size = cmd_cache_ent_size[k]; k 665 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c int i, k, ret; k 675 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c for (i = num_of_builders, k = 0; i < new_hw_ste_arr_sz; i++, k++) { k 690 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c ste_info_arr[k] = kzalloc(sizeof(*ste_info_arr[k]), k 692 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c if (!ste_info_arr[k]) k 704 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c ste_info_arr[k], k 711 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c kfree(ste_info_arr[k]); k 1254 drivers/net/ethernet/microchip/enc28j60.c int test_len, k; k 1265 drivers/net/ethernet/microchip/enc28j60.c for (k = 0; k < test_len; k++) { k 1266 drivers/net/ethernet/microchip/enc28j60.c if (priv->tx_skb->data[k] != test_buf[k]) { k 1269 drivers/net/ethernet/microchip/enc28j60.c k, priv->tx_skb->data[k], test_buf[k]); k 640 drivers/net/ethernet/neterion/s2io.c int k = 0; k 670 drivers/net/ethernet/neterion/s2io.c while (k < lst_per_page) { k 671 drivers/net/ethernet/neterion/s2io.c int l = (j * lst_per_page) + k; k 675 drivers/net/ethernet/neterion/s2io.c tmp_v + (k * lst_size); k 677 drivers/net/ethernet/neterion/s2io.c tmp_p + (k * lst_size); k 678 drivers/net/ethernet/neterion/s2io.c k++; k 800 drivers/net/ethernet/neterion/s2io.c int k = 0; k 808 drivers/net/ethernet/neterion/s2io.c while (k != rxd_count[nic->rxd_mode]) { k 809 drivers/net/ethernet/neterion/s2io.c ba = &ring->ba[j][k]; k 829 drivers/net/ethernet/neterion/s2io.c k++; k 960 drivers/net/ethernet/neterion/s2io.c int k = 0; k 963 drivers/net/ethernet/neterion/s2io.c while (k != rxd_count[nic->rxd_mode]) { k 964 drivers/net/ethernet/neterion/s2io.c struct buffAdd *ba = &ring->ba[j][k]; k 971 drivers/net/ethernet/neterion/s2io.c k++; k 6231 drivers/net/ethernet/neterion/s2io.c int i = 0, k; k 6428 drivers/net/ethernet/neterion/s2io.c for (k = 0; k < MAX_RX_RINGS; k++) k 6429 drivers/net/ethernet/neterion/s2io.c tmp_stats[i++] = swstats->ring_full_cnt[k]; k 6860 drivers/net/ethernet/neterion/s2io.c int i, j, k, blk_cnt = 0, size; k 6884 drivers/net/ethernet/neterion/s2io.c for (k = 0; k < rxd_count[sp->rxd_mode]; k++) { k 6885 drivers/net/ethernet/neterion/s2io.c rxdp = ring->rx_blocks[j].rxds[k].virt_addr; k 6887 drivers/net/ethernet/neterion/s2io.c ba = &ring->ba[j][k]; k 232 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c int j, k; k 298 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->no_of_vpath; k++) { k 301 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c vpath = &vdev->vpaths[k]; k 375 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->max_config_port; k++) { k 376 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_frms; k 377 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_data_octets; k 378 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_mcast_frms; k 379 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_bcast_frms; k 380 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_discarded_frms; k 381 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].tx_errored_frms; k 382 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_frms; k 383 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_data_octets; k 384 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_mcast_frms; k 385 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_bcast_frms; k 386 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_discarded_frms; k 387 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_errored_frms; k 388 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->aggr_stats[k].rx_unknown_slow_proto_frms; k 391 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->max_config_port; k++) { k 392 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_ttl_frms; k 393 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_ttl_octets; k 394 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_data_octets; k 395 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_mcast_frms; k 396 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_bcast_frms; k 397 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_ucast_frms; k 398 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_tagged_frms; k 399 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_vld_ip; k 400 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_vld_ip_octets; k 401 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_icmp; k 402 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_tcp; k 403 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_rst_tcp; k 404 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_udp; k 405 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_parse_error; k 406 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_unknown_protocol; k 407 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_pause_ctrl_frms; k 408 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_marker_pdu_frms; k 409 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_lacpdu_frms; k 410 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_drop_ip; k 411 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_marker_resp_pdu_frms; k 412 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_xgmii_char2_match; k 413 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_xgmii_char1_match; k 414 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_xgmii_column2_match; k 415 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_xgmii_column1_match; k 416 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_any_err_frms; k 417 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].tx_drop_frms; k 418 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_frms; k 419 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_vld_frms; k 420 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_offload_frms; k 421 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_octets; k 422 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_data_octets; k 423 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_offload_octets; k 424 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_vld_mcast_frms; k 425 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_vld_bcast_frms; k 426 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_accepted_ucast_frms; k 427 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_accepted_nucast_frms; k 428 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_tagged_frms; k 429 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_long_frms; k 430 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_usized_frms; k 431 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_osized_frms; k 432 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_frag_frms; k 433 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_jabber_frms; k 434 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_64_frms; k 435 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_65_127_frms; k 436 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_128_255_frms; k 437 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_256_511_frms; k 438 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_512_1023_frms; k 439 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_1024_1518_frms; k 440 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_1519_4095_frms; k 441 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_4096_8191_frms; k 442 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_8192_max_frms; k 443 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ttl_gt_max_frms; k 444 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ip; k 445 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_accepted_ip; k 446 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_ip_octets; k 447 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_err_ip; k 448 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_icmp; k 449 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_tcp; k 450 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_udp; k 451 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_err_tcp; k 452 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_pause_count; k 453 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_pause_ctrl_frms; k 454 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_unsup_ctrl_frms; k 455 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_fcs_err_frms; k 456 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_in_rng_len_err_frms; k 457 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_out_rng_len_err_frms; k 458 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_drop_frms; k 459 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_discarded_frms; k 460 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_drop_ip; k 461 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_drop_udp; k 462 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_marker_pdu_frms; k 463 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_lacpdu_frms; k 464 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_unknown_pdu_frms; k 465 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_marker_resp_pdu_frms; k 466 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_fcs_discard; k 467 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_illegal_pdu_frms; k 468 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_switch_discard; k 469 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_len_discard; k 470 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_rpa_discard; k 471 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_l2_mgmt_discard; k 472 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_rts_discard; k 473 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_trash_discard; k 474 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_buff_full_discard; k 475 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_red_discard; k 476 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_ctrl_err_cnt; k 477 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_data_err_cnt; k 478 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_char1_match; k 479 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_err_sym; k 480 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_column1_match; k 481 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_char2_match; k 482 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_local_fault; k 483 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_xgmii_column2_match; k 484 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_jettison; k 485 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr++ = xmac_stats->port_stats[k].rx_remote_fault; k 489 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->no_of_vpath; k++) { k 492 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c vpath = &vdev->vpaths[k]; k 533 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->no_of_vpath; k++) { k 535 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c vpath = &vdev->vpaths[k]; k 578 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c for (k = 0; k < vdev->no_of_vpath; k++) { k 579 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *ptr += vdev->vpaths[k].fifo.stats.tx_frms; k 580 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 1) += vdev->vpaths[k].fifo.stats.tx_errors; k 581 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 2) += vdev->vpaths[k].fifo.stats.tx_bytes; k 582 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 3) += vdev->vpaths[k].fifo.stats.txd_not_free; k 583 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 4) += vdev->vpaths[k].fifo.stats.txd_out_of_desc; k 584 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 5) += vdev->vpaths[k].ring.stats.rx_frms; k 585 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 6) += vdev->vpaths[k].ring.stats.rx_errors; k 586 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 7) += vdev->vpaths[k].ring.stats.rx_bytes; k 587 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 8) += vdev->vpaths[k].ring.stats.rx_mcast; k 588 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 9) += vdev->vpaths[k].fifo.stats.pci_map_fail + k 589 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c vdev->vpaths[k].ring.stats.pci_map_fail; k 590 drivers/net/ethernet/neterion/vxge/vxge-ethtool.c *(ptr + 10) += vdev->vpaths[k].ring.stats.skb_alloc_fail; k 3105 drivers/net/ethernet/neterion/vxge/vxge-main.c int k; k 3108 drivers/net/ethernet/neterion/vxge/vxge-main.c for (k = 0; k < vdev->no_of_vpath; k++) { k 3109 drivers/net/ethernet/neterion/vxge/vxge-main.c struct vxge_ring_stats *rxstats = &vdev->vpaths[k].ring.stats; k 3110 drivers/net/ethernet/neterion/vxge/vxge-main.c struct vxge_fifo_stats *txstats = &vdev->vpaths[k].fifo.stats; k 24 drivers/net/ethernet/netronome/nfp/abm/cls.c struct tc_u32_key *k; k 79 drivers/net/ethernet/netronome/nfp/abm/cls.c k = &knode->sel->keys[0]; k 80 drivers/net/ethernet/netronome/nfp/abm/cls.c if (k->offmask) { k 84 drivers/net/ethernet/netronome/nfp/abm/cls.c if (k->off) { k 88 drivers/net/ethernet/netronome/nfp/abm/cls.c if (k->val & ~k->mask) { k 92 drivers/net/ethernet/netronome/nfp/abm/cls.c if (be32_to_cpu(k->mask) >> tos_off & ~abm->dscp_mask) { k 96 drivers/net/ethernet/netronome/nfp/abm/cls.c be32_to_cpu(k->mask) >> tos_off, abm->dscp_mask); k 771 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c int k; k 779 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c k = nfp_cpp_area_write(area, offset + i, &tmp, sizeof(tmp)); k 780 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c if (k < 0) k 781 drivers/net/ethernet/netronome/nfp/nfpcore/nfp_cppcore.c return k; k 1503 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c int j, k; k 1512 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c k = i; k 1515 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c tx_desc = PCH_GBE_TX_DESC(*tx_ring, k); k 1517 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c if (++k >= tx_ring->count) k = 0; /*increment, wrap*/ k 1522 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c unused, j, i, k, tx_ring->next_to_use, k 1524 drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c i = k; /*found one to clean, usu gbec_status==2000.*/ k 2149 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c int loop_cnt, i, k, timeout_flag = 0; k 2188 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c for (k = 0; k < read_cnt; k++) { k 2205 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c int i, k, loop_cnt; k 2223 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c for (k = 0; k < read_cnt; k++) { k 2283 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c int loop_cnt, k; k 2294 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c for (k = 0; k < read_cnt; k++) { k 2501 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c int i, k, data_size = 0; k 2507 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) { k 2509 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c data_size += hdr->capture_size_array[k]; k 2044 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c int i, k; k 2098 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c k = i % 4; k 2100 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c if ((k == 0) && (i > 0)) { k 2110 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length); k 2111 drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c switch (k) { k 1082 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 size, i, j, k; k 1104 drivers/net/ethernet/qlogic/qed/qed_cxt.c for (k = 0; k < p_mngr->vf_count; k++) { k 1106 drivers/net/ethernet/qlogic/qed/qed_cxt.c u32 lines = clients[i].vf_total_lines * k; k 996 drivers/net/ethernet/qlogic/qed/qed_int.c u8 i, j, k, bit_idx; k 1035 drivers/net/ethernet/qlogic/qed/qed_int.c for (k = 0; k < MAX_ATTN_GRPS; k++) { k 1039 drivers/net/ethernet/qlogic/qed/qed_int.c if (!(deasserted_bits & (1 << k))) k 1047 drivers/net/ethernet/qlogic/qed/qed_int.c k * sizeof(u32) * NUM_ATTN_REGS; k 1347 drivers/net/ethernet/qlogic/qed/qed_int.c int i, j, k; k 1359 drivers/net/ethernet/qlogic/qed/qed_int.c for (j = 0, k = 0; k < 32; j++) { k 1364 drivers/net/ethernet/qlogic/qed/qed_int.c sb_info->parity_mask[i] |= 1 << k; k 1366 drivers/net/ethernet/qlogic/qed/qed_int.c k += ATTENTION_LENGTH(p_aeu->flags); k 4476 drivers/net/ethernet/qlogic/qed/qed_sriov.c int k; k 4482 drivers/net/ethernet/qlogic/qed/qed_sriov.c for (k = 0; k < 100; k++) { k 4489 drivers/net/ethernet/qlogic/qed/qed_sriov.c if (k < 100) k 3471 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c int err, k, total_regs; k 3485 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k = 2; k < 28; k += 2) k 3486 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3489 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k += 6; k < 60; k += 2) k 3490 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3493 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k += 6; k < 80; k += 2) k 3494 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3496 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (; k < total_regs; k += 2) k 3497 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3500 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k = 2; k < 8; k += 2) k 3501 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3503 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k += 2; k < 24; k += 2) k 3504 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3506 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k += 2; k < total_regs; k += 2) k 3507 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3510 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k = 2; k < 10; k += 2) k 3511 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 3513 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c for (k += 2; k < total_regs; k += 2) k 3514 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c data = qlcnic_83xx_copy_stats(cmd, data, k); k 570 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c int err, i, j, k, max_app, size; k 594 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c k = 2; k 600 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->hdr_prio_pfc_map[0] = cmd.rsp.arg[k++]; k 601 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->hdr_prio_pfc_map[1] = cmd.rsp.arg[k++]; k 602 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->prio_pg_map[0] = cmd.rsp.arg[k++]; k 603 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->prio_pg_map[1] = cmd.rsp.arg[k++]; k 604 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->pg_bw_map[0] = cmd.rsp.arg[k++]; k 605 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->pg_bw_map[1] = cmd.rsp.arg[k++]; k 606 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->pg_tsa_map[0] = cmd.rsp.arg[k++]; k 607 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->pg_tsa_map[1] = cmd.rsp.arg[k++]; k 612 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c each->app[i] = cmd.rsp.arg[i + k]; k 618 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c k = 18; k 620 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c k = 34; k 1070 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c u8 i, j, k, map; k 1083 drivers/net/ethernet/qlogic/qlcnic/qlcnic_dcb.c for (k = 0; k < QLC_DCB_MAX_TC; k++) { k 658 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c int i, k, frag_count, delta = 0; k 721 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c k = i % 4; k 723 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c if ((k == 0) && (i > 0)) { k 732 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c hwdesc->buffer_length[k] = cpu_to_le16(buffrag->length); k 733 drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c switch (k) { k 408 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c int i, k, timeout = 0; k 416 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c k = 0; k 417 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c for (k = 0; k < 8; k++) { k 418 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c if (!(ctr->opcode & (1 << k))) k 420 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c switch (1 << k) { k 1292 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c int i, k, ops_cnt, ops_index, dump_size = 0; k 1322 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++) k 1324 drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c dump_size += qlcnic_get_cap_size(adapter, tmpl_hdr, k); k 945 drivers/net/ethernet/sfc/siena_sriov.c unsigned int pos, count, k, buftbl, abs_evq; k 968 drivers/net/ethernet/sfc/siena_sriov.c for (k = 0; k < count; k++) { k 969 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].from_buf = NULL; k 970 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].from_rid = efx->pci_dev->devfn; k 971 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].from_addr = buffer->dma_addr; k 972 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].to_rid = vf->pci_rid; k 973 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].to_addr = vf->evq0_addrs[pos + k]; k 974 drivers/net/ethernet/sfc/siena_sriov.c copy_req[k].length = EFX_PAGE_SIZE; k 402 drivers/net/ethernet/smsc/smc91c92_cs.c int k; k 411 drivers/net/ethernet/smsc/smc91c92_cs.c for (k = 0; k < 0x400; k += 0x10) { k 412 drivers/net/ethernet/smsc/smc91c92_cs.c if (k & 0x80) k 414 drivers/net/ethernet/smsc/smc91c92_cs.c p_dev->resource[0]->start = k ^ 0x300; k 6434 drivers/net/ethernet/sun/niu.c int i, j, k, err; k 6440 drivers/net/ethernet/sun/niu.c for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { k 6449 drivers/net/ethernet/sun/niu.c rp->rbr[k++] = cpu_to_le32(base); k 6453 drivers/net/ethernet/sun/niu.c for (; k < MAX_RBR_RING_SIZE; k++) { k 6454 drivers/net/ethernet/sun/niu.c err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); k 55 drivers/net/fddi/skfp/fplustm.c #define CHECK_NPP() { unsigned int k = 10000 ;\ k 56 drivers/net/fddi/skfp/fplustm.c while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\ k 57 drivers/net/fddi/skfp/fplustm.c if (!k) { \ k 62 drivers/net/fddi/skfp/fplustm.c #define CHECK_CAM() { unsigned int k = 10 ;\ k 63 drivers/net/fddi/skfp/fplustm.c while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\ k 64 drivers/net/fddi/skfp/fplustm.c if (!k) { \ k 343 drivers/net/hamradio/scc.c int k; k 345 drivers/net/hamradio/scc.c for (k=0; k<3; k++) k 636 drivers/net/hamradio/scc.c int k; k 640 drivers/net/hamradio/scc.c for(k=0; k < SCC_IRQTIMEOUT; k++) k 656 drivers/net/hamradio/scc.c if (k == SCC_IRQTIMEOUT) k 676 drivers/net/hamradio/scc.c for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++) k 687 drivers/net/hamradio/scc.c if (k == SCC_IRQTIMEOUT) k 1092 drivers/net/hamradio/scc.c int k; k 1098 drivers/net/hamradio/scc.c for (k = 0; k < (Nchips * 2); k++) k 1100 drivers/net/hamradio/scc.c scc2 = &SCC_Info[k]; k 1462 drivers/net/hamradio/scc.c int chip, k; k 1470 drivers/net/hamradio/scc.c for (k = 0; k < nr_irqs; k++) k 1471 drivers/net/hamradio/scc.c if (Ivec[k].used) k 1473 drivers/net/hamradio/scc.c printk("%s%d", flag, k); k 1977 drivers/net/hamradio/scc.c int k; k 1979 drivers/net/hamradio/scc.c for (k = 0; k < Nchips*2; ++k) { k 1980 drivers/net/hamradio/scc.c if (!SCC_Info[k].init) k 1983 drivers/net/hamradio/scc.c return &SCC_Info[k]; k 1996 drivers/net/hamradio/scc.c unsigned k; k 2000 drivers/net/hamradio/scc.c for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1; k 2001 drivers/net/hamradio/scc.c k < Nchips*2; ++k) { k 2002 drivers/net/hamradio/scc.c if (SCC_Info[k].init) k 2003 drivers/net/hamradio/scc.c return &SCC_Info[k]; k 2118 drivers/net/hamradio/scc.c int k; k 2131 drivers/net/hamradio/scc.c for (k = 0; k < Nchips; k++) k 2132 drivers/net/hamradio/scc.c if ( (ctrl = SCC_ctrl[k].chan_A) ) k 2140 drivers/net/hamradio/scc.c for (k = 0; k < nr_irqs ; k++) k 2141 drivers/net/hamradio/scc.c if (Ivec[k].used) free_irq(k, NULL); k 2146 drivers/net/hamradio/scc.c for (k = 0; k < Nchips*2; k++) k 2148 drivers/net/hamradio/scc.c scc = &SCC_Info[k]; k 316 drivers/net/hamradio/yam.c int k; k 319 drivers/net/hamradio/yam.c for (k = 0; k < 8; k++) { k 2500 drivers/net/macsec.c int k; k 2539 drivers/net/macsec.c for (i = 0, k = 1; i < MACSEC_NUM_AN; i++) { k 2546 drivers/net/macsec.c rxsa_nest = nla_nest_start_noflag(skb, k++); k 710 drivers/net/sb1000.c int i, j, k; k 721 drivers/net/sb1000.c for (i = 0, k = 0; i < (size + 7) / 8; i++) { k 723 drivers/net/sb1000.c for (j = 0; j < 8 && k < size; j++, k++) k 724 drivers/net/sb1000.c printk(" %02x", buffer[k]); k 543 drivers/net/wireless/ath/ath10k/debugfs_sta.c int k = 0; \ k 549 drivers/net/wireless/ath/ath10k/debugfs_sta.c k++; \ k 550 drivers/net/wireless/ath/ath10k/debugfs_sta.c if (k % 8 == 0) { \ k 656 drivers/net/wireless/ath/ath10k/debugfs_sta.c int len = 0, i, j, k, retval = 0; k 674 drivers/net/wireless/ath/ath10k/debugfs_sta.c for (k = 0; k < ATH10K_STATS_TYPE_MAX; k++) { k 676 drivers/net/wireless/ath/ath10k/debugfs_sta.c stats = &arsta->tx_stats->stats[k]; k 678 drivers/net/wireless/ath/ath10k/debugfs_sta.c str_name[k], k 443 drivers/net/wireless/ath/ath9k/calib.c int i, j, k = 0; k 450 drivers/net/wireless/ath/ath9k/calib.c h[i].privNF = ath9k_hw_get_default_nf(ah, chan, k); k 454 drivers/net/wireless/ath/ath9k/calib.c if (++k >= AR5416_MAX_CHAINS) k 455 drivers/net/wireless/ath/ath9k/calib.c k = 0; k 246 drivers/net/wireless/ath/ath9k/eeprom.c u16 i, k; k 259 drivers/net/wireless/ath/ath9k/eeprom.c k = pVpdList[idxL]; k 261 drivers/net/wireless/ath/ath9k/eeprom.c k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + k 264 drivers/net/wireless/ath/ath9k/eeprom.c pRetVpdList[i] = (u8) k; k 462 drivers/net/wireless/ath/ath9k/eeprom.c int i, j, k; k 585 drivers/net/wireless/ath/ath9k/eeprom.c k = 0; k 613 drivers/net/wireless/ath/ath9k/eeprom.c while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { k 615 drivers/net/wireless/ath/ath9k/eeprom.c pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); k 625 drivers/net/wireless/ath/ath9k/eeprom.c while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { k 626 drivers/net/wireless/ath/ath9k/eeprom.c pPDADCValues[k++] = vpdTableI[i][ss++]; k 635 drivers/net/wireless/ath/ath9k/eeprom.c (k < (AR5416_NUM_PDADC_VALUES - 1))) { k 638 drivers/net/wireless/ath/ath9k/eeprom.c pPDADCValues[k++] = (u8)((tmpVal > 255) ? k 655 drivers/net/wireless/ath/ath9k/eeprom.c while (k < AR5416_NUM_PDADC_VALUES) { k 656 drivers/net/wireless/ath/ath9k/eeprom.c pPDADCValues[k] = pPDADCValues[k - 1]; k 657 drivers/net/wireless/ath/ath9k/eeprom.c k++; k 699 drivers/net/wireless/ath/ath9k/eeprom_def.c u16 k; k 717 drivers/net/wireless/ath/ath9k/eeprom_def.c for (k = 0; k < numXpdGain; k++) k 718 drivers/net/wireless/ath/ath9k/eeprom_def.c gb[k] = (u16)(gb[k] - *diff); k 725 drivers/net/wireless/ath/ath9k/eeprom_def.c for (k = 0; k < numXpdGain; k++) k 726 drivers/net/wireless/ath/ath9k/eeprom_def.c gb[k] = (u16)min(gb_limit, gb[k]); k 738 drivers/net/wireless/ath/ath9k/eeprom_def.c u16 k; k 748 drivers/net/wireless/ath/ath9k/eeprom_def.c for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) { k 749 drivers/net/wireless/ath/ath9k/eeprom_def.c pdadcValues[k] = pdadcValues[k + diff]; k 753 drivers/net/wireless/ath/ath9k/eeprom_def.c for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) { k 754 drivers/net/wireless/ath/ath9k/eeprom_def.c pdadcValues[k] = pdadcValues[NUM_PDADC(diff)]; k 1395 drivers/net/wireless/ath/carl9170/phy.c int k = i; k 1398 drivers/net/wireless/ath/carl9170/phy.c while (k-- > 0) { k 1399 drivers/net/wireless/ath/carl9170/phy.c if (modes[k].max_power != k 1401 drivers/net/wireless/ath/carl9170/phy.c modes[i].max_power = modes[k].max_power; k 130 drivers/net/wireless/ath/key.c const struct ath_keyval *k, k 143 drivers/net/wireless/ath/key.c switch (k->kv_type) { k 164 drivers/net/wireless/ath/key.c if (k->kv_len < WLAN_KEY_LEN_WEP40) { k 166 drivers/net/wireless/ath/key.c k->kv_len); k 169 drivers/net/wireless/ath/key.c if (k->kv_len <= WLAN_KEY_LEN_WEP40) k 171 drivers/net/wireless/ath/key.c else if (k->kv_len <= WLAN_KEY_LEN_WEP104) k 180 drivers/net/wireless/ath/key.c ath_err(common, "cipher %u not supported\n", k->kv_type); k 184 drivers/net/wireless/ath/key.c key0 = get_unaligned_le32(k->kv_val + 0); k 185 drivers/net/wireless/ath/key.c key1 = get_unaligned_le16(k->kv_val + 4); k 186 drivers/net/wireless/ath/key.c key2 = get_unaligned_le32(k->kv_val + 6); k 187 drivers/net/wireless/ath/key.c key3 = get_unaligned_le16(k->kv_val + 10); k 188 drivers/net/wireless/ath/key.c key4 = get_unaligned_le32(k->kv_val + 12); k 189 drivers/net/wireless/ath/key.c if (k->kv_len <= WLAN_KEY_LEN_WEP104) k 237 drivers/net/wireless/ath/key.c mic0 = get_unaligned_le32(k->kv_mic + 0); k 238 drivers/net/wireless/ath/key.c mic2 = get_unaligned_le32(k->kv_mic + 4); k 239 drivers/net/wireless/ath/key.c mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; k 240 drivers/net/wireless/ath/key.c mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; k 241 drivers/net/wireless/ath/key.c mic4 = get_unaligned_le32(k->kv_txmic + 4); k 279 drivers/net/wireless/ath/key.c mic0 = get_unaligned_le32(k->kv_mic + 0); k 280 drivers/net/wireless/ath/key.c mic2 = get_unaligned_le32(k->kv_mic + 4); k 501 drivers/net/wireless/ath/wil6210/fw_inc.c int n, i, k; k 524 drivers/net/wireless/ath/wil6210/fw_inc.c for (k = 0; k < ARRAY_SIZE(block->value); k++) k 525 drivers/net/wireless/ath/wil6210/fw_inc.c if (!wil_fw_addr_check(wil, &gwa_val[k], k 526 drivers/net/wireless/ath/wil6210/fw_inc.c d->gateway_value_addr[k], k 548 drivers/net/wireless/ath/wil6210/fw_inc.c for (k = 0; k < ARRAY_SIZE(block->value); k++) k 549 drivers/net/wireless/ath/wil6210/fw_inc.c v[k] = le32_to_cpu(block[i].value[k]); k 555 drivers/net/wireless/ath/wil6210/fw_inc.c for (k = 0; k < ARRAY_SIZE(block->value); k++) k 556 drivers/net/wireless/ath/wil6210/fw_inc.c writel(v[k], gwa_val[k]); k 2401 drivers/net/wireless/atmel/atmel.c int k, i, j; k 2414 drivers/net/wireless/atmel/atmel.c for (k = 0, i = channel_table[j].min; i <= channel_table[j].max; i++) { k 2415 drivers/net/wireless/atmel/atmel.c range->freq[k].i = i; /* List index */ k 2418 drivers/net/wireless/atmel/atmel.c range->freq[k].m = 100000 * k 2420 drivers/net/wireless/atmel/atmel.c range->freq[k++].e = 1; k 2422 drivers/net/wireless/atmel/atmel.c range->num_frequency = k; k 6239 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c int k; k 6301 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c for (k = 0; k < hw->max_rates; k++) { k 6302 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false; k 6304 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((txrate[k]->idx >= 0) k 6305 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c && (txrate[k]->idx < k 6307 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] = k 6309 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c bitrates[txrate[k]->idx].hw_value; k 6310 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c short_preamble[k] = k 6311 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c txrate[k]-> k 6315 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] = BRCM_RATE_1M; k 6318 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, k 6319 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c NRATE_MCS_INUSE | txrate[k]->idx); k 6328 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c txrate[k]-> k 6331 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c txrate[k]-> k 6340 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (!rspec_active(rspec[k])) { k 6341 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] = BRCM_RATE_1M; k 6354 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c for (k = 0; k < hw->max_rates; k++) { k 6359 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (((is_mcs_rate(rspec[k]) && k 6360 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c is_single_stream(rspec[k] & RSPEC_RATE_MASK)) || k 6361 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c is_ofdm_rate(rspec[k])) k 6362 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY) k 6363 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c || !(rspec[k] & RSPEC_OVERRIDE))) { k 6364 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK); k 6367 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (is_mcs_rate(rspec[k]) k 6373 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= (PHY_TXC1_MODE_STBC << k 6377 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= k 6392 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (is_mcs_rate(rspec[k])) { k 6394 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((rspec[k] & RSPEC_RATE_MASK) k 6404 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c } else if (is_ofdm_rate(rspec[k])) { k 6416 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((rspec[k] & RSPEC_RATE_MASK) == 32) k 6418 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] = RSPEC_MIMORATE; k 6424 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] &= ~RSPEC_BW_MASK; k 6425 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k]))) k 6426 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT); k 6428 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT); k 6431 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] &= ~RSPEC_SHORT_GI; k 6434 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD) k 6437 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((txrate[k]->flags & IEEE80211_TX_RC_MCS) k 6438 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c && (!is_mcs_rate(rspec[k]))) { k 6444 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (is_mcs_rate(rspec[k])) { k 6445 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c preamble_type[k] = mimo_preamble_type; k 6451 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if ((rspec[k] & RSPEC_SHORT_GI) k 6452 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c && is_single_stream(rspec[k] & k 6454 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c preamble_type[k] = BRCMS_MM_PREAMBLE; k 6461 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c preamble_type[k] = BRCMS_SHORT_PREAMBLE; k 6464 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c for (k = 0; k < hw->max_rates; k++) { k 6466 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] &= ~RSPEC_BW_MASK; k 6467 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT); k 6470 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) { k 6471 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] &= ~RSPEC_STF_MASK; k 6472 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT; k 6596 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c for (k = 0; k < 2; k++) { k 6597 drivers/net/wireless/broadcom/brcm80211/brcmsmac/main.c rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], k 1651 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c int rate_start_index = 0, rate1, rate2, k; k 1663 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c for (k = 0; k < 4; k++) { k 1664 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c switch (k) { k 1709 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c for (k = 0; k < 4; k++) { k 1710 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c switch (k) { k 1754 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c for (k = 0; k < 2; k++) { k 1755 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c switch (k) { k 1773 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c for (k = 0; k < 2; k++) { k 1774 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c switch (k) { k 2645 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c uint k; k 2657 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++) k 2658 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_cmn.c pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY; k 1032 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c int k; k 1033 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = 0; k 1036 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = (coeff_x - 1) / 2; k 1038 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = coeff_x / 2; k 1043 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = (coeff_x) / 2; k 1045 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = (coeff_x + 1) / 2; k 1047 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c return k; k 3396 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c u16 num_samps, t, k; k 3418 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = 1; k 3420 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c bw = phy_bw * 1000 * k; k 3422 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k++; k 3491 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c int k; k 3501 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_x, 0); k 3502 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c y = 8 + k; k 3503 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_x, 1); k 3504 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c x = 8 - k; k 3507 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_y, 0); k 3508 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c y = 8 + k; k 3509 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_y, 1); k 3510 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c x = 8 - k; k 3515 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_x, 0); k 3516 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c y = 8 + k; k 3517 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_x, 1); k 3518 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c x = 8 - k; k 3521 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_y, 0); k 3522 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c y = 8 + k; k 3523 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c k = wlc_lcnphy_calc_floor(coeff_y, 1); k 3524 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c x = 8 - k; k 3654 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c int phy_c4, phy_c5, k, l, j, phy_c6; k 3775 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c for (k = -phy_c7; k <= phy_c7; k += phy_c7) { k 3777 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_lcn.c phy_c11 = phy_c15 + k; k 23405 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c u8 k; k 23440 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c for (k = 0; k < NPHY_IQCAL_NUMGAINS; k++) { k 23441 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c if (tbl_iqcal_gainparams_nphy[band_idx][k][0] == k 23443 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c idx = k; k 23448 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1]; k 23449 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2]; k 23450 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3]; k 23453 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->ncorr[0] = tbl_iqcal_gainparams_nphy[band_idx][k][4]; k 23454 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->ncorr[1] = tbl_iqcal_gainparams_nphy[band_idx][k][5]; k 23455 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->ncorr[2] = tbl_iqcal_gainparams_nphy[band_idx][k][6]; k 23456 drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/phy_n.c params->ncorr[3] = tbl_iqcal_gainparams_nphy[band_idx][k][7]; k 4867 drivers/net/wireless/cisco/airo.c int v, i = 0, k = 0; /* i is index into line, k 4872 drivers/net/wireless/cisco/airo.c ai->config.rates[k++] = (u8)v; k 6888 drivers/net/wireless/cisco/airo.c int k; k 6899 drivers/net/wireless/cisco/airo.c k = 0; k 6901 drivers/net/wireless/cisco/airo.c range->freq[k].i = i + 1; /* List index */ k 6902 drivers/net/wireless/cisco/airo.c range->freq[k].m = 100000 * k 6904 drivers/net/wireless/cisco/airo.c range->freq[k++].e = 1; /* Values in MHz -> * 10^5 * 10 */ k 6906 drivers/net/wireless/cisco/airo.c range->num_frequency = k; k 108 drivers/net/wireless/intersil/orinoco/hermes.c int k = CMD_BUSY_TIMEOUT; k 113 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & HERMES_CMD_BUSY) && k) { k 114 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 139 drivers/net/wireless/intersil/orinoco/hermes.c int k; k 147 drivers/net/wireless/intersil/orinoco/hermes.c k = CMD_INIT_TIMEOUT; k 148 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_CMD)) && k) { k 149 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 202 drivers/net/wireless/intersil/orinoco/hermes.c int k; k 215 drivers/net/wireless/intersil/orinoco/hermes.c k = CMD_BUSY_TIMEOUT; k 217 drivers/net/wireless/intersil/orinoco/hermes.c while (k && (reg & HERMES_CMD_BUSY)) { k 222 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 256 drivers/net/wireless/intersil/orinoco/hermes.c int k; k 277 drivers/net/wireless/intersil/orinoco/hermes.c k = CMD_COMPL_TIMEOUT; k 278 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_CMD)) && k) { k 279 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 319 drivers/net/wireless/intersil/orinoco/hermes.c int k; k 330 drivers/net/wireless/intersil/orinoco/hermes.c k = ALLOC_COMPL_TIMEOUT; k 331 drivers/net/wireless/intersil/orinoco/hermes.c while ((!(reg & HERMES_EV_ALLOC)) && k) { k 332 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 370 drivers/net/wireless/intersil/orinoco/hermes.c int k; k 377 drivers/net/wireless/intersil/orinoco/hermes.c k = HERMES_BAP_BUSY_TIMEOUT; k 379 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & HERMES_OFFSET_BUSY) && k) { k 380 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 393 drivers/net/wireless/intersil/orinoco/hermes.c k = HERMES_BAP_BUSY_TIMEOUT; k 395 drivers/net/wireless/intersil/orinoco/hermes.c while ((reg & (HERMES_OFFSET_BUSY | HERMES_OFFSET_ERR)) && k) { k 396 drivers/net/wireless/intersil/orinoco/hermes.c k--; k 1005 drivers/net/wireless/intersil/orinoco/hw.c int k; k 1035 drivers/net/wireless/intersil/orinoco/hw.c for (k = 100; k > 0; k--) { k 1043 drivers/net/wireless/intersil/orinoco/hw.c if (k == 0) k 324 drivers/net/wireless/intersil/p54/eeprom.c unsigned int i, j, k, max_channel_num; k 397 drivers/net/wireless/intersil/p54/eeprom.c k = 0; k 399 drivers/net/wireless/intersil/p54/eeprom.c if (p54_generate_band(dev, list, &k, i) == 0) k 803 drivers/net/wireless/intersil/prism54/oid_mgt.c int i, k; k 804 drivers/net/wireless/intersil/prism54/oid_mgt.c k = snprintf(str, PRIV_STR_SIZE, "nr=%u\n", list->nr); k 806 drivers/net/wireless/intersil/prism54/oid_mgt.c k += snprintf(str + k, PRIV_STR_SIZE - k, k 815 drivers/net/wireless/intersil/prism54/oid_mgt.c return k; k 3218 drivers/net/wireless/marvell/mwifiex/cfg80211.c int j, k, valid_byte_cnt = 0; k 3222 drivers/net/wireless/marvell/mwifiex/cfg80211.c for (k = 0; k < 8; k++) { k 3223 drivers/net/wireless/marvell/mwifiex/cfg80211.c if (pat->mask[j] & 1 << k) { k 3225 drivers/net/wireless/marvell/mwifiex/cfg80211.c &pat->pattern[j * 8 + k], 1); k 427 drivers/net/wireless/marvell/mwifiex/cfp.c u32 k = 0; k 437 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_b, k 445 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_g, k 457 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_bg, k 465 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_a, k 476 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_a, k 483 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, supported_rates_n, k 492 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, adhoc_rates_b, k 498 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, adhoc_rates_g, k 504 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, adhoc_rates_bg, k 510 drivers/net/wireless/marvell/mwifiex/cfp.c k = mwifiex_copy_rates(rates, k, adhoc_rates_a, k 516 drivers/net/wireless/marvell/mwifiex/cfp.c return k; k 604 drivers/net/wireless/mediatek/mt76/mt7603/mac.c int i, k; k 635 drivers/net/wireless/mediatek/mt76/mt7603/mac.c for (k = 0; k < i; k++) { k 636 drivers/net/wireless/mediatek/mt76/mt7603/mac.c if (rates[i].idx != rates[k].idx) k 638 drivers/net/wireless/mediatek/mt76/mt7603/mac.c if ((rates[i].flags ^ rates[k].flags) & k 477 drivers/net/wireless/mediatek/mt76/mt7615/mac.c int i, k; k 508 drivers/net/wireless/mediatek/mt76/mt7615/mac.c for (k = 0; k < i; k++) { k 509 drivers/net/wireless/mediatek/mt76/mt7615/mac.c if (rates[i].idx != rates[k].idx) k 511 drivers/net/wireless/mediatek/mt76/mt7615/mac.c if ((rates[i].flags ^ rates[k].flags) & k 215 drivers/net/wireless/mediatek/mt76/mt76x0/init.c int ret, i, k; k 241 drivers/net/wireless/mediatek/mt76/mt76x0/init.c for (k = 0; k < 4; k++) k 242 drivers/net/wireless/mediatek/mt76/mt76x0/init.c mt76x02_mac_shared_key_setup(dev, i, k, NULL); k 73 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c int i, k; k 129 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c for (k = 0; k < 4; k++) k 130 drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c mt76x02_mac_shared_key_setup(dev, i, k, NULL); k 128 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c int i, k, err; k 171 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c for (k = 0; k < 4; k++) k 172 drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c mt76x02_mac_shared_key_setup(dev, i, k, NULL); k 318 drivers/net/wireless/mediatek/mt7601u/mac.c int i, j, k; k 326 drivers/net/wireless/mediatek/mt7601u/mac.c k = 0; k 342 drivers/net/wireless/mediatek/mt7601u/mac.c sum += (val & 0xffff) * (1 + k * 2) + k 343 drivers/net/wireless/mediatek/mt7601u/mac.c (val >> 16) * (2 + k * 2); k 344 drivers/net/wireless/mediatek/mt7601u/mac.c k++; k 1639 drivers/net/wireless/ray_cs.c int i, j, k; k 1655 drivers/net/wireless/ray_cs.c if ((k = hex_to_bin(in_str[j--])) != -1) k 1656 drivers/net/wireless/ray_cs.c out[i] = k; k 1662 drivers/net/wireless/ray_cs.c if ((k = hex_to_bin(in_str[j--])) != -1) k 1663 drivers/net/wireless/ray_cs.c out[i] += k << 4; k 76 drivers/net/wireless/realtek/rtlwifi/efuse.c u32 k = 0; k 102 drivers/net/wireless/realtek/rtlwifi/efuse.c k++; k 103 drivers/net/wireless/realtek/rtlwifi/efuse.c if (k == 1000) k 119 drivers/net/wireless/realtek/rtlwifi/efuse.c u32 k = 0; k 152 drivers/net/wireless/realtek/rtlwifi/efuse.c k++; k 153 drivers/net/wireless/realtek/rtlwifi/efuse.c if (k == 100) { k 154 drivers/net/wireless/realtek/rtlwifi/efuse.c k = 0; k 1444 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c u8 i, j, k, l, m; k 1451 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) k 1455 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c [i][j][k][m][l] k 1460 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) k 1464 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c [i][j][k][m][l] k 3759 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c int i, k, vdf_y[3], vdf_x[3], k 3869 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c for (k = 0; k <= 2; k++) { k 3870 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c switch (k) { k 3923 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; k 3925 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; k 3944 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (k == 3) { k 3945 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_x0[cal] = vdf_x[k-1]; k 3946 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c tx_y0[cal] = vdf_y[k-1]; k 4005 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c for (k = 0; k <= 2; k++) { k 4024 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c switch (k) { k 4142 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (k == 2) k 4170 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; k 4172 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21; k 4193 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c if (k == 3) { k 4194 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rx_x0[cal] = vdf_x[k-1]; k 4195 drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c rx_y0[cal] = vdf_y[k-1]; k 633 drivers/net/wireless/zydas/zd1211rw/zd_usb.c unsigned int l, k, n; k 635 drivers/net/wireless/zydas/zd1211rw/zd_usb.c k = get_unaligned_le16(&length_info->length[i]); k 636 drivers/net/wireless/zydas/zd1211rw/zd_usb.c if (k == 0) k 638 drivers/net/wireless/zydas/zd1211rw/zd_usb.c n = l+k; k 641 drivers/net/wireless/zydas/zd1211rw/zd_usb.c zd_mac_rx(zd_usb_to_hw(usb), buffer+l, k); k 134 drivers/nfc/fdp/i2c.c u8 tmp[FDP_NCI_I2C_MAX_PAYLOAD], lrc, k; k 141 drivers/nfc/fdp/i2c.c for (k = 0; k < 2; k++) { k 144 drivers/of/base.c u32 k; k 149 drivers/of/base.c for (k = 0; k < cache_entries; k++) k 150 drivers/of/base.c of_node_put(phandle_cache[k]); k 209 drivers/of/overlay.c int k; k 229 drivers/of/overlay.c for (k = 0; k < ovcs->count; k++) { k 230 drivers/of/overlay.c fragment = &ovcs->fragments[k]; k 234 drivers/of/overlay.c if (k >= ovcs->count) k 6420 drivers/pci/pci.c char *k = strchr(str, ','); k 6421 drivers/pci/pci.c if (k) k 6422 drivers/pci/pci.c *k++ = 0; k 6474 drivers/pci/pci.c str = k; k 755 drivers/pcmcia/i82365.c int i, j, sock, k, ns, id; k 816 drivers/pcmcia/i82365.c for (k = 0; k <= sockets; k++) k 817 drivers/pcmcia/i82365.c i365_set(k, I365_MEM(0)+I365_W_OFF, k); k 818 drivers/pcmcia/i82365.c for (k = 0; k <= sockets; k++) k 819 drivers/pcmcia/i82365.c if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k) k 821 drivers/pcmcia/i82365.c if (k <= sockets) break; k 573 drivers/pinctrl/mvebu/pinctrl-mvebu.c unsigned gid, n, k; k 607 drivers/pinctrl/mvebu/pinctrl-mvebu.c for (k = 0; k < ctrl->npins; k++) k 608 drivers/pinctrl/mvebu/pinctrl-mvebu.c ctrl->pins[k] = ctrl->pid + k; k 670 drivers/pinctrl/mvebu/pinctrl-mvebu.c for (k = 1; k < ctrl->npins; k++) { k 676 drivers/pinctrl/mvebu/pinctrl-mvebu.c pctl->groups[gid].pins = &ctrl->pins[k]; k 678 drivers/pinctrl/mvebu/pinctrl-mvebu.c sprintf(noname_buf, "mpp%d", ctrl->pid+k); k 897 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ k 901 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c .flag = k } k 1345 drivers/pinctrl/pinctrl-at91.c int ret, i, j, k, ngpio_chips_enabled = 0; k 1382 drivers/pinctrl/pinctrl-at91.c for (i = 0, k = 0; i < gpio_banks; i++) { k 1383 drivers/pinctrl/pinctrl-at91.c for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { k 1384 drivers/pinctrl/pinctrl-at91.c pdesc->number = k; k 2634 drivers/pinctrl/pinctrl-rockchip.c int k; k 2652 drivers/pinctrl/pinctrl-rockchip.c for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { k 2654 drivers/pinctrl/pinctrl-rockchip.c for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { k 2655 drivers/pinctrl/pinctrl-rockchip.c pdesc->number = k; k 1563 drivers/pinctrl/pinctrl-st.c int i = 0, j = 0, k = 0, bank; k 1634 drivers/pinctrl/pinctrl-st.c k = info->banks[bank].range.pin_base; k 1636 drivers/pinctrl/pinctrl-st.c for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) { k 1637 drivers/pinctrl/pinctrl-st.c pdesc->number = k; k 193 drivers/pinctrl/sh-pfc/core.c unsigned int k; k 203 drivers/pinctrl/sh-pfc/core.c for (k = 0; k <= in_pos; k++) k 204 drivers/pinctrl/sh-pfc/core.c *posp -= crp->var_field_width[k]; k 241 drivers/pinctrl/sh-pfc/core.c unsigned int k = 0; k 245 drivers/pinctrl/sh-pfc/core.c pfc->info->cfg_regs + k; k 277 drivers/pinctrl/sh-pfc/core.c k++; k 287 drivers/pinctrl/sh-pfc/core.c unsigned int k; k 294 drivers/pinctrl/sh-pfc/core.c for (k = 0; k < pfc->info->pinmux_data_size; k++) { k 295 drivers/pinctrl/sh-pfc/core.c if (data[k] == mark) { k 296 drivers/pinctrl/sh-pfc/core.c *enum_idp = data[k + 1]; k 297 drivers/pinctrl/sh-pfc/core.c return k + 1; k 768 drivers/pinctrl/sh-pfc/core.c unsigned int i, j, k; k 814 drivers/pinctrl/sh-pfc/core.c for (k = 0; k < info->nr_groups; k++) { k 815 drivers/pinctrl/sh-pfc/core.c if (info->groups[k].name && k 817 drivers/pinctrl/sh-pfc/core.c info->groups[k].name)) { k 818 drivers/pinctrl/sh-pfc/core.c refcnts[k]++; k 823 drivers/pinctrl/sh-pfc/core.c if (k == info->nr_groups) { k 201 drivers/pinctrl/sh-pfc/gpio.c unsigned int i, k; k 206 drivers/pinctrl/sh-pfc/gpio.c for (k = 0; gpios[k] >= 0; k++) { k 207 drivers/pinctrl/sh-pfc/gpio.c if (gpios[k] == offset) k 653 drivers/pinctrl/tegra/pinctrl-tegra.c unsigned int i, k; k 658 drivers/pinctrl/tegra/pinctrl-tegra.c for (k = 0; k < bank_size; k++) k 671 drivers/pinctrl/tegra/pinctrl-tegra.c unsigned int i, k; k 676 drivers/pinctrl/tegra/pinctrl-tegra.c for (k = 0; k < bank_size; k++) k 795 drivers/ps3/ps3av.c int i, j, k, res; k 816 drivers/ps3/ps3av.c for (k = 0; k < hw_conf->num_of_spdif; k++) k 817 drivers/ps3/ps3av.c ps3av->av_port[i + j + k] = PS3AV_CMD_AVPORT_SPDIF_0 + k; k 4877 drivers/regulator/core.c int i, k; k 4893 drivers/regulator/core.c for (k = 1; k < __n_coupled; k++) { k 4894 drivers/regulator/core.c __c_rdev = __c_desc->coupled_rdevs[k]; k 4897 drivers/regulator/core.c __c_desc->coupled_rdevs[k] = NULL; k 55 drivers/rtc/rtc-r9701.c int k, ret; k 59 drivers/rtc/rtc-r9701.c for (k = 0; ret == 0 && k < no_regs; k++) { k 60 drivers/rtc/rtc-r9701.c txbuf[0] = 0x80 | regs[k]; k 62 drivers/rtc/rtc-r9701.c regs[k] = rxbuf[0]; k 947 drivers/s390/block/dcssblk.c int rc, i, j, k; k 963 drivers/s390/block/dcssblk.c for (k = 0; (buf[k] != ':') && (buf[k] != '\0'); k++) k 964 drivers/s390/block/dcssblk.c buf[k] = toupper(buf[k]); k 965 drivers/s390/block/dcssblk.c buf[k] = '\0'; k 157 drivers/s390/char/keyboard.c int i, j, k; k 165 drivers/s390/char/keyboard.c k = ((i & 1) << 7) + j; k 169 drivers/s390/char/keyboard.c ascebc[KVAL(keysym)] = k; k 171 drivers/s390/char/keyboard.c ascebc[ret_diacr[KVAL(keysym)]] = k; k 184 drivers/s390/char/keyboard.c int i, j, k; k 193 drivers/s390/char/keyboard.c k = ((i & 1) << 7) + j; k 196 drivers/s390/char/keyboard.c ebcasc[k] = KVAL(keysym); k 198 drivers/s390/char/keyboard.c ebcasc[k] = ret_diacr[KVAL(keysym)]; k 1262 drivers/s390/char/tty3270.c int k; k 1273 drivers/s390/char/tty3270.c k = min_t(int, line->len - tp->cx, tp->view.cols - tp->cx - n); k 1274 drivers/s390/char/tty3270.c while (k--) k 1275 drivers/s390/char/tty3270.c line->cells[tp->cx + n + k] = line->cells[tp->cx + k]; k 269 drivers/s390/crypto/pkey_api.c unsigned int k; k 292 drivers/s390/crypto/pkey_api.c k = cpacf_kmc(fc | CPACF_ENCRYPT, ¶m, null_msg, dest_buf, k 294 drivers/s390/crypto/pkey_api.c if (k != sizeof(null_msg)) { k 4739 drivers/s390/net/qeth_core_main.c int i, j, k; k 4784 drivers/s390/net/qeth_core_main.c for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i) k 4785 drivers/s390/net/qeth_core_main.c for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; j++, k++) k 4786 drivers/s390/net/qeth_core_main.c out_sbal_ptrs[k] = k 5460 drivers/scsi/FlashPoint.c unsigned char i, k, ScamFlg; k 5591 drivers/scsi/FlashPoint.c k = FPT_scxferc(p_port, 0x00); k 5593 drivers/scsi/FlashPoint.c if (FPT_scvalq(k)) { k 5599 drivers/scsi/FlashPoint.c (k & k 5761 drivers/scsi/FlashPoint.c unsigned char i, k, scam_id; k 5772 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k++) { k 5773 drivers/scsi/FlashPoint.c temp_id_string[k] = (unsigned char)0x00; k 5787 drivers/scsi/FlashPoint.c for (k = 4; k < ID_STRING_LENGTH; k++) k 5788 drivers/scsi/FlashPoint.c temp_id_string[k] = (unsigned char)0x00; k 5806 drivers/scsi/FlashPoint.c for (k = 1; k < 0x08; k <<= 1) k 5807 drivers/scsi/FlashPoint.c if (!(k & i)) k 6204 drivers/scsi/FlashPoint.c unsigned char i, k, max_id; k 6219 drivers/scsi/FlashPoint.c for (k = 0; k < 4; k++) k 6220 drivers/scsi/FlashPoint.c FPT_scamInfo[i].id_string[k] = k 6221 drivers/scsi/FlashPoint.c pCurrNvRam->niScamTbl[i][k]; k 6222 drivers/scsi/FlashPoint.c for (k = 4; k < ID_STRING_LENGTH; k++) k 6223 drivers/scsi/FlashPoint.c FPT_scamInfo[i].id_string[k] = k 6234 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k += 2) { k 6240 drivers/scsi/FlashPoint.c ((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2))); k 6241 drivers/scsi/FlashPoint.c FPT_scamInfo[i].id_string[k] = k 6244 drivers/scsi/FlashPoint.c FPT_scamInfo[i].id_string[k + 1] = k 6258 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k++) k 6259 drivers/scsi/FlashPoint.c FPT_scamInfo[p_our_id].id_string[k] = FPT_scamHAString[k]; k 6276 drivers/scsi/FlashPoint.c unsigned char i, k, match; k 6282 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k++) { k 6283 drivers/scsi/FlashPoint.c if (p_id_string[k] != FPT_scamInfo[i].id_string[k]) k 6309 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k++) { k 6310 drivers/scsi/FlashPoint.c FPT_scamInfo[match].id_string[k] = k 6311 drivers/scsi/FlashPoint.c p_id_string[k]; k 6353 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k++) { k 6354 drivers/scsi/FlashPoint.c FPT_scamInfo[match].id_string[k] = k 6355 drivers/scsi/FlashPoint.c p_id_string[k]; k 6390 drivers/scsi/FlashPoint.c unsigned char i, k, max_id; k 6409 drivers/scsi/FlashPoint.c for (k = 0; k < ID_STRING_LENGTH; k += 2) { k 6410 drivers/scsi/FlashPoint.c ee_data = FPT_scamInfo[i].id_string[k + 1]; k 6412 drivers/scsi/FlashPoint.c ee_data |= FPT_scamInfo[i].id_string[k]; k 6417 drivers/scsi/FlashPoint.c ((unsigned short)ID_STRING_LENGTH / 2)) + (unsigned short)(k / 2))); k 2446 drivers/scsi/advansys.c int k; k 2454 drivers/scsi/advansys.c if ((k = (l - i) / 4) >= 8) { k 2455 drivers/scsi/advansys.c k = 8; k 2461 drivers/scsi/advansys.c for (j = 0; j < k; j++) { k 153 drivers/scsi/aic7xxx/aic7xxx_93cx6.c u_int k = 0; k 161 drivers/scsi/aic7xxx/aic7xxx_93cx6.c for (k = start_addr; k < count + start_addr; k++) { k 171 drivers/scsi/aic7xxx/aic7xxx_93cx6.c if ((k & (1 << i)) != 0) k 177 drivers/scsi/aic7xxx/aic7xxx_93cx6.c if ((k & (1 << i)) != 0) k 198 drivers/scsi/aic7xxx/aic7xxx_93cx6.c buf[k - start_addr] = v; k 205 drivers/scsi/aic7xxx/aic7xxx_93cx6.c for (k = 0; k < count; k = k + 1) { k 206 drivers/scsi/aic7xxx/aic7xxx_93cx6.c if (((k % 8) == 0) && (k != 0)) { k 209 drivers/scsi/aic7xxx/aic7xxx_93cx6.c printk(KERN_CONT " 0x%x", buf[k]); k 227 drivers/scsi/aic7xxx/aic7xxx_93cx6.c int i, k; k 247 drivers/scsi/aic7xxx/aic7xxx_93cx6.c for (k = start_addr; k < count + start_addr; k++) { k 253 drivers/scsi/aic7xxx/aic7xxx_93cx6.c if ((k & (1 << i)) != 0) k 259 drivers/scsi/aic7xxx/aic7xxx_93cx6.c if ((k & (1 << i)) != 0) k 264 drivers/scsi/aic7xxx/aic7xxx_93cx6.c v = buf[k - start_addr]; k 342 drivers/scsi/aic94xx/aic94xx_hwi.c int i, k, z = 0; k 352 drivers/scsi/aic94xx/aic94xx_hwi.c for (k = 0; k < ASD_EDBS_PER_SCB; k++) { k 353 drivers/scsi/aic94xx/aic94xx_hwi.c struct sg_el *eb = &escb->eb[k]; k 1339 drivers/scsi/aic94xx/aic94xx_hwi.c int num = 0, k; k 1353 drivers/scsi/aic94xx/aic94xx_hwi.c k = num; k 1354 drivers/scsi/aic94xx/aic94xx_hwi.c ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL); k 1359 drivers/scsi/aic94xx/aic94xx_hwi.c num -= k; k 1367 drivers/scsi/aic94xx/aic94xx_hwi.c k = asd_post_ascb_list(asd_ha, ascb_list, num); k 1368 drivers/scsi/aic94xx/aic94xx_hwi.c if (k) k 1371 drivers/scsi/aic94xx/aic94xx_hwi.c return k; k 114 drivers/scsi/aic94xx/aic94xx_scb.c int i, k = 0; k 118 drivers/scsi/aic94xx/aic94xx_scb.c return k; k 119 drivers/scsi/aic94xx/aic94xx_scb.c k++; k 125 drivers/scsi/atp870u.c unsigned long adrcnt, k; k 152 drivers/scsi/atp870u.c for (k=0; k < 1000; k++) { k 199 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 200 drivers/scsi/atp870u.c k -= adrcnt; k 201 drivers/scsi/atp870u.c dev->id[c][target_id].tran_len = k; k 253 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 254 drivers/scsi/atp870u.c k -= adrcnt; k 255 drivers/scsi/atp870u.c dev->id[c][target_id].tran_len = k; k 291 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 292 drivers/scsi/atp870u.c k -= adrcnt; k 293 drivers/scsi/atp870u.c dev->id[c][target_id].tran_len = k; k 343 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 345 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]); k 346 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]); k 347 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]); k 349 drivers/scsi/atp870u.c printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12)); k 407 drivers/scsi/atp870u.c k = 0x10000; k 409 drivers/scsi/atp870u.c k = id; k 411 drivers/scsi/atp870u.c if (k > adrcnt) { k 413 drivers/scsi/atp870u.c (k - adrcnt); k 418 drivers/scsi/atp870u.c adrcnt -= k; k 530 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 531 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); k 532 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); k 533 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); k 549 drivers/scsi/atp870u.c k = dev->id[c][target_id].last_len; k 550 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); k 551 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); k 552 drivers/scsi/atp870u.c atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); k 935 drivers/scsi/atp870u.c unsigned short int i, k; k 940 drivers/scsi/atp870u.c k = atp_readw_io(dev, 0, 0x1c); k 941 drivers/scsi/atp870u.c j = (unsigned char) (k >> 8); k 942 drivers/scsi/atp870u.c if ((k & 0x8000) != 0) /* DB7 all release? */ k 969 drivers/scsi/atp870u.c unsigned char i, j, k; k 1019 drivers/scsi/atp870u.c k = (i & 0x07) | 0x40; k 1021 drivers/scsi/atp870u.c k = i; k 1023 drivers/scsi/atp870u.c atp_writeb_io(dev, 0, 0x15, k); k 1033 drivers/scsi/atp870u.c k = atp_readb_io(dev, 0, 0x17); k 1034 drivers/scsi/atp870u.c if ((k == 0x85) || (k == 0x42)) k 1036 drivers/scsi/atp870u.c if (k != 0x16) k 1038 drivers/scsi/atp870u.c } while (k != 0x16); k 1039 drivers/scsi/atp870u.c if ((k == 0x85) || (k == 0x42)) k 1118 drivers/scsi/atp870u.c k = fun_scam(dev, &val); k 1119 drivers/scsi/atp870u.c if ((k & 0x03) == 0) k 1123 drivers/scsi/atp870u.c if ((k & 0x02) != 0) k 1141 drivers/scsi/atp870u.c k = mbuf[1]; k 1144 drivers/scsi/atp870u.c m <<= k; k 1147 drivers/scsi/atp870u.c if (k > 0) k 1148 drivers/scsi/atp870u.c k--; k 1154 drivers/scsi/atp870u.c k = i; /* max acceptable ID# */ k 1157 drivers/scsi/atp870u.c m <<= k; k 1160 drivers/scsi/atp870u.c if (k > 0) k 1161 drivers/scsi/atp870u.c k--; k 1168 drivers/scsi/atp870u.c if (k < 8) { k 1173 drivers/scsi/atp870u.c k &= 0x07; k 1174 drivers/scsi/atp870u.c quintet[1] = g2q_tab[k]; k 1191 drivers/scsi/atp870u.c int j, k; k 1193 drivers/scsi/atp870u.c for (k = 0; k < 16; k++) { k 1194 drivers/scsi/atp870u.c if (!atp_dev->id[j][k].prd_table) k 1196 drivers/scsi/atp870u.c dma_free_coherent(&atp_dev->pdev->dev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus); k 1197 drivers/scsi/atp870u.c atp_dev->id[j][k].prd_table = NULL; k 1205 drivers/scsi/atp870u.c int c,k; k 1207 drivers/scsi/atp870u.c for(k=0;k<16;k++) { k 1208 drivers/scsi/atp870u.c atp_dev->id[c][k].prd_table = dma_alloc_coherent(&atp_dev->pdev->dev, 1024, &(atp_dev->id[c][k].prd_bus), GFP_KERNEL); k 1209 drivers/scsi/atp870u.c if (!atp_dev->id[c][k].prd_table) { k 1214 drivers/scsi/atp870u.c atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus; k 1215 drivers/scsi/atp870u.c atp_dev->id[c][k].devsp=0x20; k 1216 drivers/scsi/atp870u.c atp_dev->id[c][k].devtype = 0x7f; k 1217 drivers/scsi/atp870u.c atp_dev->id[c][k].curr_req = NULL; k 1229 drivers/scsi/atp870u.c for (k = 0; k < qcnt; k++) { k 1230 drivers/scsi/atp870u.c atp_dev->quereq[c][k] = NULL; k 1232 drivers/scsi/atp870u.c for (k = 0; k < 16; k++) { k 1233 drivers/scsi/atp870u.c atp_dev->id[c][k].curr_req = NULL; k 1234 drivers/scsi/atp870u.c atp_dev->sp[c][k] = 0x04; k 1256 drivers/scsi/atp870u.c unsigned char k, host_id; k 1286 drivers/scsi/atp870u.c k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10; k 1287 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x3a, k); k 1288 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x3a, k & 0xdf); k 1290 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x3a, k); k 1307 drivers/scsi/atp870u.c unsigned char k, m, host_id; k 1359 drivers/scsi/atp870u.c for (k = 0; k < 16; k++) { k 1360 drivers/scsi/atp870u.c n = 1 << k; k 1361 drivers/scsi/atp870u.c if (atpdev->sp[0][k] > 1) k 1364 drivers/scsi/atp870u.c if (atpdev->sp[0][k] == 0) k 1370 drivers/scsi/atp870u.c k = atp_readb_base(atpdev, 0x38) & 0x80; k 1371 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x38, k); k 1392 drivers/scsi/atp870u.c unsigned char k, m, c; k 1414 drivers/scsi/atp870u.c for (k = 0; k < 4; k++) { k 1416 drivers/scsi/atp870u.c ((u32 *)&setupdata[m][0])[k] = atp_readl_base(atpdev, 0x38); k 1418 drivers/scsi/atp870u.c for (k = 0; k < 4; k++) { k 1420 drivers/scsi/atp870u.c ((u32 *)&atpdev->sp[m][0])[k] = atp_readl_base(atpdev, 0x38); k 1430 drivers/scsi/atp870u.c for (k = 0; k < 16; k++) { k 1431 drivers/scsi/atp870u.c n = 1 << k; k 1432 drivers/scsi/atp870u.c if (atpdev->sp[c][k] > 1) k 1435 drivers/scsi/atp870u.c if (atpdev->sp[c][k] == 0) k 1441 drivers/scsi/atp870u.c k = setupdata[c][1]; k 1442 drivers/scsi/atp870u.c if ((k & 0x40) != 0) k 1444 drivers/scsi/atp870u.c k &= 0x07; k 1445 drivers/scsi/atp870u.c atpdev->global_map[c] |= k; k 1452 drivers/scsi/atp870u.c k = atp_readb_base(atpdev, 0x28) & 0x8f; k 1453 drivers/scsi/atp870u.c k |= 0x10; k 1454 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x28, k); k 1466 drivers/scsi/atp870u.c k = atpdev->host_id[0]; k 1467 drivers/scsi/atp870u.c if (k > 7) k 1468 drivers/scsi/atp870u.c k = (k & 0x07) | 0x40; k 1469 drivers/scsi/atp870u.c atp_set_host_id(atpdev, 0, k); k 1471 drivers/scsi/atp870u.c k = atpdev->host_id[1]; k 1472 drivers/scsi/atp870u.c if (k > 7) k 1473 drivers/scsi/atp870u.c k = (k & 0x07) | 0x40; k 1474 drivers/scsi/atp870u.c atp_set_host_id(atpdev, 1, k); k 1483 drivers/scsi/atp870u.c k = atp_readb_base(atpdev, 0x28) & 0xcf; k 1484 drivers/scsi/atp870u.c k |= 0xc0; k 1485 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x28, k); k 1486 drivers/scsi/atp870u.c k = atp_readb_base(atpdev, 0x1f) | 0x80; k 1487 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x1f, k); k 1488 drivers/scsi/atp870u.c k = atp_readb_base(atpdev, 0x29) | 0x01; k 1489 drivers/scsi/atp870u.c atp_writeb_base(atpdev, 0x29, k); k 1587 drivers/scsi/atp870u.c unsigned char j, k, c; k 1609 drivers/scsi/atp870u.c for (k=0; k < workrequ->cmd_len; k++) { k 1610 drivers/scsi/atp870u.c printk(" %2x ",workrequ->cmnd[k]); k 1714 drivers/scsi/atp870u.c unsigned char i, j, k, rmb, n; k 1817 drivers/scsi/atp870u.c k = atp_readb_io(dev, c, 0x1f); k 1818 drivers/scsi/atp870u.c if ((k & 0x01) != 0) { k 1822 drivers/scsi/atp870u.c if ((k & 0x80) == 0) { k 1936 drivers/scsi/atp870u.c k = 0; k 1940 drivers/scsi/atp870u.c mbuf[k++] = atp_readb_io(dev, c, 0x19); k 2060 drivers/scsi/atp870u.c k = 0; k 2064 drivers/scsi/atp870u.c mbuf[k++] = atp_readb_io(dev, c, 0x19); k 2225 drivers/scsi/atp870u.c k = 0; k 2229 drivers/scsi/atp870u.c mbuf[k++] = atp_readb_io(dev, c, 0x19); k 253 drivers/scsi/bfa/bfa_fcpim.h uint16_t k = (__ioim)->iotag >> BFA_IOIM_RETRY_TAG_OFFSET; \ k 254 drivers/scsi/bfa/bfa_fcpim.h k++; (__ioim)->iotag &= BFA_IOIM_IOTAG_MASK; \ k 255 drivers/scsi/bfa/bfa_fcpim.h (__ioim)->iotag |= k << BFA_IOIM_RETRY_TAG_OFFSET; \ k 261 drivers/scsi/bfa/bfa_fcpim.h uint16_t k = ioim->iotag >> BFA_IOIM_RETRY_TAG_OFFSET; k 262 drivers/scsi/bfa/bfa_fcpim.h if (k < BFA_IOIM_RETRY_MAX) k 1290 drivers/scsi/bfa/bfa_fcs_lport.c u8 k = 0; k 1302 drivers/scsi/bfa/bfa_fcs_lport.c port->port_topo.ploop.alpa_pos_map[k] = k 1304 drivers/scsi/bfa/bfa_fcs_lport.c k++; k 1305 drivers/scsi/bfa/bfa_fcs_lport.c bfa_trc(port->fcs->bfa, k); k 1307 drivers/scsi/bfa/bfa_fcs_lport.c port->port_topo.ploop.alpa_pos_map[k]); k 1311 drivers/scsi/bfa/bfa_fcs_lport.c port->port_topo.ploop.num_alpa = k; k 265 drivers/scsi/constants.c int arr_sz, k; k 284 drivers/scsi/constants.c for (k = 0; k < arr_sz; ++k, ++arr) { k 288 drivers/scsi/constants.c if (k < arr_sz) k 451 drivers/scsi/constants.c int k; k 453 drivers/scsi/constants.c for (k = 0; k < ARRAY_SIZE(scsi_mlreturn_arr); ++k, ++arr) { k 2246 drivers/scsi/csiostor/csio_hw.c int k, int c) k 2255 drivers/scsi/csiostor/csio_hw.c if (k > c) { k 2267 drivers/scsi/csiostor/csio_hw.c FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), k 2268 drivers/scsi/csiostor/csio_hw.c FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); k 2370 drivers/scsi/csiostor/csio_hw.c uint32_t d, c, k; k 2374 drivers/scsi/csiostor/csio_hw.c k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0; k 2385 drivers/scsi/csiostor/csio_hw.c FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k), k 2386 drivers/scsi/csiostor/csio_hw.c FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k)); k 339 drivers/scsi/csiostor/csio_init.c int i, j, idx, k = 0; k 411 drivers/scsi/csiostor/csio_init.c k = j % info->max_cpus; k 412 drivers/scsi/csiostor/csio_init.c orig = &hw->sqset[i][k]; k 356 drivers/scsi/csiostor/csio_isr.c int k = CSIO_EXTRA_VECS; k 358 drivers/scsi/csiostor/csio_isr.c int cnt = hw->num_sqsets + k; k 372 drivers/scsi/csiostor/csio_isr.c for (i = k; i < cnt; i++, entryp++) { k 383 drivers/scsi/csiostor/csio_isr.c int rv, i, j, k = 0; k 403 drivers/scsi/csiostor/csio_isr.c rv = request_irq(pci_irq_vector(pdev, k), csio_nondata_isr, 0, k 404 drivers/scsi/csiostor/csio_isr.c entryp[k].desc, hw); k 407 drivers/scsi/csiostor/csio_isr.c pci_irq_vector(pdev, k), rv); k 411 drivers/scsi/csiostor/csio_isr.c entryp[k++].dev_id = hw; k 413 drivers/scsi/csiostor/csio_isr.c rv = request_irq(pci_irq_vector(pdev, k), csio_fwevt_isr, 0, k 414 drivers/scsi/csiostor/csio_isr.c entryp[k].desc, hw); k 417 drivers/scsi/csiostor/csio_isr.c pci_irq_vector(pdev, k), rv); k 421 drivers/scsi/csiostor/csio_isr.c entryp[k++].dev_id = (void *)hw; k 426 drivers/scsi/csiostor/csio_isr.c for (j = 0; j < info->max_cpus; j++, k++) { k 430 drivers/scsi/csiostor/csio_isr.c rv = request_irq(pci_irq_vector(pdev, k), csio_scsi_isr, 0, k 431 drivers/scsi/csiostor/csio_isr.c entryp[k].desc, q); k 435 drivers/scsi/csiostor/csio_isr.c pci_irq_vector(pdev, k), rv); k 439 drivers/scsi/csiostor/csio_isr.c entryp[k].dev_id = q; k 449 drivers/scsi/csiostor/csio_isr.c for (i = 0; i < k; i++) k 499 drivers/scsi/csiostor/csio_isr.c int i, j, k, n, min, cnt; k 531 drivers/scsi/csiostor/csio_isr.c k = 0; k 532 drivers/scsi/csiostor/csio_isr.c csio_set_nondata_intr_idx(hw, k); k 533 drivers/scsi/csiostor/csio_isr.c csio_set_mb_intr_idx(csio_hw_to_mbm(hw), k++); k 534 drivers/scsi/csiostor/csio_isr.c csio_set_fwevt_intr_idx(hw, k++); k 540 drivers/scsi/csiostor/csio_isr.c n = (j % info->max_cpus) + k; k 544 drivers/scsi/csiostor/csio_isr.c k += info->max_cpus; k 821 drivers/scsi/cxlflash/main.c int k; k 832 drivers/scsi/cxlflash/main.c for (k = cfg->afu->num_hwqs - 1; k >= 0; k--) k 833 drivers/scsi/cxlflash/main.c term_intr(cfg, UNMAP_THREE, k); k 837 drivers/scsi/cxlflash/main.c for (k = cfg->afu->num_hwqs - 1; k >= 0; k--) k 838 drivers/scsi/cxlflash/main.c term_mc(cfg, k); k 1638 drivers/scsi/cxlflash/main.c int ro_start, ro_size, i, j, k; k 1689 drivers/scsi/cxlflash/main.c for (k = 0; k < cfg->num_fc_ports; k++) { k 1693 drivers/scsi/cxlflash/main.c i = pci_vpd_find_info_keyword(vpd_data, i, j, wwpn_vpd_tags[k]); k 1697 drivers/scsi/cxlflash/main.c __func__, k); k 1698 drivers/scsi/cxlflash/main.c wwpn[k] = 0ULL; k 1706 drivers/scsi/cxlflash/main.c __func__, k); k 1712 drivers/scsi/cxlflash/main.c rc = kstrtoul(tmp_buf, WWPN_LEN, (ulong *)&wwpn[k]); k 1715 drivers/scsi/cxlflash/main.c __func__, k); k 1720 drivers/scsi/cxlflash/main.c dev_dbg(dev, "%s: wwpn%d=%016llx\n", __func__, k, wwpn[k]); k 3673 drivers/scsi/cxlflash/main.c int k; k 3719 drivers/scsi/cxlflash/main.c for (k = 0; k < MAX_FC_PORTS; k++) k 3720 drivers/scsi/cxlflash/main.c cfg->last_lun_index[k] = CXLFLASH_NUM_VLUNS/2 - 1; k 836 drivers/scsi/cxlflash/vlun.c int k; k 849 drivers/scsi/cxlflash/vlun.c for (k = 0; k < cfg->num_fc_ports; k++) k 850 drivers/scsi/cxlflash/vlun.c if (lli->port_sel & (1 << k)) { k 851 drivers/scsi/cxlflash/vlun.c fc_port_luns = get_fc_port_luns(cfg, k); k 852 drivers/scsi/cxlflash/vlun.c writeq_be(lli->lun_id[k], &fc_port_luns[lind]); k 853 drivers/scsi/cxlflash/vlun.c dev_dbg(dev, "\t%d=%llx\n", k, lli->lun_id[k]); k 891 drivers/scsi/cxlflash/vlun.c int k; k 912 drivers/scsi/cxlflash/vlun.c for (k = 0; k < cfg->num_fc_ports; k++) { k 913 drivers/scsi/cxlflash/vlun.c if (!(lli->port_sel & (1 << k))) k 916 drivers/scsi/cxlflash/vlun.c if (cfg->promote_lun_index == cfg->last_lun_index[k]) { k 925 drivers/scsi/cxlflash/vlun.c for (k = 0; k < cfg->num_fc_ports; k++) { k 926 drivers/scsi/cxlflash/vlun.c if (!(lli->port_sel & (1 << k))) k 929 drivers/scsi/cxlflash/vlun.c fc_port_luns = get_fc_port_luns(cfg, k); k 930 drivers/scsi/cxlflash/vlun.c writeq_be(lli->lun_id[k], &fc_port_luns[lind]); k 931 drivers/scsi/cxlflash/vlun.c dev_dbg(dev, "\t%d=%llx\n", k, lli->lun_id[k]); k 509 drivers/scsi/device_handler/scsi_dh_alua.c int len, k, off, bufflen = ALUA_RTPG_SIZE; k 641 drivers/scsi/device_handler/scsi_dh_alua.c for (k = tpg_desc_tbl_off, desc = buff + tpg_desc_tbl_off; k 642 drivers/scsi/device_handler/scsi_dh_alua.c k < len; k 643 drivers/scsi/device_handler/scsi_dh_alua.c k += off, desc += off) { k 1318 drivers/scsi/esas2r/esas2r_ioctl.c int i = 0, k = 0; k 1325 drivers/scsi/esas2r/esas2r_ioctl.c ioctl->data.chanlist.channel[k] = i; k 1326 drivers/scsi/esas2r/esas2r_ioctl.c k++; k 155 drivers/scsi/gdth_proc.c int id, i, j, k, sec, flag; k 301 drivers/scsi/gdth_proc.c for (k = 0; k < pds->count; ++k) { k 302 drivers/scsi/gdth_proc.c if (pds->list[k].tid == pdi->target_id && k 303 drivers/scsi/gdth_proc.c pds->list[k].lun == pdi->lun) { k 306 drivers/scsi/gdth_proc.c pds->list[k].retries, k 307 drivers/scsi/gdth_proc.c pds->list[k].reassigns); k 344 drivers/scsi/gdth_proc.c j = k = 0; k 366 drivers/scsi/gdth_proc.c k++; j--; k 404 drivers/scsi/gdth_proc.c no_mdrv - j - k, k); k 498 drivers/scsi/gdth_proc.c k = phg->entry[j].host_drive; k 499 drivers/scsi/gdth_proc.c if (k >= MAX_LDRIVES) k 501 drivers/scsi/gdth_proc.c ha->hdr[k].ldr_no = phg->entry[j].log_drive; k 502 drivers/scsi/gdth_proc.c ha->hdr[k].rw_attribs = phg->entry[j].rw_attribs; k 503 drivers/scsi/gdth_proc.c ha->hdr[k].start_sec = phg->entry[j].start_sec; k 175 drivers/scsi/imm.c int k; k 181 drivers/scsi/imm.c k = IMM_SPIN_TMO; k 184 drivers/scsi/imm.c k--; k 187 drivers/scsi/imm.c while (!(r & 0x80) && (k)); k 209 drivers/scsi/imm.c if (k) k 543 drivers/scsi/imm.c int k; k 552 drivers/scsi/imm.c k = IMM_SELECT_TMO; k 554 drivers/scsi/imm.c k--; k 555 drivers/scsi/imm.c } while ((r_str(ppb) & 0x08) && (k)); k 557 drivers/scsi/imm.c if (!k) k 577 drivers/scsi/imm.c k = IMM_SELECT_TMO; k 579 drivers/scsi/imm.c k--; k 581 drivers/scsi/imm.c while (!(r_str(ppb) & 0x08) && (k)); k 587 drivers/scsi/imm.c return (k) ? 1 : 0; k 604 drivers/scsi/imm.c int k; k 607 drivers/scsi/imm.c for (k = 0; k < cmd->cmd_len; k += 2) k 608 drivers/scsi/imm.c if (!imm_out(dev, &cmd->cmnd[k], 2)) k 1013 drivers/scsi/imm.c int loop, old_mode, status, k, ppb = dev->base; k 1054 drivers/scsi/imm.c k = 1000000; /* 1 Second */ k 1057 drivers/scsi/imm.c k--; k 1059 drivers/scsi/imm.c } while (!(l & 0x80) && (k)); k 3187 drivers/scsi/lpfc/lpfc_hbadisc.c int numalpa, j, k; k 3201 drivers/scsi/lpfc/lpfc_hbadisc.c for (k = 1; j < numalpa; k++) { k 3202 drivers/scsi/lpfc/lpfc_hbadisc.c un.pamap[k - 1] = k 3205 drivers/scsi/lpfc/lpfc_hbadisc.c if (k == 16) k 5817 drivers/scsi/lpfc/lpfc_sli.c uint16_t rsrc_id, rsrc_start, j, k; k 5995 drivers/scsi/lpfc/lpfc_sli.c for (i = 0, j = 0, k = 0; i < rsrc_cnt; i++) { k 5998 drivers/scsi/lpfc/lpfc_sli.c &id_array[k]); k 6001 drivers/scsi/lpfc/lpfc_sli.c &id_array[k]); k 6026 drivers/scsi/lpfc/lpfc_sli.c k++; k 739 drivers/scsi/megaraid/megaraid_sas_fusion.c int i, j, k, msix_count; k 837 drivers/scsi/megaraid/megaraid_sas_fusion.c for (k = 0; k < dma_alloc_count; k++) { k 839 drivers/scsi/megaraid/megaraid_sas_fusion.c abs_index = (k * RDPQ_MAX_INDEX_IN_ONE_CHUNK) + i; k 845 drivers/scsi/megaraid/megaraid_sas_fusion.c cpu_to_le64(rdpq_chunk_phys[k] + offset); k 847 drivers/scsi/megaraid/megaraid_sas_fusion.c rdpq_chunk_phys[k] + offset; k 849 drivers/scsi/megaraid/megaraid_sas_fusion.c (union MPI2_REPLY_DESCRIPTORS_UNION *)((u8 *)rdpq_chunk_virt[k] + offset); k 181 drivers/scsi/ppa.c int k; k 185 drivers/scsi/ppa.c k = PPA_SPIN_TMO; k 187 drivers/scsi/ppa.c for (r = r_str(ppb); ((r & 0xc0) != 0xc0) && (k); k--) { k 199 drivers/scsi/ppa.c if (k) k 421 drivers/scsi/ppa.c int k; k 428 drivers/scsi/ppa.c k = PPA_SELECT_TMO; k 430 drivers/scsi/ppa.c k--; k 432 drivers/scsi/ppa.c } while ((r_str(ppb) & 0x40) && (k)); k 433 drivers/scsi/ppa.c if (!k) k 442 drivers/scsi/ppa.c k = PPA_SELECT_TMO; k 444 drivers/scsi/ppa.c k--; k 447 drivers/scsi/ppa.c while (!(r_str(ppb) & 0x40) && (k)); k 448 drivers/scsi/ppa.c if (!k) k 496 drivers/scsi/ppa.c int k; k 500 drivers/scsi/ppa.c for (k = 0; k < cmd->cmd_len; k++) k 501 drivers/scsi/ppa.c if (!ppa_out(dev, &cmd->cmnd[k], 1)) k 565 drivers/scsi/ppa.c unsigned long k = dev->recon_tmo; k 566 drivers/scsi/ppa.c for (; k && ((r = (r_str(ppb) & 0xf0)) & 0xc0) != 0xc0; k 567 drivers/scsi/ppa.c k--) k 570 drivers/scsi/ppa.c if (!k) k 887 drivers/scsi/ppa.c int loop, old_mode, status, k, ppb = dev->base; k 929 drivers/scsi/ppa.c k = 1000000; /* 1 Second */ k 932 drivers/scsi/ppa.c k--; k 934 drivers/scsi/ppa.c } while (!(l & 0x80) && (k)); k 3595 drivers/scsi/qla2xxx/qla_gs.c int k; k 3605 drivers/scsi/qla2xxx/qla_gs.c for (k = i + 1; k < vha->hw->max_fibre_devices; k++) { k 3606 drivers/scsi/qla2xxx/qla_gs.c trp = &vha->scan.l[k]; k 3774 drivers/scsi/qla2xxx/qla_gs.c int i, j, k; k 3800 drivers/scsi/qla2xxx/qla_gs.c for (k = 0; k < num_fibre_dev; k++) { k 3801 drivers/scsi/qla2xxx/qla_gs.c rp = &vha->scan.l[k]; k 3814 drivers/scsi/qla2xxx/qla_gs.c for (k = 0; k < num_fibre_dev; k++) { k 3815 drivers/scsi/qla2xxx/qla_gs.c rp = &vha->scan.l[k]; k 3829 drivers/scsi/qla2xxx/qla_gs.c for (k = 0; k < num_fibre_dev; k++) { k 3830 drivers/scsi/qla2xxx/qla_gs.c rp = &vha->scan.l[k]; k 3844 drivers/scsi/qla2xxx/qla_gs.c for (k = 0; k < num_fibre_dev; k++) { k 3845 drivers/scsi/qla2xxx/qla_gs.c rp = &vha->scan.l[k]; k 2185 drivers/scsi/qla2xxx/qla_isr.c uint32_t i, j = 0, k = 0, num_ent; k 2193 drivers/scsi/qla2xxx/qla_isr.c if (k + num_ent < blocks_done) { k 2194 drivers/scsi/qla2xxx/qla_isr.c k += num_ent; k 2197 drivers/scsi/qla2xxx/qla_isr.c j = blocks_done - k - 1; k 2198 drivers/scsi/qla2xxx/qla_isr.c k = blocks_done; k 2202 drivers/scsi/qla2xxx/qla_isr.c if (k != blocks_done) { k 1472 drivers/scsi/qla2xxx/qla_nx.c int i, j = 0, k, start, end, loop, sz[2], off0[2]; k 1523 drivers/scsi/qla2xxx/qla_nx.c for (k = start; k <= end; k++) { k 1525 drivers/scsi/qla2xxx/qla_nx.c mem_crb + MIU_TEST_AGT_RDDATA(k)); k 1526 drivers/scsi/qla2xxx/qla_nx.c word[i] |= ((uint64_t)temp << (32 * (k & 1))); k 3919 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 3961 drivers/scsi/qla2xxx/qla_nx.c for (k = 0; k < r_cnt; k++) { k 3978 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 3997 drivers/scsi/qla2xxx/qla_nx.c for (k = 0; k < r_cnt; k++) { k 4014 drivers/scsi/qla2xxx/qla_nx.c uint32_t i, k, loop_cnt; k 4027 drivers/scsi/qla2xxx/qla_nx.c for (k = 0; k < r_cnt; k++) { k 4371 drivers/scsi/qla2xxx/qla_nx.c int i, k; k 4383 drivers/scsi/qla2xxx/qla_nx.c for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { k 4385 drivers/scsi/qla2xxx/qla_nx.c ha->md_dump_size += tmplt_hdr->capture_size_array[k]; k 2476 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 2517 drivers/scsi/qla2xxx/qla_nx2.c for (k = 0; k < r_cnt; k++) { k 2533 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 2552 drivers/scsi/qla2xxx/qla_nx2.c for (k = 0; k < r_cnt; k++) { k 2628 drivers/scsi/qla2xxx/qla_nx2.c uint32_t i, k, loop_cnt; k 2642 drivers/scsi/qla2xxx/qla_nx2.c for (k = 0; k < r_cnt; k++) { k 311 drivers/scsi/qla4xxx/ql4_init.c int hdr_entry_bit, k; k 378 drivers/scsi/qla4xxx/ql4_init.c for (hdr_entry_bit = 0x2, k = 1; (hdr_entry_bit & 0xFF); k 379 drivers/scsi/qla4xxx/ql4_init.c hdr_entry_bit <<= 1, k++) { k 381 drivers/scsi/qla4xxx/ql4_init.c ha->fw_dump_size += md_hdr->capture_size_array[k]; k 1369 drivers/scsi/qla4xxx/ql4_nx.c int i, j = 0, k, start, end, loop, sz[2], off0[2]; k 1422 drivers/scsi/qla4xxx/ql4_nx.c for (k = start; k <= end; k++) { k 1424 drivers/scsi/qla4xxx/ql4_nx.c mem_crb + MIU_TEST_AGT_RDDATA(k)); k 1425 drivers/scsi/qla4xxx/ql4_nx.c word[i] |= ((uint64_t)temp << (32 * (k & 1))); k 2151 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 2193 drivers/scsi/qla4xxx/ql4_nx.c for (k = 0; k < r_cnt; k++) { k 2381 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_count, t_value, r_cnt, r_value; k 2400 drivers/scsi/qla4xxx/ql4_nx.c for (k = 0; k < r_cnt; k++) { k 2416 drivers/scsi/qla4xxx/ql4_nx.c uint32_t i, k, loop_cnt; k 2430 drivers/scsi/qla4xxx/ql4_nx.c for (k = 0; k < r_cnt; k++) { k 183 drivers/scsi/qlogicfas408.c int k; k 187 drivers/scsi/qlogicfas408.c k = 0; k 190 drivers/scsi/qlogicfas408.c !((k = inb(qbase + 4)) & 0xe0)) { k 198 drivers/scsi/qlogicfas408.c if (k & 0x60) k 200 drivers/scsi/qlogicfas408.c if (k & 0x20) k 202 drivers/scsi/qlogicfas408.c if (k & 0x40) k 262 drivers/scsi/qlogicfas408.c unsigned long k; k 330 drivers/scsi/qlogicfas408.c if ((k = ql_wai(priv))) k 331 drivers/scsi/qlogicfas408.c return (k << 16); k 332 drivers/scsi/qlogicfas408.c k = inb(qbase + 5); /* should be 0x10, bus service */ k 339 drivers/scsi/qlogicfas408.c k = jiffies + WATCHDOG; k 341 drivers/scsi/qlogicfas408.c while (time_before(jiffies, k) && !priv->qabort && k 345 drivers/scsi/qlogicfas408.c if (time_after_eq(jiffies, k)) { k 358 drivers/scsi/qlogicfas408.c if ((k = ql_wai(priv))) k 359 drivers/scsi/qlogicfas408.c return (k << 16); k 375 drivers/scsi/qlogicfas408.c if ((k = ql_wai(priv))) k 376 drivers/scsi/qlogicfas408.c return (k << 16); k 199 drivers/scsi/scsi_common.c int add_sen_len, add_len, desc_len, k; k 209 drivers/scsi/scsi_common.c for (desc_len = 0, k = 0; k < add_sen_len; k += desc_len) { k 211 drivers/scsi/scsi_common.c add_len = (k < (add_sen_len - 1)) ? descp[1]: -1; k 923 drivers/scsi/scsi_debug.c int k; k 925 drivers/scsi/scsi_debug.c k = find_first_bit(devip->uas_bm, SDEBUG_NUM_UAS); k 926 drivers/scsi/scsi_debug.c if (k != SDEBUG_NUM_UAS) { k 929 drivers/scsi/scsi_debug.c switch (k) { k 986 drivers/scsi/scsi_debug.c pr_warn("unexpected unit attention code=%d\n", k); k 991 drivers/scsi/scsi_debug.c clear_bit(k, devip->uas_bm); k 1778 drivers/scsi/scsi_debug.c int k, offset, len, errsts, count, bump, na; k 1829 drivers/scsi/scsi_debug.c for (k = 0, oip = oip->arrp; k < na; ++k, ++oip) { k 1877 drivers/scsi/scsi_debug.c for (k = 0, oip = oip->arrp; k < na; k 1878 drivers/scsi/scsi_debug.c ++k, ++oip) { k 1882 drivers/scsi/scsi_debug.c supp = (k >= na) ? 1 : 3; k 1885 drivers/scsi/scsi_debug.c for (k = 0, oip = oip->arrp; k < na; k 1886 drivers/scsi/scsi_debug.c ++k, ++oip) { k 1890 drivers/scsi/scsi_debug.c supp = (k >= na) ? 1 : 3; k 1897 drivers/scsi/scsi_debug.c for (k = 1; k < u; ++k) k 1898 drivers/scsi/scsi_debug.c arr[4 + k] = (k < 16) ? k 1899 drivers/scsi/scsi_debug.c oip->len_mask[k] : 0xff; k 3088 drivers/scsi/scsi_debug.c u16 lbdof, num_lrd, k; k 3159 drivers/scsi/scsi_debug.c for (k = 0, up = lrdp + lrd_size; k < num_lrd; ++k, up += lrd_size) { k 3165 drivers/scsi/scsi_debug.c my_name, __func__, k, lba, num, sg_off); k 3618 drivers/scsi/scsi_debug.c int k, j, n, res; k 3666 drivers/scsi/scsi_debug.c for (k = 0, j = 0, res = 0; true; ++k, j = 0) { k 3669 drivers/scsi/scsi_debug.c if (k == 0) { k 3675 drivers/scsi/scsi_debug.c if ((k * RL_BUCKET_ELEMS) + j > lun_cnt) k 3758 drivers/scsi/scsi_debug.c int k, retval; k 3766 drivers/scsi/scsi_debug.c k = find_last_bit(sqp->in_use_bm, retval); k 3767 drivers/scsi/scsi_debug.c if ((k < sdebug_max_queue) || (k == retval)) k 3770 drivers/scsi/scsi_debug.c atomic_set(&retired_max_queue, k + 1); k 3925 drivers/scsi/scsi_debug.c int j, k, qmax, r_qmax; k 3938 drivers/scsi/scsi_debug.c for (k = 0; k < qmax; ++k) { k 3939 drivers/scsi/scsi_debug.c if (test_bit(k, sqp->in_use_bm)) { k 3940 drivers/scsi/scsi_debug.c sqcp = &sqp->qc_arr[k]; k 3957 drivers/scsi/scsi_debug.c clear_bit(k, sqp->in_use_bm); k 3970 drivers/scsi/scsi_debug.c int j, k; k 3979 drivers/scsi/scsi_debug.c for (k = 0; k < SDEBUG_CANQUEUE; ++k) { k 3980 drivers/scsi/scsi_debug.c if (test_bit(k, sqp->in_use_bm)) { k 3981 drivers/scsi/scsi_debug.c sqcp = &sqp->qc_arr[k]; k 3997 drivers/scsi/scsi_debug.c clear_bit(k, sqp->in_use_bm); k 4008 drivers/scsi/scsi_debug.c int j, k; k 4013 drivers/scsi/scsi_debug.c for (k = 0; k < SDEBUG_CANQUEUE; ++k) { k 4014 drivers/scsi/scsi_debug.c sqcp = &sqp->qc_arr[k]; k 4058 drivers/scsi/scsi_debug.c int k = 0; k 4078 drivers/scsi/scsi_debug.c ++k; k 4083 drivers/scsi/scsi_debug.c "%s: %d device(s) found in target\n", __func__, k); k 4094 drivers/scsi/scsi_debug.c int k = 0; k 4110 drivers/scsi/scsi_debug.c ++k; k 4116 drivers/scsi/scsi_debug.c "%s: %d device(s) found in host\n", __func__, k); k 4125 drivers/scsi/scsi_debug.c int k = 0; k 4135 drivers/scsi/scsi_debug.c ++k; k 4142 drivers/scsi/scsi_debug.c "%s: %d device(s) found\n", __func__, k); k 4151 drivers/scsi/scsi_debug.c int sectors_per_part, num_sectors, k; k 4166 drivers/scsi/scsi_debug.c for (k = 1; k < sdebug_num_parts; ++k) k 4167 drivers/scsi/scsi_debug.c starts[k] = ((k * sectors_per_part) / heads_by_sects) k 4175 drivers/scsi/scsi_debug.c for (k = 0; starts[k + 1]; ++k, ++pp) { k 4176 drivers/scsi/scsi_debug.c start_sec = starts[k]; k 4177 drivers/scsi/scsi_debug.c end_sec = starts[k + 1] - 1; k 4261 drivers/scsi/scsi_debug.c int k, num_in_q, qdepth, inject; k 4305 drivers/scsi/scsi_debug.c k = find_first_zero_bit(sqp->in_use_bm, sdebug_max_queue); k 4306 drivers/scsi/scsi_debug.c if (unlikely(k >= sdebug_max_queue)) { k 4323 drivers/scsi/scsi_debug.c __set_bit(k, sqp->in_use_bm); k 4325 drivers/scsi/scsi_debug.c sqcp = &sqp->qc_arr[k]; k 4367 drivers/scsi/scsi_debug.c sd_dp->qc_idx = k; k 4378 drivers/scsi/scsi_debug.c sd_dp->qc_idx = k; k 4536 drivers/scsi/scsi_debug.c int k; k 4538 drivers/scsi/scsi_debug.c k = scnprintf(sdebug_info, SDEBUG_INFO_LEN, "%s: version %s [%s]\n", k 4540 drivers/scsi/scsi_debug.c if (k >= (SDEBUG_INFO_LEN - 1)) k 4542 drivers/scsi/scsi_debug.c scnprintf(sdebug_info + k, SDEBUG_INFO_LEN - k, k 4631 drivers/scsi/scsi_debug.c int j, k; k 4637 drivers/scsi/scsi_debug.c k = find_first_bit(sqp->in_use_bm, k 4639 drivers/scsi/scsi_debug.c if (k != sdebug_max_queue) { k 4671 drivers/scsi/scsi_debug.c int j, k; k 4677 drivers/scsi/scsi_debug.c k = find_first_bit(sqp->in_use_bm, k 4679 drivers/scsi/scsi_debug.c if (k != sdebug_max_queue) { k 4910 drivers/scsi/scsi_debug.c int j, n, k, a; k 4916 drivers/scsi/scsi_debug.c k = 0; k 4920 drivers/scsi/scsi_debug.c if (a > k) k 4921 drivers/scsi/scsi_debug.c k = a; k 4924 drivers/scsi/scsi_debug.c if (k == SDEBUG_CANQUEUE) k 4926 drivers/scsi/scsi_debug.c else if (k >= n) k 4927 drivers/scsi/scsi_debug.c atomic_set(&retired_max_queue, k + 1); k 5230 drivers/scsi/scsi_debug.c int k; k 5303 drivers/scsi/scsi_debug.c for (k = 0; k < submit_queues; ++k) k 5304 drivers/scsi/scsi_debug.c spin_lock_init(&sdebug_q_arr[k].qc_lock); k 5415 drivers/scsi/scsi_debug.c for (k = 0; k < host_to_add; k++) { k 5417 drivers/scsi/scsi_debug.c pr_err("sdebug_add_adapter failed k=%d\n", k); k 5442 drivers/scsi/scsi_debug.c int k = sdebug_add_host; k 5445 drivers/scsi/scsi_debug.c for (; k; k--) k 5471 drivers/scsi/scsi_debug.c int k, devs_per_host; k 5485 drivers/scsi/scsi_debug.c for (k = 0; k < devs_per_host; k++) { k 5600 drivers/scsi/scsi_debug.c int k, na; k 5620 drivers/scsi/scsi_debug.c for (k = 0, n = 0; k < len && n < sb; ++k) k 5622 drivers/scsi/scsi_debug.c (u32)cmd[k]); k 5650 drivers/scsi/scsi_debug.c for (k = 0; k <= na; oip = r_oip->arrp + k++) { k 5655 drivers/scsi/scsi_debug.c for (k = 0; k <= na; oip = r_oip->arrp + k++) { k 5660 drivers/scsi/scsi_debug.c if (k > na) { k 5686 drivers/scsi/scsi_debug.c for (k = 1; k < oip->len_mask[0] && k < 16; ++k) { k 5687 drivers/scsi/scsi_debug.c rem = ~oip->len_mask[k] & cmd[k]; k 5693 drivers/scsi/scsi_debug.c mk_sense_invalid_fld(scp, SDEB_IN_CDB, k, j); k 157 drivers/scsi/scsi_logging.c int len, k; k 167 drivers/scsi/scsi_logging.c for (k = 0; k < len; ++k) { k 171 drivers/scsi/scsi_logging.c " %02x", cdb[k]); k 179 drivers/scsi/scsi_logging.c int k; k 209 drivers/scsi/scsi_logging.c for (k = 0; k < cmd->cmd_len; k += 16) { k 210 drivers/scsi/scsi_logging.c size_t linelen = min(cmd->cmd_len - k, 16); k 220 drivers/scsi/scsi_logging.c "CDB[%02x]: ", k); k 221 drivers/scsi/scsi_logging.c hex_dump_to_buffer(&cmd->cmnd[k], linelen, k 627 drivers/scsi/scsi_transport_spi.c int j, k, r, result; k 645 drivers/scsi/scsi_transport_spi.c k = j; k 648 drivers/scsi/scsi_transport_spi.c for ( ; j < min(len, k + 32); j += 2) { k 653 drivers/scsi/scsi_transport_spi.c k = j; k 656 drivers/scsi/scsi_transport_spi.c for ( ; j < min(len, k + 32); j += 2) { k 661 drivers/scsi/scsi_transport_spi.c k = j; k 663 drivers/scsi/scsi_transport_spi.c for ( ; j < min(len, k + 32); j += 4) { k 605 drivers/scsi/sg.c int mxsize, cmd_size, k; k 711 drivers/scsi/sg.c k = sg_common_write(sfp, srp, cmnd, sfp->timeout, blocking); k 712 drivers/scsi/sg.c return (k < 0) ? k : count; k 720 drivers/scsi/sg.c int k; k 780 drivers/scsi/sg.c k = sg_common_write(sfp, srp, cmnd, timeout, blocking); k 781 drivers/scsi/sg.c if (k < 0) k 782 drivers/scsi/sg.c return k; k 792 drivers/scsi/sg.c int k, at_head; k 813 drivers/scsi/sg.c k = sg_start_req(srp, cmnd); k 814 drivers/scsi/sg.c if (k) { k 816 drivers/scsi/sg.c "sg_common_write: start_req err=%d\n", k)); k 819 drivers/scsi/sg.c return k; /* probably out of space --> ENOMEM */ k 1229 drivers/scsi/sg.c int k, length; k 1242 drivers/scsi/sg.c for (k = 0; k < rsv_schp->k_use_sg && sa < vma->vm_end; k++) { k 1246 drivers/scsi/sg.c struct page *page = nth_page(rsv_schp->pages[k], k 1269 drivers/scsi/sg.c int k, length; k 1289 drivers/scsi/sg.c for (k = 0; k < rsv_schp->k_use_sg && sa < vma->vm_end; k++) { k 1444 drivers/scsi/sg.c u32 k; k 1470 drivers/scsi/sg.c k = error; k 1473 drivers/scsi/sg.c "sg_alloc: dev=%d \n", k)); k 1474 drivers/scsi/sg.c sprintf(disk->disk_name, "sg%d", k); k 1475 drivers/scsi/sg.c disk->first_minor = k; k 1484 drivers/scsi/sg.c sdp->index = k; k 1874 drivers/scsi/sg.c int ret_sz = 0, i, k, rem_sz, num, mx_sc_elems; k 1911 drivers/scsi/sg.c for (k = 0, rem_sz = blk_size; rem_sz > 0 && k < mx_sc_elems; k 1912 drivers/scsi/sg.c k++, rem_sz -= ret_sz) { k 1917 drivers/scsi/sg.c schp->pages[k] = alloc_pages(gfp_mask, order); k 1918 drivers/scsi/sg.c if (!schp->pages[k]) k 1930 drivers/scsi/sg.c k, num, ret_sz)); k 1934 drivers/scsi/sg.c schp->k_use_sg = k; k 1937 drivers/scsi/sg.c k, rem_sz)); k 1944 drivers/scsi/sg.c for (i = 0; i < k; i++) k 1960 drivers/scsi/sg.c int k; k 1962 drivers/scsi/sg.c for (k = 0; k < schp->k_use_sg && schp->pages[k]; k++) { k 1966 drivers/scsi/sg.c k, schp->pages[k])); k 1967 drivers/scsi/sg.c __free_pages(schp->pages[k], schp->page_order); k 1980 drivers/scsi/sg.c int k, num; k 1989 drivers/scsi/sg.c for (k = 0; k < schp->k_use_sg && schp->pages[k]; k++) { k 1991 drivers/scsi/sg.c if (__copy_to_user(outp, page_address(schp->pages[k]), k 1996 drivers/scsi/sg.c if (__copy_to_user(outp, page_address(schp->pages[k]), k 2032 drivers/scsi/sg.c int k, num, rem; k 2040 drivers/scsi/sg.c for (k = 0; k < rsv_schp->k_use_sg; k++) { k 2042 drivers/scsi/sg.c req_schp->k_use_sg = k + 1; k 2053 drivers/scsi/sg.c if (k >= rsv_schp->k_use_sg) k 2100 drivers/scsi/sg.c int k; k 2109 drivers/scsi/sg.c for (k = 0; k < SG_MAX_QUEUE; ++k, ++rp) { k 2113 drivers/scsi/sg.c if (k >= SG_MAX_QUEUE) k 2248 drivers/scsi/sg.c int *k = data; k 2250 drivers/scsi/sg.c if (*k < id) k 2251 drivers/scsi/sg.c *k = id; k 2259 drivers/scsi/sg.c int k = -1; k 2263 drivers/scsi/sg.c idr_for_each(&sg_index_idr, sg_idr_max_id, &k); k 2265 drivers/scsi/sg.c return k + 1; /* origin 1 */ k 2410 drivers/scsi/sg.c unsigned long k = ULONG_MAX; k 2415 drivers/scsi/sg.c err = kstrtoul_from_user(buffer, count, 0, &k); k 2418 drivers/scsi/sg.c if (k <= 1048576) { /* limit "big buff" to 1 MB */ k 2419 drivers/scsi/sg.c sg_big_buff = k; k 2519 drivers/scsi/sg.c int k, new_interface, blen, usg; k 2526 drivers/scsi/sg.c k = 0; k 2528 drivers/scsi/sg.c k++; k 2531 drivers/scsi/sg.c "(res)sgat=%d low_dma=%d\n", k, k 3276 drivers/scsi/sym53c8xx_2/sym_hipd.c int i, k; k 3297 drivers/scsi/sym53c8xx_2/sym_hipd.c for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { k 3298 drivers/scsi/sym53c8xx_2/sym_hipd.c if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { k 3433 drivers/scsi/sym53c8xx_2/sym_hipd.c for (k = 1 ; k < SYM_CONF_MAX_LUN ; k++) { k 3434 drivers/scsi/sym53c8xx_2/sym_hipd.c if (tp->lunmp[k] && tp->lunmp[k]->to_clear) { k 3435 drivers/scsi/sym53c8xx_2/sym_hipd.c lun = k; k 98 drivers/sh/clk/cpg.c int k; k 100 drivers/sh/clk/cpg.c for (k = 0; !ret && (k < nr); k++) { k 101 drivers/sh/clk/cpg.c clkp = clks + k; k 249 drivers/sh/clk/cpg.c int k; k 258 drivers/sh/clk/cpg.c for (k = 0; !ret && (k < nr); k++) { k 259 drivers/sh/clk/cpg.c clkp = clks + k; k 264 drivers/sh/clk/cpg.c clkp->freq_table = freq_table + (k * freq_table_size); k 17 drivers/sh/intc/access.c int k; k 20 drivers/sh/intc/access.c for (k = 0; k < d->nr_windows; k++) { k 21 drivers/sh/intc/access.c window = d->window + k; k 41 drivers/sh/intc/access.c unsigned int k; k 45 drivers/sh/intc/access.c for (k = 0; k < d->nr_reg; k++) { k 46 drivers/sh/intc/access.c if (d->reg[k] == address) k 47 drivers/sh/intc/access.c return k; k 184 drivers/sh/intc/core.c unsigned int i, k, smp; k 211 drivers/sh/intc/core.c for (k = 0; k < d->nr_windows; k++) { k 212 drivers/sh/intc/core.c res = desc->resource + k; k 214 drivers/sh/intc/core.c d->window[k].phys = res->start; k 215 drivers/sh/intc/core.c d->window[k].size = resource_size(res); k 216 drivers/sh/intc/core.c d->window[k].virt = ioremap_nocache(res->start, k 218 drivers/sh/intc/core.c if (!d->window[k].virt) k 242 drivers/sh/intc/core.c k = 0; k 247 drivers/sh/intc/core.c k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); k 248 drivers/sh/intc/core.c k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); k 250 drivers/sh/intc/core.c k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); k 263 drivers/sh/intc/core.c k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); k 264 drivers/sh/intc/core.c k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); k 278 drivers/sh/intc/core.c k += save_reg(d, k, hw->sense_regs[i].reg, 0); k 287 drivers/sh/intc/core.c k+= save_reg(d, k, hw->subgroups[i].reg, 0); k 294 drivers/sh/intc/core.c k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); k 306 drivers/sh/intc/core.c BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ k 336 drivers/sh/intc/core.c for (k = i + 1; k < hw->nr_vectors; k++) { k 337 drivers/sh/intc/core.c struct intc_vect *vect2 = hw->vectors + k; k 395 drivers/sh/intc/core.c for (k = 0; k < d->nr_windows; k++) k 396 drivers/sh/intc/core.c if (d->window[k].virt) k 397 drivers/sh/intc/core.c iounmap(d->window[k].virt); k 494 drivers/sh/maple/maple.c int retval, k, devcheck; k 499 drivers/sh/maple/maple.c for (k = 0; k < 5; k++) { k 500 drivers/sh/maple/maple.c ds.unit = k + 1; k 510 drivers/sh/maple/maple.c mdev_add = maple_alloc_dev(mdev->port, k + 1); k 395 drivers/soc/fsl/qbman/qman_ccsr.c static void qm_set_pfdr_threshold(u32 th, u8 k) k 398 drivers/soc/fsl/qbman/qman_ccsr.c qm_ccsr_out(REG_PFDR_CFG, k); k 111 drivers/soc/fsl/qbman/qman_test_stash.c struct task_struct *k = kthread_create(bstrap_fn, &bstrap, k 115 drivers/soc/fsl/qbman/qman_test_stash.c if (IS_ERR(k)) k 117 drivers/soc/fsl/qbman/qman_test_stash.c kthread_bind(k, cpu); k 118 drivers/soc/fsl/qbman/qman_test_stash.c wake_up_process(k); k 127 drivers/soc/fsl/qbman/qman_test_stash.c ret = kthread_stop(k); k 315 drivers/soc/qcom/rpmh-rsc.c int i, j, k; k 326 drivers/soc/qcom/rpmh-rsc.c for (k = 0; k < msg->num_cmds; k++) { k 327 drivers/soc/qcom/rpmh-rsc.c if (addr == msg->cmds[k].addr) k 70 drivers/soc/renesas/rcar-sysc.c int k; k 81 drivers/soc/renesas/rcar-sysc.c for (k = 0; k < SYSCSR_RETRIES; k++) { k 87 drivers/soc/renesas/rcar-sysc.c if (k == SYSCSR_RETRIES) k 104 drivers/soc/renesas/rcar-sysc.c int k; k 120 drivers/soc/renesas/rcar-sysc.c for (k = 0; k < PWRER_RETRIES; k++) { k 133 drivers/soc/renesas/rcar-sysc.c if (k == PWRER_RETRIES) { k 139 drivers/soc/renesas/rcar-sysc.c for (k = 0; k < SYSCISR_RETRIES; k++) { k 145 drivers/soc/renesas/rcar-sysc.c if (k == SYSCISR_RETRIES) k 414 drivers/spi/spi-sh-msiof.c int k; k 416 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 417 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, buf_8[k] << fs); k 424 drivers/spi/spi-sh-msiof.c int k; k 426 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 427 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, buf_16[k] << fs); k 434 drivers/spi/spi-sh-msiof.c int k; k 436 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 437 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); k 444 drivers/spi/spi-sh-msiof.c int k; k 446 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 447 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, buf_32[k] << fs); k 454 drivers/spi/spi-sh-msiof.c int k; k 456 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 457 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); k 464 drivers/spi/spi-sh-msiof.c int k; k 466 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 467 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); k 474 drivers/spi/spi-sh-msiof.c int k; k 476 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 477 drivers/spi/spi-sh-msiof.c sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); k 484 drivers/spi/spi-sh-msiof.c int k; k 486 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 487 drivers/spi/spi-sh-msiof.c buf_8[k] = sh_msiof_read(p, RFDR) >> fs; k 494 drivers/spi/spi-sh-msiof.c int k; k 496 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 497 drivers/spi/spi-sh-msiof.c buf_16[k] = sh_msiof_read(p, RFDR) >> fs; k 504 drivers/spi/spi-sh-msiof.c int k; k 506 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 507 drivers/spi/spi-sh-msiof.c put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); k 514 drivers/spi/spi-sh-msiof.c int k; k 516 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 517 drivers/spi/spi-sh-msiof.c buf_32[k] = sh_msiof_read(p, RFDR) >> fs; k 524 drivers/spi/spi-sh-msiof.c int k; k 526 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 527 drivers/spi/spi-sh-msiof.c put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); k 534 drivers/spi/spi-sh-msiof.c int k; k 536 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 537 drivers/spi/spi-sh-msiof.c buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); k 544 drivers/spi/spi-sh-msiof.c int k; k 546 drivers/spi/spi-sh-msiof.c for (k = 0; k < words; k++) k 547 drivers/spi/spi-sh-msiof.c put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); k 391 drivers/spi/spi-zynq-qspi.c int count, len, k; k 414 drivers/spi/spi-zynq-qspi.c for (k = 0; k < count; k++) k 429 drivers/spi/spi-zynq-qspi.c int count, len, k; k 440 drivers/spi/spi-zynq-qspi.c for (k = 0; k < count; k++) k 627 drivers/staging/comedi/drivers/jr3_pci.c int k; k 640 drivers/staging/comedi/drivers/jr3_pci.c for (k = 0; k < 7; k++) { k 641 drivers/staging/comedi/drivers/jr3_pci.c spriv->range_table_list[j + k * 8] = &spriv->range[j].l; k 642 drivers/staging/comedi/drivers/jr3_pci.c spriv->maxdata_list[j + k * 8] = 0x7fff; k 469 drivers/staging/exfat/exfat_core.c u8 k; k 476 drivers/staging/exfat/exfat_core.c k = *(((u8 *)p_fs->vol_amap[map_i]->b_data) + map_b); k 477 drivers/staging/exfat/exfat_core.c count += used_bit[k]; k 647 drivers/staging/exfat/exfat_core.c u8 k, clu_mask; k 658 drivers/staging/exfat/exfat_core.c k = *(((u8 *)p_fs->vol_amap[map_i]->b_data) + map_b); k 660 drivers/staging/exfat/exfat_core.c k |= clu_mask; k 663 drivers/staging/exfat/exfat_core.c if (k < 0xFF) { k 664 drivers/staging/exfat/exfat_core.c clu_free = clu_base + free_bit[k]; k 139 drivers/staging/fwserial/fwserial.c int k = 4; k 144 drivers/staging/fwserial/fwserial.c snprintf(t, 10, "< %d", 1 << k); k 146 drivers/staging/fwserial/fwserial.c for (j = k + 1; j < DISTRIBUTION_MAX_INDEX; ++j) k 149 drivers/staging/fwserial/fwserial.c ++k; k 150 drivers/staging/fwserial/fwserial.c for (j = 0, sum = 0; j <= k; ++j) k 153 drivers/staging/fwserial/fwserial.c for (j = k + 1; j <= DISTRIBUTION_MAX_INDEX; ++j) k 156 drivers/staging/fwserial/fwserial.c for (j = 0, sum = 0; j <= k; ++j) k 159 drivers/staging/fwserial/fwserial.c for (j = k + 1; j <= DISTRIBUTION_MAX_INDEX; ++j) k 162 drivers/staging/fwserial/fwserial.c for (j = 0, sum = 0; j <= k; ++j) k 165 drivers/staging/fwserial/fwserial.c for (j = k + 1; j <= DISTRIBUTION_MAX_INDEX; ++j) k 168 drivers/staging/fwserial/fwserial.c for (j = 0, sum = 0; j <= k; ++j) k 171 drivers/staging/fwserial/fwserial.c for (j = k + 1; j <= DISTRIBUTION_MAX_INDEX; ++j) k 504 drivers/staging/greybus/audio_topology.c struct snd_kcontrol *k, int event) k 512 drivers/staging/greybus/audio_topology.c struct snd_kcontrol *k, int event) k 520 drivers/staging/greybus/audio_topology.c struct snd_kcontrol *k, int event) k 961 drivers/staging/isdn/gigaset/bas-gigaset.c int j, k; k 970 drivers/staging/isdn/gigaset/bas-gigaset.c for (k = 0; k < BAS_INURBS; k++) { k 971 drivers/staging/isdn/gigaset/bas-gigaset.c urb = ubc->isoinurbs[k]; k 978 drivers/staging/isdn/gigaset/bas-gigaset.c ubc->isoinbuf + k * BAS_INBUFSIZE, k 1001 drivers/staging/isdn/gigaset/bas-gigaset.c for (k = 0; k < BAS_OUTURBS; ++k) { k 1002 drivers/staging/isdn/gigaset/bas-gigaset.c urb = ubc->isoouturbs[k].urb; k 1011 drivers/staging/isdn/gigaset/bas-gigaset.c write_iso_callback, &ubc->isoouturbs[k], k 1022 drivers/staging/isdn/gigaset/bas-gigaset.c ubc->isoouturbs[k].limit = -1; k 1026 drivers/staging/isdn/gigaset/bas-gigaset.c for (k = 0; k < BAS_OUTURBS - 1; ++k) { k 1028 drivers/staging/isdn/gigaset/bas-gigaset.c rc = usb_submit_urb(ubc->isoouturbs[k].urb, GFP_ATOMIC); k 1049 drivers/staging/isdn/gigaset/bas-gigaset.c int k, rc; k 1053 drivers/staging/isdn/gigaset/bas-gigaset.c for (k = 0; k < BAS_INURBS; ++k) { k 1054 drivers/staging/isdn/gigaset/bas-gigaset.c rc = usb_unlink_urb(ubc->isoinurbs[k]); k 1057 drivers/staging/isdn/gigaset/bas-gigaset.c __func__, k, get_usb_rcmsg(rc)); k 1060 drivers/staging/isdn/gigaset/bas-gigaset.c for (k = 0; k < BAS_OUTURBS; ++k) { k 1061 drivers/staging/isdn/gigaset/bas-gigaset.c rc = usb_unlink_urb(ubc->isoouturbs[k].urb); k 1064 drivers/staging/isdn/gigaset/bas-gigaset.c __func__, k, get_usb_rcmsg(rc)); k 908 drivers/staging/ks7010/ks_wlan_net.c int i, k; k 922 drivers/staging/ks7010/ks_wlan_net.c k = 0; k 924 drivers/staging/ks7010/ks_wlan_net.c range->freq[k].i = i + 1; /* List index */ k 925 drivers/staging/ks7010/ks_wlan_net.c range->freq[k].m = frequency_list[i] * 100000; k 926 drivers/staging/ks7010/ks_wlan_net.c range->freq[k++].e = 1; /* Values in table in MHz -> * 10^5 * 10 */ k 928 drivers/staging/ks7010/ks_wlan_net.c range->num_frequency = k; k 53 drivers/staging/media/hantro/hantro_vp8.c u32 i, j, k; k 115 drivers/staging/media/hantro/hantro_vp8.c for (k = 0; k < 3; ++k) { k 116 drivers/staging/media/hantro/hantro_vp8.c dst[0] = entropy->coeff_probs[i][j][k][0]; k 117 drivers/staging/media/hantro/hantro_vp8.c dst[1] = entropy->coeff_probs[i][j][k][1]; k 118 drivers/staging/media/hantro/hantro_vp8.c dst[2] = entropy->coeff_probs[i][j][k][2]; k 119 drivers/staging/media/hantro/hantro_vp8.c dst[3] = entropy->coeff_probs[i][j][k][3]; k 130 drivers/staging/media/hantro/hantro_vp8.c for (k = 0; k < 3; ++k) { k 131 drivers/staging/media/hantro/hantro_vp8.c dst[0] = entropy->coeff_probs[i][j][k][4]; k 132 drivers/staging/media/hantro/hantro_vp8.c dst[1] = entropy->coeff_probs[i][j][k][5]; k 133 drivers/staging/media/hantro/hantro_vp8.c dst[2] = entropy->coeff_probs[i][j][k][6]; k 134 drivers/staging/media/hantro/hantro_vp8.c dst[3] = entropy->coeff_probs[i][j][k][7]; k 135 drivers/staging/media/hantro/hantro_vp8.c dst[4] = entropy->coeff_probs[i][j][k][8]; k 136 drivers/staging/media/hantro/hantro_vp8.c dst[5] = entropy->coeff_probs[i][j][k][9]; k 137 drivers/staging/media/hantro/hantro_vp8.c dst[6] = entropy->coeff_probs[i][j][k][10]; k 110 drivers/staging/media/ipu3/ipu3.c unsigned int i, k, node; k 143 drivers/staging/media/ipu3/ipu3.c for (k = 0; k < IMGU_MAX_QUEUE_DEPTH; k++) k 144 drivers/staging/media/ipu3/ipu3.c imgu_css_buf_init(&imgu_pipe->queues[i].dummybufs[k], i, k 263 drivers/staging/media/sunxi/cedrus/cedrus_h264.c int i, j, k; k 285 drivers/staging/media/sunxi/cedrus/cedrus_h264.c for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { k 288 drivers/staging/media/sunxi/cedrus/cedrus_h264.c val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | k 289 drivers/staging/media/sunxi/cedrus/cedrus_h264.c (factors->chroma_weight[j][k] & 0x1ff); k 236 drivers/staging/media/tegra-vde/vde.c unsigned int i, k; k 271 drivers/staging/media/tegra-vde/vde.c for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) { k 272 drivers/staging/media/tegra-vde/vde.c frame = &dpb_frames[k + 1]; k 276 drivers/staging/media/tegra-vde/vde.c value = (k + 1) << 26; k 284 drivers/staging/media/tegra-vde/vde.c for (k = 0; i < ref_frames_nb; i++, k++) { k 285 drivers/staging/media/tegra-vde/vde.c frame = &dpb_frames[k + 1]; k 289 drivers/staging/media/tegra-vde/vde.c value = (k + 1) << 26; k 523 drivers/staging/netlogic/xlr_net.c int b1, b2, c1, c2, i, j, k; k 541 drivers/staging/netlogic/xlr_net.c k = 0; k 553 drivers/staging/netlogic/xlr_net.c b1 = bkts[k]; k 554 drivers/staging/netlogic/xlr_net.c k = (k + 1) % j; k 555 drivers/staging/netlogic/xlr_net.c b2 = bkts[k]; k 556 drivers/staging/netlogic/xlr_net.c k = (k + 1) % j; k 1797 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c int j, k = 0; k 1799 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c InfoContent[k] = i; k 1801 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 1805 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c if (k < 16) { k 1806 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c InfoContent[k] = j; /* channel number */ k 1808 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 1813 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &pattrib->pktlen); k 2377 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c u8 j, k; k 2415 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k = 0; k 2427 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 2428 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 2431 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 2433 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 2434 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 2436 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 2438 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 2439 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 2441 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 2449 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 2450 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 2452 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 2457 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 2458 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 2460 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 2467 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 2468 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c chplan_new[k].ScanType = chplan_sta[i].ScanType; k 2470 drivers/staging/rtl8188eu/core/rtw_mlme_ext.c k++; k 93 drivers/staging/rtl8188eu/core/rtw_security.c u8 k; k 101 drivers/staging/rtl8188eu/core/rtw_security.c k = crc32_reverseBit((u8)i); k 102 drivers/staging/rtl8188eu/core/rtw_security.c for (c = ((u32)k) << 24, j = 8; j > 0; --j) k 624 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c int i = 0, j = 0, k = 0; k 684 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c for (k = 0; k < 5; k++) { k 685 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c if (k != 4) k 686 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c tmp_report[k] = rtl92e_readb(dev, k 687 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c Tssi_Report_Value1+k); k 689 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c tmp_report[k] = rtl92e_readb(dev, k 694 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c tmp_report[k]); k 696 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c if (tmp_report[k] <= 20) { k 707 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c for (k = 0; k < 5; k++) k 708 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c tmp_report[k] = 0; k 712 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c for (k = 0; k < 5; k++) k 713 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c Avg_TSSI_Meas_from_driver += tmp_report[k]; k 813 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c for (k = 0; k < 5; k++) k 814 drivers/staging/rtl8192e/rtl8192e/rtl_dm.c tmp_report[k] = 0; k 499 drivers/staging/rtl8192u/r8192U_dm.c int i = 0, j = 0, k = 0; k 540 drivers/staging/rtl8192u/r8192U_dm.c for (k = 0; k < 5; k++) { k 541 drivers/staging/rtl8192u/r8192U_dm.c if (k != 4) k 542 drivers/staging/rtl8192u/r8192U_dm.c read_nic_byte(dev, 0x134+k, &tmp_report[k]); k 544 drivers/staging/rtl8192u/r8192U_dm.c read_nic_byte(dev, 0x13e, &tmp_report[k]); k 545 drivers/staging/rtl8192u/r8192U_dm.c RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]); k 549 drivers/staging/rtl8192u/r8192U_dm.c for (k = 0; k < 5; k++) { k 550 drivers/staging/rtl8192u/r8192U_dm.c if (tmp_report[k] <= 20) { k 559 drivers/staging/rtl8192u/r8192U_dm.c for (k = 0; k < 5; k++) k 560 drivers/staging/rtl8192u/r8192U_dm.c tmp_report[k] = 0; k 564 drivers/staging/rtl8192u/r8192U_dm.c for (k = 0; k < 5; k++) k 565 drivers/staging/rtl8192u/r8192U_dm.c Avg_TSSI_Meas_from_driver += tmp_report[k]; k 639 drivers/staging/rtl8192u/r8192U_dm.c for (k = 0; k < 5; k++) k 640 drivers/staging/rtl8192u/r8192U_dm.c tmp_report[k] = 0; k 117 drivers/staging/rtl8712/rtl871x_security.c u8 k; k 123 drivers/staging/rtl8712/rtl871x_security.c k = crc32_reverseBit((u8)i); k 124 drivers/staging/rtl8712/rtl871x_security.c for (c = ((u32)k) << 24, j = 8; j > 0; --j) k 223 drivers/staging/rtl8723bs/core/rtw_efuse.c u32 k = 0; k 246 drivers/staging/rtl8723bs/core/rtw_efuse.c k++; k 247 drivers/staging/rtl8723bs/core/rtw_efuse.c if (k == 1000) { k 248 drivers/staging/rtl8723bs/core/rtw_efuse.c k = 0; k 4148 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c int j, k = 0; k 4150 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c InfoContent[k] = i; k 4152 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4156 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c if (k < 16) { k 4157 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c InfoContent[k] = j; /* channel number */ k 4159 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4164 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); k 4784 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c u8 j, k; k 4843 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c i = j = k = 0; k 4855 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4856 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4859 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4861 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4863 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 4865 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4867 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4868 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4870 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4879 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4881 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 4883 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4888 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4889 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4891 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4898 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4899 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = chplan_sta[i].ScanType; k 4901 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4920 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4921 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4924 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4926 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4928 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 4930 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4932 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4933 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4935 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4941 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4943 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_PASSIVE; k 4945 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4950 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_ap.Channel[j]; k 4951 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = SCAN_ACTIVE; k 4953 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4958 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; k 4959 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c chplan_new[k].ScanType = chplan_sta[i].ScanType; k 4961 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 4968 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k = 0; k 4970 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) { k 4971 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c DBG_871X("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType == SCAN_PASSIVE?'p':'c'); k 4972 drivers/staging/rtl8723bs/core/rtw_mlme_ext.c k++; k 173 drivers/staging/rtl8723bs/core/rtw_security.c u8 k; k 178 drivers/staging/rtl8723bs/core/rtw_security.c k = crc32_reverseBit((u8)i); k 179 drivers/staging/rtl8723bs/core/rtw_security.c for (c = ((u32)k) << 24, j = 8; j > 0; --j) { k 1920 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c u8 i, j, k, l, m; k 1926 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) k 1929 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; k 1934 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) k 1937 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX; k 203 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c u32 k = 0; k 287 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c (k >= (rtw_hal_sdio_max_txoqt_free_space(padapter) - 1)) k 295 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c pframe->agg_num = k; k 296 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c pxmitbuf->agg_num = k; k 316 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c k = 0; k 338 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c if (k == 0) { k 352 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c k++; k 353 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c if (k != 1) k 366 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c if (k != 1) k 386 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c pframe->agg_num = k; k 387 drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c pxmitbuf->agg_num = k; k 4907 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c s32 k; k 4953 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c k = -1; k 4954 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c while ((++k < num_priv_args) && strcmp(priv_args[k].name, cmdname)); k 4957 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (k == num_priv_args) { k 4963 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (priv_args[k].cmd < SIOCDEVPRIVATE) { k 4968 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (priv_args[j].set_args != priv_args[k].set_args) || k 4969 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (priv_args[j].get_args != priv_args[k].get_args))); k 4978 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c subcmd = priv_args[k].cmd; k 4982 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c k = j; k 4992 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && k 4993 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { k 4996 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) { k 5010 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) k 5011 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; k 5028 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) k 5029 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; k 5037 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) k 5038 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; k 5055 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && k 5056 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) { k 5058 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); k 5068 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && k 5069 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) { k 5075 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].set_args == 0) && k 5076 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && k 5077 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) { k 5095 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if (IW_IS_SET(priv_args[k].cmd)) { k 5097 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c extra_size = get_priv_size(priv_args[k].set_args); k 5100 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && k 5105 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c extra_size = get_priv_size(priv_args[k].get_args); k 5108 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && k 5120 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV]; k 5124 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) && k 5125 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) { k 5131 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && k 5132 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) k 5133 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c n = priv_args[k].get_args & IW_PRIV_SIZE_MASK; k 5143 drivers/staging/rtl8723bs/os_dep/ioctl_linux.c switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) { k 674 drivers/staging/rts5208/ms.c int retval, i, k; k 678 drivers/staging/rts5208/ms.c k = 0; k 694 drivers/staging/rts5208/ms.c if (k > 100) k 697 drivers/staging/rts5208/ms.c k++; k 2289 drivers/staging/rts5208/sd.c int retval, i = 0, j = 0, k = 0; k 2304 drivers/staging/rts5208/sd.c k = 0; k 2400 drivers/staging/rts5208/sd.c k++; k 2401 drivers/staging/rts5208/sd.c if (k < 3) k 2874 drivers/staging/rts5208/sd.c int retval, i = 0, j = 0, k = 0; k 2910 drivers/staging/rts5208/sd.c k++; k 2911 drivers/staging/rts5208/sd.c if (k < 20) { k 184 drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c unsigned int k; k 186 drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c for (k = 0; k < ARRAY_SIZE(formats); k++) { k 187 drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c fmt = &formats[k]; k 362 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c unsigned int num_pages, offset, i, k; k 495 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c k = 0; k 507 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c if (k > 0 && k 508 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c ((addrs[k - 1] & PAGE_MASK) + k 509 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c (((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT)) k 511 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c addrs[k - 1] += ((len + PAGE_SIZE - 1) >> PAGE_SHIFT); k 513 drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c addrs[k++] = (addr & PAGE_MASK) | k 935 drivers/staging/wilc1000/wilc_spi.c int k = IRG_FLAGS_OFFSET + 5; k 955 drivers/staging/wilc1000/wilc_spi.c tmp |= (((irq_flags >> 0) & 0x7) << k); k 147 drivers/staging/wlan-ng/p80211wep.c u32 i, j, k, crc, keylen; k 190 drivers/staging/wlan-ng/p80211wep.c for (k = 0; k < len; k++) { k 194 drivers/staging/wlan-ng/p80211wep.c buf[k] ^= s[(s[i] + s[j]) & 0xff]; k 195 drivers/staging/wlan-ng/p80211wep.c crc = wep_crc32_table[(crc ^ buf[k]) & 0xff] ^ (crc >> 8); k 205 drivers/staging/wlan-ng/p80211wep.c for (k = 0; k < 4; k++) { k 209 drivers/staging/wlan-ng/p80211wep.c if ((c_crc[k] ^ s[(s[i] + s[j]) & 0xff]) != icv[k]) k 210 drivers/staging/wlan-ng/p80211wep.c return -(4 | (k << 4)); /* ICV mismatch */ k 220 drivers/staging/wlan-ng/p80211wep.c u32 i, j, k, crc, keylen; k 263 drivers/staging/wlan-ng/p80211wep.c for (k = 0; k < len; k++) { k 264 drivers/staging/wlan-ng/p80211wep.c crc = wep_crc32_table[(crc ^ buf[k]) & 0xff] ^ (crc >> 8); k 268 drivers/staging/wlan-ng/p80211wep.c dst[k] = buf[k] ^ s[(s[i] + s[j]) & 0xff]; k 278 drivers/staging/wlan-ng/p80211wep.c for (k = 0; k < 4; k++) { k 282 drivers/staging/wlan-ng/p80211wep.c icv[k] ^= s[(s[i] + s[j]) & 0xff]; k 276 drivers/staging/wusbcore/host/whci/whci-hc.h #define WHC_DI_KEY_IDX(k) ((k) << 8) k 96 drivers/target/iscsi/iscsi_target_seq_pdu_list.c int i, j, k; k 107 drivers/target/iscsi/iscsi_target_seq_pdu_list.c for (k = 0; k < i + 1; k++) { k 109 drivers/target/iscsi/iscsi_target_seq_pdu_list.c if ((array[k] & 0x80000000) && (array[k] == j)) k 2732 drivers/target/target_core_user.c int ret, i, k, len = 0; k 2773 drivers/target/target_core_user.c for (k = 0; tcmu_attrib_attrs[k] != NULL; k++) { k 2774 drivers/target/target_core_user.c tcmu_attrs[i] = tcmu_attrib_attrs[k]; k 3237 drivers/tty/cyclades.c unsigned short i, j, k, cy_isa_nchan; k 3340 drivers/tty/cyclades.c for (k = 0, j = cy_next_channel; k 3341 drivers/tty/cyclades.c j < cy_next_channel + cy_isa_nchan; j++, k++) k 3342 drivers/tty/cyclades.c tty_port_register_device(&card->ports[k].port, k 1462 drivers/tty/mxser.c int i, k, value, id; k 1469 drivers/tty/mxser.c k = (i & 0x3F) | 0x180; k 1472 drivers/tty/mxser.c if (k & j) { k 1482 drivers/tty/mxser.c for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) { k 2242 drivers/tty/n_gsm.c c->k = 0; k 2251 drivers/tty/n_gsm.c if ((c->adaption != 1 && c->adaption != 2) || c->k) k 392 drivers/tty/serial/8250/8250_fintek.c int i, j, k, min, max; k 407 drivers/tty/serial/8250/8250_fintek.c for (k = min; k < max; k++) { k 410 drivers/tty/serial/8250/8250_fintek.c sio_write_reg(pdata, LDN, k); k 416 drivers/tty/serial/8250/8250_fintek.c pdata->index = k; k 226 drivers/tty/vt/consolemap.c int i, j, k, glyph; k 248 drivers/tty/vt/consolemap.c for (k = 0; k < 64; k++) { k 249 drivers/tty/vt/consolemap.c glyph = p2[k]; k 252 drivers/tty/vt/consolemap.c q[glyph] = (i << 11) + (j << 6) + k; k 436 drivers/tty/vt/consolemap.c int i, j, k; k 452 drivers/tty/vt/consolemap.c for (k = 0; k < 32; k++) { k 453 drivers/tty/vt/consolemap.c if (!p1[k] && !q1[k]) k 455 drivers/tty/vt/consolemap.c if (!p1[k] || !q1[k]) k 457 drivers/tty/vt/consolemap.c if (memcmp(p1[k], q1[k], 64*sizeof(u16))) k 460 drivers/tty/vt/consolemap.c if (k < 32) k 561 drivers/tty/vt/consolemap.c int j, k; k 589 drivers/tty/vt/consolemap.c for (k = 0; k < 64; k++, l++) k 590 drivers/tty/vt/consolemap.c if (p2[k] != 0xffff) { k 595 drivers/tty/vt/consolemap.c err1 = con_insert_unipair(q, l, p2[k]); k 740 drivers/tty/vt/consolemap.c int i, j, k, ret = 0; k 761 drivers/tty/vt/consolemap.c for (k = 0; k < 64; k++, p2++) { k 766 drivers/tty/vt/consolemap.c (i<<11)+(j<<6)+k; k 376 drivers/tty/vt/keyboard.c unsigned int k, sym, val; k 381 drivers/tty/vt/keyboard.c for_each_set_bit(k, key_down, min(NR_KEYS, KEY_CNT)) { k 382 drivers/tty/vt/keyboard.c sym = U(key_maps[0][k]); k 2003 drivers/tty/vt/keyboard.c int i, j, k; k 2070 drivers/tty/vt/keyboard.c for (k = j; k < MAX_NR_FUNC; k++) k 2071 drivers/tty/vt/keyboard.c if (func_table[k]) k 2072 drivers/tty/vt/keyboard.c func_table[k] += delta; k 2098 drivers/tty/vt/keyboard.c for (k = 0; k < j; k++) k 2099 drivers/tty/vt/keyboard.c if (func_table[k]) k 2100 drivers/tty/vt/keyboard.c func_table[k] = fnw + (func_table[k] - funcbufptr); k 2105 drivers/tty/vt/keyboard.c for (k = j; k < MAX_NR_FUNC; k++) k 2106 drivers/tty/vt/keyboard.c if (func_table[k]) k 2107 drivers/tty/vt/keyboard.c func_table[k] = fnw + (func_table[k] - funcbufptr) + delta; k 444 drivers/tty/vt/vt.c unsigned int i, j, k, sz, d, clear; k 457 drivers/tty/vt/vt.c k = j + d; k 458 drivers/tty/vt/vt.c if (k >= sz) k 459 drivers/tty/vt/vt.c k -= sz; k 460 drivers/tty/vt/vt.c if (k == i) k 462 drivers/tty/vt/vt.c uniscr->lines[t + j] = uniscr->lines[t + k]; k 463 drivers/tty/vt/vt.c j = k; k 3328 drivers/tty/vt/vt.c int j, k ; k 3338 drivers/tty/vt/vt.c for (j=k=0; j<16; j++) { k 3339 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_red[j] ; k 3340 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_grn[j] ; k 3341 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_blu[j] ; k 3510 drivers/tty/vt/vt.c int i, j = -1, k = -1, retval = -ENODEV; k 3562 drivers/tty/vt/vt.c k = i; k 3591 drivers/tty/vt/vt.c if (k >= 0) { k 3592 drivers/tty/vt/vt.c vc = vc_cons[k].d; k 4394 drivers/tty/vt/vt.c int i, j, k; k 4401 drivers/tty/vt/vt.c for (i = k = 0; i < 16; i++) { k 4402 drivers/tty/vt/vt.c default_red[i] = colormap[k++]; k 4403 drivers/tty/vt/vt.c default_grn[i] = colormap[k++]; k 4404 drivers/tty/vt/vt.c default_blu[i] = colormap[k++]; k 4409 drivers/tty/vt/vt.c for (j = k = 0; j < 16; j++) { k 4410 drivers/tty/vt/vt.c vc_cons[i].d->vc_palette[k++] = default_red[j]; k 4411 drivers/tty/vt/vt.c vc_cons[i].d->vc_palette[k++] = default_grn[j]; k 4412 drivers/tty/vt/vt.c vc_cons[i].d->vc_palette[k++] = default_blu[j]; k 4423 drivers/tty/vt/vt.c int i, k; k 4427 drivers/tty/vt/vt.c for (i = k = 0; i < 16; i++) { k 4428 drivers/tty/vt/vt.c colormap[k++] = default_red[i]; k 4429 drivers/tty/vt/vt.c colormap[k++] = default_grn[i]; k 4430 drivers/tty/vt/vt.c colormap[k++] = default_blu[i]; k 4442 drivers/tty/vt/vt.c int j, k; k 4443 drivers/tty/vt/vt.c for (j=k=0; j<16; j++) { k 4444 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_red[j]; k 4445 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_grn[j]; k 4446 drivers/tty/vt/vt.c vc->vc_palette[k++] = default_blu[j]; k 1682 drivers/usb/chipidea/udc.c int k = i + j * ci->hw_ep_max/2; k 1683 drivers/usb/chipidea/udc.c struct ci_hw_ep *hwep = &ci->ci_hw_ep[k]; k 230 drivers/usb/core/config.c int i, j, k; k 242 drivers/usb/core/config.c for (k = 0; k < alt->desc.bNumEndpoints; ++k) { k 243 drivers/usb/core/config.c epd = &alt->endpoint[k].desc; k 566 drivers/usb/host/isp116x.h int k; k 570 drivers/usb/host/isp116x.h for (k = 0; k < PTD_GET_LEN(ptd); ++k) k 571 drivers/usb/host/isp116x.h printk("%02x ", ((u8 *) buf)[k]); k 578 drivers/usb/host/isp116x.h int k; k 582 drivers/usb/host/isp116x.h for (k = 0; k < PTD_GET_COUNT(ptd); ++k) k 583 drivers/usb/host/isp116x.h printk("%02x ", ((u8 *) buf)[k]); k 892 drivers/usb/host/isp1362.h int k; k 895 drivers/usb/host/isp1362.h for (k = 0; k < len; ++k) { k 897 drivers/usb/host/isp1362.h DBG(0, "%04x:", k); k 898 drivers/usb/host/isp1362.h printk(" %02x", ((u8 *) buf)[k]); k 900 drivers/usb/host/isp1362.h if (!k) k 902 drivers/usb/host/isp1362.h if (k % 16 == 15) { k 907 drivers/usb/host/isp1362.h if (k % 8 == 7) k 909 drivers/usb/host/isp1362.h if (k % 4 == 3) k 967 drivers/usb/host/xhci-tegra.c unsigned int i, j, k; k 1142 drivers/usb/host/xhci-tegra.c for (i = 0, k = 0; i < tegra->soc->num_types; i++) { k 1158 drivers/usb/host/xhci-tegra.c tegra->phys[k++] = phy; k 766 drivers/usb/misc/sisusbvga/sisusb_init.c unsigned short data, data2, time, i, j, k, m, n, o; k 800 drivers/usb/misc/sisusbvga/sisusb_init.c for (k = 0; k < 3; k++) { k 814 drivers/usb/misc/sisusbvga/sisusb_init.c for (k = 0; k < 3; k++) k 592 drivers/usb/serial/garmin_gps.c int k; k 597 drivers/usb/serial/garmin_gps.c k = garmin_data_p->outsize; k 598 drivers/usb/serial/garmin_gps.c if ((k+count) > GPS_OUT_BUFSIZ) { k 604 drivers/usb/serial/garmin_gps.c memcpy(garmin_data_p->outbuffer+k, buf, count); k 605 drivers/usb/serial/garmin_gps.c k += count; k 606 drivers/usb/serial/garmin_gps.c garmin_data_p->outsize = k; k 608 drivers/usb/serial/garmin_gps.c if (k >= GARMIN_PKTHDR_LENGTH) { k 612 drivers/usb/serial/garmin_gps.c if (k < i) k 618 drivers/usb/serial/garmin_gps.c dev_dbg(dev, "%s - %d bytes in buffer, %d bytes in pkt.\n", __func__, k, i); k 622 drivers/usb/serial/garmin_gps.c usb_serial_debug_data(&garmin_data_p->port->dev, __func__, k, k 645 drivers/usb/serial/garmin_gps.c k = 0; k 649 drivers/usb/serial/garmin_gps.c k++; k 653 drivers/usb/serial/garmin_gps.c if (k > (GARMIN_PKTHDR_LENGTH-2)) { k 293 drivers/usb/usbip/usbip_common.h #define kthread_stop_put(k) \ k 295 drivers/usb/usbip/usbip_common.h kthread_stop(k); \ k 296 drivers/usb/usbip/usbip_common.h put_task_struct(k); \ k 622 drivers/video/fbdev/aty/mach64_gx.c u16 m, n, k = 0, save_m, save_n, twoToKth; k 646 drivers/video/fbdev/aty/mach64_gx.c k++; k 649 drivers/video/fbdev/aty/mach64_gx.c twoToKth = 1 << k; k 674 drivers/video/fbdev/aty/mach64_gx.c program_bits = (k << 6) + (save_m) + (save_n << 8); k 781 drivers/video/fbdev/controlfb.c unsigned long p0, p1, p2, k, l, m, n, min; k 790 drivers/video/fbdev/controlfb.c for (k = 1, min = l; k < 32; k++) { k 793 drivers/video/fbdev/controlfb.c m = CONTROL_PIXCLOCK_BASE * k; k 797 drivers/video/fbdev/controlfb.c p0 = k; k 225 drivers/video/fbdev/core/cfbimgblt.c int i, j, k; k 249 drivers/video/fbdev/core/cfbimgblt.c k = image->width/ppw; k 254 drivers/video/fbdev/core/cfbimgblt.c for (j = k; j--; ) { k 2729 drivers/video/fbdev/core/fbcon.c int i, j, k, depth; k 2741 drivers/video/fbdev/core/fbcon.c k = table[i]; k 2743 drivers/video/fbdev/core/fbcon.c palette_red[k] = (val << 8) | val; k 2745 drivers/video/fbdev/core/fbcon.c palette_green[k] = (val << 8) | val; k 2747 drivers/video/fbdev/core/fbcon.c palette_blue[k] = (val << 8) | val; k 276 drivers/video/fbdev/core/fbmem.c int i, j, k; k 313 drivers/video/fbdev/core/fbmem.c for (k = 7; k >= 0 && j < logo->width; k--) { k 314 drivers/video/fbdev/core/fbmem.c *dst++ = ((d >> k) & 1) ? fg : 0; k 195 drivers/video/fbdev/core/sysimgblt.c int i, j, k; k 219 drivers/video/fbdev/core/sysimgblt.c k = image->width/ppw; k 226 drivers/video/fbdev/core/sysimgblt.c for (j = k; j--; ) { k 78 drivers/video/fbdev/maxinefb.c register unsigned int j, k; k 82 drivers/video/fbdev/maxinefb.c k = *((volatile unsigned short *) regs); k 84 drivers/video/fbdev/maxinefb.c return (j & 0xffff) | ((k & 0xff00) << 8); k 105 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c int k = 0; k 106 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c for (k = 0; k < step; k++) k 107 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c cmd[9 + i * step + k] = k 108 drivers/video/fbdev/mb862xx/mb862xxfb_accel.c cpu_to_be32(cmd[9 + i * step + k]); k 358 drivers/video/fbdev/nvidia/nv_accel.c int j, k = 0; k 386 drivers/video/fbdev/nvidia/nv_accel.c tmp = data[k++]; k 398 drivers/video/fbdev/nvidia/nv_accel.c tmp = data[k++]; k 118 drivers/video/fbdev/nvidia/nvidia.c int i, j, k = 0; k 140 drivers/video/fbdev/nvidia/nvidia.c NV_WR32(&par->CURSOR[k++], 0, tmp); k 142 drivers/video/fbdev/nvidia/nvidia.c k += (MAX_CURS - w) / 2; k 560 drivers/video/fbdev/omap/sossi.c u32 l, k; k 616 drivers/video/fbdev/omap/sossi.c k = sossi_read_reg(SOSSI_ID_REG); k 618 drivers/video/fbdev/omap/sossi.c if (l != 0x55555555 || k != 0xaaaaaaaa) { k 620 drivers/video/fbdev/omap/sossi.c "invalid SoSSI sync pattern: %08x, %08x\n", l, k); k 1324 drivers/video/fbdev/pm2fb.c int k = 8 - j; k 1344 drivers/video/fbdev/pm2fb.c for (; k > 0; k--) { k 1433 drivers/video/fbdev/pm2fb.c int k = 8 - j; k 1446 drivers/video/fbdev/pm2fb.c for (; k > 0; k--) k 1459 drivers/video/fbdev/pm2fb.c int k = 8 - j; k 1467 drivers/video/fbdev/pm2fb.c for (; k > 0; k--) k 686 drivers/video/fbdev/pm3fb.c int k = 8 - j; k 704 drivers/video/fbdev/pm3fb.c for (; k > 0; k--) { k 490 drivers/video/fbdev/riva/fbdev.c int i, j, k = 0; k 515 drivers/video/fbdev/riva/fbdev.c writel(tmp, &par->riva.CURSOR[k++]); k 517 drivers/video/fbdev/riva/fbdev.c k += (MAX_CURS - w)/2; k 645 drivers/video/fbdev/sh_mobile_lcdcfb.c int k; k 655 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 656 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 703 drivers/video/fbdev/sh_mobile_lcdcfb.c int k; k 712 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) k 713 drivers/video/fbdev/sh_mobile_lcdcfb.c if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled) k 715 drivers/video/fbdev/sh_mobile_lcdcfb.c tmp = lcdc_read_chan(&priv->ch[k], LDPMR) k 881 drivers/video/fbdev/sh_mobile_lcdcfb.c int k, m; k 894 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 895 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 922 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 923 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 993 drivers/video/fbdev/sh_mobile_lcdcfb.c int k; k 996 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 997 drivers/video/fbdev/sh_mobile_lcdcfb.c if (priv->ch[k].enabled) k 1005 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 1008 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 1021 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 1022 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 1032 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) { k 1033 drivers/video/fbdev/sh_mobile_lcdcfb.c struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k]; k 1043 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 1044 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 1070 drivers/video/fbdev/sh_mobile_lcdcfb.c int k; k 1073 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) { k 1074 drivers/video/fbdev/sh_mobile_lcdcfb.c ch = &priv->ch[k]; k 1106 drivers/video/fbdev/sh_mobile_lcdcfb.c for (k = 0; k < ARRAY_SIZE(priv->ch); k++) k 1107 drivers/video/fbdev/sh_mobile_lcdcfb.c if (priv->ch[k].enabled) k 2876 drivers/video/fbdev/sis/init.c unsigned short data, data2, time, i, j, k, m, n, o; k 2911 drivers/video/fbdev/sis/init.c for(k = 0; k < 3; k++) { k 2923 drivers/video/fbdev/sis/init.c for(k = 0; k < 3; k++) SiS_SetRegByte(DACData, data); k 4262 drivers/video/fbdev/sis/sis_main.c unsigned int k, RankCapacity, PageCapacity, BankNumHigh, BankNumMid; k 4265 drivers/video/fbdev/sis/sis_main.c for(k = 0; k < ARRAY_SIZE(SiS_DRAMType); k++) { k 4267 drivers/video/fbdev/sis/sis_main.c RankCapacity = buswidth * SiS_DRAMType[k][3]; k 4272 drivers/video/fbdev/sis/sis_main.c if((SiS_DRAMType[k][2] + SiS_DRAMType[k][0]) > PseudoAdrPinCount) k 4282 drivers/video/fbdev/sis/sis_main.c PageCapacity = (1 << SiS_DRAMType[k][1]) * buswidth * 4; k 4285 drivers/video/fbdev/sis/sis_main.c PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh; k 4289 drivers/video/fbdev/sis/sis_main.c sr14 = (SiS_DRAMType[k][3] * buswidth) - 1; k 4292 drivers/video/fbdev/sis/sis_main.c SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]); k 4634 drivers/video/fbdev/sis/sis_main.c int i, j, k, l, status; k 4837 drivers/video/fbdev/sis/sis_main.c k = (ivideo->chip == XGI_20) ? 12 : 4; k 4840 drivers/video/fbdev/sis/sis_main.c for(i = 0; i < k; i++) { k 5112 drivers/video/fbdev/sis/sis_main.c int i, j, k, index; k 5462 drivers/video/fbdev/sis/sis_main.c for(k = 0; k < 16; k++) { k 1528 drivers/video/fbdev/sm501fb.c int k; k 1619 drivers/video/fbdev/sm501fb.c for (k = 0; k < (256 * 3); k++) k 1620 drivers/video/fbdev/sm501fb.c smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4)); k 164 drivers/video/fbdev/ssd1307fb.c int i, j, k; k 207 drivers/video/fbdev/ssd1307fb.c for (k = 0; k < m; k++) { k 208 drivers/video/fbdev/ssd1307fb.c u8 byte = vmem[(8 * i + k) * line_length + k 211 drivers/video/fbdev/ssd1307fb.c array->data[array_idx] |= bit << k; k 291 drivers/video/fbdev/tdfxfb.c int m, n, k, best_m, best_n, best_k, best_error; k 297 drivers/video/fbdev/tdfxfb.c for (k = 3; k >= 0; k--) { k 303 drivers/video/fbdev/tdfxfb.c int n_estimated = ((freq * (m + 2) << k) / fref) - 2; k 313 drivers/video/fbdev/tdfxfb.c int f = (fref * (n + 2) / (m + 2)) >> k; k 324 drivers/video/fbdev/tdfxfb.c best_k = k; k 332 drivers/video/fbdev/tdfxfb.c k = best_k; k 333 drivers/video/fbdev/tdfxfb.c *freq_out = (fref * (n + 2) / (m + 2)) >> k; k 335 drivers/video/fbdev/tdfxfb.c return (n << 8) | (m << 2) | k; k 838 drivers/video/fbdev/tridentfb.c int m, n, k; k 845 drivers/video/fbdev/tridentfb.c for (k = shift; k >= 0; k--) k 849 drivers/video/fbdev/tridentfb.c fi = ((14318l * (n + 8)) / (m + 2)) >> k; k 851 drivers/video/fbdev/tridentfb.c if (di < d || (di == d && k == best_k)) { k 855 drivers/video/fbdev/tridentfb.c best_k = k; k 912 drivers/video/fbdev/tridentfb.c unsigned int k; k 916 drivers/video/fbdev/tridentfb.c k = memsize * Kb; k 920 drivers/video/fbdev/tridentfb.c k = 2560 * Kb; k 927 drivers/video/fbdev/tridentfb.c k = 512 * Kb; k 930 drivers/video/fbdev/tridentfb.c k = 6 * Mb; /* XP */ k 933 drivers/video/fbdev/tridentfb.c k = 1 * Mb; k 936 drivers/video/fbdev/tridentfb.c k = 8 * Mb; k 939 drivers/video/fbdev/tridentfb.c k = 10 * Mb; /* XP */ k 942 drivers/video/fbdev/tridentfb.c k = 2 * Mb; k 945 drivers/video/fbdev/tridentfb.c k = 12 * Mb; /* XP */ k 948 drivers/video/fbdev/tridentfb.c k = 14 * Mb; /* XP */ k 951 drivers/video/fbdev/tridentfb.c k = 16 * Mb; /* XP */ k 958 drivers/video/fbdev/tridentfb.c k = 20 * Mb; k 961 drivers/video/fbdev/tridentfb.c k = 24 * Mb; k 964 drivers/video/fbdev/tridentfb.c k = 28 * Mb; k 967 drivers/video/fbdev/tridentfb.c k = 32 * Mb; k 970 drivers/video/fbdev/tridentfb.c k = 1 * Mb; k 976 drivers/video/fbdev/tridentfb.c k = 4 * Mb; k 979 drivers/video/fbdev/tridentfb.c k = 1 * Mb; k 984 drivers/video/fbdev/tridentfb.c k -= memdiff * Kb; k 985 drivers/video/fbdev/tridentfb.c output("framebuffer size = %d Kb\n", k / Kb); k 986 drivers/video/fbdev/tridentfb.c return k; k 366 drivers/video/fbdev/udlfb.c int j, k; k 381 drivers/video/fbdev/udlfb.c for (k = width - 1; k > j; k--) { k 382 drivers/video/fbdev/udlfb.c if (back[k] != front[k]) { k 383 drivers/video/fbdev/udlfb.c end = k+1; k 582 fs/binfmt_elf.c unsigned long k, map_addr; k 610 fs/binfmt_elf.c k = load_addr + eppnt->p_vaddr; k 611 fs/binfmt_elf.c if (BAD_ADDR(k) || k 614 fs/binfmt_elf.c TASK_SIZE - eppnt->p_memsz < k) { k 623 fs/binfmt_elf.c k = load_addr + eppnt->p_vaddr + eppnt->p_filesz; k 624 fs/binfmt_elf.c if (k > elf_bss) k 625 fs/binfmt_elf.c elf_bss = k; k 631 fs/binfmt_elf.c k = load_addr + eppnt->p_vaddr + eppnt->p_memsz; k 632 fs/binfmt_elf.c if (k > last_bss) { k 633 fs/binfmt_elf.c last_bss = k; k 883 fs/binfmt_elf.c unsigned long k, vaddr; k 1001 fs/binfmt_elf.c k = elf_ppnt->p_vaddr; k 1002 fs/binfmt_elf.c if (k < start_code) k 1003 fs/binfmt_elf.c start_code = k; k 1004 fs/binfmt_elf.c if (start_data < k) k 1005 fs/binfmt_elf.c start_data = k; k 1012 fs/binfmt_elf.c if (BAD_ADDR(k) || elf_ppnt->p_filesz > elf_ppnt->p_memsz || k 1014 fs/binfmt_elf.c TASK_SIZE - elf_ppnt->p_memsz < k) { k 1020 fs/binfmt_elf.c k = elf_ppnt->p_vaddr + elf_ppnt->p_filesz; k 1022 fs/binfmt_elf.c if (k > elf_bss) k 1023 fs/binfmt_elf.c elf_bss = k; k 1024 fs/binfmt_elf.c if ((elf_ppnt->p_flags & PF_X) && end_code < k) k 1025 fs/binfmt_elf.c end_code = k; k 1026 fs/binfmt_elf.c if (end_data < k) k 1027 fs/binfmt_elf.c end_data = k; k 1028 fs/binfmt_elf.c k = elf_ppnt->p_vaddr + elf_ppnt->p_memsz; k 1029 fs/binfmt_elf.c if (k > elf_brk) { k 1031 fs/binfmt_elf.c elf_brk = k; k 31 fs/cachefiles/namei.c const u8 *k; k 55 fs/cachefiles/namei.c k = (cookie->key_len <= sizeof(cookie->inline_key)) ? k 58 fs/cachefiles/namei.c pr_cont("%02x", k[loop]); k 179 fs/dlm/lockspace.c static void lockspace_kobj_release(struct kobject *k) k 181 fs/dlm/lockspace.c struct dlm_ls *ls = container_of(k, struct dlm_ls, ls_kobj); k 362 fs/ext2/inode.c ext2_blks_to_allocate(Indirect * branch, int k, unsigned long blks, k 371 fs/ext2/inode.c if (k > 0) { k 1055 fs/ext2/inode.c int k, err; k 1058 fs/ext2/inode.c for (k = depth; k > 1 && !offsets[k-1]; k--) k 1060 fs/ext2/inode.c partial = ext2_get_branch(inode, k, offsets, chain, &err); k 1062 fs/ext2/inode.c partial = chain + k-1; k 1080 fs/ext2/inode.c if (p == chain + k - 1 && p > chain) { k 640 fs/ext4/extents.c int k, l = path->p_depth; k 643 fs/ext4/extents.c for (k = 0; k <= l; k++, path++) { k 769 fs/ext4/extents.c int k; k 772 fs/ext4/extents.c for (k = 0; k < le16_to_cpu(eh->eh_entries); k++, ix++) { k 773 fs/ext4/extents.c if (k != 0 && k 776 fs/ext4/extents.c "first=0x%p\n", k, k 782 fs/ext4/extents.c BUG_ON(k && le32_to_cpu(ix->ei_block) k 840 fs/ext4/extents.c int k; k 843 fs/ext4/extents.c for (k = 0; k < le16_to_cpu(eh->eh_entries); k++, ex++) { k 844 fs/ext4/extents.c BUG_ON(k && le32_to_cpu(ex->ee_block) k 1044 fs/ext4/extents.c int i = at, k, m, a; k 1168 fs/ext4/extents.c k = depth - at - 1; k 1169 fs/ext4/extents.c if (unlikely(k < 0)) { k 1170 fs/ext4/extents.c EXT4_ERROR_INODE(inode, "k %d < 0!", k); k 1174 fs/ext4/extents.c if (k) k 1175 fs/ext4/extents.c ext_debug("create %d intermediate indices\n", k); k 1179 fs/ext4/extents.c while (k--) { k 1690 fs/ext4/extents.c int k, err = 0; k 1714 fs/ext4/extents.c k = depth - 1; k 1716 fs/ext4/extents.c err = ext4_ext_get_access(handle, inode, path + k); k 1719 fs/ext4/extents.c path[k].p_idx->ei_block = border; k 1720 fs/ext4/extents.c err = ext4_ext_dirty(handle, inode, path + k); k 1724 fs/ext4/extents.c while (k--) { k 1726 fs/ext4/extents.c if (path[k+1].p_idx != EXT_FIRST_INDEX(path[k+1].p_hdr)) k 1728 fs/ext4/extents.c err = ext4_ext_get_access(handle, inode, path + k); k 1731 fs/ext4/extents.c path[k].p_idx->ei_block = border; k 1732 fs/ext4/extents.c err = ext4_ext_dirty(handle, inode, path + k); k 3058 fs/ext4/extents.c int k = i = depth; k 3059 fs/ext4/extents.c while (--k > 0) k 3060 fs/ext4/extents.c path[k].p_block = k 3061 fs/ext4/extents.c le16_to_cpu(path[k].p_hdr->eh_entries)+1; k 270 fs/ext4/indirect.c static int ext4_blks_to_allocate(Indirect *branch, int k, unsigned int blks, k 279 fs/ext4/indirect.c if (k > 0) { k 768 fs/ext4/indirect.c int k, err; k 772 fs/ext4/indirect.c for (k = depth; k > 1 && !offsets[k-1]; k--) k 774 fs/ext4/indirect.c partial = ext4_get_branch(inode, k, offsets, chain, &err); k 777 fs/ext4/indirect.c partial = chain + k-1; k 793 fs/ext4/indirect.c if (p == chain + k - 1 && p > chain) { k 552 fs/ext4/mballoc.c int k; k 595 fs/ext4/mballoc.c k = (i * (1 << order)) + j; k 597 fs/ext4/mballoc.c !mb_test_bit(k, e4b->bd_bitmap)); k 620 fs/ext4/mballoc.c k = i >> j; k 621 fs/ext4/mballoc.c MB_CHECK_ASSERT(k < max2); k 622 fs/ext4/mballoc.c MB_CHECK_ASSERT(mb_test_bit(k, buddy2)); k 633 fs/ext4/mballoc.c ext4_get_group_no_and_offset(sb, pa->pa_pstart, &groupnr, &k); k 636 fs/ext4/mballoc.c MB_CHECK_ASSERT(mb_test_bit(k + i, buddy)); k 1892 fs/ext4/mballoc.c int k; k 1903 fs/ext4/mballoc.c k = mb_find_next_zero_bit(buddy, max, 0); k 1904 fs/ext4/mballoc.c BUG_ON(k >= max); k 1909 fs/ext4/mballoc.c ac->ac_b_ex.fe_start = k << i; k 361 fs/fat/dir.c int chi, chl, i, j, k; k 414 fs/fat/dir.c for (k = 8; k < MSDOS_NAME;) { k 415 fs/fat/dir.c c = work[k]; k 418 fs/fat/dir.c chl = fat_shortname2uni(nls_disk, &work[k], MSDOS_NAME - k, k 422 fs/fat/dir.c k++; k 433 fs/fat/dir.c int offset = min(chl, MSDOS_NAME-k); k 434 fs/fat/dir.c k += offset; k 437 fs/fat/dir.c for (chi = 0; chi < chl && k < MSDOS_NAME; k 438 fs/fat/dir.c chi++, i++, k++) { k 439 fs/fat/dir.c ptname[i] = work[k]; k 33 fs/fscache/cookie.c const u8 *k; k 49 fs/fscache/cookie.c k = (cookie->key_len <= sizeof(cookie->inline_key)) ? k 52 fs/fscache/cookie.c pr_cont("%02x", k[loop]); k 342 fs/fuse/file.c u32 *k = fc->scramble_key; k 350 fs/fuse/file.c v0 += ((v1 << 4 ^ v1 >> 5) + v1) ^ (sum + k[sum & 3]); k 352 fs/fuse/file.c v1 += ((v0 << 4 ^ v0 >> 5) + v0) ^ (sum + k[sum>>11 & 3]); k 161 fs/hpfs/alloc.c unsigned k = le32_to_cpu(bmp[i-1]); k 162 fs/hpfs/alloc.c while (k & 0x80000000) { k 163 fs/hpfs/alloc.c q--; k <<= 1; k 368 fs/hpfs/alloc.c unsigned k; k 370 fs/hpfs/alloc.c for (k = le32_to_cpu(bmp[j]); k; k >>= 1) if (k & 1) if (!--n) { k 389 fs/hpfs/alloc.c u32 k; k 391 fs/hpfs/alloc.c for (k = 0xf; k; k <<= 4) k 392 fs/hpfs/alloc.c if ((le32_to_cpu(bmp[j]) & k) == k) { k 1357 fs/jfs/jfs_dmap.c int rc, ti, i, k, m, n, agperlev; k 1449 fs/jfs/jfs_dmap.c for (k = bmp->db_agheight; k > 0; k--) { k 2887 fs/jfs/jfs_dmap.c int lp, pp, k; k 2906 fs/jfs/jfs_dmap.c for (k = 0; k < le32_to_cpu(tp->dmt_height); k++) { k 2961 fs/jfs/jfs_dmap.c int ti, n = 0, k, x = 0; k 2973 fs/jfs/jfs_dmap.c for (k = le32_to_cpu(tp->dmt_height), ti = 1; k 2974 fs/jfs/jfs_dmap.c k > 0; k--, ti = ((ti + n) << 2) + 1) { k 3375 fs/jfs/jfs_dmap.c int i, i0 = true, j, j0 = true, k, n; k 3424 fs/jfs/jfs_dmap.c k = 1 << (l2agsize - oldl2agsize); k 3430 fs/jfs/jfs_dmap.c for (j = 0; j < k && i < agno; j++, i++) { k 3444 fs/jfs/jfs_dmap.c bmp->db_maxag = bmp->db_maxag / k; k 3463 fs/jfs/jfs_dmap.c k = blkno >> L2MAXL1SIZE; k 3464 fs/jfs/jfs_dmap.c l2leaf = l2dcp->stree + CTLLEAFIND + k; k 3470 fs/jfs/jfs_dmap.c for (; k < LPERCTL; k++, p += nbperpage) { k 3611 fs/jfs/jfs_dmap.c if (k > 0) k 626 fs/jfs/jfs_extent.c u64 m, k; k 634 fs/jfs/jfs_extent.c k = (u64) 1 << i; k 635 fs/jfs/jfs_extent.c k = ((k - 1) & nb) ? k : k >> 1; k 637 fs/jfs/jfs_extent.c return (k); k 227 fs/jfs/jfs_txnmgr.c int k, size; k 275 fs/jfs/jfs_txnmgr.c for (k = 1; k < nTxBlock - 1; k++) { k 276 fs/jfs/jfs_txnmgr.c TxBlock[k].next = k + 1; k 277 fs/jfs/jfs_txnmgr.c init_waitqueue_head(&TxBlock[k].gcwait); k 278 fs/jfs/jfs_txnmgr.c init_waitqueue_head(&TxBlock[k].waitor); k 280 fs/jfs/jfs_txnmgr.c TxBlock[k].next = 0; k 281 fs/jfs/jfs_txnmgr.c init_waitqueue_head(&TxBlock[k].gcwait); k 282 fs/jfs/jfs_txnmgr.c init_waitqueue_head(&TxBlock[k].waitor); k 303 fs/jfs/jfs_txnmgr.c for (k = 1; k < nTxLock - 1; k++) k 304 fs/jfs/jfs_txnmgr.c TxLock[k].next = k + 1; k 305 fs/jfs/jfs_txnmgr.c TxLock[k].next = 0; k 899 fs/jfs/jfs_txnmgr.c lid_t lid, next, llid, k; k 953 fs/jfs/jfs_txnmgr.c k = linelock->next; k 955 fs/jfs/jfs_txnmgr.c llid = k; k 1134 fs/jfs/jfs_txnmgr.c int k, n; k 1190 fs/jfs/jfs_txnmgr.c for (k = 0; k < cd.nip; k++) { k 1191 fs/jfs/jfs_txnmgr.c top = (cd.iplist[k])->i_ino; k 1192 fs/jfs/jfs_txnmgr.c for (n = k + 1; n < cd.nip; n++) { k 1196 fs/jfs/jfs_txnmgr.c cd.iplist[n] = cd.iplist[k]; k 1197 fs/jfs/jfs_txnmgr.c cd.iplist[k] = ip; k 1201 fs/jfs/jfs_txnmgr.c ip = cd.iplist[k]; k 1337 fs/jfs/jfs_txnmgr.c for (k = 0; k < cd.nip; k++) { k 1338 fs/jfs/jfs_txnmgr.c ip = cd.iplist[k]; k 2286 fs/jfs/jfs_txnmgr.c int k, nlock; k 2333 fs/jfs/jfs_txnmgr.c for (k = 0; k < nlock; k++, maplock++) { k 47 fs/minix/bitmap.c int k = sb->s_blocksize_bits + 3; k 55 fs/minix/bitmap.c bit = zone & ((1<<k) - 1); k 56 fs/minix/bitmap.c zone >>= k; k 188 fs/minix/bitmap.c int k = sb->s_blocksize_bits + 3; k 196 fs/minix/bitmap.c bit = ino & ((1<<k) - 1); k 197 fs/minix/bitmap.c ino >>= k; k 224 fs/minix/itree_common.c int k, err; k 227 fs/minix/itree_common.c for (k = depth; k > 1 && !offsets[k-1]; k--) k 229 fs/minix/itree_common.c partial = get_branch(inode, k, offsets, chain, &err); k 233 fs/minix/itree_common.c partial = chain + k-1; k 240 fs/minix/itree_common.c if (p == chain + k - 1 && p > chain) { k 353 fs/minix/itree_common.c int k = sb->s_blocksize_bits - 10; k 355 fs/minix/itree_common.c blocks = (size + sb->s_blocksize - 1) >> (BLOCK_SIZE_BITS + k); k 1919 fs/nfsd/nfs4state.c static void __free_client(struct kref *k) k 1921 fs/nfsd/nfs4state.c struct nfsdfs_client *c = container_of(k, struct nfsdfs_client, cl_ref); k 736 fs/nilfs2/alloc.c int i, j, k, ret; k 807 fs/nilfs2/alloc.c for (k = 0; k < nempties; k++) { k 809 fs/nilfs2/alloc.c last_nrs[k]); k 813 fs/nilfs2/alloc.c ret, (unsigned long long)last_nrs[k], k 254 fs/proc/array.c struct k_sigaction *k; k 257 fs/proc/array.c k = p->sighand->action; k 258 fs/proc/array.c for (i = 1; i <= _NSIG; ++i, ++k) { k 259 fs/proc/array.c if (k->sa.sa_handler == SIG_IGN) k 261 fs/proc/array.c else if (k->sa.sa_handler != SIG_DFL) k 92 fs/proc/page.c u64 k; k 102 fs/proc/page.c k = page->flags; k 165 fs/proc/page.c u |= kpf_copy_bit(k, KPF_LOCKED, PG_locked); k 167 fs/proc/page.c u |= kpf_copy_bit(k, KPF_SLAB, PG_slab); k 171 fs/proc/page.c u |= kpf_copy_bit(k, KPF_ERROR, PG_error); k 172 fs/proc/page.c u |= kpf_copy_bit(k, KPF_DIRTY, PG_dirty); k 173 fs/proc/page.c u |= kpf_copy_bit(k, KPF_UPTODATE, PG_uptodate); k 174 fs/proc/page.c u |= kpf_copy_bit(k, KPF_WRITEBACK, PG_writeback); k 176 fs/proc/page.c u |= kpf_copy_bit(k, KPF_LRU, PG_lru); k 177 fs/proc/page.c u |= kpf_copy_bit(k, KPF_REFERENCED, PG_referenced); k 178 fs/proc/page.c u |= kpf_copy_bit(k, KPF_ACTIVE, PG_active); k 179 fs/proc/page.c u |= kpf_copy_bit(k, KPF_RECLAIM, PG_reclaim); k 183 fs/proc/page.c u |= kpf_copy_bit(k, KPF_SWAPBACKED, PG_swapbacked); k 185 fs/proc/page.c u |= kpf_copy_bit(k, KPF_UNEVICTABLE, PG_unevictable); k 186 fs/proc/page.c u |= kpf_copy_bit(k, KPF_MLOCKED, PG_mlocked); k 189 fs/proc/page.c u |= kpf_copy_bit(k, KPF_HWPOISON, PG_hwpoison); k 193 fs/proc/page.c u |= kpf_copy_bit(k, KPF_UNCACHED, PG_uncached); k 196 fs/proc/page.c u |= kpf_copy_bit(k, KPF_RESERVED, PG_reserved); k 197 fs/proc/page.c u |= kpf_copy_bit(k, KPF_MAPPEDTODISK, PG_mappedtodisk); k 198 fs/proc/page.c u |= kpf_copy_bit(k, KPF_PRIVATE, PG_private); k 199 fs/proc/page.c u |= kpf_copy_bit(k, KPF_PRIVATE_2, PG_private_2); k 200 fs/proc/page.c u |= kpf_copy_bit(k, KPF_OWNER_PRIVATE, PG_owner_priv_1); k 201 fs/proc/page.c u |= kpf_copy_bit(k, KPF_ARCH, PG_arch_1); k 46 fs/reiserfs/hashes.c u32 k[] = { 0x9464a485, 0x542e1a94, 0x3e846bff, 0xb75bcfc3 }; k 48 fs/reiserfs/hashes.c u32 h0 = k[0], h1 = k[1]; k 819 fs/reiserfs/ibalance.c int insert_num, n, k; k 853 fs/reiserfs/ibalance.c k = 0; k 891 fs/reiserfs/ibalance.c k = tb->lnum[h] - child_pos - 1; k 898 fs/reiserfs/ibalance.c n + child_pos + 1, k, k 901 fs/reiserfs/ibalance.c replace_lkey(tb, h, insert_key + k); k 909 fs/reiserfs/ibalance.c MAX_CHILD_SIZE(insert_ptr[k]) - k 910 fs/reiserfs/ibalance.c B_FREE_SPACE(insert_ptr[k])); k 911 fs/reiserfs/ibalance.c put_dc_block_number(dc, insert_ptr[k]->b_blocknr); k 915 fs/reiserfs/ibalance.c k++; k 916 fs/reiserfs/ibalance.c insert_key += k; k 917 fs/reiserfs/ibalance.c insert_ptr += k; k 918 fs/reiserfs/ibalance.c insert_num -= k; k 957 fs/reiserfs/ibalance.c k = tb->rnum[h] - n + child_pos - 1; k 964 fs/reiserfs/ibalance.c 0, k, insert_key + 1, k 967 fs/reiserfs/ibalance.c replace_rkey(tb, h, insert_key + insert_num - k - 1); k 976 fs/reiserfs/ibalance.c [insert_num - k - 1]) - k 978 fs/reiserfs/ibalance.c [insert_num - k - 1])); k 980 fs/reiserfs/ibalance.c insert_ptr[insert_num - k - k 985 fs/reiserfs/ibalance.c insert_num -= (k + 1); k 1106 fs/reiserfs/ibalance.c k = snum - n + child_pos - 1; k 1108 fs/reiserfs/ibalance.c internal_insert_childs(&dest_bi, /*S_new, */ 0, k, k 1112 fs/reiserfs/ibalance.c memcpy(&new_insert_key, insert_key + insert_num - k - 1, k 1122 fs/reiserfs/ibalance.c (insert_ptr[insert_num - k - 1]) - k 1124 fs/reiserfs/ibalance.c [insert_num - k - 1]))); k 1126 fs/reiserfs/ibalance.c insert_ptr[insert_num - k - k 1131 fs/reiserfs/ibalance.c insert_num -= (k + 1); k 499 fs/reiserfs/item_ops.c int k, l; k 502 fs/reiserfs/item_ops.c for (k = 0; k < dir_u->entry_count; k++) k 503 fs/reiserfs/item_ops.c l += dir_u->entry_sizes[k]; k 176 fs/reiserfs/prints.c char *k = fmt; k 178 fs/reiserfs/prints.c while ((k = strchr(k, '%')) != NULL) { k 179 fs/reiserfs/prints.c if (k[1] == 'k' || k[1] == 'K' || k[1] == 'h' || k[1] == 't' || k 180 fs/reiserfs/prints.c k[1] == 'z' || k[1] == 'b' || k[1] == 'y' || k[1] == 'a') { k 181 fs/reiserfs/prints.c *what = k[1]; k 184 fs/reiserfs/prints.c k++; k 186 fs/reiserfs/prints.c return k; k 206 fs/reiserfs/prints.c char *k; k 218 fs/reiserfs/prints.c while ((k = is_there_reiserfs_struct(fmt1, &what)) != NULL) { k 219 fs/reiserfs/prints.c *k = 0; k 258 fs/reiserfs/prints.c fmt1 = k + 2; k 85 fs/squashfs/block.c int bytes, compressed, b = 0, k = 0, avail, i; k 170 fs/squashfs/block.c for (bytes = length; k < b; k++) { k 180 fs/squashfs/block.c memcpy(data + pg_offset, bh[k]->b_data + offset, k 187 fs/squashfs/block.c put_bh(bh[k]); k 196 fs/squashfs/block.c for (; k < b; k++) k 197 fs/squashfs/block.c put_bh(bh[k]); k 124 fs/squashfs/xz_wrapper.c int avail, total = 0, k = 0; k 135 fs/squashfs/xz_wrapper.c if (stream->buf.in_pos == stream->buf.in_size && k < b) { k 138 fs/squashfs/xz_wrapper.c stream->buf.in = bh[k]->b_data + offset; k 154 fs/squashfs/xz_wrapper.c if (stream->buf.in_pos == stream->buf.in_size && k < b) k 155 fs/squashfs/xz_wrapper.c put_bh(bh[k++]); k 160 fs/squashfs/xz_wrapper.c if (xz_err != XZ_STREAM_END || k < b) k 166 fs/squashfs/xz_wrapper.c for (; k < b; k++) k 167 fs/squashfs/xz_wrapper.c put_bh(bh[k]); k 56 fs/squashfs/zlib_wrapper.c int zlib_err, zlib_init = 0, k = 0; k 64 fs/squashfs/zlib_wrapper.c if (stream->avail_in == 0 && k < b) { k 67 fs/squashfs/zlib_wrapper.c stream->next_in = bh[k]->b_data + offset; k 89 fs/squashfs/zlib_wrapper.c if (stream->avail_in == 0 && k < b) k 90 fs/squashfs/zlib_wrapper.c put_bh(bh[k++]); k 102 fs/squashfs/zlib_wrapper.c if (k < b) k 108 fs/squashfs/zlib_wrapper.c for (; k < b; k++) k 109 fs/squashfs/zlib_wrapper.c put_bh(bh[k]); k 69 fs/squashfs/zstd_wrapper.c int k = 0; k 84 fs/squashfs/zstd_wrapper.c if (in_buf.pos == in_buf.size && k < b) { k 88 fs/squashfs/zstd_wrapper.c in_buf.src = bh[k]->b_data + offset; k 111 fs/squashfs/zstd_wrapper.c if (in_buf.pos == in_buf.size && k < b) k 112 fs/squashfs/zstd_wrapper.c put_bh(bh[k++]); k 123 fs/squashfs/zstd_wrapper.c if (k < b) k 129 fs/squashfs/zstd_wrapper.c for (; k < b; k++) k 130 fs/squashfs/zstd_wrapper.c put_bh(bh[k]); k 284 fs/sysv/itree.c int k, err; k 287 fs/sysv/itree.c for (k = depth; k > 1 && !offsets[k-1]; k--) k 291 fs/sysv/itree.c partial = get_branch(inode, k, offsets, chain, &err); k 293 fs/sysv/itree.c partial = chain + k-1; k 310 fs/sysv/itree.c if (p == chain + k - 1 && p > chain) { k 103 fs/ubifs/key.h static inline void ino_key_init_flash(const struct ubifs_info *c, void *k, k 106 fs/ubifs/key.h union ubifs_key *key = k; k 110 fs/ubifs/key.h memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); k 182 fs/ubifs/key.h static inline void dent_key_init_flash(const struct ubifs_info *c, void *k, k 186 fs/ubifs/key.h union ubifs_key *key = k; k 193 fs/ubifs/key.h memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); k 234 fs/ubifs/key.h static inline void xent_key_init_flash(const struct ubifs_info *c, void *k, k 237 fs/ubifs/key.h union ubifs_key *key = k; k 244 fs/ubifs/key.h memset(k + 8, 0, UBIFS_MAX_KEY_LEN - 8); k 334 fs/ubifs/key.h static inline int key_type_flash(const struct ubifs_info *c, const void *k) k 336 fs/ubifs/key.h const union ubifs_key *key = k; k 346 fs/ubifs/key.h static inline ino_t key_inum(const struct ubifs_info *c, const void *k) k 348 fs/ubifs/key.h const union ubifs_key *key = k; k 358 fs/ubifs/key.h static inline ino_t key_inum_flash(const struct ubifs_info *c, const void *k) k 360 fs/ubifs/key.h const union ubifs_key *key = k; k 381 fs/ubifs/key.h static inline uint32_t key_hash_flash(const struct ubifs_info *c, const void *k) k 383 fs/ubifs/key.h const union ubifs_key *key = k; k 405 fs/ubifs/key.h const void *k) k 407 fs/ubifs/key.h const union ubifs_key *key = k; k 275 fs/ubifs/lpt.c const int k = 32 - nrbits; k 324 fs/ubifs/lpt.c val <<= k; k 325 fs/ubifs/lpt.c val >>= k; k 2787 fs/ubifs/tnc.c int i, n, k, err = 0; k 2825 fs/ubifs/tnc.c for (i = n + 1, k = 0; i < znode->child_cnt; i++, k++) { k 2838 fs/ubifs/tnc.c if (k) { k 2839 fs/ubifs/tnc.c for (i = n + 1 + k; i < znode->child_cnt; i++) k 2840 fs/ubifs/tnc.c znode->zbranch[i - k] = znode->zbranch[i]; k 2841 fs/ubifs/tnc.c znode->child_cnt -= k; k 158 fs/udf/partition.c int i, j, k, l; k 187 fs/udf/partition.c for (k = 0; k < reallocationTableLen; k++) { k 188 fs/udf/partition.c struct sparingEntry *entry = &st->mapEntry[k]; k 228 fs/udf/partition.c for (l = k; l < reallocationTableLen; l++) { k 244 fs/udf/partition.c memmove(&st->mapEntry[k + 1], k 245 fs/udf/partition.c &st->mapEntry[k], k 246 fs/udf/partition.c (l - k) * k 248 fs/udf/partition.c st->mapEntry[k] = mapEntry; k 257 fs/udf/partition.c st->mapEntry[k].mappedLocation) + k 583 fs/ufs/balloc.c for (k = count; k < uspi->s_fpb; k++) \ k 584 fs/ufs/balloc.c if (fs32_to_cpu(sb, ucg->cg_frsum[k])) \ k 594 fs/ufs/balloc.c unsigned oldcg, i, j, k, allocsize; k 375 fs/xfs/libxfs/xfs_alloc.c xfs_extlen_t k; k 385 fs/xfs/libxfs/xfs_alloc.c k = rlen % args->prod; k 386 fs/xfs/libxfs/xfs_alloc.c if (k == args->mod) k 388 fs/xfs/libxfs/xfs_alloc.c if (k > args->mod) k 389 fs/xfs/libxfs/xfs_alloc.c rlen = rlen - (k - args->mod); k 391 fs/xfs/libxfs/xfs_alloc.c rlen = rlen - args->prod + (args->mod - k); k 1071 fs/xfs/libxfs/xfs_format.h #define XFS_INO_MASK(k) (uint32_t)((1ULL << (k)) - 1) k 1564 fs/xfs/libxfs/xfs_format.h static inline xfs_fsblock_t nullstartblock(int k) k 1566 fs/xfs/libxfs/xfs_format.h ASSERT(k < (1 << STARTBLOCKVALBITS)); k 1567 fs/xfs/libxfs/xfs_format.h return STARTBLOCKMASK | (k); k 1611 fs/xfs/xfs_log.c int i, j, k; k 1632 fs/xfs/xfs_log.c k = i % (XLOG_HEADER_CYCLE_SIZE / BBSIZE); k 1633 fs/xfs/xfs_log.c xhdr[j].hic_xheader.xh_cycle_data[k] = *(__be32 *)dp; k 3813 fs/xfs/xfs_log.c int len, i, j, k, op_len; k 3855 fs/xfs/xfs_log.c k = idx % (XLOG_HEADER_CYCLE_SIZE / BBSIZE); k 3857 fs/xfs/xfs_log.c xhdr[j].hic_xheader.xh_cycle_data[k]); k 3879 fs/xfs/xfs_log.c k = idx % (XLOG_HEADER_CYCLE_SIZE / BBSIZE); k 3880 fs/xfs/xfs_log.c op_len = be32_to_cpu(xhdr[j].hic_xheader.xh_cycle_data[k]); k 5107 fs/xfs/xfs_log_recover.c int i, j, k; k 5119 fs/xfs/xfs_log_recover.c k = i % (XLOG_HEADER_CYCLE_SIZE / BBSIZE); k 5120 fs/xfs/xfs_log_recover.c *(__be32 *)dp = xhdr[j].hic_xheader.xh_cycle_data[k]; k 66 include/asm-generic/termios-base.h #define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) k 70 include/asm-generic/termios-base.h #define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) k 73 include/asm-generic/termios-base.h #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) k 74 include/asm-generic/termios-base.h #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) k 71 include/asm-generic/termios.h static inline int user_termios_to_kernel_termios(struct ktermios *k, k 74 include/asm-generic/termios.h return copy_from_user(k, u, sizeof(struct termios2)); k 78 include/asm-generic/termios.h struct ktermios *k) k 80 include/asm-generic/termios.h return copy_to_user(u, k, sizeof(struct termios2)); k 83 include/asm-generic/termios.h static inline int user_termios_to_kernel_termios_1(struct ktermios *k, k 86 include/asm-generic/termios.h return copy_from_user(k, u, sizeof(struct termios)); k 90 include/asm-generic/termios.h struct ktermios *k) k 92 include/asm-generic/termios.h return copy_to_user(u, k, sizeof(struct termios)); k 95 include/asm-generic/termios.h static inline int user_termios_to_kernel_termios(struct ktermios *k, k 98 include/asm-generic/termios.h return copy_from_user(k, u, sizeof(struct termios)); k 102 include/asm-generic/termios.h struct ktermios *k) k 104 include/asm-generic/termios.h return copy_to_user(u, k, sizeof(struct termios)); k 148 include/asm-generic/uaccess.h #define __put_user_fn(sz, u, k) __put_user_fn(sz, u, k) k 209 include/asm-generic/uaccess.h #define __get_user_fn(sz, u, k) __get_user_fn(sz, u, k) k 18 include/crypto/twofish.h u32 s[4][256], w[8], k[32]; k 107 include/drm/drm_edid.h u8 k; k 213 include/drm/drm_hdcp.h __be16 k; k 62 include/drm/i915_mei_hdcp_interface.h u16 k; k 357 include/kvm/arm_vgic.h #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) k 358 include/kvm/arm_vgic.h #define vgic_initialized(k) ((k)->arch.vgic.initialized) k 359 include/kvm/arm_vgic.h #define vgic_ready(k) ((k)->arch.vgic.ready) k 360 include/kvm/arm_vgic.h #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ k 361 include/kvm/arm_vgic.h ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) k 1120 include/linux/filter.h if (first->k == SKF_AD_OFF + SKF_AD_ALU_XOR_X) k 1139 include/linux/filter.h switch (ftest->k) { k 1164 include/linux/filter.h int k, unsigned int size); k 1166 include/linux/filter.h static inline void *bpf_load_pointer(const struct sk_buff *skb, int k, k 1169 include/linux/filter.h if (k >= 0) k 1170 include/linux/filter.h return skb_header_pointer(skb, k, size, buffer); k 1172 include/linux/filter.h return bpf_internal_load_pointer_neg_helper(skb, k, size); k 16 include/linux/input/matrix_keypad.h #define KEY_ROW(k) (((k) >> 24) & 0xff) k 17 include/linux/input/matrix_keypad.h #define KEY_COL(k) (((k) >> 16) & 0xff) k 18 include/linux/input/matrix_keypad.h #define KEY_VAL(k) ((k) & 0xffff) k 73 include/linux/jhash.h const u8 *k = key; k 80 include/linux/jhash.h a += __get_unaligned_cpu32(k); k 81 include/linux/jhash.h b += __get_unaligned_cpu32(k + 4); k 82 include/linux/jhash.h c += __get_unaligned_cpu32(k + 8); k 85 include/linux/jhash.h k += 12; k 89 include/linux/jhash.h case 12: c += (u32)k[11]<<24; /* fall through */ k 90 include/linux/jhash.h case 11: c += (u32)k[10]<<16; /* fall through */ k 91 include/linux/jhash.h case 10: c += (u32)k[9]<<8; /* fall through */ k 92 include/linux/jhash.h case 9: c += k[8]; /* fall through */ k 93 include/linux/jhash.h case 8: b += (u32)k[7]<<24; /* fall through */ k 94 include/linux/jhash.h case 7: b += (u32)k[6]<<16; /* fall through */ k 95 include/linux/jhash.h case 6: b += (u32)k[5]<<8; /* fall through */ k 96 include/linux/jhash.h case 5: b += k[4]; /* fall through */ k 97 include/linux/jhash.h case 4: a += (u32)k[3]<<24; /* fall through */ k 98 include/linux/jhash.h case 3: a += (u32)k[2]<<16; /* fall through */ k 99 include/linux/jhash.h case 2: a += (u32)k[1]<<8; /* fall through */ k 100 include/linux/jhash.h case 1: a += k[0]; k 116 include/linux/jhash.h static inline u32 jhash2(const u32 *k, u32 length, u32 initval) k 125 include/linux/jhash.h a += k[0]; k 126 include/linux/jhash.h b += k[1]; k 127 include/linux/jhash.h c += k[2]; k 130 include/linux/jhash.h k += 3; k 135 include/linux/jhash.h case 3: c += k[2]; /* fall through */ k 136 include/linux/jhash.h case 2: b += k[1]; /* fall through */ k 137 include/linux/jhash.h case 1: a += k[0]; k 326 include/linux/jump_label.h #define static_key_enable_cpuslocked(k) static_key_enable((k)) k 327 include/linux/jump_label.h #define static_key_disable_cpuslocked(k) static_key_disable((k)) k 482 include/linux/key.h #define key_validate(k) 0 k 483 include/linux/key.h #define key_serial(k) 0 k 484 include/linux/key.h #define key_get(k) ({ NULL; }) k 485 include/linux/key.h #define key_revoke(k) do { } while(0) k 486 include/linux/key.h #define key_invalidate(k) do { } while(0) k 487 include/linux/key.h #define key_put(k) do { } while(0) k 488 include/linux/key.h #define key_ref_put(k) do { } while(0) k 489 include/linux/key.h #define make_key_ref(k, p) NULL k 490 include/linux/key.h #define key_ref_to_ptr(k) NULL k 491 include/linux/key.h #define is_key_possessed(k) 0 k 34 include/linux/klist.h extern void klist_init(struct klist *k, void (*get)(struct klist_node *), k 43 include/linux/klist.h extern void klist_add_tail(struct klist_node *n, struct klist *k); k 44 include/linux/klist.h extern void klist_add_head(struct klist_node *n, struct klist *k); k 60 include/linux/klist.h extern void klist_iter_init(struct klist *k, struct klist_iter *i); k 61 include/linux/klist.h extern void klist_iter_init_node(struct klist *k, struct klist_iter *i, k 212 include/linux/kobject.h static inline struct kset *kset_get(struct kset *k) k 214 include/linux/kobject.h return k ? to_kset(kobject_get(&k->kobj)) : NULL; k 217 include/linux/kobject.h static inline void kset_put(struct kset *k) k 219 include/linux/kobject.h kobject_put(&k->kobj); k 52 include/linux/kthread.h void free_kthread_struct(struct task_struct *k); k 53 include/linux/kthread.h void kthread_bind(struct task_struct *k, unsigned int cpu); k 54 include/linux/kthread.h void kthread_bind_mask(struct task_struct *k, const struct cpumask *mask); k 55 include/linux/kthread.h int kthread_stop(struct task_struct *k); k 58 include/linux/kthread.h bool __kthread_should_park(struct task_struct *k); k 60 include/linux/kthread.h void *kthread_data(struct task_struct *k); k 61 include/linux/kthread.h void *kthread_probe_data(struct task_struct *k); k 62 include/linux/kthread.h int kthread_park(struct task_struct *k); k 63 include/linux/kthread.h void kthread_unpark(struct task_struct *k); k 433 include/linux/lockdep.h # define lock_set_class(l, n, k, s, i) do { } while (0) k 501 include/linux/lockdep.h #define lockdep_init_map_crosslock(m, n, k, s) do {} while (0) k 159 include/linux/mempolicy.h static inline void check_highest_zone(enum zone_type k) k 161 include/linux/mempolicy.h if (k > policy_zone && k != ZONE_MOVABLE) k 162 include/linux/mempolicy.h policy_zone = k; k 291 include/linux/mempolicy.h static inline void check_highest_zone(int k) k 128 include/linux/mmc/sh_mmcif.h int k; k 141 include/linux/mmc/sh_mmcif.h for (k = 0; k < (SH_MMCIF_BBS / 4); k++) k 142 include/linux/mmc/sh_mmcif.h buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA); k 152 include/linux/mmc/sh_mmcif.h unsigned long k; k 169 include/linux/mmc/sh_mmcif.h for (k = 0; !ret && k < nr_blocks; k++) k 170 include/linux/mmc/sh_mmcif.h ret = sh_mmcif_boot_do_read_single(base, first_block + k, k 171 include/linux/mmc/sh_mmcif.h buf + (k * SH_MMCIF_BBS)); k 678 include/linux/slab.h static inline void *kmem_cache_zalloc(struct kmem_cache *k, gfp_t flags) k 680 include/linux/slab.h return kmem_cache_alloc(k, flags | __GFP_ZERO); k 423 include/linux/sysfs.h static inline int sysfs_rename_link_ns(struct kobject *k, struct kobject *t, k 430 include/linux/sysfs.h static inline void sysfs_delete_link(struct kobject *k, struct kobject *t, k 178 include/linux/workqueue.h #define __WORK_INIT_LOCKDEP_MAP(n, k) \ k 179 include/linux/workqueue.h .lockdep_map = STATIC_LOCKDEP_MAP_INIT(n, k), k 181 include/linux/workqueue.h #define __WORK_INIT_LOCKDEP_MAP(n, k) k 84 include/linux/zutil.h int k; k 89 include/linux/zutil.h k = len < NMAX ? len : NMAX; k 90 include/linux/zutil.h len -= k; k 91 include/linux/zutil.h while (k >= 16) { k 94 include/linux/zutil.h k -= 16; k 96 include/linux/zutil.h if (k != 0) do { k 99 include/linux/zutil.h } while (--k); k 54 include/net/llc_conn.h u8 k; /* tx window size; max = 127 */ k 581 include/net/xfrm.h const struct xfrm_kmaddress *k, k 1660 include/net/xfrm.h const struct xfrm_kmaddress *k, k 1668 include/net/xfrm.h struct xfrm_kmaddress *k, struct net *net, k 104 include/sound/soc-topology.h struct snd_kcontrol *k, int event); k 42 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 43 include/trace/events/bcache.h TP_ARGS(k), k 53 include/trace/events/bcache.h __entry->inode = KEY_INODE(k); k 54 include/trace/events/bcache.h __entry->offset = KEY_OFFSET(k); k 55 include/trace/events/bcache.h __entry->size = KEY_SIZE(k); k 56 include/trace/events/bcache.h __entry->dirty = KEY_DIRTY(k); k 188 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 189 include/trace/events/bcache.h TP_ARGS(k) k 210 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 211 include/trace/events/bcache.h TP_ARGS(k) k 322 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 323 include/trace/events/bcache.h TP_ARGS(k) k 327 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 328 include/trace/events/bcache.h TP_ARGS(k) k 332 include/trace/events/bcache.h TP_PROTO(struct btree *b, struct bkey *k, unsigned op, unsigned status), k 333 include/trace/events/bcache.h TP_ARGS(b, k, op, status), k 349 include/trace/events/bcache.h __entry->inode = KEY_INODE(k); k 350 include/trace/events/bcache.h __entry->offset = KEY_OFFSET(k); k 351 include/trace/events/bcache.h __entry->size = KEY_SIZE(k); k 352 include/trace/events/bcache.h __entry->dirty = KEY_DIRTY(k); k 492 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 493 include/trace/events/bcache.h TP_ARGS(k) k 497 include/trace/events/bcache.h TP_PROTO(struct bkey *k), k 498 include/trace/events/bcache.h TP_ARGS(k) k 12 include/uapi/linux/bcache.h static inline __u64 name(const type *k) \ k 13 include/uapi/linux/bcache.h { return (k->field >> offset) & ~(~0ULL << size); } \ k 15 include/uapi/linux/bcache.h static inline void SET_##name(type *k, __u64 v) \ k 17 include/uapi/linux/bcache.h k->field &= ~(~(~0ULL << size) << offset); \ k 18 include/uapi/linux/bcache.h k->field |= (v & ~(~0ULL << size)) << offset; \ k 33 include/uapi/linux/bcache.h static inline __u64 name(const struct bkey *k, unsigned int i) \ k 34 include/uapi/linux/bcache.h { return (k->ptr[i] >> offset) & ~(~0ULL << size); } \ k 36 include/uapi/linux/bcache.h static inline void SET_##name(struct bkey *k, unsigned int i, __u64 v) \ k 38 include/uapi/linux/bcache.h k->ptr[i] &= ~(~(~0ULL << size) << offset); \ k 39 include/uapi/linux/bcache.h k->ptr[i] |= (v & ~(~0ULL << size)) << offset; \ k 56 include/uapi/linux/bcache.h static inline __u64 KEY_OFFSET(const struct bkey *k) k 58 include/uapi/linux/bcache.h return k->low; k 61 include/uapi/linux/bcache.h static inline void SET_KEY_OFFSET(struct bkey *k, __u64 v) k 63 include/uapi/linux/bcache.h k->low = v; k 83 include/uapi/linux/bcache.h #define KEY_START(k) (KEY_OFFSET(k) - KEY_SIZE(k)) k 84 include/uapi/linux/bcache.h #define START_KEY(k) KEY(KEY_INODE(k), KEY_START(k), 0) k 99 include/uapi/linux/bcache.h static inline unsigned long bkey_u64s(const struct bkey *k) k 101 include/uapi/linux/bcache.h return (sizeof(struct bkey) / sizeof(__u64)) + KEY_PTRS(k); k 104 include/uapi/linux/bcache.h static inline unsigned long bkey_bytes(const struct bkey *k) k 106 include/uapi/linux/bcache.h return bkey_u64s(k) * sizeof(__u64); k 117 include/uapi/linux/bcache.h static inline struct bkey *bkey_next(const struct bkey *k) k 119 include/uapi/linux/bcache.h __u64 *d = (void *) k; k 121 include/uapi/linux/bcache.h return (struct bkey *) (d + bkey_u64s(k)); k 124 include/uapi/linux/bcache.h static inline struct bkey *bkey_idx(const struct bkey *k, unsigned int nr_keys) k 126 include/uapi/linux/bcache.h __u64 *d = (void *) k; k 28 include/uapi/linux/filter.h __u32 k; /* Generic multiuse field */ k 49 include/uapi/linux/filter.h #define BPF_STMT(code, k) { (unsigned short)(code), 0, 0, k } k 52 include/uapi/linux/filter.h #define BPF_JUMP(code, k, jt, jf) { (unsigned short)(code), jt, jf, k } k 20 include/uapi/linux/gsmmux.h unsigned int k; k 172 include/uapi/misc/xilinx_sdfec.h __u32 k; k 297 kernel/audit.h #define audit_to_watch(k, p, l, o) (-EINVAL) k 298 kernel/audit.h #define audit_add_watch(k, l) (-EINVAL) k 299 kernel/audit.h #define audit_remove_watch_rule(k) BUG() k 303 kernel/audit.h #define audit_alloc_mark(k, p, l) (ERR_PTR(-EINVAL)) k 306 kernel/audit.h #define audit_remove_mark_rule(k) k 62 kernel/bpf/core.c void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb, int k, unsigned int size) k 66 kernel/bpf/core.c if (k >= SKF_NET_OFF) k 67 kernel/bpf/core.c ptr = skb_network_header(skb) + k - SKF_NET_OFF; k 68 kernel/bpf/core.c else if (k >= SKF_LL_OFF) k 69 kernel/bpf/core.c ptr = skb_mac_header(skb) + k - SKF_LL_OFF; k 543 kernel/bpf/devmap.c int k = *(u32 *)key; k 545 kernel/bpf/devmap.c if (k >= map->max_entries) k 556 kernel/bpf/devmap.c old_dev = xchg(&dtab->netdev_map[k], NULL); k 566 kernel/bpf/devmap.c int k = *(u32 *)key; k 572 kernel/bpf/devmap.c old_dev = __dev_map_hash_lookup_elem(map, k); k 284 kernel/bpf/xskmap.c int k = *(u32 *)key; k 286 kernel/bpf/xskmap.c if (k >= map->max_entries) k 290 kernel/bpf/xskmap.c map_entry = &m->xsk_map[k]; k 739 kernel/cgroup/cpuset.c int i, j, k; /* indices for partition finding loops */ k 826 kernel/cgroup/cpuset.c for (k = 0; k < csn; k++) { k 827 kernel/cgroup/cpuset.c struct cpuset *c = csa[k]; k 201 kernel/compat.c unsigned long *k; k 208 kernel/compat.c k = cpumask_bits(new_mask); k 209 kernel/compat.c return compat_get_bitmap(k, user_mask_ptr, len * 8); k 1068 kernel/kexec_file.c int i, k; k 1087 kernel/kexec_file.c for (k = 0; k < sechdrs[i].sh_size/sizeof(Elf_Sym); k++) { k 1088 kernel/kexec_file.c if (ELF_ST_BIND(syms[k].st_info) != STB_GLOBAL) k 1091 kernel/kexec_file.c if (strcmp(strtab + syms[k].st_name, name) != 0) k 1094 kernel/kexec_file.c if (syms[k].st_shndx == SHN_UNDEF || k 1095 kernel/kexec_file.c syms[k].st_shndx >= ehdr->e_shnum) { k 1097 kernel/kexec_file.c name, syms[k].st_shndx); k 1102 kernel/kexec_file.c return &syms[k]; k 73 kernel/kthread.c static inline struct kthread *to_kthread(struct task_struct *k) k 75 kernel/kthread.c WARN_ON(!(k->flags & PF_KTHREAD)); k 76 kernel/kthread.c return (__force void *)k->set_child_tid; k 79 kernel/kthread.c void free_kthread_struct(struct task_struct *k) k 87 kernel/kthread.c kthread = to_kthread(k); k 107 kernel/kthread.c bool __kthread_should_park(struct task_struct *k) k 109 kernel/kthread.c return test_bit(KTHREAD_SHOULD_PARK, &to_kthread(k)->flags); k 472 kernel/kthread.c void kthread_unpark(struct task_struct *k) k 474 kernel/kthread.c struct kthread *kthread = to_kthread(k); k 481 kernel/kthread.c __kthread_bind(k, kthread->cpu, TASK_PARKED); k 487 kernel/kthread.c wake_up_state(k, TASK_PARKED); k 503 kernel/kthread.c int kthread_park(struct task_struct *k) k 505 kernel/kthread.c struct kthread *kthread = to_kthread(k); k 507 kernel/kthread.c if (WARN_ON(k->flags & PF_EXITING)) k 514 kernel/kthread.c if (k != current) { k 515 kernel/kthread.c wake_up_process(k); k 525 kernel/kthread.c WARN_ON_ONCE(!wait_task_inactive(k, TASK_PARKED)); k 547 kernel/kthread.c int kthread_stop(struct task_struct *k) k 552 kernel/kthread.c trace_sched_kthread_stop(k); k 554 kernel/kthread.c get_task_struct(k); k 555 kernel/kthread.c kthread = to_kthread(k); k 557 kernel/kthread.c kthread_unpark(k); k 558 kernel/kthread.c wake_up_process(k); k 560 kernel/kthread.c ret = k->exit_code; k 561 kernel/kthread.c put_task_struct(k); k 1116 kernel/locking/lockdep.c struct lock_class_key *k; k 1126 kernel/locking/lockdep.c hlist_for_each_entry_rcu(k, hash_head, hash_entry) { k 1127 kernel/locking/lockdep.c if (WARN_ON_ONCE(k == key)) k 1142 kernel/locking/lockdep.c struct lock_class_key *k; k 1159 kernel/locking/lockdep.c hlist_for_each_entry_rcu(k, hash_head, hash_entry) { k 1160 kernel/locking/lockdep.c if (k == key) { k 5175 kernel/locking/lockdep.c struct lock_class_key *k; k 5190 kernel/locking/lockdep.c hlist_for_each_entry_rcu(k, hash_head, hash_entry) { k 5191 kernel/locking/lockdep.c if (k == key) { k 5192 kernel/locking/lockdep.c hlist_del_rcu(&k->hash_entry); k 21 kernel/locking/rtmutex.h #define debug_rt_mutex_init(m, n, k) do { } while (0) k 245 kernel/power/hibernate.c unsigned int k; k 253 kernel/power/hibernate.c k = nr_pages * (PAGE_SIZE / 1024); k 254 kernel/power/hibernate.c kps = (k * 100) / centisecs; k 256 kernel/power/hibernate.c msg, k, centisecs / 100, centisecs % 100, kps / 1000, k 100 kernel/power/swap.c unsigned int k; k 429 kernel/power/swap.c handle->k = 0; k 452 kernel/power/swap.c handle->cur->entries[handle->k++] = offset; k 453 kernel/power/swap.c if (handle->k >= MAP_PAGE_ENTRIES) { k 463 kernel/power/swap.c handle->k = 0; k 1002 kernel/power/swap.c handle->k = 0; k 1016 kernel/power/swap.c offset = handle->cur->entries[handle->k]; k 1022 kernel/power/swap.c if (++handle->k >= MAP_PAGE_ENTRIES) { k 1023 kernel/power/swap.c handle->k = 0; k 1300 kernel/power/swap.c handle->cur->entries[handle->k]) { k 1257 kernel/printk/printk.c unsigned long long k; k 1265 kernel/printk/printk.c k = (unsigned long long)loops_per_msec * boot_delay; k 1268 kernel/printk/printk.c while (k) { k 1269 kernel/printk/printk.c k--; k 127 kernel/range.c int i, j, k = az - 1, nr_range = az; k 129 kernel/range.c for (i = 0; i < k; i++) { k 132 kernel/range.c for (j = k; j > i; j--) { k 134 kernel/range.c k = j; k 140 kernel/range.c range[i].start = range[k].start; k 141 kernel/range.c range[i].end = range[k].end; k 142 kernel/range.c range[k].start = 0; k 143 kernel/range.c range[k].end = 0; k 144 kernel/range.c k--; k 1560 kernel/sched/topology.c int i, j, k; k 1580 kernel/sched/topology.c for (k = 0; k < nr_node_ids; k++) { k 1581 kernel/sched/topology.c int distance = node_distance(i, k); k 1593 kernel/sched/topology.c if (sched_debug() && node_distance(k, i) != distance) k 1652 kernel/sched/topology.c for_each_node(k) { k 1653 kernel/sched/topology.c if (node_distance(j, k) > sched_domains_numa_distance[i]) k 1656 kernel/sched/topology.c cpumask_or(mask, mask, cpumask_of_node(k)); k 180 kernel/seccomp.c u32 k = ftest->k; k 186 kernel/seccomp.c if (k >= sizeof(struct seccomp_data) || k & 3) k 191 kernel/seccomp.c ftest->k = sizeof(struct seccomp_data); k 195 kernel/seccomp.c ftest->k = sizeof(struct seccomp_data); k 3961 kernel/signal.c struct k_sigaction *k; k 3967 kernel/signal.c k = &p->sighand->action[sig-1]; k 3971 kernel/signal.c *oact = *k; k 3978 kernel/signal.c *k = *act; k 4835 kernel/trace/trace_events_hist.c unsigned int i, j, k; k 4879 kernel/trace/trace_events_hist.c for (j = 1, k = 1; j < hist_data->n_fields; j++) { k 4886 kernel/trace/trace_events_hist.c idx = k++; k 223 kernel/user_namespace.c static int cmp_map_id(const void *k, const void *e) k 226 kernel/user_namespace.c const struct idmap_key *key = k; k 395 lib/bch.c int k, pp = -1; k 408 lib/bch.c k = 2*i-pp; k 415 lib/bch.c elp->c[j+k] ^= a_pow(bch, tmp+l); k 419 lib/bch.c tmp = pelp->deg+k; k 447 lib/bch.c int rem, c, r, p, k, param[BCH_MAX_M]; k 449 lib/bch.c k = 0; k 455 lib/bch.c p = c-k; k 477 lib/bch.c param[k++] = c; k 482 lib/bch.c if (k > 0) { k 483 lib/bch.c p = k; k 485 lib/bch.c if ((r > m-1-k) && rows[r]) k 494 lib/bch.c if (nsol != (1 << k)) k 500 lib/bch.c for (c = 0; c < k; c++) k 522 lib/bch.c int i, j, k; k 527 lib/bch.c k = a_log(bch, a); k 533 lib/bch.c (a ? bch->a_pow_tab[mod_s(bch, k)] : 0)^ k 536 lib/bch.c k += 2; k 543 lib/bch.c for (k = 0; k < 16; k = (k+j+1) & ~j) { k 544 lib/bch.c t = ((rows[k] >> j)^rows[k+j]) & mask; k 545 lib/bch.c rows[k] ^= (t << j); k 546 lib/bch.c rows[k+j] ^= t; k 805 lib/bch.c static void compute_trace_bk_mod(struct bch_control *bch, int k, k 815 lib/bch.c z->c[1] = bch->a_pow_tab[k]; k 842 lib/bch.c dbg("Tr(a^%d.X) mod f = %s\n", k, gf_poly_str(out)); k 848 lib/bch.c static void factor_polynomial(struct bch_control *bch, int k, struct gf_poly *f, k 863 lib/bch.c compute_trace_bk_mod(bch, k, f, z, tk); k 884 lib/bch.c static int find_poly_roots(struct bch_control *bch, unsigned int k, k 907 lib/bch.c if (poly->deg && (k <= GF_M(bch))) { k 908 lib/bch.c factor_polynomial(bch, k, poly, &f1, &f2); k 910 lib/bch.c cnt += find_poly_roots(bch, k+1, f1, roots); k 912 lib/bch.c cnt += find_poly_roots(bch, k+1, f2, roots+cnt); k 929 lib/bch.c const unsigned int k = 8*len+bch->ecc_bits; k 936 lib/bch.c for (i = GF_N(bch)-k+1; i <= GF_N(bch); i++) { k 1064 lib/bch.c const unsigned int k = 1 << deg(poly); k 1067 lib/bch.c if (k != (1u << GF_M(bch))) k 1077 lib/bch.c if (x & k) k 49 lib/bitmap.c unsigned int k, lim = bits/BITS_PER_LONG; k 50 lib/bitmap.c for (k = 0; k < lim; ++k) k 51 lib/bitmap.c if (bitmap1[k] != bitmap2[k]) k 55 lib/bitmap.c if ((bitmap1[k] ^ bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) k 67 lib/bitmap.c unsigned int k, lim = bits / BITS_PER_LONG; k 70 lib/bitmap.c for (k = 0; k < lim; ++k) { k 71 lib/bitmap.c if ((bitmap1[k] | bitmap2[k]) != bitmap3[k]) k 78 lib/bitmap.c tmp = (bitmap1[k] | bitmap2[k]) ^ bitmap3[k]; k 84 lib/bitmap.c unsigned int k, lim = BITS_TO_LONGS(bits); k 85 lib/bitmap.c for (k = 0; k < lim; ++k) k 86 lib/bitmap.c dst[k] = ~src[k]; k 104 lib/bitmap.c unsigned k, lim = BITS_TO_LONGS(nbits); k 107 lib/bitmap.c for (k = 0; off + k < lim; ++k) { k 114 lib/bitmap.c if (!rem || off + k + 1 >= lim) k 117 lib/bitmap.c upper = src[off + k + 1]; k 118 lib/bitmap.c if (off + k + 1 == lim - 1) k 122 lib/bitmap.c lower = src[off + k]; k 123 lib/bitmap.c if (off + k == lim - 1) k 126 lib/bitmap.c dst[k] = lower | upper; k 149 lib/bitmap.c int k; k 152 lib/bitmap.c for (k = lim - off - 1; k >= 0; --k) { k 159 lib/bitmap.c if (rem && k > 0) k 160 lib/bitmap.c lower = src[k - 1] >> (BITS_PER_LONG - rem); k 163 lib/bitmap.c upper = src[k] << rem; k 164 lib/bitmap.c dst[k + off] = lower | upper; k 174 lib/bitmap.c unsigned int k; k 178 lib/bitmap.c for (k = 0; k < lim; k++) k 179 lib/bitmap.c result |= (dst[k] = bitmap1[k] & bitmap2[k]); k 181 lib/bitmap.c result |= (dst[k] = bitmap1[k] & bitmap2[k] & k 190 lib/bitmap.c unsigned int k; k 193 lib/bitmap.c for (k = 0; k < nr; k++) k 194 lib/bitmap.c dst[k] = bitmap1[k] | bitmap2[k]; k 201 lib/bitmap.c unsigned int k; k 204 lib/bitmap.c for (k = 0; k < nr; k++) k 205 lib/bitmap.c dst[k] = bitmap1[k] ^ bitmap2[k]; k 212 lib/bitmap.c unsigned int k; k 216 lib/bitmap.c for (k = 0; k < lim; k++) k 217 lib/bitmap.c result |= (dst[k] = bitmap1[k] & ~bitmap2[k]); k 219 lib/bitmap.c result |= (dst[k] = bitmap1[k] & ~bitmap2[k] & k 228 lib/bitmap.c unsigned int k, lim = bits/BITS_PER_LONG; k 229 lib/bitmap.c for (k = 0; k < lim; ++k) k 230 lib/bitmap.c if (bitmap1[k] & bitmap2[k]) k 234 lib/bitmap.c if ((bitmap1[k] & bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) k 243 lib/bitmap.c unsigned int k, lim = bits/BITS_PER_LONG; k 244 lib/bitmap.c for (k = 0; k < lim; ++k) k 245 lib/bitmap.c if (bitmap1[k] & ~bitmap2[k]) k 249 lib/bitmap.c if ((bitmap1[k] & ~bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) k 257 lib/bitmap.c unsigned int k, lim = bits/BITS_PER_LONG; k 260 lib/bitmap.c for (k = 0; k < lim; k++) k 261 lib/bitmap.c w += hweight_long(bitmap[k]); k 264 lib/bitmap.c w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); k 15 lib/crypto/arc4.c int i, j = 0, k = 0; k 26 lib/crypto/arc4.c j = (j + in_key[k] + a) & 0xff; k 29 lib/crypto/arc4.c if (++k >= key_len) k 30 lib/crypto/arc4.c k = 0; k 623 lib/crypto/des.c static unsigned long des_ekey(u32 *pe, const u8 *k) k 629 lib/crypto/des.c d = k[4]; d &= 0x0e; d <<= 4; d |= k[0] & 0x1e; d = pc1[d]; k 630 lib/crypto/des.c c = k[5]; c &= 0x0e; c <<= 4; c |= k[1] & 0x1e; c = pc1[c]; k 631 lib/crypto/des.c b = k[6]; b &= 0x0e; b <<= 4; b |= k[2] & 0x1e; b = pc1[b]; k 632 lib/crypto/des.c a = k[7]; a &= 0x0e; a <<= 4; a |= k[3] & 0x1e; a = pc1[a]; k 657 lib/crypto/des.c d = k[0]; d &= 0xe0; d >>= 4; d |= k[4] & 0xf0; d = pc1[d + 1]; k 658 lib/crypto/des.c c = k[1]; c &= 0xe0; c >>= 4; c |= k[5] & 0xf0; c = pc1[c + 1]; k 659 lib/crypto/des.c b = k[2]; b &= 0xe0; b >>= 4; b |= k[6] & 0xf0; b = pc1[b + 1]; k 660 lib/crypto/des.c a = k[3]; a &= 0xe0; a >>= 4; a |= k[7] & 0xf0; a = pc1[a + 1]; k 714 lib/crypto/des.c static void dkey(u32 *pe, const u8 *k) k 720 lib/crypto/des.c d = k[4]; d &= 0x0e; d <<= 4; d |= k[0] & 0x1e; d = pc1[d]; k 721 lib/crypto/des.c c = k[5]; c &= 0x0e; c <<= 4; c |= k[1] & 0x1e; c = pc1[c]; k 722 lib/crypto/des.c b = k[6]; b &= 0x0e; b <<= 4; b |= k[2] & 0x1e; b = pc1[b]; k 723 lib/crypto/des.c a = k[7]; a &= 0x0e; a <<= 4; a |= k[3] & 0x1e; a = pc1[a]; k 745 lib/crypto/des.c d = k[0]; d &= 0xe0; d >>= 4; d |= k[4] & 0xf0; d = pc1[d + 1]; k 746 lib/crypto/des.c c = k[1]; c &= 0xe0; c >>= 4; c |= k[5] & 0xf0; c = pc1[c + 1]; k 747 lib/crypto/des.c b = k[2]; b &= 0xe0; b >>= 4; b |= k[6] & 0xf0; b = pc1[b + 1]; k 748 lib/crypto/des.c a = k[3]; a &= 0xe0; a >>= 4; a |= k[7] & 0xf0; a = pc1[a + 1]; k 162 lib/decompress_bunzip2.c i, j, k, t, runPos, symCount, symTotal, nSelectors, *byteCount; k 199 lib/decompress_bunzip2.c k = get_bits(bd, 16); k 201 lib/decompress_bunzip2.c if (k&(1 << (15-j))) k 258 lib/decompress_bunzip2.c k = get_bits(bd, 2); k 259 lib/decompress_bunzip2.c if (k < 2) { k 265 lib/decompress_bunzip2.c t += (((k+1)&2)-1); k 489 lib/decompress_bunzip2.c k = j+byteCount[i]; k 491 lib/decompress_bunzip2.c j = k; k 234 lib/inflate.c #define NEEDBITS(n) {while(k<(n)){b|=((ulg)NEXTBYTE())<<k;k+=8;}} k 235 lib/inflate.c #define DUMPBITS(n) {b>>=(n);k-=(n);} k 343 lib/inflate.c register int k; /* number of bits in current code */ k 397 lib/inflate.c k = j; /* minimum code length */ k 454 lib/inflate.c for (; k <= g; k++) k 457 lib/inflate.c a = c[k]; k 463 lib/inflate.c while (k > w + l) k 471 lib/inflate.c if ((f = 1 << (j = k - w)) > a + 1) /* try a k-w bit table */ k 475 lib/inflate.c xp = c + k; k 518 lib/inflate.c r.b = (uch)(k - w); k 535 lib/inflate.c f = 1 << (k - w); k 540 lib/inflate.c for (j = 1 << (k - 1); i & j; j >>= 1) k 604 lib/inflate.c register unsigned k; /* number of bits in bit buffer */ k 609 lib/inflate.c k = bk; k 693 lib/inflate.c bk = k; k 710 lib/inflate.c register unsigned k; /* number of bits in bit buffer */ k 716 lib/inflate.c k = bk; k 721 lib/inflate.c n = k & 7; k 752 lib/inflate.c bk = k; k 846 lib/inflate.c register unsigned k; /* number of bits in bit buffer */ k 862 lib/inflate.c k = bk; k 972 lib/inflate.c bk = k; k 1041 lib/inflate.c register unsigned k; /* number of bits in bit buffer */ k 1047 lib/inflate.c k = bk; k 1064 lib/inflate.c bk = k; k 1154 lib/inflate.c int k; /* byte being shifted into crc apparatus */ k 1169 lib/inflate.c for (k = i | 256; k != 1; k >>= 1) k 1172 lib/inflate.c if (k & 1) k 84 lib/klist.c void klist_init(struct klist *k, void (*get)(struct klist_node *), k 87 lib/klist.c INIT_LIST_HEAD(&k->k_list); k 88 lib/klist.c spin_lock_init(&k->k_lock); k 89 lib/klist.c k->get = get; k 90 lib/klist.c k->put = put; k 94 lib/klist.c static void add_head(struct klist *k, struct klist_node *n) k 96 lib/klist.c spin_lock(&k->k_lock); k 97 lib/klist.c list_add(&n->n_node, &k->k_list); k 98 lib/klist.c spin_unlock(&k->k_lock); k 101 lib/klist.c static void add_tail(struct klist *k, struct klist_node *n) k 103 lib/klist.c spin_lock(&k->k_lock); k 104 lib/klist.c list_add_tail(&n->n_node, &k->k_list); k 105 lib/klist.c spin_unlock(&k->k_lock); k 108 lib/klist.c static void klist_node_init(struct klist *k, struct klist_node *n) k 112 lib/klist.c knode_set_klist(n, k); k 113 lib/klist.c if (k->get) k 114 lib/klist.c k->get(n); k 122 lib/klist.c void klist_add_head(struct klist_node *n, struct klist *k) k 124 lib/klist.c klist_node_init(k, n); k 125 lib/klist.c add_head(k, n); k 134 lib/klist.c void klist_add_tail(struct klist_node *n, struct klist *k) k 136 lib/klist.c klist_node_init(k, n); k 137 lib/klist.c add_tail(k, n); k 148 lib/klist.c struct klist *k = knode_klist(pos); k 150 lib/klist.c klist_node_init(k, n); k 151 lib/klist.c spin_lock(&k->k_lock); k 153 lib/klist.c spin_unlock(&k->k_lock); k 164 lib/klist.c struct klist *k = knode_klist(pos); k 166 lib/klist.c klist_node_init(k, n); k 167 lib/klist.c spin_lock(&k->k_lock); k 169 lib/klist.c spin_unlock(&k->k_lock); k 211 lib/klist.c struct klist *k = knode_klist(n); k 212 lib/klist.c void (*put)(struct klist_node *) = k->put; k 214 lib/klist.c spin_lock(&k->k_lock); k 219 lib/klist.c spin_unlock(&k->k_lock); k 280 lib/klist.c void klist_iter_init_node(struct klist *k, struct klist_iter *i, k 283 lib/klist.c i->i_klist = k; k 297 lib/klist.c void klist_iter_init(struct klist *k, struct klist_iter *i) k 299 lib/klist.c klist_iter_init_node(k, i, NULL); k 814 lib/kobject.c void kset_init(struct kset *k) k 816 lib/kobject.c kobject_init_internal(&k->kobj); k 817 lib/kobject.c INIT_LIST_HEAD(&k->list); k 818 lib/kobject.c spin_lock_init(&k->list_lock); k 856 lib/kobject.c int kset_register(struct kset *k) k 860 lib/kobject.c if (!k) k 863 lib/kobject.c kset_init(k); k 864 lib/kobject.c err = kobject_add_internal(&k->kobj); k 867 lib/kobject.c kobject_uevent(&k->kobj, KOBJ_ADD); k 876 lib/kobject.c void kset_unregister(struct kset *k) k 878 lib/kobject.c if (!k) k 880 lib/kobject.c kobject_del(&k->kobj); k 881 lib/kobject.c kobject_put(&k->kobj); k 896 lib/kobject.c struct kobject *k; k 901 lib/kobject.c list_for_each_entry(k, &kset->list, entry) { k 902 lib/kobject.c if (kobject_name(k) && !strcmp(kobject_name(k), name)) { k 903 lib/kobject.c ret = kobject_get_unless_zero(k); k 30 lib/oid_registry.c unsigned i, j, k, hash; k 46 lib/oid_registry.c k = OID__NR; k 47 lib/oid_registry.c while (i < k) { k 48 lib/oid_registry.c j = (i + k) / 2; k 52 lib/oid_registry.c k = j; k 63 lib/oid_registry.c k = j; k 78 lib/oid_registry.c k = j; k 55 lib/raid6/mktables.c int i, j, k; k 70 lib/raid6/mktables.c for (k = 0; k < 8; k++) k 71 lib/raid6/mktables.c printf("0x%02x,%c", gfmul(i, j + k), k 72 lib/raid6/mktables.c (k == 7) ? '\n' : ' '); k 89 lib/raid6/mktables.c for (k = 0; k < 8; k++) k 90 lib/raid6/mktables.c printf("0x%02x,%c", gfmul(i, j + k), k 91 lib/raid6/mktables.c (k == 7) ? '\n' : ' '); k 95 lib/raid6/mktables.c for (k = 0; k < 8; k++) k 96 lib/raid6/mktables.c printf("0x%02x,%c", gfmul(i, (j + k) << 4), k 97 lib/raid6/mktables.c (k == 7) ? '\n' : ' '); k 132 lib/raid6/mktables.c for (k = 0; k < 256; k++) k 133 lib/raid6/mktables.c if (exptbl[k] == (i + j)) { k 134 lib/raid6/mktables.c v = k; k 15 lib/reed_solomon/decode_rs.c int i, j, r, k, pad; k 200 lib/reed_solomon/decode_rs.c for (i = 1, k = iprim - 1; i <= nn; i++, k = rs_modnn(rs, k + iprim)) { k 211 lib/reed_solomon/decode_rs.c if (k < pad) { k 218 lib/reed_solomon/decode_rs.c loc[count] = k; k 295 lib/reed_solomon/decode_rs.c k = (fcr + i) * prim * (nn-loc[j]-1); k 296 lib/reed_solomon/decode_rs.c tmp ^= alpha_to[rs_modnn(rs, index_of[b[j]] + k)]; k 91 lib/test_bpf.c __u32 k = ~0; k 98 lib/test_bpf.c for (i = 0; i < len; i++, k--) k 99 lib/test_bpf.c insn[i] = __BPF_STMT(BPF_RET | BPF_K, k); k 140 lib/test_bpf.c __u32 k = prandom_u32_state(&rnd); k 142 lib/test_bpf.c insn[i] = __BPF_STMT(BPF_ALU | BPF_ADD | BPF_K, k); k 6564 lib/test_bpf.c if (fp[len].code != 0 || fp[len].k != 0) k 71 lib/test_hash.c int k; k 88 lib/test_hash.c for (k = 1; k <= 32; k++) { k 89 lib/test_hash.c u32 const m = ((u32)2 << (k-1)) - 1; /* Low k bits set */ k 92 lib/test_hash.c hash_or[0][k] |= h1 = hash_32(h0, k); k 94 lib/test_hash.c pr_err("hash_32(%#x, %d) = %#x > %#x", h0, k, h1, m); k 98 lib/test_hash.c h2 = hash_32_generic(h0, k); k 102 lib/test_hash.c " = %#x", h0, k, h1, h2); k 108 lib/test_hash.c h0, k, h1, m); k 114 lib/test_hash.c hash_or[1][k] |= h1 = hash_64(h64, k); k 116 lib/test_hash.c pr_err("hash_64(%#llx, %d) = %#x > %#x", h64, k, h1, m); k 120 lib/test_hash.c h2 = hash_64_generic(h64, k); k 124 lib/test_hash.c "= %#x", h64, k, h1, h2); k 130 lib/test_hash.c h64, k, h1, m); k 273 lib/test_rhashtable.c unsigned int i, j, k; k 294 lib/test_rhashtable.c k = prandom_u32(); k 297 lib/test_rhashtable.c rhl_test_objects[i].value.id = k; k 314 lib/test_rhashtable.c .id = k, k 9 lib/test_string.c unsigned i, j, k; k 20 lib/test_string.c for (k = 0; k < 512; k++) { k 21 lib/test_string.c v = p[k]; k 22 lib/test_string.c if (k < i) { k 25 lib/test_string.c } else if (k < i + j) { k 39 lib/test_string.c return (i << 24) | (j << 16) | k | 0x8000; k 45 lib/test_string.c unsigned i, j, k; k 56 lib/test_string.c for (k = 0; k < 512; k++) { k 57 lib/test_string.c v = p[k]; k 58 lib/test_string.c if (k < i) { k 61 lib/test_string.c } else if (k < i + j) { k 75 lib/test_string.c return (i << 24) | (j << 16) | k | 0x8000; k 81 lib/test_string.c unsigned i, j, k; k 92 lib/test_string.c for (k = 0; k < 512; k++) { k 93 lib/test_string.c v = p[k]; k 94 lib/test_string.c if (k < i) { k 97 lib/test_string.c } else if (k < i + j) { k 111 lib/test_string.c return (i << 24) | (j << 16) | k | 0x8000; k 575 lib/test_xarray.c unsigned long i, j, k; k 625 lib/test_xarray.c for (k = 0; k < max_order; k++) { k 626 lib/test_xarray.c void *entry = xa_load(xa, (1UL << k) - 1); k 627 lib/test_xarray.c if ((i < k) && (j < k)) k 981 lib/test_xarray.c unsigned long i, j, k; k 996 lib/test_xarray.c for (k = 0; k < 100; k++) { k 997 lib/test_xarray.c unsigned long index = k; k 1000 lib/test_xarray.c if (k <= j) k 1002 lib/test_xarray.c else if (k <= i) k 1007 lib/test_xarray.c index = k; k 1010 lib/test_xarray.c if (k <= j) k 1012 lib/test_xarray.c else if (k <= i) k 1051 lib/test_xarray.c unsigned long i, j, k; k 1057 lib/test_xarray.c for (k = 0; k < 100; k++) { k 1059 lib/test_xarray.c xas_for_each_marked(&xas, entry, k, XA_MARK_0) k 1061 lib/test_xarray.c if (j > k) k 77 lib/ts_kmp.c unsigned int k, q; k 80 lib/ts_kmp.c for (k = 0, q = 1; q < len; q++) { k 81 lib/ts_kmp.c while (k > 0 && (icase ? toupper(pattern[k]) : pattern[k]) k 83 lib/ts_kmp.c k = prefix_tbl[k-1]; k 84 lib/ts_kmp.c if ((icase ? toupper(pattern[k]) : pattern[k]) k 86 lib/ts_kmp.c k++; k 87 lib/ts_kmp.c prefix_tbl[q] = k; k 138 lib/zlib_deflate/deftree.c static void pqdownheap (deflate_state *s, ct_data *tree, int k); k 374 lib/zlib_deflate/deftree.c int k /* node to move down */ k 377 lib/zlib_deflate/deftree.c int v = s->heap[k]; k 378 lib/zlib_deflate/deftree.c int j = k << 1; /* left son of k */ k 389 lib/zlib_deflate/deftree.c s->heap[k] = s->heap[j]; k = j; k 394 lib/zlib_deflate/deftree.c s->heap[k] = v; k 1330 mm/mempolicy.c unsigned long k; k 1358 mm/mempolicy.c for (k = BITS_TO_LONGS(MAX_NUMNODES); k < nlongs; k++) { k 1359 mm/mempolicy.c if (get_user(t, nmask + k)) k 1361 mm/mempolicy.c if (k == nlongs - 1) { k 5643 mm/slub.c static void kmem_cache_release(struct kobject *k) k 5645 mm/slub.c slab_kmem_cache_release(to_slab(k)); k 3010 mm/swapfile.c unsigned int j, k; k 3068 mm/swapfile.c for (k = 0; k < SWAP_CLUSTER_COLS; k++) { k 3069 mm/swapfile.c j = (k + col) % SWAP_CLUSTER_COLS; k 350 net/ax25/af_ax25.c unsigned int k; k 366 net/ax25/af_ax25.c for (k = 0; k < digi.ndigi; k++) k 367 net/ax25/af_ax25.c digi.calls[k] = ax25_ctl.digi_addr[k]; k 1876 net/ax25/af_ax25.c int k; k 1891 net/ax25/af_ax25.c for (k=0; (ax25->digipeat != NULL) && (k < ax25->digipeat->ndigi); k++) { k 1893 net/ax25/af_ax25.c ax2asc(buf, &ax25->digipeat->calls[k]), k 1894 net/ax25/af_ax25.c ax25->digipeat->repeated[k]? "*":""); k 375 net/ax25/ax25_route.c int k; k 377 net/ax25/ax25_route.c for (k = 0; k < digipeat->ndigi; k++) { k 378 net/ax25/ax25_route.c if (ax25cmp(addr, &digipeat->calls[k]) == 0) k 382 net/ax25/ax25_route.c digipeat->ndigi = k; k 151 net/ax25/sysctl_net_ax25.c int k; k 158 net/ax25/sysctl_net_ax25.c for (k = 0; k < AX25_MAX_VALUES; k++) k 159 net/ax25/sysctl_net_ax25.c table[k].data = &ax25_dev->values[k]; k 2296 net/bluetooth/hci_core.c struct smp_ltk *k; k 2298 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { k 2299 net/bluetooth/hci_core.c list_del_rcu(&k->list); k 2300 net/bluetooth/hci_core.c kfree_rcu(k, rcu); k 2306 net/bluetooth/hci_core.c struct smp_irk *k; k 2308 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->identity_resolving_keys, list) { k 2309 net/bluetooth/hci_core.c list_del_rcu(&k->list); k 2310 net/bluetooth/hci_core.c kfree_rcu(k, rcu); k 2316 net/bluetooth/hci_core.c struct link_key *k; k 2319 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->link_keys, list) { k 2320 net/bluetooth/hci_core.c if (bacmp(bdaddr, &k->bdaddr) == 0) { k 2322 net/bluetooth/hci_core.c return k; k 2381 net/bluetooth/hci_core.c struct smp_ltk *k; k 2384 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { k 2385 net/bluetooth/hci_core.c if (addr_type != k->bdaddr_type || bacmp(bdaddr, &k->bdaddr)) k 2388 net/bluetooth/hci_core.c if (smp_ltk_is_sc(k) || ltk_role(k->type) == role) { k 2390 net/bluetooth/hci_core.c return k; k 2561 net/bluetooth/hci_core.c struct smp_ltk *k; k 2564 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { k 2565 net/bluetooth/hci_core.c if (bacmp(bdaddr, &k->bdaddr) || k->bdaddr_type != bdaddr_type) k 2570 net/bluetooth/hci_core.c list_del_rcu(&k->list); k 2571 net/bluetooth/hci_core.c kfree_rcu(k, rcu); k 2580 net/bluetooth/hci_core.c struct smp_irk *k; k 2582 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->identity_resolving_keys, list) { k 2583 net/bluetooth/hci_core.c if (bacmp(bdaddr, &k->bdaddr) || k->addr_type != addr_type) k 2588 net/bluetooth/hci_core.c list_del_rcu(&k->list); k 2589 net/bluetooth/hci_core.c kfree_rcu(k, rcu); k 2595 net/bluetooth/hci_core.c struct smp_ltk *k; k 2618 net/bluetooth/hci_core.c list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { k 2619 net/bluetooth/hci_core.c if (k->bdaddr_type == addr_type && !bacmp(bdaddr, &k->bdaddr)) { k 169 net/bluetooth/smp.c static int aes_cmac(struct crypto_shash *tfm, const u8 k[16], const u8 *m, k 187 net/bluetooth/smp.c swap_buf(k, tmp, 16); k 191 net/bluetooth/smp.c SMP_DBG("key %16phN", k); k 379 net/bluetooth/smp.c static int smp_e(const u8 *k, u8 *r) k 385 net/bluetooth/smp.c SMP_DBG("k %16phN r %16phN", k, r); k 388 net/bluetooth/smp.c swap_buf(k, tmp, 16); k 410 net/bluetooth/smp.c static int smp_c1(const u8 k[16], k 417 net/bluetooth/smp.c SMP_DBG("k %16phN r %16phN", k, r); k 435 net/bluetooth/smp.c err = smp_e(k, res); k 452 net/bluetooth/smp.c err = smp_e(k, res); k 459 net/bluetooth/smp.c static int smp_s1(const u8 k[16], k 468 net/bluetooth/smp.c err = smp_e(k, _r); k 3577 net/bluetooth/smp.c const u8 k[16] = { k 3595 net/bluetooth/smp.c err = smp_c1(k, r, preq, pres, _iat, &ia, _rat, &ra, res); k 3607 net/bluetooth/smp.c const u8 k[16] = { k 3620 net/bluetooth/smp.c err = smp_s1(k, r1, r2, res); k 831 net/bridge/netfilter/ebtables.c unsigned int i, j, k, udc_cnt; k 859 net/bridge/netfilter/ebtables.c k = 0; /* holds the total nr. of entries, should equal k 865 net/bridge/netfilter/ebtables.c &i, &j, &k, &udc_cnt); k 873 net/bridge/netfilter/ebtables.c if (k != newinfo->nentries) k 25 net/ceph/ceph_hash.c const unsigned char *k = (const unsigned char *)str; k 37 net/ceph/ceph_hash.c a = a + (k[0] + ((__u32)k[1] << 8) + ((__u32)k[2] << 16) + k 38 net/ceph/ceph_hash.c ((__u32)k[3] << 24)); k 39 net/ceph/ceph_hash.c b = b + (k[4] + ((__u32)k[5] << 8) + ((__u32)k[6] << 16) + k 40 net/ceph/ceph_hash.c ((__u32)k[7] << 24)); k 41 net/ceph/ceph_hash.c c = c + (k[8] + ((__u32)k[9] << 8) + ((__u32)k[10] << 16) + k 42 net/ceph/ceph_hash.c ((__u32)k[11] << 24)); k 44 net/ceph/ceph_hash.c k = k + 12; k 52 net/ceph/ceph_hash.c c = c + ((__u32)k[10] << 24); k 55 net/ceph/ceph_hash.c c = c + ((__u32)k[9] << 16); k 58 net/ceph/ceph_hash.c c = c + ((__u32)k[8] << 8); k 62 net/ceph/ceph_hash.c b = b + ((__u32)k[7] << 24); k 65 net/ceph/ceph_hash.c b = b + ((__u32)k[6] << 16); k 68 net/ceph/ceph_hash.c b = b + ((__u32)k[5] << 8); k 71 net/ceph/ceph_hash.c b = b + k[4]; k 74 net/ceph/ceph_hash.c a = a + ((__u32)k[3] << 24); k 77 net/ceph/ceph_hash.c a = a + ((__u32)k[2] << 16); k 80 net/ceph/ceph_hash.c a = a + ((__u32)k[1] << 8); k 83 net/ceph/ceph_hash.c a = a + k[0]; k 323 net/core/filter.c switch (fp->k) { k 350 net/core/filter.c if (fp->k == SKF_AD_OFF + SKF_AD_IFINDEX) k 409 net/core/filter.c switch (fp->k) { k 456 net/core/filter.c int offset = fp->k; k 491 net/core/filter.c if (fp->k) k 657 net/core/filter.c *insn = BPF_RAW_INSN(fp->code, BPF_REG_A, BPF_REG_X, 0, fp->k); k 683 net/core/filter.c target = i + fp->k + 1; k 696 net/core/filter.c if (BPF_SRC(fp->code) == BPF_K && (int) fp->k < 0) { k 701 net/core/filter.c *insn++ = BPF_MOV32_IMM(BPF_REG_TMP, fp->k); k 708 net/core/filter.c insn->imm = fp->k; k 757 net/core/filter.c .k = fp->k, k 786 net/core/filter.c 0, fp->k); k 793 net/core/filter.c stack_off = fp->k * 4 + 4; k 808 net/core/filter.c stack_off = fp->k * 4 + 4; k 818 net/core/filter.c BPF_REG_A : BPF_REG_X, fp->k); k 842 net/core/filter.c *insn = BPF_LDX_MEM(BPF_W, BPF_REG_A, BPF_REG_CTX, fp->k); k 907 net/core/filter.c memvalid |= (1 << filter[pc].k); k 911 net/core/filter.c if (!(memvalid & (1 << filter[pc].k))) { k 918 net/core/filter.c masks[pc + 1 + filter[pc].k] &= memvalid; k 1051 net/core/filter.c if (ftest->k == 0) k 1056 net/core/filter.c if (ftest->k >= 32) k 1064 net/core/filter.c if (ftest->k >= BPF_MEMWORDS) k 1072 net/core/filter.c if (ftest->k >= (unsigned int)(flen - pc - 1)) k 1095 net/core/filter.c if (anc_found == false && ftest->k >= SKF_AD_OFF) k 2056 net/core/skbuff.c int i, k, eat = (skb->tail + delta) - skb->end; k 2139 net/core/skbuff.c k = 0; k 2147 net/core/skbuff.c skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; k 2157 net/core/skbuff.c k++; k 2160 net/core/skbuff.c skb_shinfo(skb)->nr_frags = k; k 3215 net/core/skbuff.c int i, k = 0; k 3227 net/core/skbuff.c skb_shinfo(skb1)->frags[k] = skb_shinfo(skb)->frags[i]; k 3244 net/core/skbuff.c k++; k 3249 net/core/skbuff.c skb_shinfo(skb1)->nr_frags = k; k 5832 net/core/skbuff.c int i, k = 0; k 5862 net/core/skbuff.c shinfo->frags[k] = skb_shinfo(skb)->frags[i]; k 5877 net/core/skbuff.c k++; k 5881 net/core/skbuff.c shinfo->nr_frags = k; k 5885 net/core/skbuff.c if (k == 0) { k 36 net/core/xdp.c const u32 *k = data; k 37 net/core/xdp.c const u32 key = *k; k 61 net/dccp/ccids/lib/loss_interval.c int i, k = tfrc_lh_length(lh) - 1; /* k is as in rfc3448bis, 5.4 */ k 63 net/dccp/ccids/lib/loss_interval.c if (k <= 0) k 66 net/dccp/ccids/lib/loss_interval.c for (i = 0; i <= k; i++) { k 69 net/dccp/ccids/lib/loss_interval.c if (i < k) { k 98 net/decnet/dn_table.c dn_fib_key_t k; k 99 net/decnet/dn_table.c k.datum = dst & DZ_MASK(dz); k 100 net/decnet/dn_table.c return k; k 799 net/decnet/dn_table.c dn_fib_key_t k = dz_key(flp->daddr, dz); k 801 net/decnet/dn_table.c for(f = dz_chain(k, dz); f; f = f->fn_next) { k 802 net/decnet/dn_table.c if (!dn_key_eq(k, f->fn_key)) { k 803 net/decnet/dn_table.c if (dn_key_leq(k, f->fn_key)) k 1343 net/ipv4/arp.c int k, j; k 1355 net/ipv4/arp.c for (k = 0, j = 0; k < HBUFFERLEN - 3 && j < dev->addr_len; j++) { k 1356 net/ipv4/arp.c hbuffer[k++] = hex_asc_hi(n->ha[j]); k 1357 net/ipv4/arp.c hbuffer[k++] = hex_asc_lo(n->ha[j]); k 1358 net/ipv4/arp.c hbuffer[k++] = ':'; k 1360 net/ipv4/arp.c if (k != 0) k 1361 net/ipv4/arp.c --k; k 1362 net/ipv4/arp.c hbuffer[k] = 0; k 562 net/ipv4/fib_trie.c unsigned long j, k; k 609 net/ipv4/fib_trie.c for (k = child_length(inode), j = k / 2; j;) { k 610 net/ipv4/fib_trie.c put_child(node1, --j, get_child(inode, --k)); k 612 net/ipv4/fib_trie.c put_child(node1, --j, get_child(inode, --k)); k 590 net/ipv4/netfilter/ipt_CLUSTERIP.c int j, k; k 592 net/ipv4/netfilter/ipt_CLUSTERIP.c for (k = 0, j = 0; k < HBUFFERLEN - 3 && j < ETH_ALEN; j++) { k 593 net/ipv4/netfilter/ipt_CLUSTERIP.c hbuffer[k++] = hex_asc_hi(payload->src_hw[j]); k 594 net/ipv4/netfilter/ipt_CLUSTERIP.c hbuffer[k++] = hex_asc_lo(payload->src_hw[j]); k 595 net/ipv4/netfilter/ipt_CLUSTERIP.c hbuffer[k++] = ':'; k 597 net/ipv4/netfilter/ipt_CLUSTERIP.c hbuffer[--k] = '\0'; k 1404 net/ipv4/tcp_output.c int i, k, eat; k 1414 net/ipv4/tcp_output.c k = 0; k 1423 net/ipv4/tcp_output.c shinfo->frags[k] = shinfo->frags[i]; k 1425 net/ipv4/tcp_output.c skb_frag_off_add(&shinfo->frags[k], eat); k 1426 net/ipv4/tcp_output.c skb_frag_size_sub(&shinfo->frags[k], eat); k 1429 net/ipv4/tcp_output.c k++; k 1432 net/ipv4/tcp_output.c shinfo->nr_frags = k; k 2548 net/key/af_key.c struct xfrm_kmaddress k; k 2568 net/key/af_key.c k.reserved = kma->sadb_x_kmaddress_reserved; k 2571 net/key/af_key.c &k.local, &k.remote, &k.family); k 2623 net/key/af_key.c kma ? &k : NULL, net, NULL); k 2906 net/key/af_key.c int i, k, sz = 0; k 2919 net/key/af_key.c for (k = 1; ; k++) { k 2920 net/key/af_key.c const struct xfrm_algo_desc *aalg = xfrm_aalg_get_byidx(k); k 2971 net/key/af_key.c int i, k; k 2990 net/key/af_key.c for (k = 1; ; k++) { k 2992 net/key/af_key.c const struct xfrm_algo_desc *aalg = xfrm_aalg_get_byidx(k); k 3469 net/key/af_key.c static int set_sadb_kmaddress(struct sk_buff *skb, const struct xfrm_kmaddress *k) k 3473 net/key/af_key.c int family = k->family; k 3483 net/key/af_key.c kma->sadb_x_kmaddress_reserved = k->reserved; k 3486 net/key/af_key.c if (!pfkey_sockaddr_fill(&k->local, 0, (struct sockaddr *)sa, family) || k 3487 net/key/af_key.c !pfkey_sockaddr_fill(&k->remote, 0, (struct sockaddr *)(sa+socklen), family)) k 3525 net/key/af_key.c const struct xfrm_kmaddress *k, k 3543 net/key/af_key.c if (k != NULL) { k 3546 net/key/af_key.c pfkey_sockaddr_pair_size(k->family)); k 3586 net/key/af_key.c if (k != NULL && (set_sadb_kmaddress(skb, k) < 0)) k 3636 net/key/af_key.c const struct xfrm_kmaddress *k, k 1101 net/llc/af_llc.c llc->k = opt; k 1164 net/llc/af_llc.c val = llc->k; break; k 1079 net/llc/llc_c_ac.c if (llc->k - unacked_pdu < 1) k 1080 net/llc/llc_c_ac.c llc->k = 1; k 1082 net/llc/llc_c_ac.c llc->k -= unacked_pdu; k 1098 net/llc/llc_c_ac.c llc->k += 1; k 1099 net/llc/llc_c_ac.c if (llc->k > (u8) ~LLC_2_SEQ_NBR_MODULO) k 1100 net/llc/llc_c_ac.c llc->k = (u8) ~LLC_2_SEQ_NBR_MODULO; k 623 net/llc/llc_c_ev.c return !(skb_queue_len(&llc_sk(sk)->pdu_unack_q) + 1 == llc_sk(sk)->k); k 637 net/llc/llc_c_ev.c return skb_queue_len(&llc_sk(sk)->pdu_unack_q) + 1 == llc_sk(sk)->k; k 900 net/llc/llc_conn.c llc->k = 2; /* tx win size, will adjust dynam */ k 192 net/llc/llc_proc.c llc->retry_count, llc->k, llc->rw, llc->p_flag, llc->f_flag, k 83 net/mac80211/trace.h #define KEY_ASSIGN(k) __entry->cipher = (k)->cipher; \ k 84 net/mac80211/trace.h __entry->flags = (k)->flags; \ k 85 net/mac80211/trace.h __entry->keyidx = (k)->keyidx; \ k 86 net/mac80211/trace.h __entry->hw_key_idx = (k)->hw_key_idx; k 520 net/netfilter/ipset/ip_set_hash_gen.h u8 k; k 542 net/netfilter/ipset/ip_set_hash_gen.h for (k = 0; k < IPSET_NET_COUNT; k++) k 544 net/netfilter/ipset/ip_set_hash_gen.h NCIDR_PUT(DCIDR_GET(data->cidr, k)), k 545 net/netfilter/ipset/ip_set_hash_gen.h k); k 1054 net/netfilter/ipset/ip_set_hash_gen.h int i, j, k, r, ret = -IPSET_ERR_EXIST; k 1072 net/netfilter/ipset/ip_set_hash_gen.h for (i = 0, k = 0; i < n->pos; i++) { k 1074 net/netfilter/ipset/ip_set_hash_gen.h k++; k 1111 net/netfilter/ipset/ip_set_hash_gen.h k++; k 1113 net/netfilter/ipset/ip_set_hash_gen.h if (n->pos == 0 && k == 0) { k 1117 net/netfilter/ipset/ip_set_hash_gen.h } else if (k >= AHASH_INIT_SIZE) { k 1124 net/netfilter/ipset/ip_set_hash_gen.h for (j = 0, k = 0; j < n->pos; j++) { k 1128 net/netfilter/ipset/ip_set_hash_gen.h memcpy(tmp->value + k * dsize, data, dsize); k 1129 net/netfilter/ipset/ip_set_hash_gen.h set_bit(k, tmp->used); k 1130 net/netfilter/ipset/ip_set_hash_gen.h k++; k 1132 net/netfilter/ipset/ip_set_hash_gen.h tmp->pos = k; k 1180 net/netfilter/ipset/ip_set_hash_gen.h int ret, i, j = 0, k; k 1191 net/netfilter/ipset/ip_set_hash_gen.h for (k = 0; k < NLEN && h->nets[k].cidr[1] && !multi; k 1192 net/netfilter/ipset/ip_set_hash_gen.h k++) { k 1193 net/netfilter/ipset/ip_set_hash_gen.h mtype_data_netmask(d, NCIDR_GET(h->nets[k].cidr[1]), k 160 net/netfilter/ipvs/ip_vs_est.c struct ip_vs_kstats *k = &stats->kstats; k 163 net/netfilter/ipvs/ip_vs_est.c est->last_inbytes = k->inbytes; k 164 net/netfilter/ipvs/ip_vs_est.c est->last_outbytes = k->outbytes; k 165 net/netfilter/ipvs/ip_vs_est.c est->last_conns = k->conns; k 166 net/netfilter/ipvs/ip_vs_est.c est->last_inpkts = k->inpkts; k 167 net/netfilter/ipvs/ip_vs_est.c est->last_outpkts = k->outpkts; k 871 net/netfilter/nf_tables_api.c const struct nft_object_hash_key *k = data; k 873 net/netfilter/nf_tables_api.c seed ^= hash_ptr(k->table, 32); k 875 net/netfilter/nf_tables_api.c return jhash(k->name, strlen(k->name), seed); k 888 net/netfilter/nf_tables_api.c const struct nft_object_hash_key *k = arg->key; k 891 net/netfilter/nf_tables_api.c if (obj->key.table != k->table) k 894 net/netfilter/nf_tables_api.c return strcmp(obj->key.name, k->name); k 5029 net/netfilter/nf_tables_api.c struct nft_object_hash_key k = { .table = table }; k 5035 net/netfilter/nf_tables_api.c k.name = search; k 5041 net/netfilter/nf_tables_api.c list = rhltable_lookup(&nft_objname_ht, &k, nft_objname_ht_params); k 5825 net/netfilter/nf_tables_api.c int err, i, k; k 5892 net/netfilter/nf_tables_api.c for (k = 0; k < ft->ops_len; k++) { k 5893 net/netfilter/nf_tables_api.c if (!ft->ops[k].dev) k 5896 net/netfilter/nf_tables_api.c if (flowtable->ops[i].dev == ft->ops[k].dev && k 5897 net/netfilter/nf_tables_api.c flowtable->ops[i].pf == ft->ops[k].pf) { k 5920 net/netfilter/nf_tables_api.c for (k = i - 1; k >= 0; k--) k 5921 net/netfilter/nf_tables_api.c nf_unregister_net_hook(net, &flowtable->ops[k]); k 47 net/netfilter/nft_ct.c enum nft_ct_keys k, k 51 net/netfilter/nft_ct.c return k == NFT_CT_BYTES ? atomic64_read(&c[d].bytes) : k 54 net/netfilter/nft_ct.c return nft_ct_get_eval_counter(c, k, IP_CT_DIR_ORIGINAL) + k 55 net/netfilter/nft_ct.c nft_ct_get_eval_counter(c, k, IP_CT_DIR_REPLY); k 55 net/netfilter/nft_set_bitmap.c u32 k; k 58 net/netfilter/nft_set_bitmap.c k = *(u16 *)key; k 60 net/netfilter/nft_set_bitmap.c k = *(u8 *)key; k 61 net/netfilter/nft_set_bitmap.c k <<= 1; k 63 net/netfilter/nft_set_bitmap.c *idx = k / BITS_PER_BYTE; k 64 net/netfilter/nft_set_bitmap.c *off = k % BITS_PER_BYTE; k 97 net/netfilter/nft_xfrm.c static bool xfrm_state_addr_ok(enum nft_xfrm_keys k, u8 family, u8 mode) k 99 net/netfilter/nft_xfrm.c switch (k) { k 804 net/rds/ib_recv.c unsigned int k; k 813 net/rds/ib_recv.c for (k = 0; k < to_copy; k += 8) { k 78 net/rxrpc/conn_object.c struct rxrpc_conn_proto k; k 97 net/rxrpc/conn_object.c k.epoch = sp->hdr.epoch; k 98 net/rxrpc/conn_object.c k.cid = sp->hdr.cid & RXRPC_CIDMASK; k 125 net/rxrpc/conn_object.c if (conn->proto.epoch != k.epoch || k 25 net/rxrpc/conn_service.c struct rxrpc_conn_proto k; k 30 net/rxrpc/conn_service.c k.epoch = sp->hdr.epoch; k 31 net/rxrpc/conn_service.c k.cid = sp->hdr.cid & RXRPC_CIDMASK; k 44 net/rxrpc/conn_service.c if (conn->proto.index_key < k.index_key) k 46 net/rxrpc/conn_service.c else if (conn->proto.index_key > k.index_key) k 67 net/rxrpc/conn_service.c struct rxrpc_conn_proto k = conn->proto; k 79 net/rxrpc/conn_service.c if (cursor->proto.index_key < k.index_key) k 81 net/rxrpc/conn_service.c else if (cursor->proto.index_key > k.index_key) k 41 net/sched/act_pedit.c struct tcf_pedit_key_ex *k; k 49 net/sched/act_pedit.c keys_ex = kcalloc(n, sizeof(*k), GFP_KERNEL); k 53 net/sched/act_pedit.c k = keys_ex; k 81 net/sched/act_pedit.c k->htype = nla_get_u16(tb[TCA_PEDIT_KEY_EX_HTYPE]); k 82 net/sched/act_pedit.c k->cmd = nla_get_u16(tb[TCA_PEDIT_KEY_EX_CMD]); k 84 net/sched/act_pedit.c if (k->htype > TCA_PEDIT_HDR_TYPE_MAX || k 85 net/sched/act_pedit.c k->cmd > TCA_PEDIT_CMD_MAX) { k 90 net/sched/act_pedit.c k++; k 3439 net/sched/cls_api.c int i, j, k, err = 0; k 3502 net/sched/cls_api.c for (k = 0; k < tcf_pedit_nkeys(act); k++) { k 3503 net/sched/cls_api.c switch (tcf_pedit_cmd(act, k)) { k 3514 net/sched/cls_api.c entry->mangle.htype = tcf_pedit_htype(act, k); k 3515 net/sched/cls_api.c entry->mangle.mask = tcf_pedit_mask(act, k); k 3516 net/sched/cls_api.c entry->mangle.val = tcf_pedit_val(act, k); k 3517 net/sched/cls_api.c entry->mangle.offset = tcf_pedit_offset(act, k); k 450 net/sched/cls_rsvp.h int i, k; k 452 net/sched/cls_rsvp.h for (k = 0; k < 2; k++) { k 714 net/sched/sch_cake.c u32 i, k; k 719 net/sched/sch_cake.c for (i = 0, k = inner_hash; i < CAKE_SET_WAYS; k 720 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 721 net/sched/sch_cake.c if (q->tags[outer_hash + k] == flow_hash) { k 725 net/sched/sch_cake.c if (!q->flows[outer_hash + k].set) { k 739 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 740 net/sched/sch_cake.c if (!q->flows[outer_hash + k].set) { k 752 net/sched/sch_cake.c if (q->flows[outer_hash + k].set == CAKE_SET_BULK) { k 760 net/sched/sch_cake.c reduced_hash = outer_hash + k; k 767 net/sched/sch_cake.c for (i = 0, k = inner_hash; i < CAKE_SET_WAYS; k 768 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 769 net/sched/sch_cake.c if (q->hosts[outer_hash + k].srchost_tag == k 774 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 775 net/sched/sch_cake.c if (!q->hosts[outer_hash + k].srchost_bulk_flow_count) k 778 net/sched/sch_cake.c q->hosts[outer_hash + k].srchost_tag = srchost_hash; k 780 net/sched/sch_cake.c srchost_idx = outer_hash + k; k 790 net/sched/sch_cake.c for (i = 0, k = inner_hash; i < CAKE_SET_WAYS; k 791 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 792 net/sched/sch_cake.c if (q->hosts[outer_hash + k].dsthost_tag == k 797 net/sched/sch_cake.c i++, k = (k + 1) % CAKE_SET_WAYS) { k 798 net/sched/sch_cake.c if (!q->hosts[outer_hash + k].dsthost_bulk_flow_count) k 801 net/sched/sch_cake.c q->hosts[outer_hash + k].dsthost_tag = dsthost_hash; k 803 net/sched/sch_cake.c dsthost_idx = outer_hash + k; k 2713 net/sched/sch_cake.c u32 k = j * CAKE_MAX_TINS + i; k 2718 net/sched/sch_cake.c q->overflow_heap[k].t = i; k 2719 net/sched/sch_cake.c q->overflow_heap[k].b = j; k 2720 net/sched/sch_cake.c b->overflow_idx[j] = k; k 322 net/sunrpc/sched.c struct wait_bit_key k = __WAIT_BIT_KEY_INITIALIZER(m, RPC_TASK_ACTIVE); k 332 net/sunrpc/sched.c __wake_up_locked_key(wq, TASK_NORMAL, &k); k 1036 net/wireless/nl80211.c struct key_parse *k) k 1045 net/wireless/nl80211.c k->def = !!tb[NL80211_KEY_DEFAULT]; k 1046 net/wireless/nl80211.c k->defmgmt = !!tb[NL80211_KEY_DEFAULT_MGMT]; k 1048 net/wireless/nl80211.c if (k->def) { k 1049 net/wireless/nl80211.c k->def_uni = true; k 1050 net/wireless/nl80211.c k->def_multi = true; k 1052 net/wireless/nl80211.c if (k->defmgmt) k 1053 net/wireless/nl80211.c k->def_multi = true; k 1056 net/wireless/nl80211.c k->idx = nla_get_u8(tb[NL80211_KEY_IDX]); k 1059 net/wireless/nl80211.c k->p.key = nla_data(tb[NL80211_KEY_DATA]); k 1060 net/wireless/nl80211.c k->p.key_len = nla_len(tb[NL80211_KEY_DATA]); k 1064 net/wireless/nl80211.c k->p.seq = nla_data(tb[NL80211_KEY_SEQ]); k 1065 net/wireless/nl80211.c k->p.seq_len = nla_len(tb[NL80211_KEY_SEQ]); k 1069 net/wireless/nl80211.c k->p.cipher = nla_get_u32(tb[NL80211_KEY_CIPHER]); k 1072 net/wireless/nl80211.c k->type = nla_get_u32(tb[NL80211_KEY_TYPE]); k 1085 net/wireless/nl80211.c k->def_uni = kdt[NL80211_KEY_DEFAULT_TYPE_UNICAST]; k 1086 net/wireless/nl80211.c k->def_multi = kdt[NL80211_KEY_DEFAULT_TYPE_MULTICAST]; k 1090 net/wireless/nl80211.c k->p.mode = nla_get_u8(tb[NL80211_KEY_MODE]); k 1095 net/wireless/nl80211.c static int nl80211_parse_key_old(struct genl_info *info, struct key_parse *k) k 1098 net/wireless/nl80211.c k->p.key = nla_data(info->attrs[NL80211_ATTR_KEY_DATA]); k 1099 net/wireless/nl80211.c k->p.key_len = nla_len(info->attrs[NL80211_ATTR_KEY_DATA]); k 1103 net/wireless/nl80211.c k->p.seq = nla_data(info->attrs[NL80211_ATTR_KEY_SEQ]); k 1104 net/wireless/nl80211.c k->p.seq_len = nla_len(info->attrs[NL80211_ATTR_KEY_SEQ]); k 1108 net/wireless/nl80211.c k->idx = nla_get_u8(info->attrs[NL80211_ATTR_KEY_IDX]); k 1111 net/wireless/nl80211.c k->p.cipher = nla_get_u32(info->attrs[NL80211_ATTR_KEY_CIPHER]); k 1113 net/wireless/nl80211.c k->def = !!info->attrs[NL80211_ATTR_KEY_DEFAULT]; k 1114 net/wireless/nl80211.c k->defmgmt = !!info->attrs[NL80211_ATTR_KEY_DEFAULT_MGMT]; k 1116 net/wireless/nl80211.c if (k->def) { k 1117 net/wireless/nl80211.c k->def_uni = true; k 1118 net/wireless/nl80211.c k->def_multi = true; k 1120 net/wireless/nl80211.c if (k->defmgmt) k 1121 net/wireless/nl80211.c k->def_multi = true; k 1124 net/wireless/nl80211.c k->type = nla_get_u32(info->attrs[NL80211_ATTR_KEY_TYPE]); k 1136 net/wireless/nl80211.c k->def_uni = kdt[NL80211_KEY_DEFAULT_TYPE_UNICAST]; k 1137 net/wireless/nl80211.c k->def_multi = kdt[NL80211_KEY_DEFAULT_TYPE_MULTICAST]; k 1143 net/wireless/nl80211.c static int nl80211_parse_key(struct genl_info *info, struct key_parse *k) k 1147 net/wireless/nl80211.c memset(k, 0, sizeof(*k)); k 1148 net/wireless/nl80211.c k->idx = -1; k 1149 net/wireless/nl80211.c k->type = -1; k 1152 net/wireless/nl80211.c err = nl80211_parse_key_new(info, info->attrs[NL80211_ATTR_KEY], k); k 1154 net/wireless/nl80211.c err = nl80211_parse_key_old(info, k); k 1159 net/wireless/nl80211.c if (k->def && k->defmgmt) { k 1164 net/wireless/nl80211.c if (k->defmgmt) { k 1165 net/wireless/nl80211.c if (k->def_uni || !k->def_multi) { k 1171 net/wireless/nl80211.c if (k->idx != -1) { k 1172 net/wireless/nl80211.c if (k->defmgmt) { k 1173 net/wireless/nl80211.c if (k->idx < 4 || k->idx > 5) { k 1178 net/wireless/nl80211.c } else if (k->def) { k 1179 net/wireless/nl80211.c if (k->idx < 0 || k->idx > 3) { k 1184 net/wireless/nl80211.c if (k->idx < 0 || k->idx > 5) { k 2185 net/wireless/scan.c int k; k 2187 net/wireless/scan.c for (k = 0; k < wreq->num_channels; k++) { k 2189 net/wireless/scan.c &wreq->channel_list[k]; k 117 net/xfrm/xfrm_policy.c struct xfrm_pol_inexact_key k; k 695 net/xfrm/xfrm_policy.c struct xfrm_pol_inexact_key k = { k 705 net/xfrm/xfrm_policy.c write_pnet(&k.net, net); k 706 net/xfrm/xfrm_policy.c bin = rhashtable_lookup_fast(&xfrm_policy_inexact_table, &k, k 715 net/xfrm/xfrm_policy.c bin->k = k; k 722 net/xfrm/xfrm_policy.c &bin->k, &bin->head, k 1094 net/xfrm/xfrm_policy.c struct net *net = read_pnet(&b->k.net); k 1445 net/xfrm/xfrm_policy.c const struct xfrm_pol_inexact_key *k = data; k 1446 net/xfrm/xfrm_policy.c u32 a = k->type << 24 | k->dir << 16 | k->family; k 1448 net/xfrm/xfrm_policy.c return jhash_3words(a, k->if_id, net_hash_mix(read_pnet(&k->net)), k 1456 net/xfrm/xfrm_policy.c return xfrm_pol_bin_key(&b->k, 0, seed); k 1466 net/xfrm/xfrm_policy.c if (!net_eq(read_pnet(&b->k.net), read_pnet(&key->net))) k 1469 net/xfrm/xfrm_policy.c ret = b->k.dir ^ key->dir; k 1473 net/xfrm/xfrm_policy.c ret = b->k.type ^ key->type; k 1477 net/xfrm/xfrm_policy.c ret = b->k.family ^ key->family; k 1481 net/xfrm/xfrm_policy.c return b->k.if_id ^ key->if_id; k 1953 net/xfrm/xfrm_policy.c family = b->k.family; k 1979 net/xfrm/xfrm_policy.c struct xfrm_pol_inexact_key k = { k 1986 net/xfrm/xfrm_policy.c write_pnet(&k.net, net); k 1988 net/xfrm/xfrm_policy.c return rhashtable_lookup(&xfrm_policy_inexact_table, &k, k 3490 net/xfrm/xfrm_policy.c static inline int secpath_has_nontransport(const struct sec_path *sp, int k, int *idxp) k 3492 net/xfrm/xfrm_policy.c for (; k < sp->len; k++) { k 3493 net/xfrm/xfrm_policy.c if (sp->xvec[k]->props.mode != XFRM_MODE_TRANSPORT) { k 3494 net/xfrm/xfrm_policy.c *idxp = k; k 3608 net/xfrm/xfrm_policy.c int i, k; k 3639 net/xfrm/xfrm_policy.c for (i = xfrm_nr-1, k = 0; i >= 0; i--) { k 3640 net/xfrm/xfrm_policy.c k = xfrm_policy_ok(tpp[i], sp, k, family); k 3641 net/xfrm/xfrm_policy.c if (k < 0) { k 3642 net/xfrm/xfrm_policy.c if (k < -1) k 3644 net/xfrm/xfrm_policy.c xerr_idx = -(2+k); k 3650 net/xfrm/xfrm_policy.c if (secpath_has_nontransport(sp, k, &xerr_idx)) { k 4385 net/xfrm/xfrm_policy.c struct xfrm_kmaddress *k, struct net *net, k 4437 net/xfrm/xfrm_policy.c km_migrate(sel, dir, type, m, num_migrate, k, encap); k 2206 net/xfrm/xfrm_state.c const struct xfrm_kmaddress *k, k 2216 net/xfrm/xfrm_state.c ret = km->migrate(sel, dir, type, m, num_migrate, k, k 2321 net/xfrm/xfrm_user.c struct xfrm_kmaddress *k, k 2328 net/xfrm/xfrm_user.c if (k != NULL) { k 2332 net/xfrm/xfrm_user.c memcpy(&k->local, &uk->local, sizeof(k->local)); k 2333 net/xfrm/xfrm_user.c memcpy(&k->remote, &uk->remote, sizeof(k->remote)); k 2334 net/xfrm/xfrm_user.c k->family = uk->family; k 2335 net/xfrm/xfrm_user.c k->reserved = uk->reserved; k 2430 net/xfrm/xfrm_user.c static int copy_to_user_kmaddress(const struct xfrm_kmaddress *k, struct sk_buff *skb) k 2435 net/xfrm/xfrm_user.c uk.family = k->family; k 2436 net/xfrm/xfrm_user.c uk.reserved = k->reserved; k 2437 net/xfrm/xfrm_user.c memcpy(&uk.local, &k->local, sizeof(uk.local)); k 2438 net/xfrm/xfrm_user.c memcpy(&uk.remote, &k->remote, sizeof(uk.remote)); k 2454 net/xfrm/xfrm_user.c int num_migrate, const struct xfrm_kmaddress *k, k 2473 net/xfrm/xfrm_user.c if (k != NULL) { k 2474 net/xfrm/xfrm_user.c err = copy_to_user_kmaddress(k, skb); k 2502 net/xfrm/xfrm_user.c const struct xfrm_kmaddress *k, k 2509 net/xfrm/xfrm_user.c skb = nlmsg_new(xfrm_migrate_msgsize(num_migrate, !!k, !!encap), k 2515 net/xfrm/xfrm_user.c err = build_migrate(skb, m, num_migrate, k, sel, encap, dir, type); k 2523 net/xfrm/xfrm_user.c const struct xfrm_kmaddress *k, k 320 samples/bpf/hbm.c int k; k 386 samples/bpf/hbm.c for (k = 0; k < RET_VAL_COUNT; k++) { k 387 samples/bpf/hbm.c percent_pkts = (qstats.returnValCount[k] * 100.0) / k 389 samples/bpf/hbm.c fprintf(fout, "%s:%6.2f (%d)\n", returnValNames[k], k 390 samples/bpf/hbm.c percent_pkts, (int)qstats.returnValCount[k]); k 438 samples/bpf/hbm.c int k; k 447 samples/bpf/hbm.c while ((k = getopt_long(argc, argv, optstring, loptions, NULL)) != -1) { k 448 samples/bpf/hbm.c switch (k) { k 35 samples/bpf/tracex3_kern.c #define S(k) if (n >= (1ull << k)) { i += k; n >>= k; } k 37 samples/seccomp/bpf-helper.c if (labels->labels[instr->k].location == 0xffffffff) { k 39 samples/seccomp/bpf-helper.c labels->labels[instr->k].label); k 42 samples/seccomp/bpf-helper.c instr->k = labels->labels[instr->k].location - k 48 samples/seccomp/bpf-helper.c if (labels->labels[instr->k].location != 0xffffffff) { k 50 samples/seccomp/bpf-helper.c labels->labels[instr->k].label); k 53 samples/seccomp/bpf-helper.c labels->labels[instr->k].location = offset; k 54 samples/seccomp/bpf-helper.c instr->k = 0; /* fall through */ k 95 samples/seccomp/bpf-helper.c filter->code, filter->jt, filter->jf, filter->k); k 144 scripts/gcc-plugins/randomize_layout_plugin.c #define rot(x,k) (((x)<<(k))|((x)>>(64-(k)))) k 332 scripts/kallsyms.c unsigned int i, k, off; k 428 scripts/kallsyms.c for (k = 0; k < table[i].len; k++) k 429 scripts/kallsyms.c printf(", 0x%02x", table[i].sym[k]); k 367 scripts/kconfig/mconf.c int k = 0; k 373 scripts/kconfig/mconf.c if (k < JUMP_NB) { k 377 scripts/kconfig/mconf.c data->keys[k] = key; k 378 scripts/kconfig/mconf.c data->targets[k] = pos->target; k 379 scripts/kconfig/mconf.c k++; k 387 scripts/kconfig/mconf.c data->keys[k] = 0; k 642 scripts/mod/file2alias.c int k; k 648 scripts/mod/file2alias.c for (k = 0; k < sizeof(acpi_id); k++) k 649 scripts/mod/file2alias.c acpi_id[k] = toupper(id[k]); k 67 scripts/mod/sumversion.c #define ROUND1(a,b,c,d,k,s) (a = lshift(a + F(b,c,d) + k, s)) k 68 scripts/mod/sumversion.c #define ROUND2(a,b,c,d,k,s) (a = lshift(a + G(b,c,d) + k + (uint32_t)0x5A827999,s)) k 69 scripts/mod/sumversion.c #define ROUND3(a,b,c,d,k,s) (a = lshift(a + H(b,c,d) + k + (uint32_t)0x6ED9EBA1,s)) k 313 scripts/pnmtologo.c unsigned int i, j, k; k 319 scripts/pnmtologo.c for (k = 0; k < 16; k++) k 320 scripts/pnmtologo.c if (is_equal(logo_data[i][j], clut_vga16[k])) k 322 scripts/pnmtologo.c if (k == 16) k 334 scripts/pnmtologo.c for (k = 0; k < 16; k++) k 335 scripts/pnmtologo.c if (is_equal(logo_data[i][j], clut_vga16[k])) k 337 scripts/pnmtologo.c val = k<<4; k 339 scripts/pnmtologo.c for (k = 0; k < 16; k++) k 340 scripts/pnmtologo.c if (is_equal(logo_data[i][j], clut_vga16[k])) k 342 scripts/pnmtologo.c val |= k; k 353 scripts/pnmtologo.c unsigned int i, j, k; k 358 scripts/pnmtologo.c for (k = 0; k < logo_clutsize; k++) k 359 scripts/pnmtologo.c if (is_equal(logo_data[i][j], logo_clut[k])) k 361 scripts/pnmtologo.c if (k == logo_clutsize) { k 376 scripts/pnmtologo.c for (k = 0; k < logo_clutsize; k++) k 377 scripts/pnmtologo.c if (is_equal(logo_data[i][j], logo_clut[k])) k 379 scripts/pnmtologo.c write_hex(k+32); k 532 scripts/recordmcount.h unsigned k; k 564 scripts/recordmcount.h for (relhdr = shdr0, k = nhdr; k; --k, ++relhdr) { k 980 security/apparmor/label.c int k; k 986 security/apparmor/label.c for (k = 0; k 987 security/apparmor/label.c k < z->size && (p = aa_label_next_in_merge(&i, a, b)); k 988 security/apparmor/label.c k++) { k 989 security/apparmor/label.c int res = profile_cmp(p, z->vec[k]); k 997 security/apparmor/label.c else if (k < z->size) k 1028 security/apparmor/label.c int k = 0, invcount = 0; k 1041 security/apparmor/label.c new->vec[k] = aa_get_newest_profile(next); k 1042 security/apparmor/label.c AA_BUG(!new->vec[k]->label.proxy); k 1043 security/apparmor/label.c AA_BUG(!new->vec[k]->label.proxy->label); k 1044 security/apparmor/label.c if (next->label.proxy != new->vec[k]->label.proxy) k 1046 security/apparmor/label.c k++; k 1049 security/apparmor/label.c new->vec[k++] = aa_get_profile(next); k 1052 security/apparmor/label.c new->size = k; k 1053 security/apparmor/label.c new->vec[k] = NULL; k 1068 security/apparmor/label.c if (k == a->size) k 1070 security/apparmor/label.c else if (k == b->size) k 220 security/apparmor/match.c size_t j, k; k 225 security/apparmor/match.c j = k) { k 226 security/apparmor/match.c k = DEFAULT_TABLE(dfa)[j]; k 227 security/apparmor/match.c if (j == k) k 229 security/apparmor/match.c if (k < j) k 6549 security/selinux/hooks.c static int selinux_key_alloc(struct key *k, const struct cred *cred, k 6565 security/selinux/hooks.c k->security = ksec; k 6569 security/selinux/hooks.c static void selinux_key_free(struct key *k) k 6571 security/selinux/hooks.c struct key_security_struct *ksec = k->security; k 6573 security/selinux/hooks.c k->security = NULL; k 388 security/selinux/ss/avtab.c int (*insertf)(struct avtab *a, struct avtab_key *k, k 549 security/selinux/ss/avtab.c static int avtab_insertf(struct avtab *a, struct avtab_key *k, k 552 security/selinux/ss/avtab.c return avtab_insert(a, k, d); k 92 security/selinux/ss/avtab.h struct avtab_datum *avtab_search(struct avtab *h, struct avtab_key *k); k 98 security/selinux/ss/avtab.h int (*insert)(struct avtab *a, struct avtab_key *k, k 268 security/selinux/ss/conditional.c static int cond_insertf(struct avtab *a, struct avtab_key *k, struct avtab_datum *d, void *ptr) k 282 security/selinux/ss/conditional.c if (k->specified & AVTAB_TYPE) { k 283 security/selinux/ss/conditional.c if (avtab_search(&p->te_avtab, k)) { k 296 security/selinux/ss/conditional.c node_ptr = avtab_search_node(&p->te_cond_avtab, k); k 298 security/selinux/ss/conditional.c if (avtab_search_node_next(node_ptr, k->specified)) { k 315 security/selinux/ss/conditional.c if (avtab_search(&p->te_cond_avtab, k)) { k 322 security/selinux/ss/conditional.c node_ptr = avtab_insert_nonunique(&p->te_cond_avtab, k, d); k 124 security/selinux/ss/hashtab.c int (*apply)(void *k, void *d, void *args), k 55 security/selinux/ss/hashtab.h int hashtab_insert(struct hashtab *h, void *k, void *d); k 63 security/selinux/ss/hashtab.h void *hashtab_search(struct hashtab *h, const void *k); k 82 security/selinux/ss/hashtab.h int (*apply)(void *k, void *d, void *args), k 402 security/selinux/ss/policydb.c static u32 filenametr_hash(struct hashtab *h, const void *k) k 404 security/selinux/ss/policydb.c const struct filename_trans *ft = k; k 439 security/selinux/ss/policydb.c static u32 rangetr_hash(struct hashtab *h, const void *k) k 441 security/selinux/ss/policydb.c const struct range_trans *key = k; k 2169 security/selinux/ss/policydb.c int k; k 2174 security/selinux/ss/policydb.c for (k = 0; k < 4; k++) k 2175 security/selinux/ss/policydb.c c->u.node6.addr[k] = nodebuf[k]; k 2176 security/selinux/ss/policydb.c for (k = 0; k < 4; k++) k 2177 security/selinux/ss/policydb.c c->u.node6.mask[k] = nodebuf[k+4]; k 106 security/selinux/ss/services.c unsigned k; k 144 security/selinux/ss/services.c k = 0; k 145 security/selinux/ss/services.c while (p_in->perms[k]) { k 147 security/selinux/ss/services.c if (!*p_in->perms[k]) { k 148 security/selinux/ss/services.c k++; k 151 security/selinux/ss/services.c p_out->perms[k] = string_to_av_perm(pol, p_out->value, k 152 security/selinux/ss/services.c p_in->perms[k]); k 153 security/selinux/ss/services.c if (!p_out->perms[k]) { k 155 security/selinux/ss/services.c p_in->perms[k], p_in->name); k 161 security/selinux/ss/services.c k++; k 163 security/selinux/ss/services.c p_out->num_perms = k; k 441 security/selinux/ss/services.c static int dump_masked_av_helper(void *k, void *d, void *args) k 448 security/selinux/ss/services.c permission_names[pdatum->value - 1] = (char *)k; k 3125 security/selinux/ss/services.c static int get_classes_callback(void *k, void *d, void *args) k 3128 security/selinux/ss/services.c char *name = k, **classes = args; k 3172 security/selinux/ss/services.c static int get_permissions_callback(void *k, void *d, void *args) k 3175 security/selinux/ss/services.c char *name = k, **perms = args; k 706 sound/core/pcm_lib.c unsigned int k, struct snd_interval *c) k 714 sound/core/pcm_lib.c c->min = muldiv32(a->min, b->min, k, &r); k 716 sound/core/pcm_lib.c c->max = muldiv32(a->max, b->max, k, &r); k 736 sound/core/pcm_lib.c void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k, k 745 sound/core/pcm_lib.c c->min = muldiv32(a->min, k, b->max, &r); k 748 sound/core/pcm_lib.c c->max = muldiv32(a->max, k, b->min, &r); k 781 sound/core/pcm_lib.c unsigned int k; k 788 sound/core/pcm_lib.c for (k = 0; k < rats_count; ++k) { k 789 sound/core/pcm_lib.c unsigned int num = rats[k].num; k 796 sound/core/pcm_lib.c if (den < rats[k].den_min) k 798 sound/core/pcm_lib.c if (den > rats[k].den_max) k 799 sound/core/pcm_lib.c den = rats[k].den_max; k 802 sound/core/pcm_lib.c r = (den - rats[k].den_min) % rats[k].den_step; k 827 sound/core/pcm_lib.c for (k = 0; k < rats_count; ++k) { k 828 sound/core/pcm_lib.c unsigned int num = rats[k].num; k 837 sound/core/pcm_lib.c if (den > rats[k].den_max) k 839 sound/core/pcm_lib.c if (den < rats[k].den_min) k 840 sound/core/pcm_lib.c den = rats[k].den_min; k 843 sound/core/pcm_lib.c r = (den - rats[k].den_min) % rats[k].den_step; k 845 sound/core/pcm_lib.c den += rats[k].den_step - r; k 899 sound/core/pcm_lib.c unsigned int k; k 904 sound/core/pcm_lib.c for (k = 0; k < rats_count; ++k) { k 906 sound/core/pcm_lib.c unsigned int den = rats[k].den; k 910 sound/core/pcm_lib.c if (num > rats[k].num_max) k 912 sound/core/pcm_lib.c if (num < rats[k].num_min) k 913 sound/core/pcm_lib.c num = rats[k].num_max; k 916 sound/core/pcm_lib.c r = (num - rats[k].num_min) % rats[k].num_step; k 918 sound/core/pcm_lib.c num += rats[k].num_step - r; k 936 sound/core/pcm_lib.c for (k = 0; k < rats_count; ++k) { k 938 sound/core/pcm_lib.c unsigned int den = rats[k].den; k 942 sound/core/pcm_lib.c if (num < rats[k].num_min) k 944 sound/core/pcm_lib.c if (num > rats[k].num_max) k 945 sound/core/pcm_lib.c num = rats[k].num_max; k 948 sound/core/pcm_lib.c r = (num - rats[k].num_min) % rats[k].num_step; k 997 sound/core/pcm_lib.c unsigned int k; k 1007 sound/core/pcm_lib.c for (k = 0; k < count; k++) { k 1008 sound/core/pcm_lib.c if (mask && !(mask & (1 << k))) k 1010 sound/core/pcm_lib.c if (!snd_interval_test(i, list[k])) k 1012 sound/core/pcm_lib.c list_range.min = min(list_range.min, list[k]); k 1013 sound/core/pcm_lib.c list_range.max = max(list_range.max, list[k]); k 1036 sound/core/pcm_lib.c unsigned int k; k 1047 sound/core/pcm_lib.c for (k = 0; k < count; k++) { k 1048 sound/core/pcm_lib.c if (mask && !(mask & (1 << k))) k 1050 sound/core/pcm_lib.c snd_interval_copy(&range, &ranges[k]); k 1116 sound/core/pcm_lib.c unsigned int k; k 1136 sound/core/pcm_lib.c k = 0; k 1138 sound/core/pcm_lib.c if (snd_BUG_ON(k >= ARRAY_SIZE(c->deps))) { k 1142 sound/core/pcm_lib.c c->deps[k++] = dep; k 1522 sound/core/pcm_lib.c unsigned int k; k 1524 sound/core/pcm_lib.c for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++) k 1525 sound/core/pcm_lib.c _snd_pcm_hw_param_any(params, k); k 1526 sound/core/pcm_lib.c for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) k 1527 sound/core/pcm_lib.c _snd_pcm_hw_param_any(params, k); k 19 sound/core/pcm_local.h unsigned int k, struct snd_interval *c); k 20 sound/core/pcm_local.h void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k, k 248 sound/core/pcm_native.c unsigned int k; k 252 sound/core/pcm_native.c for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++) { k 253 sound/core/pcm_native.c m = hw_param_mask(params, k); k 258 sound/core/pcm_native.c if (!(params->rmask & (1 << k))) k 264 sound/core/pcm_native.c changed = snd_mask_refine(m, constrs_mask(constrs, k)); k 271 sound/core/pcm_native.c trace_hw_mask_param(substream, k, 0, &old_mask, m); k 272 sound/core/pcm_native.c params->cmask |= 1 << k; k 284 sound/core/pcm_native.c unsigned int k; k 288 sound/core/pcm_native.c for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) { k 289 sound/core/pcm_native.c i = hw_param_interval(params, k); k 294 sound/core/pcm_native.c if (!(params->rmask & (1 << k))) k 300 sound/core/pcm_native.c changed = snd_interval_refine(i, constrs_interval(constrs, k)); k 307 sound/core/pcm_native.c trace_hw_interval_param(substream, k, 0, &old_interval, i); k 308 sound/core/pcm_native.c params->cmask |= 1 << k; k 319 sound/core/pcm_native.c unsigned int k; k 349 sound/core/pcm_native.c for (k = 0; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) k 350 sound/core/pcm_native.c vstamps[k] = (params->rmask & (1 << k)) ? 1 : 0; k 357 sound/core/pcm_native.c for (k = 0; k < constrs->rules_num; k++) { k 358 sound/core/pcm_native.c r = &constrs->rules[k]; k 380 sound/core/pcm_native.c if (vstamps[r->deps[d]] > rstamps[k]) k 409 sound/core/pcm_native.c k + 1, &old_mask, k 414 sound/core/pcm_native.c k + 1, &old_interval, k 423 sound/core/pcm_native.c rstamps[k] = stamp++; k 2143 sound/core/pcm_native.c unsigned int k; k 2149 sound/core/pcm_native.c for (k = 0; k <= SNDRV_PCM_FORMAT_LAST; ++k) { k 2151 sound/core/pcm_native.c if (! snd_mask_test(mask, k)) k 2153 sound/core/pcm_native.c bits = snd_pcm_format_physical_width(k); k 2157 sound/core/pcm_native.c snd_mask_reset(&m, k); k 2166 sound/core/pcm_native.c unsigned int k; k 2171 sound/core/pcm_native.c for (k = 0; k <= SNDRV_PCM_FORMAT_LAST; ++k) { k 2173 sound/core/pcm_native.c if (! snd_mask_test(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT), k)) k 2175 sound/core/pcm_native.c bits = snd_pcm_format_physical_width(k); k 2227 sound/core/pcm_native.c int k, err; k 2229 sound/core/pcm_native.c for (k = SNDRV_PCM_HW_PARAM_FIRST_MASK; k <= SNDRV_PCM_HW_PARAM_LAST_MASK; k++) { k 2230 sound/core/pcm_native.c snd_mask_any(constrs_mask(constrs, k)); k 2233 sound/core/pcm_native.c for (k = SNDRV_PCM_HW_PARAM_FIRST_INTERVAL; k <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; k++) { k 2234 sound/core/pcm_native.c snd_interval_any(constrs_interval(constrs, k)); k 33 sound/drivers/pcm-indirect2.c int k; k 62 sound/drivers/pcm-indirect2.c k = 0; k 68 sound/drivers/pcm-indirect2.c k++; k 70 sound/drivers/pcm-indirect2.c if (((k % 8) == 0) && (k != 0)) { k 72 sound/drivers/pcm-indirect2.c k = 0; k 78 sound/drivers/pcm-indirect2.c k = 0; k 84 sound/drivers/pcm-indirect2.c k++; k 85 sound/drivers/pcm-indirect2.c if (!k) k 229 sound/isa/sb/emu8000_patch.c int k; k 232 sound/isa/sb/emu8000_patch.c for (k = 1; k <= looplen; k++) { k 233 sound/isa/sb/emu8000_patch.c s = read_word(data, offset - k, sp->v.mode_flags); k 435 sound/pci/ac97/ac97_pcm.c int i, j, k; k 491 sound/pci/ac97/ac97_pcm.c for (k = 0; k < i; k++) { k 492 sound/pci/ac97/ac97_pcm.c if (rpcm->stream == rpcms[k].stream) k 493 sound/pci/ac97/ac97_pcm.c tmp &= ~rpcms[k].r[0].rslots[j]; k 51 sound/pci/asihpi/hpidebug.c int k; k 62 sound/pci/asihpi/hpidebug.c for (k = 0; k < cols && i < len; i++, k++) k 63 sound/pci/asihpi/hpidebug.c printk(KERN_CONT "%s%04x", k == 0 ? "" : " ", pdata[i]); k 937 sound/pci/ctxfi/ctmixer.c enum CT_SUM_CTL k; k 942 sound/pci/ctxfi/ctmixer.c for (i = AMIXER_MASTER_F, k = SUM_IN_F; k 943 sound/pci/ctxfi/ctmixer.c i <= AMIXER_MASTER_S; i++, k++) { k 945 sound/pci/ctxfi/ctmixer.c sum = mixer->sums[k*CHN_NUM]; k 948 sound/pci/ctxfi/ctmixer.c sum = mixer->sums[k*CHN_NUM+1]; k 972 sound/pci/ctxfi/ctmixer.c for (i = AMIXER_PCM_F, k = SUM_IN_F; i <= AMIXER_PCM_S; i++, k++) { k 974 sound/pci/ctxfi/ctmixer.c sum = mixer->sums[k*CHN_NUM]; k 977 sound/pci/ctxfi/ctmixer.c sum = mixer->sums[k*CHN_NUM+1]; k 26 sound/pci/ctxfi/ctresource.c int i, j, k, n; k 31 sound/pci/ctxfi/ctresource.c k = i % 8; k 32 sound/pci/ctxfi/ctresource.c if (rscs[j] & ((u8)1 << k)) { k 48 sound/pci/ctxfi/ctresource.c k = i % 8; k 49 sound/pci/ctxfi/ctresource.c rscs[j] |= ((u8)1 << k); k 60 sound/pci/ctxfi/ctresource.c unsigned int i, j, k, n; k 65 sound/pci/ctxfi/ctresource.c k = i % 8; k 66 sound/pci/ctxfi/ctresource.c rscs[j] &= ~((u8)1 << k); k 1498 sound/pci/emu10k1/emufx.c int j, k, l, d; k 1500 sound/pci/emu10k1/emufx.c k = 0xb0 + (z * 8) + (j * 4); k 1505 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j)); k 1506 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j)); k 1507 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j)); k 1508 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j)); k 1509 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); k 1511 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j)); k 1513 sound/pci/emu10k1/emufx.c A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j)); k 2220 sound/pci/emu10k1/emufx.c int j, k, l, d; k 2222 sound/pci/emu10k1/emufx.c k = 0xa0 + (z * 8) + (j * 4); k 2227 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); k 2228 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); k 2229 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); k 2230 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); k 2231 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); k 2233 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); k 2235 sound/pci/emu10k1/emufx.c OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); k 38 sound/pci/emu10k1/voice.c int i, j, k, first_voice, last_voice, skip; k 56 sound/pci/emu10k1/voice.c for (k = 0; k < number; k++) { k 57 sound/pci/emu10k1/voice.c voice = &emu->voices[(i+k) % NUM_G]; k 1355 sound/pci/ice1712/aureon.c static int aureon_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo) k 707 sound/pci/ice1712/phase.c static int phase28_oversampling_info(struct snd_kcontrol *k, k 130 sound/pci/mixart/mixart_hwdep.c u32 k; k 162 sound/pci/mixart/mixart_hwdep.c for(k=0; k < connector->uid_count; k++) { k 165 sound/pci/mixart/mixart_hwdep.c if(k < MIXART_FIRST_DIG_AUDIO_ID) { k 166 sound/pci/mixart/mixart_hwdep.c pipe = &mgr->chip[k/2]->pipe_out_ana; k 168 sound/pci/mixart/mixart_hwdep.c pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_out_dig; k 170 sound/pci/mixart/mixart_hwdep.c if(k & 1) { k 171 sound/pci/mixart/mixart_hwdep.c pipe->uid_right_connector = connector->uid[k]; /* odd */ k 173 sound/pci/mixart/mixart_hwdep.c pipe->uid_left_connector = connector->uid[k]; /* even */ k 180 sound/pci/mixart/mixart_hwdep.c request.uid = connector->uid[k]; k 206 sound/pci/mixart/mixart_hwdep.c for(k=0; k < connector->uid_count; k++) { k 209 sound/pci/mixart/mixart_hwdep.c if(k < MIXART_FIRST_DIG_AUDIO_ID) { k 210 sound/pci/mixart/mixart_hwdep.c pipe = &mgr->chip[k/2]->pipe_in_ana; k 212 sound/pci/mixart/mixart_hwdep.c pipe = &mgr->chip[(k-MIXART_FIRST_DIG_AUDIO_ID)/2]->pipe_in_dig; k 214 sound/pci/mixart/mixart_hwdep.c if(k & 1) { k 215 sound/pci/mixart/mixart_hwdep.c pipe->uid_right_connector = connector->uid[k]; /* odd */ k 217 sound/pci/mixart/mixart_hwdep.c pipe->uid_left_connector = connector->uid[k]; /* even */ k 224 sound/pci/mixart/mixart_hwdep.c request.uid = connector->uid[k]; k 248 sound/pci/mixart/mixart_hwdep.c u32 k; k 293 sound/pci/mixart/mixart_hwdep.c for(k=0; k<mgr->num_cards; k++) { k 294 sound/pci/mixart/mixart_hwdep.c mgr->chip[k]->uid_in_analog_physio = phys_io.uid[k]; k 295 sound/pci/mixart/mixart_hwdep.c mgr->chip[k]->uid_out_analog_physio = phys_io.uid[phys_io.nb_uid/2 + k]; k 304 sound/pci/mixart/mixart_hwdep.c u32 k; k 319 sound/pci/mixart/mixart_hwdep.c err = snd_mixart_send_msg(mgr, &request, sizeof(k), &k); k 320 sound/pci/mixart/mixart_hwdep.c if( (err < 0) || (k != 0) ) { k 1255 sound/pci/rme9652/rme9652.c unsigned int k; k 1258 sound/pci/rme9652/rme9652.c for (k = 0; k < rme9652->ss_channels; ++k) { k 1259 sound/pci/rme9652/rme9652.c ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k)); k 1783 sound/pci/rme9652/rme9652.c unsigned int k; k 1811 sound/pci/rme9652/rme9652.c for (k = 0; k < RME9652_NCHANNELS; ++k) k 1812 sound/pci/rme9652/rme9652.c rme9652_write(rme9652, RME9652_thru_base + k * 4, 0); k 119 sound/soc/codecs/alc5623.h #define ALC5623_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) k 203 sound/soc/codecs/alc5632.h #define ALC5632_PLL1_CTRL_K_VAL(k) (((k) & 0x07) << 4) k 688 sound/soc/codecs/max98088.c struct snd_kcontrol *k, int event) k 694 sound/soc/codecs/max98088.c struct snd_kcontrol *k, int event) k 700 sound/soc/codecs/max98088.c struct snd_kcontrol *k, int event) k 706 sound/soc/codecs/max98088.c struct snd_kcontrol *k, int event) k 658 sound/soc/codecs/max98095.c struct snd_kcontrol *k, int event) k 664 sound/soc/codecs/max98095.c struct snd_kcontrol *k, int event) k 234 sound/soc/codecs/nau8540.c struct snd_kcontrol *k, int event) k 256 sound/soc/codecs/nau8540.c struct snd_kcontrol *k, int event) k 494 sound/soc/codecs/nau8824.c struct snd_kcontrol *k, int event) k 553 sound/soc/codecs/nau8824.c struct snd_kcontrol *k, int event) k 96 sound/soc/codecs/rl6231.c int k; k 140 sound/soc/codecs/rl6231.c int i, k, n_t; k 153 sound/soc/codecs/rl6231.c k = pll_preset_table[i].k; k 173 sound/soc/codecs/rl6231.c k = min_k; k 181 sound/soc/codecs/rl6231.c k = k_t; k 190 sound/soc/codecs/rl6231.c k = k_t; k 202 sound/soc/codecs/rl6231.c k = k_t; k 217 sound/soc/codecs/rl6231.c pll_code->k_code = k; k 563 sound/soc/codecs/rt5631.h #define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) k 1889 sound/soc/codecs/rt5645.c struct snd_kcontrol *k, int event) k 1910 sound/soc/codecs/rt5645.c struct snd_kcontrol *k, int event) k 1935 sound/soc/codecs/rt5645.c struct snd_kcontrol *k, int event) k 964 sound/soc/codecs/wm8350.c int k; k 1013 sound/soc/codecs/wm8350.c fll_div->k = K; k 1015 sound/soc/codecs/wm8350.c fll_div->k = 0; k 1046 sound/soc/codecs/wm8350.c freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, k 1057 sound/soc/codecs/wm8350.c snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k); k 1061 sound/soc/codecs/wm8350.c fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | k 856 sound/soc/codecs/wm8400.c u16 k; k 922 sound/soc/codecs/wm8400.c factors->k = K / 10; k 927 sound/soc/codecs/wm8400.c factors->n, factors->k, factors->fratio, factors->outdiv); k 976 sound/soc/codecs/wm8400.c snd_soc_component_write(component, WM8400_FLL_CONTROL_2, factors.k); k 268 sound/soc/codecs/wm8510.c unsigned int k; k 310 sound/soc/codecs/wm8510.c pll_div.k = K; k 333 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18); k 334 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff); k 335 sound/soc/codecs/wm8510.c snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff); k 378 sound/soc/codecs/wm8580.c u32 k:24; k 451 sound/soc/codecs/wm8580.c pll_div->k = K; k 454 sound/soc/codecs/wm8580.c pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, k 509 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); k 510 sound/soc/codecs/wm8580.c snd_soc_component_write(component, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff); k 512 sound/soc/codecs/wm8580.c (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); k 695 sound/soc/codecs/wm8753.c u32 k:24; k 735 sound/soc/codecs/wm8753.c pll_div->k = K; k 771 sound/soc/codecs/wm8753.c value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18); k 775 sound/soc/codecs/wm8753.c value = (pll_div.k & 0x03fe00) >> 9; k 779 sound/soc/codecs/wm8753.c value = pll_div.k & 0x0001ff; k 324 sound/soc/codecs/wm8804.c u32 k:22; k 396 sound/soc/codecs/wm8804.c pll_div->k = K; k 437 sound/soc/codecs/wm8804.c snd_soc_component_write(component, WM8804_PLL1, pll_div.k & 0xff); k 438 sound/soc/codecs/wm8804.c snd_soc_component_write(component, WM8804_PLL2, (pll_div.k >> 8) & 0xff); k 439 sound/soc/codecs/wm8804.c snd_soc_component_write(component, WM8804_PLL3, pll_div.k >> 16); k 678 sound/soc/codecs/wm8900.c u16 k; k 742 sound/soc/codecs/wm8900.c fll_div->k = K / 10; k 791 sound/soc/codecs/wm8900.c if (fll_div.k) { k 793 sound/soc/codecs/wm8900.c (fll_div.k >> 8) | 0x100); k 794 sound/soc/codecs/wm8900.c snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff); k 1585 sound/soc/codecs/wm8904.c u16 k; k 1678 sound/soc/codecs/wm8904.c fll_div->k = K / 10; k 1681 sound/soc/codecs/wm8904.c fll_div->n, fll_div->k, k 1785 sound/soc/codecs/wm8904.c if (fll_div.k) k 1797 sound/soc/codecs/wm8904.c snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k); k 516 sound/soc/codecs/wm8940.c unsigned int k; k 569 sound/soc/codecs/wm8940.c pll_div.k = K; k 594 sound/soc/codecs/wm8940.c if (pll_div.k) k 600 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_PLLK1, pll_div.k >> 18); k 601 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff); k 602 sound/soc/codecs/wm8940.c snd_soc_component_write(component, WM8940_PLLK3, pll_div.k & 0x1ff); k 135 sound/soc/codecs/wm8955.c int k; k 185 sound/soc/codecs/wm8955.c pll->k = K / 10; k 187 sound/soc/codecs/wm8955.c dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); k 294 sound/soc/codecs/wm8955.c pll.k >> 18); k 297 sound/soc/codecs/wm8955.c (pll.k >> 9) & WM8955_K_17_9_MASK); k 300 sound/soc/codecs/wm8955.c pll.k & WM8955_K_8_0_MASK); k 301 sound/soc/codecs/wm8955.c if (pll.k) k 631 sound/soc/codecs/wm8960.c int i, j, k; k 648 sound/soc/codecs/wm8960.c for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { k 649 sound/soc/codecs/wm8960.c diff = sysclk - bclk * bclk_divs[k] / 10; k 653 sound/soc/codecs/wm8960.c *bclk_idx = k; k 659 sound/soc/codecs/wm8960.c *bclk_idx = k; k 663 sound/soc/codecs/wm8960.c if (k != ARRAY_SIZE(bclk_divs)) k 701 sound/soc/codecs/wm8960.c int i, j, k; k 717 sound/soc/codecs/wm8960.c for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { k 721 sound/soc/codecs/wm8960.c diff = sysclk - bclk * bclk_divs[k] / 10; k 725 sound/soc/codecs/wm8960.c *bclk_idx = k; k 731 sound/soc/codecs/wm8960.c *bclk_idx = k; k 746 sound/soc/codecs/wm8960.c int i, j, k; k 779 sound/soc/codecs/wm8960.c ret = wm8960_configure_sysclk(wm8960, freq_out, &i, &j, &k); k 788 sound/soc/codecs/wm8960.c freq_out = wm8960_configure_pll(component, freq_in, &i, &j, &k); k 804 sound/soc/codecs/wm8960.c snd_soc_component_update_bits(component, WM8960_CLOCK2, 0xf, k); k 1108 sound/soc/codecs/wm8960.c u32 k:24; k 1176 sound/soc/codecs/wm8960.c pll_div->k = K; k 1179 sound/soc/codecs/wm8960.c pll_div->n, pll_div->k, pll_div->pre_div); k 1209 sound/soc/codecs/wm8960.c if (pll_div.k) { k 1212 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_PLL2, (pll_div.k >> 16) & 0xff); k 1213 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_PLL3, (pll_div.k >> 8) & 0xff); k 1214 sound/soc/codecs/wm8960.c snd_soc_component_write(component, WM8960_PLL4, pll_div.k & 0xff); k 273 sound/soc/codecs/wm8974.c unsigned int k; k 317 sound/soc/codecs/wm8974.c pll_div->k = K; k 341 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18); k 342 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff); k 343 sound/soc/codecs/wm8974.c snd_soc_component_write(component, WM8974_PLLK3, pll_div.k & 0x1ff); k 401 sound/soc/codecs/wm8978.c u32 k; k 412 sound/soc/codecs/wm8978.c unsigned int k, n_div, n_mod; k 434 sound/soc/codecs/wm8978.c k = k_part & 0xFFFFFFFF; k 436 sound/soc/codecs/wm8978.c pll_div->k = k; k 539 sound/soc/codecs/wm8978.c __func__, pll_div.n, pll_div.k, pll_div.div2); k 545 sound/soc/codecs/wm8978.c snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18); k 546 sound/soc/codecs/wm8978.c snd_soc_component_write(component, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff); k 547 sound/soc/codecs/wm8978.c snd_soc_component_write(component, WM8978_PLL_K3, pll_div.k & 0x1ff); k 746 sound/soc/codecs/wm8983.c u32 k:24; k 780 sound/soc/codecs/wm8983.c pll_div->k = K; k 812 sound/soc/codecs/wm8983.c snd_soc_component_write(component, WM8983_PLL_K_3, pll_div.k & 0x1ff); k 813 sound/soc/codecs/wm8983.c snd_soc_component_write(component, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff); k 814 sound/soc/codecs/wm8983.c snd_soc_component_write(component, WM8983_PLL_K_1, (pll_div.k >> 18)); k 843 sound/soc/codecs/wm8985.c u32 k:24; k 877 sound/soc/codecs/wm8985.c pll_div->k = K; k 905 sound/soc/codecs/wm8985.c snd_soc_component_write(component, WM8985_PLL_K_3, pll_div.k & 0x1ff); k 906 sound/soc/codecs/wm8985.c snd_soc_component_write(component, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); k 907 sound/soc/codecs/wm8985.c snd_soc_component_write(component, WM8985_PLL_K_1, (pll_div.k >> 18)); k 886 sound/soc/codecs/wm8990.c u32 k; k 927 sound/soc/codecs/wm8990.c pll_div->k = K; k 950 sound/soc/codecs/wm8990.c snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8)); k 951 sound/soc/codecs/wm8990.c snd_soc_component_write(component, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); k 878 sound/soc/codecs/wm8991.c u32 k; k 919 sound/soc/codecs/wm8991.c pll_div->k = K; k 944 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8)); k 945 sound/soc/codecs/wm8991.c snd_soc_component_write(component, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); k 362 sound/soc/codecs/wm8993.c u16 k; k 456 sound/soc/codecs/wm8993.c fll_div->k = K / 10; k 459 sound/soc/codecs/wm8993.c fll_div->n, fll_div->k, k 524 sound/soc/codecs/wm8993.c if (fll_div.k) k 533 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k); k 2045 sound/soc/codecs/wm8994.c u16 k; k 2117 sound/soc/codecs/wm8994.c fll->k = K / 10; k 2120 sound/soc/codecs/wm8994.c pr_debug("N=%x K=%x\n", fll->n, fll->k); k 2126 sound/soc/codecs/wm8994.c fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll; k 2234 sound/soc/codecs/wm8994.c WM8994_FLL1_K_MASK, fll.k); k 2284 sound/soc/codecs/wm8994.c if (fll.k) k 1718 sound/soc/codecs/wm8995.c u16 k; k 1787 sound/soc/codecs/wm8995.c fll->k = K / 10; k 1789 sound/soc/codecs/wm8995.c pr_debug("N=%x K=%x\n", fll->n, fll->k); k 1874 sound/soc/codecs/wm8995.c snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); k 442 sound/soc/codecs/wm9081.c u16 k; k 535 sound/soc/codecs/wm9081.c fll_div->k = K / 10; k 538 sound/soc/codecs/wm9081.c fll_div->n, fll_div->k, k 597 sound/soc/codecs/wm9081.c if (fll_div.k) k 606 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_FLL_CONTROL_3, fll_div.k); k 745 sound/soc/codecs/wm9713.c u32 k:24; k 807 sound/soc/codecs/wm9713.c pll_div->k = K; k 832 sound/soc/codecs/wm9713.c if (pll_div.k == 0) { k 842 sound/soc/codecs/wm9713.c reg = reg2 | (0x5 << 4) | (pll_div.k >> 20); k 846 sound/soc/codecs/wm9713.c reg = reg2 | (0x4 << 4) | ((pll_div.k >> 16) & 0xf); k 850 sound/soc/codecs/wm9713.c reg = reg2 | (0x3 << 4) | ((pll_div.k >> 12) & 0xf); k 854 sound/soc/codecs/wm9713.c reg = reg2 | (0x2 << 4) | ((pll_div.k >> 8) & 0xf); k 858 sound/soc/codecs/wm9713.c reg = reg2 | (0x1 << 4) | ((pll_div.k >> 4) & 0xf); k 861 sound/soc/codecs/wm9713.c reg = reg2 | (0x0 << 4) | (pll_div.k & 0xf); /* K [3:0] */ k 518 sound/soc/intel/atom/sst-atom-controls.c struct snd_kcontrol *k, int event) k 521 sound/soc/intel/atom/sst-atom-controls.c return sst_send_pipe_module_params(w, k); k 605 sound/soc/intel/atom/sst-atom-controls.c struct snd_kcontrol *k, int event) k 960 sound/soc/intel/atom/sst-atom-controls.c struct snd_kcontrol *k, int event) k 974 sound/soc/intel/atom/sst-atom-controls.c ret = sst_send_pipe_module_params(w, k); k 980 sound/soc/intel/atom/sst-atom-controls.c struct snd_kcontrol *k, int event) k 1012 sound/soc/intel/atom/sst-atom-controls.c ret = sst_send_pipe_module_params(w, k); k 1017 sound/soc/intel/atom/sst-atom-controls.c struct snd_kcontrol *k, int event) k 1050 sound/soc/intel/atom/sst-atom-controls.c ret = sst_send_pipe_module_params(w, k); k 31 sound/soc/intel/boards/bdw-rt5677.c struct snd_kcontrol *k, int event) k 55 sound/soc/intel/boards/bxt_da7219_max98357a.c struct snd_kcontrol *k, int event) k 222 sound/soc/intel/boards/bytcr_rt5640.c struct snd_kcontrol *k, int event) k 172 sound/soc/intel/boards/bytcr_rt5651.c struct snd_kcontrol *k, int event) k 43 sound/soc/intel/boards/cht_bsw_max98090_ti.c struct snd_kcontrol *k, int event) k 68 sound/soc/intel/boards/cht_bsw_rt5645.c struct snd_kcontrol *k, int event) k 49 sound/soc/intel/boards/cht_bsw_rt5672.c struct snd_kcontrol *k, int event) k 54 sound/soc/intel/boards/kbl_da7219_max98357a.c struct snd_kcontrol *k, int event) k 65 sound/soc/intel/boards/kbl_da7219_max98927.c struct snd_kcontrol *k, int event) k 93 sound/soc/intel/boards/kbl_rt5660.c struct snd_kcontrol *k, int event) k 70 sound/soc/intel/boards/kbl_rt5663_max98927.c struct snd_kcontrol *k, int event) k 50 sound/soc/intel/boards/skl_nau88l25_max98357a.c struct snd_kcontrol *k, int event) k 60 sound/soc/intel/boards/skl_nau88l25_ssm4567.c struct snd_kcontrol *k, int event) k 250 sound/soc/intel/common/sst-dsp.c int k = 0, s = 500; k 265 sound/soc/intel/common/sst-dsp.c k++; k 266 sound/soc/intel/common/sst-dsp.c if (k > 10) k 383 sound/soc/intel/skylake/skl-topology.c const struct snd_kcontrol_new *k; k 399 sound/soc/intel/skylake/skl-topology.c k = &w->kcontrol_news[i]; k 400 sound/soc/intel/skylake/skl-topology.c if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { k 401 sound/soc/intel/skylake/skl-topology.c sb = (void *) k->private_value; k 425 sound/soc/intel/skylake/skl-topology.c const struct snd_kcontrol_new *k; k 432 sound/soc/intel/skylake/skl-topology.c k = &w->kcontrol_news[i]; k 433 sound/soc/intel/skylake/skl-topology.c if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { k 434 sound/soc/intel/skylake/skl-topology.c sb = (struct soc_bytes_ext *)k->private_value; k 743 sound/soc/intel/skylake/skl-topology.c const struct snd_kcontrol_new *k; k 774 sound/soc/intel/skylake/skl-topology.c k = &w->kcontrol_news[i]; k 775 sound/soc/intel/skylake/skl-topology.c if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { k 776 sound/soc/intel/skylake/skl-topology.c sb = (void *) k->private_value; k 813 sound/soc/intel/skylake/skl-topology.c const struct snd_kcontrol_new *k) k 815 sound/soc/intel/skylake/skl-topology.c struct soc_bytes_ext *sb = (void *) k->private_value; k 1271 sound/soc/intel/skylake/skl-topology.c struct snd_kcontrol *k, int event) k 1300 sound/soc/intel/skylake/skl-topology.c struct snd_kcontrol *k, int event) k 200 sound/soc/pxa/corgi.c struct snd_kcontrol *k, int event) k 207 sound/soc/pxa/corgi.c struct snd_kcontrol *k, int event) k 82 sound/soc/pxa/hx4700.c struct snd_kcontrol *k, int event) k 89 sound/soc/pxa/hx4700.c struct snd_kcontrol *k, int event) k 228 sound/soc/pxa/magician.c struct snd_kcontrol *k, int event) k 235 sound/soc/pxa/magician.c struct snd_kcontrol *k, int event) k 242 sound/soc/pxa/magician.c struct snd_kcontrol *k, int event) k 174 sound/soc/pxa/poodle.c struct snd_kcontrol *k, int event) k 200 sound/soc/pxa/spitz.c struct snd_kcontrol *k, int event) k 129 sound/soc/pxa/tosa.c struct snd_kcontrol *k, int event) k 34 sound/soc/rockchip/rk3288_hdmi_analog.c struct snd_kcontrol *k, int event) k 189 sound/soc/samsung/neo1973_wm8753.c struct snd_kcontrol *k, int event) k 103 sound/soc/samsung/smartq_wm8987.c struct snd_kcontrol *k, k 360 sound/soc/soc-topology.c struct snd_kcontrol_new *k, struct snd_kcontrol **kcontrol) k 365 sound/soc/soc-topology.c comp->dev, k, comp->name_prefix, comp, kcontrol); k 581 sound/soc/soc-topology.c struct snd_kcontrol_new *k, k 589 sound/soc/soc-topology.c && k->iface & SNDRV_CTL_ELEM_IFACE_MIXER k 590 sound/soc/soc-topology.c && k->access & SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE k 591 sound/soc/soc-topology.c && k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { k 595 sound/soc/soc-topology.c sbe = (struct soc_bytes_ext *)k->private_value; k 601 sound/soc/soc-topology.c k->info = snd_soc_bytes_info_ext; k 602 sound/soc/soc-topology.c k->tlv.c = snd_soc_bytes_tlv_callback; k 626 sound/soc/soc-topology.c if (k->put == NULL && ops[i].id == le32_to_cpu(hdr->ops.put)) k 627 sound/soc/soc-topology.c k->put = ops[i].put; k 628 sound/soc/soc-topology.c if (k->get == NULL && ops[i].id == le32_to_cpu(hdr->ops.get)) k 629 sound/soc/soc-topology.c k->get = ops[i].get; k 630 sound/soc/soc-topology.c if (k->info == NULL && ops[i].id == le32_to_cpu(hdr->ops.info)) k 631 sound/soc/soc-topology.c k->info = ops[i].info; k 635 sound/soc/soc-topology.c if (k->put && k->get && k->info) k 643 sound/soc/soc-topology.c if (k->put == NULL && ops[i].id == le32_to_cpu(hdr->ops.put)) k 644 sound/soc/soc-topology.c k->put = ops[i].put; k 645 sound/soc/soc-topology.c if (k->get == NULL && ops[i].id == le32_to_cpu(hdr->ops.get)) k 646 sound/soc/soc-topology.c k->get = ops[i].get; k 647 sound/soc/soc-topology.c if (k->info == NULL && ops[i].id == le32_to_cpu(hdr->ops.info)) k 648 sound/soc/soc-topology.c k->info = ops[i].info; k 652 sound/soc/soc-topology.c if (k->put && k->get && k->info) k 684 sound/soc/soc-topology.c struct snd_kcontrol_new *k, struct snd_soc_tplg_ctl_hdr *hdr) k 687 sound/soc/soc-topology.c return tplg->ops->control_load(tplg->comp, tplg->index, k, k 135 sound/soc/sof/topology.c struct snd_kcontrol *k, int event) k 215 sound/soc/sti/sti_uniperif.c int i, j, k; k 226 sound/soc/sti/sti_uniperif.c for (i = 0, j = 0, k = 0; (i < slots_num) && (k < WORD_MAX); i++) { k 237 sound/soc/sti/sti_uniperif.c word_pos[k] = word16_pos[1] | k 242 sound/soc/sti/sti_uniperif.c k++; k 1326 sound/soc/sunxi/sun4i-codec.c struct snd_kcontrol *k, int event) k 345 sound/soc/sunxi/sun8i-codec-analog.c struct snd_kcontrol *k, int event) k 70 sound/soc/tegra/tegra_rt5677.c struct snd_kcontrol *k, int event) k 115 sound/soc/tegra/tegra_wm8903.c struct snd_kcontrol *k, int event) k 131 sound/soc/tegra/tegra_wm8903.c struct snd_kcontrol *k, int event) k 30 sound/soc/ti/ams-delta.c struct snd_kcontrol *k, int event) k 37 sound/soc/ti/ams-delta.c struct snd_kcontrol *k, int event) k 187 sound/soc/ti/n810.c struct snd_kcontrol *k, int event) k 198 sound/soc/ti/n810.c struct snd_kcontrol *k, int event) k 66 sound/soc/ti/omap3pandora.c struct snd_kcontrol *k, int event) k 92 sound/soc/ti/omap3pandora.c struct snd_kcontrol *k, int event) k 141 sound/soc/ti/rx51.c struct snd_kcontrol *k, int event) k 155 sound/usb/6fire/pcm.c int k; k 163 sound/usb/6fire/pcm.c for (k = 0; k < PCM_N_PACKETS_PER_URB; k++) { k 164 sound/usb/6fire/pcm.c packet = &rt->in_urbs[i].packets[k]; k 165 sound/usb/6fire/pcm.c packet->offset = k * rt->in_packet_size; k 219 tools/bpf/bpf_dbg.c int val = f.k; k 302 tools/bpf/bpf_dbg.c val = i + 1 + f.k; k 444 tools/bpf/bpf_dbg.c f->code, f->jt, f->jf, f->k); k 495 tools/bpf/bpf_dbg.c f[i].code, f[i].jt, f[i].jf, f[i].k); k 519 tools/bpf/bpf_dbg.c f[i].k > SKF_AD_OFF) { k 636 tools/bpf/bpf_dbg.c uint32_t K = f->k; k 1027 tools/bpf/bpf_dbg.c &tmp.code, &tmp.jt, &tmp.jf, &tmp.k) != 4) { k 1035 tools/bpf/bpf_dbg.c bpf_image[i].k = tmp.k; k 43 tools/bpf/bpf_exp.y static void bpf_set_curr_instr(uint16_t op, uint8_t jt, uint8_t jf, uint32_t k); k 480 tools/bpf/bpf_exp.y uint32_t k) k 486 tools/bpf/bpf_exp.y out[curr_instr].k = k; k 543 tools/bpf/bpf_exp.y out[i].k = (uint32_t) (off - i - 1); k 585 tools/bpf/bpf_exp.y out[i].jt, out[i].jf, out[i].k); k 595 tools/bpf/bpf_exp.y out[i].jt, out[i].jf, out[i].k); k 270 tools/hv/hv_kvp_daemon.c int j, k; k 296 tools/hv/hv_kvp_daemon.c k = j + 1; k 297 tools/hv/hv_kvp_daemon.c for (; k < num_records; k++) { k 298 tools/hv/hv_kvp_daemon.c strcpy(record[j].key, record[k].key); k 299 tools/hv/hv_kvp_daemon.c strcpy(record[j].value, record[k].value); k 174 tools/iio/iio_generic_buffer.c int k; k 176 tools/iio/iio_generic_buffer.c for (k = 0; k < num_channels; k++) k 177 tools/iio/iio_generic_buffer.c switch (channels[k].bytes) { k 180 tools/iio/iio_generic_buffer.c print1byte(*(uint8_t *)(data + channels[k].location), k 181 tools/iio/iio_generic_buffer.c &channels[k]); k 184 tools/iio/iio_generic_buffer.c print2byte(*(uint16_t *)(data + channels[k].location), k 185 tools/iio/iio_generic_buffer.c &channels[k]); k 188 tools/iio/iio_generic_buffer.c print4byte(*(uint32_t *)(data + channels[k].location), k 189 tools/iio/iio_generic_buffer.c &channels[k]); k 192 tools/iio/iio_generic_buffer.c print8byte(*(uint64_t *)(data + channels[k].location), k 193 tools/iio/iio_generic_buffer.c &channels[k]); k 73 tools/include/linux/jhash.h const u8 *k = key; k 80 tools/include/linux/jhash.h a += __get_unaligned_cpu32(k); k 81 tools/include/linux/jhash.h b += __get_unaligned_cpu32(k + 4); k 82 tools/include/linux/jhash.h c += __get_unaligned_cpu32(k + 8); k 85 tools/include/linux/jhash.h k += 12; k 90 tools/include/linux/jhash.h case 12: c += (u32)k[11]<<24; k 91 tools/include/linux/jhash.h case 11: c += (u32)k[10]<<16; k 92 tools/include/linux/jhash.h case 10: c += (u32)k[9]<<8; k 93 tools/include/linux/jhash.h case 9: c += k[8]; k 94 tools/include/linux/jhash.h case 8: b += (u32)k[7]<<24; k 95 tools/include/linux/jhash.h case 7: b += (u32)k[6]<<16; k 96 tools/include/linux/jhash.h case 6: b += (u32)k[5]<<8; k 97 tools/include/linux/jhash.h case 5: b += k[4]; k 98 tools/include/linux/jhash.h case 4: a += (u32)k[3]<<24; k 99 tools/include/linux/jhash.h case 3: a += (u32)k[2]<<16; k 100 tools/include/linux/jhash.h case 2: a += (u32)k[1]<<8; k 101 tools/include/linux/jhash.h case 1: a += k[0]; k 117 tools/include/linux/jhash.h static inline u32 jhash2(const u32 *k, u32 length, u32 initval) k 126 tools/include/linux/jhash.h a += k[0]; k 127 tools/include/linux/jhash.h b += k[1]; k 128 tools/include/linux/jhash.h c += k[2]; k 131 tools/include/linux/jhash.h k += 3; k 136 tools/include/linux/jhash.h case 3: c += k[2]; k 137 tools/include/linux/jhash.h case 2: b += k[1]; k 138 tools/include/linux/jhash.h case 1: a += k[0]; k 119 tools/include/linux/kernel.h #define current_gfp_context(k) 0 k 10 tools/lib/bitmap.c int k, w = 0, lim = bits/BITS_PER_LONG; k 12 tools/lib/bitmap.c for (k = 0; k < lim; k++) k 13 tools/lib/bitmap.c w += hweight_long(bitmap[k]); k 16 tools/lib/bitmap.c w += hweight_long(bitmap[k] & BITMAP_LAST_WORD_MASK(bits)); k 24 tools/lib/bitmap.c int k; k 27 tools/lib/bitmap.c for (k = 0; k < nr; k++) k 28 tools/lib/bitmap.c dst[k] = bitmap1[k] | bitmap2[k]; k 63 tools/lib/bitmap.c unsigned int k; k 67 tools/lib/bitmap.c for (k = 0; k < lim; k++) k 68 tools/lib/bitmap.c result |= (dst[k] = bitmap1[k] & bitmap2[k]); k 70 tools/lib/bitmap.c result |= (dst[k] = bitmap1[k] & bitmap2[k] & k 338 tools/perf/builtin-probe.c int i, k; k 358 tools/perf/builtin-probe.c for (i = k = 0; i < npevs; i++) k 359 tools/perf/builtin-probe.c k += pevs[i].ntevs; k 361 tools/perf/builtin-probe.c pr_info("Added new event%s\n", (k > 1) ? "s:" : ":"); k 365 tools/perf/builtin-probe.c for (k = 0; k < pev->ntevs; k++) { k 366 tools/perf/builtin-probe.c struct probe_trace_event *tev = &pev->tevs[k]; k 128 tools/perf/tests/hists_common.c size_t k; k 138 tools/perf/tests/hists_common.c for (k = 0; k < fake_symbols[i].nr_syms; k++) { k 140 tools/perf/tests/hists_common.c struct fake_sym *fsym = &fake_symbols[i].syms[k]; k 70 tools/perf/tests/hists_link.c size_t i = 0, k; k 80 tools/perf/tests/hists_link.c for (k = 0; k < ARRAY_SIZE(fake_common_samples); k++) { k 82 tools/perf/tests/hists_link.c sample.pid = fake_common_samples[k].pid; k 83 tools/perf/tests/hists_link.c sample.tid = fake_common_samples[k].pid; k 84 tools/perf/tests/hists_link.c sample.ip = fake_common_samples[k].ip; k 96 tools/perf/tests/hists_link.c fake_common_samples[k].thread = al.thread; k 97 tools/perf/tests/hists_link.c fake_common_samples[k].map = al.map; k 98 tools/perf/tests/hists_link.c fake_common_samples[k].sym = al.sym; k 101 tools/perf/tests/hists_link.c for (k = 0; k < ARRAY_SIZE(fake_samples[i]); k++) { k 102 tools/perf/tests/hists_link.c sample.pid = fake_samples[i][k].pid; k 103 tools/perf/tests/hists_link.c sample.tid = fake_samples[i][k].pid; k 104 tools/perf/tests/hists_link.c sample.ip = fake_samples[i][k].ip; k 115 tools/perf/tests/hists_link.c fake_samples[i][k].thread = al.thread; k 116 tools/perf/tests/hists_link.c fake_samples[i][k].map = al.map; k 117 tools/perf/tests/hists_link.c fake_samples[i][k].sym = al.sym; k 44 tools/perf/tests/kmod-path.c #define T(path, an, k, c, n) \ k 45 tools/perf/tests/kmod-path.c TEST_ASSERT_VAL("failed", !test(path, an, k, c, n)) k 820 tools/perf/util/bpf-loader.c } k; k 837 tools/perf/util/bpf-loader.c parse_events__clear_array(&op->k.array); k 871 tools/perf/util/bpf-loader.c sizeof(op->k.array.ranges[0]); k 873 tools/perf/util/bpf-loader.c op->k.array.ranges = memdup(term->array.ranges, memsz); k 874 tools/perf/util/bpf-loader.c if (!op->k.array.ranges) { k 879 tools/perf/util/bpf-loader.c op->k.array.nr_ranges = term->array.nr_ranges; k 918 tools/perf/util/bpf-loader.c size_t memsz = op->k.array.nr_ranges * k 919 tools/perf/util/bpf-loader.c sizeof(op->k.array.ranges[0]); k 921 tools/perf/util/bpf-loader.c newop->k.array.ranges = memdup(op->k.array.ranges, memsz); k 922 tools/perf/util/bpf-loader.c if (!newop->k.array.ranges) { k 1290 tools/perf/util/bpf-loader.c for (i = 0; i < op->k.array.nr_ranges; i++) { k 1291 tools/perf/util/bpf-loader.c unsigned int start = op->k.array.ranges[i].start; k 1292 tools/perf/util/bpf-loader.c size_t length = op->k.array.ranges[i].length; k 494 tools/perf/util/config.c static int perf_env_bool(const char *k, int def) k 496 tools/perf/util/config.c const char *v = getenv(k); k 497 tools/perf/util/config.c return v ? perf_config_bool(k, v) : def; k 2410 tools/perf/util/cs-etm.c int i, j, k; k 2474 tools/perf/util/cs-etm.c for (k = 0; k < CS_ETM_PRIV_MAX; k++) k 2475 tools/perf/util/cs-etm.c metadata[j][k] = ptr[i + k]; k 2487 tools/perf/util/cs-etm.c for (k = 0; k < CS_ETMV4_PRIV_MAX; k++) k 2488 tools/perf/util/cs-etm.c metadata[j][k] = ptr[i + k]; k 2719 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c size_t k; k 2724 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c k = len - INTEL_PT_PSB_LEN + 1; k 2726 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c p = memrchr(buf, n[0], k); k 2731 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c k = p - buf; k 2732 tools/perf/util/intel-pt-decoder/intel-pt-decoder.c if (!k) k 2188 tools/perf/util/machine.c int lbr_nr = lbr_stack->nr, j, k; k 2212 tools/perf/util/machine.c k = j - i - 2; k 2213 tools/perf/util/machine.c ip = lbr_stack->entries[k].from; k 2215 tools/perf/util/machine.c flags = &lbr_stack->entries[k].flags; k 2225 tools/perf/util/machine.c k = lbr_nr - j - 1; k 2226 tools/perf/util/machine.c ip = lbr_stack->entries[k].from; k 2228 tools/perf/util/machine.c flags = &lbr_stack->entries[k].flags; k 1458 tools/perf/util/symbol-elf.c #define kcore_copy__for_each_phdr(k, p) \ k 1459 tools/perf/util/symbol-elf.c list_for_each_entry((p), &(k)->phdrs, node) k 1648 tools/perf/util/symbol-elf.c struct phdr_data *p, *k = NULL; k 1659 tools/perf/util/symbol-elf.c k = p; k 1664 tools/perf/util/symbol-elf.c if (!k) k 1667 tools/perf/util/symbol-elf.c kend = k->offset + k->len; k 1673 tools/perf/util/symbol-elf.c if (p == k) k 1676 tools/perf/util/symbol-elf.c if (p->offset >= k->offset && pend <= kend) k 1677 tools/perf/util/symbol-elf.c p->remaps = k; k 1697 tools/perf/util/symbol-elf.c struct phdr_data *k = p->remaps; k 1699 tools/perf/util/symbol-elf.c if (k) k 1700 tools/perf/util/symbol-elf.c p->rel = p->offset - k->offset + k->rel; k 367 tools/power/x86/intel-speed-select/isst-core.c int i, k, ret; k 389 tools/power/x86/intel-speed-select/isst-core.c for (k = 0; k < 3; ++k) { k 396 tools/power/x86/intel-speed-select/isst-core.c (k << 16) | (i << 8) | level, &resp); k 402 tools/power/x86/intel-speed-select/isst-core.c cpu, i, level, k, resp); k 405 tools/power/x86/intel-speed-select/isst-core.c switch (k) { k 141 tools/power/x86/intel-speed-select/isst-display.c int k = 0; k 144 tools/power/x86/intel-speed-select/isst-display.c k += snprintf(&delimiters[k], k 145 tools/power/x86/intel-speed-select/isst-display.c sizeof(delimiters) - k, k 98 tools/testing/radix-tree/multiorder.c int k; k 101 tools/testing/radix-tree/multiorder.c for (k = i; index[k] < tag_index[i]; k++) k 103 tools/testing/radix-tree/multiorder.c if (j <= (index[k] | ((1 << order[k]) - 1))) k 110 tools/testing/radix-tree/multiorder.c for (k = i; index[k] < tag_index[i]; k++) k 112 tools/testing/radix-tree/multiorder.c mask = (1UL << order[k]) - 1; k 117 tools/testing/radix-tree/multiorder.c assert(item->order == order[k]); k 126 tools/testing/radix-tree/multiorder.c int mask, k; k 129 tools/testing/radix-tree/multiorder.c for (k = i; index[k] < tag_index[i]; k++) k 131 tools/testing/radix-tree/multiorder.c if (j <= (index[k] | ((1 << order[k]) - 1))) k 137 tools/testing/radix-tree/multiorder.c for (k = i; index[k] < tag_index[i]; k++) k 139 tools/testing/radix-tree/multiorder.c mask = (1 << order[k]) - 1; k 144 tools/testing/radix-tree/multiorder.c assert(item->order == order[k]); k 110 tools/testing/selftests/bpf/progs/btf_dump_test_case_syntax.c fn_ptr_arr1_t k; k 39 tools/testing/selftests/bpf/progs/test_jhash.h const unsigned char *k = key; k 44 tools/testing/selftests/bpf/progs/test_jhash.h a += *(volatile u32 *)(k); k 45 tools/testing/selftests/bpf/progs/test_jhash.h b += *(volatile u32 *)(k + 4); k 46 tools/testing/selftests/bpf/progs/test_jhash.h c += *(volatile u32 *)(k + 8); k 49 tools/testing/selftests/bpf/progs/test_jhash.h k += 12; k 52 tools/testing/selftests/bpf/progs/test_jhash.h case 12: c += (u32)k[11]<<24; k 53 tools/testing/selftests/bpf/progs/test_jhash.h case 11: c += (u32)k[10]<<16; k 54 tools/testing/selftests/bpf/progs/test_jhash.h case 10: c += (u32)k[9]<<8; k 55 tools/testing/selftests/bpf/progs/test_jhash.h case 9: c += k[8]; k 56 tools/testing/selftests/bpf/progs/test_jhash.h case 8: b += (u32)k[7]<<24; k 57 tools/testing/selftests/bpf/progs/test_jhash.h case 7: b += (u32)k[6]<<16; k 58 tools/testing/selftests/bpf/progs/test_jhash.h case 6: b += (u32)k[5]<<8; k 59 tools/testing/selftests/bpf/progs/test_jhash.h case 5: b += k[4]; k 60 tools/testing/selftests/bpf/progs/test_jhash.h case 4: a += (u32)k[3]<<24; k 61 tools/testing/selftests/bpf/progs/test_jhash.h case 3: a += (u32)k[2]<<16; k 62 tools/testing/selftests/bpf/progs/test_jhash.h case 2: a += (u32)k[1]<<8; k 63 tools/testing/selftests/bpf/progs/test_jhash.h case 1: a += k[0]; k 62 tools/testing/selftests/bpf/progs/test_l4lb.c const unsigned char *k = key; k 67 tools/testing/selftests/bpf/progs/test_l4lb.c a += *(u32 *)(k); k 68 tools/testing/selftests/bpf/progs/test_l4lb.c b += *(u32 *)(k + 4); k 69 tools/testing/selftests/bpf/progs/test_l4lb.c c += *(u32 *)(k + 8); k 72 tools/testing/selftests/bpf/progs/test_l4lb.c k += 12; k 75 tools/testing/selftests/bpf/progs/test_l4lb.c case 12: c += (u32)k[11]<<24; k 76 tools/testing/selftests/bpf/progs/test_l4lb.c case 11: c += (u32)k[10]<<16; k 77 tools/testing/selftests/bpf/progs/test_l4lb.c case 10: c += (u32)k[9]<<8; k 78 tools/testing/selftests/bpf/progs/test_l4lb.c case 9: c += k[8]; k 79 tools/testing/selftests/bpf/progs/test_l4lb.c case 8: b += (u32)k[7]<<24; k 80 tools/testing/selftests/bpf/progs/test_l4lb.c case 7: b += (u32)k[6]<<16; k 81 tools/testing/selftests/bpf/progs/test_l4lb.c case 6: b += (u32)k[5]<<8; k 82 tools/testing/selftests/bpf/progs/test_l4lb.c case 5: b += k[4]; k 83 tools/testing/selftests/bpf/progs/test_l4lb.c case 4: a += (u32)k[3]<<24; k 84 tools/testing/selftests/bpf/progs/test_l4lb.c case 3: a += (u32)k[2]<<16; k 85 tools/testing/selftests/bpf/progs/test_l4lb.c case 2: a += (u32)k[1]<<8; k 86 tools/testing/selftests/bpf/progs/test_l4lb.c case 1: a += k[0]; k 58 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c const unsigned char *k = key; k 63 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c a += *(u32 *)(k); k 64 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c b += *(u32 *)(k + 4); k 65 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c c += *(u32 *)(k + 8); k 68 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c k += 12; k 71 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 12: c += (u32)k[11]<<24; k 72 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 11: c += (u32)k[10]<<16; k 73 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 10: c += (u32)k[9]<<8; k 74 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 9: c += k[8]; k 75 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 8: b += (u32)k[7]<<24; k 76 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 7: b += (u32)k[6]<<16; k 77 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 6: b += (u32)k[5]<<8; k 78 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 5: b += k[4]; k 79 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 4: a += (u32)k[3]<<24; k 80 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 3: a += (u32)k[2]<<16; k 81 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 2: a += (u32)k[1]<<8; k 82 tools/testing/selftests/bpf/progs/test_l4lb_noinline.c case 1: a += k[0]; k 56 tools/testing/selftests/bpf/progs/test_xdp_noinline.c const unsigned char *k = key; k 61 tools/testing/selftests/bpf/progs/test_xdp_noinline.c a += *(u32 *)(k); k 62 tools/testing/selftests/bpf/progs/test_xdp_noinline.c b += *(u32 *)(k + 4); k 63 tools/testing/selftests/bpf/progs/test_xdp_noinline.c c += *(u32 *)(k + 8); k 66 tools/testing/selftests/bpf/progs/test_xdp_noinline.c k += 12; k 69 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 12: c += (u32)k[11]<<24; k 70 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 11: c += (u32)k[10]<<16; k 71 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 10: c += (u32)k[9]<<8; k 72 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 9: c += k[8]; k 73 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 8: b += (u32)k[7]<<24; k 74 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 7: b += (u32)k[6]<<16; k 75 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 6: b += (u32)k[5]<<8; k 76 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 5: b += k[4]; k 77 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 4: a += (u32)k[3]<<24; k 78 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 3: a += (u32)k[2]<<16; k 79 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 2: a += (u32)k[1]<<8; k 80 tools/testing/selftests/bpf/progs/test_xdp_noinline.c case 1: a += k[0]; k 22 tools/testing/selftests/bpf/test_hashmap.c size_t hash_fn(const void *k, void *ctx) k 24 tools/testing/selftests/bpf/test_hashmap.c return (long)k; k 66 tools/testing/selftests/bpf/test_hashmap.c const void *oldk, *k = (const void *)(long)i; k 69 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__update(map, k, v, &oldk, &oldv); k 74 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__add(map, k, v); k 76 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__set(map, k, v, &oldk, &oldv); k 83 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v, err)) k 86 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(!hashmap__find(map, k, &oldv), k 87 tools/testing/selftests/bpf/test_hashmap.c "failed to find key %ld\n", (long)k)) k 102 tools/testing/selftests/bpf/test_hashmap.c long k = (long)entry->key; k 105 tools/testing/selftests/bpf/test_hashmap.c found_msk |= 1ULL << k; k 106 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(v - k != 1024, "invalid k/v pair: %ld = %ld\n", k, v)) k 114 tools/testing/selftests/bpf/test_hashmap.c const void *oldk, *k = (const void *)(long)i; k 117 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__add(map, k, v); k 122 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__update(map, k, v, &oldk, &oldv); k 124 tools/testing/selftests/bpf/test_hashmap.c err = hashmap__set(map, k, v, &oldk, &oldv); k 127 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v, err)) k 129 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(!hashmap__find(map, k, &oldv), k 130 tools/testing/selftests/bpf/test_hashmap.c "failed to find key %ld\n", (long)k)) k 145 tools/testing/selftests/bpf/test_hashmap.c long k = (long)entry->key; k 148 tools/testing/selftests/bpf/test_hashmap.c found_msk |= 1ULL << k; k 149 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(v - k != 256, k 150 tools/testing/selftests/bpf/test_hashmap.c "invalid updated k/v pair: %ld = %ld\n", k, v)) k 167 tools/testing/selftests/bpf/test_hashmap.c const void *oldk, *k; k 170 tools/testing/selftests/bpf/test_hashmap.c k = entry->key; k 174 tools/testing/selftests/bpf/test_hashmap.c found_msk |= 1ULL << (long)k; k 176 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(!hashmap__delete(map, k, &oldk, &oldv), k 178 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v)) k 180 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(oldk != k || oldv != v, k 182 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v, (long)oldk, (long)oldv)) k 184 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(hashmap__delete(map, k, &oldk, &oldv), k 202 tools/testing/selftests/bpf/test_hashmap.c const void *oldk, *k; k 205 tools/testing/selftests/bpf/test_hashmap.c k = entry->key; k 209 tools/testing/selftests/bpf/test_hashmap.c found_msk |= 1ULL << (long)k; k 211 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(!hashmap__delete(map, k, &oldk, &oldv), k 213 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v)) k 215 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(oldk != k || oldv != v, k 217 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v, (long)oldk, (long)oldv)) k 219 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(hashmap__delete(map, k, &oldk, &oldv), k 221 tools/testing/selftests/bpf/test_hashmap.c (long)k, (long)v)) k 252 tools/testing/selftests/bpf/test_hashmap.c size_t collision_hash_fn(const void *k, void *ctx) k 337 tools/testing/selftests/bpf/test_hashmap.c void *k = (void *)0; k 352 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(hashmap__find(map, k, NULL), "unexpected find\n")) k 354 tools/testing/selftests/bpf/test_hashmap.c if (CHECK(hashmap__delete(map, k, NULL, NULL), "unexpected delete\n")) k 361 tools/testing/selftests/bpf/test_hashmap.c hashmap__for_each_key_entry(map, entry, k) { k 330 tools/testing/selftests/bpf/test_sockmap.c unsigned char k = 0; k 339 tools/testing/selftests/bpf/test_sockmap.c for (i = 0; i < iov_length * cnt; i++, k++) k 340 tools/testing/selftests/bpf/test_sockmap.c fwrite(&k, sizeof(char), 1, file); k 383 tools/testing/selftests/bpf/test_sockmap.c unsigned char k = 0; k 405 tools/testing/selftests/bpf/test_sockmap.c d[j] = k++; k 422 tools/testing/selftests/bpf/test_sockmap.c unsigned char k = 0; k 429 tools/testing/selftests/bpf/test_sockmap.c if (d[j] != k++) { k 432 tools/testing/selftests/bpf/test_sockmap.c i, j, d[j], k - 1, d[j+1], k); k 437 tools/testing/selftests/bpf/test_sockmap.c k = 0; k 140 tools/testing/selftests/bpf/test_verifier.c int i = 0, j, k = 0; k 168 tools/testing/selftests/bpf/test_verifier.c if (++k < 5) k 233 tools/testing/selftests/bpf/test_verifier.c int i = 0, k = 0; k 237 tools/testing/selftests/bpf/test_verifier.c while (k++ < MAX_JMP_SEQ) { k 243 tools/testing/selftests/bpf/test_verifier.c -8 * (k % 64 + 1)); k 259 tools/testing/selftests/bpf/test_verifier.c int i = 0, k = 0; k 262 tools/testing/selftests/bpf/test_verifier.c for (k = 0; k < FUNC_NEST; k++) { k 268 tools/testing/selftests/bpf/test_verifier.c k = 0; k 269 tools/testing/selftests/bpf/test_verifier.c while (k++ < MAX_JMP_SEQ) { k 275 tools/testing/selftests/bpf/test_verifier.c -8 * (k % (64 - 4 * FUNC_NEST) + 1)); k 87 tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c volatile int *k; k 117 tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c k = &readint; k 120 tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c k = &(readintalign[i % (DAWR_LENGTH_MAX/sizeof(int))]); k 122 tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c j = *k; k 123 tools/testing/selftests/powerpc/ptrace/perf-hwbreak.c *k = j; k 249 tools/testing/selftests/powerpc/tm/tm-trap.c uint16_t k = 1; k 289 tools/testing/selftests/powerpc/tm/tm-trap.c le = (int) *(uint8_t *)&k; k 283 tools/thermal/tmon/sysfs.c int i, j, n, k = 0; k 302 tools/thermal/tmon/sysfs.c sysfs_get_string(tz_name, "type", ptdata.tzi[k].type); k 303 tools/thermal/tmon/sysfs.c ptdata.tzi[k].instance = i; k 306 tools/thermal/tmon/sysfs.c ptdata.tzi[k].nr_cdev = 0; k 307 tools/thermal/tmon/sysfs.c ptdata.tzi[k].nr_trip_pts = 0; k 312 tools/thermal/tmon/sysfs.c &ptdata.tzi[k], k)) k 320 tools/thermal/tmon/sysfs.c &ptdata.tzi[k], i, j)) k 329 tools/thermal/tmon/sysfs.c ptdata.tzi[k].nr_cdev); k 330 tools/thermal/tmon/sysfs.c k++; k 341 tools/thermal/tmon/sysfs.c int i, n, k = 0; k 364 tools/thermal/tmon/sysfs.c sysfs_get_string(cdev_name, "type", ptdata.cdi[k].type); k 365 tools/thermal/tmon/sysfs.c ptdata.cdi[k].instance = i; k 366 tools/thermal/tmon/sysfs.c if (strstr(ptdata.cdi[k].type, ctrl_cdev)) { k 367 tools/thermal/tmon/sysfs.c ptdata.cdi[k].flag |= CDEV_FLAG_IN_CONTROL; k 375 tools/thermal/tmon/sysfs.c k++; k 240 tools/thermal/tmon/tui.c int k = 0; /* per zone trip point id that k 251 tools/thermal/tmon/tui.c k++; k 258 tools/thermal/tmon/tui.c k - 1, "*"); k 606 tools/vm/page-types.c size_t k = HASH_KEY(flags); k 616 tools/vm/page-types.c for (i = 1; i < ARRAY_SIZE(page_flags); i++, k++) { k 617 tools/vm/page-types.c if (!k || k >= ARRAY_SIZE(page_flags)) k 618 tools/vm/page-types.c k = 1; k 619 tools/vm/page-types.c if (page_flags[k] == 0) { k 620 tools/vm/page-types.c page_flags[k] = flags; k 621 tools/vm/page-types.c return k; k 623 tools/vm/page-types.c if (page_flags[k] == flags) k 624 tools/vm/page-types.c return k;