CMD_LEN          1409 drivers/atm/iphase.h 		for (i=0; i<CMD_LEN; i++) { \
CMD_LEN          1410 drivers/atm/iphase.h 			NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
CMD_LEN           966 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 valid_len = CMD_LEN(1);
CMD_LEN          1409 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 valid_len = CMD_LEN(1);
CMD_LEN          1537 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 valid_len = CMD_LEN(2);
CMD_LEN          1594 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 valid_len = CMD_LEN(1);
CMD_LEN          1602 drivers/gpu/drm/i915/gvt/cmd_parser.c 		valid_len = CMD_LEN(9);
CMD_LEN          1645 drivers/gpu/drm/i915/gvt/cmd_parser.c 	u32 valid_len = CMD_LEN(2);
CMD_LEN          2022 drivers/gpu/drm/i915/gvt/cmd_parser.c 		R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
CMD_LEN          2027 drivers/gpu/drm/i915/gvt/cmd_parser.c 		D_ALL, 0, 8, NULL, CMD_LEN(0)},
CMD_LEN          2031 drivers/gpu/drm/i915/gvt/cmd_parser.c 		NULL, CMD_LEN(0)},
CMD_LEN          2035 drivers/gpu/drm/i915/gvt/cmd_parser.c 		8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
CMD_LEN          2051 drivers/gpu/drm/i915/gvt/cmd_parser.c 		cmd_handler_srm, CMD_LEN(2)},
CMD_LEN          2061 drivers/gpu/drm/i915/gvt/cmd_parser.c 		cmd_handler_mi_report_perf_count, CMD_LEN(2)},
CMD_LEN          2065 drivers/gpu/drm/i915/gvt/cmd_parser.c 		cmd_handler_lrm, CMD_LEN(2)},
CMD_LEN          2069 drivers/gpu/drm/i915/gvt/cmd_parser.c 		cmd_handler_lrr, CMD_LEN(1)},
CMD_LEN          2073 drivers/gpu/drm/i915/gvt/cmd_parser.c 		8, NULL, CMD_LEN(2)},
CMD_LEN          2076 drivers/gpu/drm/i915/gvt/cmd_parser.c 		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
CMD_LEN          2082 drivers/gpu/drm/i915/gvt/cmd_parser.c 		ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
CMD_LEN          2093 drivers/gpu/drm/i915/gvt/cmd_parser.c 		cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},