jbt_reg_write_2   182 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
jbt_reg_write_2   213 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
jbt_reg_write_2   214 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
jbt_reg_write_2   215 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
jbt_reg_write_2   216 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
jbt_reg_write_2   218 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
jbt_reg_write_2   223 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
jbt_reg_write_2   225 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
jbt_reg_write_2   228 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
jbt_reg_write_2   230 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
jbt_reg_write_2   231 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
jbt_reg_write_2   266 drivers/gpu/drm/panel/panel-tpo-td028ttec1.c 	jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0x8002, NULL);
jbt_reg_write_2   234 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
jbt_reg_write_2   265 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
jbt_reg_write_2   266 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
jbt_reg_write_2   267 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
jbt_reg_write_2   268 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
jbt_reg_write_2   270 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
jbt_reg_write_2   275 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
jbt_reg_write_2   277 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
jbt_reg_write_2   280 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
jbt_reg_write_2   282 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
jbt_reg_write_2   283 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
jbt_reg_write_2   306 drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c 	jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);