ixDIDT_TD_EDC_CTRL 559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 560 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 561 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 562 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, ixDIDT_TD_EDC_CTRL 563 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, ixDIDT_TD_EDC_CTRL 564 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, ixDIDT_TD_EDC_CTRL 565 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 566 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 567 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 568 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, ixDIDT_TD_EDC_CTRL 569 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, ixDIDT_TD_EDC_CTRL 905 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); ixDIDT_TD_EDC_CTRL 908 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);