ivch_read 278 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR00, &temp)) ivch_read 293 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR20, &priv->width); ivch_read 294 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR21, &priv->height); ivch_read 300 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, backup_addresses[i], priv->reg_backup + i); ivch_read 351 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR01, &vr01)) ivch_read 370 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR30, &vr30)) ivch_read 388 drivers/gpu/drm/i915/display/dvo_ivch.c if (!ivch_read(dvo, VR01, &vr01)) ivch_read 444 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR00, &val); ivch_read 446 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR01, &val); ivch_read 448 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR10, &val); ivch_read 450 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR30, &val); ivch_read 452 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR40, &val); ivch_read 456 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR80, &val); ivch_read 458 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR81, &val); ivch_read 460 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR82, &val); ivch_read 462 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR83, &val); ivch_read 464 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR84, &val); ivch_read 466 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR85, &val); ivch_read 468 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR86, &val); ivch_read 470 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR87, &val); ivch_read 472 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR88, &val); ivch_read 476 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8E, &val); ivch_read 480 drivers/gpu/drm/i915/display/dvo_ivch.c ivch_read(dvo, VR8F, &val);