ipu_plane 36 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_plane *plane[2]; ipu_plane 189 drivers/gpu/drm/imx/ipuv3-crtc.c struct ipu_plane *plane = ipu_crtc->plane[i]; ipu_plane 32 drivers/gpu/drm/imx/ipuv3-plane.c static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p) ipu_plane 34 drivers/gpu/drm/imx/ipuv3-plane.c return container_of(p, struct ipu_plane, base); ipu_plane 86 drivers/gpu/drm/imx/ipuv3-plane.c int ipu_plane_irq(struct ipu_plane *ipu_plane) ipu_plane 88 drivers/gpu/drm/imx/ipuv3-plane.c return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch, ipu_plane 145 drivers/gpu/drm/imx/ipuv3-plane.c void ipu_plane_put_resources(struct ipu_plane *ipu_plane) ipu_plane 147 drivers/gpu/drm/imx/ipuv3-plane.c if (!IS_ERR_OR_NULL(ipu_plane->dp)) ipu_plane 148 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_put(ipu_plane->dp); ipu_plane 149 drivers/gpu/drm/imx/ipuv3-plane.c if (!IS_ERR_OR_NULL(ipu_plane->dmfc)) ipu_plane 150 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dmfc_put(ipu_plane->dmfc); ipu_plane 151 drivers/gpu/drm/imx/ipuv3-plane.c if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch)) ipu_plane 152 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_put(ipu_plane->ipu_ch); ipu_plane 153 drivers/gpu/drm/imx/ipuv3-plane.c if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch)) ipu_plane 154 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_put(ipu_plane->alpha_ch); ipu_plane 157 drivers/gpu/drm/imx/ipuv3-plane.c int ipu_plane_get_resources(struct ipu_plane *ipu_plane) ipu_plane 162 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma); ipu_plane 163 drivers/gpu/drm/imx/ipuv3-plane.c if (IS_ERR(ipu_plane->ipu_ch)) { ipu_plane 164 drivers/gpu/drm/imx/ipuv3-plane.c ret = PTR_ERR(ipu_plane->ipu_ch); ipu_plane 169 drivers/gpu/drm/imx/ipuv3-plane.c alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma); ipu_plane 171 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch); ipu_plane 172 drivers/gpu/drm/imx/ipuv3-plane.c if (IS_ERR(ipu_plane->alpha_ch)) { ipu_plane 173 drivers/gpu/drm/imx/ipuv3-plane.c ret = PTR_ERR(ipu_plane->alpha_ch); ipu_plane 180 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma); ipu_plane 181 drivers/gpu/drm/imx/ipuv3-plane.c if (IS_ERR(ipu_plane->dmfc)) { ipu_plane 182 drivers/gpu/drm/imx/ipuv3-plane.c ret = PTR_ERR(ipu_plane->dmfc); ipu_plane 187 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp_flow >= 0) { ipu_plane 188 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow); ipu_plane 189 drivers/gpu/drm/imx/ipuv3-plane.c if (IS_ERR(ipu_plane->dp)) { ipu_plane 190 drivers/gpu/drm/imx/ipuv3-plane.c ret = PTR_ERR(ipu_plane->dp); ipu_plane 198 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane_put_resources(ipu_plane); ipu_plane 203 drivers/gpu/drm/imx/ipuv3-plane.c static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane) ipu_plane 205 drivers/gpu/drm/imx/ipuv3-plane.c switch (ipu_plane->base.state->fb->format->format) { ipu_plane 218 drivers/gpu/drm/imx/ipuv3-plane.c static void ipu_plane_enable(struct ipu_plane *ipu_plane) ipu_plane 220 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp) ipu_plane 221 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_enable(ipu_plane->ipu); ipu_plane 222 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dmfc_enable_channel(ipu_plane->dmfc); ipu_plane 223 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_enable_channel(ipu_plane->ipu_ch); ipu_plane 224 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane_separate_alpha(ipu_plane)) ipu_plane 225 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_enable_channel(ipu_plane->alpha_ch); ipu_plane 226 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp) ipu_plane 227 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_enable_channel(ipu_plane->dp); ipu_plane 230 drivers/gpu/drm/imx/ipuv3-plane.c void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel) ipu_plane 236 drivers/gpu/drm/imx/ipuv3-plane.c ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50); ipu_plane 239 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->base.base.id); ipu_plane 242 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp && disable_dp_channel) ipu_plane 243 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_disable_channel(ipu_plane->dp, false); ipu_plane 244 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_disable_channel(ipu_plane->ipu_ch); ipu_plane 245 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->alpha_ch) ipu_plane 246 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_disable_channel(ipu_plane->alpha_ch); ipu_plane 247 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dmfc_disable_channel(ipu_plane->dmfc); ipu_plane 248 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp) ipu_plane 249 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_disable(ipu_plane->ipu); ipu_plane 250 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_prg_present(ipu_plane->ipu)) ipu_plane 251 drivers/gpu/drm/imx/ipuv3-plane.c ipu_prg_channel_disable(ipu_plane->ipu_ch); ipu_plane 256 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane = to_ipu_plane(plane); ipu_plane 258 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->disabling) { ipu_plane 259 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->disabling = false; ipu_plane 260 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane_disable(ipu_plane, false); ipu_plane 267 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane = to_ipu_plane(plane); ipu_plane 272 drivers/gpu/drm/imx/ipuv3-plane.c kfree(ipu_plane); ipu_plane 502 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane = to_ipu_plane(plane); ipu_plane 504 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp) ipu_plane 505 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_disable_channel(ipu_plane->dp, true); ipu_plane 506 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->disabling = true; ipu_plane 547 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane = to_ipu_plane(plane); ipu_plane 562 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG) ipu_plane 563 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1); ipu_plane 565 drivers/gpu/drm/imx/ipuv3-plane.c switch (ipu_plane->dp_flow) { ipu_plane 568 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_set_global_alpha(ipu_plane->dp, ipu_plane 572 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true); ipu_plane 577 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_set_global_alpha(ipu_plane->dp, ipu_plane 591 drivers/gpu/drm/imx/ipuv3-plane.c axi_id = ipu_chan_assign_axi_id(ipu_plane->dma); ipu_plane 592 drivers/gpu/drm/imx/ipuv3-plane.c ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, ipu_plane 603 drivers/gpu/drm/imx/ipuv3-plane.c active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); ipu_plane 604 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); ipu_plane 605 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active); ipu_plane 606 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_plane_separate_alpha(ipu_plane)) { ipu_plane 607 drivers/gpu/drm/imx/ipuv3-plane.c active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch); ipu_plane 608 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active, ipu_plane 610 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active); ipu_plane 616 drivers/gpu/drm/imx/ipuv3-plane.c switch (ipu_plane->dp_flow) { ipu_plane 618 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_setup_channel(ipu_plane->dp, ics, IPUV3_COLORSPACE_RGB); ipu_plane 621 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dp_setup_channel(ipu_plane->dp, ics, ipu_plane 626 drivers/gpu/drm/imx/ipuv3-plane.c ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst)); ipu_plane 634 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_zero(ipu_plane->ipu_ch); ipu_plane 635 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height); ipu_plane 636 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format); ipu_plane 637 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize); ipu_plane 638 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_high_priority(ipu_plane->ipu_ch); ipu_plane 639 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true); ipu_plane 640 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1); ipu_plane 641 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]); ipu_plane 642 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id); ipu_plane 658 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, ipu_plane 661 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, ipu_plane 669 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch, ipu_plane 672 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, ipu_plane 685 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d", ipu_plane 688 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16); ipu_plane 690 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_zero(ipu_plane->alpha_ch); ipu_plane 691 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_resolution(ipu_plane->alpha_ch, ipu_plane 694 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8); ipu_plane 695 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_high_priority(ipu_plane->alpha_ch); ipu_plane 696 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1); ipu_plane 697 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]); ipu_plane 698 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16); ipu_plane 699 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba); ipu_plane 700 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba); ipu_plane 703 drivers/gpu/drm/imx/ipuv3-plane.c dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d", ipu_plane 707 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba); ipu_plane 708 drivers/gpu/drm/imx/ipuv3-plane.c ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba); ipu_plane 709 drivers/gpu/drm/imx/ipuv3-plane.c ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts); ipu_plane 710 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane_enable(ipu_plane); ipu_plane 722 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane = to_ipu_plane(plane); ipu_plane 731 drivers/gpu/drm/imx/ipuv3-plane.c return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch); ipu_plane 749 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane; ipu_plane 771 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane = to_ipu_plane(plane); ipu_plane 782 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_prg_present(ipu_plane->ipu) || !available_pres) ipu_plane 785 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_prg_format_supported(ipu_plane->ipu, ipu_plane 796 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane = to_ipu_plane(plane); ipu_plane 810 drivers/gpu/drm/imx/ipuv3-plane.c if (ipu_prg_present(ipu_plane->ipu) && available_pres && ipu_plane 811 drivers/gpu/drm/imx/ipuv3-plane.c ipu_prg_format_supported(ipu_plane->ipu, ipu_plane 825 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, ipu_plane 829 drivers/gpu/drm/imx/ipuv3-plane.c struct ipu_plane *ipu_plane; ipu_plane 837 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL); ipu_plane 838 drivers/gpu/drm/imx/ipuv3-plane.c if (!ipu_plane) { ipu_plane 843 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->ipu = ipu; ipu_plane 844 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dma = dma; ipu_plane 845 drivers/gpu/drm/imx/ipuv3-plane.c ipu_plane->dp_flow = dp; ipu_plane 850 drivers/gpu/drm/imx/ipuv3-plane.c ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs, ipu_plane 856 drivers/gpu/drm/imx/ipuv3-plane.c kfree(ipu_plane); ipu_plane 860 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs); ipu_plane 863 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0, 1); ipu_plane 865 drivers/gpu/drm/imx/ipuv3-plane.c drm_plane_create_zpos_immutable_property(&ipu_plane->base, 0); ipu_plane 867 drivers/gpu/drm/imx/ipuv3-plane.c return ipu_plane; ipu_plane 32 drivers/gpu/drm/imx/ipuv3-plane.h struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu, ipu_plane 37 drivers/gpu/drm/imx/ipuv3-plane.h int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc, ipu_plane 44 drivers/gpu/drm/imx/ipuv3-plane.h int ipu_plane_get_resources(struct ipu_plane *plane); ipu_plane 45 drivers/gpu/drm/imx/ipuv3-plane.h void ipu_plane_put_resources(struct ipu_plane *plane); ipu_plane 47 drivers/gpu/drm/imx/ipuv3-plane.h int ipu_plane_irq(struct ipu_plane *plane); ipu_plane 49 drivers/gpu/drm/imx/ipuv3-plane.h void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);